core_cm3.h (68209B)
1 /**************************************************************************//** 2 * @file core_cm3.h 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File 4 * @version V2.10 5 * @date 19. July 2011 6 * 7 * @note 8 * Copyright (C) 2009-2011 ARM Limited. All rights reserved. 9 * 10 * @par 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M 12 * processor based microcontrollers. This file can be freely distributed 13 * within development tools that are supporting such ARM based processors. 14 * 15 * @par 16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED 17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. 19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR 20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. 21 * 22 ******************************************************************************/ 23 #if defined ( __ICCARM__ ) 24 #pragma system_include /* treat file as system include file for MISRA check */ 25 #endif 26 27 #ifdef __cplusplus 28 extern "C" { 29 #endif 30 31 #ifndef __CORE_CM3_H_GENERIC 32 #define __CORE_CM3_H_GENERIC 33 34 35 /** \ingroup CMSIS_Core 36 \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions 37 CMSIS violates following MISRA-C2004 Rules: 38 39 - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.<br> 40 Function definitions in header files are used to allow 'inlining'. 41 42 - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 43 Unions are used for effective representation of core registers. 44 45 - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.<br> 46 Function-like macros are used to allow more efficient code. 47 48 */ 49 50 51 /******************************************************************************* 52 * CMSIS definitions 53 ******************************************************************************/ 54 /** \ingroup CMSIS_Core 55 \defgroup CMSIS_core_definitions CMSIS Core Definitions 56 This file defines all structures and symbols for CMSIS core: 57 - CMSIS version number 58 - Cortex-M core 59 - Cortex-M core Revision Number 60 @{ 61 */ 62 63 /* CMSIS CM3 definitions */ 64 #define __CM3_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */ 65 #define __CM3_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */ 66 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ 67 68 #define __CORTEX_M (0x03) /*!< Cortex core */ 69 70 71 #if defined ( __CC_ARM ) 72 #define __ASM __asm /*!< asm keyword for ARM Compiler */ 73 #define __INLINE __inline /*!< inline keyword for ARM Compiler */ 74 75 #elif defined ( __ICCARM__ ) 76 #define __ASM __asm /*!< asm keyword for IAR Compiler */ 77 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ 78 79 #elif defined ( __GNUC__ ) 80 #define __ASM __asm /*!< asm keyword for GNU Compiler */ 81 #define __INLINE inline /*!< inline keyword for GNU Compiler */ 82 83 #elif defined ( __TASKING__ ) 84 #define __ASM __asm /*!< asm keyword for TASKING Compiler */ 85 #define __INLINE inline /*!< inline keyword for TASKING Compiler */ 86 87 #endif 88 89 /*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */ 90 #define __FPU_USED 0 91 92 #if defined ( __CC_ARM ) 93 #if defined __TARGET_FPU_VFP 94 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 95 #endif 96 #elif defined ( __ICCARM__ ) 97 #if defined __ARMVFP__ 98 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 99 #endif 100 101 #elif defined ( __GNUC__ ) 102 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 103 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 104 #endif 105 106 #elif defined ( __TASKING__ ) 107 /* add preprocessor checks */ 108 #endif 109 110 #include <stdint.h> /*!< standard types definitions */ 111 #include "core_cmInstr.h" /*!< Core Instruction Access */ 112 #include "core_cmFunc.h" /*!< Core Function Access */ 113 114 #endif /* __CORE_CM3_H_GENERIC */ 115 116 #ifndef __CMSIS_GENERIC 117 118 #ifndef __CORE_CM3_H_DEPENDANT 119 #define __CORE_CM3_H_DEPENDANT 120 121 /* check device defines and use defaults */ 122 #if defined __CHECK_DEVICE_DEFINES 123 #ifndef __CM3_REV 124 #define __CM3_REV 0x0200 125 #warning "__CM3_REV not defined in device header file; using default!" 126 #endif 127 128 #ifndef __MPU_PRESENT 129 #define __MPU_PRESENT 0 130 #warning "__MPU_PRESENT not defined in device header file; using default!" 131 #endif 132 133 #ifndef __NVIC_PRIO_BITS 134 #define __NVIC_PRIO_BITS 4 135 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 136 #endif 137 138 #ifndef __Vendor_SysTickConfig 139 #define __Vendor_SysTickConfig 0 140 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 141 #endif 142 #endif 143 144 /* IO definitions (access restrictions to peripheral registers) */ 145 #ifdef __cplusplus 146 #define __I volatile /*!< defines 'read only' permissions */ 147 #else 148 #define __I volatile const /*!< defines 'read only' permissions */ 149 #endif 150 #define __O volatile /*!< defines 'write only' permissions */ 151 #define __IO volatile /*!< defines 'read / write' permissions */ 152 153 /*@} end of group CMSIS_core_definitions */ 154 155 156 157 /******************************************************************************* 158 * Register Abstraction 159 ******************************************************************************/ 160 /** \ingroup CMSIS_Core 161 \defgroup CMSIS_core_register CMSIS Core Register 162 Core Register contain: 163 - Core Register 164 - Core NVIC Register 165 - Core SCB Register 166 - Core SysTick Register 167 - Core Debug Register 168 - Core MPU Register 169 */ 170 171 /** \ingroup CMSIS_core_register 172 \defgroup CMSIS_CORE CMSIS Core 173 Type definitions for the Cortex-M Core Registers 174 @{ 175 */ 176 177 /** \brief Union type to access the Application Program Status Register (APSR). 178 */ 179 typedef union 180 { 181 struct 182 { 183 #if (__CORTEX_M != 0x04) 184 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ 185 #else 186 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ 187 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 188 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ 189 #endif 190 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 191 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 192 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 193 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 194 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 195 } b; /*!< Structure used for bit access */ 196 uint32_t w; /*!< Type used for word access */ 197 } APSR_Type; 198 199 200 /** \brief Union type to access the Interrupt Program Status Register (IPSR). 201 */ 202 typedef union 203 { 204 struct 205 { 206 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 207 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 208 } b; /*!< Structure used for bit access */ 209 uint32_t w; /*!< Type used for word access */ 210 } IPSR_Type; 211 212 213 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 214 */ 215 typedef union 216 { 217 struct 218 { 219 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 220 #if (__CORTEX_M != 0x04) 221 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ 222 #else 223 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ 224 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 225 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ 226 #endif 227 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ 228 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ 229 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 230 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 231 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 232 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 233 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 234 } b; /*!< Structure used for bit access */ 235 uint32_t w; /*!< Type used for word access */ 236 } xPSR_Type; 237 238 239 /** \brief Union type to access the Control Registers (CONTROL). 240 */ 241 typedef union 242 { 243 struct 244 { 245 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 246 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ 247 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ 248 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ 249 } b; /*!< Structure used for bit access */ 250 uint32_t w; /*!< Type used for word access */ 251 } CONTROL_Type; 252 253 /*@} end of group CMSIS_CORE */ 254 255 256 /** \ingroup CMSIS_core_register 257 \defgroup CMSIS_NVIC CMSIS NVIC 258 Type definitions for the Cortex-M NVIC Registers 259 @{ 260 */ 261 262 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 263 */ 264 typedef struct 265 { 266 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 267 uint32_t RESERVED0[24]; 268 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 269 uint32_t RSERVED1[24]; 270 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 271 uint32_t RESERVED2[24]; 272 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 273 uint32_t RESERVED3[24]; 274 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ 275 uint32_t RESERVED4[56]; 276 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ 277 uint32_t RESERVED5[644]; 278 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ 279 } NVIC_Type; 280 281 /* Software Triggered Interrupt Register Definitions */ 282 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ 283 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ 284 285 /*@} end of group CMSIS_NVIC */ 286 287 288 /** \ingroup CMSIS_core_register 289 \defgroup CMSIS_SCB CMSIS SCB 290 Type definitions for the Cortex-M System Control Block Registers 291 @{ 292 */ 293 294 /** \brief Structure type to access the System Control Block (SCB). 295 */ 296 typedef struct 297 { 298 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 299 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 300 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 301 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 302 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 303 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 304 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ 305 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 306 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ 307 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ 308 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ 309 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ 310 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ 311 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ 312 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ 313 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ 314 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ 315 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ 316 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ 317 uint32_t RESERVED0[5]; 318 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ 319 } SCB_Type; 320 321 /* SCB CPUID Register Definitions */ 322 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ 323 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 324 325 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ 326 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 327 328 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ 329 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 330 331 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ 332 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 333 334 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ 335 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ 336 337 /* SCB Interrupt Control State Register Definitions */ 338 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ 339 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ 340 341 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ 342 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 343 344 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ 345 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 346 347 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ 348 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 349 350 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ 351 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 352 353 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ 354 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 355 356 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ 357 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 358 359 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ 360 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 361 362 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ 363 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ 364 365 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ 366 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ 367 368 /* SCB Vector Table Offset Register Definitions */ 369 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ 370 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 371 372 /* SCB Application Interrupt and Reset Control Register Definitions */ 373 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ 374 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 375 376 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ 377 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 378 379 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ 380 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 381 382 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ 383 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ 384 385 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ 386 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 387 388 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ 389 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 390 391 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ 392 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ 393 394 /* SCB System Control Register Definitions */ 395 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ 396 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 397 398 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ 399 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 400 401 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ 402 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 403 404 /* SCB Configuration Control Register Definitions */ 405 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ 406 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ 407 408 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ 409 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ 410 411 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ 412 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ 413 414 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ 415 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 416 417 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ 418 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ 419 420 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ 421 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ 422 423 /* SCB System Handler Control and State Register Definitions */ 424 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ 425 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ 426 427 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ 428 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ 429 430 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ 431 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ 432 433 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ 434 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 435 436 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ 437 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ 438 439 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ 440 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ 441 442 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ 443 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ 444 445 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ 446 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ 447 448 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ 449 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ 450 451 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ 452 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ 453 454 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ 455 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ 456 457 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ 458 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ 459 460 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ 461 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ 462 463 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ 464 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ 465 466 /* SCB Configurable Fault Status Registers Definitions */ 467 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ 468 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ 469 470 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ 471 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ 472 473 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ 474 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ 475 476 /* SCB Hard Fault Status Registers Definitions */ 477 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ 478 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ 479 480 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ 481 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ 482 483 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ 484 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ 485 486 /* SCB Debug Fault Status Register Definitions */ 487 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ 488 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ 489 490 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ 491 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ 492 493 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ 494 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ 495 496 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ 497 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ 498 499 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ 500 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ 501 502 /*@} end of group CMSIS_SCB */ 503 504 505 /** \ingroup CMSIS_core_register 506 \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB 507 Type definitions for the Cortex-M System Control and ID Register not in the SCB 508 @{ 509 */ 510 511 /** \brief Structure type to access the System Control and ID Register not in the SCB. 512 */ 513 typedef struct 514 { 515 uint32_t RESERVED0[1]; 516 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ 517 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) 518 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ 519 #else 520 uint32_t RESERVED1[1]; 521 #endif 522 } SCnSCB_Type; 523 524 /* Interrupt Controller Type Register Definitions */ 525 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ 526 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ 527 528 /* Auxiliary Control Register Definitions */ 529 530 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ 531 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ 532 533 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ 534 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ 535 536 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ 537 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ 538 539 /*@} end of group CMSIS_SCnotSCB */ 540 541 542 /** \ingroup CMSIS_core_register 543 \defgroup CMSIS_SysTick CMSIS SysTick 544 Type definitions for the Cortex-M System Timer Registers 545 @{ 546 */ 547 548 /** \brief Structure type to access the System Timer (SysTick). 549 */ 550 typedef struct 551 { 552 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 553 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 554 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 555 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 556 } SysTick_Type; 557 558 /* SysTick Control / Status Register Definitions */ 559 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ 560 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 561 562 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ 563 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 564 565 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ 566 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 567 568 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ 569 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ 570 571 /* SysTick Reload Register Definitions */ 572 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ 573 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ 574 575 /* SysTick Current Register Definitions */ 576 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ 577 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ 578 579 /* SysTick Calibration Register Definitions */ 580 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ 581 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 582 583 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ 584 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 585 586 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ 587 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ 588 589 /*@} end of group CMSIS_SysTick */ 590 591 592 /** \ingroup CMSIS_core_register 593 \defgroup CMSIS_ITM CMSIS ITM 594 Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM) 595 @{ 596 */ 597 598 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). 599 */ 600 typedef struct 601 { 602 __O union 603 { 604 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ 605 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ 606 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ 607 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ 608 uint32_t RESERVED0[864]; 609 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ 610 uint32_t RESERVED1[15]; 611 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ 612 uint32_t RESERVED2[15]; 613 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ 614 } ITM_Type; 615 616 /* ITM Trace Privilege Register Definitions */ 617 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ 618 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ 619 620 /* ITM Trace Control Register Definitions */ 621 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ 622 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ 623 624 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ 625 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ 626 627 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ 628 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ 629 630 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ 631 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ 632 633 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ 634 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ 635 636 #define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */ 637 #define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */ 638 639 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ 640 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ 641 642 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ 643 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ 644 645 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ 646 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ 647 648 /*@}*/ /* end of group CMSIS_ITM */ 649 650 651 #if (__MPU_PRESENT == 1) 652 /** \ingroup CMSIS_core_register 653 \defgroup CMSIS_MPU CMSIS MPU 654 Type definitions for the Cortex-M Memory Protection Unit (MPU) 655 @{ 656 */ 657 658 /** \brief Structure type to access the Memory Protection Unit (MPU). 659 */ 660 typedef struct 661 { 662 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 663 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 664 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ 665 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 666 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ 667 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ 668 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ 669 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ 670 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ 671 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ 672 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ 673 } MPU_Type; 674 675 /* MPU Type Register */ 676 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ 677 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 678 679 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ 680 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 681 682 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ 683 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ 684 685 /* MPU Control Register */ 686 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ 687 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 688 689 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ 690 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 691 692 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ 693 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ 694 695 /* MPU Region Number Register */ 696 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ 697 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ 698 699 /* MPU Region Base Address Register */ 700 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ 701 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ 702 703 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ 704 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ 705 706 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ 707 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ 708 709 /* MPU Region Attribute and Size Register */ 710 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ 711 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ 712 713 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ 714 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ 715 716 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ 717 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ 718 719 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ 720 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ 721 722 /*@} end of group CMSIS_MPU */ 723 #endif 724 725 726 /** \ingroup CMSIS_core_register 727 \defgroup CMSIS_CoreDebug CMSIS Core Debug 728 Type definitions for the Cortex-M Core Debug Registers 729 @{ 730 */ 731 732 /** \brief Structure type to access the Core Debug Register (CoreDebug). 733 */ 734 typedef struct 735 { 736 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ 737 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ 738 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ 739 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ 740 } CoreDebug_Type; 741 742 /* Debug Halting Control and Status Register */ 743 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ 744 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ 745 746 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ 747 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ 748 749 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ 750 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ 751 752 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ 753 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ 754 755 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ 756 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ 757 758 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ 759 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ 760 761 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ 762 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ 763 764 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ 765 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ 766 767 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ 768 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ 769 770 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ 771 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ 772 773 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ 774 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ 775 776 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ 777 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ 778 779 /* Debug Core Register Selector Register */ 780 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ 781 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ 782 783 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ 784 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ 785 786 /* Debug Exception and Monitor Control Register */ 787 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ 788 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ 789 790 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ 791 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ 792 793 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ 794 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ 795 796 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ 797 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ 798 799 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ 800 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ 801 802 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ 803 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ 804 805 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ 806 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ 807 808 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ 809 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ 810 811 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ 812 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ 813 814 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ 815 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ 816 817 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ 818 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ 819 820 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ 821 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ 822 823 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ 824 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ 825 826 /*@} end of group CMSIS_CoreDebug */ 827 828 829 /** \ingroup CMSIS_core_register 830 @{ 831 */ 832 833 /* Memory mapping of Cortex-M3 Hardware */ 834 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 835 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ 836 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ 837 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 838 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 839 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 840 841 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ 842 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 843 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 844 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 845 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ 846 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ 847 848 #if (__MPU_PRESENT == 1) 849 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 850 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 851 #endif 852 853 /*@} */ 854 855 856 857 /******************************************************************************* 858 * Hardware Abstraction Layer 859 ******************************************************************************/ 860 /** \ingroup CMSIS_Core 861 \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface 862 Core Function Interface contains: 863 - Core NVIC Functions 864 - Core SysTick Functions 865 - Core Debug Functions 866 - Core Register Access Functions 867 */ 868 869 870 871 /* ########################## NVIC functions #################################### */ 872 /** \ingroup CMSIS_Core_FunctionInterface 873 \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions 874 @{ 875 */ 876 877 /** \brief Set Priority Grouping 878 879 This function sets the priority grouping field using the required unlock sequence. 880 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. 881 Only values from 0..7 are used. 882 In case of a conflict between priority grouping and available 883 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. 884 885 \param [in] PriorityGroup Priority grouping field 886 */ 887 static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) 888 { 889 uint32_t reg_value; 890 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ 891 892 reg_value = SCB->AIRCR; /* read old register configuration */ 893 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ 894 reg_value = (reg_value | 895 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | 896 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ 897 SCB->AIRCR = reg_value; 898 } 899 900 901 /** \brief Get Priority Grouping 902 903 This function gets the priority grouping from NVIC Interrupt Controller. 904 Priority grouping is SCB->AIRCR [10:8] PRIGROUP field. 905 906 \return Priority grouping field 907 */ 908 static __INLINE uint32_t NVIC_GetPriorityGrouping(void) 909 { 910 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ 911 } 912 913 914 /** \brief Enable External Interrupt 915 916 This function enables a device specific interrupt in the NVIC interrupt controller. 917 The interrupt number cannot be a negative value. 918 919 \param [in] IRQn Number of the external interrupt to enable 920 */ 921 static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) 922 { 923 NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ 924 } 925 926 927 /** \brief Disable External Interrupt 928 929 This function disables a device specific interrupt in the NVIC interrupt controller. 930 The interrupt number cannot be a negative value. 931 932 \param [in] IRQn Number of the external interrupt to disable 933 */ 934 static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) 935 { 936 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ 937 } 938 939 940 /** \brief Get Pending Interrupt 941 942 This function reads the pending register in the NVIC and returns the pending bit 943 for the specified interrupt. 944 945 \param [in] IRQn Number of the interrupt for get pending 946 \return 0 Interrupt status is not pending 947 \return 1 Interrupt status is pending 948 */ 949 static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) 950 { 951 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ 952 } 953 954 955 /** \brief Set Pending Interrupt 956 957 This function sets the pending bit for the specified interrupt. 958 The interrupt number cannot be a negative value. 959 960 \param [in] IRQn Number of the interrupt for set pending 961 */ 962 static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) 963 { 964 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ 965 } 966 967 968 /** \brief Clear Pending Interrupt 969 970 This function clears the pending bit for the specified interrupt. 971 The interrupt number cannot be a negative value. 972 973 \param [in] IRQn Number of the interrupt for clear pending 974 */ 975 static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) 976 { 977 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ 978 } 979 980 981 /** \brief Get Active Interrupt 982 983 This function reads the active register in NVIC and returns the active bit. 984 \param [in] IRQn Number of the interrupt for get active 985 \return 0 Interrupt status is not active 986 \return 1 Interrupt status is active 987 */ 988 static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) 989 { 990 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ 991 } 992 993 994 /** \brief Set Interrupt Priority 995 996 This function sets the priority for the specified interrupt. The interrupt 997 number can be positive to specify an external (device specific) 998 interrupt, or negative to specify an internal (core) interrupt. 999 1000 Note: The priority cannot be set for every core interrupt. 1001 1002 \param [in] IRQn Number of the interrupt for set priority 1003 \param [in] priority Priority to set 1004 */ 1005 static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 1006 { 1007 if(IRQn < 0) { 1008 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ 1009 else { 1010 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ 1011 } 1012 1013 1014 /** \brief Get Interrupt Priority 1015 1016 This function reads the priority for the specified interrupt. The interrupt 1017 number can be positive to specify an external (device specific) 1018 interrupt, or negative to specify an internal (core) interrupt. 1019 1020 The returned priority value is automatically aligned to the implemented 1021 priority bits of the microcontroller. 1022 1023 \param [in] IRQn Number of the interrupt for get priority 1024 \return Interrupt Priority 1025 */ 1026 static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) 1027 { 1028 1029 if(IRQn < 0) { 1030 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ 1031 else { 1032 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ 1033 } 1034 1035 1036 /** \brief Encode Priority 1037 1038 This function encodes the priority for an interrupt with the given priority group, 1039 preemptive priority value and sub priority value. 1040 In case of a conflict between priority grouping and available 1041 priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. 1042 1043 The returned priority value can be used for NVIC_SetPriority(...) function 1044 1045 \param [in] PriorityGroup Used priority group 1046 \param [in] PreemptPriority Preemptive priority value (starting from 0) 1047 \param [in] SubPriority Sub priority value (starting from 0) 1048 \return Encoded priority for the interrupt 1049 */ 1050 static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) 1051 { 1052 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ 1053 uint32_t PreemptPriorityBits; 1054 uint32_t SubPriorityBits; 1055 1056 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; 1057 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; 1058 1059 return ( 1060 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | 1061 ((SubPriority & ((1 << (SubPriorityBits )) - 1))) 1062 ); 1063 } 1064 1065 1066 /** \brief Decode Priority 1067 1068 This function decodes an interrupt priority value with the given priority group to 1069 preemptive priority value and sub priority value. 1070 In case of a conflict between priority grouping and available 1071 priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. 1072 1073 The priority value can be retrieved with NVIC_GetPriority(...) function 1074 1075 \param [in] Priority Priority value 1076 \param [in] PriorityGroup Used priority group 1077 \param [out] pPreemptPriority Preemptive priority value (starting from 0) 1078 \param [out] pSubPriority Sub priority value (starting from 0) 1079 */ 1080 static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) 1081 { 1082 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ 1083 uint32_t PreemptPriorityBits; 1084 uint32_t SubPriorityBits; 1085 1086 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; 1087 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; 1088 1089 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); 1090 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); 1091 } 1092 1093 1094 /** \brief System Reset 1095 1096 This function initiate a system reset request to reset the MCU. 1097 */ 1098 static __INLINE void NVIC_SystemReset(void) 1099 { 1100 __DSB(); /* Ensure all outstanding memory accesses included 1101 buffered write are completed before reset */ 1102 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | 1103 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 1104 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ 1105 __DSB(); /* Ensure completion of memory access */ 1106 while(1); /* wait until reset */ 1107 } 1108 1109 /*@} end of CMSIS_Core_NVICFunctions */ 1110 1111 1112 1113 /* ################################## SysTick function ############################################ */ 1114 /** \ingroup CMSIS_Core_FunctionInterface 1115 \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions 1116 @{ 1117 */ 1118 1119 #if (__Vendor_SysTickConfig == 0) 1120 1121 /** \brief System Tick Configuration 1122 1123 This function initialises the system tick timer and its interrupt and start the system tick timer. 1124 Counter is in free running mode to generate periodical interrupts. 1125 1126 \param [in] ticks Number of ticks between two interrupts 1127 \return 0 Function succeeded 1128 \return 1 Function failed 1129 */ 1130 static __INLINE uint32_t SysTick_Config(uint32_t ticks) 1131 { 1132 if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ 1133 1134 SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ 1135 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ 1136 SysTick->VAL = 0; /* Load the SysTick Counter Value */ 1137 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 1138 SysTick_CTRL_TICKINT_Msk | 1139 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 1140 return (0); /* Function successful */ 1141 } 1142 1143 #endif 1144 1145 /*@} end of CMSIS_Core_SysTickFunctions */ 1146 1147 1148 1149 /* ##################################### Debug In/Output function ########################################### */ 1150 /** \ingroup CMSIS_Core_FunctionInterface 1151 \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions 1152 @{ 1153 */ 1154 1155 extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */ 1156 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ 1157 1158 1159 /** \brief ITM Send Character 1160 1161 This function transmits a character via the ITM channel 0. 1162 It just returns when no debugger is connected that has booked the output. 1163 It is blocking when a debugger is connected, but the previous character send is not transmitted. 1164 1165 \param [in] ch Character to transmit 1166 \return Character to transmit 1167 */ 1168 static __INLINE uint32_t ITM_SendChar (uint32_t ch) 1169 { 1170 if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ 1171 (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ 1172 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ 1173 { 1174 while (ITM->PORT[0].u32 == 0); 1175 ITM->PORT[0].u8 = (uint8_t) ch; 1176 } 1177 return (ch); 1178 } 1179 1180 1181 /** \brief ITM Receive Character 1182 1183 This function inputs a character via external variable ITM_RxBuffer. 1184 It just returns when no debugger is connected that has booked the output. 1185 It is blocking when a debugger is connected, but the previous character send is not transmitted. 1186 1187 \return Received character 1188 \return -1 No character received 1189 */ 1190 static __INLINE int32_t ITM_ReceiveChar (void) { 1191 int32_t ch = -1; /* no character available */ 1192 1193 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { 1194 ch = ITM_RxBuffer; 1195 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ 1196 } 1197 1198 return (ch); 1199 } 1200 1201 1202 /** \brief ITM Check Character 1203 1204 This function checks external variable ITM_RxBuffer whether a character is available or not. 1205 It returns '1' if a character is available and '0' if no character is available. 1206 1207 \return 0 No character available 1208 \return 1 Character available 1209 */ 1210 static __INLINE int32_t ITM_CheckChar (void) { 1211 1212 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { 1213 return (0); /* no character available */ 1214 } else { 1215 return (1); /* character available */ 1216 } 1217 } 1218 1219 /*@} end of CMSIS_core_DebugFunctions */ 1220 1221 #endif /* __CORE_CM3_H_DEPENDANT */ 1222 1223 #endif /* __CMSIS_GENERIC */ 1224 1225 #ifdef __cplusplus 1226 } 1227 #endif