core_cmFunc.h (15082B)
1 /**************************************************************************//** 2 * @file core_cmFunc.h 3 * @brief CMSIS Cortex-M Core Function Access Header File 4 * @version V2.10 5 * @date 26. July 2011 6 * 7 * @note 8 * Copyright (C) 2009-2011 ARM Limited. All rights reserved. 9 * 10 * @par 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M 12 * processor based microcontrollers. This file can be freely distributed 13 * within development tools that are supporting such ARM based processors. 14 * 15 * @par 16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED 17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. 19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR 20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. 21 * 22 ******************************************************************************/ 23 24 #ifndef __CORE_CMFUNC_H 25 #define __CORE_CMFUNC_H 26 27 28 /* ########################### Core Function Access ########################### */ 29 /** \ingroup CMSIS_Core_FunctionInterface 30 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions 31 @{ 32 */ 33 34 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ 35 /* ARM armcc specific functions */ 36 37 #if (__ARMCC_VERSION < 400677) 38 #error "Please use ARM Compiler Toolchain V4.0.677 or later!" 39 #endif 40 41 /* intrinsic void __enable_irq(); */ 42 /* intrinsic void __disable_irq(); */ 43 44 /** \brief Get Control Register 45 46 This function returns the content of the Control Register. 47 48 \return Control Register value 49 */ 50 static __INLINE uint32_t __get_CONTROL(void) 51 { 52 register uint32_t __regControl __ASM("control"); 53 return(__regControl); 54 } 55 56 57 /** \brief Set Control Register 58 59 This function writes the given value to the Control Register. 60 61 \param [in] control Control Register value to set 62 */ 63 static __INLINE void __set_CONTROL(uint32_t control) 64 { 65 register uint32_t __regControl __ASM("control"); 66 __regControl = control; 67 } 68 69 70 /** \brief Get ISPR Register 71 72 This function returns the content of the ISPR Register. 73 74 \return ISPR Register value 75 */ 76 static __INLINE uint32_t __get_IPSR(void) 77 { 78 register uint32_t __regIPSR __ASM("ipsr"); 79 return(__regIPSR); 80 } 81 82 83 /** \brief Get APSR Register 84 85 This function returns the content of the APSR Register. 86 87 \return APSR Register value 88 */ 89 static __INLINE uint32_t __get_APSR(void) 90 { 91 register uint32_t __regAPSR __ASM("apsr"); 92 return(__regAPSR); 93 } 94 95 96 /** \brief Get xPSR Register 97 98 This function returns the content of the xPSR Register. 99 100 \return xPSR Register value 101 */ 102 static __INLINE uint32_t __get_xPSR(void) 103 { 104 register uint32_t __regXPSR __ASM("xpsr"); 105 return(__regXPSR); 106 } 107 108 109 /** \brief Get Process Stack Pointer 110 111 This function returns the current value of the Process Stack Pointer (PSP). 112 113 \return PSP Register value 114 */ 115 static __INLINE uint32_t __get_PSP(void) 116 { 117 register uint32_t __regProcessStackPointer __ASM("psp"); 118 return(__regProcessStackPointer); 119 } 120 121 122 /** \brief Set Process Stack Pointer 123 124 This function assigns the given value to the Process Stack Pointer (PSP). 125 126 \param [in] topOfProcStack Process Stack Pointer value to set 127 */ 128 static __INLINE void __set_PSP(uint32_t topOfProcStack) 129 { 130 register uint32_t __regProcessStackPointer __ASM("psp"); 131 __regProcessStackPointer = topOfProcStack; 132 } 133 134 135 /** \brief Get Main Stack Pointer 136 137 This function returns the current value of the Main Stack Pointer (MSP). 138 139 \return MSP Register value 140 */ 141 static __INLINE uint32_t __get_MSP(void) 142 { 143 register uint32_t __regMainStackPointer __ASM("msp"); 144 return(__regMainStackPointer); 145 } 146 147 148 /** \brief Set Main Stack Pointer 149 150 This function assigns the given value to the Main Stack Pointer (MSP). 151 152 \param [in] topOfMainStack Main Stack Pointer value to set 153 */ 154 static __INLINE void __set_MSP(uint32_t topOfMainStack) 155 { 156 register uint32_t __regMainStackPointer __ASM("msp"); 157 __regMainStackPointer = topOfMainStack; 158 } 159 160 161 /** \brief Get Priority Mask 162 163 This function returns the current state of the priority mask bit from the Priority Mask Register. 164 165 \return Priority Mask value 166 */ 167 static __INLINE uint32_t __get_PRIMASK(void) 168 { 169 register uint32_t __regPriMask __ASM("primask"); 170 return(__regPriMask); 171 } 172 173 174 /** \brief Set Priority Mask 175 176 This function assigns the given value to the Priority Mask Register. 177 178 \param [in] priMask Priority Mask 179 */ 180 static __INLINE void __set_PRIMASK(uint32_t priMask) 181 { 182 register uint32_t __regPriMask __ASM("primask"); 183 __regPriMask = (priMask); 184 } 185 186 187 #if (__CORTEX_M >= 0x03) 188 189 /** \brief Enable FIQ 190 191 This function enables FIQ interrupts by clearing the F-bit in the CPSR. 192 Can only be executed in Privileged modes. 193 */ 194 #define __enable_fault_irq __enable_fiq 195 196 197 /** \brief Disable FIQ 198 199 This function disables FIQ interrupts by setting the F-bit in the CPSR. 200 Can only be executed in Privileged modes. 201 */ 202 #define __disable_fault_irq __disable_fiq 203 204 205 /** \brief Get Base Priority 206 207 This function returns the current value of the Base Priority register. 208 209 \return Base Priority register value 210 */ 211 static __INLINE uint32_t __get_BASEPRI(void) 212 { 213 register uint32_t __regBasePri __ASM("basepri"); 214 return(__regBasePri); 215 } 216 217 218 /** \brief Set Base Priority 219 220 This function assigns the given value to the Base Priority register. 221 222 \param [in] basePri Base Priority value to set 223 */ 224 static __INLINE void __set_BASEPRI(uint32_t basePri) 225 { 226 register uint32_t __regBasePri __ASM("basepri"); 227 __regBasePri = (basePri & 0xff); 228 } 229 230 231 /** \brief Get Fault Mask 232 233 This function returns the current value of the Fault Mask register. 234 235 \return Fault Mask register value 236 */ 237 static __INLINE uint32_t __get_FAULTMASK(void) 238 { 239 register uint32_t __regFaultMask __ASM("faultmask"); 240 return(__regFaultMask); 241 } 242 243 244 /** \brief Set Fault Mask 245 246 This function assigns the given value to the Fault Mask register. 247 248 \param [in] faultMask Fault Mask value to set 249 */ 250 static __INLINE void __set_FAULTMASK(uint32_t faultMask) 251 { 252 register uint32_t __regFaultMask __ASM("faultmask"); 253 __regFaultMask = (faultMask & (uint32_t)1); 254 } 255 256 #endif /* (__CORTEX_M >= 0x03) */ 257 258 259 #if (__CORTEX_M == 0x04) 260 261 /** \brief Get FPSCR 262 263 This function returns the current value of the Floating Point Status/Control register. 264 265 \return Floating Point Status/Control register value 266 */ 267 static __INLINE uint32_t __get_FPSCR(void) 268 { 269 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) 270 register uint32_t __regfpscr __ASM("fpscr"); 271 return(__regfpscr); 272 #else 273 return(0); 274 #endif 275 } 276 277 278 /** \brief Set FPSCR 279 280 This function assigns the given value to the Floating Point Status/Control register. 281 282 \param [in] fpscr Floating Point Status/Control value to set 283 */ 284 static __INLINE void __set_FPSCR(uint32_t fpscr) 285 { 286 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) 287 register uint32_t __regfpscr __ASM("fpscr"); 288 __regfpscr = (fpscr); 289 #endif 290 } 291 292 #endif /* (__CORTEX_M == 0x04) */ 293 294 295 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ 296 /* IAR iccarm specific functions */ 297 298 #include <cmsis_iar.h> 299 300 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ 301 /* GNU gcc specific functions */ 302 303 /** \brief Enable IRQ Interrupts 304 305 This function enables IRQ interrupts by clearing the I-bit in the CPSR. 306 Can only be executed in Privileged modes. 307 */ 308 __attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void) 309 { 310 __ASM volatile ("cpsie i"); 311 } 312 313 314 /** \brief Disable IRQ Interrupts 315 316 This function disables IRQ interrupts by setting the I-bit in the CPSR. 317 Can only be executed in Privileged modes. 318 */ 319 __attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void) 320 { 321 __ASM volatile ("cpsid i"); 322 } 323 324 325 /** \brief Get Control Register 326 327 This function returns the content of the Control Register. 328 329 \return Control Register value 330 */ 331 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void) 332 { 333 uint32_t result; 334 335 __ASM volatile ("MRS %0, control" : "=r" (result) ); 336 return(result); 337 } 338 339 340 /** \brief Set Control Register 341 342 This function writes the given value to the Control Register. 343 344 \param [in] control Control Register value to set 345 */ 346 __attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control) 347 { 348 __ASM volatile ("MSR control, %0" : : "r" (control) ); 349 } 350 351 352 /** \brief Get ISPR Register 353 354 This function returns the content of the ISPR Register. 355 356 \return ISPR Register value 357 */ 358 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void) 359 { 360 uint32_t result; 361 362 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 363 return(result); 364 } 365 366 367 /** \brief Get APSR Register 368 369 This function returns the content of the APSR Register. 370 371 \return APSR Register value 372 */ 373 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void) 374 { 375 uint32_t result; 376 377 __ASM volatile ("MRS %0, apsr" : "=r" (result) ); 378 return(result); 379 } 380 381 382 /** \brief Get xPSR Register 383 384 This function returns the content of the xPSR Register. 385 386 \return xPSR Register value 387 */ 388 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void) 389 { 390 uint32_t result; 391 392 __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); 393 return(result); 394 } 395 396 397 /** \brief Get Process Stack Pointer 398 399 This function returns the current value of the Process Stack Pointer (PSP). 400 401 \return PSP Register value 402 */ 403 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void) 404 { 405 register uint32_t result; 406 407 __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); 408 return(result); 409 } 410 411 412 /** \brief Set Process Stack Pointer 413 414 This function assigns the given value to the Process Stack Pointer (PSP). 415 416 \param [in] topOfProcStack Process Stack Pointer value to set 417 */ 418 __attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack) 419 { 420 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); 421 } 422 423 424 /** \brief Get Main Stack Pointer 425 426 This function returns the current value of the Main Stack Pointer (MSP). 427 428 \return MSP Register value 429 */ 430 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void) 431 { 432 register uint32_t result; 433 434 __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); 435 return(result); 436 } 437 438 439 /** \brief Set Main Stack Pointer 440 441 This function assigns the given value to the Main Stack Pointer (MSP). 442 443 \param [in] topOfMainStack Main Stack Pointer value to set 444 */ 445 __attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack) 446 { 447 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); 448 } 449 450 451 /** \brief Get Priority Mask 452 453 This function returns the current state of the priority mask bit from the Priority Mask Register. 454 455 \return Priority Mask value 456 */ 457 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void) 458 { 459 uint32_t result; 460 461 __ASM volatile ("MRS %0, primask" : "=r" (result) ); 462 return(result); 463 } 464 465 466 /** \brief Set Priority Mask 467 468 This function assigns the given value to the Priority Mask Register. 469 470 \param [in] priMask Priority Mask 471 */ 472 __attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask) 473 { 474 __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); 475 } 476 477 478 #if (__CORTEX_M >= 0x03) 479 480 /** \brief Enable FIQ 481 482 This function enables FIQ interrupts by clearing the F-bit in the CPSR. 483 Can only be executed in Privileged modes. 484 */ 485 __attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void) 486 { 487 __ASM volatile ("cpsie f"); 488 } 489 490 491 /** \brief Disable FIQ 492 493 This function disables FIQ interrupts by setting the F-bit in the CPSR. 494 Can only be executed in Privileged modes. 495 */ 496 __attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void) 497 { 498 __ASM volatile ("cpsid f"); 499 } 500 501 502 /** \brief Get Base Priority 503 504 This function returns the current value of the Base Priority register. 505 506 \return Base Priority register value 507 */ 508 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void) 509 { 510 uint32_t result; 511 512 __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); 513 return(result); 514 } 515 516 517 /** \brief Set Base Priority 518 519 This function assigns the given value to the Base Priority register. 520 521 \param [in] basePri Base Priority value to set 522 */ 523 __attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value) 524 { 525 __ASM volatile ("MSR basepri, %0" : : "r" (value) ); 526 } 527 528 529 /** \brief Get Fault Mask 530 531 This function returns the current value of the Fault Mask register. 532 533 \return Fault Mask register value 534 */ 535 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void) 536 { 537 uint32_t result; 538 539 __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); 540 return(result); 541 } 542 543 544 /** \brief Set Fault Mask 545 546 This function assigns the given value to the Fault Mask register. 547 548 \param [in] faultMask Fault Mask value to set 549 */ 550 __attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask) 551 { 552 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); 553 } 554 555 #endif /* (__CORTEX_M >= 0x03) */ 556 557 558 #if (__CORTEX_M == 0x04) 559 560 /** \brief Get FPSCR 561 562 This function returns the current value of the Floating Point Status/Control register. 563 564 \return Floating Point Status/Control register value 565 */ 566 __attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void) 567 { 568 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) 569 uint32_t result; 570 571 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); 572 return(result); 573 #else 574 return(0); 575 #endif 576 } 577 578 579 /** \brief Set FPSCR 580 581 This function assigns the given value to the Floating Point Status/Control register. 582 583 \param [in] fpscr Floating Point Status/Control value to set 584 */ 585 __attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr) 586 { 587 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) 588 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) ); 589 #endif 590 } 591 592 #endif /* (__CORTEX_M == 0x04) */ 593 594 595 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ 596 /* TASKING carm specific functions */ 597 598 /* 599 * The CMSIS functions have been implemented as intrinsics in the compiler. 600 * Please use "carm -?i" to get an up to date list of all instrinsics, 601 * Including the CMSIS ones. 602 */ 603 604 #endif 605 606 /*@} end of CMSIS_Core_RegAccFunctions */ 607 608 609 #endif /* __CORE_CMFUNC_H */