core_cmInstr.h (15511B)
1 /**************************************************************************//** 2 * @file core_cmInstr.h 3 * @brief CMSIS Cortex-M Core Instruction Access Header File 4 * @version V2.10 5 * @date 19. July 2011 6 * 7 * @note 8 * Copyright (C) 2009-2011 ARM Limited. All rights reserved. 9 * 10 * @par 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M 12 * processor based microcontrollers. This file can be freely distributed 13 * within development tools that are supporting such ARM based processors. 14 * 15 * @par 16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED 17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. 19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR 20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. 21 * 22 ******************************************************************************/ 23 24 #ifndef __CORE_CMINSTR_H 25 #define __CORE_CMINSTR_H 26 27 28 /* ########################## Core Instruction Access ######################### */ 29 /** \ingroup CMSIS_Core 30 \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface 31 Access to dedicated instructions 32 @{ 33 */ 34 35 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ 36 /* ARM armcc specific functions */ 37 38 #if (__ARMCC_VERSION < 400677) 39 #error "Please use ARM Compiler Toolchain V4.0.677 or later!" 40 #endif 41 42 43 /** \brief No Operation 44 45 No Operation does nothing. This instruction can be used for code alignment purposes. 46 */ 47 #define __NOP __nop 48 49 50 /** \brief Wait For Interrupt 51 52 Wait For Interrupt is a hint instruction that suspends execution 53 until one of a number of events occurs. 54 */ 55 #define __WFI __wfi 56 57 58 /** \brief Wait For Event 59 60 Wait For Event is a hint instruction that permits the processor to enter 61 a low-power state until one of a number of events occurs. 62 */ 63 #define __WFE __wfe 64 65 66 /** \brief Send Event 67 68 Send Event is a hint instruction. It causes an event to be signaled to the CPU. 69 */ 70 #define __SEV __sev 71 72 73 /** \brief Instruction Synchronization Barrier 74 75 Instruction Synchronization Barrier flushes the pipeline in the processor, 76 so that all instructions following the ISB are fetched from cache or 77 memory, after the instruction has been completed. 78 */ 79 #define __ISB() __isb(0xF) 80 81 82 /** \brief Data Synchronization Barrier 83 84 This function acts as a special kind of Data Memory Barrier. 85 It completes when all explicit memory accesses before this instruction complete. 86 */ 87 #define __DSB() __dsb(0xF) 88 89 90 /** \brief Data Memory Barrier 91 92 This function ensures the apparent order of the explicit memory operations before 93 and after the instruction, without ensuring their completion. 94 */ 95 #define __DMB() __dmb(0xF) 96 97 98 /** \brief Reverse byte order (32 bit) 99 100 This function reverses the byte order in integer value. 101 102 \param [in] value Value to reverse 103 \return Reversed value 104 */ 105 #define __REV __rev 106 107 108 /** \brief Reverse byte order (16 bit) 109 110 This function reverses the byte order in two unsigned short values. 111 112 \param [in] value Value to reverse 113 \return Reversed value 114 */ 115 static __INLINE __ASM uint32_t __REV16(uint32_t value) 116 { 117 rev16 r0, r0 118 bx lr 119 } 120 121 122 /** \brief Reverse byte order in signed short value 123 124 This function reverses the byte order in a signed short value with sign extension to integer. 125 126 \param [in] value Value to reverse 127 \return Reversed value 128 */ 129 static __INLINE __ASM int32_t __REVSH(int32_t value) 130 { 131 revsh r0, r0 132 bx lr 133 } 134 135 136 #if (__CORTEX_M >= 0x03) 137 138 /** \brief Reverse bit order of value 139 140 This function reverses the bit order of the given value. 141 142 \param [in] value Value to reverse 143 \return Reversed value 144 */ 145 #define __RBIT __rbit 146 147 148 /** \brief LDR Exclusive (8 bit) 149 150 This function performs a exclusive LDR command for 8 bit value. 151 152 \param [in] ptr Pointer to data 153 \return value of type uint8_t at (*ptr) 154 */ 155 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) 156 157 158 /** \brief LDR Exclusive (16 bit) 159 160 This function performs a exclusive LDR command for 16 bit values. 161 162 \param [in] ptr Pointer to data 163 \return value of type uint16_t at (*ptr) 164 */ 165 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) 166 167 168 /** \brief LDR Exclusive (32 bit) 169 170 This function performs a exclusive LDR command for 32 bit values. 171 172 \param [in] ptr Pointer to data 173 \return value of type uint32_t at (*ptr) 174 */ 175 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) 176 177 178 /** \brief STR Exclusive (8 bit) 179 180 This function performs a exclusive STR command for 8 bit values. 181 182 \param [in] value Value to store 183 \param [in] ptr Pointer to location 184 \return 0 Function succeeded 185 \return 1 Function failed 186 */ 187 #define __STREXB(value, ptr) __strex(value, ptr) 188 189 190 /** \brief STR Exclusive (16 bit) 191 192 This function performs a exclusive STR command for 16 bit values. 193 194 \param [in] value Value to store 195 \param [in] ptr Pointer to location 196 \return 0 Function succeeded 197 \return 1 Function failed 198 */ 199 #define __STREXH(value, ptr) __strex(value, ptr) 200 201 202 /** \brief STR Exclusive (32 bit) 203 204 This function performs a exclusive STR command for 32 bit values. 205 206 \param [in] value Value to store 207 \param [in] ptr Pointer to location 208 \return 0 Function succeeded 209 \return 1 Function failed 210 */ 211 #define __STREXW(value, ptr) __strex(value, ptr) 212 213 214 /** \brief Remove the exclusive lock 215 216 This function removes the exclusive lock which is created by LDREX. 217 218 */ 219 #define __CLREX __clrex 220 221 222 /** \brief Signed Saturate 223 224 This function saturates a signed value. 225 226 \param [in] value Value to be saturated 227 \param [in] sat Bit position to saturate to (1..32) 228 \return Saturated value 229 */ 230 #define __SSAT __ssat 231 232 233 /** \brief Unsigned Saturate 234 235 This function saturates an unsigned value. 236 237 \param [in] value Value to be saturated 238 \param [in] sat Bit position to saturate to (0..31) 239 \return Saturated value 240 */ 241 #define __USAT __usat 242 243 244 /** \brief Count leading zeros 245 246 This function counts the number of leading zeros of a data value. 247 248 \param [in] value Value to count the leading zeros 249 \return number of leading zeros in value 250 */ 251 #define __CLZ __clz 252 253 #endif /* (__CORTEX_M >= 0x03) */ 254 255 256 257 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ 258 /* IAR iccarm specific functions */ 259 260 #include <cmsis_iar.h> 261 262 263 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ 264 /* GNU gcc specific functions */ 265 266 /** \brief No Operation 267 268 No Operation does nothing. This instruction can be used for code alignment purposes. 269 */ 270 __attribute__( ( always_inline ) ) static __INLINE void __NOP(void) 271 { 272 __ASM volatile ("nop"); 273 } 274 275 276 /** \brief Wait For Interrupt 277 278 Wait For Interrupt is a hint instruction that suspends execution 279 until one of a number of events occurs. 280 */ 281 __attribute__( ( always_inline ) ) static __INLINE void __WFI(void) 282 { 283 __ASM volatile ("wfi"); 284 } 285 286 287 /** \brief Wait For Event 288 289 Wait For Event is a hint instruction that permits the processor to enter 290 a low-power state until one of a number of events occurs. 291 */ 292 __attribute__( ( always_inline ) ) static __INLINE void __WFE(void) 293 { 294 __ASM volatile ("wfe"); 295 } 296 297 298 /** \brief Send Event 299 300 Send Event is a hint instruction. It causes an event to be signaled to the CPU. 301 */ 302 __attribute__( ( always_inline ) ) static __INLINE void __SEV(void) 303 { 304 __ASM volatile ("sev"); 305 } 306 307 308 /** \brief Instruction Synchronization Barrier 309 310 Instruction Synchronization Barrier flushes the pipeline in the processor, 311 so that all instructions following the ISB are fetched from cache or 312 memory, after the instruction has been completed. 313 */ 314 __attribute__( ( always_inline ) ) static __INLINE void __ISB(void) 315 { 316 __ASM volatile ("isb"); 317 } 318 319 320 /** \brief Data Synchronization Barrier 321 322 This function acts as a special kind of Data Memory Barrier. 323 It completes when all explicit memory accesses before this instruction complete. 324 */ 325 __attribute__( ( always_inline ) ) static __INLINE void __DSB(void) 326 { 327 __ASM volatile ("dsb"); 328 } 329 330 331 /** \brief Data Memory Barrier 332 333 This function ensures the apparent order of the explicit memory operations before 334 and after the instruction, without ensuring their completion. 335 */ 336 __attribute__( ( always_inline ) ) static __INLINE void __DMB(void) 337 { 338 __ASM volatile ("dmb"); 339 } 340 341 342 /** \brief Reverse byte order (32 bit) 343 344 This function reverses the byte order in integer value. 345 346 \param [in] value Value to reverse 347 \return Reversed value 348 */ 349 __attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value) 350 { 351 uint32_t result; 352 353 __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); 354 return(result); 355 } 356 357 358 /** \brief Reverse byte order (16 bit) 359 360 This function reverses the byte order in two unsigned short values. 361 362 \param [in] value Value to reverse 363 \return Reversed value 364 */ 365 __attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value) 366 { 367 uint32_t result; 368 369 __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); 370 return(result); 371 } 372 373 374 /** \brief Reverse byte order in signed short value 375 376 This function reverses the byte order in a signed short value with sign extension to integer. 377 378 \param [in] value Value to reverse 379 \return Reversed value 380 */ 381 __attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value) 382 { 383 uint32_t result; 384 385 __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); 386 return(result); 387 } 388 389 390 #if (__CORTEX_M >= 0x03) 391 392 /** \brief Reverse bit order of value 393 394 This function reverses the bit order of the given value. 395 396 \param [in] value Value to reverse 397 \return Reversed value 398 */ 399 __attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value) 400 { 401 uint32_t result; 402 403 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 404 return(result); 405 } 406 407 408 /** \brief LDR Exclusive (8 bit) 409 410 This function performs a exclusive LDR command for 8 bit value. 411 412 \param [in] ptr Pointer to data 413 \return value of type uint8_t at (*ptr) 414 */ 415 __attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr) 416 { 417 uint8_t result; 418 419 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); 420 return(result); 421 } 422 423 424 /** \brief LDR Exclusive (16 bit) 425 426 This function performs a exclusive LDR command for 16 bit values. 427 428 \param [in] ptr Pointer to data 429 \return value of type uint16_t at (*ptr) 430 */ 431 __attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr) 432 { 433 uint16_t result; 434 435 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); 436 return(result); 437 } 438 439 440 /** \brief LDR Exclusive (32 bit) 441 442 This function performs a exclusive LDR command for 32 bit values. 443 444 \param [in] ptr Pointer to data 445 \return value of type uint32_t at (*ptr) 446 */ 447 __attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr) 448 { 449 uint32_t result; 450 451 __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); 452 return(result); 453 } 454 455 456 /** \brief STR Exclusive (8 bit) 457 458 This function performs a exclusive STR command for 8 bit values. 459 460 \param [in] value Value to store 461 \param [in] ptr Pointer to location 462 \return 0 Function succeeded 463 \return 1 Function failed 464 */ 465 __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) 466 { 467 uint32_t result; 468 469 __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); 470 return(result); 471 } 472 473 474 /** \brief STR Exclusive (16 bit) 475 476 This function performs a exclusive STR command for 16 bit values. 477 478 \param [in] value Value to store 479 \param [in] ptr Pointer to location 480 \return 0 Function succeeded 481 \return 1 Function failed 482 */ 483 __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) 484 { 485 uint32_t result; 486 487 __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); 488 return(result); 489 } 490 491 492 /** \brief STR Exclusive (32 bit) 493 494 This function performs a exclusive STR command for 32 bit values. 495 496 \param [in] value Value to store 497 \param [in] ptr Pointer to location 498 \return 0 Function succeeded 499 \return 1 Function failed 500 */ 501 __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) 502 { 503 uint32_t result; 504 505 __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); 506 return(result); 507 } 508 509 510 /** \brief Remove the exclusive lock 511 512 This function removes the exclusive lock which is created by LDREX. 513 514 */ 515 __attribute__( ( always_inline ) ) static __INLINE void __CLREX(void) 516 { 517 __ASM volatile ("clrex"); 518 } 519 520 521 /** \brief Signed Saturate 522 523 This function saturates a signed value. 524 525 \param [in] value Value to be saturated 526 \param [in] sat Bit position to saturate to (1..32) 527 \return Saturated value 528 */ 529 #define __SSAT(ARG1,ARG2) \ 530 ({ \ 531 uint32_t __RES, __ARG1 = (ARG1); \ 532 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ 533 __RES; \ 534 }) 535 536 537 /** \brief Unsigned Saturate 538 539 This function saturates an unsigned value. 540 541 \param [in] value Value to be saturated 542 \param [in] sat Bit position to saturate to (0..31) 543 \return Saturated value 544 */ 545 #define __USAT(ARG1,ARG2) \ 546 ({ \ 547 uint32_t __RES, __ARG1 = (ARG1); \ 548 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ 549 __RES; \ 550 }) 551 552 553 /** \brief Count leading zeros 554 555 This function counts the number of leading zeros of a data value. 556 557 \param [in] value Value to count the leading zeros 558 \return number of leading zeros in value 559 */ 560 __attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value) 561 { 562 uint8_t result; 563 564 __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); 565 return(result); 566 } 567 568 #endif /* (__CORTEX_M >= 0x03) */ 569 570 571 572 573 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ 574 /* TASKING carm specific functions */ 575 576 /* 577 * The CMSIS functions have been implemented as intrinsics in the compiler. 578 * Please use "carm -?i" to get an up to date list of all intrinsics, 579 * Including the CMSIS ones. 580 */ 581 582 #endif 583 584 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ 585 586 #endif /* __CORE_CMINSTR_H */