lpc17xx_clkpwr.h (17462B)
1 /********************************************************************** 2 * $Id$ lpc17xx_clkpwr.h 2010-05-21 3 *//** 4 * @file lpc17xx_clkpwr.h 5 * @brief Contains all macro definitions and function prototypes 6 * support for Clock and Power Control firmware library on LPC17xx 7 * @version 2.0 8 * @date 21. May. 2010 9 * @author NXP MCU SW Application Team 10 * 11 * Copyright(C) 2010, NXP Semiconductor 12 * All rights reserved. 13 * 14 *********************************************************************** 15 * Software that is described herein is for illustrative purposes only 16 * which provides customers with programming information regarding the 17 * products. This software is supplied "AS IS" without any warranties. 18 * NXP Semiconductors assumes no responsibility or liability for the 19 * use of the software, conveys no license or title under any patent, 20 * copyright, or mask work right to the product. NXP Semiconductors 21 * reserves the right to make changes in the software without 22 * notification. NXP Semiconductors also make no representation or 23 * warranty that such application will be suitable for the specified 24 * use without further testing or modification. 25 * Permission to use, copy, modify, and distribute this software and its 26 * documentation is hereby granted, under NXP Semiconductors' 27 * relevant copyright in the software, without fee, provided that it 28 * is used in conjunction with NXP Semiconductors microcontrollers. This 29 * copyright, permission, and disclaimer notice must appear in all copies of 30 * this code. 31 **********************************************************************/ 32 33 /* Peripheral group ----------------------------------------------------------- */ 34 /** @defgroup CLKPWR CLKPWR (Clock Power) 35 * @ingroup LPC1700CMSIS_FwLib_Drivers 36 * @{ 37 */ 38 39 #ifndef LPC17XX_CLKPWR_H_ 40 #define LPC17XX_CLKPWR_H_ 41 42 /* Includes ------------------------------------------------------------------- */ 43 #include "LPC17xx.h" 44 #include "lpc_types.h" 45 46 #ifdef __cplusplus 47 extern "C" 48 { 49 #endif 50 51 /* Public Macros -------------------------------------------------------------- */ 52 /** @defgroup CLKPWR_Public_Macros CLKPWR Public Macros 53 * @{ 54 */ 55 56 /********************************************************************** 57 * Peripheral Clock Selection Definitions 58 **********************************************************************/ 59 /** Peripheral clock divider bit position for WDT */ 60 #define CLKPWR_PCLKSEL_WDT ((uint32_t)(0)) 61 /** Peripheral clock divider bit position for TIMER0 */ 62 #define CLKPWR_PCLKSEL_TIMER0 ((uint32_t)(2)) 63 /** Peripheral clock divider bit position for TIMER1 */ 64 #define CLKPWR_PCLKSEL_TIMER1 ((uint32_t)(4)) 65 /** Peripheral clock divider bit position for UART0 */ 66 #define CLKPWR_PCLKSEL_UART0 ((uint32_t)(6)) 67 /** Peripheral clock divider bit position for UART1 */ 68 #define CLKPWR_PCLKSEL_UART1 ((uint32_t)(8)) 69 /** Peripheral clock divider bit position for PWM1 */ 70 #define CLKPWR_PCLKSEL_PWM1 ((uint32_t)(12)) 71 /** Peripheral clock divider bit position for I2C0 */ 72 #define CLKPWR_PCLKSEL_I2C0 ((uint32_t)(14)) 73 /** Peripheral clock divider bit position for SPI */ 74 #define CLKPWR_PCLKSEL_SPI ((uint32_t)(16)) 75 /** Peripheral clock divider bit position for SSP1 */ 76 #define CLKPWR_PCLKSEL_SSP1 ((uint32_t)(20)) 77 /** Peripheral clock divider bit position for DAC */ 78 #define CLKPWR_PCLKSEL_DAC ((uint32_t)(22)) 79 /** Peripheral clock divider bit position for ADC */ 80 #define CLKPWR_PCLKSEL_ADC ((uint32_t)(24)) 81 /** Peripheral clock divider bit position for CAN1 */ 82 #define CLKPWR_PCLKSEL_CAN1 ((uint32_t)(26)) 83 /** Peripheral clock divider bit position for CAN2 */ 84 #define CLKPWR_PCLKSEL_CAN2 ((uint32_t)(28)) 85 /** Peripheral clock divider bit position for ACF */ 86 #define CLKPWR_PCLKSEL_ACF ((uint32_t)(30)) 87 /** Peripheral clock divider bit position for QEI */ 88 #define CLKPWR_PCLKSEL_QEI ((uint32_t)(32)) 89 /** Peripheral clock divider bit position for PCB */ 90 #define CLKPWR_PCLKSEL_PCB ((uint32_t)(36)) 91 /** Peripheral clock divider bit position for I2C1 */ 92 #define CLKPWR_PCLKSEL_I2C1 ((uint32_t)(38)) 93 /** Peripheral clock divider bit position for SSP0 */ 94 #define CLKPWR_PCLKSEL_SSP0 ((uint32_t)(42)) 95 /** Peripheral clock divider bit position for TIMER2 */ 96 #define CLKPWR_PCLKSEL_TIMER2 ((uint32_t)(44)) 97 /** Peripheral clock divider bit position for TIMER3 */ 98 #define CLKPWR_PCLKSEL_TIMER3 ((uint32_t)(46)) 99 /** Peripheral clock divider bit position for UART2 */ 100 #define CLKPWR_PCLKSEL_UART2 ((uint32_t)(48)) 101 /** Peripheral clock divider bit position for UART3 */ 102 #define CLKPWR_PCLKSEL_UART3 ((uint32_t)(50)) 103 /** Peripheral clock divider bit position for I2C2 */ 104 #define CLKPWR_PCLKSEL_I2C2 ((uint32_t)(52)) 105 /** Peripheral clock divider bit position for I2S */ 106 #define CLKPWR_PCLKSEL_I2S ((uint32_t)(54)) 107 /** Peripheral clock divider bit position for RIT */ 108 #define CLKPWR_PCLKSEL_RIT ((uint32_t)(58)) 109 /** Peripheral clock divider bit position for SYSCON */ 110 #define CLKPWR_PCLKSEL_SYSCON ((uint32_t)(60)) 111 /** Peripheral clock divider bit position for MC */ 112 #define CLKPWR_PCLKSEL_MC ((uint32_t)(62)) 113 114 /** Macro for Peripheral Clock Selection register bit values 115 * Note: When CCLK_DIV_8, Peripheral’s clock is selected to 116 * PCLK_xyz = CCLK/8 except for CAN1, CAN2, and CAN filtering 117 * when ’11’selects PCLK_xyz = CCLK/6 */ 118 /* Peripheral clock divider is set to 4 from CCLK */ 119 #define CLKPWR_PCLKSEL_CCLK_DIV_4 ((uint32_t)(0)) 120 /** Peripheral clock divider is the same with CCLK */ 121 #define CLKPWR_PCLKSEL_CCLK_DIV_1 ((uint32_t)(1)) 122 /** Peripheral clock divider is set to 2 from CCLK */ 123 #define CLKPWR_PCLKSEL_CCLK_DIV_2 ((uint32_t)(2)) 124 125 126 /******************************************************************** 127 * Power Control for Peripherals Definitions 128 **********************************************************************/ 129 /** Timer/Counter 0 power/clock control bit */ 130 #define CLKPWR_PCONP_PCTIM0 ((uint32_t)(1<<1)) 131 /* Timer/Counter 1 power/clock control bit */ 132 #define CLKPWR_PCONP_PCTIM1 ((uint32_t)(1<<2)) 133 /** UART0 power/clock control bit */ 134 #define CLKPWR_PCONP_PCUART0 ((uint32_t)(1<<3)) 135 /** UART1 power/clock control bit */ 136 #define CLKPWR_PCONP_PCUART1 ((uint32_t)(1<<4)) 137 /** PWM1 power/clock control bit */ 138 #define CLKPWR_PCONP_PCPWM1 ((uint32_t)(1<<6)) 139 /** The I2C0 interface power/clock control bit */ 140 #define CLKPWR_PCONP_PCI2C0 ((uint32_t)(1<<7)) 141 /** The SPI interface power/clock control bit */ 142 #define CLKPWR_PCONP_PCSPI ((uint32_t)(1<<8)) 143 /** The RTC power/clock control bit */ 144 #define CLKPWR_PCONP_PCRTC ((uint32_t)(1<<9)) 145 /** The SSP1 interface power/clock control bit */ 146 #define CLKPWR_PCONP_PCSSP1 ((uint32_t)(1<<10)) 147 /** A/D converter 0 (ADC0) power/clock control bit */ 148 #define CLKPWR_PCONP_PCAD ((uint32_t)(1<<12)) 149 /** CAN Controller 1 power/clock control bit */ 150 #define CLKPWR_PCONP_PCAN1 ((uint32_t)(1<<13)) 151 /** CAN Controller 2 power/clock control bit */ 152 #define CLKPWR_PCONP_PCAN2 ((uint32_t)(1<<14)) 153 /** GPIO power/clock control bit */ 154 #define CLKPWR_PCONP_PCGPIO ((uint32_t)(1<<15)) 155 /** Repetitive Interrupt Timer power/clock control bit */ 156 #define CLKPWR_PCONP_PCRIT ((uint32_t)(1<<16)) 157 /** Motor Control PWM */ 158 #define CLKPWR_PCONP_PCMC ((uint32_t)(1<<17)) 159 /** Quadrature Encoder Interface power/clock control bit */ 160 #define CLKPWR_PCONP_PCQEI ((uint32_t)(1<<18)) 161 /** The I2C1 interface power/clock control bit */ 162 #define CLKPWR_PCONP_PCI2C1 ((uint32_t)(1<<19)) 163 /** The SSP0 interface power/clock control bit */ 164 #define CLKPWR_PCONP_PCSSP0 ((uint32_t)(1<<21)) 165 /** Timer 2 power/clock control bit */ 166 #define CLKPWR_PCONP_PCTIM2 ((uint32_t)(1<<22)) 167 /** Timer 3 power/clock control bit */ 168 #define CLKPWR_PCONP_PCTIM3 ((uint32_t)(1<<23)) 169 /** UART 2 power/clock control bit */ 170 #define CLKPWR_PCONP_PCUART2 ((uint32_t)(1<<24)) 171 /** UART 3 power/clock control bit */ 172 #define CLKPWR_PCONP_PCUART3 ((uint32_t)(1<<25)) 173 /** I2C interface 2 power/clock control bit */ 174 #define CLKPWR_PCONP_PCI2C2 ((uint32_t)(1<<26)) 175 /** I2S interface power/clock control bit*/ 176 #define CLKPWR_PCONP_PCI2S ((uint32_t)(1<<27)) 177 /** GP DMA function power/clock control bit*/ 178 #define CLKPWR_PCONP_PCGPDMA ((uint32_t)(1<<29)) 179 /** Ethernet block power/clock control bit*/ 180 #define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30)) 181 /** USB interface power/clock control bit*/ 182 #define CLKPWR_PCONP_PCUSB ((uint32_t)(1<<31)) 183 184 185 /** 186 * @} 187 */ 188 /* Private Macros ------------------------------------------------------------- */ 189 /** @defgroup CLKPWR_Private_Macros CLKPWR Private Macros 190 * @{ 191 */ 192 193 /* --------------------- BIT DEFINITIONS -------------------------------------- */ 194 /*********************************************************************//** 195 * Macro defines for Clock Source Select Register 196 **********************************************************************/ 197 /** Internal RC oscillator */ 198 #define CLKPWR_CLKSRCSEL_CLKSRC_IRC ((uint32_t)(0x00)) 199 /** Main oscillator */ 200 #define CLKPWR_CLKSRCSEL_CLKSRC_MAINOSC ((uint32_t)(0x01)) 201 /** RTC oscillator */ 202 #define CLKPWR_CLKSRCSEL_CLKSRC_RTC ((uint32_t)(0x02)) 203 /** Clock source selection bit mask */ 204 #define CLKPWR_CLKSRCSEL_BITMASK ((uint32_t)(0x03)) 205 206 /*********************************************************************//** 207 * Macro defines for Clock Output Configuration Register 208 **********************************************************************/ 209 /* Clock Output Configuration register definition */ 210 /** Selects the CPU clock as the CLKOUT source */ 211 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_CPU ((uint32_t)(0x00)) 212 /** Selects the main oscillator as the CLKOUT source */ 213 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_MAINOSC ((uint32_t)(0x01)) 214 /** Selects the Internal RC oscillator as the CLKOUT source */ 215 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_RC ((uint32_t)(0x02)) 216 /** Selects the USB clock as the CLKOUT source */ 217 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_USB ((uint32_t)(0x03)) 218 /** Selects the RTC oscillator as the CLKOUT source */ 219 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_RTC ((uint32_t)(0x04)) 220 /** Integer value to divide the output clock by, minus one */ 221 #define CLKPWR_CLKOUTCFG_CLKOUTDIV(n) ((uint32_t)((n&0x0F)<<4)) 222 /** CLKOUT enable control */ 223 #define CLKPWR_CLKOUTCFG_CLKOUT_EN ((uint32_t)(1<<8)) 224 /** CLKOUT activity indication */ 225 #define CLKPWR_CLKOUTCFG_CLKOUT_ACT ((uint32_t)(1<<9)) 226 /** Clock source selection bit mask */ 227 #define CLKPWR_CLKOUTCFG_BITMASK ((uint32_t)(0x3FF)) 228 229 /*********************************************************************//** 230 * Macro defines for PPL0 Control Register 231 **********************************************************************/ 232 /** PLL 0 control enable */ 233 #define CLKPWR_PLL0CON_ENABLE ((uint32_t)(0x01)) 234 /** PLL 0 control connect */ 235 #define CLKPWR_PLL0CON_CONNECT ((uint32_t)(0x02)) 236 /** PLL 0 control bit mask */ 237 #define CLKPWR_PLL0CON_BITMASK ((uint32_t)(0x03)) 238 239 /*********************************************************************//** 240 * Macro defines for PPL0 Configuration Register 241 **********************************************************************/ 242 /** PLL 0 Configuration MSEL field */ 243 #define CLKPWR_PLL0CFG_MSEL(n) ((uint32_t)(n&0x7FFF)) 244 /** PLL 0 Configuration NSEL field */ 245 #define CLKPWR_PLL0CFG_NSEL(n) ((uint32_t)((n<<16)&0xFF0000)) 246 /** PLL 0 Configuration bit mask */ 247 #define CLKPWR_PLL0CFG_BITMASK ((uint32_t)(0xFF7FFF)) 248 249 250 /*********************************************************************//** 251 * Macro defines for PPL0 Status Register 252 **********************************************************************/ 253 /** PLL 0 MSEL value */ 254 #define CLKPWR_PLL0STAT_MSEL(n) ((uint32_t)(n&0x7FFF)) 255 /** PLL NSEL get value */ 256 #define CLKPWR_PLL0STAT_NSEL(n) ((uint32_t)((n>>16)&0xFF)) 257 /** PLL status enable bit */ 258 #define CLKPWR_PLL0STAT_PLLE ((uint32_t)(1<<24)) 259 /** PLL status Connect bit */ 260 #define CLKPWR_PLL0STAT_PLLC ((uint32_t)(1<<25)) 261 /** PLL status lock */ 262 #define CLKPWR_PLL0STAT_PLOCK ((uint32_t)(1<<26)) 263 264 /*********************************************************************//** 265 * Macro defines for PPL0 Feed Register 266 **********************************************************************/ 267 /** PLL0 Feed bit mask */ 268 #define CLKPWR_PLL0FEED_BITMASK ((uint32_t)0xFF) 269 270 /*********************************************************************//** 271 * Macro defines for PLL1 Control Register 272 **********************************************************************/ 273 /** USB PLL control enable */ 274 #define CLKPWR_PLL1CON_ENABLE ((uint32_t)(0x01)) 275 /** USB PLL control connect */ 276 #define CLKPWR_PLL1CON_CONNECT ((uint32_t)(0x02)) 277 /** USB PLL control bit mask */ 278 #define CLKPWR_PLL1CON_BITMASK ((uint32_t)(0x03)) 279 280 /*********************************************************************//** 281 * Macro defines for PLL1 Configuration Register 282 **********************************************************************/ 283 /** USB PLL MSEL set value */ 284 #define CLKPWR_PLL1CFG_MSEL(n) ((uint32_t)(n&0x1F)) 285 /** USB PLL PSEL set value */ 286 #define CLKPWR_PLL1CFG_PSEL(n) ((uint32_t)((n&0x03)<<5)) 287 /** USB PLL configuration bit mask */ 288 #define CLKPWR_PLL1CFG_BITMASK ((uint32_t)(0x7F)) 289 290 /*********************************************************************//** 291 * Macro defines for PLL1 Status Register 292 **********************************************************************/ 293 /** USB PLL MSEL get value */ 294 #define CLKPWR_PLL1STAT_MSEL(n) ((uint32_t)(n&0x1F)) 295 /** USB PLL PSEL get value */ 296 #define CLKPWR_PLL1STAT_PSEL(n) ((uint32_t)((n>>5)&0x03)) 297 /** USB PLL status enable bit */ 298 #define CLKPWR_PLL1STAT_PLLE ((uint32_t)(1<<8)) 299 /** USB PLL status Connect bit */ 300 #define CLKPWR_PLL1STAT_PLLC ((uint32_t)(1<<9)) 301 /** USB PLL status lock */ 302 #define CLKPWR_PLL1STAT_PLOCK ((uint32_t)(1<<10)) 303 304 /*********************************************************************//** 305 * Macro defines for PLL1 Feed Register 306 **********************************************************************/ 307 /** PLL1 Feed bit mask */ 308 #define CLKPWR_PLL1FEED_BITMASK ((uint32_t)0xFF) 309 310 /*********************************************************************//** 311 * Macro defines for CPU Clock Configuration Register 312 **********************************************************************/ 313 /** CPU Clock configuration bit mask */ 314 #define CLKPWR_CCLKCFG_BITMASK ((uint32_t)(0xFF)) 315 316 /*********************************************************************//** 317 * Macro defines for USB Clock Configuration Register 318 **********************************************************************/ 319 /** USB Clock Configuration bit mask */ 320 #define CLKPWR_USBCLKCFG_BITMASK ((uint32_t)(0x0F)) 321 322 /*********************************************************************//** 323 * Macro defines for IRC Trim Register 324 **********************************************************************/ 325 /** IRC Trim bit mask */ 326 #define CLKPWR_IRCTRIM_BITMASK ((uint32_t)(0x0F)) 327 328 /*********************************************************************//** 329 * Macro defines for Peripheral Clock Selection Register 0 and 1 330 **********************************************************************/ 331 /** Peripheral Clock Selection 0 mask bit */ 332 #define CLKPWR_PCLKSEL0_BITMASK ((uint32_t)(0xFFF3F3FF)) 333 /** Peripheral Clock Selection 1 mask bit */ 334 #define CLKPWR_PCLKSEL1_BITMASK ((uint32_t)(0xFCF3F0F3)) 335 /** Macro to set peripheral clock of each type 336 * p: position of two bits that hold divider of peripheral clock 337 * n: value of divider of peripheral clock to be set */ 338 #define CLKPWR_PCLKSEL_SET(p,n) _SBF(p,n) 339 /** Macro to mask peripheral clock of each type */ 340 #define CLKPWR_PCLKSEL_BITMASK(p) _SBF(p,0x03) 341 /** Macro to get peripheral clock of each type */ 342 #define CLKPWR_PCLKSEL_GET(p, n) ((uint32_t)((n>>p)&0x03)) 343 344 /*********************************************************************//** 345 * Macro defines for Power Mode Control Register 346 **********************************************************************/ 347 /** Power mode control bit 0 */ 348 #define CLKPWR_PCON_PM0 ((uint32_t)(1<<0)) 349 /** Power mode control bit 1 */ 350 #define CLKPWR_PCON_PM1 ((uint32_t)(1<<1)) 351 /** Brown-Out Reduced Power Mode */ 352 #define CLKPWR_PCON_BODPDM ((uint32_t)(1<<2)) 353 /** Brown-Out Global Disable */ 354 #define CLKPWR_PCON_BOGD ((uint32_t)(1<<3)) 355 /** Brown Out Reset Disable */ 356 #define CLKPWR_PCON_BORD ((uint32_t)(1<<4)) 357 /** Sleep Mode entry flag */ 358 #define CLKPWR_PCON_SMFLAG ((uint32_t)(1<<8)) 359 /** Deep Sleep entry flag */ 360 #define CLKPWR_PCON_DSFLAG ((uint32_t)(1<<9)) 361 /** Power-down entry flag */ 362 #define CLKPWR_PCON_PDFLAG ((uint32_t)(1<<10)) 363 /** Deep Power-down entry flag */ 364 #define CLKPWR_PCON_DPDFLAG ((uint32_t)(1<<11)) 365 366 /*********************************************************************//** 367 * Macro defines for Power Control for Peripheral Register 368 **********************************************************************/ 369 /** Power Control for Peripherals bit mask */ 370 #define CLKPWR_PCONP_BITMASK 0xEFEFF7DE 371 372 /** 373 * @} 374 */ 375 376 377 /* Public Functions ----------------------------------------------------------- */ 378 /** @defgroup CLKPWR_Public_Functions CLKPWR Public Functions 379 * @{ 380 */ 381 382 void CLKPWR_SetPCLKDiv (uint32_t ClkType, uint32_t DivVal); 383 uint32_t CLKPWR_GetPCLKSEL (uint32_t ClkType); 384 uint32_t CLKPWR_GetPCLK (uint32_t ClkType); 385 void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState); 386 void CLKPWR_Sleep(void); 387 void CLKPWR_DeepSleep(void); 388 void CLKPWR_PowerDown(void); 389 void CLKPWR_DeepPowerDown(void); 390 391 /** 392 * @} 393 */ 394 395 396 #ifdef __cplusplus 397 } 398 #endif 399 400 #endif /* LPC17XX_CLKPWR_H_ */ 401 402 /** 403 * @} 404 */ 405 406 /* --------------------------------- End Of File ------------------------------ */