lpc-field

Template project for programming NXP's LPC1768 MCUs
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lpc17xx_emac.h (39819B)


      1 /**********************************************************************
      2 * $Id$		lpc17xx_emac.h				2010-05-21
      3 *//**
      4 * @file		lpc17xx_emac.h
      5 * @brief	Contains all macro definitions and function prototypes
      6 * 			support for Ethernet MAC firmware library on LPC17xx
      7 * @version	2.0
      8 * @date		21. May. 2010
      9 * @author	NXP MCU SW Application Team
     10 *
     11 * Copyright(C) 2010, NXP Semiconductor
     12 * All rights reserved.
     13 *
     14 ***********************************************************************
     15 * Software that is described herein is for illustrative purposes only
     16 * which provides customers with programming information regarding the
     17 * products. This software is supplied "AS IS" without any warranties.
     18 * NXP Semiconductors assumes no responsibility or liability for the
     19 * use of the software, conveys no license or title under any patent,
     20 * copyright, or mask work right to the product. NXP Semiconductors
     21 * reserves the right to make changes in the software without
     22 * notification. NXP Semiconductors also make no representation or
     23 * warranty that such application will be suitable for the specified
     24 * use without further testing or modification.
     25 * Permission to use, copy, modify, and distribute this software and its
     26 * documentation is hereby granted, under NXP Semiconductors'
     27 * relevant copyright in the software, without fee, provided that it
     28 * is used in conjunction with NXP Semiconductors microcontrollers.  This
     29 * copyright, permission, and disclaimer notice must appear in all copies of
     30 * this code.
     31 **********************************************************************/
     32 
     33 /* Peripheral group ----------------------------------------------------------- */
     34 /** @defgroup EMAC EMAC (Ethernet Media Access Controller)
     35  * @ingroup LPC1700CMSIS_FwLib_Drivers
     36  * @{
     37  */
     38 
     39 #ifndef LPC17XX_EMAC_H_
     40 #define LPC17XX_EMAC_H_
     41 
     42 /* Includes ------------------------------------------------------------------- */
     43 #include "LPC17xx.h"
     44 #include "lpc_types.h"
     45 
     46 
     47 #ifdef __cplusplus
     48 extern "C"
     49 {
     50 #endif
     51 
     52 #define MCB_LPC_1768
     53 //#define IAR_LPC_1768
     54 
     55 /* Public Macros -------------------------------------------------------------- */
     56 /** @defgroup EMAC_Public_Macros EMAC Public Macros
     57  * @{
     58  */
     59 
     60 
     61 /* EMAC PHY status type definitions */
     62 #define EMAC_PHY_STAT_LINK			(0)		/**< Link Status */
     63 #define EMAC_PHY_STAT_SPEED			(1)		/**< Speed Status */
     64 #define EMAC_PHY_STAT_DUP			(2)		/**< Duplex Status */
     65 
     66 /* EMAC PHY device Speed definitions */
     67 #define EMAC_MODE_AUTO				(0)		/**< Auto-negotiation mode */
     68 #define EMAC_MODE_10M_FULL			(1)		/**< 10Mbps FullDuplex mode */
     69 #define EMAC_MODE_10M_HALF			(2)		/**< 10Mbps HalfDuplex mode */
     70 #define EMAC_MODE_100M_FULL			(3)		/**< 100Mbps FullDuplex mode */
     71 #define EMAC_MODE_100M_HALF			(4)		/**< 100Mbps HalfDuplex mode */
     72 
     73 /**
     74  * @}
     75  */
     76 /* Private Macros ------------------------------------------------------------- */
     77 /** @defgroup EMAC_Private_Macros EMAC Private Macros
     78  * @{
     79  */
     80 
     81 
     82 /* EMAC Memory Buffer configuration for 16K Ethernet RAM */
     83 #define EMAC_NUM_RX_FRAG         4           /**< Num.of RX Fragments 4*1536= 6.0kB */
     84 #define EMAC_NUM_TX_FRAG         3           /**< Num.of TX Fragments 3*1536= 4.6kB */
     85 #define EMAC_ETH_MAX_FLEN        1536        /**< Max. Ethernet Frame Size          */
     86 #define EMAC_TX_FRAME_TOUT       0x00100000  /**< Frame Transmit timeout count      */
     87 
     88 /* --------------------- BIT DEFINITIONS -------------------------------------- */
     89 /*********************************************************************//**
     90  * Macro defines for MAC Configuration Register 1
     91  **********************************************************************/
     92 #define EMAC_MAC1_REC_EN         0x00000001  /**< Receive Enable                    */
     93 #define EMAC_MAC1_PASS_ALL       0x00000002  /**< Pass All Receive Frames           */
     94 #define EMAC_MAC1_RX_FLOWC       0x00000004  /**< RX Flow Control                   */
     95 #define EMAC_MAC1_TX_FLOWC       0x00000008  /**< TX Flow Control                   */
     96 #define EMAC_MAC1_LOOPB          0x00000010  /**< Loop Back Mode                    */
     97 #define EMAC_MAC1_RES_TX         0x00000100  /**< Reset TX Logic                    */
     98 #define EMAC_MAC1_RES_MCS_TX     0x00000200  /**< Reset MAC TX Control Sublayer     */
     99 #define EMAC_MAC1_RES_RX         0x00000400  /**< Reset RX Logic                    */
    100 #define EMAC_MAC1_RES_MCS_RX     0x00000800  /**< Reset MAC RX Control Sublayer     */
    101 #define EMAC_MAC1_SIM_RES        0x00004000  /**< Simulation Reset                  */
    102 #define EMAC_MAC1_SOFT_RES       0x00008000  /**< Soft Reset MAC                    */
    103 
    104 /*********************************************************************//**
    105  * Macro defines for MAC Configuration Register 2
    106  **********************************************************************/
    107 #define EMAC_MAC2_FULL_DUP       0x00000001  /**< Full-Duplex Mode                  */
    108 #define EMAC_MAC2_FRM_LEN_CHK    0x00000002  /**< Frame Length Checking             */
    109 #define EMAC_MAC2_HUGE_FRM_EN    0x00000004  /**< Huge Frame Enable                 */
    110 #define EMAC_MAC2_DLY_CRC        0x00000008  /**< Delayed CRC Mode                  */
    111 #define EMAC_MAC2_CRC_EN         0x00000010  /**< Append CRC to every Frame         */
    112 #define EMAC_MAC2_PAD_EN         0x00000020  /**< Pad all Short Frames              */
    113 #define EMAC_MAC2_VLAN_PAD_EN    0x00000040  /**< VLAN Pad Enable                   */
    114 #define EMAC_MAC2_ADET_PAD_EN    0x00000080  /**< Auto Detect Pad Enable            */
    115 #define EMAC_MAC2_PPREAM_ENF     0x00000100  /**< Pure Preamble Enforcement         */
    116 #define EMAC_MAC2_LPREAM_ENF     0x00000200  /**< Long Preamble Enforcement         */
    117 #define EMAC_MAC2_NO_BACKOFF     0x00001000  /**< No Backoff Algorithm              */
    118 #define EMAC_MAC2_BACK_PRESSURE  0x00002000  /**< Backoff Presurre / No Backoff     */
    119 #define EMAC_MAC2_EXCESS_DEF     0x00004000  /**< Excess Defer                      */
    120 
    121 /*********************************************************************//**
    122  * Macro defines for Back-to-Back Inter-Packet-Gap Register
    123  **********************************************************************/
    124 /** Programmable field representing the nibble time offset of the minimum possible period
    125  * between the end of any transmitted packet to the beginning of the next */
    126 #define EMAC_IPGT_BBIPG(n)		(n&0x7F)
    127 /** Recommended value for Full Duplex of Programmable field representing the nibble time
    128  * offset of the minimum possible period between the end of any transmitted packet to the
    129  * beginning of the next */
    130 #define EMAC_IPGT_FULL_DUP		(EMAC_IPGT_BBIPG(0x15))
    131 /** Recommended value for Half Duplex of Programmable field representing the nibble time
    132  * offset of the minimum possible period between the end of any transmitted packet to the
    133  * beginning of the next */
    134 #define EMAC_IPGT_HALF_DUP      (EMAC_IPGT_BBIPG(0x12))
    135 
    136 /*********************************************************************//**
    137  * Macro defines for Non Back-to-Back Inter-Packet-Gap Register
    138  **********************************************************************/
    139 /** Programmable field representing the Non-Back-to-Back Inter-Packet-Gap */
    140 #define EMAC_IPGR_NBBIPG_P2(n)	(n&0x7F)
    141 /** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 1 */
    142 #define EMAC_IPGR_P2_DEF		(EMAC_IPGR_NBBIPG_P2(0x12))
    143 /** Programmable field representing the optional carrierSense window referenced in
    144  * IEEE 802.3/4.2.3.2.1 'Carrier Deference' */
    145 #define EMAC_IPGR_NBBIPG_P1(n)	((n&0x7F)<<8)
    146 /** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 2 */
    147 #define EMAC_IPGR_P1_DEF        EMAC_IPGR_NBBIPG_P1(0x0C)
    148 
    149 /*********************************************************************//**
    150  * Macro defines for Collision Window/Retry Register
    151  **********************************************************************/
    152 /** Programmable field specifying the number of retransmission attempts following a collision before
    153  * aborting the packet due to excessive collisions */
    154 #define EMAC_CLRT_MAX_RETX(n)	(n&0x0F)
    155 /** Programmable field representing the slot time or collision window during which collisions occur
    156  * in properly configured networks */
    157 #define EMAC_CLRT_COLL(n)		((n&0x3F)<<8)
    158 /** Default value for Collision Window / Retry register */
    159 #define EMAC_CLRT_DEF           ((EMAC_CLRT_MAX_RETX(0x0F))|(EMAC_CLRT_COLL(0x37)))
    160 
    161 /*********************************************************************//**
    162  * Macro defines for Maximum Frame Register
    163  **********************************************************************/
    164 /** Represents a maximum receive frame of 1536 octets */
    165 #define EMAC_MAXF_MAXFRMLEN(n)	(n&0xFFFF)
    166 
    167 /*********************************************************************//**
    168  * Macro defines for PHY Support Register
    169  **********************************************************************/
    170 #define EMAC_SUPP_SPEED			0x00000100  	/**< Reduced MII Logic Current Speed   */
    171 //#define EMAC_SUPP_RES_RMII      0x00000800  	/**< Reset Reduced MII Logic           */
    172 
    173 /*********************************************************************//**
    174  * Macro defines for Test Register
    175  **********************************************************************/
    176 #define EMAC_TEST_SHCUT_PQUANTA  0x00000001  	/**< Shortcut Pause Quanta             */
    177 #define EMAC_TEST_TST_PAUSE      0x00000002  	/**< Test Pause                        */
    178 #define EMAC_TEST_TST_BACKP      0x00000004  	/**< Test Back Pressure                */
    179 
    180 /*********************************************************************//**
    181  * Macro defines for MII Management Configuration Register
    182  **********************************************************************/
    183 #define EMAC_MCFG_SCAN_INC       0x00000001  	/**< Scan Increment PHY Address        */
    184 #define EMAC_MCFG_SUPP_PREAM     0x00000002  	/**< Suppress Preamble                 */
    185 #define EMAC_MCFG_CLK_SEL(n)     ((n&0x0F)<<2)  /**< Clock Select Field                 */
    186 #define EMAC_MCFG_RES_MII        0x00008000  	/**< Reset MII Management Hardware     */
    187 #define EMAC_MCFG_MII_MAXCLK	 2500000UL		/**< MII Clock max */
    188 
    189 /*********************************************************************//**
    190  * Macro defines for MII Management Command Register
    191  **********************************************************************/
    192 #define EMAC_MCMD_READ           0x00000001  	/**< MII Read                          */
    193 #define EMAC_MCMD_SCAN           0x00000002  	/**< MII Scan continuously             */
    194 
    195 #define EMAC_MII_WR_TOUT         0x00050000  	/**< MII Write timeout count           */
    196 #define EMAC_MII_RD_TOUT         0x00050000  	/**< MII Read timeout count            */
    197 
    198 /*********************************************************************//**
    199  * Macro defines for MII Management Address Register
    200  **********************************************************************/
    201 #define EMAC_MADR_REG_ADR(n)     (n&0x1F)  		/**< MII Register Address field         */
    202 #define EMAC_MADR_PHY_ADR(n)     ((n&0x1F)<<8)  /**< PHY Address Field                  */
    203 
    204 /*********************************************************************//**
    205  * Macro defines for MII Management Write Data Register
    206  **********************************************************************/
    207 #define EMAC_MWTD_DATA(n)		(n&0xFFFF)		/**< Data field for MMI Management Write Data register */
    208 
    209 /*********************************************************************//**
    210  * Macro defines for MII Management Read Data Register
    211  **********************************************************************/
    212 #define EMAC_MRDD_DATA(n)		(n&0xFFFF)		/**< Data field for MMI Management Read Data register */
    213 
    214 /*********************************************************************//**
    215  * Macro defines for MII Management Indicators Register
    216  **********************************************************************/
    217 #define EMAC_MIND_BUSY           0x00000001  	/**< MII is Busy                       */
    218 #define EMAC_MIND_SCAN           0x00000002  	/**< MII Scanning in Progress          */
    219 #define EMAC_MIND_NOT_VAL        0x00000004  	/**< MII Read Data not valid           */
    220 #define EMAC_MIND_MII_LINK_FAIL  0x00000008  	/**< MII Link Failed                   */
    221 
    222 /* Station Address 0 Register */
    223 /* Station Address 1 Register */
    224 /* Station Address 2 Register */
    225 
    226 
    227 /* Control register definitions --------------------------------------------------------------------------- */
    228 /*********************************************************************//**
    229  * Macro defines for Command Register
    230  **********************************************************************/
    231 #define EMAC_CR_RX_EN            0x00000001  	/**< Enable Receive                    */
    232 #define EMAC_CR_TX_EN            0x00000002  	/**< Enable Transmit                   */
    233 #define EMAC_CR_REG_RES          0x00000008  	/**< Reset Host Registers              */
    234 #define EMAC_CR_TX_RES           0x00000010  	/**< Reset Transmit Datapath           */
    235 #define EMAC_CR_RX_RES           0x00000020  	/**< Reset Receive Datapath            */
    236 #define EMAC_CR_PASS_RUNT_FRM    0x00000040  	/**< Pass Runt Frames                  */
    237 #define EMAC_CR_PASS_RX_FILT     0x00000080  	/**< Pass RX Filter                    */
    238 #define EMAC_CR_TX_FLOW_CTRL     0x00000100  	/**< TX Flow Control                   */
    239 #define EMAC_CR_RMII             0x00000200  	/**< Reduced MII Interface             */
    240 #define EMAC_CR_FULL_DUP         0x00000400  	/**< Full Duplex                       */
    241 
    242 /*********************************************************************//**
    243  * Macro defines for Status Register
    244  **********************************************************************/
    245 #define EMAC_SR_RX_EN            0x00000001  	/**< Enable Receive                    */
    246 #define EMAC_SR_TX_EN            0x00000002  	/**< Enable Transmit                   */
    247 
    248 /*********************************************************************//**
    249  * Macro defines for Transmit Status Vector 0 Register
    250  **********************************************************************/
    251 #define EMAC_TSV0_CRC_ERR        0x00000001  /**< CRC error                         */
    252 #define EMAC_TSV0_LEN_CHKERR     0x00000002  /**< Length Check Error                */
    253 #define EMAC_TSV0_LEN_OUTRNG     0x00000004  /**< Length Out of Range               */
    254 #define EMAC_TSV0_DONE           0x00000008  /**< Tramsmission Completed            */
    255 #define EMAC_TSV0_MCAST          0x00000010  /**< Multicast Destination             */
    256 #define EMAC_TSV0_BCAST          0x00000020  /**< Broadcast Destination             */
    257 #define EMAC_TSV0_PKT_DEFER      0x00000040  /**< Packet Deferred                   */
    258 #define EMAC_TSV0_EXC_DEFER      0x00000080  /**< Excessive Packet Deferral         */
    259 #define EMAC_TSV0_EXC_COLL       0x00000100  /**< Excessive Collision               */
    260 #define EMAC_TSV0_LATE_COLL      0x00000200  /**< Late Collision Occured            */
    261 #define EMAC_TSV0_GIANT          0x00000400  /**< Giant Frame                       */
    262 #define EMAC_TSV0_UNDERRUN       0x00000800  /**< Buffer Underrun                   */
    263 #define EMAC_TSV0_BYTES          0x0FFFF000  /**< Total Bytes Transferred           */
    264 #define EMAC_TSV0_CTRL_FRAME     0x10000000  /**< Control Frame                     */
    265 #define EMAC_TSV0_PAUSE          0x20000000  /**< Pause Frame                       */
    266 #define EMAC_TSV0_BACK_PRESS     0x40000000  /**< Backpressure Method Applied       */
    267 #define EMAC_TSV0_VLAN           0x80000000  /**< VLAN Frame                        */
    268 
    269 /*********************************************************************//**
    270  * Macro defines for Transmit Status Vector 1 Register
    271  **********************************************************************/
    272 #define EMAC_TSV1_BYTE_CNT       0x0000FFFF  /**< Transmit Byte Count               */
    273 #define EMAC_TSV1_COLL_CNT       0x000F0000  /**< Transmit Collision Count          */
    274 
    275 /*********************************************************************//**
    276  * Macro defines for Receive Status Vector Register
    277  **********************************************************************/
    278 #define EMAC_RSV_BYTE_CNT        0x0000FFFF  /**< Receive Byte Count                */
    279 #define EMAC_RSV_PKT_IGNORED     0x00010000  /**< Packet Previously Ignored         */
    280 #define EMAC_RSV_RXDV_SEEN       0x00020000  /**< RXDV Event Previously Seen        */
    281 #define EMAC_RSV_CARR_SEEN       0x00040000  /**< Carrier Event Previously Seen     */
    282 #define EMAC_RSV_REC_CODEV       0x00080000  /**< Receive Code Violation            */
    283 #define EMAC_RSV_CRC_ERR         0x00100000  /**< CRC Error                         */
    284 #define EMAC_RSV_LEN_CHKERR      0x00200000  /**< Length Check Error                */
    285 #define EMAC_RSV_LEN_OUTRNG      0x00400000  /**< Length Out of Range               */
    286 #define EMAC_RSV_REC_OK          0x00800000  /**< Frame Received OK                 */
    287 #define EMAC_RSV_MCAST           0x01000000  /**< Multicast Frame                   */
    288 #define EMAC_RSV_BCAST           0x02000000  /**< Broadcast Frame                   */
    289 #define EMAC_RSV_DRIB_NIBB       0x04000000  /**< Dribble Nibble                    */
    290 #define EMAC_RSV_CTRL_FRAME      0x08000000  /**< Control Frame                     */
    291 #define EMAC_RSV_PAUSE           0x10000000  /**< Pause Frame                       */
    292 #define EMAC_RSV_UNSUPP_OPC      0x20000000  /**< Unsupported Opcode                */
    293 #define EMAC_RSV_VLAN            0x40000000  /**< VLAN Frame                        */
    294 
    295 /*********************************************************************//**
    296  * Macro defines for Flow Control Counter Register
    297  **********************************************************************/
    298 #define EMAC_FCC_MIRR_CNT(n)        	(n&0xFFFF)  		/**< Mirror Counter                    */
    299 #define EMAC_FCC_PAUSE_TIM(n)       	((n&0xFFFF)<<16)  	/**< Pause Timer                       */
    300 
    301 /*********************************************************************//**
    302  * Macro defines for Flow Control Status Register
    303  **********************************************************************/
    304 #define EMAC_FCS_MIRR_CNT(n)        	(n&0xFFFF)  		/**< Mirror Counter Current            */
    305 
    306 
    307 /* Receive filter register definitions -------------------------------------------------------- */
    308 /*********************************************************************//**
    309  * Macro defines for Receive Filter Control Register
    310  **********************************************************************/
    311 #define EMAC_RFC_UCAST_EN        0x00000001  /**< Accept Unicast Frames Enable      */
    312 #define EMAC_RFC_BCAST_EN        0x00000002  /**< Accept Broadcast Frames Enable    */
    313 #define EMAC_RFC_MCAST_EN        0x00000004  /**< Accept Multicast Frames Enable    */
    314 #define EMAC_RFC_UCAST_HASH_EN   0x00000008  /**< Accept Unicast Hash Filter Frames */
    315 #define EMAC_RFC_MCAST_HASH_EN   0x00000010  /**< Accept Multicast Hash Filter Fram.*/
    316 #define EMAC_RFC_PERFECT_EN      0x00000020  /**< Accept Perfect Match Enable       */
    317 #define EMAC_RFC_MAGP_WOL_EN     0x00001000  /**< Magic Packet Filter WoL Enable    */
    318 #define EMAC_RFC_PFILT_WOL_EN    0x00002000  /**< Perfect Filter WoL Enable         */
    319 
    320 /*********************************************************************//**
    321  * Macro defines for Receive Filter WoL Status/Clear Registers
    322  **********************************************************************/
    323 #define EMAC_WOL_UCAST           0x00000001  /**< Unicast Frame caused WoL          */
    324 #define EMAC_WOL_BCAST           0x00000002  /**< Broadcast Frame caused WoL        */
    325 #define EMAC_WOL_MCAST           0x00000004  /**< Multicast Frame caused WoL        */
    326 #define EMAC_WOL_UCAST_HASH      0x00000008  /**< Unicast Hash Filter Frame WoL     */
    327 #define EMAC_WOL_MCAST_HASH      0x00000010  /**< Multicast Hash Filter Frame WoL   */
    328 #define EMAC_WOL_PERFECT         0x00000020  /**< Perfect Filter WoL                */
    329 #define EMAC_WOL_RX_FILTER       0x00000080  /**< RX Filter caused WoL              */
    330 #define EMAC_WOL_MAG_PACKET      0x00000100  /**< Magic Packet Filter caused WoL    */
    331 #define EMAC_WOL_BITMASK		 0x01BF		/**< Receive Filter WoL Status/Clear bitmasl value */
    332 
    333 
    334 /* Module control register definitions ---------------------------------------------------- */
    335 /*********************************************************************//**
    336  * Macro defines for Interrupt Status/Enable/Clear/Set Registers
    337  **********************************************************************/
    338 #define EMAC_INT_RX_OVERRUN      0x00000001  /**< Overrun Error in RX Queue         */
    339 #define EMAC_INT_RX_ERR          0x00000002  /**< Receive Error                     */
    340 #define EMAC_INT_RX_FIN          0x00000004  /**< RX Finished Process Descriptors   */
    341 #define EMAC_INT_RX_DONE         0x00000008  /**< Receive Done                      */
    342 #define EMAC_INT_TX_UNDERRUN     0x00000010  /**< Transmit Underrun                 */
    343 #define EMAC_INT_TX_ERR          0x00000020  /**< Transmit Error                    */
    344 #define EMAC_INT_TX_FIN          0x00000040  /**< TX Finished Process Descriptors   */
    345 #define EMAC_INT_TX_DONE         0x00000080  /**< Transmit Done                     */
    346 #define EMAC_INT_SOFT_INT        0x00001000  /**< Software Triggered Interrupt      */
    347 #define EMAC_INT_WAKEUP          0x00002000  /**< Wakeup Event Interrupt            */
    348 
    349 /*********************************************************************//**
    350  * Macro defines for Power Down Register
    351  **********************************************************************/
    352 #define EMAC_PD_POWER_DOWN       0x80000000  /**< Power Down MAC                    */
    353 
    354 /* Descriptor and status formats ---------------------------------------------------- */
    355 /*********************************************************************//**
    356  * Macro defines for RX Descriptor Control Word
    357  **********************************************************************/
    358 #define EMAC_RCTRL_SIZE(n)       (n&0x7FF)  	/**< Buffer size field                  */
    359 #define EMAC_RCTRL_INT           0x80000000  	/**< Generate RxDone Interrupt         */
    360 
    361 /*********************************************************************//**
    362  * Macro defines for RX Status Hash CRC Word
    363  **********************************************************************/
    364 #define EMAC_RHASH_SA            0x000001FF  	/**< Hash CRC for Source Address       */
    365 #define EMAC_RHASH_DA            0x001FF000  	/**< Hash CRC for Destination Address  */
    366 
    367 /*********************************************************************//**
    368  * Macro defines for RX Status Information Word
    369  **********************************************************************/
    370 #define EMAC_RINFO_SIZE          0x000007FF  /**< Data size in bytes                */
    371 #define EMAC_RINFO_CTRL_FRAME    0x00040000  /**< Control Frame                     */
    372 #define EMAC_RINFO_VLAN          0x00080000  /**< VLAN Frame                        */
    373 #define EMAC_RINFO_FAIL_FILT     0x00100000  /**< RX Filter Failed                  */
    374 #define EMAC_RINFO_MCAST         0x00200000  /**< Multicast Frame                   */
    375 #define EMAC_RINFO_BCAST         0x00400000  /**< Broadcast Frame                   */
    376 #define EMAC_RINFO_CRC_ERR       0x00800000  /**< CRC Error in Frame                */
    377 #define EMAC_RINFO_SYM_ERR       0x01000000  /**< Symbol Error from PHY             */
    378 #define EMAC_RINFO_LEN_ERR       0x02000000  /**< Length Error                      */
    379 #define EMAC_RINFO_RANGE_ERR     0x04000000  /**< Range Error (exceeded max. size)  */
    380 #define EMAC_RINFO_ALIGN_ERR     0x08000000  /**< Alignment Error                   */
    381 #define EMAC_RINFO_OVERRUN       0x10000000  /**< Receive overrun                   */
    382 #define EMAC_RINFO_NO_DESCR      0x20000000  /**< No new Descriptor available       */
    383 #define EMAC_RINFO_LAST_FLAG     0x40000000  /**< Last Fragment in Frame            */
    384 #define EMAC_RINFO_ERR           0x80000000  /**< Error Occured (OR of all errors)  */
    385 #define EMAC_RINFO_ERR_MASK     (EMAC_RINFO_FAIL_FILT | EMAC_RINFO_CRC_ERR   | EMAC_RINFO_SYM_ERR | \
    386 EMAC_RINFO_LEN_ERR   | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN)
    387 
    388 /*********************************************************************//**
    389  * Macro defines for TX Descriptor Control Word
    390  **********************************************************************/
    391 #define EMAC_TCTRL_SIZE          0x000007FF  /**< Size of data buffer in bytes      */
    392 #define EMAC_TCTRL_OVERRIDE      0x04000000  /**< Override Default MAC Registers    */
    393 #define EMAC_TCTRL_HUGE          0x08000000  /**< Enable Huge Frame                 */
    394 #define EMAC_TCTRL_PAD           0x10000000  /**< Pad short Frames to 64 bytes      */
    395 #define EMAC_TCTRL_CRC           0x20000000  /**< Append a hardware CRC to Frame    */
    396 #define EMAC_TCTRL_LAST          0x40000000  /**< Last Descriptor for TX Frame      */
    397 #define EMAC_TCTRL_INT           0x80000000  /**< Generate TxDone Interrupt         */
    398 
    399 /*********************************************************************//**
    400  * Macro defines for TX Status Information Word
    401  **********************************************************************/
    402 #define EMAC_TINFO_COL_CNT       0x01E00000  /**< Collision Count                   */
    403 #define EMAC_TINFO_DEFER         0x02000000  /**< Packet Deferred (not an error)    */
    404 #define EMAC_TINFO_EXCESS_DEF    0x04000000  /**< Excessive Deferral                */
    405 #define EMAC_TINFO_EXCESS_COL    0x08000000  /**< Excessive Collision               */
    406 #define EMAC_TINFO_LATE_COL      0x10000000  /**< Late Collision Occured            */
    407 #define EMAC_TINFO_UNDERRUN      0x20000000  /**< Transmit Underrun                 */
    408 #define EMAC_TINFO_NO_DESCR      0x40000000  /**< No new Descriptor available       */
    409 #define EMAC_TINFO_ERR           0x80000000  /**< Error Occured (OR of all errors)  */
    410 
    411 #ifdef MCB_LPC_1768
    412 /* DP83848C PHY definition ------------------------------------------------------------ */
    413 
    414 /** PHY device reset time out definition */
    415 #define EMAC_PHY_RESP_TOUT		0x100000UL
    416 
    417 /* ENET Device Revision ID */
    418 #define EMAC_OLD_EMAC_MODULE_ID  0x39022000  /**< Rev. ID for first rev '-'         */
    419 
    420 /*********************************************************************//**
    421  * Macro defines for DP83848C PHY Registers
    422  **********************************************************************/
    423 #define EMAC_PHY_REG_BMCR        0x00        /**< Basic Mode Control Register       */
    424 #define EMAC_PHY_REG_BMSR        0x01        /**< Basic Mode Status Register        */
    425 #define EMAC_PHY_REG_IDR1        0x02        /**< PHY Identifier 1                  */
    426 #define EMAC_PHY_REG_IDR2        0x03        /**< PHY Identifier 2                  */
    427 #define EMAC_PHY_REG_ANAR        0x04        /**< Auto-Negotiation Advertisement    */
    428 #define EMAC_PHY_REG_ANLPAR      0x05        /**< Auto-Neg. Link Partner Abitily    */
    429 #define EMAC_PHY_REG_ANER        0x06        /**< Auto-Neg. Expansion Register      */
    430 #define EMAC_PHY_REG_ANNPTR      0x07        /**< Auto-Neg. Next Page TX            */
    431 #define EMAC_PHY_REG_LPNPA		 0x08
    432 
    433 /*********************************************************************//**
    434  * Macro defines for PHY Extended Registers
    435  **********************************************************************/
    436 #define EMAC_PHY_REG_STS         0x10        /**< Status Register                   */
    437 #define EMAC_PHY_REG_MICR        0x11        /**< MII Interrupt Control Register    */
    438 #define EMAC_PHY_REG_MISR        0x12        /**< MII Interrupt Status Register     */
    439 #define EMAC_PHY_REG_FCSCR       0x14        /**< False Carrier Sense Counter       */
    440 #define EMAC_PHY_REG_RECR        0x15        /**< Receive Error Counter             */
    441 #define EMAC_PHY_REG_PCSR        0x16        /**< PCS Sublayer Config. and Status   */
    442 #define EMAC_PHY_REG_RBR         0x17        /**< RMII and Bypass Register          */
    443 #define EMAC_PHY_REG_LEDCR       0x18        /**< LED Direct Control Register       */
    444 #define EMAC_PHY_REG_PHYCR       0x19        /**< PHY Control Register              */
    445 #define EMAC_PHY_REG_10BTSCR     0x1A        /**< 10Base-T Status/Control Register  */
    446 #define EMAC_PHY_REG_CDCTRL1     0x1B        /**< CD Test Control and BIST Extens.  */
    447 #define EMAC_PHY_REG_EDCR        0x1D        /**< Energy Detect Control Register    */
    448 
    449 /*********************************************************************//**
    450  * Macro defines for PHY Basic Mode Control Register
    451  **********************************************************************/
    452 #define EMAC_PHY_BMCR_RESET     			(1<<15)		/**< Reset bit */
    453 #define EMAC_PHY_BMCR_LOOPBACK      		(1<<14)		/**< Loop back */
    454 #define EMAC_PHY_BMCR_SPEED_SEL     		(1<<13)		/**< Speed selection */
    455 #define EMAC_PHY_BMCR_AN					(1<<12)		/**< Auto Negotiation */
    456 #define EMAC_PHY_BMCR_POWERDOWN				(1<<11)		/**< Power down mode */
    457 #define EMAC_PHY_BMCR_ISOLATE				(1<<10)		/**< Isolate */
    458 #define EMAC_PHY_BMCR_RE_AN					(1<<9)		/**< Restart auto negotiation */
    459 #define EMAC_PHY_BMCR_DUPLEX				(1<<8)		/**< Duplex mode */
    460 
    461 /*********************************************************************//**
    462  * Macro defines for PHY Basic Mode Status Status Register
    463  **********************************************************************/
    464 #define EMAC_PHY_BMSR_100BE_T4        	   	(1<<15)		/**< 100 base T4 */
    465 #define EMAC_PHY_BMSR_100TX_FULL			(1<<14)		/**< 100 base full duplex */
    466 #define EMAC_PHY_BMSR_100TX_HALF			(1<<13)		/**< 100 base half duplex */
    467 #define EMAC_PHY_BMSR_10BE_FULL				(1<<12)		/**< 10 base T full duplex */
    468 #define EMAC_PHY_BMSR_10BE_HALF				(1<<11)		/**< 10 base T half duplex */
    469 #define EMAC_PHY_BMSR_NOPREAM				(1<<6)		/**< MF Preamable Supress */
    470 #define EMAC_PHY_BMSR_AUTO_DONE				(1<<5)		/**< Auto negotiation complete */
    471 #define EMAC_PHY_BMSR_REMOTE_FAULT			(1<<4)		/**< Remote fault */
    472 #define EMAC_PHY_BMSR_NO_AUTO				(1<<3)		/**< Auto Negotiation ability */
    473 #define EMAC_PHY_BMSR_LINK_ESTABLISHED		(1<<2)		/**< Link status */
    474 
    475 /*********************************************************************//**
    476  * Macro defines for PHY Status Register
    477  **********************************************************************/
    478 #define EMAC_PHY_SR_REMOTE_FAULT   			(1<<6)		/**< Remote Fault */
    479 #define EMAC_PHY_SR_JABBER					(1<<5)		/**< Jabber detect */
    480 #define EMAC_PHY_SR_AUTO_DONE				(1<<4)		/**< Auto Negotiation complete */
    481 #define EMAC_PHY_SR_LOOPBACK				(1<<3)		/**< Loop back status */
    482 #define EMAC_PHY_SR_DUP						(1<<2)		/**< Duplex status */
    483 #define EMAC_PHY_SR_SPEED					(1<<1)		/**< Speed status */
    484 #define EMAC_PHY_SR_LINK					(1<<0)		/**< Link Status */
    485 
    486 #define EMAC_PHY_FULLD_100M      0x2100      /**< Full Duplex 100Mbit               */
    487 #define EMAC_PHY_HALFD_100M      0x2000      /**< Half Duplex 100Mbit               */
    488 #define EMAC_PHY_FULLD_10M       0x0100      /**< Full Duplex 10Mbit                */
    489 #define EMAC_PHY_HALFD_10M       0x0000      /**< Half Duplex 10MBit                */
    490 #define EMAC_PHY_AUTO_NEG        0x3000      /**< Select Auto Negotiation           */
    491 
    492 #define EMAC_DEF_ADR    0x0100      /**< Default PHY device address        */
    493 #define EMAC_DP83848C_ID         0x20005C90  /**< PHY Identifier                    */
    494 
    495 #define EMAC_PHY_SR_100_SPEED		((1<<14)|(1<<13))
    496 #define EMAC_PHY_SR_FULL_DUP		((1<<14)|(1<<12))
    497 #define EMAC_PHY_BMSR_LINK_STATUS			(1<<2)		/**< Link status */
    498 
    499 #elif defined(IAR_LPC_1768)
    500 /* KSZ8721BL PHY definition ------------------------------------------------------------ */
    501 /** PHY device reset time out definition */
    502 #define EMAC_PHY_RESP_TOUT		0x100000UL
    503 
    504 /* ENET Device Revision ID */
    505 #define EMAC_OLD_EMAC_MODULE_ID  0x39022000  /**< Rev. ID for first rev '-'         */
    506 
    507 /*********************************************************************//**
    508  * Macro defines for KSZ8721BL PHY Registers
    509  **********************************************************************/
    510 #define EMAC_PHY_REG_BMCR        0x00        /**< Basic Mode Control Register       */
    511 #define EMAC_PHY_REG_BMSR        0x01        /**< Basic Mode Status Register        */
    512 #define EMAC_PHY_REG_IDR1        0x02        /**< PHY Identifier 1                  */
    513 #define EMAC_PHY_REG_IDR2        0x03        /**< PHY Identifier 2                  */
    514 #define EMAC_PHY_REG_ANAR        0x04        /**< Auto-Negotiation Advertisement    */
    515 #define EMAC_PHY_REG_ANLPAR      0x05        /**< Auto-Neg. Link Partner Abitily    */
    516 #define EMAC_PHY_REG_ANER        0x06        /**< Auto-Neg. Expansion Register      */
    517 #define EMAC_PHY_REG_ANNPTR      0x07        /**< Auto-Neg. Next Page TX            */
    518 #define EMAC_PHY_REG_LPNPA		 0x08		 /**< Link Partner Next Page Ability    */
    519 #define EMAC_PHY_REG_REC		 0x15		 /**< RXError Counter Register			*/
    520 #define EMAC_PHY_REG_ISC		 0x1b		 /**< Interrupt Control/Status Register */
    521 #define EMAC_PHY_REG_100BASE	 0x1f		 /**< 100BASE-TX PHY Control Register   */
    522 
    523 /*********************************************************************//**
    524  * Macro defines for PHY Basic Mode Control Register
    525  **********************************************************************/
    526 #define EMAC_PHY_BMCR_RESET     			(1<<15)		/**< Reset bit */
    527 #define EMAC_PHY_BMCR_LOOPBACK      		(1<<14)		/**< Loop back */
    528 #define EMAC_PHY_BMCR_SPEED_SEL     		(1<<13)		/**< Speed selection */
    529 #define EMAC_PHY_BMCR_AN					(1<<12)		/**< Auto Negotiation */
    530 #define EMAC_PHY_BMCR_POWERDOWN				(1<<11)		/**< Power down mode */
    531 #define EMAC_PHY_BMCR_ISOLATE				(1<<10)		/**< Isolate */
    532 #define EMAC_PHY_BMCR_RE_AN					(1<<9)		/**< Restart auto negotiation */
    533 #define EMAC_PHY_BMCR_DUPLEX				(1<<8)		/**< Duplex mode */
    534 #define EMAC_PHY_BMCR_COLLISION				(1<<7)		/**< Collision test */
    535 #define EMAC_PHY_BMCR_TXDIS					(1<<0)		/**< Disable transmit */
    536 
    537 /*********************************************************************//**
    538  * Macro defines for PHY Basic Mode Status Register
    539  **********************************************************************/
    540 #define EMAC_PHY_BMSR_100BE_T4        	   	(1<<15)		/**< 100 base T4 */
    541 #define EMAC_PHY_BMSR_100TX_FULL			(1<<14)		/**< 100 base full duplex */
    542 #define EMAC_PHY_BMSR_100TX_HALF			(1<<13)		/**< 100 base half duplex */
    543 #define EMAC_PHY_BMSR_10BE_FULL				(1<<12)		/**< 10 base T full duplex */
    544 #define EMAC_PHY_BMSR_10BE_HALF				(1<<11)		/**< 10 base T half duplex */
    545 #define EMAC_PHY_BMSR_NOPREAM				(1<<6)		/**< MF Preamable Supress */
    546 #define EMAC_PHY_BMSR_AUTO_DONE				(1<<5)		/**< Auto negotiation complete */
    547 #define EMAC_PHY_BMSR_REMOTE_FAULT			(1<<4)		/**< Remote fault */
    548 #define EMAC_PHY_BMSR_NO_AUTO				(1<<3)		/**< Auto Negotiation ability */
    549 #define EMAC_PHY_BMSR_LINK_STATUS			(1<<2)		/**< Link status */
    550 #define EMAC_PHY_BMSR_JABBER_DETECT			(1<<1)		/**< Jabber detect */
    551 #define EMAC_PHY_BMSR_EXTEND				(1<<0)		/**< Extended support */
    552 
    553 /*********************************************************************//**
    554  * Macro defines for PHY Identifier
    555  **********************************************************************/
    556 /* PHY Identifier 1 bitmap definitions */
    557 #define EMAC_PHY_IDR1(n)		(n & 0xFFFF)		/**< PHY ID1 Number */
    558 
    559 /* PHY Identifier 2 bitmap definitions */
    560 #define EMAC_PHY_IDR2(n)		(n & 0xFFFF)		/**< PHY ID2 Number */
    561 
    562 /*********************************************************************//**
    563  * Macro defines for Auto-Negotiation Advertisement
    564  **********************************************************************/
    565 #define EMAC_PHY_AN_NEXTPAGE					(1<<15)		/**<  Next page capable */
    566 #define EMAC_PHY_AN_REMOTE_FAULT				(1<<13)		/**< Remote Fault support */
    567 #define EMAC_PHY_AN_PAUSE						(1<<10)		/**< Pause support */
    568 #define EMAC_PHY_AN_100BASE_T4					(1<<9)		/**< T4 capable */
    569 #define EMAC_PHY_AN_100BASE_TX_FD				(1<<8)		/**< TX with Full-duplex capable */
    570 #define EMAC_PHY_AN_100BASE_TX					(1<<7)		/**< TX capable */
    571 #define EMAC_PHY_AN_10BASE_T_FD					(1<<6)		/**< 10Mbps with full-duplex capable */
    572 #define EMAC_PHY_AN_10BASE_T					(1<<5)		/**< 10Mbps capable */
    573 #define EMAC_PHY_AN_FIELD(n)					(n & 0x1F)  /**< Selector Field */
    574 
    575 #define EMAC_PHY_FULLD_100M      0x2100      /**< Full Duplex 100Mbit               */
    576 #define EMAC_PHY_HALFD_100M      0x2000      /**< Half Duplex 100Mbit               */
    577 #define EMAC_PHY_FULLD_10M       0x0100      /**< Full Duplex 10Mbit                */
    578 #define EMAC_PHY_HALFD_10M       0x0000      /**< Half Duplex 10MBit                */
    579 #define EMAC_PHY_AUTO_NEG        0x3000      /**< Select Auto Negotiation           */
    580 
    581 #define EMAC_PHY_SR_100_SPEED		((1<<14)|(1<<13))
    582 #define EMAC_PHY_SR_FULL_DUP		((1<<14)|(1<<12))
    583 
    584 #define EMAC_DEF_ADR    (0x01<<8)		/**< Default PHY device address        */
    585 #define EMAC_KSZ8721BL_ID 	((0x22 << 16) | 0x1619 ) /**< PHY Identifier */
    586 #endif
    587 
    588 /**
    589  * @}
    590  */
    591 
    592 
    593 /* Public Types --------------------------------------------------------------- */
    594 /** @defgroup EMAC_Public_Types EMAC Public Types
    595  * @{
    596  */
    597 
    598 /* Descriptor and status formats ---------------------------------------------- */
    599 
    600 /**
    601  * @brief RX Descriptor structure type definition
    602  */
    603 typedef struct {
    604 	uint32_t Packet;	/**< Receive Packet Descriptor */
    605 	uint32_t Ctrl;		/**< Receive Control Descriptor */
    606 } RX_Desc;
    607 
    608 /**
    609  * @brief RX Status structure type definition
    610  */
    611 typedef struct {
    612 	uint32_t Info;		/**< Receive Information Status */
    613 	uint32_t HashCRC;	/**< Receive Hash CRC Status */
    614 } RX_Stat;
    615 
    616 /**
    617  * @brief TX Descriptor structure type definition
    618  */
    619 typedef struct {
    620 	uint32_t Packet;	/**< Transmit Packet Descriptor */
    621 	uint32_t Ctrl;		/**< Transmit Control Descriptor */
    622 } TX_Desc;
    623 
    624 /**
    625  * @brief TX Status structure type definition
    626  */
    627 typedef struct {
    628    uint32_t Info;		/**< Transmit Information Status */
    629 } TX_Stat;
    630 
    631 
    632 /**
    633  * @brief TX Data Buffer structure definition
    634  */
    635 typedef struct {
    636 	uint32_t ulDataLen;			/**< Data length */
    637 	uint32_t *pbDataBuf;		/**< A word-align data pointer to data buffer */
    638 } EMAC_PACKETBUF_Type;
    639 
    640 /**
    641  * @brief EMAC configuration structure definition
    642  */
    643 typedef struct {
    644 	uint32_t	Mode;						/**< Supported EMAC PHY device speed, should be one of the following:
    645 											- EMAC_MODE_AUTO
    646 											- EMAC_MODE_10M_FULL
    647 											- EMAC_MODE_10M_HALF
    648 											- EMAC_MODE_100M_FULL
    649 											- EMAC_MODE_100M_HALF
    650 											*/
    651 	uint8_t 	*pbEMAC_Addr;				/**< Pointer to EMAC Station address that contains 6-bytes
    652 											of MAC address, it must be sorted in order (bEMAC_Addr[0]..[5])
    653 											*/
    654 } EMAC_CFG_Type;
    655 
    656 
    657 /**
    658  * @}
    659  */
    660 
    661 
    662 /* Public Functions ----------------------------------------------------------- */
    663 /** @defgroup EMAC_Public_Functions EMAC Public Functions
    664  * @{
    665  */
    666 /* Init/DeInit EMAC peripheral */
    667 Status EMAC_Init(EMAC_CFG_Type *EMAC_ConfigStruct);
    668 void EMAC_DeInit(void);
    669 
    670 /* PHY functions --------------*/
    671 int32_t EMAC_CheckPHYStatus(uint32_t ulPHYState);
    672 int32_t EMAC_SetPHYMode(uint32_t ulPHYMode);
    673 int32_t EMAC_UpdatePHYStatus(void);
    674 
    675 /* Filter functions ----------*/
    676 void EMAC_SetHashFilter(uint8_t dstMAC_addr[], FunctionalState NewState);
    677 void EMAC_SetFilterMode(uint32_t ulFilterMode, FunctionalState NewState);
    678 
    679 /* EMAC Packet Buffer functions */
    680 void EMAC_WritePacketBuffer(EMAC_PACKETBUF_Type *pDataStruct);
    681 void EMAC_ReadPacketBuffer(EMAC_PACKETBUF_Type *pDataStruct);
    682 
    683 /* EMAC Interrupt functions -------*/
    684 void EMAC_IntCmd(uint32_t ulIntType, FunctionalState NewState);
    685 IntStatus EMAC_IntGetStatus(uint32_t ulIntType);
    686 
    687 /* EMAC Index functions -----------*/
    688 Bool EMAC_CheckReceiveIndex(void);
    689 Bool EMAC_CheckTransmitIndex(void);
    690 void EMAC_UpdateRxConsumeIndex(void);
    691 void EMAC_UpdateTxProduceIndex(void);
    692 
    693 FlagStatus EMAC_CheckReceiveDataStatus(uint32_t ulRxStatType);
    694 uint32_t EMAC_GetReceiveDataSize(void);
    695 FlagStatus EMAC_GetWoLStatus(uint32_t ulWoLMode);
    696 
    697 /**
    698  * @}
    699  */
    700 
    701 #ifdef __cplusplus
    702 }
    703 #endif
    704 
    705 #endif /* LPC17XX_EMAC_H_ */
    706 
    707 /**
    708  * @}
    709  */
    710 
    711 /* --------------------------------- End Of File ------------------------------ */