lpc17xx_gpdma.h (19615B)
1 /********************************************************************** 2 * $Id$ lpc17xx_gpdma.h 2010-05-21 3 *//** 4 * @file lpc17xx_gpdma.h 5 * @brief Contains all macro definitions and function prototypes 6 * support for GPDMA firmware library on LPC17xx 7 * @version 2.0 8 * @date 21. May. 2010 9 * @author NXP MCU SW Application Team 10 * 11 * Copyright(C) 2010, NXP Semiconductor 12 * All rights reserved. 13 * 14 *********************************************************************** 15 * Software that is described herein is for illustrative purposes only 16 * which provides customers with programming information regarding the 17 * products. This software is supplied "AS IS" without any warranties. 18 * NXP Semiconductors assumes no responsibility or liability for the 19 * use of the software, conveys no license or title under any patent, 20 * copyright, or mask work right to the product. NXP Semiconductors 21 * reserves the right to make changes in the software without 22 * notification. NXP Semiconductors also make no representation or 23 * warranty that such application will be suitable for the specified 24 * use without further testing or modification. 25 * Permission to use, copy, modify, and distribute this software and its 26 * documentation is hereby granted, under NXP Semiconductors' 27 * relevant copyright in the software, without fee, provided that it 28 * is used in conjunction with NXP Semiconductors microcontrollers. This 29 * copyright, permission, and disclaimer notice must appear in all copies of 30 * this code. 31 **********************************************************************/ 32 33 /* Peripheral group ----------------------------------------------------------- */ 34 /** @defgroup GPDMA GPDMA (General Purpose Direct Memory Access) 35 * @ingroup LPC1700CMSIS_FwLib_Drivers 36 * @{ 37 */ 38 39 #ifndef LPC17XX_GPDMA_H_ 40 #define LPC17XX_GPDMA_H_ 41 42 /* Includes ------------------------------------------------------------------- */ 43 #include "LPC17xx.h" 44 #include "lpc_types.h" 45 46 47 #ifdef __cplusplus 48 extern "C" 49 { 50 #endif 51 52 /* Public Macros -------------------------------------------------------------- */ 53 /** @defgroup GPDMA_Public_Macros GPDMA Public Macros 54 * @{ 55 */ 56 57 /** DMA Connection number definitions */ 58 #define GPDMA_CONN_SSP0_Tx ((0UL)) /**< SSP0 Tx */ 59 #define GPDMA_CONN_SSP0_Rx ((1UL)) /**< SSP0 Rx */ 60 #define GPDMA_CONN_SSP1_Tx ((2UL)) /**< SSP1 Tx */ 61 #define GPDMA_CONN_SSP1_Rx ((3UL)) /**< SSP1 Rx */ 62 #define GPDMA_CONN_ADC ((4UL)) /**< ADC */ 63 #define GPDMA_CONN_I2S_Channel_0 ((5UL)) /**< I2S channel 0 */ 64 #define GPDMA_CONN_I2S_Channel_1 ((6UL)) /**< I2S channel 1 */ 65 #define GPDMA_CONN_DAC ((7UL)) /**< DAC */ 66 #define GPDMA_CONN_UART0_Tx ((8UL)) /**< UART0 Tx */ 67 #define GPDMA_CONN_UART0_Rx ((9UL)) /**< UART0 Rx */ 68 #define GPDMA_CONN_UART1_Tx ((10UL)) /**< UART1 Tx */ 69 #define GPDMA_CONN_UART1_Rx ((11UL)) /**< UART1 Rx */ 70 #define GPDMA_CONN_UART2_Tx ((12UL)) /**< UART2 Tx */ 71 #define GPDMA_CONN_UART2_Rx ((13UL)) /**< UART2 Rx */ 72 #define GPDMA_CONN_UART3_Tx ((14UL)) /**< UART3 Tx */ 73 #define GPDMA_CONN_UART3_Rx ((15UL)) /**< UART3 Rx */ 74 #define GPDMA_CONN_MAT0_0 ((16UL)) /**< MAT0.0 */ 75 #define GPDMA_CONN_MAT0_1 ((17UL)) /**< MAT0.1 */ 76 #define GPDMA_CONN_MAT1_0 ((18UL)) /**< MAT1.0 */ 77 #define GPDMA_CONN_MAT1_1 ((19UL)) /**< MAT1.1 */ 78 #define GPDMA_CONN_MAT2_0 ((20UL)) /**< MAT2.0 */ 79 #define GPDMA_CONN_MAT2_1 ((21UL)) /**< MAT2.1 */ 80 #define GPDMA_CONN_MAT3_0 ((22UL)) /**< MAT3.0 */ 81 #define GPDMA_CONN_MAT3_1 ((23UL)) /**< MAT3.1 */ 82 83 /** GPDMA Transfer type definitions */ 84 #define GPDMA_TRANSFERTYPE_M2M ((0UL)) /**< Memory to memory - DMA control */ 85 #define GPDMA_TRANSFERTYPE_M2P ((1UL)) /**< Memory to peripheral - DMA control */ 86 #define GPDMA_TRANSFERTYPE_P2M ((2UL)) /**< Peripheral to memory - DMA control */ 87 #define GPDMA_TRANSFERTYPE_P2P ((3UL)) /**< Source peripheral to destination peripheral - DMA control */ 88 89 /** Burst size in Source and Destination definitions */ 90 #define GPDMA_BSIZE_1 ((0UL)) /**< Burst size = 1 */ 91 #define GPDMA_BSIZE_4 ((1UL)) /**< Burst size = 4 */ 92 #define GPDMA_BSIZE_8 ((2UL)) /**< Burst size = 8 */ 93 #define GPDMA_BSIZE_16 ((3UL)) /**< Burst size = 16 */ 94 #define GPDMA_BSIZE_32 ((4UL)) /**< Burst size = 32 */ 95 #define GPDMA_BSIZE_64 ((5UL)) /**< Burst size = 64 */ 96 #define GPDMA_BSIZE_128 ((6UL)) /**< Burst size = 128 */ 97 #define GPDMA_BSIZE_256 ((7UL)) /**< Burst size = 256 */ 98 99 /** Width in Source transfer width and Destination transfer width definitions */ 100 #define GPDMA_WIDTH_BYTE ((0UL)) /**< Width = 1 byte */ 101 #define GPDMA_WIDTH_HALFWORD ((1UL)) /**< Width = 2 bytes */ 102 #define GPDMA_WIDTH_WORD ((2UL)) /**< Width = 4 bytes */ 103 104 /** DMA Request Select Mode definitions */ 105 #define GPDMA_REQSEL_UART ((0UL)) /**< UART TX/RX is selected */ 106 #define GPDMA_REQSEL_TIMER ((1UL)) /**< Timer match is selected */ 107 108 /** 109 * @} 110 */ 111 112 113 /* Private Macros ------------------------------------------------------------- */ 114 /** @defgroup GPDMA_Private_Macros GPDMA Private Macros 115 * @{ 116 */ 117 118 /* --------------------- BIT DEFINITIONS -------------------------------------- */ 119 /*********************************************************************//** 120 * Macro defines for DMA Interrupt Status register 121 **********************************************************************/ 122 #define GPDMA_DMACIntStat_Ch(n) (((1UL<<n)&0xFF)) 123 #define GPDMA_DMACIntStat_BITMASK ((0xFF)) 124 125 /*********************************************************************//** 126 * Macro defines for DMA Interrupt Terminal Count Request Status register 127 **********************************************************************/ 128 #define GPDMA_DMACIntTCStat_Ch(n) (((1UL<<n)&0xFF)) 129 #define GPDMA_DMACIntTCStat_BITMASK ((0xFF)) 130 131 /*********************************************************************//** 132 * Macro defines for DMA Interrupt Terminal Count Request Clear register 133 **********************************************************************/ 134 #define GPDMA_DMACIntTCClear_Ch(n) (((1UL<<n)&0xFF)) 135 #define GPDMA_DMACIntTCClear_BITMASK ((0xFF)) 136 137 /*********************************************************************//** 138 * Macro defines for DMA Interrupt Error Status register 139 **********************************************************************/ 140 #define GPDMA_DMACIntErrStat_Ch(n) (((1UL<<n)&0xFF)) 141 #define GPDMA_DMACIntErrStat_BITMASK ((0xFF)) 142 143 /*********************************************************************//** 144 * Macro defines for DMA Interrupt Error Clear register 145 **********************************************************************/ 146 #define GPDMA_DMACIntErrClr_Ch(n) (((1UL<<n)&0xFF)) 147 #define GPDMA_DMACIntErrClr_BITMASK ((0xFF)) 148 149 /*********************************************************************//** 150 * Macro defines for DMA Raw Interrupt Terminal Count Status register 151 **********************************************************************/ 152 #define GPDMA_DMACRawIntTCStat_Ch(n) (((1UL<<n)&0xFF)) 153 #define GPDMA_DMACRawIntTCStat_BITMASK ((0xFF)) 154 155 /*********************************************************************//** 156 * Macro defines for DMA Raw Error Interrupt Status register 157 **********************************************************************/ 158 #define GPDMA_DMACRawIntErrStat_Ch(n) (((1UL<<n)&0xFF)) 159 #define GPDMA_DMACRawIntErrStat_BITMASK ((0xFF)) 160 161 /*********************************************************************//** 162 * Macro defines for DMA Enabled Channel register 163 **********************************************************************/ 164 #define GPDMA_DMACEnbldChns_Ch(n) (((1UL<<n)&0xFF)) 165 #define GPDMA_DMACEnbldChns_BITMASK ((0xFF)) 166 167 /*********************************************************************//** 168 * Macro defines for DMA Software Burst Request register 169 **********************************************************************/ 170 #define GPDMA_DMACSoftBReq_Src(n) (((1UL<<n)&0xFFFF)) 171 #define GPDMA_DMACSoftBReq_BITMASK ((0xFFFF)) 172 173 /*********************************************************************//** 174 * Macro defines for DMA Software Single Request register 175 **********************************************************************/ 176 #define GPDMA_DMACSoftSReq_Src(n) (((1UL<<n)&0xFFFF)) 177 #define GPDMA_DMACSoftSReq_BITMASK ((0xFFFF)) 178 179 /*********************************************************************//** 180 * Macro defines for DMA Software Last Burst Request register 181 **********************************************************************/ 182 #define GPDMA_DMACSoftLBReq_Src(n) (((1UL<<n)&0xFFFF)) 183 #define GPDMA_DMACSoftLBReq_BITMASK ((0xFFFF)) 184 185 /*********************************************************************//** 186 * Macro defines for DMA Software Last Single Request register 187 **********************************************************************/ 188 #define GPDMA_DMACSoftLSReq_Src(n) (((1UL<<n)&0xFFFF)) 189 #define GPDMA_DMACSoftLSReq_BITMASK ((0xFFFF)) 190 191 /*********************************************************************//** 192 * Macro defines for DMA Configuration register 193 **********************************************************************/ 194 #define GPDMA_DMACConfig_E ((0x01)) /**< DMA Controller enable*/ 195 #define GPDMA_DMACConfig_M ((0x02)) /**< AHB Master endianness configuration*/ 196 #define GPDMA_DMACConfig_BITMASK ((0x03)) 197 198 /*********************************************************************//** 199 * Macro defines for DMA Synchronization register 200 **********************************************************************/ 201 #define GPDMA_DMACSync_Src(n) (((1UL<<n)&0xFFFF)) 202 #define GPDMA_DMACSync_BITMASK ((0xFFFF)) 203 204 /*********************************************************************//** 205 * Macro defines for DMA Request Select register 206 **********************************************************************/ 207 #define GPDMA_DMAReqSel_Input(n) (((1UL<<(n-8))&0xFF)) 208 #define GPDMA_DMAReqSel_BITMASK ((0xFF)) 209 210 /*********************************************************************//** 211 * Macro defines for DMA Channel Linked List Item registers 212 **********************************************************************/ 213 /** DMA Channel Linked List Item registers bit mask*/ 214 #define GPDMA_DMACCxLLI_BITMASK ((0xFFFFFFFC)) 215 216 /*********************************************************************//** 217 * Macro defines for DMA channel control registers 218 **********************************************************************/ 219 #define GPDMA_DMACCxControl_TransferSize(n) (((n&0xFFF)<<0)) /**< Transfer size*/ 220 #define GPDMA_DMACCxControl_SBSize(n) (((n&0x07)<<12)) /**< Source burst size*/ 221 #define GPDMA_DMACCxControl_DBSize(n) (((n&0x07)<<15)) /**< Destination burst size*/ 222 #define GPDMA_DMACCxControl_SWidth(n) (((n&0x07)<<18)) /**< Source transfer width*/ 223 #define GPDMA_DMACCxControl_DWidth(n) (((n&0x07)<<21)) /**< Destination transfer width*/ 224 #define GPDMA_DMACCxControl_SI ((1UL<<26)) /**< Source increment*/ 225 #define GPDMA_DMACCxControl_DI ((1UL<<27)) /**< Destination increment*/ 226 #define GPDMA_DMACCxControl_Prot1 ((1UL<<28)) /**< Indicates that the access is in user mode or privileged mode*/ 227 #define GPDMA_DMACCxControl_Prot2 ((1UL<<29)) /**< Indicates that the access is bufferable or not bufferable*/ 228 #define GPDMA_DMACCxControl_Prot3 ((1UL<<30)) /**< Indicates that the access is cacheable or not cacheable*/ 229 #define GPDMA_DMACCxControl_I ((1UL<<31)) /**< Terminal count interrupt enable bit */ 230 /** DMA channel control registers bit mask */ 231 #define GPDMA_DMACCxControl_BITMASK ((0xFCFFFFFF)) 232 233 /*********************************************************************//** 234 * Macro defines for DMA Channel Configuration registers 235 **********************************************************************/ 236 #define GPDMA_DMACCxConfig_E ((1UL<<0)) /**< DMA control enable*/ 237 #define GPDMA_DMACCxConfig_SrcPeripheral(n) (((n&0x1F)<<1)) /**< Source peripheral*/ 238 #define GPDMA_DMACCxConfig_DestPeripheral(n) (((n&0x1F)<<6)) /**< Destination peripheral*/ 239 #define GPDMA_DMACCxConfig_TransferType(n) (((n&0x7)<<11)) /**< This value indicates the type of transfer*/ 240 #define GPDMA_DMACCxConfig_IE ((1UL<<14)) /**< Interrupt error mask*/ 241 #define GPDMA_DMACCxConfig_ITC ((1UL<<15)) /**< Terminal count interrupt mask*/ 242 #define GPDMA_DMACCxConfig_L ((1UL<<16)) /**< Lock*/ 243 #define GPDMA_DMACCxConfig_A ((1UL<<17)) /**< Active*/ 244 #define GPDMA_DMACCxConfig_H ((1UL<<18)) /**< Halt*/ 245 /** DMA Channel Configuration registers bit mask */ 246 #define GPDMA_DMACCxConfig_BITMASK ((0x7FFFF)) 247 248 /* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */ 249 /* Macros check GPDMA channel */ 250 #define PARAM_GPDMA_CHANNEL(n) (n<=7) 251 252 /* Macros check GPDMA connection type */ 253 #define PARAM_GPDMA_CONN(n) ((n==GPDMA_CONN_SSP0_Tx) || (n==GPDMA_CONN_SSP0_Rx) \ 254 || (n==GPDMA_CONN_SSP1_Tx) || (n==GPDMA_CONN_SSP1_Rx) \ 255 || (n==GPDMA_CONN_ADC) || (n==GPDMA_CONN_I2S_Channel_0) \ 256 || (n==GPDMA_CONN_I2S_Channel_1) || (n==GPDMA_CONN_DAC) \ 257 || (n==GPDMA_CONN_UART0_Tx) || (n==GPDMA_CONN_UART0_Rx) \ 258 || (n==GPDMA_CONN_UART1_Tx) || (n==GPDMA_CONN_UART1_Rx) \ 259 || (n==GPDMA_CONN_UART2_Tx) || (n==GPDMA_CONN_UART2_Rx) \ 260 || (n==GPDMA_CONN_UART3_Tx) || (n==GPDMA_CONN_UART3_Rx) \ 261 || (n==GPDMA_CONN_MAT0_0) || (n==GPDMA_CONN_MAT0_1) \ 262 || (n==GPDMA_CONN_MAT1_0) || (n==GPDMA_CONN_MAT1_1) \ 263 || (n==GPDMA_CONN_MAT2_0) || (n==GPDMA_CONN_MAT2_1) \ 264 || (n==GPDMA_CONN_MAT3_0) || (n==GPDMA_CONN_MAT3_1)) 265 266 /* Macros check GPDMA burst size type */ 267 #define PARAM_GPDMA_BSIZE(n) ((n==GPDMA_BSIZE_1) || (n==GPDMA_BSIZE_4) \ 268 || (n==GPDMA_BSIZE_8) || (n==GPDMA_BSIZE_16) \ 269 || (n==GPDMA_BSIZE_32) || (n==GPDMA_BSIZE_64) \ 270 || (n==GPDMA_BSIZE_128) || (n==GPDMA_BSIZE_256)) 271 272 /* Macros check GPDMA width type */ 273 #define PARAM_GPDMA_WIDTH(n) ((n==GPDMA_WIDTH_BYTE) || (n==GPDMA_WIDTH_HALFWORD) \ 274 || (n==GPDMA_WIDTH_WORD)) 275 276 /* Macros check GPDMA status type */ 277 #define PARAM_GPDMA_STAT(n) ((n==GPDMA_STAT_INT) || (n==GPDMA_STAT_INTTC) \ 278 || (n==GPDMA_STAT_INTERR) || (n==GPDMA_STAT_RAWINTTC) \ 279 || (n==GPDMA_STAT_RAWINTERR) || (n==GPDMA_STAT_ENABLED_CH)) 280 281 /* Macros check GPDMA transfer type */ 282 #define PARAM_GPDMA_TRANSFERTYPE(n) ((n==GPDMA_TRANSFERTYPE_M2M)||(n==GPDMA_TRANSFERTYPE_M2P) \ 283 ||(n==GPDMA_TRANSFERTYPE_P2M)||(n==GPDMA_TRANSFERTYPE_P2P)) 284 285 /* Macros check GPDMA state clear type */ 286 #define PARAM_GPDMA_STATCLR(n) ((n==GPDMA_STATCLR_INTTC) || (n==GPDMA_STATCLR_INTERR)) 287 288 /* Macros check GPDMA request select type */ 289 #define PARAM_GPDMA_REQSEL(n) ((n==GPDMA_REQSEL_UART) || (n==GPDMA_REQSEL_TIMER)) 290 /** 291 * @} 292 */ 293 294 295 /* Public Types --------------------------------------------------------------- */ 296 /** @defgroup GPDMA_Public_Types GPDMA Public Types 297 * @{ 298 */ 299 300 /** 301 * @brief GPDMA Status enumeration 302 */ 303 typedef enum { 304 GPDMA_STAT_INT, /**< GPDMA Interrupt Status */ 305 GPDMA_STAT_INTTC, /**< GPDMA Interrupt Terminal Count Request Status */ 306 GPDMA_STAT_INTERR, /**< GPDMA Interrupt Error Status */ 307 GPDMA_STAT_RAWINTTC, /**< GPDMA Raw Interrupt Terminal Count Status */ 308 GPDMA_STAT_RAWINTERR, /**< GPDMA Raw Error Interrupt Status */ 309 GPDMA_STAT_ENABLED_CH /**< GPDMA Enabled Channel Status */ 310 } GPDMA_Status_Type; 311 312 /** 313 * @brief GPDMA Interrupt clear status enumeration 314 */ 315 typedef enum{ 316 GPDMA_STATCLR_INTTC, /**< GPDMA Interrupt Terminal Count Request Clear */ 317 GPDMA_STATCLR_INTERR /**< GPDMA Interrupt Error Clear */ 318 }GPDMA_StateClear_Type; 319 320 /** 321 * @brief GPDMA Channel configuration structure type definition 322 */ 323 typedef struct { 324 uint32_t ChannelNum; /**< DMA channel number, should be in 325 range from 0 to 7. 326 Note: DMA channel 0 has the highest priority 327 and DMA channel 7 the lowest priority. 328 */ 329 uint32_t TransferSize; /**< Length/Size of transfer */ 330 uint32_t TransferWidth; /**< Transfer width - used for TransferType is GPDMA_TRANSFERTYPE_M2M only */ 331 uint32_t SrcMemAddr; /**< Physical Source Address, used in case TransferType is chosen as 332 GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_M2P */ 333 uint32_t DstMemAddr; /**< Physical Destination Address, used in case TransferType is chosen as 334 GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_P2M */ 335 uint32_t TransferType; /**< Transfer Type, should be one of the following: 336 - GPDMA_TRANSFERTYPE_M2M: Memory to memory - DMA control 337 - GPDMA_TRANSFERTYPE_M2P: Memory to peripheral - DMA control 338 - GPDMA_TRANSFERTYPE_P2M: Peripheral to memory - DMA control 339 - GPDMA_TRANSFERTYPE_P2P: Source peripheral to destination peripheral - DMA control 340 */ 341 uint32_t SrcConn; /**< Peripheral Source Connection type, used in case TransferType is chosen as 342 GPDMA_TRANSFERTYPE_P2M or GPDMA_TRANSFERTYPE_P2P, should be one of 343 following: 344 - GPDMA_CONN_SSP0_Tx: SSP0, Tx 345 - GPDMA_CONN_SSP0_Rx: SSP0, Rx 346 - GPDMA_CONN_SSP1_Tx: SSP1, Tx 347 - GPDMA_CONN_SSP1_Rx: SSP1, Rx 348 - GPDMA_CONN_ADC: ADC 349 - GPDMA_CONN_I2S_Channel_0: I2S Channel 0 350 - GPDMA_CONN_I2S_Channel_1: I2S Channel 1 351 - GPDMA_CONN_DAC: DAC 352 - GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0 353 - GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1 354 - GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0 355 - GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1 356 - GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0 357 - GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1 358 - GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0 359 - GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1 360 */ 361 uint32_t DstConn; /**< Peripheral Destination Connection type, used in case TransferType is chosen as 362 GPDMA_TRANSFERTYPE_M2P or GPDMA_TRANSFERTYPE_P2P, should be one of 363 following: 364 - GPDMA_CONN_SSP0_Tx: SSP0, Tx 365 - GPDMA_CONN_SSP0_Rx: SSP0, Rx 366 - GPDMA_CONN_SSP1_Tx: SSP1, Tx 367 - GPDMA_CONN_SSP1_Rx: SSP1, Rx 368 - GPDMA_CONN_ADC: ADC 369 - GPDMA_CONN_I2S_Channel_0: I2S Channel 0 370 - GPDMA_CONN_I2S_Channel_1: I2S Channel 1 371 - GPDMA_CONN_DAC: DAC 372 - GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0 373 - GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1 374 - GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0 375 - GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1 376 - GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0 377 - GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1 378 - GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0 379 - GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1 380 */ 381 uint32_t DMALLI; /**< Linker List Item structure data address 382 if there's no Linker List, set as '0' 383 */ 384 } GPDMA_Channel_CFG_Type; 385 386 /** 387 * @brief GPDMA Linker List Item structure type definition 388 */ 389 typedef struct { 390 uint32_t SrcAddr; /**< Source Address */ 391 uint32_t DstAddr; /**< Destination address */ 392 uint32_t NextLLI; /**< Next LLI address, otherwise set to '0' */ 393 uint32_t Control; /**< GPDMA Control of this LLI */ 394 } GPDMA_LLI_Type; 395 396 397 /** 398 * @} 399 */ 400 401 /* Public Functions ----------------------------------------------------------- */ 402 /** @defgroup GPDMA_Public_Functions GPDMA Public Functions 403 * @{ 404 */ 405 406 void GPDMA_Init(void); 407 //Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig, fnGPDMACbs_Type *pfnGPDMACbs); 408 Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig); 409 IntStatus GPDMA_IntGetStatus(GPDMA_Status_Type type, uint8_t channel); 410 void GPDMA_ClearIntPending(GPDMA_StateClear_Type type, uint8_t channel); 411 void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState); 412 //void GPDMA_IntHandler(void); 413 414 /** 415 * @} 416 */ 417 418 419 #ifdef __cplusplus 420 } 421 #endif 422 423 #endif /* LPC17XX_GPDMA_H_ */ 424 425 /** 426 * @} 427 */ 428 429 /* --------------------------------- End Of File ------------------------------ */