lpc17xx_i2c.h (15929B)
1 /********************************************************************** 2 * $Id$ lpc17xx_i2c.h 2010-05-21 3 *//** 4 * @file lpc17xx_i2c.h 5 * @brief Contains all macro definitions and function prototypes 6 * support for I2C firmware library on LPC17xx 7 * @version 2.0 8 * @date 21. May. 2010 9 * @author NXP MCU SW Application Team 10 * 11 * Copyright(C) 2010, NXP Semiconductor 12 * All rights reserved. 13 * 14 *********************************************************************** 15 * Software that is described herein is for illustrative purposes only 16 * which provides customers with programming information regarding the 17 * products. This software is supplied "AS IS" without any warranties. 18 * NXP Semiconductors assumes no responsibility or liability for the 19 * use of the software, conveys no license or title under any patent, 20 * copyright, or mask work right to the product. NXP Semiconductors 21 * reserves the right to make changes in the software without 22 * notification. NXP Semiconductors also make no representation or 23 * warranty that such application will be suitable for the specified 24 * use without further testing or modification. 25 * Permission to use, copy, modify, and distribute this software and its 26 * documentation is hereby granted, under NXP Semiconductors' 27 * relevant copyright in the software, without fee, provided that it 28 * is used in conjunction with NXP Semiconductors microcontrollers. This 29 * copyright, permission, and disclaimer notice must appear in all copies of 30 * this code. 31 **********************************************************************/ 32 33 /* Peripheral group ----------------------------------------------------------- */ 34 /** @defgroup I2C I2C (Inter-IC Control bus) 35 * @ingroup LPC1700CMSIS_FwLib_Drivers 36 * @{ 37 */ 38 39 #ifndef LPC17XX_I2C_H_ 40 #define LPC17XX_I2C_H_ 41 42 /* Includes ------------------------------------------------------------------- */ 43 #include "LPC17xx.h" 44 #include "lpc_types.h" 45 46 47 #ifdef __cplusplus 48 extern "C" 49 { 50 #endif 51 52 53 /* Private Macros ------------------------------------------------------------- */ 54 /** @defgroup I2C_Private_Macros I2C Private Macros 55 * @{ 56 */ 57 58 /* --------------------- BIT DEFINITIONS -------------------------------------- */ 59 /*******************************************************************//** 60 * I2C Control Set register description 61 *********************************************************************/ 62 #define I2C_I2CONSET_AA ((0x04)) /*!< Assert acknowledge flag */ 63 #define I2C_I2CONSET_SI ((0x08)) /*!< I2C interrupt flag */ 64 #define I2C_I2CONSET_STO ((0x10)) /*!< STOP flag */ 65 #define I2C_I2CONSET_STA ((0x20)) /*!< START flag */ 66 #define I2C_I2CONSET_I2EN ((0x40)) /*!< I2C interface enable */ 67 68 /*******************************************************************//** 69 * I2C Control Clear register description 70 *********************************************************************/ 71 /** Assert acknowledge Clear bit */ 72 #define I2C_I2CONCLR_AAC ((1<<2)) 73 /** I2C interrupt Clear bit */ 74 #define I2C_I2CONCLR_SIC ((1<<3)) 75 /** I2C STOP Clear bit */ 76 #define I2C_I2CONCLR_STOC ((1<<4)) 77 /** START flag Clear bit */ 78 #define I2C_I2CONCLR_STAC ((1<<5)) 79 /** I2C interface Disable bit */ 80 #define I2C_I2CONCLR_I2ENC ((1<<6)) 81 82 /********************************************************************//** 83 * I2C Status Code definition (I2C Status register) 84 *********************************************************************/ 85 /* Return Code in I2C status register */ 86 #define I2C_STAT_CODE_BITMASK ((0xF8)) 87 88 /* I2C return status code definitions ----------------------------- */ 89 90 /** No relevant information */ 91 #define I2C_I2STAT_NO_INF ((0xF8)) 92 93 /** Bus Error */ 94 #define I2C_I2STAT_BUS_ERROR ((0x00)) 95 96 /* Master transmit mode -------------------------------------------- */ 97 /** A start condition has been transmitted */ 98 #define I2C_I2STAT_M_TX_START ((0x08)) 99 100 /** A repeat start condition has been transmitted */ 101 #define I2C_I2STAT_M_TX_RESTART ((0x10)) 102 103 /** SLA+W has been transmitted, ACK has been received */ 104 #define I2C_I2STAT_M_TX_SLAW_ACK ((0x18)) 105 106 /** SLA+W has been transmitted, NACK has been received */ 107 #define I2C_I2STAT_M_TX_SLAW_NACK ((0x20)) 108 109 /** Data has been transmitted, ACK has been received */ 110 #define I2C_I2STAT_M_TX_DAT_ACK ((0x28)) 111 112 /** Data has been transmitted, NACK has been received */ 113 #define I2C_I2STAT_M_TX_DAT_NACK ((0x30)) 114 115 /** Arbitration lost in SLA+R/W or Data bytes */ 116 #define I2C_I2STAT_M_TX_ARB_LOST ((0x38)) 117 118 /* Master receive mode -------------------------------------------- */ 119 /** A start condition has been transmitted */ 120 #define I2C_I2STAT_M_RX_START ((0x08)) 121 122 /** A repeat start condition has been transmitted */ 123 #define I2C_I2STAT_M_RX_RESTART ((0x10)) 124 125 /** Arbitration lost */ 126 #define I2C_I2STAT_M_RX_ARB_LOST ((0x38)) 127 128 /** SLA+R has been transmitted, ACK has been received */ 129 #define I2C_I2STAT_M_RX_SLAR_ACK ((0x40)) 130 131 /** SLA+R has been transmitted, NACK has been received */ 132 #define I2C_I2STAT_M_RX_SLAR_NACK ((0x48)) 133 134 /** Data has been received, ACK has been returned */ 135 #define I2C_I2STAT_M_RX_DAT_ACK ((0x50)) 136 137 /** Data has been received, NACK has been return */ 138 #define I2C_I2STAT_M_RX_DAT_NACK ((0x58)) 139 140 /* Slave receive mode -------------------------------------------- */ 141 /** Own slave address has been received, ACK has been returned */ 142 #define I2C_I2STAT_S_RX_SLAW_ACK ((0x60)) 143 144 /** Arbitration lost in SLA+R/W as master */ 145 #define I2C_I2STAT_S_RX_ARB_LOST_M_SLA ((0x68)) 146 147 /** General call address has been received, ACK has been returned */ 148 #define I2C_I2STAT_S_RX_GENCALL_ACK ((0x70)) 149 150 /** Arbitration lost in SLA+R/W (GENERAL CALL) as master */ 151 #define I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL ((0x78)) 152 153 /** Previously addressed with own SLV address; 154 * Data has been received, ACK has been return */ 155 #define I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK ((0x80)) 156 157 /** Previously addressed with own SLA; 158 * Data has been received and NOT ACK has been return */ 159 #define I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK ((0x88)) 160 161 /** Previously addressed with General Call; 162 * Data has been received and ACK has been return */ 163 #define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK ((0x90)) 164 165 /** Previously addressed with General Call; 166 * Data has been received and NOT ACK has been return */ 167 #define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK ((0x98)) 168 169 /** A STOP condition or repeated START condition has 170 * been received while still addressed as SLV/REC 171 * (Slave Receive) or SLV/TRX (Slave Transmit) */ 172 #define I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX ((0xA0)) 173 174 /** Slave transmit mode */ 175 /** Own SLA+R has been received, ACK has been returned */ 176 #define I2C_I2STAT_S_TX_SLAR_ACK ((0xA8)) 177 178 /** Arbitration lost in SLA+R/W as master */ 179 #define I2C_I2STAT_S_TX_ARB_LOST_M_SLA ((0xB0)) 180 181 /** Data has been transmitted, ACK has been received */ 182 #define I2C_I2STAT_S_TX_DAT_ACK ((0xB8)) 183 184 /** Data has been transmitted, NACK has been received */ 185 #define I2C_I2STAT_S_TX_DAT_NACK ((0xC0)) 186 187 /** Last data byte in I2DAT has been transmitted (AA = 0); 188 ACK has been received */ 189 #define I2C_I2STAT_S_TX_LAST_DAT_ACK ((0xC8)) 190 191 /** Time out in case of using I2C slave mode */ 192 #define I2C_SLAVE_TIME_OUT 0x10000UL 193 194 /********************************************************************//** 195 * I2C Data register definition 196 *********************************************************************/ 197 /** Mask for I2DAT register*/ 198 #define I2C_I2DAT_BITMASK ((0xFF)) 199 200 /** Idle data value will be send out in slave mode in case of the actual 201 * expecting data requested from the master is greater than its sending data 202 * length that can be supported */ 203 #define I2C_I2DAT_IDLE_CHAR (0xFF) 204 205 /********************************************************************//** 206 * I2C Monitor mode control register description 207 *********************************************************************/ 208 #define I2C_I2MMCTRL_MM_ENA ((1<<0)) /**< Monitor mode enable */ 209 #define I2C_I2MMCTRL_ENA_SCL ((1<<1)) /**< SCL output enable */ 210 #define I2C_I2MMCTRL_MATCH_ALL ((1<<2)) /**< Select interrupt register match */ 211 #define I2C_I2MMCTRL_BITMASK ((0x07)) /**< Mask for I2MMCTRL register */ 212 213 /********************************************************************//** 214 * I2C Data buffer register description 215 *********************************************************************/ 216 /** I2C Data buffer register bit mask */ 217 #define I2DATA_BUFFER_BITMASK ((0xFF)) 218 219 /********************************************************************//** 220 * I2C Slave Address registers definition 221 *********************************************************************/ 222 /** General Call enable bit */ 223 #define I2C_I2ADR_GC ((1<<0)) 224 225 /** I2C Slave Address registers bit mask */ 226 #define I2C_I2ADR_BITMASK ((0xFF)) 227 228 /********************************************************************//** 229 * I2C Mask Register definition 230 *********************************************************************/ 231 /** I2C Mask Register mask field */ 232 #define I2C_I2MASK_MASK(n) ((n&0xFE)) 233 234 /********************************************************************//** 235 * I2C SCL HIGH duty cycle Register definition 236 *********************************************************************/ 237 /** I2C SCL HIGH duty cycle Register bit mask */ 238 #define I2C_I2SCLH_BITMASK ((0xFFFF)) 239 240 /********************************************************************//** 241 * I2C SCL LOW duty cycle Register definition 242 *********************************************************************/ 243 /** I2C SCL LOW duty cycle Register bit mask */ 244 #define I2C_I2SCLL_BITMASK ((0xFFFF)) 245 246 247 /* I2C status values */ 248 #define I2C_SETUP_STATUS_ARBF (1<<8) /**< Arbitration false */ 249 #define I2C_SETUP_STATUS_NOACKF (1<<9) /**< No ACK returned */ 250 #define I2C_SETUP_STATUS_DONE (1<<10) /**< Status DONE */ 251 252 /*********************************************************************//** 253 * I2C monitor control configuration defines 254 **********************************************************************/ 255 #define I2C_MONITOR_CFG_SCL_OUTPUT I2C_I2MMCTRL_ENA_SCL /**< SCL output enable */ 256 #define I2C_MONITOR_CFG_MATCHALL I2C_I2MMCTRL_MATCH_ALL /**< Select interrupt register match */ 257 258 /* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */ 259 /* Macros check I2C slave address */ 260 #define PARAM_I2C_SLAVEADDR_CH(n) (n<=3) 261 262 /** Macro to determine if it is valid SSP port number */ 263 #define PARAM_I2Cx(n) ((((uint32_t *)n)==((uint32_t *)LPC_I2C0)) \ 264 || (((uint32_t *)n)==((uint32_t *)LPC_I2C1)) \ 265 || (((uint32_t *)n)==((uint32_t *)LPC_I2C2))) 266 267 /* Macros check I2C monitor configuration type */ 268 #define PARAM_I2C_MONITOR_CFG(n) ((n==I2C_MONITOR_CFG_SCL_OUTPUT) || (I2C_MONITOR_CFG_MATCHALL)) 269 270 /* I2C state handle return values */ 271 #define I2C_OK 0x00 272 #define I2C_BYTE_SENT 0x01 273 #define I2C_BYTE_RECV 0x02 274 #define I2C_LAST_BYTE_RECV 0x04 275 #define I2C_SEND_END 0x08 276 #define I2C_RECV_END 0x10 277 #define I2C_STA_STO_RECV 0x20 278 279 #define I2C_ERR (0x10000000) 280 #define I2C_NAK_RECV (0x10000000 |0x01) 281 282 #define I2C_CheckError(ErrorCode) (ErrorCode & 0x10000000) 283 284 /** 285 * @} 286 */ 287 288 289 290 /* Public Types --------------------------------------------------------------- */ 291 /** @defgroup I2C_Public_Types I2C Public Types 292 * @{ 293 */ 294 295 typedef enum 296 { 297 I2C_0 = 0, 298 I2C_1, 299 I2C_2 300 } en_I2C_unitId; 301 302 typedef enum 303 { 304 I2C_MASTER_MODE, 305 I2C_SLAVE_MODE, 306 I2C_GENERAL_MODE, 307 } en_I2C_Mode; 308 /** 309 * @brief I2C Own slave address setting structure 310 */ 311 typedef struct { 312 uint8_t SlaveAddrChannel; /**< Slave Address channel in I2C control, 313 should be in range from 0..3 314 */ 315 uint8_t SlaveAddr_7bit; /**< Value of 7-bit slave address */ 316 uint8_t GeneralCallState; /**< Enable/Disable General Call Functionality 317 when I2C control being in Slave mode, should be: 318 - ENABLE: Enable General Call function. 319 - DISABLE: Disable General Call function. 320 */ 321 uint8_t SlaveAddrMaskValue; /**< Any bit in this 8-bit value (bit 7:1) 322 which is set to '1' will cause an automatic compare on 323 the corresponding bit of the received address when it 324 is compared to the SlaveAddr_7bit value associated with this 325 mask register. In other words, bits in SlaveAddr_7bit value 326 which are masked are not taken into account in determining 327 an address match 328 */ 329 } I2C_OWNSLAVEADDR_CFG_Type; 330 331 332 /** 333 * @brief Master transfer setup data structure definitions 334 */ 335 typedef struct 336 { 337 uint32_t sl_addr7bit; /**< Slave address in 7bit mode */ 338 __IO uint8_t* tx_data; /**< Pointer to Transmit data - NULL if data transmit 339 is not used */ 340 uint32_t tx_length; /**< Transmit data length - 0 if data transmit 341 is not used*/ 342 __IO uint32_t tx_count; /**< Current Transmit data counter */ 343 __IO uint8_t* rx_data; /**< Pointer to Receive data - NULL if data receive 344 is not used */ 345 uint32_t rx_length; /**< Receive data length - 0 if data receive is 346 not used */ 347 __IO uint32_t rx_count; /**< Current Receive data counter */ 348 uint32_t retransmissions_max; /**< Max Re-Transmission value */ 349 uint32_t retransmissions_count; /**< Current Re-Transmission counter */ 350 __IO uint32_t status; /**< Current status of I2C activity */ 351 void (*callback)(void); /**< Pointer to Call back function when transmission complete 352 used in interrupt transfer mode */ 353 } I2C_M_SETUP_Type; 354 355 356 /** 357 * @brief Slave transfer setup data structure definitions 358 */ 359 typedef struct 360 { 361 __IO uint8_t* tx_data; 362 uint32_t tx_length; 363 __IO uint32_t tx_count; 364 __IO uint8_t* rx_data; 365 uint32_t rx_length; 366 __IO uint32_t rx_count; 367 __IO uint32_t status; 368 void (*callback)(void); 369 } I2C_S_SETUP_Type; 370 371 /** 372 * @brief Transfer option type definitions 373 */ 374 typedef enum { 375 I2C_TRANSFER_POLLING = 0, /**< Transfer in polling mode */ 376 I2C_TRANSFER_INTERRUPT /**< Transfer in interrupt mode */ 377 } I2C_TRANSFER_OPT_Type; 378 379 380 /** 381 * @} 382 */ 383 384 385 /* Public Functions ----------------------------------------------------------- */ 386 /** @defgroup I2C_Public_Functions I2C Public Functions 387 * @{ 388 */ 389 390 /* I2C Init/DeInit functions ---------- */ 391 void I2C_Init(LPC_I2C_TypeDef *I2Cx, uint32_t clockrate); 392 void I2C_DeInit(LPC_I2C_TypeDef* I2Cx); 393 void I2C_Cmd(LPC_I2C_TypeDef* I2Cx, en_I2C_Mode Mode, FunctionalState NewState); 394 395 /* I2C transfer data functions -------- */ 396 Status I2C_MasterTransferData(LPC_I2C_TypeDef *I2Cx, \ 397 I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt); 398 Status I2C_SlaveTransferData(LPC_I2C_TypeDef *I2Cx, \ 399 I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt); 400 uint32_t I2C_MasterTransferComplete(LPC_I2C_TypeDef *I2Cx); 401 uint32_t I2C_SlaveTransferComplete(LPC_I2C_TypeDef *I2Cx); 402 403 404 void I2C_SetOwnSlaveAddr(LPC_I2C_TypeDef *I2Cx, I2C_OWNSLAVEADDR_CFG_Type *OwnSlaveAddrConfigStruct); 405 uint8_t I2C_GetLastStatusCode(LPC_I2C_TypeDef* I2Cx); 406 407 /* I2C Monitor functions ---------------*/ 408 void I2C_MonitorModeConfig(LPC_I2C_TypeDef *I2Cx, uint32_t MonitorCfgType, FunctionalState NewState); 409 void I2C_MonitorModeCmd(LPC_I2C_TypeDef *I2Cx, FunctionalState NewState); 410 uint8_t I2C_MonitorGetDatabuffer(LPC_I2C_TypeDef *I2Cx); 411 BOOL_8 I2C_MonitorHandler(LPC_I2C_TypeDef *I2Cx, uint8_t *buffer, uint32_t size); 412 413 /* I2C Interrupt handler functions ------*/ 414 void I2C_IntCmd (LPC_I2C_TypeDef *I2Cx, Bool NewState); 415 void I2C_MasterHandler (LPC_I2C_TypeDef *I2Cx); 416 void I2C_SlaveHandler (LPC_I2C_TypeDef *I2Cx); 417 int32_t I2C_MasterHanleStates(LPC_I2C_TypeDef *I2Cx, uint32_t CodeStatus, I2C_M_SETUP_Type *TransferCfg); 418 int32_t I2C_SlaveHanleStates(LPC_I2C_TypeDef *I2Cx, uint32_t CodeStatus, I2C_S_SETUP_Type *TransferCfg); 419 420 /** 421 * @} 422 */ 423 424 425 #ifdef __cplusplus 426 } 427 #endif 428 429 #endif /* LPC17XX_I2C_H_ */ 430 431 /** 432 * @} 433 */ 434 435 /* --------------------------------- End Of File ------------------------------ */