lpc17xx_i2s.h (15600B)
1 /********************************************************************** 2 * $Id$ lpc17xx_i2s.h 2011-06-06 3 *//** 4 * @file lpc17xx_i2s.h 5 * @brief Contains all macro definitions and function prototypes 6 * support for I2S firmware library on LPC17xx 7 * @version 3.1 8 * @date 06. June. 2011 9 * @author NXP MCU SW Application Team 10 * 11 * Copyright(C) 2011, NXP Semiconductor 12 * All rights reserved. 13 * 14 *********************************************************************** 15 * Software that is described herein is for illustrative purposes only 16 * which provides customers with programming information regarding the 17 * products. This software is supplied "AS IS" without any warranties. 18 * NXP Semiconductors assumes no responsibility or liability for the 19 * use of the software, conveys no license or title under any patent, 20 * copyright, or mask work right to the product. NXP Semiconductors 21 * reserves the right to make changes in the software without 22 * notification. NXP Semiconductors also make no representation or 23 * warranty that such application will be suitable for the specified 24 * use without further testing or modification. 25 * Permission to use, copy, modify, and distribute this software and its 26 * documentation is hereby granted, under NXP Semiconductors' 27 * relevant copyright in the software, without fee, provided that it 28 * is used in conjunction with NXP Semiconductors microcontrollers. This 29 * copyright, permission, and disclaimer notice must appear in all copies of 30 * this code. 31 **********************************************************************/ 32 33 /* Peripheral group ----------------------------------------------------------- */ 34 /** @defgroup I2S I2S (Inter-IC Sound bus) 35 * @ingroup LPC1700CMSIS_FwLib_Drivers 36 * @{ 37 */ 38 39 #ifndef LPC17XX_I2S_H_ 40 #define LPC17XX_I2S_H_ 41 42 /* Includes ------------------------------------------------------------------- */ 43 #include "LPC17xx.h" 44 #include "lpc_types.h" 45 46 47 #ifdef __cplusplus 48 extern "C" 49 { 50 #endif 51 52 /* Public Macros -------------------------------------------------------------- */ 53 /** @defgroup I2S_Public_Macros I2S Public Macros 54 * @{ 55 */ 56 57 /*********************************************************************//** 58 * I2S configuration parameter defines 59 **********************************************************************/ 60 /** I2S Wordwidth bit */ 61 #define I2S_WORDWIDTH_8 ((uint32_t)(0)) 62 #define I2S_WORDWIDTH_16 ((uint32_t)(1)) 63 #define I2S_WORDWIDTH_32 ((uint32_t)(3)) 64 /** I2S Channel bit */ 65 #define I2S_STEREO ((uint32_t)(0)) 66 #define I2S_MONO ((uint32_t)(1)) 67 /** I2S Master/Slave mode bit */ 68 #define I2S_MASTER_MODE ((uint8_t)(0)) 69 #define I2S_SLAVE_MODE ((uint8_t)(1)) 70 /** I2S Stop bit */ 71 #define I2S_STOP_ENABLE ((uint8_t)(1)) 72 #define I2S_STOP_DISABLE ((uint8_t)(0)) 73 /** I2S Reset bit */ 74 #define I2S_RESET_ENABLE ((uint8_t)(1)) 75 #define I2S_RESET_DISABLE ((uint8_t)(0)) 76 /** I2S Mute bit */ 77 #define I2S_MUTE_ENABLE ((uint8_t)(1)) 78 #define I2S_MUTE_DISABLE ((uint8_t)(0)) 79 /** I2S Transmit/Receive bit */ 80 #define I2S_TX_MODE ((uint8_t)(0)) 81 #define I2S_RX_MODE ((uint8_t)(1)) 82 /** I2S Clock Select bit */ 83 #define I2S_CLKSEL_FRDCLK ((uint8_t)(0)) 84 #define I2S_CLKSEL_MCLK ((uint8_t)(2)) 85 /** I2S 4-pin Mode bit */ 86 #define I2S_4PIN_ENABLE ((uint8_t)(1)) 87 #define I2S_4PIN_DISABLE ((uint8_t)(0)) 88 /** I2S MCLK Enable bit */ 89 #define I2S_MCLK_ENABLE ((uint8_t)(1)) 90 #define I2S_MCLK_DISABLE ((uint8_t)(0)) 91 /** I2S select DMA bit */ 92 #define I2S_DMA_1 ((uint8_t)(0)) 93 #define I2S_DMA_2 ((uint8_t)(1)) 94 95 /** 96 * @} 97 */ 98 99 /* Private Macros ------------------------------------------------------------- */ 100 /** @defgroup I2S_Private_Macros I2S Private Macros 101 * @{ 102 */ 103 104 /*********************************************************************//** 105 * Macro defines for DAO-Digital Audio Output register 106 **********************************************************************/ 107 /** I2S wordwide - the number of bytes in data*/ 108 #define I2S_DAO_WORDWIDTH_8 ((uint32_t)(0)) /** 8 bit */ 109 #define I2S_DAO_WORDWIDTH_16 ((uint32_t)(1)) /** 16 bit */ 110 #define I2S_DAO_WORDWIDTH_32 ((uint32_t)(3)) /** 32 bit */ 111 /** I2S control mono or stereo format */ 112 #define I2S_DAO_MONO ((uint32_t)(1<<2)) 113 /** I2S control stop mode */ 114 #define I2S_DAO_STOP ((uint32_t)(1<<3)) 115 /** I2S control reset mode */ 116 #define I2S_DAO_RESET ((uint32_t)(1<<4)) 117 /** I2S control master/slave mode */ 118 #define I2S_DAO_SLAVE ((uint32_t)(1<<5)) 119 /** I2S word select half period minus one */ 120 #define I2S_DAO_WS_HALFPERIOD(n) ((uint32_t)(n<<6)) 121 /** I2S control mute mode */ 122 #define I2S_DAO_MUTE ((uint32_t)(1<<15)) 123 124 /*********************************************************************//** 125 * Macro defines for DAI-Digital Audio Input register 126 **********************************************************************/ 127 /** I2S wordwide - the number of bytes in data*/ 128 #define I2S_DAI_WORDWIDTH_8 ((uint32_t)(0)) /** 8 bit */ 129 #define I2S_DAI_WORDWIDTH_16 ((uint32_t)(1)) /** 16 bit */ 130 #define I2S_DAI_WORDWIDTH_32 ((uint32_t)(3)) /** 32 bit */ 131 /** I2S control mono or stereo format */ 132 #define I2S_DAI_MONO ((uint32_t)(1<<2)) 133 /** I2S control stop mode */ 134 #define I2S_DAI_STOP ((uint32_t)(1<<3)) 135 /** I2S control reset mode */ 136 #define I2S_DAI_RESET ((uint32_t)(1<<4)) 137 /** I2S control master/slave mode */ 138 #define I2S_DAI_SLAVE ((uint32_t)(1<<5)) 139 /** I2S word select half period minus one (9 bits)*/ 140 #define I2S_DAI_WS_HALFPERIOD(n) ((uint32_t)((n&0x1FF)<<6)) 141 /** I2S control mute mode */ 142 #define I2S_DAI_MUTE ((uint32_t)(1<<15)) 143 144 /*********************************************************************//** 145 * Macro defines for STAT register (Status Feedback register) 146 **********************************************************************/ 147 /** I2S Status Receive or Transmit Interrupt */ 148 #define I2S_STATE_IRQ ((uint32_t)(1)) 149 /** I2S Status Receive or Transmit DMA1 */ 150 #define I2S_STATE_DMA1 ((uint32_t)(1<<1)) 151 /** I2S Status Receive or Transmit DMA2 */ 152 #define I2S_STATE_DMA2 ((uint32_t)(1<<2)) 153 /** I2S Status Current level of the Receive FIFO (5 bits)*/ 154 #define I2S_STATE_RX_LEVEL(n) ((uint32_t)((n&1F)<<8)) 155 /** I2S Status Current level of the Transmit FIFO (5 bits)*/ 156 #define I2S_STATE_TX_LEVEL(n) ((uint32_t)((n&1F)<<16)) 157 158 /*********************************************************************//** 159 * Macro defines for DMA1 register (DMA1 Configuration register) 160 **********************************************************************/ 161 /** I2S control DMA1 for I2S receive */ 162 #define I2S_DMA1_RX_ENABLE ((uint32_t)(1)) 163 /** I2S control DMA1 for I2S transmit */ 164 #define I2S_DMA1_TX_ENABLE ((uint32_t)(1<<1)) 165 /** I2S set FIFO level that trigger a receive DMA request on DMA1 */ 166 #define I2S_DMA1_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8)) 167 /** I2S set FIFO level that trigger a transmit DMA request on DMA1 */ 168 #define I2S_DMA1_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16)) 169 170 /*********************************************************************//** 171 * Macro defines for DMA2 register (DMA2 Configuration register) 172 **********************************************************************/ 173 /** I2S control DMA2 for I2S receive */ 174 #define I2S_DMA2_RX_ENABLE ((uint32_t)(1)) 175 /** I2S control DMA1 for I2S transmit */ 176 #define I2S_DMA2_TX_ENABLE ((uint32_t)(1<<1)) 177 /** I2S set FIFO level that trigger a receive DMA request on DMA1 */ 178 #define I2S_DMA2_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8)) 179 /** I2S set FIFO level that trigger a transmit DMA request on DMA1 */ 180 #define I2S_DMA2_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16)) 181 182 /*********************************************************************//** 183 * Macro defines for IRQ register (Interrupt Request Control register) 184 **********************************************************************/ 185 /** I2S control I2S receive interrupt */ 186 #define I2S_IRQ_RX_ENABLE ((uint32_t)(1)) 187 /** I2S control I2S transmit interrupt */ 188 #define I2S_IRQ_TX_ENABLE ((uint32_t)(1<<1)) 189 /** I2S set the FIFO level on which to create an irq request */ 190 #define I2S_IRQ_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8)) 191 /** I2S set the FIFO level on which to create an irq request */ 192 #define I2S_IRQ_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16)) 193 194 /********************************************************************************//** 195 * Macro defines for TXRATE/RXRATE register (Transmit/Receive Clock Rate register) 196 *********************************************************************************/ 197 /** I2S Transmit MCLK rate denominator */ 198 #define I2S_TXRATE_Y_DIVIDER(n) ((uint32_t)(n&0xFF)) 199 /** I2S Transmit MCLK rate denominator */ 200 #define I2S_TXRATE_X_DIVIDER(n) ((uint32_t)((n&0xFF)<<8)) 201 /** I2S Receive MCLK rate denominator */ 202 #define I2S_RXRATE_Y_DIVIDER(n) ((uint32_t)(n&0xFF)) 203 /** I2S Receive MCLK rate denominator */ 204 #define I2S_RXRATE_X_DIVIDER(n) ((uint32_t)((n&0xFF)<<8)) 205 206 /*************************************************************************************//** 207 * Macro defines for TXBITRATE & RXBITRATE register (Transmit/Receive Bit Rate register) 208 **************************************************************************************/ 209 #define I2S_TXBITRATE(n) ((uint32_t)(n&0x3F)) 210 #define I2S_RXBITRATE(n) ((uint32_t)(n&0x3F)) 211 212 /**********************************************************************************//** 213 * Macro defines for TXMODE/RXMODE register (Transmit/Receive Mode Control register) 214 ************************************************************************************/ 215 /** I2S Transmit select clock source (2 bits)*/ 216 #define I2S_TXMODE_CLKSEL(n) ((uint32_t)(n&0x03)) 217 /** I2S Transmit control 4-pin mode */ 218 #define I2S_TXMODE_4PIN_ENABLE ((uint32_t)(1<<2)) 219 /** I2S Transmit control the TX_MCLK output */ 220 #define I2S_TXMODE_MCENA ((uint32_t)(1<<3)) 221 /** I2S Receive select clock source */ 222 #define I2S_RXMODE_CLKSEL(n) ((uint32_t)(n&0x03)) 223 /** I2S Receive control 4-pin mode */ 224 #define I2S_RXMODE_4PIN_ENABLE ((uint32_t)(1<<2)) 225 /** I2S Receive control the TX_MCLK output */ 226 #define I2S_RXMODE_MCENA ((uint32_t)(1<<3)) 227 228 229 /* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */ 230 /** Macro to determine if it is valid I2S peripheral */ 231 #define PARAM_I2Sx(n) (((uint32_t *)n)==((uint32_t *)LPC_I2S)) 232 /** Macro to check Data to send valid */ 233 #define PRAM_I2S_FREQ(freq) ((freq>=16000)&&(freq <= 96000)) 234 /* Macro check I2S word width type */ 235 #define PARAM_I2S_WORDWIDTH(n) ((n==I2S_WORDWIDTH_8)||(n==I2S_WORDWIDTH_16)\ 236 ||(n==I2S_WORDWIDTH_32)) 237 /* Macro check I2S channel type */ 238 #define PARAM_I2S_CHANNEL(n) ((n==I2S_STEREO)||(n==I2S_MONO)) 239 /* Macro check I2S master/slave mode */ 240 #define PARAM_I2S_WS_SEL(n) ((n==I2S_MASTER_MODE)||(n==I2S_SLAVE_MODE)) 241 /* Macro check I2S stop mode */ 242 #define PARAM_I2S_STOP(n) ((n==I2S_STOP_ENABLE)||(n==I2S_STOP_DISABLE)) 243 /* Macro check I2S reset mode */ 244 #define PARAM_I2S_RESET(n) ((n==I2S_RESET_ENABLE)||(n==I2S_RESET_DISABLE)) 245 /* Macro check I2S reset mode */ 246 #define PARAM_I2S_MUTE(n) ((n==I2S_MUTE_ENABLE)||(n==I2S_MUTE_DISABLE)) 247 /* Macro check I2S transmit/receive mode */ 248 #define PARAM_I2S_TRX(n) ((n==I2S_TX_MODE)||(n==I2S_RX_MODE)) 249 /* Macro check I2S clock select mode */ 250 #define PARAM_I2S_CLKSEL(n) ((n==I2S_CLKSEL_FRDCLK)||(n==I2S_CLKSEL_MCLK)) 251 /* Macro check I2S 4-pin mode */ 252 #define PARAM_I2S_4PIN(n) ((n==I2S_4PIN_ENABLE)||(n==I2S_4PIN_DISABLE)) 253 /* Macro check I2S MCLK mode */ 254 #define PARAM_I2S_MCLK(n) ((n==I2S_MCLK_ENABLE)||(n==I2S_MCLK_DISABLE)) 255 /* Macro check I2S DMA mode */ 256 #define PARAM_I2S_DMA(n) ((n==I2S_DMA_1)||(n==I2S_DMA_2)) 257 /* Macro check I2S DMA depth value */ 258 #define PARAM_I2S_DMA_DEPTH(n) (n<=31) 259 /* Macro check I2S irq level value */ 260 #define PARAM_I2S_IRQ_LEVEL(n) (n<=31) 261 /* Macro check I2S half-period value */ 262 #define PARAM_I2S_HALFPERIOD(n) (n<512) 263 /* Macro check I2S bit-rate value */ 264 #define PARAM_I2S_BITRATE(n) (n<=63) 265 /** 266 * @} 267 */ 268 269 270 271 /* Public Types --------------------------------------------------------------- */ 272 /** @defgroup I2S_Public_Types I2S Public Types 273 * @{ 274 */ 275 276 /** 277 * @brief I2S configuration structure definition 278 */ 279 typedef struct { 280 uint8_t wordwidth; /** the number of bytes in data as follow: 281 -I2S_WORDWIDTH_8: 8 bit data 282 -I2S_WORDWIDTH_16: 16 bit data 283 -I2S_WORDWIDTH_32: 32 bit data */ 284 uint8_t mono; /** Set mono/stereo mode, should be: 285 - I2S_STEREO: stereo mode 286 - I2S_MONO: mono mode */ 287 uint8_t stop; /** Disables accesses on FIFOs, should be: 288 - I2S_STOP_ENABLE: enable stop mode 289 - I2S_STOP_DISABLE: disable stop mode */ 290 uint8_t reset; /** Asynchronously reset tje transmit channel and FIFO, should be: 291 - I2S_RESET_ENABLE: enable reset mode 292 - I2S_RESET_DISABLE: disable reset mode */ 293 uint8_t ws_sel; /** Set Master/Slave mode, should be: 294 - I2S_MASTER_MODE: I2S master mode 295 - I2S_SLAVE_MODE: I2S slave mode */ 296 uint8_t mute; /** MUTE mode: when true, the transmit channel sends only zeroes, shoule be: 297 - I2S_MUTE_ENABLE: enable mute mode 298 - I2S_MUTE_DISABLE: disable mute mode */ 299 uint8_t Reserved0[2]; 300 } I2S_CFG_Type; 301 302 /** 303 * @brief I2S DMA configuration structure definition 304 */ 305 typedef struct { 306 uint8_t DMAIndex; /** Select DMA1 or DMA2, should be: 307 - I2S_DMA_1: DMA1 308 - I2S_DMA_2: DMA2 */ 309 uint8_t depth; /** FIFO level that triggers a DMA request */ 310 uint8_t Reserved0[2]; 311 }I2S_DMAConf_Type; 312 313 /** 314 * @brief I2S mode configuration structure definition 315 */ 316 typedef struct{ 317 uint8_t clksel; /** Clock source selection, should be: 318 - I2S_CLKSEL_FRDCLK: Select the fractional rate divider clock output 319 - I2S_CLKSEL_MCLK: Select the MCLK signal as the clock source */ 320 uint8_t fpin; /** Select four pin mode, should be: 321 - I2S_4PIN_ENABLE: 4-pin enable 322 - I2S_4PIN_DISABLE: 4-pin disable */ 323 uint8_t mcena; /** Select MCLK mode, should be: 324 - I2S_MCLK_ENABLE: MCLK enable for output 325 - I2S_MCLK_DISABLE: MCLK disable for output */ 326 uint8_t Reserved; 327 }I2S_MODEConf_Type; 328 329 330 /** 331 * @} 332 */ 333 334 335 /* Public Functions ----------------------------------------------------------- */ 336 /** @defgroup I2S_Public_Functions I2S Public Functions 337 * @{ 338 */ 339 /* I2S Init/DeInit functions ---------*/ 340 void I2S_Init(LPC_I2S_TypeDef *I2Sx); 341 void I2S_DeInit(LPC_I2S_TypeDef *I2Sx); 342 343 /* I2S configuration functions --------*/ 344 void I2S_Config(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, I2S_CFG_Type* ConfigStruct); 345 Status I2S_FreqConfig(LPC_I2S_TypeDef *I2Sx, uint32_t Freq, uint8_t TRMode); 346 void I2S_SetBitRate(LPC_I2S_TypeDef *I2Sx, uint8_t bitrate, uint8_t TRMode); 347 void I2S_ModeConfig(LPC_I2S_TypeDef *I2Sx, I2S_MODEConf_Type* ModeConfig, uint8_t TRMode); 348 uint8_t I2S_GetLevel(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode); 349 350 /* I2S operate functions -------------*/ 351 void I2S_Send(LPC_I2S_TypeDef *I2Sx, uint32_t BufferData); 352 uint32_t I2S_Receive(LPC_I2S_TypeDef* I2Sx); 353 void I2S_Start(LPC_I2S_TypeDef *I2Sx); 354 void I2S_Pause(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode); 355 void I2S_Mute(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode); 356 void I2S_Stop(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode); 357 358 /* I2S DMA functions ----------------*/ 359 void I2S_DMAConfig(LPC_I2S_TypeDef *I2Sx, I2S_DMAConf_Type* DMAConfig, uint8_t TRMode); 360 void I2S_DMACmd(LPC_I2S_TypeDef *I2Sx, uint8_t DMAIndex,uint8_t TRMode, FunctionalState NewState); 361 362 /* I2S IRQ functions ----------------*/ 363 void I2S_IRQCmd(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode, FunctionalState NewState); 364 void I2S_IRQConfig(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, uint8_t level); 365 FunctionalState I2S_GetIRQStatus(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode); 366 uint8_t I2S_GetIRQDepth(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode); 367 368 /** 369 * @} 370 */ 371 372 373 #ifdef __cplusplus 374 } 375 #endif 376 377 378 #endif /* LPC17XX_SSP_H_ */ 379 380 /** 381 * @} 382 */ 383 384 /* --------------------------------- End Of File ------------------------------ */