lpc17xx_mcpwm.h (14109B)
1 /********************************************************************** 2 * $Id$ lpc17xx_mcpwm.h 2010-05-21 3 *//** 4 * @file lpc17xx_mcpwm.h 5 * @brief Contains all macro definitions and function prototypes 6 * support for Motor Control PWM firmware library on LPC17xx 7 * @version 2.0 8 * @date 21. May. 2010 9 * @author NXP MCU SW Application Team 10 * 11 * Copyright(C) 2010, NXP Semiconductor 12 * All rights reserved. 13 * 14 *********************************************************************** 15 * Software that is described herein is for illustrative purposes only 16 * which provides customers with programming information regarding the 17 * products. This software is supplied "AS IS" without any warranties. 18 * NXP Semiconductors assumes no responsibility or liability for the 19 * use of the software, conveys no license or title under any patent, 20 * copyright, or mask work right to the product. NXP Semiconductors 21 * reserves the right to make changes in the software without 22 * notification. NXP Semiconductors also make no representation or 23 * warranty that such application will be suitable for the specified 24 * use without further testing or modification. 25 * Permission to use, copy, modify, and distribute this software and its 26 * documentation is hereby granted, under NXP Semiconductors' 27 * relevant copyright in the software, without fee, provided that it 28 * is used in conjunction with NXP Semiconductors microcontrollers. This 29 * copyright, permission, and disclaimer notice must appear in all copies of 30 * this code. 31 **********************************************************************/ 32 33 /* Peripheral group ----------------------------------------------------------- */ 34 /** @defgroup MCPWM MCPWM (Motor Control PWM) 35 * @ingroup LPC1700CMSIS_FwLib_Drivers 36 * @{ 37 */ 38 39 #ifndef LPC17XX_MCPWM_H_ 40 #define LPC17XX_MCPWM_H_ 41 42 /* Includes ------------------------------------------------------------------- */ 43 #include "LPC17xx.h" 44 #include "lpc_types.h" 45 46 47 #ifdef __cplusplus 48 extern "C" 49 { 50 #endif 51 52 /* Public Macros -------------------------------------------------------------- */ 53 /** @defgroup MCPWM_Public_Macros MCPWM Public Macros 54 * @{ 55 */ 56 57 58 /** Edge aligned mode for channel in MCPWM */ 59 #define MCPWM_CHANNEL_EDGE_MODE ((uint32_t)(0)) 60 /** Center aligned mode for channel in MCPWM */ 61 #define MCPWM_CHANNEL_CENTER_MODE ((uint32_t)(1)) 62 63 /** Polarity of the MCOA and MCOB pins: Passive state is LOW, active state is HIGH */ 64 #define MCPWM_CHANNEL_PASSIVE_LO ((uint32_t)(0)) 65 /** Polarity of the MCOA and MCOB pins: Passive state is HIGH, active state is LOW */ 66 #define MCPWM_CHANNEL_PASSIVE_HI ((uint32_t)(1)) 67 68 /* Output Patent in 3-phase DC mode, the internal MCOA0 signal is routed to any or all of 69 * the six output pins under the control of the bits in this register */ 70 #define MCPWM_PATENT_A0 ((uint32_t)(1<<0)) /**< MCOA0 tracks internal MCOA0 */ 71 #define MCPWM_PATENT_B0 ((uint32_t)(1<<1)) /**< MCOB0 tracks internal MCOA0 */ 72 #define MCPWM_PATENT_A1 ((uint32_t)(1<<2)) /**< MCOA1 tracks internal MCOA0 */ 73 #define MCPWM_PATENT_B1 ((uint32_t)(1<<3)) /**< MCOB1 tracks internal MCOA0 */ 74 #define MCPWM_PATENT_A2 ((uint32_t)(1<<4)) /**< MCOA2 tracks internal MCOA0 */ 75 #define MCPWM_PATENT_B2 ((uint32_t)(1<<5)) /**< MCOB2 tracks internal MCOA0 */ 76 77 /* Interrupt type in MCPWM */ 78 /** Limit interrupt for channel (0) */ 79 #define MCPWM_INTFLAG_LIM0 MCPWM_INT_ILIM(0) 80 /** Match interrupt for channel (0) */ 81 #define MCPWM_INTFLAG_MAT0 MCPWM_INT_IMAT(0) 82 /** Capture interrupt for channel (0) */ 83 #define MCPWM_INTFLAG_CAP0 MCPWM_INT_ICAP(0) 84 85 /** Limit interrupt for channel (1) */ 86 #define MCPWM_INTFLAG_LIM1 MCPWM_INT_ILIM(1) 87 /** Match interrupt for channel (1) */ 88 #define MCPWM_INTFLAG_MAT1 MCPWM_INT_IMAT(1) 89 /** Capture interrupt for channel (1) */ 90 #define MCPWM_INTFLAG_CAP1 MCPWM_INT_ICAP(1) 91 92 /** Limit interrupt for channel (2) */ 93 #define MCPWM_INTFLAG_LIM2 MCPWM_INT_ILIM(2) 94 /** Match interrupt for channel (2) */ 95 #define MCPWM_INTFLAG_MAT2 MCPWM_INT_IMAT(2) 96 /** Capture interrupt for channel (2) */ 97 #define MCPWM_INTFLAG_CAP2 MCPWM_INT_ICAP(2) 98 99 /** Fast abort interrupt */ 100 #define MCPWM_INTFLAG_ABORT MCPWM_INT_ABORT 101 102 /** 103 * @} 104 */ 105 106 /* Private Macros ------------------------------------------------------------- */ 107 /** @defgroup MCPWM_Private_Macros MCPWM Private Macros 108 * @{ 109 */ 110 111 /*********************************************************************//** 112 * Macro defines for MCPWM Control register 113 **********************************************************************/ 114 /* MCPWM Control register, these macro definitions below can be applied for these 115 * register type: 116 * - MCPWM Control read address 117 * - MCPWM Control set address 118 * - MCPWM Control clear address 119 */ 120 #define MCPWM_CON_RUN(n) ((n<=2) ? ((uint32_t)(1<<((n*8)+0))) : (0)) /**< Stops/starts timer channel n */ 121 #define MCPWM_CON_CENTER(n) ((n<=2) ? ((uint32_t)(1<<((n*8)+1))) : (0)) /**< Edge/center aligned operation for channel n */ 122 #define MCPWM_CON_POLAR(n) ((n<=2) ? ((uint32_t)(1<<((n*8)+2))) : (0)) /**< Select polarity of the MCOAn and MCOBn pin */ 123 #define MCPWM_CON_DTE(n) ((n<=2) ? ((uint32_t)(1<<((n*8)+3))) : (0)) /**< Control the dead-time feature for channel n */ 124 #define MCPWM_CON_DISUP(n) ((n<=2) ? ((uint32_t)(1<<((n*8)+4))) : (0)) /**< Enable/Disable update of functional register for channel n */ 125 #define MCPWM_CON_INVBDC ((uint32_t)(1<<29)) /**< Control the polarity for all 3 channels */ 126 #define MCPWM_CON_ACMODE ((uint32_t)(1<<30)) /**< 3-phase AC mode select */ 127 #define MCPWM_CON_DCMODE ((uint32_t)(0x80000000)) /**< 3-phase DC mode select */ 128 129 /*********************************************************************//** 130 * Macro defines for MCPWM Capture Control register 131 **********************************************************************/ 132 /* Capture Control register, these macro definitions below can be applied for these 133 * register type: 134 * - MCPWM Capture Control read address 135 * - MCPWM Capture Control set address 136 * - MCPWM Capture control clear address 137 */ 138 /** Enables/Disable channel (cap) capture event on a rising edge on MCI(mci) */ 139 #define MCPWM_CAPCON_CAPMCI_RE(cap,mci) (((cap<=2)&&(mci<=2)) ? ((uint32_t)(1<<((cap*6)+(mci*2)+0))) : (0)) 140 /** Enables/Disable channel (cap) capture event on a falling edge on MCI(mci) */ 141 #define MCPWM_CAPCON_CAPMCI_FE(cap,mci) (((cap<=2)&&(mci<=2)) ? ((uint32_t)(1<<((cap*6)+(mci*2)+1))) : (0)) 142 /** TC(n) is reset by channel (n) capture event */ 143 #define MCPWM_CAPCON_RT(n) ((n<=2) ? ((uint32_t)(1<<(18+(n)))) : (0)) 144 /** Hardware noise filter: channel (n) capture events are delayed */ 145 #define MCPWM_CAPCON_HNFCAP(n) ((n<=2) ? ((uint32_t)(1<<(21+(n)))) : (0)) 146 147 /*********************************************************************//** 148 * Macro defines for MCPWM Interrupt register 149 **********************************************************************/ 150 /* Interrupt registers, these macro definitions below can be applied for these 151 * register type: 152 * - MCPWM Interrupt Enable read address 153 * - MCPWM Interrupt Enable set address 154 * - MCPWM Interrupt Enable clear address 155 * - MCPWM Interrupt Flags read address 156 * - MCPWM Interrupt Flags set address 157 * - MCPWM Interrupt Flags clear address 158 */ 159 /** Limit interrupt for channel (n) */ 160 #define MCPWM_INT_ILIM(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+0))) : (0)) 161 /** Match interrupt for channel (n) */ 162 #define MCPWM_INT_IMAT(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+1))) : (0)) 163 /** Capture interrupt for channel (n) */ 164 #define MCPWM_INT_ICAP(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+2))) : (0)) 165 /** Fast abort interrupt */ 166 #define MCPWM_INT_ABORT ((uint32_t)(1<<15)) 167 168 /*********************************************************************//** 169 * Macro defines for MCPWM Count Control register 170 **********************************************************************/ 171 /* MCPWM Count Control register, these macro definitions below can be applied for these 172 * register type: 173 * - MCPWM Count Control read address 174 * - MCPWM Count Control set address 175 * - MCPWM Count Control clear address 176 */ 177 /** Counter(tc) advances on a rising edge on MCI(mci) pin */ 178 #define MCPWM_CNTCON_TCMCI_RE(tc,mci) (((tc<=2)&&(mci<=2)) ? ((uint32_t)(1<<((6*tc)+(2*mci)+0))) : (0)) 179 /** Counter(cnt) advances on a falling edge on MCI(mci) pin */ 180 #define MCPWM_CNTCON_TCMCI_FE(tc,mci) (((tc<=2)&&(mci<=2)) ? ((uint32_t)(1<<((6*tc)+(2*mci)+1))) : (0)) 181 /** Channel (n) is in counter mode */ 182 #define MCPWM_CNTCON_CNTR(n) ((n<=2) ? ((uint32_t)(1<<(29+n))) : (0)) 183 184 /*********************************************************************//** 185 * Macro defines for MCPWM Dead-time register 186 **********************************************************************/ 187 /** Dead time value x for channel n */ 188 #define MCPWM_DT(n,x) ((n<=2) ? ((uint32_t)((x&0x3FF)<<(n*10))) : (0)) 189 190 /*********************************************************************//** 191 * Macro defines for MCPWM Communication Pattern register 192 **********************************************************************/ 193 #define MCPWM_CP_A0 ((uint32_t)(1<<0)) /**< MCOA0 tracks internal MCOA0 */ 194 #define MCPWM_CP_B0 ((uint32_t)(1<<1)) /**< MCOB0 tracks internal MCOA0 */ 195 #define MCPWM_CP_A1 ((uint32_t)(1<<2)) /**< MCOA1 tracks internal MCOA0 */ 196 #define MCPWM_CP_B1 ((uint32_t)(1<<3)) /**< MCOB1 tracks internal MCOA0 */ 197 #define MCPWM_CP_A2 ((uint32_t)(1<<4)) /**< MCOA2 tracks internal MCOA0 */ 198 #define MCPWM_CP_B2 ((uint32_t)(1<<5)) /**< MCOB2 tracks internal MCOA0 */ 199 200 /*********************************************************************//** 201 * Macro defines for MCPWM Capture clear address register 202 **********************************************************************/ 203 /** Clear the MCCAP (n) register */ 204 #define MCPWM_CAPCLR_CAP(n) ((n<=2) ? ((uint32_t)(1<<n)) : (0)) 205 206 207 /** 208 * @} 209 */ 210 211 212 /* Public Types --------------------------------------------------------------- */ 213 /** @defgroup MCPWM_Public_Types MCPWM Public Types 214 * @{ 215 */ 216 217 /** 218 * @brief Motor Control PWM Channel Configuration structure type definition 219 */ 220 typedef struct { 221 uint32_t channelType; /**< Edge/center aligned mode for this channel, 222 should be: 223 - MCPWM_CHANNEL_EDGE_MODE: Channel is in Edge mode 224 - MCPWM_CHANNEL_CENTER_MODE: Channel is in Center mode 225 */ 226 uint32_t channelPolarity; /**< Polarity of the MCOA and MCOB pins, should be: 227 - MCPWM_CHANNEL_PASSIVE_LO: Passive state is LOW, active state is HIGH 228 - MCPWM_CHANNEL_PASSIVE_HI: Passive state is HIGH, active state is LOW 229 */ 230 uint32_t channelDeadtimeEnable; /**< Enable/Disable DeadTime function for channel, should be: 231 - ENABLE. 232 - DISABLE. 233 */ 234 uint32_t channelDeadtimeValue; /**< DeadTime value, should be less than 0x3FF */ 235 uint32_t channelUpdateEnable; /**< Enable/Disable updates of functional registers, 236 should be: 237 - ENABLE. 238 - DISABLE. 239 */ 240 uint32_t channelTimercounterValue; /**< MCPWM Timer Counter value */ 241 uint32_t channelPeriodValue; /**< MCPWM Period value */ 242 uint32_t channelPulsewidthValue; /**< MCPWM Pulse Width value */ 243 } MCPWM_CHANNEL_CFG_Type; 244 245 /** 246 * @brief MCPWM Capture Configuration type definition 247 */ 248 typedef struct { 249 uint32_t captureChannel; /**< Capture Channel Number, should be in range from 0 to 2 */ 250 uint32_t captureRising; /**< Enable/Disable Capture on Rising Edge event, should be: 251 - ENABLE. 252 - DISABLE. 253 */ 254 uint32_t captureFalling; /**< Enable/Disable Capture on Falling Edge event, should be: 255 - ENABLE. 256 - DISABLE. 257 */ 258 uint32_t timerReset; /**< Enable/Disable Timer reset function an capture, should be: 259 - ENABLE. 260 - DISABLE. 261 */ 262 uint32_t hnfEnable; /**< Enable/Disable Hardware noise filter function, should be: 263 - ENABLE. 264 - DISABLE. 265 */ 266 } MCPWM_CAPTURE_CFG_Type; 267 268 269 /** 270 * @brief MCPWM Count Control Configuration type definition 271 */ 272 typedef struct { 273 uint32_t counterChannel; /**< Counter Channel Number, should be in range from 0 to 2 */ 274 uint32_t countRising; /**< Enable/Disable Capture on Rising Edge event, should be: 275 - ENABLE. 276 - DISABLE. 277 */ 278 uint32_t countFalling; /**< Enable/Disable Capture on Falling Edge event, should be: 279 - ENABLE. 280 - DISABLE. 281 */ 282 } MCPWM_COUNT_CFG_Type; 283 284 /** 285 * @} 286 */ 287 288 289 /* Public Functions ----------------------------------------------------------- */ 290 /** @defgroup MCPWM_Public_Functions MCPWM Public Functions 291 * @{ 292 */ 293 294 void MCPWM_Init(LPC_MCPWM_TypeDef *MCPWMx); 295 void MCPWM_ConfigChannel(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum, 296 MCPWM_CHANNEL_CFG_Type * channelSetup); 297 void MCPWM_WriteToShadow(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum, 298 MCPWM_CHANNEL_CFG_Type *channelSetup); 299 void MCPWM_ConfigCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum, 300 MCPWM_CAPTURE_CFG_Type *captureConfig); 301 void MCPWM_ClearCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t captureChannel); 302 uint32_t MCPWM_GetCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t captureChannel); 303 void MCPWM_CountConfig(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum, 304 uint32_t countMode, MCPWM_COUNT_CFG_Type *countConfig); 305 void MCPWM_Start(LPC_MCPWM_TypeDef *MCPWMx,uint32_t channel0, uint32_t channel1, uint32_t channel2); 306 void MCPWM_Stop(LPC_MCPWM_TypeDef *MCPWMx,uint32_t channel0, uint32_t channel1, uint32_t channel2); 307 void MCPWM_ACMode(LPC_MCPWM_TypeDef *MCPWMx,uint32_t acMode); 308 void MCPWM_DCMode(LPC_MCPWM_TypeDef *MCPWMx, uint32_t dcMode, 309 uint32_t outputInvered, uint32_t outputPattern); 310 void MCPWM_IntConfig(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType, FunctionalState NewState); 311 void MCPWM_IntSet(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType); 312 void MCPWM_IntClear(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType); 313 FlagStatus MCPWM_GetIntStatus(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType); 314 315 /** 316 * @} 317 */ 318 319 #ifdef __cplusplus 320 } 321 #endif 322 323 #endif /* LPC17XX_MCPWM_H_ */ 324 325 /** 326 * @} 327 */ 328 329 /* --------------------------------- End Of File ------------------------------ */