lpc17xx_qei.h (24762B)
1 /********************************************************************** 2 * $Id$ lpc17xx_qei.h 2010-05-21 3 *//** 4 * @file lpc17xx_qei.h 5 * @brief Contains all macro definitions and function prototypes 6 * support for QEI firmware library on LPC17xx 7 * @version 2.0 8 * @date 21. May. 2010 9 * @author NXP MCU SW Application Team 10 * 11 * Copyright(C) 2010, NXP Semiconductor 12 * All rights reserved. 13 * 14 *********************************************************************** 15 * Software that is described herein is for illustrative purposes only 16 * which provides customers with programming information regarding the 17 * products. This software is supplied "AS IS" without any warranties. 18 * NXP Semiconductors assumes no responsibility or liability for the 19 * use of the software, conveys no license or title under any patent, 20 * copyright, or mask work right to the product. NXP Semiconductors 21 * reserves the right to make changes in the software without 22 * notification. NXP Semiconductors also make no representation or 23 * warranty that such application will be suitable for the specified 24 * use without further testing or modification. 25 * Permission to use, copy, modify, and distribute this software and its 26 * documentation is hereby granted, under NXP Semiconductors' 27 * relevant copyright in the software, without fee, provided that it 28 * is used in conjunction with NXP Semiconductors microcontrollers. This 29 * copyright, permission, and disclaimer notice must appear in all copies of 30 * this code. 31 **********************************************************************/ 32 33 /* Peripheral group ----------------------------------------------------------- */ 34 /** @defgroup QEI QEI (Quadrature Encoder Interface) 35 * @ingroup LPC1700CMSIS_FwLib_Drivers 36 * @{ 37 */ 38 39 #ifndef LPC17XX_QEI_H_ 40 #define LPC17XX_QEI_H_ 41 42 /* Includes ------------------------------------------------------------------- */ 43 #include "LPC17xx.h" 44 #include "lpc_types.h" 45 46 47 #ifdef __cplusplus 48 extern "C" 49 { 50 #endif 51 52 /* Public Macros -------------------------------------------------------------- */ 53 /** @defgroup QEI_Public_Macros QEI Public Macros 54 * @{ 55 */ 56 57 /* QEI Reset types */ 58 #define QEI_RESET_POS QEI_CON_RESP /**< Reset position counter */ 59 #define QEI_RESET_POSOnIDX QEI_CON_RESPI /**< Reset Posistion Counter on Index */ 60 #define QEI_RESET_VEL QEI_CON_RESV /**< Reset Velocity */ 61 #define QEI_RESET_IDX QEI_CON_RESI /**< Reset Index Counter */ 62 63 /* QEI Direction Invert Type Option */ 64 #define QEI_DIRINV_NONE ((uint32_t)(0)) /**< Direction is not inverted */ 65 #define QEI_DIRINV_CMPL ((uint32_t)(1)) /**< Direction is complemented */ 66 67 /* QEI Signal Mode Option */ 68 #define QEI_SIGNALMODE_QUAD ((uint32_t)(0)) /**< Signal operation: Quadrature phase mode */ 69 #define QEI_SIGNALMODE_CLKDIR ((uint32_t)(1)) /**< Signal operation: Clock/Direction mode */ 70 71 /* QEI Capture Mode Option */ 72 #define QEI_CAPMODE_2X ((uint32_t)(0)) /**< Capture mode: Only Phase-A edges are counted (2X) */ 73 #define QEI_CAPMODE_4X ((uint32_t)(1)) /**< Capture mode: BOTH PhA and PhB edges are counted (4X)*/ 74 75 /* QEI Invert Index Signal Option */ 76 #define QEI_INVINX_NONE ((uint32_t)(0)) /**< Invert Index signal option: None */ 77 #define QEI_INVINX_EN ((uint32_t)(1)) /**< Invert Index signal option: Enable */ 78 79 /* QEI timer reload option */ 80 #define QEI_TIMERRELOAD_TICKVAL ((uint8_t)(0)) /**< Reload value in absolute value */ 81 #define QEI_TIMERRELOAD_USVAL ((uint8_t)(1)) /**< Reload value in microsecond value */ 82 83 /* QEI Flag Status type */ 84 #define QEI_STATUS_DIR ((uint32_t)(1<<0)) /**< Direction status */ 85 86 /* QEI Compare Position channel option */ 87 #define QEI_COMPPOS_CH_0 ((uint8_t)(0)) /**< QEI compare position channel 0 */ 88 #define QEI_COMPPOS_CH_1 ((uint8_t)(1)) /**< QEI compare position channel 1 */ 89 #define QEI_COMPPOS_CH_2 ((uint8_t)(2)) /**< QEI compare position channel 2 */ 90 91 /* QEI interrupt flag type */ 92 #define QEI_INTFLAG_INX_Int ((uint32_t)(1<<0)) /**< index pulse was detected interrupt */ 93 #define QEI_INTFLAG_TIM_Int ((uint32_t)(1<<1)) /**< Velocity timer over flow interrupt */ 94 #define QEI_INTFLAG_VELC_Int ((uint32_t)(1<<2)) /**< Capture velocity is less than compare interrupt */ 95 #define QEI_INTFLAG_DIR_Int ((uint32_t)(1<<3)) /**< Change of direction interrupt */ 96 #define QEI_INTFLAG_ERR_Int ((uint32_t)(1<<4)) /**< An encoder phase error interrupt */ 97 #define QEI_INTFLAG_ENCLK_Int ((uint32_t)(1<<5)) /**< An encoder clock pulse was detected interrupt */ 98 #define QEI_INTFLAG_POS0_Int ((uint32_t)(1<<6)) /**< position 0 compare value is equal to the 99 current position interrupt */ 100 #define QEI_INTFLAG_POS1_Int ((uint32_t)(1<<7)) /**< position 1 compare value is equal to the 101 current position interrupt */ 102 #define QEI_INTFLAG_POS2_Int ((uint32_t)(1<<8)) /**< position 2 compare value is equal to the 103 current position interrupt */ 104 #define QEI_INTFLAG_REV_Int ((uint32_t)(1<<9)) /**< Index compare value is equal to the current 105 index count interrupt */ 106 #define QEI_INTFLAG_POS0REV_Int ((uint32_t)(1<<10)) /**< Combined position 0 and revolution count interrupt */ 107 #define QEI_INTFLAG_POS1REV_Int ((uint32_t)(1<<11)) /**< Combined position 1 and revolution count interrupt */ 108 #define QEI_INTFLAG_POS2REV_Int ((uint32_t)(1<<12)) /**< Combined position 2 and revolution count interrupt */ 109 110 /** 111 * @} 112 */ 113 114 115 /* Private Macros ------------------------------------------------------------- */ 116 /** @defgroup QEI_Private_Macros QEI Private Macros 117 * @{ 118 */ 119 120 /* --------------------- BIT DEFINITIONS -------------------------------------- */ 121 /* Quadrature Encoder Interface Control Register Definition --------------------- */ 122 /*********************************************************************//** 123 * Macro defines for QEI Control register 124 **********************************************************************/ 125 #define QEI_CON_RESP ((uint32_t)(1<<0)) /**< Reset position counter */ 126 #define QEI_CON_RESPI ((uint32_t)(1<<1)) /**< Reset Posistion Counter on Index */ 127 #define QEI_CON_RESV ((uint32_t)(1<<2)) /**< Reset Velocity */ 128 #define QEI_CON_RESI ((uint32_t)(1<<3)) /**< Reset Index Counter */ 129 #define QEI_CON_BITMASK ((uint32_t)(0x0F)) /**< QEI Control register bit-mask */ 130 131 /*********************************************************************//** 132 * Macro defines for QEI Configuration register 133 **********************************************************************/ 134 #define QEI_CONF_DIRINV ((uint32_t)(1<<0)) /**< Direction Invert */ 135 #define QEI_CONF_SIGMODE ((uint32_t)(1<<1)) /**< Signal mode */ 136 #define QEI_CONF_CAPMODE ((uint32_t)(1<<2)) /**< Capture mode */ 137 #define QEI_CONF_INVINX ((uint32_t)(1<<3)) /**< Invert index */ 138 #define QEI_CONF_BITMASK ((uint32_t)(0x0F)) /**< QEI Configuration register bit-mask */ 139 140 /*********************************************************************//** 141 * Macro defines for QEI Status register 142 **********************************************************************/ 143 #define QEI_STAT_DIR ((uint32_t)(1<<0)) /**< Direction bit */ 144 #define QEI_STAT_BITMASK ((uint32_t)(1<<0)) /**< QEI status register bit-mask */ 145 146 /* Quadrature Encoder Interface Interrupt registers definitions --------------------- */ 147 /*********************************************************************//** 148 * Macro defines for QEI Interrupt Status register 149 **********************************************************************/ 150 #define QEI_INTSTAT_INX_Int ((uint32_t)(1<<0)) /**< Indicates that an index pulse was detected */ 151 #define QEI_INTSTAT_TIM_Int ((uint32_t)(1<<1)) /**< Indicates that a velocity timer overflow occurred */ 152 #define QEI_INTSTAT_VELC_Int ((uint32_t)(1<<2)) /**< Indicates that capture velocity is less than compare velocity */ 153 #define QEI_INTSTAT_DIR_Int ((uint32_t)(1<<3)) /**< Indicates that a change of direction was detected */ 154 #define QEI_INTSTAT_ERR_Int ((uint32_t)(1<<4)) /**< Indicates that an encoder phase error was detected */ 155 #define QEI_INTSTAT_ENCLK_Int ((uint32_t)(1<<5)) /**< Indicates that and encoder clock pulse was detected */ 156 #define QEI_INTSTAT_POS0_Int ((uint32_t)(1<<6)) /**< Indicates that the position 0 compare value is equal to the 157 current position */ 158 #define QEI_INTSTAT_POS1_Int ((uint32_t)(1<<7)) /**< Indicates that the position 1compare value is equal to the 159 current position */ 160 #define QEI_INTSTAT_POS2_Int ((uint32_t)(1<<8)) /**< Indicates that the position 2 compare value is equal to the 161 current position */ 162 #define QEI_INTSTAT_REV_Int ((uint32_t)(1<<9)) /**< Indicates that the index compare value is equal to the current 163 index count */ 164 #define QEI_INTSTAT_POS0REV_Int ((uint32_t)(1<<10)) /**< Combined position 0 and revolution count interrupt. Set when 165 both the POS0_Int bit is set and the REV_Int is set */ 166 #define QEI_INTSTAT_POS1REV_Int ((uint32_t)(1<<11)) /**< Combined position 1 and revolution count interrupt. Set when 167 both the POS1_Int bit is set and the REV_Int is set */ 168 #define QEI_INTSTAT_POS2REV_Int ((uint32_t)(1<<12)) /**< Combined position 2 and revolution count interrupt. Set when 169 both the POS2_Int bit is set and the REV_Int is set */ 170 #define QEI_INTSTAT_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Status register bit-mask */ 171 172 /*********************************************************************//** 173 * Macro defines for QEI Interrupt Set register 174 **********************************************************************/ 175 #define QEI_INTSET_INX_Int ((uint32_t)(1<<0)) /**< Set Bit Indicates that an index pulse was detected */ 176 #define QEI_INTSET_TIM_Int ((uint32_t)(1<<1)) /**< Set Bit Indicates that a velocity timer overflow occurred */ 177 #define QEI_INTSET_VELC_Int ((uint32_t)(1<<2)) /**< Set Bit Indicates that capture velocity is less than compare velocity */ 178 #define QEI_INTSET_DIR_Int ((uint32_t)(1<<3)) /**< Set Bit Indicates that a change of direction was detected */ 179 #define QEI_INTSET_ERR_Int ((uint32_t)(1<<4)) /**< Set Bit Indicates that an encoder phase error was detected */ 180 #define QEI_INTSET_ENCLK_Int ((uint32_t)(1<<5)) /**< Set Bit Indicates that and encoder clock pulse was detected */ 181 #define QEI_INTSET_POS0_Int ((uint32_t)(1<<6)) /**< Set Bit Indicates that the position 0 compare value is equal to the 182 current position */ 183 #define QEI_INTSET_POS1_Int ((uint32_t)(1<<7)) /**< Set Bit Indicates that the position 1compare value is equal to the 184 current position */ 185 #define QEI_INTSET_POS2_Int ((uint32_t)(1<<8)) /**< Set Bit Indicates that the position 2 compare value is equal to the 186 current position */ 187 #define QEI_INTSET_REV_Int ((uint32_t)(1<<9)) /**< Set Bit Indicates that the index compare value is equal to the current 188 index count */ 189 #define QEI_INTSET_POS0REV_Int ((uint32_t)(1<<10)) /**< Set Bit that combined position 0 and revolution count interrupt */ 190 #define QEI_INTSET_POS1REV_Int ((uint32_t)(1<<11)) /**< Set Bit that Combined position 1 and revolution count interrupt */ 191 #define QEI_INTSET_POS2REV_Int ((uint32_t)(1<<12)) /**< Set Bit that Combined position 2 and revolution count interrupt */ 192 #define QEI_INTSET_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Set register bit-mask */ 193 194 /*********************************************************************//** 195 * Macro defines for QEI Interrupt Clear register 196 **********************************************************************/ 197 #define QEI_INTCLR_INX_Int ((uint32_t)(1<<0)) /**< Clear Bit Indicates that an index pulse was detected */ 198 #define QEI_INTCLR_TIM_Int ((uint32_t)(1<<1)) /**< Clear Bit Indicates that a velocity timer overflow occurred */ 199 #define QEI_INTCLR_VELC_Int ((uint32_t)(1<<2)) /**< Clear Bit Indicates that capture velocity is less than compare velocity */ 200 #define QEI_INTCLR_DIR_Int ((uint32_t)(1<<3)) /**< Clear Bit Indicates that a change of direction was detected */ 201 #define QEI_INTCLR_ERR_Int ((uint32_t)(1<<4)) /**< Clear Bit Indicates that an encoder phase error was detected */ 202 #define QEI_INTCLR_ENCLK_Int ((uint32_t)(1<<5)) /**< Clear Bit Indicates that and encoder clock pulse was detected */ 203 #define QEI_INTCLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Bit Indicates that the position 0 compare value is equal to the 204 current position */ 205 #define QEI_INTCLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Bit Indicates that the position 1compare value is equal to the 206 current position */ 207 #define QEI_INTCLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Bit Indicates that the position 2 compare value is equal to the 208 current position */ 209 #define QEI_INTCLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Bit Indicates that the index compare value is equal to the current 210 index count */ 211 #define QEI_INTCLR_POS0REV_Int ((uint32_t)(1<<10)) /**< Clear Bit that combined position 0 and revolution count interrupt */ 212 #define QEI_INTCLR_POS1REV_Int ((uint32_t)(1<<11)) /**< Clear Bit that Combined position 1 and revolution count interrupt */ 213 #define QEI_INTCLR_POS2REV_Int ((uint32_t)(1<<12)) /**< Clear Bit that Combined position 2 and revolution count interrupt */ 214 #define QEI_INTCLR_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Clear register bit-mask */ 215 216 /*********************************************************************//** 217 * Macro defines for QEI Interrupt Enable register 218 **********************************************************************/ 219 #define QEI_INTEN_INX_Int ((uint32_t)(1<<0)) /**< Enabled Interrupt Bit Indicates that an index pulse was detected */ 220 #define QEI_INTEN_TIM_Int ((uint32_t)(1<<1)) /**< Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */ 221 #define QEI_INTEN_VELC_Int ((uint32_t)(1<<2)) /**< Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */ 222 #define QEI_INTEN_DIR_Int ((uint32_t)(1<<3)) /**< Enabled Interrupt Bit Indicates that a change of direction was detected */ 223 #define QEI_INTEN_ERR_Int ((uint32_t)(1<<4)) /**< Enabled Interrupt Bit Indicates that an encoder phase error was detected */ 224 #define QEI_INTEN_ENCLK_Int ((uint32_t)(1<<5)) /**< Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */ 225 #define QEI_INTEN_POS0_Int ((uint32_t)(1<<6)) /**< Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the 226 current position */ 227 #define QEI_INTEN_POS1_Int ((uint32_t)(1<<7)) /**< Enabled Interrupt Bit Indicates that the position 1compare value is equal to the 228 current position */ 229 #define QEI_INTEN_POS2_Int ((uint32_t)(1<<8)) /**< Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the 230 current position */ 231 #define QEI_INTEN_REV_Int ((uint32_t)(1<<9)) /**< Enabled Interrupt Bit Indicates that the index compare value is equal to the current 232 index count */ 233 #define QEI_INTEN_POS0REV_Int ((uint32_t)(1<<10)) /**< Enabled Interrupt Bit that combined position 0 and revolution count interrupt */ 234 #define QEI_INTEN_POS1REV_Int ((uint32_t)(1<<11)) /**< Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */ 235 #define QEI_INTEN_POS2REV_Int ((uint32_t)(1<<12)) /**< Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */ 236 #define QEI_INTEN_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable register bit-mask */ 237 238 /*********************************************************************//** 239 * Macro defines for QEI Interrupt Enable Set register 240 **********************************************************************/ 241 #define QEI_IESET_INX_Int ((uint32_t)(1<<0)) /**< Set Enable Interrupt Bit Indicates that an index pulse was detected */ 242 #define QEI_IESET_TIM_Int ((uint32_t)(1<<1)) /**< Set Enable Interrupt Bit Indicates that a velocity timer overflow occurred */ 243 #define QEI_IESET_VELC_Int ((uint32_t)(1<<2)) /**< Set Enable Interrupt Bit Indicates that capture velocity is less than compare velocity */ 244 #define QEI_IESET_DIR_Int ((uint32_t)(1<<3)) /**< Set Enable Interrupt Bit Indicates that a change of direction was detected */ 245 #define QEI_IESET_ERR_Int ((uint32_t)(1<<4)) /**< Set Enable Interrupt Bit Indicates that an encoder phase error was detected */ 246 #define QEI_IESET_ENCLK_Int ((uint32_t)(1<<5)) /**< Set Enable Interrupt Bit Indicates that and encoder clock pulse was detected */ 247 #define QEI_IESET_POS0_Int ((uint32_t)(1<<6)) /**< Set Enable Interrupt Bit Indicates that the position 0 compare value is equal to the 248 current position */ 249 #define QEI_IESET_POS1_Int ((uint32_t)(1<<7)) /**< Set Enable Interrupt Bit Indicates that the position 1compare value is equal to the 250 current position */ 251 #define QEI_IESET_POS2_Int ((uint32_t)(1<<8)) /**< Set Enable Interrupt Bit Indicates that the position 2 compare value is equal to the 252 current position */ 253 #define QEI_IESET_REV_Int ((uint32_t)(1<<9)) /**< Set Enable Interrupt Bit Indicates that the index compare value is equal to the current 254 index count */ 255 #define QEI_IESET_POS0REV_Int ((uint32_t)(1<<10)) /**< Set Enable Interrupt Bit that combined position 0 and revolution count interrupt */ 256 #define QEI_IESET_POS1REV_Int ((uint32_t)(1<<11)) /**< Set Enable Interrupt Bit that Combined position 1 and revolution count interrupt */ 257 #define QEI_IESET_POS2REV_Int ((uint32_t)(1<<12)) /**< Set Enable Interrupt Bit that Combined position 2 and revolution count interrupt */ 258 #define QEI_IESET_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable Set register bit-mask */ 259 260 /*********************************************************************//** 261 * Macro defines for QEI Interrupt Enable Clear register 262 **********************************************************************/ 263 #define QEI_IECLR_INX_Int ((uint32_t)(1<<0)) /**< Clear Enabled Interrupt Bit Indicates that an index pulse was detected */ 264 #define QEI_IECLR_TIM_Int ((uint32_t)(1<<1)) /**< Clear Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */ 265 #define QEI_IECLR_VELC_Int ((uint32_t)(1<<2)) /**< Clear Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */ 266 #define QEI_IECLR_DIR_Int ((uint32_t)(1<<3)) /**< Clear Enabled Interrupt Bit Indicates that a change of direction was detected */ 267 #define QEI_IECLR_ERR_Int ((uint32_t)(1<<4)) /**< Clear Enabled Interrupt Bit Indicates that an encoder phase error was detected */ 268 #define QEI_IECLR_ENCLK_Int ((uint32_t)(1<<5)) /**< Clear Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */ 269 #define QEI_IECLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the 270 current position */ 271 #define QEI_IECLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Enabled Interrupt Bit Indicates that the position 1compare value is equal to the 272 current position */ 273 #define QEI_IECLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the 274 current position */ 275 #define QEI_IECLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Enabled Interrupt Bit Indicates that the index compare value is equal to the current 276 index count */ 277 #define QEI_IECLR_POS0REV_Int ((uint32_t)(1<<10)) /**< Clear Enabled Interrupt Bit that combined position 0 and revolution count interrupt */ 278 #define QEI_IECLR_POS1REV_Int ((uint32_t)(1<<11)) /**< Clear Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */ 279 #define QEI_IECLR_POS2REV_Int ((uint32_t)(1<<12)) /**< Clear Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */ 280 #define QEI_IECLR_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable Clear register bit-mask */ 281 282 283 /* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */ 284 /* Macro check QEI peripheral */ 285 #define PARAM_QEIx(n) ((n==LPC_QEI)) 286 287 /* Macro check QEI reset type */ 288 #define PARAM_QEI_RESET(n) ((n==QEI_CON_RESP) \ 289 || (n==QEI_RESET_POSOnIDX) \ 290 || (n==QEI_RESET_VEL) \ 291 || (n==QEI_RESET_IDX)) 292 293 /* Macro check QEI Direction invert mode */ 294 #define PARAM_QEI_DIRINV(n) ((n==QEI_DIRINV_NONE) || (n==QEI_DIRINV_CMPL)) 295 296 /* Macro check QEI signal mode */ 297 #define PARAM_QEI_SIGNALMODE(n) ((n==QEI_SIGNALMODE_QUAD) || (n==QEI_SIGNALMODE_CLKDIR)) 298 299 /* Macro check QEI Capture mode */ 300 #define PARAM_QEI_CAPMODE(n) ((n==QEI_CAPMODE_2X) || (n==QEI_CAPMODE_4X)) 301 302 /* Macro check QEI Invert index mode */ 303 #define PARAM_QEI_INVINX(n) ((n==QEI_INVINX_NONE) || (n==QEI_INVINX_EN)) 304 305 /* Macro check QEI Direction invert mode */ 306 #define PARAM_QEI_TIMERRELOAD(n) ((n==QEI_TIMERRELOAD_TICKVAL) || (n==QEI_TIMERRELOAD_USVAL)) 307 308 /* Macro check QEI status type */ 309 #define PARAM_QEI_STATUS(n) ((n==QEI_STATUS_DIR)) 310 311 /* Macro check QEI combine position type */ 312 #define PARAM_QEI_COMPPOS_CH(n) ((n==QEI_COMPPOS_CH_0) || (n==QEI_COMPPOS_CH_1) || (n==QEI_COMPPOS_CH_2)) 313 314 /* Macro check QEI interrupt flag type */ 315 #define PARAM_QEI_INTFLAG(n) ((n==QEI_INTFLAG_INX_Int) \ 316 || (n==QEI_INTFLAG_TIM_Int) \ 317 || (n==QEI_INTFLAG_VELC_Int) \ 318 || (n==QEI_INTFLAG_DIR_Int) \ 319 || (n==QEI_INTFLAG_ERR_Int) \ 320 || (n==QEI_INTFLAG_ENCLK_Int) \ 321 || (n==QEI_INTFLAG_POS0_Int) \ 322 || (n==QEI_INTFLAG_POS1_Int) \ 323 || (n==QEI_INTFLAG_POS2_Int) \ 324 || (n==QEI_INTFLAG_REV_Int) \ 325 || (n==QEI_INTFLAG_POS0REV_Int) \ 326 || (n==QEI_INTFLAG_POS1REV_Int) \ 327 || (n==QEI_INTFLAG_POS2REV_Int)) 328 /** 329 * @} 330 */ 331 332 /* Public Types --------------------------------------------------------------- */ 333 /** @defgroup QEI_Public_Types QEI Public Types 334 * @{ 335 */ 336 337 /** 338 * @brief QEI Configuration structure type definition 339 */ 340 typedef struct { 341 uint32_t DirectionInvert :1; /**< Direction invert option: 342 - QEI_DIRINV_NONE: QEI Direction is normal 343 - QEI_DIRINV_CMPL: QEI Direction is complemented 344 */ 345 uint32_t SignalMode :1; /**< Signal mode Option: 346 - QEI_SIGNALMODE_QUAD: Signal is in Quadrature phase mode 347 - QEI_SIGNALMODE_CLKDIR: Signal is in Clock/Direction mode 348 */ 349 uint32_t CaptureMode :1; /**< Capture Mode Option: 350 - QEI_CAPMODE_2X: Only Phase-A edges are counted (2X) 351 - QEI_CAPMODE_4X: BOTH Phase-A and Phase-B edges are counted (4X) 352 */ 353 uint32_t InvertIndex :1; /**< Invert Index Option: 354 - QEI_INVINX_NONE: the sense of the index input is normal 355 - QEI_INVINX_EN: inverts the sense of the index input 356 */ 357 } QEI_CFG_Type; 358 359 /** 360 * @brief Timer Reload Configuration structure type definition 361 */ 362 typedef struct { 363 364 uint8_t ReloadOption; /**< Velocity Timer Reload Option, should be: 365 - QEI_TIMERRELOAD_TICKVAL: Reload value in absolute value 366 - QEI_TIMERRELOAD_USVAL: Reload value in microsecond value 367 */ 368 uint8_t Reserved[3]; 369 uint32_t ReloadValue; /**< Velocity Timer Reload Value, 32-bit long, should be matched 370 with Velocity Timer Reload Option 371 */ 372 } QEI_RELOADCFG_Type; 373 374 /** 375 * @} 376 */ 377 378 379 380 381 382 /* Public Functions ----------------------------------------------------------- */ 383 /** @defgroup QEI_Public_Functions QEI Public Functions 384 * @{ 385 */ 386 387 void QEI_Reset(LPC_QEI_TypeDef *QEIx, uint32_t ulResetType); 388 void QEI_Init(LPC_QEI_TypeDef *QEIx, QEI_CFG_Type *QEI_ConfigStruct); 389 void QEI_ConfigStructInit(QEI_CFG_Type *QIE_InitStruct); 390 void QEI_DeInit(LPC_QEI_TypeDef *QEIx); 391 FlagStatus QEI_GetStatus(LPC_QEI_TypeDef *QEIx, uint32_t ulFlagType); 392 uint32_t QEI_GetPosition(LPC_QEI_TypeDef *QEIx); 393 void QEI_SetMaxPosition(LPC_QEI_TypeDef *QEIx, uint32_t ulMaxPos); 394 void QEI_SetPositionComp(LPC_QEI_TypeDef *QEIx, uint8_t bPosCompCh, uint32_t ulPosComp); 395 uint32_t QEI_GetIndex(LPC_QEI_TypeDef *QEIx); 396 void QEI_SetIndexComp(LPC_QEI_TypeDef *QEIx, uint32_t ulIndexComp); 397 void QEI_SetTimerReload(LPC_QEI_TypeDef *QEIx, QEI_RELOADCFG_Type *QEIReloadStruct); 398 uint32_t QEI_GetTimer(LPC_QEI_TypeDef *QEIx); 399 uint32_t QEI_GetVelocity(LPC_QEI_TypeDef *QEIx); 400 uint32_t QEI_GetVelocityCap(LPC_QEI_TypeDef *QEIx); 401 void QEI_SetVelocityComp(LPC_QEI_TypeDef *QEIx, uint32_t ulVelComp); 402 void QEI_SetDigiFilter(LPC_QEI_TypeDef *QEIx, uint32_t ulSamplingPulse); 403 FlagStatus QEI_GetIntStatus(LPC_QEI_TypeDef *QEIx, uint32_t ulIntType); 404 void QEI_IntCmd(LPC_QEI_TypeDef *QEIx, uint32_t ulIntType, FunctionalState NewState); 405 void QEI_IntSet(LPC_QEI_TypeDef *QEIx, uint32_t ulIntType); 406 void QEI_IntClear(LPC_QEI_TypeDef *QEIx, uint32_t ulIntType); 407 uint32_t QEI_CalculateRPM(LPC_QEI_TypeDef *QEIx, uint32_t ulVelCapValue, uint32_t ulPPR); 408 409 410 /** 411 * @} 412 */ 413 414 #ifdef __cplusplus 415 } 416 #endif 417 418 #endif /* LPC17XX_QEI_H_ */ 419 420 /** 421 * @} 422 */ 423 424 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