lpc17xx_ssp.h (18381B)
1 /********************************************************************** 2 * $Id$ lpc17xx_ssp.h 2010-06-18 3 *//** 4 * @file lpc17xx_ssp.h 5 * @brief Contains all macro definitions and function prototypes 6 * support for SSP firmware library on LPC17xx 7 * @version 3.0 8 * @date 18. June. 2010 9 * @author NXP MCU SW Application Team 10 * 11 * Copyright(C) 2010, NXP Semiconductor 12 * All rights reserved. 13 * 14 *********************************************************************** 15 * Software that is described herein is for illustrative purposes only 16 * which provides customers with programming information regarding the 17 * products. This software is supplied "AS IS" without any warranties. 18 * NXP Semiconductors assumes no responsibility or liability for the 19 * use of the software, conveys no license or title under any patent, 20 * copyright, or mask work right to the product. NXP Semiconductors 21 * reserves the right to make changes in the software without 22 * notification. NXP Semiconductors also make no representation or 23 * warranty that such application will be suitable for the specified 24 * use without further testing or modification. 25 * Permission to use, copy, modify, and distribute this software and its 26 * documentation is hereby granted, under NXP Semiconductors' 27 * relevant copyright in the software, without fee, provided that it 28 * is used in conjunction with NXP Semiconductors microcontrollers. This 29 * copyright, permission, and disclaimer notice must appear in all copies of 30 * this code. 31 **********************************************************************/ 32 33 /* Peripheral group ----------------------------------------------------------- */ 34 /** @defgroup SSP SSP (Synchronous Serial Port) 35 * @ingroup LPC1700CMSIS_FwLib_Drivers 36 * @{ 37 */ 38 39 #ifndef LPC17XX_SSP_H_ 40 #define LPC17XX_SSP_H_ 41 42 /* Includes ------------------------------------------------------------------- */ 43 #include "LPC17xx.h" 44 #include "lpc_types.h" 45 46 47 #ifdef __cplusplus 48 extern "C" 49 { 50 #endif 51 52 /* Public Macros -------------------------------------------------------------- */ 53 /** @defgroup SSP_Public_Macros SSP Public Macros 54 * @{ 55 */ 56 57 /*********************************************************************//** 58 * SSP configuration parameter defines 59 **********************************************************************/ 60 /** Clock phase control bit */ 61 #define SSP_CPHA_FIRST ((uint32_t)(0)) 62 #define SSP_CPHA_SECOND SSP_CR0_CPHA_SECOND 63 64 65 /** Clock polarity control bit */ 66 /* There's no bug here!!! 67 * - If bit[6] in SSPnCR0 is 0: SSP controller maintains the bus clock low between frames. 68 * That means the active clock is in HI state. 69 * - If bit[6] in SSPnCR0 is 1 (SSP_CR0_CPOL_HI): SSP controller maintains the bus clock 70 * high between frames. That means the active clock is in LO state. 71 */ 72 #define SSP_CPOL_HI ((uint32_t)(0)) 73 #define SSP_CPOL_LO SSP_CR0_CPOL_HI 74 75 /** SSP master mode enable */ 76 #define SSP_SLAVE_MODE SSP_CR1_SLAVE_EN 77 #define SSP_MASTER_MODE ((uint32_t)(0)) 78 79 /** SSP data bit number defines */ 80 #define SSP_DATABIT_4 SSP_CR0_DSS(4) /*!< Databit number = 4 */ 81 #define SSP_DATABIT_5 SSP_CR0_DSS(5) /*!< Databit number = 5 */ 82 #define SSP_DATABIT_6 SSP_CR0_DSS(6) /*!< Databit number = 6 */ 83 #define SSP_DATABIT_7 SSP_CR0_DSS(7) /*!< Databit number = 7 */ 84 #define SSP_DATABIT_8 SSP_CR0_DSS(8) /*!< Databit number = 8 */ 85 #define SSP_DATABIT_9 SSP_CR0_DSS(9) /*!< Databit number = 9 */ 86 #define SSP_DATABIT_10 SSP_CR0_DSS(10) /*!< Databit number = 10 */ 87 #define SSP_DATABIT_11 SSP_CR0_DSS(11) /*!< Databit number = 11 */ 88 #define SSP_DATABIT_12 SSP_CR0_DSS(12) /*!< Databit number = 12 */ 89 #define SSP_DATABIT_13 SSP_CR0_DSS(13) /*!< Databit number = 13 */ 90 #define SSP_DATABIT_14 SSP_CR0_DSS(14) /*!< Databit number = 14 */ 91 #define SSP_DATABIT_15 SSP_CR0_DSS(15) /*!< Databit number = 15 */ 92 #define SSP_DATABIT_16 SSP_CR0_DSS(16) /*!< Databit number = 16 */ 93 94 /** SSP Frame Format definition */ 95 /** Motorola SPI mode */ 96 #define SSP_FRAME_SPI SSP_CR0_FRF_SPI 97 /** TI synchronous serial mode */ 98 #define SSP_FRAME_TI SSP_CR0_FRF_TI 99 /** National Micro-wire mode */ 100 #define SSP_FRAME_MICROWIRE SSP_CR0_FRF_MICROWIRE 101 102 /*********************************************************************//** 103 * SSP Status defines 104 **********************************************************************/ 105 /** SSP status TX FIFO Empty bit */ 106 #define SSP_STAT_TXFIFO_EMPTY SSP_SR_TFE 107 /** SSP status TX FIFO not full bit */ 108 #define SSP_STAT_TXFIFO_NOTFULL SSP_SR_TNF 109 /** SSP status RX FIFO not empty bit */ 110 #define SSP_STAT_RXFIFO_NOTEMPTY SSP_SR_RNE 111 /** SSP status RX FIFO full bit */ 112 #define SSP_STAT_RXFIFO_FULL SSP_SR_RFF 113 /** SSP status SSP Busy bit */ 114 #define SSP_STAT_BUSY SSP_SR_BSY 115 116 /*********************************************************************//** 117 * SSP Interrupt Configuration defines 118 **********************************************************************/ 119 /** Receive Overrun */ 120 #define SSP_INTCFG_ROR SSP_IMSC_ROR 121 /** Receive TimeOut */ 122 #define SSP_INTCFG_RT SSP_IMSC_RT 123 /** Rx FIFO is at least half full */ 124 #define SSP_INTCFG_RX SSP_IMSC_RX 125 /** Tx FIFO is at least half empty */ 126 #define SSP_INTCFG_TX SSP_IMSC_TX 127 128 /*********************************************************************//** 129 * SSP Configured Interrupt Status defines 130 **********************************************************************/ 131 /** Receive Overrun */ 132 #define SSP_INTSTAT_ROR SSP_MIS_ROR 133 /** Receive TimeOut */ 134 #define SSP_INTSTAT_RT SSP_MIS_RT 135 /** Rx FIFO is at least half full */ 136 #define SSP_INTSTAT_RX SSP_MIS_RX 137 /** Tx FIFO is at least half empty */ 138 #define SSP_INTSTAT_TX SSP_MIS_TX 139 140 /*********************************************************************//** 141 * SSP Raw Interrupt Status defines 142 **********************************************************************/ 143 /** Receive Overrun */ 144 #define SSP_INTSTAT_RAW_ROR SSP_RIS_ROR 145 /** Receive TimeOut */ 146 #define SSP_INTSTAT_RAW_RT SSP_RIS_RT 147 /** Rx FIFO is at least half full */ 148 #define SSP_INTSTAT_RAW_RX SSP_RIS_RX 149 /** Tx FIFO is at least half empty */ 150 #define SSP_INTSTAT_RAW_TX SSP_RIS_TX 151 152 /*********************************************************************//** 153 * SSP Interrupt Clear defines 154 **********************************************************************/ 155 /** Writing a 1 to this bit clears the "frame was received when 156 * RxFIFO was full" interrupt */ 157 #define SSP_INTCLR_ROR SSP_ICR_ROR 158 /** Writing a 1 to this bit clears the "Rx FIFO was not empty and 159 * has not been read for a timeout period" interrupt */ 160 #define SSP_INTCLR_RT SSP_ICR_RT 161 162 /*********************************************************************//** 163 * SSP DMA defines 164 **********************************************************************/ 165 /** SSP bit for enabling RX DMA */ 166 #define SSP_DMA_RX SSP_DMA_RXDMA_EN 167 /** SSP bit for enabling TX DMA */ 168 #define SSP_DMA_TX SSP_DMA_TXDMA_EN 169 170 /* SSP Status Implementation definitions */ 171 #define SSP_STAT_DONE (1UL<<8) /**< Done */ 172 #define SSP_STAT_ERROR (1UL<<9) /**< Error */ 173 174 /** 175 * @} 176 */ 177 178 /* Private Macros ------------------------------------------------------------- */ 179 /** @defgroup SSP_Private_Macros SSP Private Macros 180 * @{ 181 */ 182 183 /* --------------------- BIT DEFINITIONS -------------------------------------- */ 184 /*********************************************************************//** 185 * Macro defines for CR0 register 186 **********************************************************************/ 187 /** SSP data size select, must be 4 bits to 16 bits */ 188 #define SSP_CR0_DSS(n) ((uint32_t)((n-1)&0xF)) 189 /** SSP control 0 Motorola SPI mode */ 190 #define SSP_CR0_FRF_SPI ((uint32_t)(0<<4)) 191 /** SSP control 0 TI synchronous serial mode */ 192 #define SSP_CR0_FRF_TI ((uint32_t)(1<<4)) 193 /** SSP control 0 National Micro-wire mode */ 194 #define SSP_CR0_FRF_MICROWIRE ((uint32_t)(2<<4)) 195 /** SPI clock polarity bit (used in SPI mode only), (1) = maintains the 196 bus clock high between frames, (0) = low */ 197 #define SSP_CR0_CPOL_HI ((uint32_t)(1<<6)) 198 /** SPI clock out phase bit (used in SPI mode only), (1) = captures data 199 on the second clock transition of the frame, (0) = first */ 200 #define SSP_CR0_CPHA_SECOND ((uint32_t)(1<<7)) 201 /** SSP serial clock rate value load macro, divider rate is 202 PERIPH_CLK / (cpsr * (SCR + 1)) */ 203 #define SSP_CR0_SCR(n) ((uint32_t)((n&0xFF)<<8)) 204 /** SSP CR0 bit mask */ 205 #define SSP_CR0_BITMASK ((uint32_t)(0xFFFF)) 206 207 /*********************************************************************//** 208 * Macro defines for CR1 register 209 **********************************************************************/ 210 /** SSP control 1 loopback mode enable bit */ 211 #define SSP_CR1_LBM_EN ((uint32_t)(1<<0)) 212 /** SSP control 1 enable bit */ 213 #define SSP_CR1_SSP_EN ((uint32_t)(1<<1)) 214 /** SSP control 1 slave enable */ 215 #define SSP_CR1_SLAVE_EN ((uint32_t)(1<<2)) 216 /** SSP control 1 slave out disable bit, disables transmit line in slave 217 mode */ 218 #define SSP_CR1_SO_DISABLE ((uint32_t)(1<<3)) 219 /** SSP CR1 bit mask */ 220 #define SSP_CR1_BITMASK ((uint32_t)(0x0F)) 221 222 /*********************************************************************//** 223 * Macro defines for DR register 224 **********************************************************************/ 225 /** SSP data bit mask */ 226 #define SSP_DR_BITMASK(n) ((n)&0xFFFF) 227 228 /*********************************************************************//** 229 * Macro defines for SR register 230 **********************************************************************/ 231 /** SSP status TX FIFO Empty bit */ 232 #define SSP_SR_TFE ((uint32_t)(1<<0)) 233 /** SSP status TX FIFO not full bit */ 234 #define SSP_SR_TNF ((uint32_t)(1<<1)) 235 /** SSP status RX FIFO not empty bit */ 236 #define SSP_SR_RNE ((uint32_t)(1<<2)) 237 /** SSP status RX FIFO full bit */ 238 #define SSP_SR_RFF ((uint32_t)(1<<3)) 239 /** SSP status SSP Busy bit */ 240 #define SSP_SR_BSY ((uint32_t)(1<<4)) 241 /** SSP SR bit mask */ 242 #define SSP_SR_BITMASK ((uint32_t)(0x1F)) 243 244 /*********************************************************************//** 245 * Macro defines for CPSR register 246 **********************************************************************/ 247 /** SSP clock prescaler */ 248 #define SSP_CPSR_CPDVSR(n) ((uint32_t)(n&0xFF)) 249 /** SSP CPSR bit mask */ 250 #define SSP_CPSR_BITMASK ((uint32_t)(0xFF)) 251 252 /*********************************************************************//** 253 * Macro define for (IMSC) Interrupt Mask Set/Clear registers 254 **********************************************************************/ 255 /** Receive Overrun */ 256 #define SSP_IMSC_ROR ((uint32_t)(1<<0)) 257 /** Receive TimeOut */ 258 #define SSP_IMSC_RT ((uint32_t)(1<<1)) 259 /** Rx FIFO is at least half full */ 260 #define SSP_IMSC_RX ((uint32_t)(1<<2)) 261 /** Tx FIFO is at least half empty */ 262 #define SSP_IMSC_TX ((uint32_t)(1<<3)) 263 /** IMSC bit mask */ 264 #define SSP_IMSC_BITMASK ((uint32_t)(0x0F)) 265 266 /*********************************************************************//** 267 * Macro define for (RIS) Raw Interrupt Status registers 268 **********************************************************************/ 269 /** Receive Overrun */ 270 #define SSP_RIS_ROR ((uint32_t)(1<<0)) 271 /** Receive TimeOut */ 272 #define SSP_RIS_RT ((uint32_t)(1<<1)) 273 /** Rx FIFO is at least half full */ 274 #define SSP_RIS_RX ((uint32_t)(1<<2)) 275 /** Tx FIFO is at least half empty */ 276 #define SSP_RIS_TX ((uint32_t)(1<<3)) 277 /** RIS bit mask */ 278 #define SSP_RIS_BITMASK ((uint32_t)(0x0F)) 279 280 /*********************************************************************//** 281 * Macro define for (MIS) Masked Interrupt Status registers 282 **********************************************************************/ 283 /** Receive Overrun */ 284 #define SSP_MIS_ROR ((uint32_t)(1<<0)) 285 /** Receive TimeOut */ 286 #define SSP_MIS_RT ((uint32_t)(1<<1)) 287 /** Rx FIFO is at least half full */ 288 #define SSP_MIS_RX ((uint32_t)(1<<2)) 289 /** Tx FIFO is at least half empty */ 290 #define SSP_MIS_TX ((uint32_t)(1<<3)) 291 /** MIS bit mask */ 292 #define SSP_MIS_BITMASK ((uint32_t)(0x0F)) 293 294 /*********************************************************************//** 295 * Macro define for (ICR) Interrupt Clear registers 296 **********************************************************************/ 297 /** Writing a 1 to this bit clears the "frame was received when 298 * RxFIFO was full" interrupt */ 299 #define SSP_ICR_ROR ((uint32_t)(1<<0)) 300 /** Writing a 1 to this bit clears the "Rx FIFO was not empty and 301 * has not been read for a timeout period" interrupt */ 302 #define SSP_ICR_RT ((uint32_t)(1<<1)) 303 /** ICR bit mask */ 304 #define SSP_ICR_BITMASK ((uint32_t)(0x03)) 305 306 /*********************************************************************//** 307 * Macro defines for DMACR register 308 **********************************************************************/ 309 /** SSP bit for enabling RX DMA */ 310 #define SSP_DMA_RXDMA_EN ((uint32_t)(1<<0)) 311 /** SSP bit for enabling TX DMA */ 312 #define SSP_DMA_TXDMA_EN ((uint32_t)(1<<1)) 313 /** DMACR bit mask */ 314 #define SSP_DMA_BITMASK ((uint32_t)(0x03)) 315 316 317 /* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */ 318 /** Macro to determine if it is valid SSP port number */ 319 #define PARAM_SSPx(n) ((((uint32_t *)n)==((uint32_t *)LPC_SSP0)) \ 320 || (((uint32_t *)n)==((uint32_t *)LPC_SSP1))) 321 322 /** Macro check clock phase control mode */ 323 #define PARAM_SSP_CPHA(n) ((n==SSP_CPHA_FIRST) || (n==SSP_CPHA_SECOND)) 324 325 /** Macro check clock polarity mode */ 326 #define PARAM_SSP_CPOL(n) ((n==SSP_CPOL_HI) || (n==SSP_CPOL_LO)) 327 328 /* Macro check master/slave mode */ 329 #define PARAM_SSP_MODE(n) ((n==SSP_SLAVE_MODE) || (n==SSP_MASTER_MODE)) 330 331 /* Macro check databit value */ 332 #define PARAM_SSP_DATABIT(n) ((n==SSP_DATABIT_4) || (n==SSP_DATABIT_5) \ 333 || (n==SSP_DATABIT_6) || (n==SSP_DATABIT_16) \ 334 || (n==SSP_DATABIT_7) || (n==SSP_DATABIT_8) \ 335 || (n==SSP_DATABIT_9) || (n==SSP_DATABIT_10) \ 336 || (n==SSP_DATABIT_11) || (n==SSP_DATABIT_12) \ 337 || (n==SSP_DATABIT_13) || (n==SSP_DATABIT_14) \ 338 || (n==SSP_DATABIT_15)) 339 340 /* Macro check frame type */ 341 #define PARAM_SSP_FRAME(n) ((n==SSP_FRAME_SPI) || (n==SSP_FRAME_TI)\ 342 || (n==SSP_FRAME_MICROWIRE)) 343 344 /* Macro check SSP status */ 345 #define PARAM_SSP_STAT(n) ((n==SSP_STAT_TXFIFO_EMPTY) || (n==SSP_STAT_TXFIFO_NOTFULL) \ 346 || (n==SSP_STAT_RXFIFO_NOTEMPTY) || (n==SSP_STAT_RXFIFO_FULL) \ 347 || (n==SSP_STAT_BUSY)) 348 349 /* Macro check interrupt configuration */ 350 #define PARAM_SSP_INTCFG(n) ((n==SSP_INTCFG_ROR) || (n==SSP_INTCFG_RT) \ 351 || (n==SSP_INTCFG_RX) || (n==SSP_INTCFG_TX)) 352 353 /* Macro check interrupt status value */ 354 #define PARAM_SSP_INTSTAT(n) ((n==SSP_INTSTAT_ROR) || (n==SSP_INTSTAT_RT) \ 355 || (n==SSP_INTSTAT_RX) || (n==SSP_INTSTAT_TX)) 356 357 /* Macro check interrupt status raw value */ 358 #define PARAM_SSP_INTSTAT_RAW(n) ((n==SSP_INTSTAT_RAW_ROR) || (n==SSP_INTSTAT_RAW_RT) \ 359 || (n==SSP_INTSTAT_RAW_RX) || (n==SSP_INTSTAT_RAW_TX)) 360 361 /* Macro check interrupt clear mode */ 362 #define PARAM_SSP_INTCLR(n) ((n==SSP_INTCLR_ROR) || (n==SSP_INTCLR_RT)) 363 364 /* Macro check DMA mode */ 365 #define PARAM_SSP_DMA(n) ((n==SSP_DMA_TX) || (n==SSP_DMA_RX)) 366 /** 367 * @} 368 */ 369 370 371 /* Public Types --------------------------------------------------------------- */ 372 /** @defgroup SSP_Public_Types SSP Public Types 373 * @{ 374 */ 375 376 /** @brief SSP configuration structure */ 377 typedef struct { 378 uint32_t Databit; /** Databit number, should be SSP_DATABIT_x, 379 where x is in range from 4 - 16 */ 380 uint32_t CPHA; /** Clock phase, should be: 381 - SSP_CPHA_FIRST: first clock edge 382 - SSP_CPHA_SECOND: second clock edge */ 383 uint32_t CPOL; /** Clock polarity, should be: 384 - SSP_CPOL_HI: high level 385 - SSP_CPOL_LO: low level */ 386 uint32_t Mode; /** SSP mode, should be: 387 - SSP_MASTER_MODE: Master mode 388 - SSP_SLAVE_MODE: Slave mode */ 389 uint32_t FrameFormat; /** Frame Format: 390 - SSP_FRAME_SPI: Motorola SPI frame format 391 - SSP_FRAME_TI: TI frame format 392 - SSP_FRAME_MICROWIRE: National Microwire frame format */ 393 uint32_t ClockRate; /** Clock rate,in Hz */ 394 } SSP_CFG_Type; 395 396 /** 397 * @brief SSP Transfer Type definitions 398 */ 399 typedef enum { 400 SSP_TRANSFER_POLLING = 0, /**< Polling transfer */ 401 SSP_TRANSFER_INTERRUPT /**< Interrupt transfer */ 402 } SSP_TRANSFER_Type; 403 404 /** 405 * @brief SPI Data configuration structure definitions 406 */ 407 typedef struct { 408 void *tx_data; /**< Pointer to transmit data */ 409 uint32_t tx_cnt; /**< Transmit counter */ 410 void *rx_data; /**< Pointer to transmit data */ 411 uint32_t rx_cnt; /**< Receive counter */ 412 uint32_t length; /**< Length of transfer data */ 413 uint32_t status; /**< Current status of SSP activity */ 414 } SSP_DATA_SETUP_Type; 415 416 417 /** 418 * @} 419 */ 420 421 422 /* Public Functions ----------------------------------------------------------- */ 423 /** @defgroup SSP_Public_Functions SSP Public Functions 424 * @{ 425 */ 426 427 /* SSP Init/DeInit functions --------------------------------------------------*/ 428 void SSP_Init(LPC_SSP_TypeDef *SSPx, SSP_CFG_Type *SSP_ConfigStruct); 429 void SSP_DeInit(LPC_SSP_TypeDef* SSPx); 430 431 /* SSP configure functions ----------------------------------------------------*/ 432 void SSP_ConfigStructInit(SSP_CFG_Type *SSP_InitStruct); 433 434 /* SSP enable/disable functions -----------------------------------------------*/ 435 void SSP_Cmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState); 436 void SSP_LoopBackCmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState); 437 void SSP_SlaveOutputCmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState); 438 void SSP_DMACmd(LPC_SSP_TypeDef *SSPx, uint32_t DMAMode, FunctionalState NewState); 439 440 /* SSP get information functions ----------------------------------------------*/ 441 FlagStatus SSP_GetStatus(LPC_SSP_TypeDef* SSPx, uint32_t FlagType); 442 uint8_t SSP_GetDataSize(LPC_SSP_TypeDef* SSPx); 443 IntStatus SSP_GetRawIntStatus(LPC_SSP_TypeDef *SSPx, uint32_t RawIntType); 444 uint32_t SSP_GetRawIntStatusReg(LPC_SSP_TypeDef *SSPx); 445 IntStatus SSP_GetIntStatus (LPC_SSP_TypeDef *SSPx, uint32_t IntType); 446 447 /* SSP transfer data functions ------------------------------------------------*/ 448 void SSP_SendData(LPC_SSP_TypeDef* SSPx, uint16_t Data); 449 uint16_t SSP_ReceiveData(LPC_SSP_TypeDef* SSPx); 450 int32_t SSP_ReadWrite (LPC_SSP_TypeDef *SSPx, SSP_DATA_SETUP_Type *dataCfg, \ 451 SSP_TRANSFER_Type xfType); 452 453 /* SSP IRQ function ------------------------------------------------------------*/ 454 void SSP_IntConfig(LPC_SSP_TypeDef *SSPx, uint32_t IntType, FunctionalState NewState); 455 void SSP_ClearIntPending(LPC_SSP_TypeDef *SSPx, uint32_t IntType); 456 457 458 /** 459 * @} 460 */ 461 462 #ifdef __cplusplus 463 } 464 #endif 465 466 #endif /* LPC17XX_SSP_H_ */ 467 468 /** 469 * @} 470 */ 471 472 /* --------------------------------- End Of File ------------------------------ */