lpc17xx_uart.h (33075B)
1 /********************************************************************** 2 * $Id$ lpc17xx_uart.h 2010-06-18 3 *//** 4 * @file lpc17xx_uart.h 5 * @brief Contains all macro definitions and function prototypes 6 * support for UART firmware library on LPC17xx 7 * @version 3.0 8 * @date 18. June. 2010 9 * @author NXP MCU SW Application Team 10 * 11 * Copyright(C) 2010, NXP Semiconductor 12 * All rights reserved. 13 * 14 *********************************************************************** 15 * Software that is described herein is for illustrative purposes only 16 * which provides customers with programming information regarding the 17 * products. This software is supplied "AS IS" without any warranties. 18 * NXP Semiconductors assumes no responsibility or liability for the 19 * use of the software, conveys no license or title under any patent, 20 * copyright, or mask work right to the product. NXP Semiconductors 21 * reserves the right to make changes in the software without 22 * notification. NXP Semiconductors also make no representation or 23 * warranty that such application will be suitable for the specified 24 * use without further testing or modification. 25 * Permission to use, copy, modify, and distribute this software and its 26 * documentation is hereby granted, under NXP Semiconductors' 27 * relevant copyright in the software, without fee, provided that it 28 * is used in conjunction with NXP Semiconductors microcontrollers. This 29 * copyright, permission, and disclaimer notice must appear in all copies of 30 * this code. 31 **********************************************************************/ 32 33 /* Peripheral group ----------------------------------------------------------- */ 34 /** @defgroup UART UART (Universal Asynchronous Receiver/Transmitter) 35 * @ingroup LPC1700CMSIS_FwLib_Drivers 36 * @{ 37 */ 38 39 #ifndef __LPC17XX_UART_H 40 #define __LPC17XX_UART_H 41 42 /* Includes ------------------------------------------------------------------- */ 43 #include "LPC17xx.h" 44 #include "lpc_types.h" 45 46 47 #ifdef __cplusplus 48 extern "C" 49 { 50 #endif 51 52 /* Public Macros -------------------------------------------------------------- */ 53 /** @defgroup UART_Public_Macros UART Public Macros 54 * @{ 55 */ 56 57 /** UART time-out definitions in case of using Read() and Write function 58 * with Blocking Flag mode 59 */ 60 #define UART_BLOCKING_TIMEOUT (0xFFFFFFFFUL) 61 62 /** 63 * @} 64 */ 65 66 /* Private Macros ------------------------------------------------------------- */ 67 /** @defgroup UART_Private_Macros UART Private Macros 68 * @{ 69 */ 70 71 /* Accepted Error baud rate value (in percent unit) */ 72 #define UART_ACCEPTED_BAUDRATE_ERROR (3) /*!< Acceptable UART baudrate error */ 73 74 75 /* --------------------- BIT DEFINITIONS -------------------------------------- */ 76 /*********************************************************************//** 77 * Macro defines for Macro defines for UARTn Receiver Buffer Register 78 **********************************************************************/ 79 #define UART_RBR_MASKBIT ((uint8_t)0xFF) /*!< UART Received Buffer mask bit (8 bits) */ 80 81 /*********************************************************************//** 82 * Macro defines for Macro defines for UARTn Transmit Holding Register 83 **********************************************************************/ 84 #define UART_THR_MASKBIT ((uint8_t)0xFF) /*!< UART Transmit Holding mask bit (8 bits) */ 85 86 /*********************************************************************//** 87 * Macro defines for Macro defines for UARTn Divisor Latch LSB register 88 **********************************************************************/ 89 #define UART_LOAD_DLL(div) ((div) & 0xFF) /**< Macro for loading least significant halfs of divisors */ 90 #define UART_DLL_MASKBIT ((uint8_t)0xFF) /*!< Divisor latch LSB bit mask */ 91 92 /*********************************************************************//** 93 * Macro defines for Macro defines for UARTn Divisor Latch MSB register 94 **********************************************************************/ 95 #define UART_DLM_MASKBIT ((uint8_t)0xFF) /*!< Divisor latch MSB bit mask */ 96 #define UART_LOAD_DLM(div) (((div) >> 8) & 0xFF) /**< Macro for loading most significant halfs of divisors */ 97 98 /*********************************************************************//** 99 * Macro defines for Macro defines for UART interrupt enable register 100 **********************************************************************/ 101 #define UART_IER_RBRINT_EN ((uint32_t)(1<<0)) /*!< RBR Interrupt enable*/ 102 #define UART_IER_THREINT_EN ((uint32_t)(1<<1)) /*!< THR Interrupt enable*/ 103 #define UART_IER_RLSINT_EN ((uint32_t)(1<<2)) /*!< RX line status interrupt enable*/ 104 #define UART1_IER_MSINT_EN ((uint32_t)(1<<3)) /*!< Modem status interrupt enable */ 105 #define UART1_IER_CTSINT_EN ((uint32_t)(1<<7)) /*!< CTS1 signal transition interrupt enable */ 106 #define UART_IER_ABEOINT_EN ((uint32_t)(1<<8)) /*!< Enables the end of auto-baud interrupt */ 107 #define UART_IER_ABTOINT_EN ((uint32_t)(1<<9)) /*!< Enables the auto-baud time-out interrupt */ 108 #define UART_IER_BITMASK ((uint32_t)(0x307)) /*!< UART interrupt enable register bit mask */ 109 #define UART1_IER_BITMASK ((uint32_t)(0x38F)) /*!< UART1 interrupt enable register bit mask */ 110 111 /*********************************************************************//** 112 * Macro defines for Macro defines for UART interrupt identification register 113 **********************************************************************/ 114 #define UART_IIR_INTSTAT_PEND ((uint32_t)(1<<0)) /*!<Interrupt Status - Active low */ 115 #define UART_IIR_INTID_RLS ((uint32_t)(3<<1)) /*!<Interrupt identification: Receive line status*/ 116 #define UART_IIR_INTID_RDA ((uint32_t)(2<<1)) /*!<Interrupt identification: Receive data available*/ 117 #define UART_IIR_INTID_CTI ((uint32_t)(6<<1)) /*!<Interrupt identification: Character time-out indicator*/ 118 #define UART_IIR_INTID_THRE ((uint32_t)(1<<1)) /*!<Interrupt identification: THRE interrupt*/ 119 #define UART1_IIR_INTID_MODEM ((uint32_t)(0<<1)) /*!<Interrupt identification: Modem interrupt*/ 120 #define UART_IIR_INTID_MASK ((uint32_t)(7<<1)) /*!<Interrupt identification: Interrupt ID mask */ 121 #define UART_IIR_FIFO_EN ((uint32_t)(3<<6)) /*!<These bits are equivalent to UnFCR[0] */ 122 #define UART_IIR_ABEO_INT ((uint32_t)(1<<8)) /*!< End of auto-baud interrupt */ 123 #define UART_IIR_ABTO_INT ((uint32_t)(1<<9)) /*!< Auto-baud time-out interrupt */ 124 #define UART_IIR_BITMASK ((uint32_t)(0x3CF)) /*!< UART interrupt identification register bit mask */ 125 126 /*********************************************************************//** 127 * Macro defines for Macro defines for UART FIFO control register 128 **********************************************************************/ 129 #define UART_FCR_FIFO_EN ((uint8_t)(1<<0)) /*!< UART FIFO enable */ 130 #define UART_FCR_RX_RS ((uint8_t)(1<<1)) /*!< UART FIFO RX reset */ 131 #define UART_FCR_TX_RS ((uint8_t)(1<<2)) /*!< UART FIFO TX reset */ 132 #define UART_FCR_DMAMODE_SEL ((uint8_t)(1<<3)) /*!< UART DMA mode selection */ 133 #define UART_FCR_TRG_LEV0 ((uint8_t)(0)) /*!< UART FIFO trigger level 0: 1 character */ 134 #define UART_FCR_TRG_LEV1 ((uint8_t)(1<<6)) /*!< UART FIFO trigger level 1: 4 character */ 135 #define UART_FCR_TRG_LEV2 ((uint8_t)(2<<6)) /*!< UART FIFO trigger level 2: 8 character */ 136 #define UART_FCR_TRG_LEV3 ((uint8_t)(3<<6)) /*!< UART FIFO trigger level 3: 14 character */ 137 #define UART_FCR_BITMASK ((uint8_t)(0xCF)) /*!< UART FIFO control bit mask */ 138 #define UART_TX_FIFO_SIZE (16) 139 140 /*********************************************************************//** 141 * Macro defines for Macro defines for UART line control register 142 **********************************************************************/ 143 #define UART_LCR_WLEN5 ((uint8_t)(0)) /*!< UART 5 bit data mode */ 144 #define UART_LCR_WLEN6 ((uint8_t)(1<<0)) /*!< UART 6 bit data mode */ 145 #define UART_LCR_WLEN7 ((uint8_t)(2<<0)) /*!< UART 7 bit data mode */ 146 #define UART_LCR_WLEN8 ((uint8_t)(3<<0)) /*!< UART 8 bit data mode */ 147 #define UART_LCR_STOPBIT_SEL ((uint8_t)(1<<2)) /*!< UART Two Stop Bits Select */ 148 #define UART_LCR_PARITY_EN ((uint8_t)(1<<3)) /*!< UART Parity Enable */ 149 #define UART_LCR_PARITY_ODD ((uint8_t)(0)) /*!< UART Odd Parity Select */ 150 #define UART_LCR_PARITY_EVEN ((uint8_t)(1<<4)) /*!< UART Even Parity Select */ 151 #define UART_LCR_PARITY_F_1 ((uint8_t)(2<<4)) /*!< UART force 1 stick parity */ 152 #define UART_LCR_PARITY_F_0 ((uint8_t)(3<<4)) /*!< UART force 0 stick parity */ 153 #define UART_LCR_BREAK_EN ((uint8_t)(1<<6)) /*!< UART Transmission Break enable */ 154 #define UART_LCR_DLAB_EN ((uint8_t)(1<<7)) /*!< UART Divisor Latches Access bit enable */ 155 #define UART_LCR_BITMASK ((uint8_t)(0xFF)) /*!< UART line control bit mask */ 156 157 /*********************************************************************//** 158 * Macro defines for Macro defines for UART1 Modem Control Register 159 **********************************************************************/ 160 #define UART1_MCR_DTR_CTRL ((uint8_t)(1<<0)) /*!< Source for modem output pin DTR */ 161 #define UART1_MCR_RTS_CTRL ((uint8_t)(1<<1)) /*!< Source for modem output pin RTS */ 162 #define UART1_MCR_LOOPB_EN ((uint8_t)(1<<4)) /*!< Loop back mode select */ 163 #define UART1_MCR_AUTO_RTS_EN ((uint8_t)(1<<6)) /*!< Enable Auto RTS flow-control */ 164 #define UART1_MCR_AUTO_CTS_EN ((uint8_t)(1<<7)) /*!< Enable Auto CTS flow-control */ 165 #define UART1_MCR_BITMASK ((uint8_t)(0x0F3)) /*!< UART1 bit mask value */ 166 167 /*********************************************************************//** 168 * Macro defines for Macro defines for UART line status register 169 **********************************************************************/ 170 #define UART_LSR_RDR ((uint8_t)(1<<0)) /*!<Line status register: Receive data ready*/ 171 #define UART_LSR_OE ((uint8_t)(1<<1)) /*!<Line status register: Overrun error*/ 172 #define UART_LSR_PE ((uint8_t)(1<<2)) /*!<Line status register: Parity error*/ 173 #define UART_LSR_FE ((uint8_t)(1<<3)) /*!<Line status register: Framing error*/ 174 #define UART_LSR_BI ((uint8_t)(1<<4)) /*!<Line status register: Break interrupt*/ 175 #define UART_LSR_THRE ((uint8_t)(1<<5)) /*!<Line status register: Transmit holding register empty*/ 176 #define UART_LSR_TEMT ((uint8_t)(1<<6)) /*!<Line status register: Transmitter empty*/ 177 #define UART_LSR_RXFE ((uint8_t)(1<<7)) /*!<Error in RX FIFO*/ 178 #define UART_LSR_BITMASK ((uint8_t)(0xFF)) /*!<UART Line status bit mask */ 179 180 /*********************************************************************//** 181 * Macro defines for Macro defines for UART Modem (UART1 only) status register 182 **********************************************************************/ 183 #define UART1_MSR_DELTA_CTS ((uint8_t)(1<<0)) /*!< Set upon state change of input CTS */ 184 #define UART1_MSR_DELTA_DSR ((uint8_t)(1<<1)) /*!< Set upon state change of input DSR */ 185 #define UART1_MSR_LO2HI_RI ((uint8_t)(1<<2)) /*!< Set upon low to high transition of input RI */ 186 #define UART1_MSR_DELTA_DCD ((uint8_t)(1<<3)) /*!< Set upon state change of input DCD */ 187 #define UART1_MSR_CTS ((uint8_t)(1<<4)) /*!< Clear To Send State */ 188 #define UART1_MSR_DSR ((uint8_t)(1<<5)) /*!< Data Set Ready State */ 189 #define UART1_MSR_RI ((uint8_t)(1<<6)) /*!< Ring Indicator State */ 190 #define UART1_MSR_DCD ((uint8_t)(1<<7)) /*!< Data Carrier Detect State */ 191 #define UART1_MSR_BITMASK ((uint8_t)(0xFF)) /*!< MSR register bit-mask value */ 192 193 /*********************************************************************//** 194 * Macro defines for Macro defines for UART Scratch Pad Register 195 **********************************************************************/ 196 #define UART_SCR_BIMASK ((uint8_t)(0xFF)) /*!< UART Scratch Pad bit mask */ 197 198 /*********************************************************************//** 199 * Macro defines for Macro defines for UART Auto baudrate control register 200 **********************************************************************/ 201 #define UART_ACR_START ((uint32_t)(1<<0)) /**< UART Auto-baud start */ 202 #define UART_ACR_MODE ((uint32_t)(1<<1)) /**< UART Auto baudrate Mode 1 */ 203 #define UART_ACR_AUTO_RESTART ((uint32_t)(1<<2)) /**< UART Auto baudrate restart */ 204 #define UART_ACR_ABEOINT_CLR ((uint32_t)(1<<8)) /**< UART End of auto-baud interrupt clear */ 205 #define UART_ACR_ABTOINT_CLR ((uint32_t)(1<<9)) /**< UART Auto-baud time-out interrupt clear */ 206 #define UART_ACR_BITMASK ((uint32_t)(0x307)) /**< UART Auto Baudrate register bit mask */ 207 208 /*********************************************************************//** 209 * Macro defines for Macro defines for UART IrDA control register 210 **********************************************************************/ 211 #define UART_ICR_IRDAEN ((uint32_t)(1<<0)) /**< IrDA mode enable */ 212 #define UART_ICR_IRDAINV ((uint32_t)(1<<1)) /**< IrDA serial input inverted */ 213 #define UART_ICR_FIXPULSE_EN ((uint32_t)(1<<2)) /**< IrDA fixed pulse width mode */ 214 #define UART_ICR_PULSEDIV(n) ((uint32_t)((n&0x07)<<3)) /**< PulseDiv - Configures the pulse when FixPulseEn = 1 */ 215 #define UART_ICR_BITMASK ((uint32_t)(0x3F)) /*!< UART IRDA bit mask */ 216 217 /*********************************************************************//** 218 * Macro defines for Macro defines for UART Fractional divider register 219 **********************************************************************/ 220 #define UART_FDR_DIVADDVAL(n) ((uint32_t)(n&0x0F)) /**< Baud-rate generation pre-scaler divisor */ 221 #define UART_FDR_MULVAL(n) ((uint32_t)((n<<4)&0xF0)) /**< Baud-rate pre-scaler multiplier value */ 222 #define UART_FDR_BITMASK ((uint32_t)(0xFF)) /**< UART Fractional Divider register bit mask */ 223 224 /*********************************************************************//** 225 * Macro defines for Macro defines for UART Tx Enable register 226 **********************************************************************/ 227 #define UART_TER_TXEN ((uint8_t)(1<<7)) /*!< Transmit enable bit */ 228 #define UART_TER_BITMASK ((uint8_t)(0x80)) /**< UART Transmit Enable Register bit mask */ 229 230 /*********************************************************************//** 231 * Macro defines for Macro defines for UART1 RS485 Control register 232 **********************************************************************/ 233 #define UART1_RS485CTRL_NMM_EN ((uint32_t)(1<<0)) /*!< RS-485/EIA-485 Normal Multi-drop Mode (NMM) 234 is disabled */ 235 #define UART1_RS485CTRL_RX_DIS ((uint32_t)(1<<1)) /*!< The receiver is disabled */ 236 #define UART1_RS485CTRL_AADEN ((uint32_t)(1<<2)) /*!< Auto Address Detect (AAD) is enabled */ 237 #define UART1_RS485CTRL_SEL_DTR ((uint32_t)(1<<3)) /*!< If direction control is enabled 238 (bit DCTRL = 1), pin DTR is used for direction control */ 239 #define UART1_RS485CTRL_DCTRL_EN ((uint32_t)(1<<4)) /*!< Enable Auto Direction Control */ 240 #define UART1_RS485CTRL_OINV_1 ((uint32_t)(1<<5)) /*!< This bit reverses the polarity of the direction 241 control signal on the RTS (or DTR) pin. The direction control pin 242 will be driven to logic "1" when the transmitter has data to be sent */ 243 #define UART1_RS485CTRL_BITMASK ((uint32_t)(0x3F)) /**< RS485 control bit-mask value */ 244 245 /*********************************************************************//** 246 * Macro defines for Macro defines for UART1 RS-485 Address Match register 247 **********************************************************************/ 248 #define UART1_RS485ADRMATCH_BITMASK ((uint8_t)(0xFF)) /**< Bit mask value */ 249 250 /*********************************************************************//** 251 * Macro defines for Macro defines for UART1 RS-485 Delay value register 252 **********************************************************************/ 253 /* Macro defines for UART1 RS-485 Delay value register */ 254 #define UART1_RS485DLY_BITMASK ((uint8_t)(0xFF)) /** Bit mask value */ 255 256 /*********************************************************************//** 257 * Macro defines for Macro defines for UART FIFO Level register 258 **********************************************************************/ 259 #define UART_FIFOLVL_RXFIFOLVL(n) ((uint32_t)(n&0x0F)) /**< Reflects the current level of the UART receiver FIFO */ 260 #define UART_FIFOLVL_TXFIFOLVL(n) ((uint32_t)((n>>8)&0x0F)) /**< Reflects the current level of the UART transmitter FIFO */ 261 #define UART_FIFOLVL_BITMASK ((uint32_t)(0x0F0F)) /**< UART FIFO Level Register bit mask */ 262 263 264 /* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */ 265 266 /** Macro to check the input UART_DATABIT parameters */ 267 #define PARAM_UART_DATABIT(databit) ((databit==UART_DATABIT_5) || (databit==UART_DATABIT_6)\ 268 || (databit==UART_DATABIT_7) || (databit==UART_DATABIT_8)) 269 270 /** Macro to check the input UART_STOPBIT parameters */ 271 #define PARAM_UART_STOPBIT(stopbit) ((stopbit==UART_STOPBIT_1) || (stopbit==UART_STOPBIT_2)) 272 273 /** Macro to check the input UART_PARITY parameters */ 274 #define PARAM_UART_PARITY(parity) ((parity==UART_PARITY_NONE) || (parity==UART_PARITY_ODD) \ 275 || (parity==UART_PARITY_EVEN) || (parity==UART_PARITY_SP_1) \ 276 || (parity==UART_PARITY_SP_0)) 277 278 /** Macro to check the input UART_FIFO parameters */ 279 #define PARAM_UART_FIFO_LEVEL(fifo) ((fifo==UART_FIFO_TRGLEV0) \ 280 || (fifo==UART_FIFO_TRGLEV1) || (fifo==UART_FIFO_TRGLEV2) \ 281 || (fifo==UART_FIFO_TRGLEV3)) 282 283 /** Macro to check the input UART_INTCFG parameters */ 284 #define PARAM_UART_INTCFG(IntCfg) ((IntCfg==UART_INTCFG_RBR) || (IntCfg==UART_INTCFG_THRE) \ 285 || (IntCfg==UART_INTCFG_RLS) || (IntCfg==UART_INTCFG_ABEO) \ 286 || (IntCfg==UART_INTCFG_ABTO)) 287 288 /** Macro to check the input UART1_INTCFG parameters - expansion input parameter for UART1 */ 289 #define PARAM_UART1_INTCFG(IntCfg) ((IntCfg==UART1_INTCFG_MS) || (IntCfg==UART1_INTCFG_CTS)) 290 291 /** Macro to check the input UART_AUTOBAUD_MODE parameters */ 292 #define PARAM_UART_AUTOBAUD_MODE(ABmode) ((ABmode==UART_AUTOBAUD_MODE0) || (ABmode==UART_AUTOBAUD_MODE1)) 293 294 /** Macro to check the input UART_AUTOBAUD_INTSTAT parameters */ 295 #define PARAM_UART_AUTOBAUD_INTSTAT(ABIntStat) ((ABIntStat==UART_AUTOBAUD_INTSTAT_ABEO) || \ 296 (ABIntStat==UART_AUTOBAUD_INTSTAT_ABTO)) 297 298 /** Macro to check the input UART_IrDA_PULSEDIV parameters */ 299 #define PARAM_UART_IrDA_PULSEDIV(PulseDiv) ((PulseDiv==UART_IrDA_PULSEDIV2) || (PulseDiv==UART_IrDA_PULSEDIV4) \ 300 || (PulseDiv==UART_IrDA_PULSEDIV8) || (PulseDiv==UART_IrDA_PULSEDIV16) \ 301 || (PulseDiv==UART_IrDA_PULSEDIV32) || (PulseDiv==UART_IrDA_PULSEDIV64) \ 302 || (PulseDiv==UART_IrDA_PULSEDIV128) || (PulseDiv==UART_IrDA_PULSEDIV256)) 303 304 /* Macro to check the input UART1_SignalState parameters */ 305 #define PARAM_UART1_SIGNALSTATE(x) ((x==INACTIVE) || (x==ACTIVE)) 306 307 /** Macro to check the input PARAM_UART1_MODEM_PIN parameters */ 308 #define PARAM_UART1_MODEM_PIN(x) ((x==UART1_MODEM_PIN_DTR) || (x==UART1_MODEM_PIN_RTS)) 309 310 /** Macro to check the input PARAM_UART1_MODEM_MODE parameters */ 311 #define PARAM_UART1_MODEM_MODE(x) ((x==UART1_MODEM_MODE_LOOPBACK) || (x==UART1_MODEM_MODE_AUTO_RTS) \ 312 || (x==UART1_MODEM_MODE_AUTO_CTS)) 313 314 /** Macro to check the direction control pin type */ 315 #define PARAM_UART_RS485_DIRCTRL_PIN(x) ((x==UART1_RS485_DIRCTRL_RTS) || (x==UART1_RS485_DIRCTRL_DTR)) 316 317 /* Macro to determine if it is valid UART port number */ 318 #define PARAM_UARTx(x) ((((uint32_t *)x)==((uint32_t *)LPC_UART0)) \ 319 || (((uint32_t *)x)==((uint32_t *)LPC_UART1)) \ 320 || (((uint32_t *)x)==((uint32_t *)LPC_UART2)) \ 321 || (((uint32_t *)x)==((uint32_t *)LPC_UART3))) 322 #define PARAM_UART_IrDA(x) (((uint32_t *)x)==((uint32_t *)LPC_UART3)) 323 #define PARAM_UART1_MODEM(x) (((uint32_t *)x)==((uint32_t *)LPC_UART1)) 324 325 /** Macro to check the input value for UART1_RS485_CFG_MATCHADDRVALUE parameter */ 326 #define PARAM_UART1_RS485_CFG_MATCHADDRVALUE(x) ((x<0xFF)) 327 328 /** Macro to check the input value for UART1_RS485_CFG_DELAYVALUE parameter */ 329 #define PARAM_UART1_RS485_CFG_DELAYVALUE(x) ((x<0xFF)) 330 331 /** 332 * @} 333 */ 334 335 336 /* Public Types --------------------------------------------------------------- */ 337 /** @defgroup UART_Public_Types UART Public Types 338 * @{ 339 */ 340 341 /** 342 * @brief UART Databit type definitions 343 */ 344 typedef enum { 345 UART_DATABIT_5 = 0, /*!< UART 5 bit data mode */ 346 UART_DATABIT_6, /*!< UART 6 bit data mode */ 347 UART_DATABIT_7, /*!< UART 7 bit data mode */ 348 UART_DATABIT_8 /*!< UART 8 bit data mode */ 349 } UART_DATABIT_Type; 350 351 /** 352 * @brief UART Stop bit type definitions 353 */ 354 typedef enum { 355 UART_STOPBIT_1 = (0), /*!< UART 1 Stop Bits Select */ 356 UART_STOPBIT_2 /*!< UART Two Stop Bits Select */ 357 } UART_STOPBIT_Type; 358 359 /** 360 * @brief UART Parity type definitions 361 */ 362 typedef enum { 363 UART_PARITY_NONE = 0, /*!< No parity */ 364 UART_PARITY_ODD, /*!< Odd parity */ 365 UART_PARITY_EVEN, /*!< Even parity */ 366 UART_PARITY_SP_1, /*!< Forced "1" stick parity */ 367 UART_PARITY_SP_0 /*!< Forced "0" stick parity */ 368 } UART_PARITY_Type; 369 370 /** 371 * @brief FIFO Level type definitions 372 */ 373 typedef enum { 374 UART_FIFO_TRGLEV0 = 0, /*!< UART FIFO trigger level 0: 1 character */ 375 UART_FIFO_TRGLEV1, /*!< UART FIFO trigger level 1: 4 character */ 376 UART_FIFO_TRGLEV2, /*!< UART FIFO trigger level 2: 8 character */ 377 UART_FIFO_TRGLEV3 /*!< UART FIFO trigger level 3: 14 character */ 378 } UART_FITO_LEVEL_Type; 379 380 /********************************************************************//** 381 * @brief UART Interrupt Type definitions 382 **********************************************************************/ 383 typedef enum { 384 UART_INTCFG_RBR = 0, /*!< RBR Interrupt enable*/ 385 UART_INTCFG_THRE, /*!< THR Interrupt enable*/ 386 UART_INTCFG_RLS, /*!< RX line status interrupt enable*/ 387 UART1_INTCFG_MS, /*!< Modem status interrupt enable (UART1 only) */ 388 UART1_INTCFG_CTS, /*!< CTS1 signal transition interrupt enable (UART1 only) */ 389 UART_INTCFG_ABEO, /*!< Enables the end of auto-baud interrupt */ 390 UART_INTCFG_ABTO /*!< Enables the auto-baud time-out interrupt */ 391 } UART_INT_Type; 392 393 /** 394 * @brief UART Line Status Type definition 395 */ 396 typedef enum { 397 UART_LINESTAT_RDR = UART_LSR_RDR, /*!<Line status register: Receive data ready*/ 398 UART_LINESTAT_OE = UART_LSR_OE, /*!<Line status register: Overrun error*/ 399 UART_LINESTAT_PE = UART_LSR_PE, /*!<Line status register: Parity error*/ 400 UART_LINESTAT_FE = UART_LSR_FE, /*!<Line status register: Framing error*/ 401 UART_LINESTAT_BI = UART_LSR_BI, /*!<Line status register: Break interrupt*/ 402 UART_LINESTAT_THRE = UART_LSR_THRE, /*!<Line status register: Transmit holding register empty*/ 403 UART_LINESTAT_TEMT = UART_LSR_TEMT, /*!<Line status register: Transmitter empty*/ 404 UART_LINESTAT_RXFE = UART_LSR_RXFE /*!<Error in RX FIFO*/ 405 } UART_LS_Type; 406 407 /** 408 * @brief UART Auto-baudrate mode type definition 409 */ 410 typedef enum { 411 UART_AUTOBAUD_MODE0 = 0, /**< UART Auto baudrate Mode 0 */ 412 UART_AUTOBAUD_MODE1 /**< UART Auto baudrate Mode 1 */ 413 } UART_AB_MODE_Type; 414 415 /** 416 * @brief Auto Baudrate mode configuration type definition 417 */ 418 typedef struct { 419 UART_AB_MODE_Type ABMode; /**< Autobaudrate mode */ 420 FunctionalState AutoRestart; /**< Auto Restart state */ 421 } UART_AB_CFG_Type; 422 423 /** 424 * @brief UART End of Auto-baudrate type definition 425 */ 426 typedef enum { 427 UART_AUTOBAUD_INTSTAT_ABEO = UART_IIR_ABEO_INT, /**< UART End of auto-baud interrupt */ 428 UART_AUTOBAUD_INTSTAT_ABTO = UART_IIR_ABTO_INT /**< UART Auto-baud time-out interrupt */ 429 }UART_ABEO_Type; 430 431 /** 432 * UART IrDA Control type Definition 433 */ 434 typedef enum { 435 UART_IrDA_PULSEDIV2 = 0, /**< Pulse width = 2 * Tpclk 436 - Configures the pulse when FixPulseEn = 1 */ 437 UART_IrDA_PULSEDIV4, /**< Pulse width = 4 * Tpclk 438 - Configures the pulse when FixPulseEn = 1 */ 439 UART_IrDA_PULSEDIV8, /**< Pulse width = 8 * Tpclk 440 - Configures the pulse when FixPulseEn = 1 */ 441 UART_IrDA_PULSEDIV16, /**< Pulse width = 16 * Tpclk 442 - Configures the pulse when FixPulseEn = 1 */ 443 UART_IrDA_PULSEDIV32, /**< Pulse width = 32 * Tpclk 444 - Configures the pulse when FixPulseEn = 1 */ 445 UART_IrDA_PULSEDIV64, /**< Pulse width = 64 * Tpclk 446 - Configures the pulse when FixPulseEn = 1 */ 447 UART_IrDA_PULSEDIV128, /**< Pulse width = 128 * Tpclk 448 - Configures the pulse when FixPulseEn = 1 */ 449 UART_IrDA_PULSEDIV256 /**< Pulse width = 256 * Tpclk 450 - Configures the pulse when FixPulseEn = 1 */ 451 } UART_IrDA_PULSE_Type; 452 453 /********************************************************************//** 454 * @brief UART1 Full modem - Signal states definition 455 **********************************************************************/ 456 typedef enum { 457 INACTIVE = 0, /* In-active state */ 458 ACTIVE = !INACTIVE /* Active state */ 459 }UART1_SignalState; 460 461 /** 462 * @brief UART modem status type definition 463 */ 464 typedef enum { 465 UART1_MODEM_STAT_DELTA_CTS = UART1_MSR_DELTA_CTS, /*!< Set upon state change of input CTS */ 466 UART1_MODEM_STAT_DELTA_DSR = UART1_MSR_DELTA_DSR, /*!< Set upon state change of input DSR */ 467 UART1_MODEM_STAT_LO2HI_RI = UART1_MSR_LO2HI_RI, /*!< Set upon low to high transition of input RI */ 468 UART1_MODEM_STAT_DELTA_DCD = UART1_MSR_DELTA_DCD, /*!< Set upon state change of input DCD */ 469 UART1_MODEM_STAT_CTS = UART1_MSR_CTS, /*!< Clear To Send State */ 470 UART1_MODEM_STAT_DSR = UART1_MSR_DSR, /*!< Data Set Ready State */ 471 UART1_MODEM_STAT_RI = UART1_MSR_RI, /*!< Ring Indicator State */ 472 UART1_MODEM_STAT_DCD = UART1_MSR_DCD /*!< Data Carrier Detect State */ 473 } UART_MODEM_STAT_type; 474 475 /** 476 * @brief Modem output pin type definition 477 */ 478 typedef enum { 479 UART1_MODEM_PIN_DTR = 0, /*!< Source for modem output pin DTR */ 480 UART1_MODEM_PIN_RTS /*!< Source for modem output pin RTS */ 481 } UART_MODEM_PIN_Type; 482 483 /** 484 * @brief UART Modem mode type definition 485 */ 486 typedef enum { 487 UART1_MODEM_MODE_LOOPBACK = 0, /*!< Loop back mode select */ 488 UART1_MODEM_MODE_AUTO_RTS, /*!< Enable Auto RTS flow-control */ 489 UART1_MODEM_MODE_AUTO_CTS /*!< Enable Auto CTS flow-control */ 490 } UART_MODEM_MODE_Type; 491 492 /** 493 * @brief UART Direction Control Pin type definition 494 */ 495 typedef enum { 496 UART1_RS485_DIRCTRL_RTS = 0, /**< Pin RTS is used for direction control */ 497 UART1_RS485_DIRCTRL_DTR /**< Pin DTR is used for direction control */ 498 } UART_RS485_DIRCTRL_PIN_Type; 499 500 /********************************************************************//** 501 * @brief UART Configuration Structure definition 502 **********************************************************************/ 503 typedef struct { 504 uint32_t Baud_rate; /**< UART baud rate */ 505 UART_PARITY_Type Parity; /**< Parity selection, should be: 506 - UART_PARITY_NONE: No parity 507 - UART_PARITY_ODD: Odd parity 508 - UART_PARITY_EVEN: Even parity 509 - UART_PARITY_SP_1: Forced "1" stick parity 510 - UART_PARITY_SP_0: Forced "0" stick parity 511 */ 512 UART_DATABIT_Type Databits; /**< Number of data bits, should be: 513 - UART_DATABIT_5: UART 5 bit data mode 514 - UART_DATABIT_6: UART 6 bit data mode 515 - UART_DATABIT_7: UART 7 bit data mode 516 - UART_DATABIT_8: UART 8 bit data mode 517 */ 518 UART_STOPBIT_Type Stopbits; /**< Number of stop bits, should be: 519 - UART_STOPBIT_1: UART 1 Stop Bits Select 520 - UART_STOPBIT_2: UART 2 Stop Bits Select 521 */ 522 } UART_CFG_Type; 523 524 /********************************************************************//** 525 * @brief UART FIFO Configuration Structure definition 526 **********************************************************************/ 527 528 typedef struct { 529 FunctionalState FIFO_ResetRxBuf; /**< Reset Rx FIFO command state , should be: 530 - ENABLE: Reset Rx FIFO in UART 531 - DISABLE: Do not reset Rx FIFO in UART 532 */ 533 FunctionalState FIFO_ResetTxBuf; /**< Reset Tx FIFO command state , should be: 534 - ENABLE: Reset Tx FIFO in UART 535 - DISABLE: Do not reset Tx FIFO in UART 536 */ 537 FunctionalState FIFO_DMAMode; /**< DMA mode, should be: 538 - ENABLE: Enable DMA mode in UART 539 - DISABLE: Disable DMA mode in UART 540 */ 541 UART_FITO_LEVEL_Type FIFO_Level; /**< Rx FIFO trigger level, should be: 542 - UART_FIFO_TRGLEV0: UART FIFO trigger level 0: 1 character 543 - UART_FIFO_TRGLEV1: UART FIFO trigger level 1: 4 character 544 - UART_FIFO_TRGLEV2: UART FIFO trigger level 2: 8 character 545 - UART_FIFO_TRGLEV3: UART FIFO trigger level 3: 14 character 546 */ 547 } UART_FIFO_CFG_Type; 548 549 /********************************************************************//** 550 * @brief UART1 Full modem - RS485 Control configuration type 551 **********************************************************************/ 552 typedef struct { 553 FunctionalState NormalMultiDropMode_State; /*!< Normal MultiDrop mode State: 554 - ENABLE: Enable this function. 555 - DISABLE: Disable this function. */ 556 FunctionalState Rx_State; /*!< Receiver State: 557 - ENABLE: Enable Receiver. 558 - DISABLE: Disable Receiver. */ 559 FunctionalState AutoAddrDetect_State; /*!< Auto Address Detect mode state: 560 - ENABLE: ENABLE this function. 561 - DISABLE: Disable this function. */ 562 FunctionalState AutoDirCtrl_State; /*!< Auto Direction Control State: 563 - ENABLE: Enable this function. 564 - DISABLE: Disable this function. */ 565 UART_RS485_DIRCTRL_PIN_Type DirCtrlPin; /*!< If direction control is enabled, state: 566 - UART1_RS485_DIRCTRL_RTS: 567 pin RTS is used for direction control. 568 - UART1_RS485_DIRCTRL_DTR: 569 pin DTR is used for direction control. */ 570 SetState DirCtrlPol_Level; /*!< Polarity of the direction control signal on 571 the RTS (or DTR) pin: 572 - RESET: The direction control pin will be driven 573 to logic "0" when the transmitter has data to be sent. 574 - SET: The direction control pin will be driven 575 to logic "1" when the transmitter has data to be sent. */ 576 uint8_t MatchAddrValue; /*!< address match value for RS-485/EIA-485 mode, 8-bit long */ 577 uint8_t DelayValue; /*!< delay time is in periods of the baud clock, 8-bit long */ 578 } UART1_RS485_CTRLCFG_Type; 579 580 /** 581 * @} 582 */ 583 584 585 /* Public Functions ----------------------------------------------------------- */ 586 /** @defgroup UART_Public_Functions UART Public Functions 587 * @{ 588 */ 589 /* UART Init/DeInit functions --------------------------------------------------*/ 590 void UART_Init(LPC_UART_TypeDef *UARTx, UART_CFG_Type *UART_ConfigStruct); 591 void UART_DeInit(LPC_UART_TypeDef* UARTx); 592 void UART_ConfigStructInit(UART_CFG_Type *UART_InitStruct); 593 594 /* UART Send/Receive functions -------------------------------------------------*/ 595 void UART_SendByte(LPC_UART_TypeDef* UARTx, uint8_t Data); 596 uint8_t UART_ReceiveByte(LPC_UART_TypeDef* UARTx); 597 uint32_t UART_Send(LPC_UART_TypeDef *UARTx, uint8_t *txbuf, 598 uint32_t buflen, TRANSFER_BLOCK_Type flag); 599 uint32_t UART_Receive(LPC_UART_TypeDef *UARTx, uint8_t *rxbuf, \ 600 uint32_t buflen, TRANSFER_BLOCK_Type flag); 601 602 /* UART FIFO functions ----------------------------------------------------------*/ 603 void UART_FIFOConfig(LPC_UART_TypeDef *UARTx, UART_FIFO_CFG_Type *FIFOCfg); 604 void UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct); 605 606 /* UART get information functions -----------------------------------------------*/ 607 uint32_t UART_GetIntId(LPC_UART_TypeDef* UARTx); 608 uint8_t UART_GetLineStatus(LPC_UART_TypeDef* UARTx); 609 610 /* UART operate functions -------------------------------------------------------*/ 611 void UART_IntConfig(LPC_UART_TypeDef *UARTx, UART_INT_Type UARTIntCfg, \ 612 FunctionalState NewState); 613 void UART_TxCmd(LPC_UART_TypeDef *UARTx, FunctionalState NewState); 614 FlagStatus UART_CheckBusy(LPC_UART_TypeDef *UARTx); 615 void UART_ForceBreak(LPC_UART_TypeDef* UARTx); 616 617 /* UART Auto-baud functions -----------------------------------------------------*/ 618 void UART_ABClearIntPending(LPC_UART_TypeDef *UARTx, UART_ABEO_Type ABIntType); 619 void UART_ABCmd(LPC_UART_TypeDef *UARTx, UART_AB_CFG_Type *ABConfigStruct, \ 620 FunctionalState NewState); 621 622 /* UART1 FullModem functions ----------------------------------------------------*/ 623 void UART_FullModemForcePinState(LPC_UART1_TypeDef *UARTx, UART_MODEM_PIN_Type Pin, \ 624 UART1_SignalState NewState); 625 void UART_FullModemConfigMode(LPC_UART1_TypeDef *UARTx, UART_MODEM_MODE_Type Mode, \ 626 FunctionalState NewState); 627 uint8_t UART_FullModemGetStatus(LPC_UART1_TypeDef *UARTx); 628 629 /* UART RS485 functions ----------------------------------------------------------*/ 630 void UART_RS485Config(LPC_UART1_TypeDef *UARTx, \ 631 UART1_RS485_CTRLCFG_Type *RS485ConfigStruct); 632 void UART_RS485ReceiverCmd(LPC_UART1_TypeDef *UARTx, FunctionalState NewState); 633 void UART_RS485SendSlvAddr(LPC_UART1_TypeDef *UARTx, uint8_t SlvAddr); 634 uint32_t UART_RS485SendData(LPC_UART1_TypeDef *UARTx, uint8_t *pData, uint32_t size); 635 636 /* UART IrDA functions-------------------------------------------------------------*/ 637 void UART_IrDAInvtInputCmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState); 638 void UART_IrDACmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState); 639 void UART_IrDAPulseDivConfig(LPC_UART_TypeDef *UARTx, UART_IrDA_PULSE_Type PulseDiv); 640 /** 641 * @} 642 */ 643 644 645 #ifdef __cplusplus 646 } 647 #endif 648 649 650 #endif /* __LPC17XX_UART_H */ 651 652 /** 653 * @} 654 */ 655 656 /* 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