lpc17xx_clkpwr.c (10879B)
1 /********************************************************************** 2 * $Id$ lpc17xx_clkpwr.c 2010-06-18 3 *//** 4 * @file lpc17xx_clkpwr.c 5 * @brief Contains all functions support for Clock and Power Control 6 * firmware library on LPC17xx 7 * @version 3.0 8 * @date 18. June. 2010 9 * @author NXP MCU SW Application Team 10 * 11 * Copyright(C) 2010, NXP Semiconductor 12 * All rights reserved. 13 * 14 *********************************************************************** 15 * Software that is described herein is for illustrative purposes only 16 * which provides customers with programming information regarding the 17 * products. This software is supplied "AS IS" without any warranties. 18 * NXP Semiconductors assumes no responsibility or liability for the 19 * use of the software, conveys no license or title under any patent, 20 * copyright, or mask work right to the product. NXP Semiconductors 21 * reserves the right to make changes in the software without 22 * notification. NXP Semiconductors also make no representation or 23 * warranty that such application will be suitable for the specified 24 * use without further testing or modification. 25 * Permission to use, copy, modify, and distribute this software and its 26 * documentation is hereby granted, under NXP Semiconductors' 27 * relevant copyright in the software, without fee, provided that it 28 * is used in conjunction with NXP Semiconductors microcontrollers. This 29 * copyright, permission, and disclaimer notice must appear in all copies of 30 * this code. 31 **********************************************************************/ 32 33 /* Peripheral group ----------------------------------------------------------- */ 34 /** @addtogroup CLKPWR 35 * @{ 36 */ 37 38 /* Includes ------------------------------------------------------------------- */ 39 #include "lpc17xx_clkpwr.h" 40 41 42 /* Public Functions ----------------------------------------------------------- */ 43 /** @addtogroup CLKPWR_Public_Functions 44 * @{ 45 */ 46 47 /*********************************************************************//** 48 * @brief Set value of each Peripheral Clock Selection 49 * @param[in] ClkType Peripheral Clock Selection of each type, 50 * should be one of the following: 51 * - CLKPWR_PCLKSEL_WDT : WDT 52 - CLKPWR_PCLKSEL_TIMER0 : Timer 0 53 - CLKPWR_PCLKSEL_TIMER1 : Timer 1 54 - CLKPWR_PCLKSEL_UART0 : UART 0 55 - CLKPWR_PCLKSEL_UART1 : UART 1 56 - CLKPWR_PCLKSEL_PWM1 : PWM 1 57 - CLKPWR_PCLKSEL_I2C0 : I2C 0 58 - CLKPWR_PCLKSEL_SPI : SPI 59 - CLKPWR_PCLKSEL_SSP1 : SSP 1 60 - CLKPWR_PCLKSEL_DAC : DAC 61 - CLKPWR_PCLKSEL_ADC : ADC 62 - CLKPWR_PCLKSEL_CAN1 : CAN 1 63 - CLKPWR_PCLKSEL_CAN2 : CAN 2 64 - CLKPWR_PCLKSEL_ACF : ACF 65 - CLKPWR_PCLKSEL_QEI : QEI 66 - CLKPWR_PCLKSEL_PCB : PCB 67 - CLKPWR_PCLKSEL_I2C1 : I2C 1 68 - CLKPWR_PCLKSEL_SSP0 : SSP 0 69 - CLKPWR_PCLKSEL_TIMER2 : Timer 2 70 - CLKPWR_PCLKSEL_TIMER3 : Timer 3 71 - CLKPWR_PCLKSEL_UART2 : UART 2 72 - CLKPWR_PCLKSEL_UART3 : UART 3 73 - CLKPWR_PCLKSEL_I2C2 : I2C 2 74 - CLKPWR_PCLKSEL_I2S : I2S 75 - CLKPWR_PCLKSEL_RIT : RIT 76 - CLKPWR_PCLKSEL_SYSCON : SYSCON 77 - CLKPWR_PCLKSEL_MC : MC 78 79 * @param[in] DivVal Value of divider, should be: 80 * - CLKPWR_PCLKSEL_CCLK_DIV_4 : PCLK_peripheral = CCLK/4 81 * - CLKPWR_PCLKSEL_CCLK_DIV_1 : PCLK_peripheral = CCLK/1 82 * - CLKPWR_PCLKSEL_CCLK_DIV_2 : PCLK_peripheral = CCLK/2 83 * 84 * @return none 85 **********************************************************************/ 86 void CLKPWR_SetPCLKDiv (uint32_t ClkType, uint32_t DivVal) 87 { 88 uint32_t bitpos; 89 90 bitpos = (ClkType < 32) ? (ClkType) : (ClkType - 32); 91 92 /* PCLKSEL0 selected */ 93 if (ClkType < 32) 94 { 95 /* Clear two bit at bit position */ 96 LPC_SC->PCLKSEL0 &= (~(CLKPWR_PCLKSEL_BITMASK(bitpos))); 97 98 /* Set two selected bit */ 99 LPC_SC->PCLKSEL0 |= (CLKPWR_PCLKSEL_SET(bitpos, DivVal)); 100 } 101 /* PCLKSEL1 selected */ 102 else 103 { 104 /* Clear two bit at bit position */ 105 LPC_SC->PCLKSEL1 &= ~(CLKPWR_PCLKSEL_BITMASK(bitpos)); 106 107 /* Set two selected bit */ 108 LPC_SC->PCLKSEL1 |= (CLKPWR_PCLKSEL_SET(bitpos, DivVal)); 109 } 110 } 111 112 113 /*********************************************************************//** 114 * @brief Get current value of each Peripheral Clock Selection 115 * @param[in] ClkType Peripheral Clock Selection of each type, 116 * should be one of the following: 117 * - CLKPWR_PCLKSEL_WDT : WDT 118 - CLKPWR_PCLKSEL_TIMER0 : Timer 0 119 - CLKPWR_PCLKSEL_TIMER1 : Timer 1 120 - CLKPWR_PCLKSEL_UART0 : UART 0 121 - CLKPWR_PCLKSEL_UART1 : UART 1 122 - CLKPWR_PCLKSEL_PWM1 : PWM 1 123 - CLKPWR_PCLKSEL_I2C0 : I2C 0 124 - CLKPWR_PCLKSEL_SPI : SPI 125 - CLKPWR_PCLKSEL_SSP1 : SSP 1 126 - CLKPWR_PCLKSEL_DAC : DAC 127 - CLKPWR_PCLKSEL_ADC : ADC 128 - CLKPWR_PCLKSEL_CAN1 : CAN 1 129 - CLKPWR_PCLKSEL_CAN2 : CAN 2 130 - CLKPWR_PCLKSEL_ACF : ACF 131 - CLKPWR_PCLKSEL_QEI : QEI 132 - CLKPWR_PCLKSEL_PCB : PCB 133 - CLKPWR_PCLKSEL_I2C1 : I2C 1 134 - CLKPWR_PCLKSEL_SSP0 : SSP 0 135 - CLKPWR_PCLKSEL_TIMER2 : Timer 2 136 - CLKPWR_PCLKSEL_TIMER3 : Timer 3 137 - CLKPWR_PCLKSEL_UART2 : UART 2 138 - CLKPWR_PCLKSEL_UART3 : UART 3 139 - CLKPWR_PCLKSEL_I2C2 : I2C 2 140 - CLKPWR_PCLKSEL_I2S : I2S 141 - CLKPWR_PCLKSEL_RIT : RIT 142 - CLKPWR_PCLKSEL_SYSCON : SYSCON 143 - CLKPWR_PCLKSEL_MC : MC 144 145 * @return Value of Selected Peripheral Clock Selection 146 **********************************************************************/ 147 uint32_t CLKPWR_GetPCLKSEL (uint32_t ClkType) 148 { 149 uint32_t bitpos, retval; 150 151 if (ClkType < 32) 152 { 153 bitpos = ClkType; 154 retval = LPC_SC->PCLKSEL0; 155 } 156 else 157 { 158 bitpos = ClkType - 32; 159 retval = LPC_SC->PCLKSEL1; 160 } 161 162 retval = CLKPWR_PCLKSEL_GET(bitpos, retval); 163 return retval; 164 } 165 166 167 168 /*********************************************************************//** 169 * @brief Get current value of each Peripheral Clock 170 * @param[in] ClkType Peripheral Clock Selection of each type, 171 * should be one of the following: 172 * - CLKPWR_PCLKSEL_WDT : WDT 173 - CLKPWR_PCLKSEL_TIMER0 : Timer 0 174 - CLKPWR_PCLKSEL_TIMER1 : Timer 1 175 - CLKPWR_PCLKSEL_UART0 : UART 0 176 - CLKPWR_PCLKSEL_UART1 : UART 1 177 - CLKPWR_PCLKSEL_PWM1 : PWM 1 178 - CLKPWR_PCLKSEL_I2C0 : I2C 0 179 - CLKPWR_PCLKSEL_SPI : SPI 180 - CLKPWR_PCLKSEL_SSP1 : SSP 1 181 - CLKPWR_PCLKSEL_DAC : DAC 182 - CLKPWR_PCLKSEL_ADC : ADC 183 - CLKPWR_PCLKSEL_CAN1 : CAN 1 184 - CLKPWR_PCLKSEL_CAN2 : CAN 2 185 - CLKPWR_PCLKSEL_ACF : ACF 186 - CLKPWR_PCLKSEL_QEI : QEI 187 - CLKPWR_PCLKSEL_PCB : PCB 188 - CLKPWR_PCLKSEL_I2C1 : I2C 1 189 - CLKPWR_PCLKSEL_SSP0 : SSP 0 190 - CLKPWR_PCLKSEL_TIMER2 : Timer 2 191 - CLKPWR_PCLKSEL_TIMER3 : Timer 3 192 - CLKPWR_PCLKSEL_UART2 : UART 2 193 - CLKPWR_PCLKSEL_UART3 : UART 3 194 - CLKPWR_PCLKSEL_I2C2 : I2C 2 195 - CLKPWR_PCLKSEL_I2S : I2S 196 - CLKPWR_PCLKSEL_RIT : RIT 197 - CLKPWR_PCLKSEL_SYSCON : SYSCON 198 - CLKPWR_PCLKSEL_MC : MC 199 200 * @return Value of Selected Peripheral Clock 201 **********************************************************************/ 202 uint32_t CLKPWR_GetPCLK (uint32_t ClkType) 203 { 204 uint32_t retval, div; 205 206 retval = SystemCoreClock; 207 div = CLKPWR_GetPCLKSEL(ClkType); 208 209 switch (div) 210 { 211 case 0: 212 div = 4; 213 break; 214 215 case 1: 216 div = 1; 217 break; 218 219 case 2: 220 div = 2; 221 break; 222 223 case 3: 224 div = 8; 225 break; 226 } 227 retval /= div; 228 229 return retval; 230 } 231 232 233 234 /*********************************************************************//** 235 * @brief Configure power supply for each peripheral according to NewState 236 * @param[in] PPType Type of peripheral used to enable power, 237 * should be one of the following: 238 * - CLKPWR_PCONP_PCTIM0 : Timer 0 239 - CLKPWR_PCONP_PCTIM1 : Timer 1 240 - CLKPWR_PCONP_PCUART0 : UART 0 241 - CLKPWR_PCONP_PCUART1 : UART 1 242 - CLKPWR_PCONP_PCPWM1 : PWM 1 243 - CLKPWR_PCONP_PCI2C0 : I2C 0 244 - CLKPWR_PCONP_PCSPI : SPI 245 - CLKPWR_PCONP_PCRTC : RTC 246 - CLKPWR_PCONP_PCSSP1 : SSP 1 247 - CLKPWR_PCONP_PCAD : ADC 248 - CLKPWR_PCONP_PCAN1 : CAN 1 249 - CLKPWR_PCONP_PCAN2 : CAN 2 250 - CLKPWR_PCONP_PCGPIO : GPIO 251 - CLKPWR_PCONP_PCRIT : RIT 252 - CLKPWR_PCONP_PCMC : MC 253 - CLKPWR_PCONP_PCQEI : QEI 254 - CLKPWR_PCONP_PCI2C1 : I2C 1 255 - CLKPWR_PCONP_PCSSP0 : SSP 0 256 - CLKPWR_PCONP_PCTIM2 : Timer 2 257 - CLKPWR_PCONP_PCTIM3 : Timer 3 258 - CLKPWR_PCONP_PCUART2 : UART 2 259 - CLKPWR_PCONP_PCUART3 : UART 3 260 - CLKPWR_PCONP_PCI2C2 : I2C 2 261 - CLKPWR_PCONP_PCI2S : I2S 262 - CLKPWR_PCONP_PCGPDMA : GPDMA 263 - CLKPWR_PCONP_PCENET : Ethernet 264 - CLKPWR_PCONP_PCUSB : USB 265 * 266 * @param[in] NewState New state of Peripheral Power, should be: 267 * - ENABLE : Enable power for this peripheral 268 * - DISABLE : Disable power for this peripheral 269 * 270 * @return none 271 **********************************************************************/ 272 void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState) 273 { 274 if (NewState == ENABLE) 275 { 276 LPC_SC->PCONP |= PPType & CLKPWR_PCONP_BITMASK; 277 } 278 else if (NewState == DISABLE) 279 { 280 LPC_SC->PCONP &= (~PPType) & CLKPWR_PCONP_BITMASK; 281 } 282 } 283 284 285 /*********************************************************************//** 286 * @brief Enter Sleep mode with co-operated instruction by the Cortex-M3. 287 * @param[in] None 288 * @return None 289 **********************************************************************/ 290 void CLKPWR_Sleep(void) 291 { 292 LPC_SC->PCON = 0x00; 293 /* Sleep Mode*/ 294 __WFI(); 295 } 296 297 298 /*********************************************************************//** 299 * @brief Enter Deep Sleep mode with co-operated instruction by the Cortex-M3. 300 * @param[in] None 301 * @return None 302 **********************************************************************/ 303 void CLKPWR_DeepSleep(void) 304 { 305 /* Deep-Sleep Mode, set SLEEPDEEP bit */ 306 SCB->SCR = 0x4; 307 LPC_SC->PCON = 0x00; 308 /* Deep Sleep Mode*/ 309 __WFI(); 310 } 311 312 313 /*********************************************************************//** 314 * @brief Enter Power Down mode with co-operated instruction by the Cortex-M3. 315 * @param[in] None 316 * @return None 317 **********************************************************************/ 318 void CLKPWR_PowerDown(void) 319 { 320 /* Deep-Sleep Mode, set SLEEPDEEP bit */ 321 SCB->SCR = 0x4; 322 LPC_SC->PCON = 0x01; 323 /* Power Down Mode*/ 324 __WFI(); 325 } 326 327 328 /*********************************************************************//** 329 * @brief Enter Deep Power Down mode with co-operated instruction by the Cortex-M3. 330 * @param[in] None 331 * @return None 332 **********************************************************************/ 333 void CLKPWR_DeepPowerDown(void) 334 { 335 /* Deep-Sleep Mode, set SLEEPDEEP bit */ 336 SCB->SCR = 0x4; 337 LPC_SC->PCON = 0x03; 338 /* Deep Power Down Mode*/ 339 __WFI(); 340 } 341 342 /** 343 * @} 344 */ 345 346 /** 347 * @} 348 */ 349 350 /* --------------------------------- End Of File ------------------------------ */