lpc17xx_gpdma.c (17592B)
1 /********************************************************************** 2 * $Id$ lpc17xx_gpdma.c 2010-03-21 3 *//** 4 * @file lpc17xx_gpdma.c 5 * @brief Contains all functions support for GPDMA firmware 6 * library on LPC17xx 7 * @version 2.1 8 * @date 25. July. 2011 9 * @author NXP MCU SW Application Team 10 * 11 * Copyright(C) 2010, NXP Semiconductor 12 * All rights reserved. 13 * 14 *********************************************************************** 15 * Software that is described herein is for illustrative purposes only 16 * which provides customers with programming information regarding the 17 * products. This software is supplied "AS IS" without any warranties. 18 * NXP Semiconductors assumes no responsibility or liability for the 19 * use of the software, conveys no license or title under any patent, 20 * copyright, or mask work right to the product. NXP Semiconductors 21 * reserves the right to make changes in the software without 22 * notification. NXP Semiconductors also make no representation or 23 * warranty that such application will be suitable for the specified 24 * use without further testing or modification. 25 * Permission to use, copy, modify, and distribute this software and its 26 * documentation is hereby granted, under NXP Semiconductors' 27 * relevant copyright in the software, without fee, provided that it 28 * is used in conjunction with NXP Semiconductors microcontrollers. This 29 * copyright, permission, and disclaimer notice must appear in all copies of 30 * this code. 31 **********************************************************************/ 32 33 /* Peripheral group ----------------------------------------------------------- */ 34 /** @addtogroup GPDMA 35 * @{ 36 */ 37 38 /* Includes ------------------------------------------------------------------- */ 39 #include "lpc17xx_gpdma.h" 40 #include "lpc17xx_clkpwr.h" 41 42 /* If this source file built with example, the LPC17xx FW library configuration 43 * file in each example directory ("lpc17xx_libcfg.h") must be included, 44 * otherwise the default FW library configuration file must be included instead 45 */ 46 #ifdef __BUILD_WITH_EXAMPLE__ 47 #include "lpc17xx_libcfg.h" 48 #else 49 #include "lpc17xx_libcfg_default.h" 50 #endif /* __BUILD_WITH_EXAMPLE__ */ 51 52 #ifdef _GPDMA 53 54 55 /* Private Variables ---------------------------------------------------------- */ 56 /** @defgroup GPDMA_Private_Variables GPDMA Private Variables 57 * @{ 58 */ 59 60 /** 61 * @brief Lookup Table of Connection Type matched with 62 * Peripheral Data (FIFO) register base address 63 */ 64 //#ifdef __IAR_SYSTEMS_ICC__ 65 volatile const void *GPDMA_LUTPerAddr[] = { 66 (&LPC_SSP0->DR), // SSP0 Tx 67 (&LPC_SSP0->DR), // SSP0 Rx 68 (&LPC_SSP1->DR), // SSP1 Tx 69 (&LPC_SSP1->DR), // SSP1 Rx 70 (&LPC_ADC->ADGDR), // ADC 71 (&LPC_I2S->I2STXFIFO), // I2S Tx 72 (&LPC_I2S->I2SRXFIFO), // I2S Rx 73 (&LPC_DAC->DACR), // DAC 74 (&LPC_UART0->/*RBTHDLR.*/THR), // UART0 Tx 75 (&LPC_UART0->/*RBTHDLR.*/RBR), // UART0 Rx 76 (&LPC_UART1->/*RBTHDLR.*/THR), // UART1 Tx 77 (&LPC_UART1->/*RBTHDLR.*/RBR), // UART1 Rx 78 (&LPC_UART2->/*RBTHDLR.*/THR), // UART2 Tx 79 (&LPC_UART2->/*RBTHDLR.*/RBR), // UART2 Rx 80 (&LPC_UART3->/*RBTHDLR.*/THR), // UART3 Tx 81 (&LPC_UART3->/*RBTHDLR.*/RBR), // UART3 Rx 82 (&LPC_TIM0->MR0), // MAT0.0 83 (&LPC_TIM0->MR1), // MAT0.1 84 (&LPC_TIM1->MR0), // MAT1.0 85 (&LPC_TIM1->MR1), // MAT1.1 86 (&LPC_TIM2->MR0), // MAT2.0 87 (&LPC_TIM2->MR1), // MAT2.1 88 (&LPC_TIM3->MR0), // MAT3.0 89 (&LPC_TIM3->MR1) // MAT3.1 90 }; 91 //#else 92 //const uint32_t GPDMA_LUTPerAddr[] = { 93 // ((uint32_t)&LPC_SSP0->DR), // SSP0 Tx 94 // ((uint32_t)&LPC_SSP0->DR), // SSP0 Rx 95 // ((uint32_t)&LPC_SSP1->DR), // SSP1 Tx 96 // ((uint32_t)&LPC_SSP1->DR), // SSP1 Rx 97 // ((uint32_t)&LPC_ADC->ADGDR), // ADC 98 // ((uint32_t)&LPC_I2S->I2STXFIFO), // I2S Tx 99 // ((uint32_t)&LPC_I2S->I2SRXFIFO), // I2S Rx 100 // ((uint32_t)&LPC_DAC->DACR), // DAC 101 // ((uint32_t)&LPC_UART0->/*RBTHDLR.*/THR), // UART0 Tx 102 // ((uint32_t)&LPC_UART0->/*RBTHDLR.*/RBR), // UART0 Rx 103 // ((uint32_t)&LPC_UART1->/*RBTHDLR.*/THR), // UART1 Tx 104 // ((uint32_t)&LPC_UART1->/*RBTHDLR.*/RBR), // UART1 Rx 105 // ((uint32_t)&LPC_UART2->/*RBTHDLR.*/THR), // UART2 Tx 106 // ((uint32_t)&LPC_UART2->/*RBTHDLR.*/RBR), // UART2 Rx 107 // ((uint32_t)&LPC_UART3->/*RBTHDLR.*/THR), // UART3 Tx 108 // ((uint32_t)&LPC_UART3->/*RBTHDLR.*/RBR), // UART3 Rx 109 // ((uint32_t)&LPC_TIM0->MR0), // MAT0.0 110 // ((uint32_t)&LPC_TIM0->MR1), // MAT0.1 111 // ((uint32_t)&LPC_TIM1->MR0), // MAT1.0 112 // ((uint32_t)&LPC_TIM1->MR1), // MAT1.1 113 // ((uint32_t)&LPC_TIM2->MR0), // MAT2.0 114 // ((uint32_t)&LPC_TIM2->MR1), // MAT2.1 115 // ((uint32_t)&LPC_TIM3->MR0), // MAT3.0 116 // ((uint32_t)&LPC_TIM3->MR1) // MAT3.1 117 //}; 118 //#endif 119 /** 120 * @brief Lookup Table of GPDMA Channel Number matched with 121 * GPDMA channel pointer 122 */ 123 const LPC_GPDMACH_TypeDef *pGPDMACh[8] = { 124 LPC_GPDMACH0, // GPDMA Channel 0 125 LPC_GPDMACH1, // GPDMA Channel 1 126 LPC_GPDMACH2, // GPDMA Channel 2 127 LPC_GPDMACH3, // GPDMA Channel 3 128 LPC_GPDMACH4, // GPDMA Channel 4 129 LPC_GPDMACH5, // GPDMA Channel 5 130 LPC_GPDMACH6, // GPDMA Channel 6 131 LPC_GPDMACH7 // GPDMA Channel 7 132 }; 133 /** 134 * @brief Optimized Peripheral Source and Destination burst size 135 */ 136 const uint8_t GPDMA_LUTPerBurst[] = { 137 GPDMA_BSIZE_4, // SSP0 Tx 138 GPDMA_BSIZE_4, // SSP0 Rx 139 GPDMA_BSIZE_4, // SSP1 Tx 140 GPDMA_BSIZE_4, // SSP1 Rx 141 GPDMA_BSIZE_1, // ADC 142 GPDMA_BSIZE_32, // I2S channel 0 143 GPDMA_BSIZE_32, // I2S channel 1 144 GPDMA_BSIZE_1, // DAC 145 GPDMA_BSIZE_1, // UART0 Tx 146 GPDMA_BSIZE_1, // UART0 Rx 147 GPDMA_BSIZE_1, // UART1 Tx 148 GPDMA_BSIZE_1, // UART1 Rx 149 GPDMA_BSIZE_1, // UART2 Tx 150 GPDMA_BSIZE_1, // UART2 Rx 151 GPDMA_BSIZE_1, // UART3 Tx 152 GPDMA_BSIZE_1, // UART3 Rx 153 GPDMA_BSIZE_1, // MAT0.0 154 GPDMA_BSIZE_1, // MAT0.1 155 GPDMA_BSIZE_1, // MAT1.0 156 GPDMA_BSIZE_1, // MAT1.1 157 GPDMA_BSIZE_1, // MAT2.0 158 GPDMA_BSIZE_1, // MAT2.1 159 GPDMA_BSIZE_1, // MAT3.0 160 GPDMA_BSIZE_1 // MAT3.1 161 }; 162 /** 163 * @brief Optimized Peripheral Source and Destination transfer width 164 */ 165 const uint8_t GPDMA_LUTPerWid[] = { 166 GPDMA_WIDTH_BYTE, // SSP0 Tx 167 GPDMA_WIDTH_BYTE, // SSP0 Rx 168 GPDMA_WIDTH_BYTE, // SSP1 Tx 169 GPDMA_WIDTH_BYTE, // SSP1 Rx 170 GPDMA_WIDTH_WORD, // ADC 171 GPDMA_WIDTH_WORD, // I2S channel 0 172 GPDMA_WIDTH_WORD, // I2S channel 1 173 GPDMA_WIDTH_BYTE, // DAC 174 GPDMA_WIDTH_BYTE, // UART0 Tx 175 GPDMA_WIDTH_BYTE, // UART0 Rx 176 GPDMA_WIDTH_BYTE, // UART1 Tx 177 GPDMA_WIDTH_BYTE, // UART1 Rx 178 GPDMA_WIDTH_BYTE, // UART2 Tx 179 GPDMA_WIDTH_BYTE, // UART2 Rx 180 GPDMA_WIDTH_BYTE, // UART3 Tx 181 GPDMA_WIDTH_BYTE, // UART3 Rx 182 GPDMA_WIDTH_WORD, // MAT0.0 183 GPDMA_WIDTH_WORD, // MAT0.1 184 GPDMA_WIDTH_WORD, // MAT1.0 185 GPDMA_WIDTH_WORD, // MAT1.1 186 GPDMA_WIDTH_WORD, // MAT2.0 187 GPDMA_WIDTH_WORD, // MAT2.1 188 GPDMA_WIDTH_WORD, // MAT3.0 189 GPDMA_WIDTH_WORD // MAT3.1 190 }; 191 192 /** 193 * @} 194 */ 195 196 /* Public Functions ----------------------------------------------------------- */ 197 /** @addtogroup GPDMA_Public_Functions 198 * @{ 199 */ 200 201 /********************************************************************//** 202 * @brief Initialize GPDMA controller 203 * @param None 204 * @return None 205 *********************************************************************/ 206 void GPDMA_Init(void) 207 { 208 /* Enable GPDMA clock */ 209 CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCGPDMA, ENABLE); 210 211 // Reset all channel configuration register 212 LPC_GPDMACH0->DMACCConfig = 0; 213 LPC_GPDMACH1->DMACCConfig = 0; 214 LPC_GPDMACH2->DMACCConfig = 0; 215 LPC_GPDMACH3->DMACCConfig = 0; 216 LPC_GPDMACH4->DMACCConfig = 0; 217 LPC_GPDMACH5->DMACCConfig = 0; 218 LPC_GPDMACH6->DMACCConfig = 0; 219 LPC_GPDMACH7->DMACCConfig = 0; 220 221 /* Clear all DMA interrupt and error flag */ 222 LPC_GPDMA->DMACIntTCClear = 0xFF; 223 LPC_GPDMA->DMACIntErrClr = 0xFF; 224 } 225 226 /********************************************************************//** 227 * @brief Setup GPDMA channel peripheral according to the specified 228 * parameters in the GPDMAChannelConfig. 229 * @param[in] GPDMAChannelConfig Pointer to a GPDMA_CH_CFG_Type 230 * structure that contains the configuration 231 * information for the specified GPDMA channel peripheral. 232 * @return ERROR if selected channel is enabled before 233 * or SUCCESS if channel is configured successfully 234 *********************************************************************/ 235 Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig) 236 { 237 LPC_GPDMACH_TypeDef *pDMAch; 238 uint32_t tmp1, tmp2; 239 240 if (LPC_GPDMA->DMACEnbldChns & (GPDMA_DMACEnbldChns_Ch(GPDMAChannelConfig->ChannelNum))) { 241 // This channel is enabled, return ERROR, need to release this channel first 242 return ERROR; 243 } 244 245 // Get Channel pointer 246 pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[GPDMAChannelConfig->ChannelNum]; 247 248 // Reset the Interrupt status 249 LPC_GPDMA->DMACIntTCClear = GPDMA_DMACIntTCClear_Ch(GPDMAChannelConfig->ChannelNum); 250 LPC_GPDMA->DMACIntErrClr = GPDMA_DMACIntErrClr_Ch(GPDMAChannelConfig->ChannelNum); 251 252 // Clear DMA configure 253 pDMAch->DMACCControl = 0x00; 254 pDMAch->DMACCConfig = 0x00; 255 256 /* Assign Linker List Item value */ 257 pDMAch->DMACCLLI = GPDMAChannelConfig->DMALLI; 258 259 /* Set value to Channel Control Registers */ 260 switch (GPDMAChannelConfig->TransferType) 261 { 262 // Memory to memory 263 case GPDMA_TRANSFERTYPE_M2M: 264 // Assign physical source and destination address 265 pDMAch->DMACCSrcAddr = GPDMAChannelConfig->SrcMemAddr; 266 pDMAch->DMACCDestAddr = GPDMAChannelConfig->DstMemAddr; 267 pDMAch->DMACCControl 268 = GPDMA_DMACCxControl_TransferSize(GPDMAChannelConfig->TransferSize) \ 269 | GPDMA_DMACCxControl_SBSize(GPDMA_BSIZE_32) \ 270 | GPDMA_DMACCxControl_DBSize(GPDMA_BSIZE_32) \ 271 | GPDMA_DMACCxControl_SWidth(GPDMAChannelConfig->TransferWidth) \ 272 | GPDMA_DMACCxControl_DWidth(GPDMAChannelConfig->TransferWidth) \ 273 | GPDMA_DMACCxControl_SI \ 274 | GPDMA_DMACCxControl_DI \ 275 | GPDMA_DMACCxControl_I; 276 break; 277 // Memory to peripheral 278 case GPDMA_TRANSFERTYPE_M2P: 279 // Assign physical source 280 pDMAch->DMACCSrcAddr = GPDMAChannelConfig->SrcMemAddr; 281 // Assign peripheral destination address 282 pDMAch->DMACCDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn]; 283 pDMAch->DMACCControl 284 = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \ 285 | GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \ 286 | GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \ 287 | GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \ 288 | GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \ 289 | GPDMA_DMACCxControl_SI \ 290 | GPDMA_DMACCxControl_I; 291 break; 292 // Peripheral to memory 293 case GPDMA_TRANSFERTYPE_P2M: 294 // Assign peripheral source address 295 pDMAch->DMACCSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn]; 296 // Assign memory destination address 297 pDMAch->DMACCDestAddr = GPDMAChannelConfig->DstMemAddr; 298 pDMAch->DMACCControl 299 = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \ 300 | GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \ 301 | GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \ 302 | GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \ 303 | GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \ 304 | GPDMA_DMACCxControl_DI \ 305 | GPDMA_DMACCxControl_I; 306 break; 307 // Peripheral to peripheral 308 case GPDMA_TRANSFERTYPE_P2P: 309 // Assign peripheral source address 310 pDMAch->DMACCSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn]; 311 // Assign peripheral destination address 312 pDMAch->DMACCDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn]; 313 pDMAch->DMACCControl 314 = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \ 315 | GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \ 316 | GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \ 317 | GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \ 318 | GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \ 319 | GPDMA_DMACCxControl_I; 320 break; 321 // Do not support any more transfer type, return ERROR 322 default: 323 return ERROR; 324 } 325 326 /* Re-Configure DMA Request Select for source peripheral */ 327 if (GPDMAChannelConfig->SrcConn > 15) 328 { 329 LPC_SC->DMAREQSEL |= (1<<(GPDMAChannelConfig->SrcConn - 16)); 330 } else { 331 LPC_SC->DMAREQSEL &= ~(1<<(GPDMAChannelConfig->SrcConn - 8)); 332 } 333 334 /* Re-Configure DMA Request Select for Destination peripheral */ 335 if (GPDMAChannelConfig->DstConn > 15) 336 { 337 LPC_SC->DMAREQSEL |= (1<<(GPDMAChannelConfig->DstConn - 16)); 338 } else { 339 LPC_SC->DMAREQSEL &= ~(1<<(GPDMAChannelConfig->DstConn - 8)); 340 } 341 342 /* Enable DMA channels, little endian */ 343 LPC_GPDMA->DMACConfig = GPDMA_DMACConfig_E; 344 while (!(LPC_GPDMA->DMACConfig & GPDMA_DMACConfig_E)); 345 346 // Calculate absolute value for Connection number 347 tmp1 = GPDMAChannelConfig->SrcConn; 348 tmp1 = ((tmp1 > 15) ? (tmp1 - 8) : tmp1); 349 tmp2 = GPDMAChannelConfig->DstConn; 350 tmp2 = ((tmp2 > 15) ? (tmp2 - 8) : tmp2); 351 352 // Configure DMA Channel, enable Error Counter and Terminate counter 353 pDMAch->DMACCConfig = GPDMA_DMACCxConfig_IE | GPDMA_DMACCxConfig_ITC /*| GPDMA_DMACCxConfig_E*/ \ 354 | GPDMA_DMACCxConfig_TransferType((uint32_t)GPDMAChannelConfig->TransferType) \ 355 | GPDMA_DMACCxConfig_SrcPeripheral(tmp1) \ 356 | GPDMA_DMACCxConfig_DestPeripheral(tmp2); 357 358 return SUCCESS; 359 } 360 361 362 /*********************************************************************//** 363 * @brief Enable/Disable DMA channel 364 * @param[in] channelNum GPDMA channel, should be in range from 0 to 7 365 * @param[in] NewState New State of this command, should be: 366 * - ENABLE. 367 * - DISABLE. 368 * @return None 369 **********************************************************************/ 370 void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState) 371 { 372 LPC_GPDMACH_TypeDef *pDMAch; 373 374 // Get Channel pointer 375 pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[channelNum]; 376 377 if (NewState == ENABLE) { 378 pDMAch->DMACCConfig |= GPDMA_DMACCxConfig_E; 379 } else { 380 pDMAch->DMACCConfig &= ~GPDMA_DMACCxConfig_E; 381 } 382 } 383 /*********************************************************************//** 384 * @brief Check if corresponding channel does have an active interrupt 385 * request or not 386 * @param[in] type type of status, should be: 387 * - GPDMA_STAT_INT: GPDMA Interrupt Status 388 * - GPDMA_STAT_INTTC: GPDMA Interrupt Terminal Count Request Status 389 * - GPDMA_STAT_INTERR: GPDMA Interrupt Error Status 390 * - GPDMA_STAT_RAWINTTC: GPDMA Raw Interrupt Terminal Count Status 391 * - GPDMA_STAT_RAWINTERR: GPDMA Raw Error Interrupt Status 392 * - GPDMA_STAT_ENABLED_CH:GPDMA Enabled Channel Status 393 * @param[in] channel GPDMA channel, should be in range from 0 to 7 394 * @return IntStatus status of DMA channel interrupt after masking 395 * Should be: 396 * - SET: the corresponding channel has no active interrupt request 397 * - RESET: the corresponding channel does have an active interrupt request 398 **********************************************************************/ 399 IntStatus GPDMA_IntGetStatus(GPDMA_Status_Type type, uint8_t channel) 400 { 401 CHECK_PARAM(PARAM_GPDMA_STAT(type)); 402 CHECK_PARAM(PARAM_GPDMA_CHANNEL(channel)); 403 404 switch (type) 405 { 406 case GPDMA_STAT_INT: //check status of DMA channel interrupts 407 if (LPC_GPDMA->DMACIntStat & (GPDMA_DMACIntStat_Ch(channel))) 408 return SET; 409 return RESET; 410 case GPDMA_STAT_INTTC: // check terminal count interrupt request status for DMA 411 if (LPC_GPDMA->DMACIntTCStat & GPDMA_DMACIntTCStat_Ch(channel)) 412 return SET; 413 return RESET; 414 case GPDMA_STAT_INTERR: //check interrupt status for DMA channels 415 if (LPC_GPDMA->DMACIntErrStat & GPDMA_DMACIntTCClear_Ch(channel)) 416 return SET; 417 return RESET; 418 case GPDMA_STAT_RAWINTTC: //check status of the terminal count interrupt for DMA channels 419 if (LPC_GPDMA->DMACRawIntErrStat & GPDMA_DMACRawIntTCStat_Ch(channel)) 420 return SET; 421 return RESET; 422 case GPDMA_STAT_RAWINTERR: //check status of the error interrupt for DMA channels 423 if (LPC_GPDMA->DMACRawIntTCStat & GPDMA_DMACRawIntErrStat_Ch(channel)) 424 return SET; 425 return RESET; 426 default: //check enable status for DMA channels 427 if (LPC_GPDMA->DMACEnbldChns & GPDMA_DMACEnbldChns_Ch(channel)) 428 return SET; 429 return RESET; 430 } 431 } 432 433 /*********************************************************************//** 434 * @brief Clear one or more interrupt requests on DMA channels 435 * @param[in] type type of interrupt request, should be: 436 * - GPDMA_STATCLR_INTTC: GPDMA Interrupt Terminal Count Request Clear 437 * - GPDMA_STATCLR_INTERR: GPDMA Interrupt Error Clear 438 * @param[in] channel GPDMA channel, should be in range from 0 to 7 439 * @return None 440 **********************************************************************/ 441 void GPDMA_ClearIntPending(GPDMA_StateClear_Type type, uint8_t channel) 442 { 443 CHECK_PARAM(PARAM_GPDMA_STATCLR(type)); 444 CHECK_PARAM(PARAM_GPDMA_CHANNEL(channel)); 445 446 if (type == GPDMA_STATCLR_INTTC) // clears the terminal count interrupt request on DMA channel 447 LPC_GPDMA->DMACIntTCClear = GPDMA_DMACIntTCClear_Ch(channel); 448 else // clear the error interrupt request 449 LPC_GPDMA->DMACIntErrClr = GPDMA_DMACIntErrClr_Ch(channel); 450 } 451 452 /** 453 * @} 454 */ 455 456 #endif /* _GPDMA */ 457 458 /** 459 * @} 460 */ 461 462 /* --------------------------------- End Of File ------------------------------ */ 463