system_LPC17xx.c (22664B)
1 /**************************************************************************//** 2 * @file system_LPC17xx.c 3 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File 4 * for the NXP LPC17xx Device Series 5 * @version V1.03 6 * @date 07. October 2009 7 * 8 * @note 9 * Copyright (C) 2009 ARM Limited. All rights reserved. 10 * 11 * @par 12 * ARM Limited (ARM) is supplying this software for use with Cortex-M 13 * processor based microcontrollers. This file can be freely distributed 14 * within development tools that are supporting such ARM based processors. 15 * 16 * @par 17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED 18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF 19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. 20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR 21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. 22 * 23 ******************************************************************************/ 24 25 26 #include <stdint.h> 27 #include "LPC17xx.h" 28 29 /** @addtogroup LPC17xx_System 30 * @{ 31 */ 32 33 /* 34 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ 35 */ 36 37 /*--------------------- Clock Configuration ---------------------------------- 38 // 39 // <e> Clock Configuration 40 // <h> System Controls and Status Register (SCS) 41 // <o1.4> OSCRANGE: Main Oscillator Range Select 42 // <0=> 1 MHz to 20 MHz 43 // <1=> 15 MHz to 24 MHz 44 // <e1.5> OSCEN: Main Oscillator Enable 45 // </e> 46 // </h> 47 // 48 // <h> Clock Source Select Register (CLKSRCSEL) 49 // <o2.0..1> CLKSRC: PLL Clock Source Selection 50 // <0=> Internal RC oscillator 51 // <1=> Main oscillator 52 // <2=> RTC oscillator 53 // </h> 54 // 55 // <e3> PLL0 Configuration (Main PLL) 56 // <h> PLL0 Configuration Register (PLL0CFG) 57 // <i> F_cco0 = (2 * M * F_in) / N 58 // <i> F_in must be in the range of 32 kHz to 50 MHz 59 // <i> F_cco0 must be in the range of 275 MHz to 550 MHz 60 // <o4.0..14> MSEL: PLL Multiplier Selection 61 // <6-32768><#-1> 62 // <i> M Value 63 // <o4.16..23> NSEL: PLL Divider Selection 64 // <1-256><#-1> 65 // <i> N Value 66 // </h> 67 // </e> 68 // 69 // <e5> PLL1 Configuration (USB PLL) 70 // <h> PLL1 Configuration Register (PLL1CFG) 71 // <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P) 72 // <i> F_cco1 = F_osc * M * 2 * P 73 // <i> F_cco1 must be in the range of 156 MHz to 320 MHz 74 // <o6.0..4> MSEL: PLL Multiplier Selection 75 // <1-32><#-1> 76 // <i> M Value (for USB maximum value is 4) 77 // <o6.5..6> PSEL: PLL Divider Selection 78 // <0=> 1 79 // <1=> 2 80 // <2=> 4 81 // <3=> 8 82 // <i> P Value 83 // </h> 84 // </e> 85 // 86 // <h> CPU Clock Configuration Register (CCLKCFG) 87 // <o7.0..7> CCLKSEL: Divide Value for CPU Clock from PLL0 88 // <3-256><#-1> 89 // </h> 90 // 91 // <h> USB Clock Configuration Register (USBCLKCFG) 92 // <o8.0..3> USBSEL: Divide Value for USB Clock from PLL0 93 // <0-15> 94 // <i> Divide is USBSEL + 1 95 // </h> 96 // 97 // <h> Peripheral Clock Selection Register 0 (PCLKSEL0) 98 // <o9.0..1> PCLK_WDT: Peripheral Clock Selection for WDT 99 // <0=> Pclk = Cclk / 4 100 // <1=> Pclk = Cclk 101 // <2=> Pclk = Cclk / 2 102 // <3=> Pclk = Hclk / 8 103 // <o9.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0 104 // <0=> Pclk = Cclk / 4 105 // <1=> Pclk = Cclk 106 // <2=> Pclk = Cclk / 2 107 // <3=> Pclk = Hclk / 8 108 // <o9.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1 109 // <0=> Pclk = Cclk / 4 110 // <1=> Pclk = Cclk 111 // <2=> Pclk = Cclk / 2 112 // <3=> Pclk = Hclk / 8 113 // <o9.6..7> PCLK_UART0: Peripheral Clock Selection for UART0 114 // <0=> Pclk = Cclk / 4 115 // <1=> Pclk = Cclk 116 // <2=> Pclk = Cclk / 2 117 // <3=> Pclk = Hclk / 8 118 // <o9.8..9> PCLK_UART1: Peripheral Clock Selection for UART1 119 // <0=> Pclk = Cclk / 4 120 // <1=> Pclk = Cclk 121 // <2=> Pclk = Cclk / 2 122 // <3=> Pclk = Hclk / 8 123 // <o9.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1 124 // <0=> Pclk = Cclk / 4 125 // <1=> Pclk = Cclk 126 // <2=> Pclk = Cclk / 2 127 // <3=> Pclk = Hclk / 8 128 // <o9.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0 129 // <0=> Pclk = Cclk / 4 130 // <1=> Pclk = Cclk 131 // <2=> Pclk = Cclk / 2 132 // <3=> Pclk = Hclk / 8 133 // <o9.16..17> PCLK_SPI: Peripheral Clock Selection for SPI 134 // <0=> Pclk = Cclk / 4 135 // <1=> Pclk = Cclk 136 // <2=> Pclk = Cclk / 2 137 // <3=> Pclk = Hclk / 8 138 // <o9.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1 139 // <0=> Pclk = Cclk / 4 140 // <1=> Pclk = Cclk 141 // <2=> Pclk = Cclk / 2 142 // <3=> Pclk = Hclk / 8 143 // <o9.22..23> PCLK_DAC: Peripheral Clock Selection for DAC 144 // <0=> Pclk = Cclk / 4 145 // <1=> Pclk = Cclk 146 // <2=> Pclk = Cclk / 2 147 // <3=> Pclk = Hclk / 8 148 // <o9.24..25> PCLK_ADC: Peripheral Clock Selection for ADC 149 // <0=> Pclk = Cclk / 4 150 // <1=> Pclk = Cclk 151 // <2=> Pclk = Cclk / 2 152 // <3=> Pclk = Hclk / 8 153 // <o9.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1 154 // <0=> Pclk = Cclk / 4 155 // <1=> Pclk = Cclk 156 // <2=> Pclk = Cclk / 2 157 // <3=> Pclk = Hclk / 6 158 // <o9.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2 159 // <0=> Pclk = Cclk / 4 160 // <1=> Pclk = Cclk 161 // <2=> Pclk = Cclk / 2 162 // <3=> Pclk = Hclk / 6 163 // <o9.30..31> PCLK_ACF: Peripheral Clock Selection for ACF 164 // <0=> Pclk = Cclk / 4 165 // <1=> Pclk = Cclk 166 // <2=> Pclk = Cclk / 2 167 // <3=> Pclk = Hclk / 6 168 // </h> 169 // 170 // <h> Peripheral Clock Selection Register 1 (PCLKSEL1) 171 // <o10.0..1> PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface 172 // <0=> Pclk = Cclk / 4 173 // <1=> Pclk = Cclk 174 // <2=> Pclk = Cclk / 2 175 // <3=> Pclk = Hclk / 8 176 // <o10.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs 177 // <0=> Pclk = Cclk / 4 178 // <1=> Pclk = Cclk 179 // <2=> Pclk = Cclk / 2 180 // <3=> Pclk = Hclk / 8 181 // <o10.4..5> PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block 182 // <0=> Pclk = Cclk / 4 183 // <1=> Pclk = Cclk 184 // <2=> Pclk = Cclk / 2 185 // <3=> Pclk = Hclk / 8 186 // <o10.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1 187 // <0=> Pclk = Cclk / 4 188 // <1=> Pclk = Cclk 189 // <2=> Pclk = Cclk / 2 190 // <3=> Pclk = Hclk / 8 191 // <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0 192 // <0=> Pclk = Cclk / 4 193 // <1=> Pclk = Cclk 194 // <2=> Pclk = Cclk / 2 195 // <3=> Pclk = Hclk / 8 196 // <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2 197 // <0=> Pclk = Cclk / 4 198 // <1=> Pclk = Cclk 199 // <2=> Pclk = Cclk / 2 200 // <3=> Pclk = Hclk / 8 201 // <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3 202 // <0=> Pclk = Cclk / 4 203 // <1=> Pclk = Cclk 204 // <2=> Pclk = Cclk / 2 205 // <3=> Pclk = Hclk / 8 206 // <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2 207 // <0=> Pclk = Cclk / 4 208 // <1=> Pclk = Cclk 209 // <2=> Pclk = Cclk / 2 210 // <3=> Pclk = Hclk / 8 211 // <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3 212 // <0=> Pclk = Cclk / 4 213 // <1=> Pclk = Cclk 214 // <2=> Pclk = Cclk / 2 215 // <3=> Pclk = Hclk / 8 216 // <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2 217 // <0=> Pclk = Cclk / 4 218 // <1=> Pclk = Cclk 219 // <2=> Pclk = Cclk / 2 220 // <3=> Pclk = Hclk / 8 221 // <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S 222 // <0=> Pclk = Cclk / 4 223 // <1=> Pclk = Cclk 224 // <2=> Pclk = Cclk / 2 225 // <3=> Pclk = Hclk / 8 226 // <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer 227 // <0=> Pclk = Cclk / 4 228 // <1=> Pclk = Cclk 229 // <2=> Pclk = Cclk / 2 230 // <3=> Pclk = Hclk / 8 231 // <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block 232 // <0=> Pclk = Cclk / 4 233 // <1=> Pclk = Cclk 234 // <2=> Pclk = Cclk / 2 235 // <3=> Pclk = Hclk / 8 236 // <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM 237 // <0=> Pclk = Cclk / 4 238 // <1=> Pclk = Cclk 239 // <2=> Pclk = Cclk / 2 240 // <3=> Pclk = Hclk / 8 241 // </h> 242 // 243 // <h> Power Control for Peripherals Register (PCONP) 244 // <o11.1> PCTIM0: Timer/Counter 0 power/clock enable 245 // <o11.2> PCTIM1: Timer/Counter 1 power/clock enable 246 // <o11.3> PCUART0: UART 0 power/clock enable 247 // <o11.4> PCUART1: UART 1 power/clock enable 248 // <o11.6> PCPWM1: PWM 1 power/clock enable 249 // <o11.7> PCI2C0: I2C interface 0 power/clock enable 250 // <o11.8> PCSPI: SPI interface power/clock enable 251 // <o11.9> PCRTC: RTC power/clock enable 252 // <o11.10> PCSSP1: SSP interface 1 power/clock enable 253 // <o11.12> PCAD: A/D converter power/clock enable 254 // <o11.13> PCCAN1: CAN controller 1 power/clock enable 255 // <o11.14> PCCAN2: CAN controller 2 power/clock enable 256 // <o11.15> PCGPIO: GPIOs power/clock enable 257 // <o11.16> PCRIT: Repetitive interrupt timer power/clock enable 258 // <o11.17> PCMC: Motor control PWM power/clock enable 259 // <o11.18> PCQEI: Quadrature encoder interface power/clock enable 260 // <o11.19> PCI2C1: I2C interface 1 power/clock enable 261 // <o11.21> PCSSP0: SSP interface 0 power/clock enable 262 // <o11.22> PCTIM2: Timer 2 power/clock enable 263 // <o11.23> PCTIM3: Timer 3 power/clock enable 264 // <o11.24> PCUART2: UART 2 power/clock enable 265 // <o11.25> PCUART3: UART 3 power/clock enable 266 // <o11.26> PCI2C2: I2C interface 2 power/clock enable 267 // <o11.27> PCI2S: I2S interface power/clock enable 268 // <o11.29> PCGPDMA: GP DMA function power/clock enable 269 // <o11.30> PCENET: Ethernet block power/clock enable 270 // <o11.31> PCUSB: USB interface power/clock enable 271 // </h> 272 // 273 // <h> Clock Output Configuration Register (CLKOUTCFG) 274 // <o12.0..3> CLKOUTSEL: Selects clock source for CLKOUT 275 // <0=> CPU clock 276 // <1=> Main oscillator 277 // <2=> Internal RC oscillator 278 // <3=> USB clock 279 // <4=> RTC oscillator 280 // <o12.4..7> CLKOUTDIV: Selects clock divider for CLKOUT 281 // <1-16><#-1> 282 // <o12.8> CLKOUT_EN: CLKOUT enable control 283 // </h> 284 // 285 // </e> 286 */ 287 288 289 290 /** @addtogroup LPC17xx_System_Defines LPC17xx System Defines 291 @{ 292 */ 293 294 #define CLOCK_SETUP 1 295 #define SCS_Val 0x00000020 296 #define CLKSRCSEL_Val 0x00000001 297 #define PLL0_SETUP 1 298 #define PLL0CFG_Val 0x00050063 299 #define PLL1_SETUP 1 300 #define PLL1CFG_Val 0x00000023 301 #define CCLKCFG_Val 0x00000003 302 #define USBCLKCFG_Val 0x00000000 303 #define PCLKSEL0_Val 0x00000000 304 #define PCLKSEL1_Val 0x00000000 305 #define PCONP_Val 0x042887DE 306 #define CLKOUTCFG_Val 0x00000000 307 308 309 /*--------------------- Flash Accelerator Configuration ---------------------- 310 // 311 // <e> Flash Accelerator Configuration 312 // <o1.0..11> Reserved 313 // <o1.12..15> FLASHTIM: Flash Access Time 314 // <0=> 1 CPU clock (for CPU clock up to 20 MHz) 315 // <1=> 2 CPU clocks (for CPU clock up to 40 MHz) 316 // <2=> 3 CPU clocks (for CPU clock up to 60 MHz) 317 // <3=> 4 CPU clocks (for CPU clock up to 80 MHz) 318 // <4=> 5 CPU clocks (for CPU clock up to 100 MHz) 319 // <5=> 6 CPU clocks (for any CPU clock) 320 // </e> 321 */ 322 #define FLASH_SETUP 1 323 #define FLASHCFG_Val 0x0000303A 324 325 /* 326 //-------- <<< end of configuration section >>> ------------------------------ 327 */ 328 329 /*---------------------------------------------------------------------------- 330 Check the register settings 331 *----------------------------------------------------------------------------*/ 332 #define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) 333 #define CHECK_RSVD(val, mask) (val & mask) 334 335 /* Clock Configuration -------------------------------------------------------*/ 336 #if (CHECK_RSVD((SCS_Val), ~0x00000030)) 337 #error "SCS: Invalid values of reserved bits!" 338 #endif 339 340 #if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2)) 341 #error "CLKSRCSEL: Value out of range!" 342 #endif 343 344 #if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF)) 345 #error "PLL0CFG: Invalid values of reserved bits!" 346 #endif 347 348 #if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F)) 349 #error "PLL1CFG: Invalid values of reserved bits!" 350 #endif 351 352 #if (CHECK_RANGE(CCLKCFG_Val, 2, 255)) 353 #error "CCLKCFG: CCLKSEL field does not contain value in range from 2 to 255!" 354 #endif 355 356 #if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F)) 357 #error "USBCLKCFG: Invalid values of reserved bits!" 358 #endif 359 360 #if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00)) 361 #error "PCLKSEL0: Invalid values of reserved bits!" 362 #endif 363 364 #if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300)) 365 #error "PCLKSEL1: Invalid values of reserved bits!" 366 #endif 367 368 #if (CHECK_RSVD((PCONP_Val), 0x10100821)) 369 #error "PCONP: Invalid values of reserved bits!" 370 #endif 371 372 #if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF)) 373 #error "CLKOUTCFG: Invalid values of reserved bits!" 374 #endif 375 376 /* Flash Accelerator Configuration -------------------------------------------*/ 377 #if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F)) 378 #error "FLASHCFG: Invalid values of reserved bits!" 379 #endif 380 381 382 /*---------------------------------------------------------------------------- 383 DEFINES 384 *----------------------------------------------------------------------------*/ 385 386 /*---------------------------------------------------------------------------- 387 Define clocks 388 *----------------------------------------------------------------------------*/ 389 #define XTAL (12000000UL) /* Oscillator frequency */ 390 #define OSC_CLK ( XTAL) /* Main oscillator frequency */ 391 #define RTC_CLK ( 32768UL) /* RTC oscillator frequency */ 392 #define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */ 393 394 395 /* F_cco0 = (2 * M * F_in) / N */ 396 #define __M (((PLL0CFG_Val ) & 0x7FFF) + 1) 397 #define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1) 398 #define __FCCO(__F_IN) ((2 * __M * __F_IN) / __N) 399 #define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1) 400 401 /* Determine core clock frequency according to settings */ 402 #if (PLL0_SETUP) 403 #if ((CLKSRCSEL_Val & 0x03) == 1) 404 #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV) 405 #elif ((CLKSRCSEL_Val & 0x03) == 2) 406 #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV) 407 #else 408 #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV) 409 #endif 410 #else 411 #if ((CLKSRCSEL_Val & 0x03) == 1) 412 #define __CORE_CLK (OSC_CLK / __CCLK_DIV) 413 #elif ((CLKSRCSEL_Val & 0x03) == 2) 414 #define __CORE_CLK (RTC_CLK / __CCLK_DIV) 415 #else 416 #define __CORE_CLK (IRC_OSC / __CCLK_DIV) 417 #endif 418 #endif 419 420 /** 421 * @} 422 */ 423 424 425 /** @addtogroup LPC17xx_System_Public_Variables LPC17xx System Public Variables 426 @{ 427 */ 428 /*---------------------------------------------------------------------------- 429 Clock Variable definitions 430 *----------------------------------------------------------------------------*/ 431 uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/ 432 433 /** 434 * @} 435 */ 436 437 438 /** @addtogroup LPC17xx_System_Public_Functions LPC17xx System Public Functions 439 @{ 440 */ 441 442 /*---------------------------------------------------------------------------- 443 Clock functions 444 *----------------------------------------------------------------------------*/ 445 446 447 void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ 448 { 449 /* Determine clock frequency according to clock register values */ 450 if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */ 451 switch (LPC_SC->CLKSRCSEL & 0x03) { 452 case 0: /* Int. RC oscillator => PLL0 */ 453 case 3: /* Reserved, default to Int. RC */ 454 SystemCoreClock = (IRC_OSC * 455 ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / 456 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / 457 ((LPC_SC->CCLKCFG & 0xFF)+ 1)); 458 break; 459 case 1: /* Main oscillator => PLL0 */ 460 SystemCoreClock = (OSC_CLK * 461 ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / 462 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / 463 ((LPC_SC->CCLKCFG & 0xFF)+ 1)); 464 break; 465 case 2: /* RTC oscillator => PLL0 */ 466 SystemCoreClock = (RTC_CLK * 467 ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) / 468 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) / 469 ((LPC_SC->CCLKCFG & 0xFF)+ 1)); 470 break; 471 } 472 } else { 473 switch (LPC_SC->CLKSRCSEL & 0x03) { 474 case 0: /* Int. RC oscillator => PLL0 */ 475 case 3: /* Reserved, default to Int. RC */ 476 SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1); 477 break; 478 case 1: /* Main oscillator => PLL0 */ 479 SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1); 480 break; 481 case 2: /* RTC oscillator => PLL0 */ 482 SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1); 483 break; 484 } 485 } 486 487 } 488 489 /** 490 * Initialize the system 491 * 492 * @param none 493 * @return none 494 * 495 * @brief Setup the microcontroller system. 496 * Initialize the System. 497 */ 498 void SystemInit (void) 499 { 500 const uint32_t PLL0_CONNECT_FLG = (1<<25) | (1<<24); 501 const uint32_t PLL1_CONNECT_FLG = (1<<8) | (1<<9); 502 503 #if (CLOCK_SETUP) /* Clock Setup */ 504 LPC_SC->SCS = SCS_Val; 505 if (LPC_SC->SCS & (1 << 5)) { /* If Main Oscillator is enabled */ 506 while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */ 507 } 508 509 LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */ 510 /* Periphral clock must be selected before PLL0 enabling and connecting 511 * - according errata.lpc1768-16.March.2010 - 512 */ 513 LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */ 514 LPC_SC->PCLKSEL1 = PCLKSEL1_Val; 515 516 #if (PLL0_SETUP) 517 LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */ 518 519 LPC_SC->PLL0CFG = PLL0CFG_Val; /* configure PLL0 */ 520 LPC_SC->PLL0FEED = 0xAA; 521 LPC_SC->PLL0FEED = 0x55; 522 523 LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */ 524 LPC_SC->PLL0FEED = 0xAA; 525 LPC_SC->PLL0FEED = 0x55; 526 while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0 */ 527 528 LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */ 529 LPC_SC->PLL0FEED = 0xAA; 530 LPC_SC->PLL0FEED = 0x55; 531 while ((LPC_SC->PLL0STAT & PLL0_CONNECT_FLG) != PLL0_CONNECT_FLG);/* Wait for PLLC0_STAT & PLLE0_STAT */ 532 #endif 533 534 #if (PLL1_SETUP) 535 LPC_SC->PLL1CFG = PLL1CFG_Val; 536 LPC_SC->PLL1FEED = 0xAA; 537 LPC_SC->PLL1FEED = 0x55; 538 539 LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */ 540 LPC_SC->PLL1FEED = 0xAA; 541 LPC_SC->PLL1FEED = 0x55; 542 while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */ 543 544 LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */ 545 LPC_SC->PLL1FEED = 0xAA; 546 LPC_SC->PLL1FEED = 0x55; 547 while ((LPC_SC->PLL1STAT & PLL1_CONNECT_FLG) != PLL1_CONNECT_FLG);/* Wait for PLLC1_STAT & PLLE1_STAT */ 548 #else 549 LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */ 550 #endif 551 LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */ 552 553 LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */ 554 #endif 555 556 #if (FLASH_SETUP == 1) /* Flash Accelerator Setup */ 557 LPC_SC->FLASHCFG = FLASHCFG_Val; 558 #endif 559 560 #define __RAM_MODE__ 0 561 // Set Vector table offset value 562 #if (__RAM_MODE__==1) 563 SCB->VTOR = 0x10000000 & 0x3FFFFF80; 564 #else 565 SCB->VTOR = 0x00000000 & 0x3FFFFF80; 566 #endif 567 } 568 569 /** 570 * @} 571 */ 572 573 /** 574 * @} 575 */