stm32f407.svd (1834893B)
1 <device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"> 2 <name>STM32F407</name> 3 <version>1.2</version> 4 <description>STM32F407</description> 5 <cpu> 6 <name>CM4</name> 7 <revision>r1p0</revision> 8 <endian>little</endian> 9 <mpuPresent>false</mpuPresent> 10 <fpuPresent>false</fpuPresent> 11 <nvicPrioBits>4</nvicPrioBits> 12 <vendorSystickConfig>false</vendorSystickConfig> 13 </cpu> 14 <addressUnitBits>8</addressUnitBits> 15 <width>32</width> 16 <size>0x20</size> 17 <resetValue>0x0</resetValue> 18 <resetMask>0xFFFFFFFF</resetMask> 19 <peripherals> 20 <peripheral> 21 <name>RNG</name> 22 <description>Random number generator</description> 23 <groupName>RNG</groupName> 24 <baseAddress>0x50060800</baseAddress> 25 <addressBlock> 26 <offset>0x0</offset> 27 <size>0x400</size> 28 <usage>registers</usage> 29 </addressBlock> 30 <interrupt> 31 <name>FPU</name> 32 <description>FPU interrupt</description> 33 <value>81</value> 34 </interrupt> 35 <registers> 36 <register> 37 <name>CR</name> 38 <displayName>CR</displayName> 39 <description>control register</description> 40 <addressOffset>0x0</addressOffset> 41 <size>0x20</size> 42 <access>read-write</access> 43 <resetValue>0x00000000</resetValue> 44 <fields> 45 <field> 46 <name>IE</name> 47 <description>Interrupt enable</description> 48 <bitOffset>3</bitOffset> 49 <bitWidth>1</bitWidth> 50 <enumeratedValues><name>IE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>RNG interrupt is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>RNG interrupt is enabled</description><value>1</value></enumeratedValue></enumeratedValues> 51 </field> 52 <field> 53 <name>RNGEN</name> 54 <description>Random number generator 55 enable</description> 56 <bitOffset>2</bitOffset> 57 <bitWidth>1</bitWidth> 58 <enumeratedValues><name>RNGEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Random number generator is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Random number generator is enabled</description><value>1</value></enumeratedValue></enumeratedValues> 59 </field> 60 </fields> 61 </register> 62 <register> 63 <name>SR</name> 64 <displayName>SR</displayName> 65 <description>status register</description> 66 <addressOffset>0x4</addressOffset> 67 <size>0x20</size> 68 <resetValue>0x00000000</resetValue> 69 <fields> 70 <field> 71 <name>SEIS</name> 72 <description>Seed error interrupt 73 status</description> 74 <bitOffset>6</bitOffset> 75 <bitWidth>1</bitWidth> 76 <access>read-write</access> 77 </field> 78 <field> 79 <name>CEIS</name> 80 <description>Clock error interrupt 81 status</description> 82 <bitOffset>5</bitOffset> 83 <bitWidth>1</bitWidth> 84 <access>read-write</access> 85 </field> 86 <field> 87 <name>SECS</name> 88 <description>Seed error current status</description> 89 <bitOffset>2</bitOffset> 90 <bitWidth>1</bitWidth> 91 <access>read-only</access> 92 </field> 93 <field> 94 <name>CECS</name> 95 <description>Clock error current status</description> 96 <bitOffset>1</bitOffset> 97 <bitWidth>1</bitWidth> 98 <access>read-only</access> 99 </field> 100 <field> 101 <name>DRDY</name> 102 <description>Data ready</description> 103 <bitOffset>0</bitOffset> 104 <bitWidth>1</bitWidth> 105 <access>read-only</access> 106 </field> 107 </fields> 108 </register> 109 <register> 110 <name>DR</name> 111 <displayName>DR</displayName> 112 <description>data register</description> 113 <addressOffset>0x8</addressOffset> 114 <size>0x20</size> 115 <access>read-only</access> 116 <resetValue>0x00000000</resetValue> 117 <fields> 118 <field> 119 <name>RNDATA</name> 120 <description>Random data</description> 121 <bitOffset>0</bitOffset> 122 <bitWidth>32</bitWidth> 123 </field> 124 </fields> 125 </register> 126 </registers> 127 </peripheral> 128 <peripheral> 129 <name>DCMI</name> 130 <description>Digital camera interface</description> 131 <groupName>DCMI</groupName> 132 <baseAddress>0x50050000</baseAddress> 133 <addressBlock> 134 <offset>0x0</offset> 135 <size>0x400</size> 136 <usage>registers</usage> 137 </addressBlock> 138 <interrupt> 139 <name>DCMI</name> 140 <description>DCMI global interrupt</description> 141 <value>78</value> 142 </interrupt> 143 <registers> 144 <register> 145 <name>CR</name> 146 <displayName>CR</displayName> 147 <description>control register 1</description> 148 <addressOffset>0x0</addressOffset> 149 <size>0x20</size> 150 <access>read-write</access> 151 <resetValue>0x0000</resetValue> 152 <fields> 153 <field> 154 <name>ENABLE</name> 155 <description>DCMI enable</description> 156 <bitOffset>14</bitOffset> 157 <bitWidth>1</bitWidth> 158 </field> 159 <field> 160 <name>EDM</name> 161 <description>Extended data mode</description> 162 <bitOffset>10</bitOffset> 163 <bitWidth>2</bitWidth> 164 </field> 165 <field> 166 <name>FCRC</name> 167 <description>Frame capture rate control</description> 168 <bitOffset>8</bitOffset> 169 <bitWidth>2</bitWidth> 170 </field> 171 <field> 172 <name>VSPOL</name> 173 <description>Vertical synchronization 174 polarity</description> 175 <bitOffset>7</bitOffset> 176 <bitWidth>1</bitWidth> 177 </field> 178 <field> 179 <name>HSPOL</name> 180 <description>Horizontal synchronization 181 polarity</description> 182 <bitOffset>6</bitOffset> 183 <bitWidth>1</bitWidth> 184 </field> 185 <field> 186 <name>PCKPOL</name> 187 <description>Pixel clock polarity</description> 188 <bitOffset>5</bitOffset> 189 <bitWidth>1</bitWidth> 190 </field> 191 <field> 192 <name>ESS</name> 193 <description>Embedded synchronization 194 select</description> 195 <bitOffset>4</bitOffset> 196 <bitWidth>1</bitWidth> 197 </field> 198 <field> 199 <name>JPEG</name> 200 <description>JPEG format</description> 201 <bitOffset>3</bitOffset> 202 <bitWidth>1</bitWidth> 203 </field> 204 <field> 205 <name>CROP</name> 206 <description>Crop feature</description> 207 <bitOffset>2</bitOffset> 208 <bitWidth>1</bitWidth> 209 </field> 210 <field> 211 <name>CM</name> 212 <description>Capture mode</description> 213 <bitOffset>1</bitOffset> 214 <bitWidth>1</bitWidth> 215 </field> 216 <field> 217 <name>CAPTURE</name> 218 <description>Capture enable</description> 219 <bitOffset>0</bitOffset> 220 <bitWidth>1</bitWidth> 221 </field> 222 </fields> 223 </register> 224 <register> 225 <name>SR</name> 226 <displayName>SR</displayName> 227 <description>status register</description> 228 <addressOffset>0x4</addressOffset> 229 <size>0x20</size> 230 <access>read-only</access> 231 <resetValue>0x0000</resetValue> 232 <fields> 233 <field> 234 <name>FNE</name> 235 <description>FIFO not empty</description> 236 <bitOffset>2</bitOffset> 237 <bitWidth>1</bitWidth> 238 </field> 239 <field> 240 <name>VSYNC</name> 241 <description>VSYNC</description> 242 <bitOffset>1</bitOffset> 243 <bitWidth>1</bitWidth> 244 </field> 245 <field> 246 <name>HSYNC</name> 247 <description>HSYNC</description> 248 <bitOffset>0</bitOffset> 249 <bitWidth>1</bitWidth> 250 </field> 251 </fields> 252 </register> 253 <register> 254 <name>RIS</name> 255 <displayName>RIS</displayName> 256 <description>raw interrupt status register</description> 257 <addressOffset>0x8</addressOffset> 258 <size>0x20</size> 259 <access>read-only</access> 260 <resetValue>0x0000</resetValue> 261 <fields> 262 <field> 263 <name>LINE_RIS</name> 264 <description>Line raw interrupt status</description> 265 <bitOffset>4</bitOffset> 266 <bitWidth>1</bitWidth> 267 </field> 268 <field> 269 <name>VSYNC_RIS</name> 270 <description>VSYNC raw interrupt status</description> 271 <bitOffset>3</bitOffset> 272 <bitWidth>1</bitWidth> 273 </field> 274 <field> 275 <name>ERR_RIS</name> 276 <description>Synchronization error raw interrupt 277 status</description> 278 <bitOffset>2</bitOffset> 279 <bitWidth>1</bitWidth> 280 </field> 281 <field> 282 <name>OVR_RIS</name> 283 <description>Overrun raw interrupt 284 status</description> 285 <bitOffset>1</bitOffset> 286 <bitWidth>1</bitWidth> 287 </field> 288 <field> 289 <name>FRAME_RIS</name> 290 <description>Capture complete raw interrupt 291 status</description> 292 <bitOffset>0</bitOffset> 293 <bitWidth>1</bitWidth> 294 </field> 295 </fields> 296 </register> 297 <register> 298 <name>IER</name> 299 <displayName>IER</displayName> 300 <description>interrupt enable register</description> 301 <addressOffset>0xC</addressOffset> 302 <size>0x20</size> 303 <access>read-write</access> 304 <resetValue>0x0000</resetValue> 305 <fields> 306 <field> 307 <name>LINE_IE</name> 308 <description>Line interrupt enable</description> 309 <bitOffset>4</bitOffset> 310 <bitWidth>1</bitWidth> 311 </field> 312 <field> 313 <name>VSYNC_IE</name> 314 <description>VSYNC interrupt enable</description> 315 <bitOffset>3</bitOffset> 316 <bitWidth>1</bitWidth> 317 </field> 318 <field> 319 <name>ERR_IE</name> 320 <description>Synchronization error interrupt 321 enable</description> 322 <bitOffset>2</bitOffset> 323 <bitWidth>1</bitWidth> 324 </field> 325 <field> 326 <name>OVR_IE</name> 327 <description>Overrun interrupt enable</description> 328 <bitOffset>1</bitOffset> 329 <bitWidth>1</bitWidth> 330 </field> 331 <field> 332 <name>FRAME_IE</name> 333 <description>Capture complete interrupt 334 enable</description> 335 <bitOffset>0</bitOffset> 336 <bitWidth>1</bitWidth> 337 </field> 338 </fields> 339 </register> 340 <register> 341 <name>MIS</name> 342 <displayName>MIS</displayName> 343 <description>masked interrupt status 344 register</description> 345 <addressOffset>0x10</addressOffset> 346 <size>0x20</size> 347 <access>read-only</access> 348 <resetValue>0x0000</resetValue> 349 <fields> 350 <field> 351 <name>LINE_MIS</name> 352 <description>Line masked interrupt 353 status</description> 354 <bitOffset>4</bitOffset> 355 <bitWidth>1</bitWidth> 356 </field> 357 <field> 358 <name>VSYNC_MIS</name> 359 <description>VSYNC masked interrupt 360 status</description> 361 <bitOffset>3</bitOffset> 362 <bitWidth>1</bitWidth> 363 </field> 364 <field> 365 <name>ERR_MIS</name> 366 <description>Synchronization error masked interrupt 367 status</description> 368 <bitOffset>2</bitOffset> 369 <bitWidth>1</bitWidth> 370 </field> 371 <field> 372 <name>OVR_MIS</name> 373 <description>Overrun masked interrupt 374 status</description> 375 <bitOffset>1</bitOffset> 376 <bitWidth>1</bitWidth> 377 </field> 378 <field> 379 <name>FRAME_MIS</name> 380 <description>Capture complete masked interrupt 381 status</description> 382 <bitOffset>0</bitOffset> 383 <bitWidth>1</bitWidth> 384 </field> 385 </fields> 386 </register> 387 <register> 388 <name>ICR</name> 389 <displayName>ICR</displayName> 390 <description>interrupt clear register</description> 391 <addressOffset>0x14</addressOffset> 392 <size>0x20</size> 393 <access>write-only</access> 394 <resetValue>0x0000</resetValue> 395 <fields> 396 <field> 397 <name>LINE_ISC</name> 398 <description>line interrupt status 399 clear</description> 400 <bitOffset>4</bitOffset> 401 <bitWidth>1</bitWidth> 402 </field> 403 <field> 404 <name>VSYNC_ISC</name> 405 <description>Vertical synch interrupt status 406 clear</description> 407 <bitOffset>3</bitOffset> 408 <bitWidth>1</bitWidth> 409 </field> 410 <field> 411 <name>ERR_ISC</name> 412 <description>Synchronization error interrupt status 413 clear</description> 414 <bitOffset>2</bitOffset> 415 <bitWidth>1</bitWidth> 416 </field> 417 <field> 418 <name>OVR_ISC</name> 419 <description>Overrun interrupt status 420 clear</description> 421 <bitOffset>1</bitOffset> 422 <bitWidth>1</bitWidth> 423 </field> 424 <field> 425 <name>FRAME_ISC</name> 426 <description>Capture complete interrupt status 427 clear</description> 428 <bitOffset>0</bitOffset> 429 <bitWidth>1</bitWidth> 430 </field> 431 </fields> 432 </register> 433 <register> 434 <name>ESCR</name> 435 <displayName>ESCR</displayName> 436 <description>embedded synchronization code 437 register</description> 438 <addressOffset>0x18</addressOffset> 439 <size>0x20</size> 440 <access>read-write</access> 441 <resetValue>0x0000</resetValue> 442 <fields> 443 <field> 444 <name>FEC</name> 445 <description>Frame end delimiter code</description> 446 <bitOffset>24</bitOffset> 447 <bitWidth>8</bitWidth> 448 </field> 449 <field> 450 <name>LEC</name> 451 <description>Line end delimiter code</description> 452 <bitOffset>16</bitOffset> 453 <bitWidth>8</bitWidth> 454 </field> 455 <field> 456 <name>LSC</name> 457 <description>Line start delimiter code</description> 458 <bitOffset>8</bitOffset> 459 <bitWidth>8</bitWidth> 460 </field> 461 <field> 462 <name>FSC</name> 463 <description>Frame start delimiter code</description> 464 <bitOffset>0</bitOffset> 465 <bitWidth>8</bitWidth> 466 </field> 467 </fields> 468 </register> 469 <register> 470 <name>ESUR</name> 471 <displayName>ESUR</displayName> 472 <description>embedded synchronization unmask 473 register</description> 474 <addressOffset>0x1C</addressOffset> 475 <size>0x20</size> 476 <access>read-write</access> 477 <resetValue>0x0000</resetValue> 478 <fields> 479 <field> 480 <name>FEU</name> 481 <description>Frame end delimiter unmask</description> 482 <bitOffset>24</bitOffset> 483 <bitWidth>8</bitWidth> 484 </field> 485 <field> 486 <name>LEU</name> 487 <description>Line end delimiter unmask</description> 488 <bitOffset>16</bitOffset> 489 <bitWidth>8</bitWidth> 490 </field> 491 <field> 492 <name>LSU</name> 493 <description>Line start delimiter 494 unmask</description> 495 <bitOffset>8</bitOffset> 496 <bitWidth>8</bitWidth> 497 </field> 498 <field> 499 <name>FSU</name> 500 <description>Frame start delimiter 501 unmask</description> 502 <bitOffset>0</bitOffset> 503 <bitWidth>8</bitWidth> 504 </field> 505 </fields> 506 </register> 507 <register> 508 <name>CWSTRT</name> 509 <displayName>CWSTRT</displayName> 510 <description>crop window start</description> 511 <addressOffset>0x20</addressOffset> 512 <size>0x20</size> 513 <access>read-write</access> 514 <resetValue>0x0000</resetValue> 515 <fields> 516 <field> 517 <name>VST</name> 518 <description>Vertical start line count</description> 519 <bitOffset>16</bitOffset> 520 <bitWidth>13</bitWidth> 521 </field> 522 <field> 523 <name>HOFFCNT</name> 524 <description>Horizontal offset count</description> 525 <bitOffset>0</bitOffset> 526 <bitWidth>14</bitWidth> 527 </field> 528 </fields> 529 </register> 530 <register> 531 <name>CWSIZE</name> 532 <displayName>CWSIZE</displayName> 533 <description>crop window size</description> 534 <addressOffset>0x24</addressOffset> 535 <size>0x20</size> 536 <access>read-write</access> 537 <resetValue>0x0000</resetValue> 538 <fields> 539 <field> 540 <name>VLINE</name> 541 <description>Vertical line count</description> 542 <bitOffset>16</bitOffset> 543 <bitWidth>14</bitWidth> 544 </field> 545 <field> 546 <name>CAPCNT</name> 547 <description>Capture count</description> 548 <bitOffset>0</bitOffset> 549 <bitWidth>14</bitWidth> 550 </field> 551 </fields> 552 </register> 553 <register> 554 <name>DR</name> 555 <displayName>DR</displayName> 556 <description>data register</description> 557 <addressOffset>0x28</addressOffset> 558 <size>0x20</size> 559 <access>read-only</access> 560 <resetValue>0x0000</resetValue> 561 <fields> 562 <field> 563 <name>Byte3</name> 564 <description>Data byte 3</description> 565 <bitOffset>24</bitOffset> 566 <bitWidth>8</bitWidth> 567 </field> 568 <field> 569 <name>Byte2</name> 570 <description>Data byte 2</description> 571 <bitOffset>16</bitOffset> 572 <bitWidth>8</bitWidth> 573 </field> 574 <field> 575 <name>Byte1</name> 576 <description>Data byte 1</description> 577 <bitOffset>8</bitOffset> 578 <bitWidth>8</bitWidth> 579 </field> 580 <field> 581 <name>Byte0</name> 582 <description>Data byte 0</description> 583 <bitOffset>0</bitOffset> 584 <bitWidth>8</bitWidth> 585 </field> 586 </fields> 587 </register> 588 </registers> 589 </peripheral> 590 <peripheral> 591 <name>FSMC</name> 592 <description>Flexible static memory controller</description> 593 <groupName>FSMC</groupName> 594 <baseAddress>0xA0000000</baseAddress> 595 <addressBlock> 596 <offset>0x0</offset> 597 <size>0x400</size> 598 <usage>registers</usage> 599 </addressBlock> 600 <interrupt> 601 <name>FSMC</name> 602 <description>FSMC global interrupt</description> 603 <value>48</value> 604 </interrupt> 605 <registers> 606 <register> 607 <name>BCR1</name> 608 <displayName>BCR1</displayName> 609 <description>SRAM/NOR-Flash chip-select control register 610 1</description> 611 <addressOffset>0x0</addressOffset> 612 <size>0x20</size> 613 <access>read-write</access> 614 <resetValue>0x000030D0</resetValue> 615 <fields> 616 <field> 617 <name>CBURSTRW</name> 618 <description>CBURSTRW</description> 619 <bitOffset>19</bitOffset> 620 <bitWidth>1</bitWidth> 621 <enumeratedValues><name>CBURSTRW</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>Write operations are performed in synchronous mode</description><value>1</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>Write operations are always performed in asynchronous mode</description><value>0</value></enumeratedValue></enumeratedValues> 622 </field> 623 <field> 624 <name>ASYNCWAIT</name> 625 <description>ASYNCWAIT</description> 626 <bitOffset>15</bitOffset> 627 <bitWidth>1</bitWidth> 628 <enumeratedValues><name>ASYNCWAIT</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Wait signal not used in asynchronous mode</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Wait signal used even in asynchronous mode</description><value>1</value></enumeratedValue></enumeratedValues> 629 </field> 630 <field> 631 <name>EXTMOD</name> 632 <description>EXTMOD</description> 633 <bitOffset>14</bitOffset> 634 <bitWidth>1</bitWidth> 635 <enumeratedValues><name>EXTMOD</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Values inside the FMC_BWTR are not taken into account</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Values inside the FMC_BWTR are taken into account</description><value>1</value></enumeratedValue></enumeratedValues> 636 </field> 637 <field> 638 <name>WAITEN</name> 639 <description>WAITEN</description> 640 <bitOffset>13</bitOffset> 641 <bitWidth>1</bitWidth> 642 <enumeratedValues><name>WAITEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Values inside the FMC_BWTR are taken into account</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>NWAIT signal enabled</description><value>1</value></enumeratedValue></enumeratedValues> 643 </field> 644 <field> 645 <name>WREN</name> 646 <description>WREN</description> 647 <bitOffset>12</bitOffset> 648 <bitWidth>1</bitWidth> 649 <enumeratedValues><name>WREN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Write operations disabled for the bank by the FMC</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Write operations enabled for the bank by the FMC</description><value>1</value></enumeratedValue></enumeratedValues> 650 </field> 651 <field> 652 <name>WAITCFG</name> 653 <description>WAITCFG</description> 654 <bitOffset>11</bitOffset> 655 <bitWidth>1</bitWidth> 656 <enumeratedValues><name>WAITCFG</name><usage>read-write</usage><enumeratedValue><name>BeforeWaitState</name><description>NWAIT signal is active one data cycle before wait state</description><value>0</value></enumeratedValue><enumeratedValue><name>DuringWaitState</name><description>NWAIT signal is active during wait state</description><value>1</value></enumeratedValue></enumeratedValues> 657 </field> 658 <field> 659 <name>WAITPOL</name> 660 <description>WAITPOL</description> 661 <bitOffset>9</bitOffset> 662 <bitWidth>1</bitWidth> 663 <enumeratedValues><name>WAITPOL</name><usage>read-write</usage><enumeratedValue><name>ActiveLow</name><description>NWAIT active low</description><value>0</value></enumeratedValue><enumeratedValue><name>ActiveHigh</name><description>NWAIT active high</description><value>1</value></enumeratedValue></enumeratedValues> 664 </field> 665 <field> 666 <name>BURSTEN</name> 667 <description>BURSTEN</description> 668 <bitOffset>8</bitOffset> 669 <bitWidth>1</bitWidth> 670 <enumeratedValues><name>BURSTEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Burst mode disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Burst mode enabled</description><value>1</value></enumeratedValue></enumeratedValues> 671 </field> 672 <field> 673 <name>FACCEN</name> 674 <description>FACCEN</description> 675 <bitOffset>6</bitOffset> 676 <bitWidth>1</bitWidth> 677 <enumeratedValues><name>FACCEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Corresponding NOR Flash memory access is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Corresponding NOR Flash memory access is enabled</description><value>1</value></enumeratedValue></enumeratedValues> 678 </field> 679 <field> 680 <name>MWID</name> 681 <description>MWID</description> 682 <bitOffset>4</bitOffset> 683 <bitWidth>2</bitWidth> 684 <enumeratedValues><name>MWID</name><usage>read-write</usage><enumeratedValue><name>Bits8</name><description>Memory data bus width 8 bits</description><value>0</value></enumeratedValue><enumeratedValue><name>Bits16</name><description>Memory data bus width 16 bits</description><value>1</value></enumeratedValue><enumeratedValue><name>Bits32</name><description>Memory data bus width 32 bits</description><value>2</value></enumeratedValue></enumeratedValues> 685 </field> 686 <field> 687 <name>MTYP</name> 688 <description>MTYP</description> 689 <bitOffset>2</bitOffset> 690 <bitWidth>2</bitWidth> 691 <enumeratedValues><name>MTYP</name><usage>read-write</usage><enumeratedValue><name>SRAM</name><description>SRAM memory type</description><value>0</value></enumeratedValue><enumeratedValue><name>PSRAM</name><description>PSRAM (CRAM) memory type</description><value>1</value></enumeratedValue><enumeratedValue><name>Flash</name><description>NOR Flash/OneNAND Flash</description><value>2</value></enumeratedValue></enumeratedValues> 692 </field> 693 <field> 694 <name>MUXEN</name> 695 <description>MUXEN</description> 696 <bitOffset>1</bitOffset> 697 <bitWidth>1</bitWidth> 698 <enumeratedValues><name>MUXEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Address/Data non-multiplexed</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Address/Data multiplexed on databus</description><value>1</value></enumeratedValue></enumeratedValues> 699 </field> 700 <field> 701 <name>MBKEN</name> 702 <description>MBKEN</description> 703 <bitOffset>0</bitOffset> 704 <bitWidth>1</bitWidth> 705 <enumeratedValues><name>MBKEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Corresponding memory bank is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Corresponding memory bank is enabled</description><value>1</value></enumeratedValue></enumeratedValues> 706 </field> 707 <field><name>WRAPMOD</name><description>WRAPMOD</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field> 708 <field><name>CPSIZE</name><description>CRAM page size</description><bitOffset>16</bitOffset><bitWidth>3</bitWidth><access>read-write</access><enumeratedValues><name>CPSIZE</name><usage>read-write</usage><enumeratedValue><name>NoBurstSplit</name><description>No burst split when crossing page boundary</description><value>0</value></enumeratedValue><enumeratedValue><name>Bytes128</name><description>128 bytes CRAM page size</description><value>1</value></enumeratedValue><enumeratedValue><name>Bytes256</name><description>256 bytes CRAM page size</description><value>2</value></enumeratedValue><enumeratedValue><name>Bytes512</name><description>512 bytes CRAM page size</description><value>3</value></enumeratedValue><enumeratedValue><name>Bytes1024</name><description>1024 bytes CRAM page size</description><value>4</value></enumeratedValue></enumeratedValues> 709 </field> 710 </fields> 711 </register> 712 <register> 713 <dim>4</dim><dimIncrement>0x8</dimIncrement><dimIndex>1,2,3,4</dimIndex><name>BTR%s</name> 714 <displayName>BTR1</displayName> 715 <description>SRAM/NOR-Flash chip-select timing register 716 1</description> 717 <addressOffset>0x4</addressOffset> 718 <size>0x20</size> 719 <access>read-write</access> 720 <resetValue>0xFFFFFFFF</resetValue> 721 <fields> 722 <field> 723 <name>ACCMOD</name> 724 <description>ACCMOD</description> 725 <bitOffset>28</bitOffset> 726 <bitWidth>2</bitWidth> 727 <enumeratedValues><name>ACCMOD</name><usage>read-write</usage><enumeratedValue><name>A</name><description>Access mode A</description><value>0</value></enumeratedValue><enumeratedValue><name>B</name><description>Access mode B</description><value>1</value></enumeratedValue><enumeratedValue><name>C</name><description>Access mode C</description><value>2</value></enumeratedValue><enumeratedValue><name>D</name><description>Access mode D</description><value>3</value></enumeratedValue></enumeratedValues> 728 </field> 729 <field> 730 <name>DATLAT</name> 731 <description>DATLAT</description> 732 <bitOffset>24</bitOffset> 733 <bitWidth>4</bitWidth> 734 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 735 </field> 736 <field> 737 <name>CLKDIV</name> 738 <description>CLKDIV</description> 739 <bitOffset>20</bitOffset> 740 <bitWidth>4</bitWidth> 741 <writeConstraint><range><minimum>1</minimum><maximum>15</maximum></range></writeConstraint> 742 </field> 743 <field> 744 <name>BUSTURN</name> 745 <description>BUSTURN</description> 746 <bitOffset>16</bitOffset> 747 <bitWidth>4</bitWidth> 748 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 749 </field> 750 <field> 751 <name>DATAST</name> 752 <description>DATAST</description> 753 <bitOffset>8</bitOffset> 754 <bitWidth>8</bitWidth> 755 <writeConstraint><range><minimum>1</minimum><maximum>255</maximum></range></writeConstraint> 756 </field> 757 <field> 758 <name>ADDHLD</name> 759 <description>ADDHLD</description> 760 <bitOffset>4</bitOffset> 761 <bitWidth>4</bitWidth> 762 <writeConstraint><range><minimum>1</minimum><maximum>15</maximum></range></writeConstraint> 763 </field> 764 <field> 765 <name>ADDSET</name> 766 <description>ADDSET</description> 767 <bitOffset>0</bitOffset> 768 <bitWidth>4</bitWidth> 769 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 770 </field> 771 </fields> 772 </register> 773 <register> 774 <dim>3</dim><dimIncrement>0x8</dimIncrement><dimIndex>2,3,4</dimIndex><name>BCR%s</name> 775 <displayName>BCR2</displayName> 776 <description>SRAM/NOR-Flash chip-select control register 777 2</description> 778 <addressOffset>0x8</addressOffset> 779 <size>0x20</size> 780 <access>read-write</access> 781 <resetValue>0x000030D0</resetValue> 782 <fields> 783 <field> 784 <name>CBURSTRW</name> 785 <description>CBURSTRW</description> 786 <bitOffset>19</bitOffset> 787 <bitWidth>1</bitWidth> 788 <enumeratedValues><name>CBURSTRW</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>Write operations are performed in synchronous mode</description><value>1</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>Write operations are always performed in asynchronous mode</description><value>0</value></enumeratedValue></enumeratedValues> 789 </field> 790 <field> 791 <name>ASYNCWAIT</name> 792 <description>ASYNCWAIT</description> 793 <bitOffset>15</bitOffset> 794 <bitWidth>1</bitWidth> 795 <enumeratedValues><name>ASYNCWAIT</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Wait signal not used in asynchronous mode</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Wait signal used even in asynchronous mode</description><value>1</value></enumeratedValue></enumeratedValues> 796 </field> 797 <field> 798 <name>EXTMOD</name> 799 <description>EXTMOD</description> 800 <bitOffset>14</bitOffset> 801 <bitWidth>1</bitWidth> 802 <enumeratedValues><name>EXTMOD</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Values inside the FMC_BWTR are not taken into account</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Values inside the FMC_BWTR are taken into account</description><value>1</value></enumeratedValue></enumeratedValues> 803 </field> 804 <field> 805 <name>WAITEN</name> 806 <description>WAITEN</description> 807 <bitOffset>13</bitOffset> 808 <bitWidth>1</bitWidth> 809 <enumeratedValues><name>WAITEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Values inside the FMC_BWTR are taken into account</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>NWAIT signal enabled</description><value>1</value></enumeratedValue></enumeratedValues> 810 </field> 811 <field> 812 <name>WREN</name> 813 <description>WREN</description> 814 <bitOffset>12</bitOffset> 815 <bitWidth>1</bitWidth> 816 <enumeratedValues><name>WREN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Write operations disabled for the bank by the FMC</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Write operations enabled for the bank by the FMC</description><value>1</value></enumeratedValue></enumeratedValues> 817 </field> 818 <field> 819 <name>WAITCFG</name> 820 <description>WAITCFG</description> 821 <bitOffset>11</bitOffset> 822 <bitWidth>1</bitWidth> 823 <enumeratedValues><name>WAITCFG</name><usage>read-write</usage><enumeratedValue><name>BeforeWaitState</name><description>NWAIT signal is active one data cycle before wait state</description><value>0</value></enumeratedValue><enumeratedValue><name>DuringWaitState</name><description>NWAIT signal is active during wait state</description><value>1</value></enumeratedValue></enumeratedValues> 824 </field> 825 <field> 826 <name>WRAPMOD</name> 827 <description>WRAPMOD</description> 828 <bitOffset>10</bitOffset> 829 <bitWidth>1</bitWidth> 830 </field> 831 <field> 832 <name>WAITPOL</name> 833 <description>WAITPOL</description> 834 <bitOffset>9</bitOffset> 835 <bitWidth>1</bitWidth> 836 <enumeratedValues><name>WAITPOL</name><usage>read-write</usage><enumeratedValue><name>ActiveLow</name><description>NWAIT active low</description><value>0</value></enumeratedValue><enumeratedValue><name>ActiveHigh</name><description>NWAIT active high</description><value>1</value></enumeratedValue></enumeratedValues> 837 </field> 838 <field> 839 <name>BURSTEN</name> 840 <description>BURSTEN</description> 841 <bitOffset>8</bitOffset> 842 <bitWidth>1</bitWidth> 843 <enumeratedValues><name>BURSTEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Burst mode disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Burst mode enabled</description><value>1</value></enumeratedValue></enumeratedValues> 844 </field> 845 <field> 846 <name>FACCEN</name> 847 <description>FACCEN</description> 848 <bitOffset>6</bitOffset> 849 <bitWidth>1</bitWidth> 850 <enumeratedValues><name>FACCEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Corresponding NOR Flash memory access is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Corresponding NOR Flash memory access is enabled</description><value>1</value></enumeratedValue></enumeratedValues> 851 </field> 852 <field> 853 <name>MWID</name> 854 <description>MWID</description> 855 <bitOffset>4</bitOffset> 856 <bitWidth>2</bitWidth> 857 <enumeratedValues><name>MWID</name><usage>read-write</usage><enumeratedValue><name>Bits8</name><description>Memory data bus width 8 bits</description><value>0</value></enumeratedValue><enumeratedValue><name>Bits16</name><description>Memory data bus width 16 bits</description><value>1</value></enumeratedValue><enumeratedValue><name>Bits32</name><description>Memory data bus width 32 bits</description><value>2</value></enumeratedValue></enumeratedValues> 858 </field> 859 <field> 860 <name>MTYP</name> 861 <description>MTYP</description> 862 <bitOffset>2</bitOffset> 863 <bitWidth>2</bitWidth> 864 <enumeratedValues><name>MTYP</name><usage>read-write</usage><enumeratedValue><name>SRAM</name><description>SRAM memory type</description><value>0</value></enumeratedValue><enumeratedValue><name>PSRAM</name><description>PSRAM (CRAM) memory type</description><value>1</value></enumeratedValue><enumeratedValue><name>Flash</name><description>NOR Flash/OneNAND Flash</description><value>2</value></enumeratedValue></enumeratedValues> 865 </field> 866 <field> 867 <name>MUXEN</name> 868 <description>MUXEN</description> 869 <bitOffset>1</bitOffset> 870 <bitWidth>1</bitWidth> 871 <enumeratedValues><name>MUXEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Address/Data non-multiplexed</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Address/Data multiplexed on databus</description><value>1</value></enumeratedValue></enumeratedValues> 872 </field> 873 <field> 874 <name>MBKEN</name> 875 <description>MBKEN</description> 876 <bitOffset>0</bitOffset> 877 <bitWidth>1</bitWidth> 878 <enumeratedValues><name>MBKEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Corresponding memory bank is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Corresponding memory bank is enabled</description><value>1</value></enumeratedValue></enumeratedValues> 879 </field> 880 <field><name>CPSIZE</name><description>CRAM page size</description><bitOffset>16</bitOffset><bitWidth>3</bitWidth><access>read-write</access><enumeratedValues><name>CPSIZE</name><usage>read-write</usage><enumeratedValue><name>NoBurstSplit</name><description>No burst split when crossing page boundary</description><value>0</value></enumeratedValue><enumeratedValue><name>Bytes128</name><description>128 bytes CRAM page size</description><value>1</value></enumeratedValue><enumeratedValue><name>Bytes256</name><description>256 bytes CRAM page size</description><value>2</value></enumeratedValue><enumeratedValue><name>Bytes512</name><description>512 bytes CRAM page size</description><value>3</value></enumeratedValue><enumeratedValue><name>Bytes1024</name><description>1024 bytes CRAM page size</description><value>4</value></enumeratedValue></enumeratedValues> 881 </field> 882 </fields> 883 </register> 884 <register> 885 <dim>3</dim><dimIncrement>0x20</dimIncrement><dimIndex>2,3,4</dimIndex><name>PCR%s</name> 886 <displayName>PCR2</displayName> 887 <description>PC Card/NAND Flash control register 888 2</description> 889 <addressOffset>0x60</addressOffset> 890 <size>0x20</size> 891 <access>read-write</access> 892 <resetValue>0x00000018</resetValue> 893 <fields> 894 <field> 895 <name>ECCPS</name> 896 <description>ECCPS</description> 897 <bitOffset>17</bitOffset> 898 <bitWidth>3</bitWidth> 899 <enumeratedValues><name>ECCPS</name><usage>read-write</usage><enumeratedValue><name>Bytes256</name><description>ECC page size 256 bytes</description><value>0</value></enumeratedValue><enumeratedValue><name>Bytes512</name><description>ECC page size 512 bytes</description><value>1</value></enumeratedValue><enumeratedValue><name>Bytes1024</name><description>ECC page size 1024 bytes</description><value>2</value></enumeratedValue><enumeratedValue><name>Bytes2048</name><description>ECC page size 2048 bytes</description><value>3</value></enumeratedValue><enumeratedValue><name>Bytes4096</name><description>ECC page size 4096 bytes</description><value>4</value></enumeratedValue><enumeratedValue><name>Bytes8192</name><description>ECC page size 8192 bytes</description><value>5</value></enumeratedValue></enumeratedValues> 900 </field> 901 <field> 902 <name>TAR</name> 903 <description>TAR</description> 904 <bitOffset>13</bitOffset> 905 <bitWidth>4</bitWidth> 906 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 907 </field> 908 <field> 909 <name>TCLR</name> 910 <description>TCLR</description> 911 <bitOffset>9</bitOffset> 912 <bitWidth>4</bitWidth> 913 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 914 </field> 915 <field> 916 <name>ECCEN</name> 917 <description>ECCEN</description> 918 <bitOffset>6</bitOffset> 919 <bitWidth>1</bitWidth> 920 <enumeratedValues><name>ECCEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>ECC logic is disabled and reset</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>ECC logic is enabled</description><value>1</value></enumeratedValue></enumeratedValues> 921 </field> 922 <field> 923 <name>PWID</name> 924 <description>PWID</description> 925 <bitOffset>4</bitOffset> 926 <bitWidth>2</bitWidth> 927 <enumeratedValues><name>PWID</name><usage>read-write</usage><enumeratedValue><name>Bits8</name><description>External memory device width 8 bits</description><value>0</value></enumeratedValue><enumeratedValue><name>Bits16</name><description>External memory device width 16 bits</description><value>1</value></enumeratedValue></enumeratedValues> 928 </field> 929 <field> 930 <name>PTYP</name> 931 <description>PTYP</description> 932 <bitOffset>3</bitOffset> 933 <bitWidth>1</bitWidth> 934 <enumeratedValues><name>PTYP</name><usage>read-write</usage><enumeratedValue><name>NANDFlash</name><description>NAND Flash</description><value>1</value></enumeratedValue></enumeratedValues> 935 </field> 936 <field> 937 <name>PBKEN</name> 938 <description>PBKEN</description> 939 <bitOffset>2</bitOffset> 940 <bitWidth>1</bitWidth> 941 <enumeratedValues><name>PBKEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Corresponding memory bank is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Corresponding memory bank is enabled</description><value>1</value></enumeratedValue></enumeratedValues> 942 </field> 943 <field> 944 <name>PWAITEN</name> 945 <description>PWAITEN</description> 946 <bitOffset>1</bitOffset> 947 <bitWidth>1</bitWidth> 948 <enumeratedValues><name>PWAITEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Wait feature disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Wait feature enabled</description><value>1</value></enumeratedValue></enumeratedValues> 949 </field> 950 </fields> 951 </register> 952 <register> 953 <dim>3</dim><dimIncrement>0x20</dimIncrement><dimIndex>2,3,4</dimIndex><name>SR%s</name> 954 <displayName>SR2</displayName> 955 <description>FIFO status and interrupt register 956 2</description> 957 <addressOffset>0x64</addressOffset> 958 <size>0x20</size> 959 <resetValue>0x00000040</resetValue> 960 <fields> 961 <field> 962 <name>FEMPT</name> 963 <description>FEMPT</description> 964 <bitOffset>6</bitOffset> 965 <bitWidth>1</bitWidth> 966 <access>read-only</access> 967 <enumeratedValues><name>FEMPT</name><usage>read-write</usage><enumeratedValue><name>NotEmpty</name><description>FIFO not empty</description><value>0</value></enumeratedValue><enumeratedValue><name>Empty</name><description>FIFO empty</description><value>1</value></enumeratedValue></enumeratedValues> 968 </field> 969 <field> 970 <name>IFEN</name> 971 <description>IFEN</description> 972 <bitOffset>5</bitOffset> 973 <bitWidth>1</bitWidth> 974 <access>read-write</access> 975 <enumeratedValues><name>IFEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Interrupt falling edge detection request disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt falling edge detection request enabled</description><value>1</value></enumeratedValue></enumeratedValues> 976 </field> 977 <field> 978 <name>ILEN</name> 979 <description>ILEN</description> 980 <bitOffset>4</bitOffset> 981 <bitWidth>1</bitWidth> 982 <access>read-write</access> 983 <enumeratedValues><name>ILEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Interrupt high-level detection request disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt high-level detection request enabled</description><value>1</value></enumeratedValue></enumeratedValues> 984 </field> 985 <field> 986 <name>IREN</name> 987 <description>IREN</description> 988 <bitOffset>3</bitOffset> 989 <bitWidth>1</bitWidth> 990 <access>read-write</access> 991 <enumeratedValues><name>IREN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Interrupt rising edge detection request disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt rising edge detection request enabled</description><value>1</value></enumeratedValue></enumeratedValues> 992 </field> 993 <field> 994 <name>IFS</name> 995 <description>IFS</description> 996 <bitOffset>2</bitOffset> 997 <bitWidth>1</bitWidth> 998 <access>read-write</access> 999 <enumeratedValues><name>IFS</name><usage>read-write</usage><enumeratedValue><name>DidNotOccur</name><description>Interrupt falling edge did not occur</description><value>0</value></enumeratedValue><enumeratedValue><name>Occurred</name><description>Interrupt falling edge occurred</description><value>1</value></enumeratedValue></enumeratedValues> 1000 </field> 1001 <field> 1002 <name>ILS</name> 1003 <description>ILS</description> 1004 <bitOffset>1</bitOffset> 1005 <bitWidth>1</bitWidth> 1006 <access>read-write</access> 1007 <enumeratedValues><name>ILS</name><usage>read-write</usage><enumeratedValue><name>DidNotOccur</name><description>Interrupt high-level did not occur</description><value>0</value></enumeratedValue><enumeratedValue><name>Occurred</name><description>Interrupt high-level occurred</description><value>1</value></enumeratedValue></enumeratedValues> 1008 </field> 1009 <field> 1010 <name>IRS</name> 1011 <description>IRS</description> 1012 <bitOffset>0</bitOffset> 1013 <bitWidth>1</bitWidth> 1014 <access>read-write</access> 1015 <enumeratedValues><name>IRS</name><usage>read-write</usage><enumeratedValue><name>DidNotOccur</name><description>Interrupt rising edge did not occur</description><value>0</value></enumeratedValue><enumeratedValue><name>Occurred</name><description>Interrupt rising edge occurred</description><value>1</value></enumeratedValue></enumeratedValues> 1016 </field> 1017 </fields> 1018 </register> 1019 <register> 1020 <name>PMEM2</name> 1021 <displayName>PMEM2</displayName> 1022 <description>Common memory space timing register 1023 2</description> 1024 <addressOffset>0x68</addressOffset> 1025 <size>0x20</size> 1026 <access>read-write</access> 1027 <resetValue>0xFCFCFCFC</resetValue> 1028 <fields> 1029 <field> 1030 <name>MEMHIZ</name> 1031 <description>MEMHIZx</description> 1032 <bitOffset>24</bitOffset> 1033 <bitWidth>8</bitWidth> 1034 <writeConstraint><range><minimum>0</minimum><maximum>254</maximum></range></writeConstraint> 1035 </field> 1036 <field> 1037 <name>MEMHOLD</name> 1038 <description>MEMHOLDx</description> 1039 <bitOffset>16</bitOffset> 1040 <bitWidth>8</bitWidth> 1041 <writeConstraint><range><minimum>1</minimum><maximum>254</maximum></range></writeConstraint> 1042 </field> 1043 <field> 1044 <name>MEMWAIT</name> 1045 <description>MEMWAITx</description> 1046 <bitOffset>8</bitOffset> 1047 <bitWidth>8</bitWidth> 1048 <writeConstraint><range><minimum>1</minimum><maximum>254</maximum></range></writeConstraint> 1049 </field> 1050 <field> 1051 <name>MEMSET</name> 1052 <description>MEMSETx</description> 1053 <bitOffset>0</bitOffset> 1054 <bitWidth>8</bitWidth> 1055 <writeConstraint><range><minimum>0</minimum><maximum>254</maximum></range></writeConstraint> 1056 </field> 1057 </fields> 1058 </register> 1059 <register> 1060 <name>PATT2</name> 1061 <displayName>PATT2</displayName> 1062 <description>Attribute memory space timing register 1063 2</description> 1064 <addressOffset>0x6C</addressOffset> 1065 <size>0x20</size> 1066 <access>read-write</access> 1067 <resetValue>0xFCFCFCFC</resetValue> 1068 <fields> 1069 <field> 1070 <name>ATTHIZ</name> 1071 <description>ATTHIZx</description> 1072 <bitOffset>24</bitOffset> 1073 <bitWidth>8</bitWidth> 1074 <writeConstraint><range><minimum>0</minimum><maximum>254</maximum></range></writeConstraint> 1075 </field> 1076 <field> 1077 <name>ATTHOLD</name> 1078 <description>ATTHOLDx</description> 1079 <bitOffset>16</bitOffset> 1080 <bitWidth>8</bitWidth> 1081 <writeConstraint><range><minimum>1</minimum><maximum>254</maximum></range></writeConstraint> 1082 </field> 1083 <field> 1084 <name>ATTWAIT</name> 1085 <description>ATTWAITx</description> 1086 <bitOffset>8</bitOffset> 1087 <bitWidth>8</bitWidth> 1088 <writeConstraint><range><minimum>1</minimum><maximum>254</maximum></range></writeConstraint> 1089 </field> 1090 <field> 1091 <name>ATTSET</name> 1092 <description>ATTSETx</description> 1093 <bitOffset>0</bitOffset> 1094 <bitWidth>8</bitWidth> 1095 <writeConstraint><range><minimum>0</minimum><maximum>254</maximum></range></writeConstraint> 1096 </field> 1097 </fields> 1098 </register> 1099 <register> 1100 <name>ECCR2</name> 1101 <displayName>ECCR2</displayName> 1102 <description>ECC result register 2</description> 1103 <addressOffset>0x74</addressOffset> 1104 <size>0x20</size> 1105 <access>read-only</access> 1106 <resetValue>0x00000000</resetValue> 1107 <fields> 1108 <field> 1109 <name>ECC</name> 1110 <description>ECCx</description> 1111 <bitOffset>0</bitOffset> 1112 <bitWidth>32</bitWidth> 1113 <writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint> 1114 </field> 1115 </fields> 1116 </register> 1117 <register> 1118 <name>PMEM3</name> 1119 <displayName>PMEM3</displayName> 1120 <description>Common memory space timing register 1121 3</description> 1122 <addressOffset>0x88</addressOffset> 1123 <size>0x20</size> 1124 <access>read-write</access> 1125 <resetValue>0xFCFCFCFC</resetValue> 1126 <fields> 1127 <field> 1128 <name>MEMHIZ</name> 1129 <description>MEMHIZx</description> 1130 <bitOffset>24</bitOffset> 1131 <bitWidth>8</bitWidth> 1132 <writeConstraint><range><minimum>0</minimum><maximum>254</maximum></range></writeConstraint> 1133 </field> 1134 <field> 1135 <name>MEMHOLD</name> 1136 <description>MEMHOLDx</description> 1137 <bitOffset>16</bitOffset> 1138 <bitWidth>8</bitWidth> 1139 <writeConstraint><range><minimum>1</minimum><maximum>254</maximum></range></writeConstraint> 1140 </field> 1141 <field> 1142 <name>MEMWAIT</name> 1143 <description>MEMWAITx</description> 1144 <bitOffset>8</bitOffset> 1145 <bitWidth>8</bitWidth> 1146 <writeConstraint><range><minimum>1</minimum><maximum>254</maximum></range></writeConstraint> 1147 </field> 1148 <field> 1149 <name>MEMSET</name> 1150 <description>MEMSETx</description> 1151 <bitOffset>0</bitOffset> 1152 <bitWidth>8</bitWidth> 1153 <writeConstraint><range><minimum>0</minimum><maximum>254</maximum></range></writeConstraint> 1154 </field> 1155 </fields> 1156 </register> 1157 <register> 1158 <name>PATT3</name> 1159 <displayName>PATT3</displayName> 1160 <description>Attribute memory space timing register 1161 3</description> 1162 <addressOffset>0x8C</addressOffset> 1163 <size>0x20</size> 1164 <access>read-write</access> 1165 <resetValue>0xFCFCFCFC</resetValue> 1166 <fields> 1167 <field> 1168 <name>ATTHIZ</name> 1169 <description>ATTHIZx</description> 1170 <bitOffset>24</bitOffset> 1171 <bitWidth>8</bitWidth> 1172 <writeConstraint><range><minimum>0</minimum><maximum>254</maximum></range></writeConstraint> 1173 </field> 1174 <field> 1175 <name>ATTHOLD</name> 1176 <description>ATTHOLDx</description> 1177 <bitOffset>16</bitOffset> 1178 <bitWidth>8</bitWidth> 1179 <writeConstraint><range><minimum>1</minimum><maximum>254</maximum></range></writeConstraint> 1180 </field> 1181 <field> 1182 <name>ATTWAIT</name> 1183 <description>ATTWAITx</description> 1184 <bitOffset>8</bitOffset> 1185 <bitWidth>8</bitWidth> 1186 <writeConstraint><range><minimum>1</minimum><maximum>254</maximum></range></writeConstraint> 1187 </field> 1188 <field> 1189 <name>ATTSET</name> 1190 <description>ATTSETx</description> 1191 <bitOffset>0</bitOffset> 1192 <bitWidth>8</bitWidth> 1193 <writeConstraint><range><minimum>0</minimum><maximum>254</maximum></range></writeConstraint> 1194 </field> 1195 </fields> 1196 </register> 1197 <register> 1198 <name>ECCR3</name> 1199 <displayName>ECCR3</displayName> 1200 <description>ECC result register 3</description> 1201 <addressOffset>0x94</addressOffset> 1202 <size>0x20</size> 1203 <access>read-only</access> 1204 <resetValue>0x00000000</resetValue> 1205 <fields> 1206 <field> 1207 <name>ECC</name> 1208 <description>ECCx</description> 1209 <bitOffset>0</bitOffset> 1210 <bitWidth>32</bitWidth> 1211 <writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint> 1212 </field> 1213 </fields> 1214 </register> 1215 <register> 1216 <name>PMEM4</name> 1217 <displayName>PMEM4</displayName> 1218 <description>Common memory space timing register 1219 4</description> 1220 <addressOffset>0xA8</addressOffset> 1221 <size>0x20</size> 1222 <access>read-write</access> 1223 <resetValue>0xFCFCFCFC</resetValue> 1224 <fields> 1225 <field> 1226 <name>MEMHIZ</name> 1227 <description>MEMHIZx</description> 1228 <bitOffset>24</bitOffset> 1229 <bitWidth>8</bitWidth> 1230 <writeConstraint><range><minimum>0</minimum><maximum>254</maximum></range></writeConstraint> 1231 </field> 1232 <field> 1233 <name>MEMHOLD</name> 1234 <description>MEMHOLDx</description> 1235 <bitOffset>16</bitOffset> 1236 <bitWidth>8</bitWidth> 1237 <writeConstraint><range><minimum>1</minimum><maximum>254</maximum></range></writeConstraint> 1238 </field> 1239 <field> 1240 <name>MEMWAIT</name> 1241 <description>MEMWAITx</description> 1242 <bitOffset>8</bitOffset> 1243 <bitWidth>8</bitWidth> 1244 <writeConstraint><range><minimum>1</minimum><maximum>254</maximum></range></writeConstraint> 1245 </field> 1246 <field> 1247 <name>MEMSET</name> 1248 <description>MEMSETx</description> 1249 <bitOffset>0</bitOffset> 1250 <bitWidth>8</bitWidth> 1251 <writeConstraint><range><minimum>0</minimum><maximum>254</maximum></range></writeConstraint> 1252 </field> 1253 </fields> 1254 </register> 1255 <register> 1256 <name>PATT4</name> 1257 <displayName>PATT4</displayName> 1258 <description>Attribute memory space timing register 1259 4</description> 1260 <addressOffset>0xAC</addressOffset> 1261 <size>0x20</size> 1262 <access>read-write</access> 1263 <resetValue>0xFCFCFCFC</resetValue> 1264 <fields> 1265 <field> 1266 <name>ATTHIZ</name> 1267 <description>ATTHIZx</description> 1268 <bitOffset>24</bitOffset> 1269 <bitWidth>8</bitWidth> 1270 <writeConstraint><range><minimum>0</minimum><maximum>254</maximum></range></writeConstraint> 1271 </field> 1272 <field> 1273 <name>ATTHOLD</name> 1274 <description>ATTHOLDx</description> 1275 <bitOffset>16</bitOffset> 1276 <bitWidth>8</bitWidth> 1277 <writeConstraint><range><minimum>1</minimum><maximum>254</maximum></range></writeConstraint> 1278 </field> 1279 <field> 1280 <name>ATTWAIT</name> 1281 <description>ATTWAITx</description> 1282 <bitOffset>8</bitOffset> 1283 <bitWidth>8</bitWidth> 1284 <writeConstraint><range><minimum>1</minimum><maximum>254</maximum></range></writeConstraint> 1285 </field> 1286 <field> 1287 <name>ATTSET</name> 1288 <description>ATTSETx</description> 1289 <bitOffset>0</bitOffset> 1290 <bitWidth>8</bitWidth> 1291 <writeConstraint><range><minimum>0</minimum><maximum>254</maximum></range></writeConstraint> 1292 </field> 1293 </fields> 1294 </register> 1295 <register> 1296 <name>PIO4</name> 1297 <displayName>PIO4</displayName> 1298 <description>I/O space timing register 4</description> 1299 <addressOffset>0xB0</addressOffset> 1300 <size>0x20</size> 1301 <access>read-write</access> 1302 <resetValue>0xFCFCFCFC</resetValue> 1303 <fields> 1304 <field> 1305 <name>IOHIZx</name> 1306 <description>IOHIZx</description> 1307 <bitOffset>24</bitOffset> 1308 <bitWidth>8</bitWidth> 1309 </field> 1310 <field> 1311 <name>IOHOLDx</name> 1312 <description>IOHOLDx</description> 1313 <bitOffset>16</bitOffset> 1314 <bitWidth>8</bitWidth> 1315 </field> 1316 <field> 1317 <name>IOWAITx</name> 1318 <description>IOWAITx</description> 1319 <bitOffset>8</bitOffset> 1320 <bitWidth>8</bitWidth> 1321 </field> 1322 <field> 1323 <name>IOSETx</name> 1324 <description>IOSETx</description> 1325 <bitOffset>0</bitOffset> 1326 <bitWidth>8</bitWidth> 1327 </field> 1328 </fields> 1329 </register> 1330 <register> 1331 <dim>4</dim><dimIncrement>0x8</dimIncrement><dimIndex>1,2,3,4</dimIndex><name>BWTR%s</name> 1332 <displayName>BWTR1</displayName> 1333 <description>SRAM/NOR-Flash write timing registers 1334 1</description> 1335 <addressOffset>0x104</addressOffset> 1336 <size>0x20</size> 1337 <access>read-write</access> 1338 <resetValue>0x0FFFFFFF</resetValue> 1339 <fields> 1340 <field> 1341 <name>ACCMOD</name> 1342 <description>ACCMOD</description> 1343 <bitOffset>28</bitOffset> 1344 <bitWidth>2</bitWidth> 1345 <enumeratedValues><name>ACCMOD</name><usage>read-write</usage><enumeratedValue><name>A</name><description>Access mode A</description><value>0</value></enumeratedValue><enumeratedValue><name>B</name><description>Access mode B</description><value>1</value></enumeratedValue><enumeratedValue><name>C</name><description>Access mode C</description><value>2</value></enumeratedValue><enumeratedValue><name>D</name><description>Access mode D</description><value>3</value></enumeratedValue></enumeratedValues> 1346 </field> 1347 <field> 1348 <name>DATLAT</name> 1349 <description>DATLAT</description> 1350 <bitOffset>24</bitOffset> 1351 <bitWidth>4</bitWidth> 1352 </field> 1353 <field> 1354 <name>CLKDIV</name> 1355 <description>CLKDIV</description> 1356 <bitOffset>20</bitOffset> 1357 <bitWidth>4</bitWidth> 1358 </field> 1359 <field> 1360 <name>DATAST</name> 1361 <description>DATAST</description> 1362 <bitOffset>8</bitOffset> 1363 <bitWidth>8</bitWidth> 1364 <writeConstraint><range><minimum>1</minimum><maximum>255</maximum></range></writeConstraint> 1365 </field> 1366 <field> 1367 <name>ADDHLD</name> 1368 <description>ADDHLD</description> 1369 <bitOffset>4</bitOffset> 1370 <bitWidth>4</bitWidth> 1371 <writeConstraint><range><minimum>1</minimum><maximum>15</maximum></range></writeConstraint> 1372 </field> 1373 <field> 1374 <name>ADDSET</name> 1375 <description>ADDSET</description> 1376 <bitOffset>0</bitOffset> 1377 <bitWidth>4</bitWidth> 1378 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 1379 </field> 1380 <field><name>BUSTURN</name><description>Bus turnaround phase duration</description><bitOffset>16</bitOffset><bitWidth>4</bitWidth><access>read-write</access><writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 1381 </field> 1382 </fields> 1383 </register> 1384 </registers> 1385 </peripheral> 1386 <peripheral> 1387 <name>DBGMCU</name> 1388 <description>Debug support</description> 1389 <groupName>DBG</groupName> 1390 <baseAddress>0xE0042000</baseAddress> 1391 <addressBlock> 1392 <offset>0x0</offset> 1393 <size>0x400</size> 1394 <usage>registers</usage> 1395 </addressBlock> 1396 <registers> 1397 <register> 1398 <name>IDCODE</name> 1399 <displayName>IDCODE</displayName> 1400 <description>IDCODE</description> 1401 <addressOffset>0x0</addressOffset> 1402 <size>0x20</size> 1403 <access>read-only</access> 1404 <resetValue>0x10006411</resetValue> 1405 <fields> 1406 <field> 1407 <name>DEV_ID</name> 1408 <description>DEV_ID</description> 1409 <bitOffset>0</bitOffset> 1410 <bitWidth>12</bitWidth> 1411 </field> 1412 <field> 1413 <name>REV_ID</name> 1414 <description>REV_ID</description> 1415 <bitOffset>16</bitOffset> 1416 <bitWidth>16</bitWidth> 1417 </field> 1418 </fields> 1419 </register> 1420 <register> 1421 <name>CR</name> 1422 <displayName>CR</displayName> 1423 <description>Control Register</description> 1424 <addressOffset>0x4</addressOffset> 1425 <size>0x20</size> 1426 <access>read-write</access> 1427 <resetValue>0x00000000</resetValue> 1428 <fields> 1429 <field> 1430 <name>DBG_SLEEP</name> 1431 <description>DBG_SLEEP</description> 1432 <bitOffset>0</bitOffset> 1433 <bitWidth>1</bitWidth> 1434 </field> 1435 <field> 1436 <name>DBG_STOP</name> 1437 <description>DBG_STOP</description> 1438 <bitOffset>1</bitOffset> 1439 <bitWidth>1</bitWidth> 1440 </field> 1441 <field> 1442 <name>DBG_STANDBY</name> 1443 <description>DBG_STANDBY</description> 1444 <bitOffset>2</bitOffset> 1445 <bitWidth>1</bitWidth> 1446 </field> 1447 <field> 1448 <name>TRACE_IOEN</name> 1449 <description>TRACE_IOEN</description> 1450 <bitOffset>5</bitOffset> 1451 <bitWidth>1</bitWidth> 1452 </field> 1453 <field> 1454 <name>TRACE_MODE</name> 1455 <description>TRACE_MODE</description> 1456 <bitOffset>6</bitOffset> 1457 <bitWidth>2</bitWidth> 1458 </field> 1459 <field> 1460 <name>DBG_I2C2_SMBUS_TIMEOUT</name> 1461 <description>DBG_I2C2_SMBUS_TIMEOUT</description> 1462 <bitOffset>16</bitOffset> 1463 <bitWidth>1</bitWidth> 1464 </field> 1465 <field> 1466 <name>DBG_TIM8_STOP</name> 1467 <description>DBG_TIM8_STOP</description> 1468 <bitOffset>17</bitOffset> 1469 <bitWidth>1</bitWidth> 1470 </field> 1471 <field> 1472 <name>DBG_TIM5_STOP</name> 1473 <description>DBG_TIM5_STOP</description> 1474 <bitOffset>18</bitOffset> 1475 <bitWidth>1</bitWidth> 1476 </field> 1477 <field> 1478 <name>DBG_TIM6_STOP</name> 1479 <description>DBG_TIM6_STOP</description> 1480 <bitOffset>19</bitOffset> 1481 <bitWidth>1</bitWidth> 1482 </field> 1483 <field> 1484 <name>DBG_TIM7_STOP</name> 1485 <description>DBG_TIM7_STOP</description> 1486 <bitOffset>20</bitOffset> 1487 <bitWidth>1</bitWidth> 1488 </field> 1489 </fields> 1490 </register> 1491 <register> 1492 <name>APB1_FZ</name> 1493 <displayName>APB1_FZ</displayName> 1494 <description>Debug MCU APB1 Freeze registe</description> 1495 <addressOffset>0x8</addressOffset> 1496 <size>0x20</size> 1497 <access>read-write</access> 1498 <resetValue>0x00000000</resetValue> 1499 <fields> 1500 <field> 1501 <name>DBG_TIM2_STOP</name> 1502 <description>DBG_TIM2_STOP</description> 1503 <bitOffset>0</bitOffset> 1504 <bitWidth>1</bitWidth> 1505 </field> 1506 <field> 1507 <name>DBG_TIM3_STOP</name> 1508 <description>DBG_TIM3 _STOP</description> 1509 <bitOffset>1</bitOffset> 1510 <bitWidth>1</bitWidth> 1511 </field> 1512 <field> 1513 <name>DBG_TIM4_STOP</name> 1514 <description>DBG_TIM4_STOP</description> 1515 <bitOffset>2</bitOffset> 1516 <bitWidth>1</bitWidth> 1517 </field> 1518 <field> 1519 <name>DBG_TIM5_STOP</name> 1520 <description>DBG_TIM5_STOP</description> 1521 <bitOffset>3</bitOffset> 1522 <bitWidth>1</bitWidth> 1523 </field> 1524 <field> 1525 <name>DBG_TIM6_STOP</name> 1526 <description>DBG_TIM6_STOP</description> 1527 <bitOffset>4</bitOffset> 1528 <bitWidth>1</bitWidth> 1529 </field> 1530 <field> 1531 <name>DBG_TIM7_STOP</name> 1532 <description>DBG_TIM7_STOP</description> 1533 <bitOffset>5</bitOffset> 1534 <bitWidth>1</bitWidth> 1535 </field> 1536 <field> 1537 <name>DBG_TIM12_STOP</name> 1538 <description>DBG_TIM12_STOP</description> 1539 <bitOffset>6</bitOffset> 1540 <bitWidth>1</bitWidth> 1541 </field> 1542 <field> 1543 <name>DBG_TIM13_STOP</name> 1544 <description>DBG_TIM13_STOP</description> 1545 <bitOffset>7</bitOffset> 1546 <bitWidth>1</bitWidth> 1547 </field> 1548 <field> 1549 <name>DBG_TIM14_STOP</name> 1550 <description>DBG_TIM14_STOP</description> 1551 <bitOffset>8</bitOffset> 1552 <bitWidth>1</bitWidth> 1553 </field> 1554 <field> 1555 <name>DBG_WWDG_STOP</name> 1556 <description>DBG_WWDG_STOP</description> 1557 <bitOffset>11</bitOffset> 1558 <bitWidth>1</bitWidth> 1559 </field> 1560 <field> 1561 <name>DBG_IWDG_STOP</name> 1562 <description>DBG_IWDEG_STOP</description> 1563 <bitOffset>12</bitOffset> 1564 <bitWidth>1</bitWidth> 1565 </field> 1566 <field> 1567 <name>DBG_J2C1_SMBUS_TIMEOUT</name> 1568 <description>DBG_J2C1_SMBUS_TIMEOUT</description> 1569 <bitOffset>21</bitOffset> 1570 <bitWidth>1</bitWidth> 1571 </field> 1572 <field> 1573 <name>DBG_J2C2_SMBUS_TIMEOUT</name> 1574 <description>DBG_J2C2_SMBUS_TIMEOUT</description> 1575 <bitOffset>22</bitOffset> 1576 <bitWidth>1</bitWidth> 1577 </field> 1578 <field> 1579 <name>DBG_J2C3SMBUS_TIMEOUT</name> 1580 <description>DBG_J2C3SMBUS_TIMEOUT</description> 1581 <bitOffset>23</bitOffset> 1582 <bitWidth>1</bitWidth> 1583 </field> 1584 <field> 1585 <name>DBG_CAN1_STOP</name> 1586 <description>DBG_CAN1_STOP</description> 1587 <bitOffset>25</bitOffset> 1588 <bitWidth>1</bitWidth> 1589 </field> 1590 <field> 1591 <name>DBG_CAN2_STOP</name> 1592 <description>DBG_CAN2_STOP</description> 1593 <bitOffset>26</bitOffset> 1594 <bitWidth>1</bitWidth> 1595 </field> 1596 </fields> 1597 </register> 1598 <register> 1599 <name>APB2_FZ</name> 1600 <displayName>APB2_FZ</displayName> 1601 <description>Debug MCU APB2 Freeze registe</description> 1602 <addressOffset>0xC</addressOffset> 1603 <size>0x20</size> 1604 <access>read-write</access> 1605 <resetValue>0x00000000</resetValue> 1606 <fields> 1607 <field> 1608 <name>DBG_TIM1_STOP</name> 1609 <description>TIM1 counter stopped when core is 1610 halted</description> 1611 <bitOffset>0</bitOffset> 1612 <bitWidth>1</bitWidth> 1613 </field> 1614 <field> 1615 <name>DBG_TIM8_STOP</name> 1616 <description>TIM8 counter stopped when core is 1617 halted</description> 1618 <bitOffset>1</bitOffset> 1619 <bitWidth>1</bitWidth> 1620 </field> 1621 <field> 1622 <name>DBG_TIM9_STOP</name> 1623 <description>TIM9 counter stopped when core is 1624 halted</description> 1625 <bitOffset>16</bitOffset> 1626 <bitWidth>1</bitWidth> 1627 </field> 1628 <field> 1629 <name>DBG_TIM10_STOP</name> 1630 <description>TIM10 counter stopped when core is 1631 halted</description> 1632 <bitOffset>17</bitOffset> 1633 <bitWidth>1</bitWidth> 1634 </field> 1635 <field> 1636 <name>DBG_TIM11_STOP</name> 1637 <description>TIM11 counter stopped when core is 1638 halted</description> 1639 <bitOffset>18</bitOffset> 1640 <bitWidth>1</bitWidth> 1641 </field> 1642 </fields> 1643 </register> 1644 </registers> 1645 </peripheral> 1646 <peripheral> 1647 <name>DMA2</name> 1648 <description>DMA controller</description> 1649 <groupName>DMA</groupName> 1650 <baseAddress>0x40026400</baseAddress> 1651 <addressBlock> 1652 <offset>0x0</offset> 1653 <size>0x400</size> 1654 <usage>registers</usage> 1655 </addressBlock> 1656 <interrupt> 1657 <name>DMA2_Stream0</name> 1658 <description>DMA2 Stream0 global interrupt</description> 1659 <value>56</value> 1660 </interrupt> 1661 <interrupt> 1662 <name>DMA2_Stream1</name> 1663 <description>DMA2 Stream1 global interrupt</description> 1664 <value>57</value> 1665 </interrupt> 1666 <interrupt> 1667 <name>DMA2_Stream2</name> 1668 <description>DMA2 Stream2 global interrupt</description> 1669 <value>58</value> 1670 </interrupt> 1671 <interrupt> 1672 <name>DMA2_Stream3</name> 1673 <description>DMA2 Stream3 global interrupt</description> 1674 <value>59</value> 1675 </interrupt> 1676 <interrupt> 1677 <name>DMA2_Stream4</name> 1678 <description>DMA2 Stream4 global interrupt</description> 1679 <value>60</value> 1680 </interrupt> 1681 <interrupt> 1682 <name>DMA2_Stream5</name> 1683 <description>DMA2 Stream5 global interrupt</description> 1684 <value>68</value> 1685 </interrupt> 1686 <interrupt> 1687 <name>DMA2_Stream6</name> 1688 <description>DMA2 Stream6 global interrupt</description> 1689 <value>69</value> 1690 </interrupt> 1691 <interrupt> 1692 <name>DMA2_Stream7</name> 1693 <description>DMA2 Stream7 global interrupt</description> 1694 <value>70</value> 1695 </interrupt> 1696 <registers> 1697 <cluster><dim>8</dim><dimIncrement>0x18</dimIncrement><dimIndex>0,1,2,3,4,5,6,7</dimIndex><name>ST%s</name><description>Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers</description><addressOffset>0x10</addressOffset><register> 1698 <name>CR</name> 1699 <displayName>S0CR</displayName> 1700 <description>stream x configuration 1701 register</description> 1702 <addressOffset>0x0</addressOffset> 1703 <size>0x20</size> 1704 <access>read-write</access> 1705 <resetValue>0x00000000</resetValue> 1706 <fields> 1707 <field> 1708 <name>CHSEL</name> 1709 <description>Channel selection</description> 1710 <bitOffset>25</bitOffset> 1711 <bitWidth>3</bitWidth> 1712 <writeConstraint><range><minimum>0</minimum><maximum>7</maximum></range></writeConstraint> 1713 </field> 1714 <field> 1715 <name>MBURST</name> 1716 <description>Memory burst transfer 1717 configuration</description> 1718 <bitOffset>23</bitOffset> 1719 <bitWidth>2</bitWidth> 1720 <enumeratedValues derivedFrom="PBURST"/> 1721 </field> 1722 <field> 1723 <name>PBURST</name> 1724 <description>Peripheral burst transfer 1725 configuration</description> 1726 <bitOffset>21</bitOffset> 1727 <bitWidth>2</bitWidth> 1728 <enumeratedValues><name>PBURST</name><usage>read-write</usage><enumeratedValue><name>Single</name><description>Single transfer</description><value>0</value></enumeratedValue><enumeratedValue><name>INCR4</name><description>Incremental burst of 4 beats</description><value>1</value></enumeratedValue><enumeratedValue><name>INCR8</name><description>Incremental burst of 8 beats</description><value>2</value></enumeratedValue><enumeratedValue><name>INCR16</name><description>Incremental burst of 16 beats</description><value>3</value></enumeratedValue></enumeratedValues> 1729 </field> 1730 <field> 1731 <name>CT</name> 1732 <description>Current target (only in double buffer 1733 mode)</description> 1734 <bitOffset>19</bitOffset> 1735 <bitWidth>1</bitWidth> 1736 <enumeratedValues><name>CT</name><usage>read-write</usage><enumeratedValue><name>Memory0</name><description>The current target memory is Memory 0</description><value>0</value></enumeratedValue><enumeratedValue><name>Memory1</name><description>The current target memory is Memory 1</description><value>1</value></enumeratedValue></enumeratedValues> 1737 </field> 1738 <field> 1739 <name>DBM</name> 1740 <description>Double buffer mode</description> 1741 <bitOffset>18</bitOffset> 1742 <bitWidth>1</bitWidth> 1743 <enumeratedValues><name>DBM</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>No buffer switching at the end of transfer</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Memory target switched at the end of the DMA transfer</description><value>1</value></enumeratedValue></enumeratedValues> 1744 </field> 1745 <field> 1746 <name>PL</name> 1747 <description>Priority level</description> 1748 <bitOffset>16</bitOffset> 1749 <bitWidth>2</bitWidth> 1750 <enumeratedValues><name>PL</name><usage>read-write</usage><enumeratedValue><name>Low</name><description>Low</description><value>0</value></enumeratedValue><enumeratedValue><name>Medium</name><description>Medium</description><value>1</value></enumeratedValue><enumeratedValue><name>High</name><description>High</description><value>2</value></enumeratedValue><enumeratedValue><name>VeryHigh</name><description>Very high</description><value>3</value></enumeratedValue></enumeratedValues> 1751 </field> 1752 <field> 1753 <name>PINCOS</name> 1754 <description>Peripheral increment offset 1755 size</description> 1756 <bitOffset>15</bitOffset> 1757 <bitWidth>1</bitWidth> 1758 <enumeratedValues><name>PINCOS</name><usage>read-write</usage><enumeratedValue><name>PSIZE</name><description>The offset size for the peripheral address calculation is linked to the PSIZE</description><value>0</value></enumeratedValue><enumeratedValue><name>Fixed4</name><description>The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)</description><value>1</value></enumeratedValue></enumeratedValues> 1759 </field> 1760 <field> 1761 <name>MSIZE</name> 1762 <description>Memory data size</description> 1763 <bitOffset>13</bitOffset> 1764 <bitWidth>2</bitWidth> 1765 <enumeratedValues derivedFrom="PSIZE"/> 1766 </field> 1767 <field> 1768 <name>PSIZE</name> 1769 <description>Peripheral data size</description> 1770 <bitOffset>11</bitOffset> 1771 <bitWidth>2</bitWidth> 1772 <enumeratedValues><name>PSIZE</name><usage>read-write</usage><enumeratedValue><name>Bits8</name><description>Byte (8-bit)</description><value>0</value></enumeratedValue><enumeratedValue><name>Bits16</name><description>Half-word (16-bit)</description><value>1</value></enumeratedValue><enumeratedValue><name>Bits32</name><description>Word (32-bit)</description><value>2</value></enumeratedValue></enumeratedValues> 1773 </field> 1774 <field> 1775 <name>MINC</name> 1776 <description>Memory increment mode</description> 1777 <bitOffset>10</bitOffset> 1778 <bitWidth>1</bitWidth> 1779 <enumeratedValues derivedFrom="PINC"/> 1780 </field> 1781 <field> 1782 <name>PINC</name> 1783 <description>Peripheral increment mode</description> 1784 <bitOffset>9</bitOffset> 1785 <bitWidth>1</bitWidth> 1786 <enumeratedValues><name>PINC</name><usage>read-write</usage><enumeratedValue><name>Fixed</name><description>Address pointer is fixed</description><value>0</value></enumeratedValue><enumeratedValue><name>Incremented</name><description>Address pointer is incremented after each data transfer</description><value>1</value></enumeratedValue></enumeratedValues> 1787 </field> 1788 <field> 1789 <name>CIRC</name> 1790 <description>Circular mode</description> 1791 <bitOffset>8</bitOffset> 1792 <bitWidth>1</bitWidth> 1793 <enumeratedValues><name>CIRC</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Circular mode disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Circular mode enabled</description><value>1</value></enumeratedValue></enumeratedValues> 1794 </field> 1795 <field> 1796 <name>DIR</name> 1797 <description>Data transfer direction</description> 1798 <bitOffset>6</bitOffset> 1799 <bitWidth>2</bitWidth> 1800 <enumeratedValues><name>DIR</name><usage>read-write</usage><enumeratedValue><name>PeripheralToMemory</name><description>Peripheral-to-memory</description><value>0</value></enumeratedValue><enumeratedValue><name>MemoryToPeripheral</name><description>Memory-to-peripheral</description><value>1</value></enumeratedValue><enumeratedValue><name>MemoryToMemory</name><description>Memory-to-memory</description><value>2</value></enumeratedValue></enumeratedValues> 1801 </field> 1802 <field> 1803 <name>PFCTRL</name> 1804 <description>Peripheral flow controller</description> 1805 <bitOffset>5</bitOffset> 1806 <bitWidth>1</bitWidth> 1807 <enumeratedValues><name>PFCTRL</name><usage>read-write</usage><enumeratedValue><name>DMA</name><description>The DMA is the flow controller</description><value>0</value></enumeratedValue><enumeratedValue><name>Peripheral</name><description>The peripheral is the flow controller</description><value>1</value></enumeratedValue></enumeratedValues> 1808 </field> 1809 <field> 1810 <name>TCIE</name> 1811 <description>Transfer complete interrupt 1812 enable</description> 1813 <bitOffset>4</bitOffset> 1814 <bitWidth>1</bitWidth> 1815 <enumeratedValues><name>TCIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>TC interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>TC interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 1816 </field> 1817 <field> 1818 <name>HTIE</name> 1819 <description>Half transfer interrupt 1820 enable</description> 1821 <bitOffset>3</bitOffset> 1822 <bitWidth>1</bitWidth> 1823 <enumeratedValues><name>HTIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>HT interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>HT interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 1824 </field> 1825 <field> 1826 <name>TEIE</name> 1827 <description>Transfer error interrupt 1828 enable</description> 1829 <bitOffset>2</bitOffset> 1830 <bitWidth>1</bitWidth> 1831 <enumeratedValues><name>TEIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>TE interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>TE interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 1832 </field> 1833 <field> 1834 <name>DMEIE</name> 1835 <description>Direct mode error interrupt 1836 enable</description> 1837 <bitOffset>1</bitOffset> 1838 <bitWidth>1</bitWidth> 1839 <enumeratedValues><name>DMEIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>DME interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>DME interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 1840 </field> 1841 <field> 1842 <name>EN</name> 1843 <description>Stream enable / flag stream ready when 1844 read low</description> 1845 <bitOffset>0</bitOffset> 1846 <bitWidth>1</bitWidth> 1847 <enumeratedValues><name>EN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Stream disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Stream enabled</description><value>1</value></enumeratedValue></enumeratedValues> 1848 </field> 1849 </fields> 1850 </register> 1851 <register> 1852 <name>NDTR</name> 1853 <displayName>S0NDTR</displayName> 1854 <description>stream x number of data 1855 register</description> 1856 <addressOffset>0x4</addressOffset> 1857 <size>0x20</size> 1858 <access>read-write</access> 1859 <resetValue>0x00000000</resetValue> 1860 <fields> 1861 <field> 1862 <name>NDT</name> 1863 <description>Number of data items to 1864 transfer</description> 1865 <bitOffset>0</bitOffset> 1866 <bitWidth>16</bitWidth> 1867 <writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint> 1868 </field> 1869 </fields> 1870 </register> 1871 <register> 1872 <name>PAR</name> 1873 <displayName>S0PAR</displayName> 1874 <description>stream x peripheral address 1875 register</description> 1876 <addressOffset>0x8</addressOffset> 1877 <size>0x20</size> 1878 <access>read-write</access> 1879 <resetValue>0x00000000</resetValue> 1880 <fields> 1881 <field> 1882 <name>PA</name> 1883 <description>Peripheral address</description> 1884 <bitOffset>0</bitOffset> 1885 <bitWidth>32</bitWidth> 1886 </field> 1887 </fields> 1888 </register> 1889 <register> 1890 <name>M0AR</name> 1891 <displayName>S0M0AR</displayName> 1892 <description>stream x memory 0 address 1893 register</description> 1894 <addressOffset>0xc</addressOffset> 1895 <size>0x20</size> 1896 <access>read-write</access> 1897 <resetValue>0x00000000</resetValue> 1898 <fields> 1899 <field> 1900 <name>M0A</name> 1901 <description>Memory 0 address</description> 1902 <bitOffset>0</bitOffset> 1903 <bitWidth>32</bitWidth> 1904 </field> 1905 </fields> 1906 </register> 1907 <register> 1908 <name>M1AR</name> 1909 <displayName>S0M1AR</displayName> 1910 <description>stream x memory 1 address 1911 register</description> 1912 <addressOffset>0x10</addressOffset> 1913 <size>0x20</size> 1914 <access>read-write</access> 1915 <resetValue>0x00000000</resetValue> 1916 <fields> 1917 <field> 1918 <name>M1A</name> 1919 <description>Memory 1 address (used in case of Double 1920 buffer mode)</description> 1921 <bitOffset>0</bitOffset> 1922 <bitWidth>32</bitWidth> 1923 </field> 1924 </fields> 1925 </register> 1926 <register> 1927 <name>FCR</name> 1928 <displayName>S0FCR</displayName> 1929 <description>stream x FIFO control register</description> 1930 <addressOffset>0x14</addressOffset> 1931 <size>0x20</size> 1932 <resetValue>0x00000021</resetValue> 1933 <fields> 1934 <field> 1935 <name>FEIE</name> 1936 <description>FIFO error interrupt 1937 enable</description> 1938 <bitOffset>7</bitOffset> 1939 <bitWidth>1</bitWidth> 1940 <access>read-write</access> 1941 <enumeratedValues><name>FEIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>FE interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>FE interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 1942 </field> 1943 <field> 1944 <name>FS</name> 1945 <description>FIFO status</description> 1946 <bitOffset>3</bitOffset> 1947 <bitWidth>3</bitWidth> 1948 <access>read-only</access> 1949 <enumeratedValues><name>FS</name><usage>read-write</usage><enumeratedValue><name>Quarter1</name><description>0 < fifo_level < 1/4</description><value>0</value></enumeratedValue><enumeratedValue><name>Quarter2</name><description>1/4 <= fifo_level < 1/2</description><value>1</value></enumeratedValue><enumeratedValue><name>Quarter3</name><description>1/2 <= fifo_level < 3/4</description><value>2</value></enumeratedValue><enumeratedValue><name>Quarter4</name><description>3/4 <= fifo_level < full</description><value>3</value></enumeratedValue><enumeratedValue><name>Empty</name><description>FIFO is empty</description><value>4</value></enumeratedValue><enumeratedValue><name>Full</name><description>FIFO is full</description><value>5</value></enumeratedValue></enumeratedValues> 1950 </field> 1951 <field> 1952 <name>DMDIS</name> 1953 <description>Direct mode disable</description> 1954 <bitOffset>2</bitOffset> 1955 <bitWidth>1</bitWidth> 1956 <access>read-write</access> 1957 <enumeratedValues><name>DMDIS</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>Direct mode is enabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>Direct mode is disabled</description><value>1</value></enumeratedValue></enumeratedValues> 1958 </field> 1959 <field> 1960 <name>FTH</name> 1961 <description>FIFO threshold selection</description> 1962 <bitOffset>0</bitOffset> 1963 <bitWidth>2</bitWidth> 1964 <access>read-write</access> 1965 <enumeratedValues><name>FTH</name><usage>read-write</usage><enumeratedValue><name>Quarter</name><description>1/4 full FIFO</description><value>0</value></enumeratedValue><enumeratedValue><name>Half</name><description>1/2 full FIFO</description><value>1</value></enumeratedValue><enumeratedValue><name>ThreeQuarters</name><description>3/4 full FIFO</description><value>2</value></enumeratedValue><enumeratedValue><name>Full</name><description>Full FIFO</description><value>3</value></enumeratedValue></enumeratedValues> 1966 </field> 1967 </fields> 1968 </register> 1969 </cluster><register> 1970 <name>LISR</name> 1971 <displayName>LISR</displayName> 1972 <description>low interrupt status register</description> 1973 <addressOffset>0x0</addressOffset> 1974 <size>0x20</size> 1975 <access>read-only</access> 1976 <resetValue>0x00000000</resetValue> 1977 <fields> 1978 <field> 1979 <name>TCIF3</name> 1980 <description>Stream x transfer complete interrupt 1981 flag (x = 3..0)</description> 1982 <bitOffset>27</bitOffset> 1983 <bitWidth>1</bitWidth> 1984 <enumeratedValues derivedFrom="TCIF0"/> 1985 </field> 1986 <field> 1987 <name>HTIF3</name> 1988 <description>Stream x half transfer interrupt flag 1989 (x=3..0)</description> 1990 <bitOffset>26</bitOffset> 1991 <bitWidth>1</bitWidth> 1992 <enumeratedValues derivedFrom="HTIF0"/> 1993 </field> 1994 <field> 1995 <name>TEIF3</name> 1996 <description>Stream x transfer error interrupt flag 1997 (x=3..0)</description> 1998 <bitOffset>25</bitOffset> 1999 <bitWidth>1</bitWidth> 2000 <enumeratedValues derivedFrom="TEIF0"/> 2001 </field> 2002 <field> 2003 <name>DMEIF3</name> 2004 <description>Stream x direct mode error interrupt 2005 flag (x=3..0)</description> 2006 <bitOffset>24</bitOffset> 2007 <bitWidth>1</bitWidth> 2008 <enumeratedValues derivedFrom="DMEIF0"/> 2009 </field> 2010 <field> 2011 <name>FEIF3</name> 2012 <description>Stream x FIFO error interrupt flag 2013 (x=3..0)</description> 2014 <bitOffset>22</bitOffset> 2015 <bitWidth>1</bitWidth> 2016 <enumeratedValues derivedFrom="FEIF0"/> 2017 </field> 2018 <field> 2019 <name>TCIF2</name> 2020 <description>Stream x transfer complete interrupt 2021 flag (x = 3..0)</description> 2022 <bitOffset>21</bitOffset> 2023 <bitWidth>1</bitWidth> 2024 <enumeratedValues derivedFrom="TCIF0"/> 2025 </field> 2026 <field> 2027 <name>HTIF2</name> 2028 <description>Stream x half transfer interrupt flag 2029 (x=3..0)</description> 2030 <bitOffset>20</bitOffset> 2031 <bitWidth>1</bitWidth> 2032 <enumeratedValues derivedFrom="HTIF0"/> 2033 </field> 2034 <field> 2035 <name>TEIF2</name> 2036 <description>Stream x transfer error interrupt flag 2037 (x=3..0)</description> 2038 <bitOffset>19</bitOffset> 2039 <bitWidth>1</bitWidth> 2040 <enumeratedValues derivedFrom="TEIF0"/> 2041 </field> 2042 <field> 2043 <name>DMEIF2</name> 2044 <description>Stream x direct mode error interrupt 2045 flag (x=3..0)</description> 2046 <bitOffset>18</bitOffset> 2047 <bitWidth>1</bitWidth> 2048 <enumeratedValues derivedFrom="DMEIF0"/> 2049 </field> 2050 <field> 2051 <name>FEIF2</name> 2052 <description>Stream x FIFO error interrupt flag 2053 (x=3..0)</description> 2054 <bitOffset>16</bitOffset> 2055 <bitWidth>1</bitWidth> 2056 <enumeratedValues derivedFrom="FEIF0"/> 2057 </field> 2058 <field> 2059 <name>TCIF1</name> 2060 <description>Stream x transfer complete interrupt 2061 flag (x = 3..0)</description> 2062 <bitOffset>11</bitOffset> 2063 <bitWidth>1</bitWidth> 2064 <enumeratedValues derivedFrom="TCIF0"/> 2065 </field> 2066 <field> 2067 <name>HTIF1</name> 2068 <description>Stream x half transfer interrupt flag 2069 (x=3..0)</description> 2070 <bitOffset>10</bitOffset> 2071 <bitWidth>1</bitWidth> 2072 <enumeratedValues derivedFrom="HTIF0"/> 2073 </field> 2074 <field> 2075 <name>TEIF1</name> 2076 <description>Stream x transfer error interrupt flag 2077 (x=3..0)</description> 2078 <bitOffset>9</bitOffset> 2079 <bitWidth>1</bitWidth> 2080 <enumeratedValues derivedFrom="TEIF0"/> 2081 </field> 2082 <field> 2083 <name>DMEIF1</name> 2084 <description>Stream x direct mode error interrupt 2085 flag (x=3..0)</description> 2086 <bitOffset>8</bitOffset> 2087 <bitWidth>1</bitWidth> 2088 <enumeratedValues derivedFrom="DMEIF0"/> 2089 </field> 2090 <field> 2091 <name>FEIF1</name> 2092 <description>Stream x FIFO error interrupt flag 2093 (x=3..0)</description> 2094 <bitOffset>6</bitOffset> 2095 <bitWidth>1</bitWidth> 2096 <enumeratedValues derivedFrom="FEIF0"/> 2097 </field> 2098 <field> 2099 <name>TCIF0</name> 2100 <description>Stream x transfer complete interrupt 2101 flag (x = 3..0)</description> 2102 <bitOffset>5</bitOffset> 2103 <bitWidth>1</bitWidth> 2104 <enumeratedValues><name>TCIF0</name><usage>read-write</usage><enumeratedValue><name>NotComplete</name><description>No transfer complete event on stream x</description><value>0</value></enumeratedValue><enumeratedValue><name>Complete</name><description>A transfer complete event occurred on stream x</description><value>1</value></enumeratedValue></enumeratedValues> 2105 </field> 2106 <field> 2107 <name>HTIF0</name> 2108 <description>Stream x half transfer interrupt flag 2109 (x=3..0)</description> 2110 <bitOffset>4</bitOffset> 2111 <bitWidth>1</bitWidth> 2112 <enumeratedValues><name>HTIF0</name><usage>read-write</usage><enumeratedValue><name>NotHalf</name><description>No half transfer event on stream x</description><value>0</value></enumeratedValue><enumeratedValue><name>Half</name><description>A half transfer event occurred on stream x</description><value>1</value></enumeratedValue></enumeratedValues> 2113 </field> 2114 <field> 2115 <name>TEIF0</name> 2116 <description>Stream x transfer error interrupt flag 2117 (x=3..0)</description> 2118 <bitOffset>3</bitOffset> 2119 <bitWidth>1</bitWidth> 2120 <enumeratedValues><name>TEIF0</name><usage>read-write</usage><enumeratedValue><name>NoError</name><description>No transfer error on stream x</description><value>0</value></enumeratedValue><enumeratedValue><name>Error</name><description>A transfer error occurred on stream x</description><value>1</value></enumeratedValue></enumeratedValues> 2121 </field> 2122 <field> 2123 <name>DMEIF0</name> 2124 <description>Stream x direct mode error interrupt 2125 flag (x=3..0)</description> 2126 <bitOffset>2</bitOffset> 2127 <bitWidth>1</bitWidth> 2128 <enumeratedValues><name>DMEIF0</name><usage>read-write</usage><enumeratedValue><name>NoError</name><description>No Direct Mode error on stream x</description><value>0</value></enumeratedValue><enumeratedValue><name>Error</name><description>A Direct Mode error occurred on stream x</description><value>1</value></enumeratedValue></enumeratedValues> 2129 </field> 2130 <field> 2131 <name>FEIF0</name> 2132 <description>Stream x FIFO error interrupt flag 2133 (x=3..0)</description> 2134 <bitOffset>0</bitOffset> 2135 <bitWidth>1</bitWidth> 2136 <enumeratedValues><name>FEIF0</name><usage>read-write</usage><enumeratedValue><name>NoError</name><description>No FIFO error event on stream x</description><value>0</value></enumeratedValue><enumeratedValue><name>Error</name><description>A FIFO error event occurred on stream x</description><value>1</value></enumeratedValue></enumeratedValues> 2137 </field> 2138 </fields> 2139 </register> 2140 <register> 2141 <name>HISR</name> 2142 <displayName>HISR</displayName> 2143 <description>high interrupt status register</description> 2144 <addressOffset>0x4</addressOffset> 2145 <size>0x20</size> 2146 <access>read-only</access> 2147 <resetValue>0x00000000</resetValue> 2148 <fields> 2149 <field> 2150 <name>TCIF7</name> 2151 <description>Stream x transfer complete interrupt 2152 flag (x=7..4)</description> 2153 <bitOffset>27</bitOffset> 2154 <bitWidth>1</bitWidth> 2155 <enumeratedValues derivedFrom="TCIF4"/> 2156 </field> 2157 <field> 2158 <name>HTIF7</name> 2159 <description>Stream x half transfer interrupt flag 2160 (x=7..4)</description> 2161 <bitOffset>26</bitOffset> 2162 <bitWidth>1</bitWidth> 2163 <enumeratedValues derivedFrom="HTIF4"/> 2164 </field> 2165 <field> 2166 <name>TEIF7</name> 2167 <description>Stream x transfer error interrupt flag 2168 (x=7..4)</description> 2169 <bitOffset>25</bitOffset> 2170 <bitWidth>1</bitWidth> 2171 <enumeratedValues derivedFrom="TEIF4"/> 2172 </field> 2173 <field> 2174 <name>DMEIF7</name> 2175 <description>Stream x direct mode error interrupt 2176 flag (x=7..4)</description> 2177 <bitOffset>24</bitOffset> 2178 <bitWidth>1</bitWidth> 2179 <enumeratedValues derivedFrom="DMEIF4"/> 2180 </field> 2181 <field> 2182 <name>FEIF7</name> 2183 <description>Stream x FIFO error interrupt flag 2184 (x=7..4)</description> 2185 <bitOffset>22</bitOffset> 2186 <bitWidth>1</bitWidth> 2187 <enumeratedValues derivedFrom="FEIF4"/> 2188 </field> 2189 <field> 2190 <name>TCIF6</name> 2191 <description>Stream x transfer complete interrupt 2192 flag (x=7..4)</description> 2193 <bitOffset>21</bitOffset> 2194 <bitWidth>1</bitWidth> 2195 <enumeratedValues derivedFrom="TCIF4"/> 2196 </field> 2197 <field> 2198 <name>HTIF6</name> 2199 <description>Stream x half transfer interrupt flag 2200 (x=7..4)</description> 2201 <bitOffset>20</bitOffset> 2202 <bitWidth>1</bitWidth> 2203 <enumeratedValues derivedFrom="HTIF4"/> 2204 </field> 2205 <field> 2206 <name>TEIF6</name> 2207 <description>Stream x transfer error interrupt flag 2208 (x=7..4)</description> 2209 <bitOffset>19</bitOffset> 2210 <bitWidth>1</bitWidth> 2211 <enumeratedValues derivedFrom="TEIF4"/> 2212 </field> 2213 <field> 2214 <name>DMEIF6</name> 2215 <description>Stream x direct mode error interrupt 2216 flag (x=7..4)</description> 2217 <bitOffset>18</bitOffset> 2218 <bitWidth>1</bitWidth> 2219 <enumeratedValues derivedFrom="DMEIF4"/> 2220 </field> 2221 <field> 2222 <name>FEIF6</name> 2223 <description>Stream x FIFO error interrupt flag 2224 (x=7..4)</description> 2225 <bitOffset>16</bitOffset> 2226 <bitWidth>1</bitWidth> 2227 <enumeratedValues derivedFrom="FEIF4"/> 2228 </field> 2229 <field> 2230 <name>TCIF5</name> 2231 <description>Stream x transfer complete interrupt 2232 flag (x=7..4)</description> 2233 <bitOffset>11</bitOffset> 2234 <bitWidth>1</bitWidth> 2235 <enumeratedValues derivedFrom="TCIF4"/> 2236 </field> 2237 <field> 2238 <name>HTIF5</name> 2239 <description>Stream x half transfer interrupt flag 2240 (x=7..4)</description> 2241 <bitOffset>10</bitOffset> 2242 <bitWidth>1</bitWidth> 2243 <enumeratedValues derivedFrom="HTIF4"/> 2244 </field> 2245 <field> 2246 <name>TEIF5</name> 2247 <description>Stream x transfer error interrupt flag 2248 (x=7..4)</description> 2249 <bitOffset>9</bitOffset> 2250 <bitWidth>1</bitWidth> 2251 <enumeratedValues derivedFrom="TEIF4"/> 2252 </field> 2253 <field> 2254 <name>DMEIF5</name> 2255 <description>Stream x direct mode error interrupt 2256 flag (x=7..4)</description> 2257 <bitOffset>8</bitOffset> 2258 <bitWidth>1</bitWidth> 2259 <enumeratedValues derivedFrom="DMEIF4"/> 2260 </field> 2261 <field> 2262 <name>FEIF5</name> 2263 <description>Stream x FIFO error interrupt flag 2264 (x=7..4)</description> 2265 <bitOffset>6</bitOffset> 2266 <bitWidth>1</bitWidth> 2267 <enumeratedValues derivedFrom="FEIF4"/> 2268 </field> 2269 <field> 2270 <name>TCIF4</name> 2271 <description>Stream x transfer complete interrupt 2272 flag (x=7..4)</description> 2273 <bitOffset>5</bitOffset> 2274 <bitWidth>1</bitWidth> 2275 <enumeratedValues><name>TCIF4</name><usage>read-write</usage><enumeratedValue><name>NotComplete</name><description>No transfer complete event on stream x</description><value>0</value></enumeratedValue><enumeratedValue><name>Complete</name><description>A transfer complete event occurred on stream x</description><value>1</value></enumeratedValue></enumeratedValues> 2276 </field> 2277 <field> 2278 <name>HTIF4</name> 2279 <description>Stream x half transfer interrupt flag 2280 (x=7..4)</description> 2281 <bitOffset>4</bitOffset> 2282 <bitWidth>1</bitWidth> 2283 <enumeratedValues><name>HTIF4</name><usage>read-write</usage><enumeratedValue><name>NotHalf</name><description>No half transfer event on stream x</description><value>0</value></enumeratedValue><enumeratedValue><name>Half</name><description>A half transfer event occurred on stream x</description><value>1</value></enumeratedValue></enumeratedValues> 2284 </field> 2285 <field> 2286 <name>TEIF4</name> 2287 <description>Stream x transfer error interrupt flag 2288 (x=7..4)</description> 2289 <bitOffset>3</bitOffset> 2290 <bitWidth>1</bitWidth> 2291 <enumeratedValues><name>TEIF4</name><usage>read-write</usage><enumeratedValue><name>NoError</name><description>No transfer error on stream x</description><value>0</value></enumeratedValue><enumeratedValue><name>Error</name><description>A transfer error occurred on stream x</description><value>1</value></enumeratedValue></enumeratedValues> 2292 </field> 2293 <field> 2294 <name>DMEIF4</name> 2295 <description>Stream x direct mode error interrupt 2296 flag (x=7..4)</description> 2297 <bitOffset>2</bitOffset> 2298 <bitWidth>1</bitWidth> 2299 <enumeratedValues><name>DMEIF4</name><usage>read-write</usage><enumeratedValue><name>NoError</name><description>No Direct Mode error on stream x</description><value>0</value></enumeratedValue><enumeratedValue><name>Error</name><description>A Direct Mode error occurred on stream x</description><value>1</value></enumeratedValue></enumeratedValues> 2300 </field> 2301 <field> 2302 <name>FEIF4</name> 2303 <description>Stream x FIFO error interrupt flag 2304 (x=7..4)</description> 2305 <bitOffset>0</bitOffset> 2306 <bitWidth>1</bitWidth> 2307 <enumeratedValues><name>FEIF4</name><usage>read-write</usage><enumeratedValue><name>NoError</name><description>No FIFO error event on stream x</description><value>0</value></enumeratedValue><enumeratedValue><name>Error</name><description>A FIFO error event occurred on stream x</description><value>1</value></enumeratedValue></enumeratedValues> 2308 </field> 2309 </fields> 2310 </register> 2311 <register> 2312 <name>LIFCR</name> 2313 <displayName>LIFCR</displayName> 2314 <description>low interrupt flag clear 2315 register</description> 2316 <addressOffset>0x8</addressOffset> 2317 <size>0x20</size> 2318 <access>write-only</access> 2319 <resetValue>0x00000000</resetValue> 2320 <fields> 2321 <field> 2322 <name>CTCIF3</name> 2323 <description>Stream x clear transfer complete 2324 interrupt flag (x = 3..0)</description> 2325 <bitOffset>27</bitOffset> 2326 <bitWidth>1</bitWidth> 2327 <enumeratedValues derivedFrom="CTCIF0"/> 2328 </field> 2329 <field> 2330 <name>CHTIF3</name> 2331 <description>Stream x clear half transfer interrupt 2332 flag (x = 3..0)</description> 2333 <bitOffset>26</bitOffset> 2334 <bitWidth>1</bitWidth> 2335 <enumeratedValues derivedFrom="CHTIF0"/> 2336 </field> 2337 <field> 2338 <name>CTEIF3</name> 2339 <description>Stream x clear transfer error interrupt 2340 flag (x = 3..0)</description> 2341 <bitOffset>25</bitOffset> 2342 <bitWidth>1</bitWidth> 2343 <enumeratedValues derivedFrom="CTEIF0"/> 2344 </field> 2345 <field> 2346 <name>CDMEIF3</name> 2347 <description>Stream x clear direct mode error 2348 interrupt flag (x = 3..0)</description> 2349 <bitOffset>24</bitOffset> 2350 <bitWidth>1</bitWidth> 2351 <enumeratedValues derivedFrom="CDMEIF0"/> 2352 </field> 2353 <field> 2354 <name>CFEIF3</name> 2355 <description>Stream x clear FIFO error interrupt flag 2356 (x = 3..0)</description> 2357 <bitOffset>22</bitOffset> 2358 <bitWidth>1</bitWidth> 2359 <enumeratedValues derivedFrom="CFEIF0"/> 2360 </field> 2361 <field> 2362 <name>CTCIF2</name> 2363 <description>Stream x clear transfer complete 2364 interrupt flag (x = 3..0)</description> 2365 <bitOffset>21</bitOffset> 2366 <bitWidth>1</bitWidth> 2367 <enumeratedValues derivedFrom="CTCIF0"/> 2368 </field> 2369 <field> 2370 <name>CHTIF2</name> 2371 <description>Stream x clear half transfer interrupt 2372 flag (x = 3..0)</description> 2373 <bitOffset>20</bitOffset> 2374 <bitWidth>1</bitWidth> 2375 <enumeratedValues derivedFrom="CHTIF0"/> 2376 </field> 2377 <field> 2378 <name>CTEIF2</name> 2379 <description>Stream x clear transfer error interrupt 2380 flag (x = 3..0)</description> 2381 <bitOffset>19</bitOffset> 2382 <bitWidth>1</bitWidth> 2383 <enumeratedValues derivedFrom="CTEIF0"/> 2384 </field> 2385 <field> 2386 <name>CDMEIF2</name> 2387 <description>Stream x clear direct mode error 2388 interrupt flag (x = 3..0)</description> 2389 <bitOffset>18</bitOffset> 2390 <bitWidth>1</bitWidth> 2391 <enumeratedValues derivedFrom="CDMEIF0"/> 2392 </field> 2393 <field> 2394 <name>CFEIF2</name> 2395 <description>Stream x clear FIFO error interrupt flag 2396 (x = 3..0)</description> 2397 <bitOffset>16</bitOffset> 2398 <bitWidth>1</bitWidth> 2399 <enumeratedValues derivedFrom="CFEIF0"/> 2400 </field> 2401 <field> 2402 <name>CTCIF1</name> 2403 <description>Stream x clear transfer complete 2404 interrupt flag (x = 3..0)</description> 2405 <bitOffset>11</bitOffset> 2406 <bitWidth>1</bitWidth> 2407 <enumeratedValues derivedFrom="CTCIF0"/> 2408 </field> 2409 <field> 2410 <name>CHTIF1</name> 2411 <description>Stream x clear half transfer interrupt 2412 flag (x = 3..0)</description> 2413 <bitOffset>10</bitOffset> 2414 <bitWidth>1</bitWidth> 2415 <enumeratedValues derivedFrom="CHTIF0"/> 2416 </field> 2417 <field> 2418 <name>CTEIF1</name> 2419 <description>Stream x clear transfer error interrupt 2420 flag (x = 3..0)</description> 2421 <bitOffset>9</bitOffset> 2422 <bitWidth>1</bitWidth> 2423 <enumeratedValues derivedFrom="CTEIF0"/> 2424 </field> 2425 <field> 2426 <name>CDMEIF1</name> 2427 <description>Stream x clear direct mode error 2428 interrupt flag (x = 3..0)</description> 2429 <bitOffset>8</bitOffset> 2430 <bitWidth>1</bitWidth> 2431 <enumeratedValues derivedFrom="CDMEIF0"/> 2432 </field> 2433 <field> 2434 <name>CFEIF1</name> 2435 <description>Stream x clear FIFO error interrupt flag 2436 (x = 3..0)</description> 2437 <bitOffset>6</bitOffset> 2438 <bitWidth>1</bitWidth> 2439 <enumeratedValues derivedFrom="CFEIF0"/> 2440 </field> 2441 <field> 2442 <name>CTCIF0</name> 2443 <description>Stream x clear transfer complete 2444 interrupt flag (x = 3..0)</description> 2445 <bitOffset>5</bitOffset> 2446 <bitWidth>1</bitWidth> 2447 <enumeratedValues><name>CTCIF0</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>Clear the corresponding TCIFx flag</description><value>1</value></enumeratedValue></enumeratedValues> 2448 </field> 2449 <field> 2450 <name>CHTIF0</name> 2451 <description>Stream x clear half transfer interrupt 2452 flag (x = 3..0)</description> 2453 <bitOffset>4</bitOffset> 2454 <bitWidth>1</bitWidth> 2455 <enumeratedValues><name>CHTIF0</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>Clear the corresponding HTIFx flag</description><value>1</value></enumeratedValue></enumeratedValues> 2456 </field> 2457 <field> 2458 <name>CTEIF0</name> 2459 <description>Stream x clear transfer error interrupt 2460 flag (x = 3..0)</description> 2461 <bitOffset>3</bitOffset> 2462 <bitWidth>1</bitWidth> 2463 <enumeratedValues><name>CTEIF0</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>Clear the corresponding TEIFx flag</description><value>1</value></enumeratedValue></enumeratedValues> 2464 </field> 2465 <field> 2466 <name>CDMEIF0</name> 2467 <description>Stream x clear direct mode error 2468 interrupt flag (x = 3..0)</description> 2469 <bitOffset>2</bitOffset> 2470 <bitWidth>1</bitWidth> 2471 <enumeratedValues><name>CDMEIF0</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>Clear the corresponding DMEIFx flag</description><value>1</value></enumeratedValue></enumeratedValues> 2472 </field> 2473 <field> 2474 <name>CFEIF0</name> 2475 <description>Stream x clear FIFO error interrupt flag 2476 (x = 3..0)</description> 2477 <bitOffset>0</bitOffset> 2478 <bitWidth>1</bitWidth> 2479 <enumeratedValues><name>CFEIF0</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>Clear the corresponding CFEIFx flag</description><value>1</value></enumeratedValue></enumeratedValues> 2480 </field> 2481 </fields> 2482 </register> 2483 <register> 2484 <name>HIFCR</name> 2485 <displayName>HIFCR</displayName> 2486 <description>high interrupt flag clear 2487 register</description> 2488 <addressOffset>0xC</addressOffset> 2489 <size>0x20</size> 2490 <access>write-only</access> 2491 <resetValue>0x00000000</resetValue> 2492 <fields> 2493 <field> 2494 <name>CTCIF7</name> 2495 <description>Stream x clear transfer complete 2496 interrupt flag (x = 7..4)</description> 2497 <bitOffset>27</bitOffset> 2498 <bitWidth>1</bitWidth> 2499 <enumeratedValues derivedFrom="CTCIF4"/> 2500 </field> 2501 <field> 2502 <name>CHTIF7</name> 2503 <description>Stream x clear half transfer interrupt 2504 flag (x = 7..4)</description> 2505 <bitOffset>26</bitOffset> 2506 <bitWidth>1</bitWidth> 2507 <enumeratedValues derivedFrom="CHTIF4"/> 2508 </field> 2509 <field> 2510 <name>CTEIF7</name> 2511 <description>Stream x clear transfer error interrupt 2512 flag (x = 7..4)</description> 2513 <bitOffset>25</bitOffset> 2514 <bitWidth>1</bitWidth> 2515 <enumeratedValues derivedFrom="CTEIF4"/> 2516 </field> 2517 <field> 2518 <name>CDMEIF7</name> 2519 <description>Stream x clear direct mode error 2520 interrupt flag (x = 7..4)</description> 2521 <bitOffset>24</bitOffset> 2522 <bitWidth>1</bitWidth> 2523 <enumeratedValues derivedFrom="CDMEIF4"/> 2524 </field> 2525 <field> 2526 <name>CFEIF7</name> 2527 <description>Stream x clear FIFO error interrupt flag 2528 (x = 7..4)</description> 2529 <bitOffset>22</bitOffset> 2530 <bitWidth>1</bitWidth> 2531 <enumeratedValues derivedFrom="CFEIF4"/> 2532 </field> 2533 <field> 2534 <name>CTCIF6</name> 2535 <description>Stream x clear transfer complete 2536 interrupt flag (x = 7..4)</description> 2537 <bitOffset>21</bitOffset> 2538 <bitWidth>1</bitWidth> 2539 <enumeratedValues derivedFrom="CTCIF4"/> 2540 </field> 2541 <field> 2542 <name>CHTIF6</name> 2543 <description>Stream x clear half transfer interrupt 2544 flag (x = 7..4)</description> 2545 <bitOffset>20</bitOffset> 2546 <bitWidth>1</bitWidth> 2547 <enumeratedValues derivedFrom="CHTIF4"/> 2548 </field> 2549 <field> 2550 <name>CTEIF6</name> 2551 <description>Stream x clear transfer error interrupt 2552 flag (x = 7..4)</description> 2553 <bitOffset>19</bitOffset> 2554 <bitWidth>1</bitWidth> 2555 <enumeratedValues derivedFrom="CTEIF4"/> 2556 </field> 2557 <field> 2558 <name>CDMEIF6</name> 2559 <description>Stream x clear direct mode error 2560 interrupt flag (x = 7..4)</description> 2561 <bitOffset>18</bitOffset> 2562 <bitWidth>1</bitWidth> 2563 <enumeratedValues derivedFrom="CDMEIF4"/> 2564 </field> 2565 <field> 2566 <name>CFEIF6</name> 2567 <description>Stream x clear FIFO error interrupt flag 2568 (x = 7..4)</description> 2569 <bitOffset>16</bitOffset> 2570 <bitWidth>1</bitWidth> 2571 <enumeratedValues derivedFrom="CFEIF4"/> 2572 </field> 2573 <field> 2574 <name>CTCIF5</name> 2575 <description>Stream x clear transfer complete 2576 interrupt flag (x = 7..4)</description> 2577 <bitOffset>11</bitOffset> 2578 <bitWidth>1</bitWidth> 2579 <enumeratedValues derivedFrom="CTCIF4"/> 2580 </field> 2581 <field> 2582 <name>CHTIF5</name> 2583 <description>Stream x clear half transfer interrupt 2584 flag (x = 7..4)</description> 2585 <bitOffset>10</bitOffset> 2586 <bitWidth>1</bitWidth> 2587 <enumeratedValues derivedFrom="CHTIF4"/> 2588 </field> 2589 <field> 2590 <name>CTEIF5</name> 2591 <description>Stream x clear transfer error interrupt 2592 flag (x = 7..4)</description> 2593 <bitOffset>9</bitOffset> 2594 <bitWidth>1</bitWidth> 2595 <enumeratedValues derivedFrom="CTEIF4"/> 2596 </field> 2597 <field> 2598 <name>CDMEIF5</name> 2599 <description>Stream x clear direct mode error 2600 interrupt flag (x = 7..4)</description> 2601 <bitOffset>8</bitOffset> 2602 <bitWidth>1</bitWidth> 2603 <enumeratedValues derivedFrom="CDMEIF4"/> 2604 </field> 2605 <field> 2606 <name>CFEIF5</name> 2607 <description>Stream x clear FIFO error interrupt flag 2608 (x = 7..4)</description> 2609 <bitOffset>6</bitOffset> 2610 <bitWidth>1</bitWidth> 2611 <enumeratedValues derivedFrom="CFEIF4"/> 2612 </field> 2613 <field> 2614 <name>CTCIF4</name> 2615 <description>Stream x clear transfer complete 2616 interrupt flag (x = 7..4)</description> 2617 <bitOffset>5</bitOffset> 2618 <bitWidth>1</bitWidth> 2619 <enumeratedValues><name>CTCIF4</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>Clear the corresponding TCIFx flag</description><value>1</value></enumeratedValue></enumeratedValues> 2620 </field> 2621 <field> 2622 <name>CHTIF4</name> 2623 <description>Stream x clear half transfer interrupt 2624 flag (x = 7..4)</description> 2625 <bitOffset>4</bitOffset> 2626 <bitWidth>1</bitWidth> 2627 <enumeratedValues><name>CHTIF4</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>Clear the corresponding HTIFx flag</description><value>1</value></enumeratedValue></enumeratedValues> 2628 </field> 2629 <field> 2630 <name>CTEIF4</name> 2631 <description>Stream x clear transfer error interrupt 2632 flag (x = 7..4)</description> 2633 <bitOffset>3</bitOffset> 2634 <bitWidth>1</bitWidth> 2635 <enumeratedValues><name>CTEIF4</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>Clear the corresponding TEIFx flag</description><value>1</value></enumeratedValue></enumeratedValues> 2636 </field> 2637 <field> 2638 <name>CDMEIF4</name> 2639 <description>Stream x clear direct mode error 2640 interrupt flag (x = 7..4)</description> 2641 <bitOffset>2</bitOffset> 2642 <bitWidth>1</bitWidth> 2643 <enumeratedValues><name>CDMEIF4</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>Clear the corresponding DMEIFx flag</description><value>1</value></enumeratedValue></enumeratedValues> 2644 </field> 2645 <field> 2646 <name>CFEIF4</name> 2647 <description>Stream x clear FIFO error interrupt flag 2648 (x = 7..4)</description> 2649 <bitOffset>0</bitOffset> 2650 <bitWidth>1</bitWidth> 2651 <enumeratedValues><name>CFEIF4</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>Clear the corresponding CFEIFx flag</description><value>1</value></enumeratedValue></enumeratedValues> 2652 </field> 2653 </fields> 2654 </register> 2655 </registers> 2656 </peripheral> 2657 <peripheral derivedFrom="DMA2"> 2658 <name>DMA1</name> 2659 <baseAddress>0x40026000</baseAddress> 2660 <interrupt> 2661 <name>DMA1_Stream0</name> 2662 <description>DMA1 Stream0 global interrupt</description> 2663 <value>11</value> 2664 </interrupt> 2665 <interrupt> 2666 <name>DMA1_Stream1</name> 2667 <description>DMA1 Stream1 global interrupt</description> 2668 <value>12</value> 2669 </interrupt> 2670 <interrupt> 2671 <name>DMA1_Stream2</name> 2672 <description>DMA1 Stream2 global interrupt</description> 2673 <value>13</value> 2674 </interrupt> 2675 <interrupt> 2676 <name>DMA1_Stream3</name> 2677 <description>DMA1 Stream3 global interrupt</description> 2678 <value>14</value> 2679 </interrupt> 2680 <interrupt> 2681 <name>DMA1_Stream4</name> 2682 <description>DMA1 Stream4 global interrupt</description> 2683 <value>15</value> 2684 </interrupt> 2685 <interrupt> 2686 <name>DMA1_Stream5</name> 2687 <description>DMA1 Stream5 global interrupt</description> 2688 <value>16</value> 2689 </interrupt> 2690 <interrupt> 2691 <name>DMA1_Stream6</name> 2692 <description>DMA1 Stream6 global interrupt</description> 2693 <value>17</value> 2694 </interrupt> 2695 <interrupt> 2696 <name>DMA1_Stream7</name> 2697 <description>DMA1 Stream7 global interrupt</description> 2698 <value>47</value> 2699 </interrupt> 2700 </peripheral> 2701 <peripheral> 2702 <name>RCC</name> 2703 <description>Reset and clock control</description> 2704 <groupName>RCC</groupName> 2705 <baseAddress>0x40023800</baseAddress> 2706 <addressBlock> 2707 <offset>0x0</offset> 2708 <size>0x400</size> 2709 <usage>registers</usage> 2710 </addressBlock> 2711 <interrupt> 2712 <name>RCC</name> 2713 <description>RCC global interrupt</description> 2714 <value>5</value> 2715 </interrupt> 2716 <registers> 2717 <register> 2718 <name>CR</name> 2719 <displayName>CR</displayName> 2720 <description>clock control register</description> 2721 <addressOffset>0x0</addressOffset> 2722 <size>0x20</size> 2723 <resetValue>0x00000083</resetValue> 2724 <fields> 2725 <field> 2726 <name>PLLI2SRDY</name> 2727 <description>PLLI2S clock ready flag</description> 2728 <bitOffset>27</bitOffset> 2729 <bitWidth>1</bitWidth> 2730 <access>read-only</access> 2731 <enumeratedValues derivedFrom="HSIRDYR"/> 2732 </field> 2733 <field> 2734 <name>PLLI2SON</name> 2735 <description>PLLI2S enable</description> 2736 <bitOffset>26</bitOffset> 2737 <bitWidth>1</bitWidth> 2738 <access>read-write</access> 2739 <enumeratedValues derivedFrom="HSION"/> 2740 </field> 2741 <field> 2742 <name>PLLRDY</name> 2743 <description>Main PLL (PLL) clock ready 2744 flag</description> 2745 <bitOffset>25</bitOffset> 2746 <bitWidth>1</bitWidth> 2747 <access>read-only</access> 2748 <enumeratedValues derivedFrom="HSIRDYR"/> 2749 </field> 2750 <field> 2751 <name>PLLON</name> 2752 <description>Main PLL (PLL) enable</description> 2753 <bitOffset>24</bitOffset> 2754 <bitWidth>1</bitWidth> 2755 <access>read-write</access> 2756 <enumeratedValues derivedFrom="HSION"/> 2757 </field> 2758 <field> 2759 <name>CSSON</name> 2760 <description>Clock security system 2761 enable</description> 2762 <bitOffset>19</bitOffset> 2763 <bitWidth>1</bitWidth> 2764 <access>read-write</access> 2765 <enumeratedValues><name>CSSON</name><usage>read-write</usage><enumeratedValue><name>Off</name><description>Clock security system disabled (clock detector OFF)</description><value>0</value></enumeratedValue><enumeratedValue><name>On</name><description>Clock security system enable (clock detector ON if the HSE is ready, OFF if not)</description><value>1</value></enumeratedValue></enumeratedValues> 2766 </field> 2767 <field> 2768 <name>HSEBYP</name> 2769 <description>HSE clock bypass</description> 2770 <bitOffset>18</bitOffset> 2771 <bitWidth>1</bitWidth> 2772 <access>read-write</access> 2773 <enumeratedValues><name>HSEBYP</name><usage>read-write</usage><enumeratedValue><name>NotBypassed</name><description>HSE crystal oscillator not bypassed</description><value>0</value></enumeratedValue><enumeratedValue><name>Bypassed</name><description>HSE crystal oscillator bypassed with external clock</description><value>1</value></enumeratedValue></enumeratedValues> 2774 </field> 2775 <field> 2776 <name>HSERDY</name> 2777 <description>HSE clock ready flag</description> 2778 <bitOffset>17</bitOffset> 2779 <bitWidth>1</bitWidth> 2780 <access>read-only</access> 2781 <enumeratedValues derivedFrom="HSIRDYR"/> 2782 </field> 2783 <field> 2784 <name>HSEON</name> 2785 <description>HSE clock enable</description> 2786 <bitOffset>16</bitOffset> 2787 <bitWidth>1</bitWidth> 2788 <access>read-write</access> 2789 <enumeratedValues derivedFrom="HSION"/> 2790 </field> 2791 <field> 2792 <name>HSICAL</name> 2793 <description>Internal high-speed clock 2794 calibration</description> 2795 <bitOffset>8</bitOffset> 2796 <bitWidth>8</bitWidth> 2797 <access>read-only</access> 2798 <writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint> 2799 </field> 2800 <field> 2801 <name>HSITRIM</name> 2802 <description>Internal high-speed clock 2803 trimming</description> 2804 <bitOffset>3</bitOffset> 2805 <bitWidth>5</bitWidth> 2806 <access>read-write</access> 2807 <writeConstraint><range><minimum>0</minimum><maximum>31</maximum></range></writeConstraint> 2808 </field> 2809 <field> 2810 <name>HSIRDY</name> 2811 <description>Internal high-speed clock ready 2812 flag</description> 2813 <bitOffset>1</bitOffset> 2814 <bitWidth>1</bitWidth> 2815 <access>read-only</access> 2816 <enumeratedValues><name>HSIRDYR</name><usage>read</usage><enumeratedValue><name>NotReady</name><description>Clock not ready</description><value>0</value></enumeratedValue><enumeratedValue><name>Ready</name><description>Clock ready</description><value>1</value></enumeratedValue></enumeratedValues> 2817 </field> 2818 <field> 2819 <name>HSION</name> 2820 <description>Internal high-speed clock 2821 enable</description> 2822 <bitOffset>0</bitOffset> 2823 <bitWidth>1</bitWidth> 2824 <access>read-write</access> 2825 <enumeratedValues><name>HSION</name><usage>read-write</usage><enumeratedValue><name>Off</name><description>Clock Off</description><value>0</value></enumeratedValue><enumeratedValue><name>On</name><description>Clock On</description><value>1</value></enumeratedValue></enumeratedValues> 2826 </field> 2827 </fields> 2828 </register> 2829 <register> 2830 <name>PLLCFGR</name> 2831 <displayName>PLLCFGR</displayName> 2832 <description>PLL configuration register</description> 2833 <addressOffset>0x4</addressOffset> 2834 <size>0x20</size> 2835 <access>read-write</access> 2836 <resetValue>0x24003010</resetValue> 2837 <fields> 2838 <field> 2839 <name>PLLSRC</name> 2840 <description>Main PLL(PLL) and audio PLL (PLLI2S) 2841 entry clock source</description> 2842 <bitOffset>22</bitOffset> 2843 <bitWidth>1</bitWidth> 2844 <enumeratedValues><name>PLLSRC</name><usage>read-write</usage><enumeratedValue><name>HSI</name><description>HSI clock selected as PLL and PLLI2S clock entry</description><value>0</value></enumeratedValue><enumeratedValue><name>HSE</name><description>HSE oscillator clock selected as PLL and PLLI2S clock entry</description><value>1</value></enumeratedValue></enumeratedValues> 2845 </field> 2846 <field><name>PLLM</name><description>Division factor for the main PLL (PLL) 2847 and audio PLL (PLLI2S) input clock</description><bitOffset>0</bitOffset><bitWidth>6</bitWidth><writeConstraint><range><minimum>2</minimum><maximum>63</maximum></range></writeConstraint> 2848 </field><field><name>PLLN</name><description>Main PLL (PLL) multiplication factor for 2849 VCO</description><bitOffset>6</bitOffset><bitWidth>9</bitWidth><writeConstraint><range><minimum>50</minimum><maximum>432</maximum></range></writeConstraint> 2850 </field><field><name>PLLP</name><description>Main PLL (PLL) division factor for main 2851 system clock</description><bitOffset>16</bitOffset><bitWidth>2</bitWidth><enumeratedValues><name>PLLP</name><usage>read-write</usage><enumeratedValue><name>Div2</name><description>PLLP=2</description><value>0</value></enumeratedValue><enumeratedValue><name>Div4</name><description>PLLP=4</description><value>1</value></enumeratedValue><enumeratedValue><name>Div6</name><description>PLLP=6</description><value>2</value></enumeratedValue><enumeratedValue><name>Div8</name><description>PLLP=8</description><value>3</value></enumeratedValue></enumeratedValues> 2852 </field><field><name>PLLQ</name><description>Main PLL (PLL) division factor for USB 2853 OTG FS, SDIO and random number generator 2854 clocks</description><bitOffset>24</bitOffset><bitWidth>4</bitWidth><writeConstraint><range><minimum>2</minimum><maximum>15</maximum></range></writeConstraint> 2855 </field></fields> 2856 </register> 2857 <register> 2858 <name>CFGR</name> 2859 <displayName>CFGR</displayName> 2860 <description>clock configuration register</description> 2861 <addressOffset>0x8</addressOffset> 2862 <size>0x20</size> 2863 <resetValue>0x00000000</resetValue> 2864 <fields> 2865 <field> 2866 <name>MCO2</name> 2867 <description>Microcontroller clock output 2868 2</description> 2869 <bitOffset>30</bitOffset> 2870 <bitWidth>2</bitWidth> 2871 <access>read-write</access> 2872 <enumeratedValues><name>MCO2</name><usage>read-write</usage><enumeratedValue><name>SYSCLK</name><description>System clock (SYSCLK) selected</description><value>0</value></enumeratedValue><enumeratedValue><name>PLLI2S</name><description>PLLI2S clock selected</description><value>1</value></enumeratedValue><enumeratedValue><name>HSE</name><description>HSE oscillator clock selected</description><value>2</value></enumeratedValue><enumeratedValue><name>PLL</name><description>PLL clock selected</description><value>3</value></enumeratedValue></enumeratedValues> 2873 </field> 2874 <field> 2875 <name>MCO2PRE</name> 2876 <description>MCO2 prescaler</description> 2877 <bitOffset>27</bitOffset> 2878 <bitWidth>3</bitWidth> 2879 <access>read-write</access> 2880 <enumeratedValues derivedFrom="MCO1PRE"/> 2881 </field> 2882 <field> 2883 <name>MCO1PRE</name> 2884 <description>MCO1 prescaler</description> 2885 <bitOffset>24</bitOffset> 2886 <bitWidth>3</bitWidth> 2887 <access>read-write</access> 2888 <enumeratedValues><name>MCO1PRE</name><usage>read-write</usage><enumeratedValue><name>Div1</name><description>No division</description><value>0</value></enumeratedValue><enumeratedValue><name>Div2</name><description>Division by 2</description><value>4</value></enumeratedValue><enumeratedValue><name>Div3</name><description>Division by 3</description><value>5</value></enumeratedValue><enumeratedValue><name>Div4</name><description>Division by 4</description><value>6</value></enumeratedValue><enumeratedValue><name>Div5</name><description>Division by 5</description><value>7</value></enumeratedValue></enumeratedValues> 2889 </field> 2890 <field> 2891 <name>I2SSRC</name> 2892 <description>I2S clock selection</description> 2893 <bitOffset>23</bitOffset> 2894 <bitWidth>1</bitWidth> 2895 <access>read-write</access> 2896 <enumeratedValues><name>I2SSRC</name><usage>read-write</usage><enumeratedValue><name>PLLI2S</name><description>PLLI2S clock used as I2S clock source</description><value>0</value></enumeratedValue><enumeratedValue><name>CKIN</name><description>External clock mapped on the I2S_CKIN pin used as I2S clock source</description><value>1</value></enumeratedValue></enumeratedValues> 2897 </field> 2898 <field> 2899 <name>MCO1</name> 2900 <description>Microcontroller clock output 2901 1</description> 2902 <bitOffset>21</bitOffset> 2903 <bitWidth>2</bitWidth> 2904 <access>read-write</access> 2905 <enumeratedValues><name>MCO1</name><usage>read-write</usage><enumeratedValue><name>HSI</name><description>HSI clock selected</description><value>0</value></enumeratedValue><enumeratedValue><name>LSE</name><description>LSE oscillator selected</description><value>1</value></enumeratedValue><enumeratedValue><name>HSE</name><description>HSE oscillator clock selected</description><value>2</value></enumeratedValue><enumeratedValue><name>PLL</name><description>PLL clock selected</description><value>3</value></enumeratedValue></enumeratedValues> 2906 </field> 2907 <field> 2908 <name>RTCPRE</name> 2909 <description>HSE division factor for RTC 2910 clock</description> 2911 <bitOffset>16</bitOffset> 2912 <bitWidth>5</bitWidth> 2913 <access>read-write</access> 2914 <writeConstraint><range><minimum>0</minimum><maximum>31</maximum></range></writeConstraint> 2915 </field> 2916 <field> 2917 <name>PPRE2</name> 2918 <description>APB high-speed prescaler 2919 (APB2)</description> 2920 <bitOffset>13</bitOffset> 2921 <bitWidth>3</bitWidth> 2922 <access>read-write</access> 2923 <enumeratedValues derivedFrom="PPRE1"/> 2924 </field> 2925 <field> 2926 <name>PPRE1</name> 2927 <description>APB Low speed prescaler 2928 (APB1)</description> 2929 <bitOffset>10</bitOffset> 2930 <bitWidth>3</bitWidth> 2931 <access>read-write</access> 2932 <enumeratedValues><name>PPRE1</name><usage>read-write</usage><enumeratedValue><name>Div1</name><description>HCLK not divided</description><value>0</value></enumeratedValue><enumeratedValue><name>Div2</name><description>HCLK divided by 2</description><value>4</value></enumeratedValue><enumeratedValue><name>Div4</name><description>HCLK divided by 4</description><value>5</value></enumeratedValue><enumeratedValue><name>Div8</name><description>HCLK divided by 8</description><value>6</value></enumeratedValue><enumeratedValue><name>Div16</name><description>HCLK divided by 16</description><value>7</value></enumeratedValue></enumeratedValues> 2933 </field> 2934 <field> 2935 <name>HPRE</name> 2936 <description>AHB prescaler</description> 2937 <bitOffset>4</bitOffset> 2938 <bitWidth>4</bitWidth> 2939 <access>read-write</access> 2940 <enumeratedValues><name>HPRE</name><usage>read-write</usage><enumeratedValue><name>Div1</name><description>SYSCLK not divided</description><value>0</value></enumeratedValue><enumeratedValue><name>Div2</name><description>SYSCLK divided by 2</description><value>8</value></enumeratedValue><enumeratedValue><name>Div4</name><description>SYSCLK divided by 4</description><value>9</value></enumeratedValue><enumeratedValue><name>Div8</name><description>SYSCLK divided by 8</description><value>10</value></enumeratedValue><enumeratedValue><name>Div16</name><description>SYSCLK divided by 16</description><value>11</value></enumeratedValue><enumeratedValue><name>Div64</name><description>SYSCLK divided by 64</description><value>12</value></enumeratedValue><enumeratedValue><name>Div128</name><description>SYSCLK divided by 128</description><value>13</value></enumeratedValue><enumeratedValue><name>Div256</name><description>SYSCLK divided by 256</description><value>14</value></enumeratedValue><enumeratedValue><name>Div512</name><description>SYSCLK divided by 512</description><value>15</value></enumeratedValue></enumeratedValues> 2941 </field> 2942 <field><name>SW</name><description>System clock switch</description><bitOffset>0</bitOffset><bitWidth>2</bitWidth><enumeratedValues><name>SW</name><usage>read-write</usage><enumeratedValue><name>HSI</name><description>HSI selected as system clock</description><value>0</value></enumeratedValue><enumeratedValue><name>HSE</name><description>HSE selected as system clock</description><value>1</value></enumeratedValue><enumeratedValue><name>PLL</name><description>PLL selected as system clock</description><value>2</value></enumeratedValue></enumeratedValues> 2943 </field><field><name>SWS</name><description>System clock switch status</description><bitOffset>2</bitOffset><bitWidth>2</bitWidth><enumeratedValues><name>SWSR</name><usage>read</usage><enumeratedValue><name>HSI</name><description>HSI oscillator used as system clock</description><value>0</value></enumeratedValue><enumeratedValue><name>HSE</name><description>HSE oscillator used as system clock</description><value>1</value></enumeratedValue><enumeratedValue><name>PLL</name><description>PLL used as system clock</description><value>2</value></enumeratedValue></enumeratedValues> 2944 </field></fields> 2945 </register> 2946 <register> 2947 <name>CIR</name> 2948 <displayName>CIR</displayName> 2949 <description>clock interrupt register</description> 2950 <addressOffset>0xC</addressOffset> 2951 <size>0x20</size> 2952 <resetValue>0x00000000</resetValue> 2953 <fields> 2954 <field> 2955 <name>CSSC</name> 2956 <description>Clock security system interrupt 2957 clear</description> 2958 <bitOffset>23</bitOffset> 2959 <bitWidth>1</bitWidth> 2960 <access>write-only</access> 2961 <enumeratedValues><name>CSSCW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clear CSSF flag</description><value>1</value></enumeratedValue></enumeratedValues> 2962 </field> 2963 <field> 2964 <name>PLLI2SRDYC</name> 2965 <description>PLLI2S ready interrupt 2966 clear</description> 2967 <bitOffset>21</bitOffset> 2968 <bitWidth>1</bitWidth> 2969 <access>write-only</access> 2970 <enumeratedValues derivedFrom="LSIRDYCW"/> 2971 </field> 2972 <field> 2973 <name>PLLRDYC</name> 2974 <description>Main PLL(PLL) ready interrupt 2975 clear</description> 2976 <bitOffset>20</bitOffset> 2977 <bitWidth>1</bitWidth> 2978 <access>write-only</access> 2979 <enumeratedValues derivedFrom="LSIRDYCW"/> 2980 </field> 2981 <field> 2982 <name>HSERDYC</name> 2983 <description>HSE ready interrupt clear</description> 2984 <bitOffset>19</bitOffset> 2985 <bitWidth>1</bitWidth> 2986 <access>write-only</access> 2987 <enumeratedValues derivedFrom="LSIRDYCW"/> 2988 </field> 2989 <field> 2990 <name>HSIRDYC</name> 2991 <description>HSI ready interrupt clear</description> 2992 <bitOffset>18</bitOffset> 2993 <bitWidth>1</bitWidth> 2994 <access>write-only</access> 2995 <enumeratedValues derivedFrom="LSIRDYCW"/> 2996 </field> 2997 <field> 2998 <name>LSERDYC</name> 2999 <description>LSE ready interrupt clear</description> 3000 <bitOffset>17</bitOffset> 3001 <bitWidth>1</bitWidth> 3002 <access>write-only</access> 3003 <enumeratedValues derivedFrom="LSIRDYCW"/> 3004 </field> 3005 <field> 3006 <name>LSIRDYC</name> 3007 <description>LSI ready interrupt clear</description> 3008 <bitOffset>16</bitOffset> 3009 <bitWidth>1</bitWidth> 3010 <access>write-only</access> 3011 <enumeratedValues><name>LSIRDYCW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clear interrupt flag</description><value>1</value></enumeratedValue></enumeratedValues> 3012 </field> 3013 <field> 3014 <name>PLLI2SRDYIE</name> 3015 <description>PLLI2S ready interrupt 3016 enable</description> 3017 <bitOffset>13</bitOffset> 3018 <bitWidth>1</bitWidth> 3019 <access>read-write</access> 3020 <enumeratedValues derivedFrom="LSIRDYIE"/> 3021 </field> 3022 <field> 3023 <name>PLLRDYIE</name> 3024 <description>Main PLL (PLL) ready interrupt 3025 enable</description> 3026 <bitOffset>12</bitOffset> 3027 <bitWidth>1</bitWidth> 3028 <access>read-write</access> 3029 <enumeratedValues derivedFrom="LSIRDYIE"/> 3030 </field> 3031 <field> 3032 <name>HSERDYIE</name> 3033 <description>HSE ready interrupt enable</description> 3034 <bitOffset>11</bitOffset> 3035 <bitWidth>1</bitWidth> 3036 <access>read-write</access> 3037 <enumeratedValues derivedFrom="LSIRDYIE"/> 3038 </field> 3039 <field> 3040 <name>HSIRDYIE</name> 3041 <description>HSI ready interrupt enable</description> 3042 <bitOffset>10</bitOffset> 3043 <bitWidth>1</bitWidth> 3044 <access>read-write</access> 3045 <enumeratedValues derivedFrom="LSIRDYIE"/> 3046 </field> 3047 <field> 3048 <name>LSERDYIE</name> 3049 <description>LSE ready interrupt enable</description> 3050 <bitOffset>9</bitOffset> 3051 <bitWidth>1</bitWidth> 3052 <access>read-write</access> 3053 <enumeratedValues derivedFrom="LSIRDYIE"/> 3054 </field> 3055 <field> 3056 <name>LSIRDYIE</name> 3057 <description>LSI ready interrupt enable</description> 3058 <bitOffset>8</bitOffset> 3059 <bitWidth>1</bitWidth> 3060 <access>read-write</access> 3061 <enumeratedValues><name>LSIRDYIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 3062 </field> 3063 <field> 3064 <name>CSSF</name> 3065 <description>Clock security system interrupt 3066 flag</description> 3067 <bitOffset>7</bitOffset> 3068 <bitWidth>1</bitWidth> 3069 <access>read-only</access> 3070 <enumeratedValues><name>CSSFR</name><usage>read</usage><enumeratedValue><name>NotInterrupted</name><description>No clock security interrupt caused by HSE clock failure</description><value>0</value></enumeratedValue><enumeratedValue><name>Interrupted</name><description>Clock security interrupt caused by HSE clock failure</description><value>1</value></enumeratedValue></enumeratedValues> 3071 </field> 3072 <field> 3073 <name>PLLI2SRDYF</name> 3074 <description>PLLI2S ready interrupt 3075 flag</description> 3076 <bitOffset>5</bitOffset> 3077 <bitWidth>1</bitWidth> 3078 <access>read-only</access> 3079 <enumeratedValues derivedFrom="LSIRDYFR"/> 3080 </field> 3081 <field> 3082 <name>PLLRDYF</name> 3083 <description>Main PLL (PLL) ready interrupt 3084 flag</description> 3085 <bitOffset>4</bitOffset> 3086 <bitWidth>1</bitWidth> 3087 <access>read-only</access> 3088 <enumeratedValues derivedFrom="LSIRDYFR"/> 3089 </field> 3090 <field> 3091 <name>HSERDYF</name> 3092 <description>HSE ready interrupt flag</description> 3093 <bitOffset>3</bitOffset> 3094 <bitWidth>1</bitWidth> 3095 <access>read-only</access> 3096 <enumeratedValues derivedFrom="LSIRDYFR"/> 3097 </field> 3098 <field> 3099 <name>HSIRDYF</name> 3100 <description>HSI ready interrupt flag</description> 3101 <bitOffset>2</bitOffset> 3102 <bitWidth>1</bitWidth> 3103 <access>read-only</access> 3104 <enumeratedValues derivedFrom="LSIRDYFR"/> 3105 </field> 3106 <field> 3107 <name>LSERDYF</name> 3108 <description>LSE ready interrupt flag</description> 3109 <bitOffset>1</bitOffset> 3110 <bitWidth>1</bitWidth> 3111 <access>read-only</access> 3112 <enumeratedValues derivedFrom="LSIRDYFR"/> 3113 </field> 3114 <field> 3115 <name>LSIRDYF</name> 3116 <description>LSI ready interrupt flag</description> 3117 <bitOffset>0</bitOffset> 3118 <bitWidth>1</bitWidth> 3119 <access>read-only</access> 3120 <enumeratedValues><name>LSIRDYFR</name><usage>read</usage><enumeratedValue><name>NotInterrupted</name><description>No clock ready interrupt</description><value>0</value></enumeratedValue><enumeratedValue><name>Interrupted</name><description>Clock ready interrupt</description><value>1</value></enumeratedValue></enumeratedValues> 3121 </field> 3122 </fields> 3123 </register> 3124 <register> 3125 <name>AHB1RSTR</name> 3126 <displayName>AHB1RSTR</displayName> 3127 <description>AHB1 peripheral reset register</description> 3128 <addressOffset>0x10</addressOffset> 3129 <size>0x20</size> 3130 <access>read-write</access> 3131 <resetValue>0x00000000</resetValue> 3132 <fields> 3133 <field> 3134 <name>OTGHSRST</name> 3135 <description>USB OTG HS module reset</description> 3136 <bitOffset>29</bitOffset> 3137 <bitWidth>1</bitWidth> 3138 <enumeratedValues derivedFrom="GPIOARST"/> 3139 </field> 3140 <field> 3141 <name>ETHMACRST</name> 3142 <description>Ethernet MAC reset</description> 3143 <bitOffset>25</bitOffset> 3144 <bitWidth>1</bitWidth> 3145 <enumeratedValues derivedFrom="GPIOARST"/> 3146 </field> 3147 <field> 3148 <name>DMA2RST</name> 3149 <description>DMA2 reset</description> 3150 <bitOffset>22</bitOffset> 3151 <bitWidth>1</bitWidth> 3152 <enumeratedValues derivedFrom="GPIOARST"/> 3153 </field> 3154 <field> 3155 <name>DMA1RST</name> 3156 <description>DMA2 reset</description> 3157 <bitOffset>21</bitOffset> 3158 <bitWidth>1</bitWidth> 3159 <enumeratedValues derivedFrom="GPIOARST"/> 3160 </field> 3161 <field> 3162 <name>CRCRST</name> 3163 <description>CRC reset</description> 3164 <bitOffset>12</bitOffset> 3165 <bitWidth>1</bitWidth> 3166 <enumeratedValues derivedFrom="GPIOARST"/> 3167 </field> 3168 <field> 3169 <name>GPIOIRST</name> 3170 <description>IO port I reset</description> 3171 <bitOffset>8</bitOffset> 3172 <bitWidth>1</bitWidth> 3173 <enumeratedValues derivedFrom="GPIOARST"/> 3174 </field> 3175 <field> 3176 <name>GPIOHRST</name> 3177 <description>IO port H reset</description> 3178 <bitOffset>7</bitOffset> 3179 <bitWidth>1</bitWidth> 3180 <enumeratedValues derivedFrom="GPIOARST"/> 3181 </field> 3182 <field> 3183 <name>GPIOGRST</name> 3184 <description>IO port G reset</description> 3185 <bitOffset>6</bitOffset> 3186 <bitWidth>1</bitWidth> 3187 <enumeratedValues derivedFrom="GPIOARST"/> 3188 </field> 3189 <field> 3190 <name>GPIOFRST</name> 3191 <description>IO port F reset</description> 3192 <bitOffset>5</bitOffset> 3193 <bitWidth>1</bitWidth> 3194 <enumeratedValues derivedFrom="GPIOARST"/> 3195 </field> 3196 <field> 3197 <name>GPIOERST</name> 3198 <description>IO port E reset</description> 3199 <bitOffset>4</bitOffset> 3200 <bitWidth>1</bitWidth> 3201 <enumeratedValues derivedFrom="GPIOARST"/> 3202 </field> 3203 <field> 3204 <name>GPIODRST</name> 3205 <description>IO port D reset</description> 3206 <bitOffset>3</bitOffset> 3207 <bitWidth>1</bitWidth> 3208 <enumeratedValues derivedFrom="GPIOARST"/> 3209 </field> 3210 <field> 3211 <name>GPIOCRST</name> 3212 <description>IO port C reset</description> 3213 <bitOffset>2</bitOffset> 3214 <bitWidth>1</bitWidth> 3215 <enumeratedValues derivedFrom="GPIOARST"/> 3216 </field> 3217 <field> 3218 <name>GPIOBRST</name> 3219 <description>IO port B reset</description> 3220 <bitOffset>1</bitOffset> 3221 <bitWidth>1</bitWidth> 3222 <enumeratedValues derivedFrom="GPIOARST"/> 3223 </field> 3224 <field> 3225 <name>GPIOARST</name> 3226 <description>IO port A reset</description> 3227 <bitOffset>0</bitOffset> 3228 <bitWidth>1</bitWidth> 3229 <enumeratedValues><name>GPIOARST</name><usage>read-write</usage><enumeratedValue><name>Reset</name><description>Reset the selected module</description><value>1</value></enumeratedValue></enumeratedValues> 3230 </field> 3231 </fields> 3232 </register> 3233 <register> 3234 <name>AHB2RSTR</name> 3235 <displayName>AHB2RSTR</displayName> 3236 <description>AHB2 peripheral reset register</description> 3237 <addressOffset>0x14</addressOffset> 3238 <size>0x20</size> 3239 <access>read-write</access> 3240 <resetValue>0x00000000</resetValue> 3241 <fields> 3242 <field> 3243 <name>OTGFSRST</name> 3244 <description>USB OTG FS module reset</description> 3245 <bitOffset>7</bitOffset> 3246 <bitWidth>1</bitWidth> 3247 <enumeratedValues derivedFrom="DCMIRST"/> 3248 </field> 3249 <field> 3250 <name>RNGRST</name> 3251 <description>Random number generator module 3252 reset</description> 3253 <bitOffset>6</bitOffset> 3254 <bitWidth>1</bitWidth> 3255 <enumeratedValues derivedFrom="DCMIRST"/> 3256 </field> 3257 <field> 3258 <name>DCMIRST</name> 3259 <description>Camera interface reset</description> 3260 <bitOffset>0</bitOffset> 3261 <bitWidth>1</bitWidth> 3262 <enumeratedValues><name>DCMIRST</name><usage>read-write</usage><enumeratedValue><name>Reset</name><description>Reset the selected module</description><value>1</value></enumeratedValue></enumeratedValues> 3263 </field> 3264 </fields> 3265 </register> 3266 <register> 3267 <name>AHB3RSTR</name> 3268 <displayName>AHB3RSTR</displayName> 3269 <description>AHB3 peripheral reset register</description> 3270 <addressOffset>0x18</addressOffset> 3271 <size>0x20</size> 3272 <access>read-write</access> 3273 <resetValue>0x00000000</resetValue> 3274 <fields> 3275 <field> 3276 <name>FSMCRST</name> 3277 <description>Flexible static memory controller module 3278 reset</description> 3279 <bitOffset>0</bitOffset> 3280 <bitWidth>1</bitWidth> 3281 <enumeratedValues><name>FSMCRST</name><usage>read-write</usage><enumeratedValue><name>Reset</name><description>Reset the selected module</description><value>1</value></enumeratedValue></enumeratedValues> 3282 </field> 3283 </fields> 3284 </register> 3285 <register> 3286 <name>APB1RSTR</name> 3287 <displayName>APB1RSTR</displayName> 3288 <description>APB1 peripheral reset register</description> 3289 <addressOffset>0x20</addressOffset> 3290 <size>0x20</size> 3291 <access>read-write</access> 3292 <resetValue>0x00000000</resetValue> 3293 <fields> 3294 <field> 3295 <name>DACRST</name> 3296 <description>DAC reset</description> 3297 <bitOffset>29</bitOffset> 3298 <bitWidth>1</bitWidth> 3299 <enumeratedValues derivedFrom="TIM2RST"/> 3300 </field> 3301 <field> 3302 <name>PWRRST</name> 3303 <description>Power interface reset</description> 3304 <bitOffset>28</bitOffset> 3305 <bitWidth>1</bitWidth> 3306 <enumeratedValues derivedFrom="TIM2RST"/> 3307 </field> 3308 <field> 3309 <name>CAN2RST</name> 3310 <description>CAN2 reset</description> 3311 <bitOffset>26</bitOffset> 3312 <bitWidth>1</bitWidth> 3313 <enumeratedValues derivedFrom="TIM2RST"/> 3314 </field> 3315 <field> 3316 <name>CAN1RST</name> 3317 <description>CAN1 reset</description> 3318 <bitOffset>25</bitOffset> 3319 <bitWidth>1</bitWidth> 3320 <enumeratedValues derivedFrom="TIM2RST"/> 3321 </field> 3322 <field> 3323 <name>I2C3RST</name> 3324 <description>I2C3 reset</description> 3325 <bitOffset>23</bitOffset> 3326 <bitWidth>1</bitWidth> 3327 <enumeratedValues derivedFrom="TIM2RST"/> 3328 </field> 3329 <field> 3330 <name>I2C2RST</name> 3331 <description>I2C 2 reset</description> 3332 <bitOffset>22</bitOffset> 3333 <bitWidth>1</bitWidth> 3334 <enumeratedValues derivedFrom="TIM2RST"/> 3335 </field> 3336 <field> 3337 <name>I2C1RST</name> 3338 <description>I2C 1 reset</description> 3339 <bitOffset>21</bitOffset> 3340 <bitWidth>1</bitWidth> 3341 <enumeratedValues derivedFrom="TIM2RST"/> 3342 </field> 3343 <field> 3344 <name>UART5RST</name> 3345 <description>USART 5 reset</description> 3346 <bitOffset>20</bitOffset> 3347 <bitWidth>1</bitWidth> 3348 <enumeratedValues derivedFrom="TIM2RST"/> 3349 </field> 3350 <field> 3351 <name>UART4RST</name> 3352 <description>USART 4 reset</description> 3353 <bitOffset>19</bitOffset> 3354 <bitWidth>1</bitWidth> 3355 <enumeratedValues derivedFrom="TIM2RST"/> 3356 </field> 3357 <field> 3358 <name>USART3RST</name> 3359 <description>USART 3 reset</description> 3360 <bitOffset>18</bitOffset> 3361 <bitWidth>1</bitWidth> 3362 <enumeratedValues derivedFrom="TIM2RST"/> 3363 </field> 3364 <field> 3365 <name>USART2RST</name> 3366 <description>USART 2 reset</description> 3367 <bitOffset>17</bitOffset> 3368 <bitWidth>1</bitWidth> 3369 <enumeratedValues derivedFrom="TIM2RST"/> 3370 </field> 3371 <field> 3372 <name>SPI3RST</name> 3373 <description>SPI 3 reset</description> 3374 <bitOffset>15</bitOffset> 3375 <bitWidth>1</bitWidth> 3376 <enumeratedValues derivedFrom="TIM2RST"/> 3377 </field> 3378 <field> 3379 <name>SPI2RST</name> 3380 <description>SPI 2 reset</description> 3381 <bitOffset>14</bitOffset> 3382 <bitWidth>1</bitWidth> 3383 <enumeratedValues derivedFrom="TIM2RST"/> 3384 </field> 3385 <field> 3386 <name>WWDGRST</name> 3387 <description>Window watchdog reset</description> 3388 <bitOffset>11</bitOffset> 3389 <bitWidth>1</bitWidth> 3390 <enumeratedValues derivedFrom="TIM2RST"/> 3391 </field> 3392 <field> 3393 <name>TIM14RST</name> 3394 <description>TIM14 reset</description> 3395 <bitOffset>8</bitOffset> 3396 <bitWidth>1</bitWidth> 3397 <enumeratedValues derivedFrom="TIM2RST"/> 3398 </field> 3399 <field> 3400 <name>TIM13RST</name> 3401 <description>TIM13 reset</description> 3402 <bitOffset>7</bitOffset> 3403 <bitWidth>1</bitWidth> 3404 <enumeratedValues derivedFrom="TIM2RST"/> 3405 </field> 3406 <field> 3407 <name>TIM12RST</name> 3408 <description>TIM12 reset</description> 3409 <bitOffset>6</bitOffset> 3410 <bitWidth>1</bitWidth> 3411 <enumeratedValues derivedFrom="TIM2RST"/> 3412 </field> 3413 <field> 3414 <name>TIM7RST</name> 3415 <description>TIM7 reset</description> 3416 <bitOffset>5</bitOffset> 3417 <bitWidth>1</bitWidth> 3418 <enumeratedValues derivedFrom="TIM2RST"/> 3419 </field> 3420 <field> 3421 <name>TIM6RST</name> 3422 <description>TIM6 reset</description> 3423 <bitOffset>4</bitOffset> 3424 <bitWidth>1</bitWidth> 3425 <enumeratedValues derivedFrom="TIM2RST"/> 3426 </field> 3427 <field> 3428 <name>TIM5RST</name> 3429 <description>TIM5 reset</description> 3430 <bitOffset>3</bitOffset> 3431 <bitWidth>1</bitWidth> 3432 <enumeratedValues derivedFrom="TIM2RST"/> 3433 </field> 3434 <field> 3435 <name>TIM4RST</name> 3436 <description>TIM4 reset</description> 3437 <bitOffset>2</bitOffset> 3438 <bitWidth>1</bitWidth> 3439 <enumeratedValues derivedFrom="TIM2RST"/> 3440 </field> 3441 <field> 3442 <name>TIM3RST</name> 3443 <description>TIM3 reset</description> 3444 <bitOffset>1</bitOffset> 3445 <bitWidth>1</bitWidth> 3446 <enumeratedValues derivedFrom="TIM2RST"/> 3447 </field> 3448 <field> 3449 <name>TIM2RST</name> 3450 <description>TIM2 reset</description> 3451 <bitOffset>0</bitOffset> 3452 <bitWidth>1</bitWidth> 3453 <enumeratedValues><name>TIM2RST</name><usage>read-write</usage><enumeratedValue><name>Reset</name><description>Reset the selected module</description><value>1</value></enumeratedValue></enumeratedValues> 3454 </field> 3455 </fields> 3456 </register> 3457 <register> 3458 <name>APB2RSTR</name> 3459 <displayName>APB2RSTR</displayName> 3460 <description>APB2 peripheral reset register</description> 3461 <addressOffset>0x24</addressOffset> 3462 <size>0x20</size> 3463 <access>read-write</access> 3464 <resetValue>0x00000000</resetValue> 3465 <fields> 3466 <field> 3467 <name>TIM11RST</name> 3468 <description>TIM11 reset</description> 3469 <bitOffset>18</bitOffset> 3470 <bitWidth>1</bitWidth> 3471 <enumeratedValues derivedFrom="TIM1RST"/> 3472 </field> 3473 <field> 3474 <name>TIM10RST</name> 3475 <description>TIM10 reset</description> 3476 <bitOffset>17</bitOffset> 3477 <bitWidth>1</bitWidth> 3478 <enumeratedValues derivedFrom="TIM1RST"/> 3479 </field> 3480 <field> 3481 <name>TIM9RST</name> 3482 <description>TIM9 reset</description> 3483 <bitOffset>16</bitOffset> 3484 <bitWidth>1</bitWidth> 3485 <enumeratedValues derivedFrom="TIM1RST"/> 3486 </field> 3487 <field> 3488 <name>SYSCFGRST</name> 3489 <description>System configuration controller 3490 reset</description> 3491 <bitOffset>14</bitOffset> 3492 <bitWidth>1</bitWidth> 3493 <enumeratedValues derivedFrom="TIM1RST"/> 3494 </field> 3495 <field> 3496 <name>SPI1RST</name> 3497 <description>SPI 1 reset</description> 3498 <bitOffset>12</bitOffset> 3499 <bitWidth>1</bitWidth> 3500 <enumeratedValues derivedFrom="TIM1RST"/> 3501 </field> 3502 <field> 3503 <name>SDIORST</name> 3504 <description>SDIO reset</description> 3505 <bitOffset>11</bitOffset> 3506 <bitWidth>1</bitWidth> 3507 <enumeratedValues derivedFrom="TIM1RST"/> 3508 </field> 3509 <field> 3510 <name>ADCRST</name> 3511 <description>ADC interface reset (common to all 3512 ADCs)</description> 3513 <bitOffset>8</bitOffset> 3514 <bitWidth>1</bitWidth> 3515 <enumeratedValues derivedFrom="TIM1RST"/> 3516 </field> 3517 <field> 3518 <name>USART6RST</name> 3519 <description>USART6 reset</description> 3520 <bitOffset>5</bitOffset> 3521 <bitWidth>1</bitWidth> 3522 <enumeratedValues derivedFrom="TIM1RST"/> 3523 </field> 3524 <field> 3525 <name>USART1RST</name> 3526 <description>USART1 reset</description> 3527 <bitOffset>4</bitOffset> 3528 <bitWidth>1</bitWidth> 3529 <enumeratedValues derivedFrom="TIM1RST"/> 3530 </field> 3531 <field> 3532 <name>TIM8RST</name> 3533 <description>TIM8 reset</description> 3534 <bitOffset>1</bitOffset> 3535 <bitWidth>1</bitWidth> 3536 <enumeratedValues derivedFrom="TIM1RST"/> 3537 </field> 3538 <field> 3539 <name>TIM1RST</name> 3540 <description>TIM1 reset</description> 3541 <bitOffset>0</bitOffset> 3542 <bitWidth>1</bitWidth> 3543 <enumeratedValues><name>TIM1RST</name><usage>read-write</usage><enumeratedValue><name>Reset</name><description>Reset the selected module</description><value>1</value></enumeratedValue></enumeratedValues> 3544 </field> 3545 </fields> 3546 </register> 3547 <register> 3548 <name>AHB1ENR</name> 3549 <displayName>AHB1ENR</displayName> 3550 <description>AHB1 peripheral clock register</description> 3551 <addressOffset>0x30</addressOffset> 3552 <size>0x20</size> 3553 <access>read-write</access> 3554 <resetValue>0x00100000</resetValue> 3555 <fields> 3556 <field> 3557 <name>OTGHSULPIEN</name> 3558 <description>USB OTG HSULPI clock 3559 enable</description> 3560 <bitOffset>30</bitOffset> 3561 <bitWidth>1</bitWidth> 3562 <enumeratedValues derivedFrom="GPIOAEN"/> 3563 </field> 3564 <field> 3565 <name>OTGHSEN</name> 3566 <description>USB OTG HS clock enable</description> 3567 <bitOffset>29</bitOffset> 3568 <bitWidth>1</bitWidth> 3569 <enumeratedValues derivedFrom="GPIOAEN"/> 3570 </field> 3571 <field> 3572 <name>ETHMACPTPEN</name> 3573 <description>Ethernet PTP clock enable</description> 3574 <bitOffset>28</bitOffset> 3575 <bitWidth>1</bitWidth> 3576 <enumeratedValues derivedFrom="GPIOAEN"/> 3577 </field> 3578 <field> 3579 <name>ETHMACRXEN</name> 3580 <description>Ethernet Reception clock 3581 enable</description> 3582 <bitOffset>27</bitOffset> 3583 <bitWidth>1</bitWidth> 3584 <enumeratedValues derivedFrom="GPIOAEN"/> 3585 </field> 3586 <field> 3587 <name>ETHMACTXEN</name> 3588 <description>Ethernet Transmission clock 3589 enable</description> 3590 <bitOffset>26</bitOffset> 3591 <bitWidth>1</bitWidth> 3592 <enumeratedValues derivedFrom="GPIOAEN"/> 3593 </field> 3594 <field> 3595 <name>ETHMACEN</name> 3596 <description>Ethernet MAC clock enable</description> 3597 <bitOffset>25</bitOffset> 3598 <bitWidth>1</bitWidth> 3599 <enumeratedValues derivedFrom="GPIOAEN"/> 3600 </field> 3601 <field> 3602 <name>DMA2EN</name> 3603 <description>DMA2 clock enable</description> 3604 <bitOffset>22</bitOffset> 3605 <bitWidth>1</bitWidth> 3606 <enumeratedValues derivedFrom="GPIOAEN"/> 3607 </field> 3608 <field> 3609 <name>DMA1EN</name> 3610 <description>DMA1 clock enable</description> 3611 <bitOffset>21</bitOffset> 3612 <bitWidth>1</bitWidth> 3613 <enumeratedValues derivedFrom="GPIOAEN"/> 3614 </field> 3615 <field> 3616 <name>BKPSRAMEN</name> 3617 <description>Backup SRAM interface clock 3618 enable</description> 3619 <bitOffset>18</bitOffset> 3620 <bitWidth>1</bitWidth> 3621 <enumeratedValues derivedFrom="GPIOAEN"/> 3622 </field> 3623 <field> 3624 <name>CRCEN</name> 3625 <description>CRC clock enable</description> 3626 <bitOffset>12</bitOffset> 3627 <bitWidth>1</bitWidth> 3628 <enumeratedValues derivedFrom="GPIOAEN"/> 3629 </field> 3630 <field> 3631 <name>GPIOIEN</name> 3632 <description>IO port I clock enable</description> 3633 <bitOffset>8</bitOffset> 3634 <bitWidth>1</bitWidth> 3635 <enumeratedValues derivedFrom="GPIOAEN"/> 3636 </field> 3637 <field> 3638 <name>GPIOHEN</name> 3639 <description>IO port H clock enable</description> 3640 <bitOffset>7</bitOffset> 3641 <bitWidth>1</bitWidth> 3642 <enumeratedValues derivedFrom="GPIOAEN"/> 3643 </field> 3644 <field> 3645 <name>GPIOGEN</name> 3646 <description>IO port G clock enable</description> 3647 <bitOffset>6</bitOffset> 3648 <bitWidth>1</bitWidth> 3649 <enumeratedValues derivedFrom="GPIOAEN"/> 3650 </field> 3651 <field> 3652 <name>GPIOFEN</name> 3653 <description>IO port F clock enable</description> 3654 <bitOffset>5</bitOffset> 3655 <bitWidth>1</bitWidth> 3656 <enumeratedValues derivedFrom="GPIOAEN"/> 3657 </field> 3658 <field> 3659 <name>GPIOEEN</name> 3660 <description>IO port E clock enable</description> 3661 <bitOffset>4</bitOffset> 3662 <bitWidth>1</bitWidth> 3663 <enumeratedValues derivedFrom="GPIOAEN"/> 3664 </field> 3665 <field> 3666 <name>GPIODEN</name> 3667 <description>IO port D clock enable</description> 3668 <bitOffset>3</bitOffset> 3669 <bitWidth>1</bitWidth> 3670 <enumeratedValues derivedFrom="GPIOAEN"/> 3671 </field> 3672 <field> 3673 <name>GPIOCEN</name> 3674 <description>IO port C clock enable</description> 3675 <bitOffset>2</bitOffset> 3676 <bitWidth>1</bitWidth> 3677 <enumeratedValues derivedFrom="GPIOAEN"/> 3678 </field> 3679 <field> 3680 <name>GPIOBEN</name> 3681 <description>IO port B clock enable</description> 3682 <bitOffset>1</bitOffset> 3683 <bitWidth>1</bitWidth> 3684 <enumeratedValues derivedFrom="GPIOAEN"/> 3685 </field> 3686 <field> 3687 <name>GPIOAEN</name> 3688 <description>IO port A clock enable</description> 3689 <bitOffset>0</bitOffset> 3690 <bitWidth>1</bitWidth> 3691 <enumeratedValues><name>GPIOAEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>The selected clock is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>The selected clock is enabled</description><value>1</value></enumeratedValue></enumeratedValues> 3692 </field> 3693 </fields> 3694 </register> 3695 <register> 3696 <name>AHB2ENR</name> 3697 <displayName>AHB2ENR</displayName> 3698 <description>AHB2 peripheral clock enable 3699 register</description> 3700 <addressOffset>0x34</addressOffset> 3701 <size>0x20</size> 3702 <access>read-write</access> 3703 <resetValue>0x00000000</resetValue> 3704 <fields> 3705 <field> 3706 <name>OTGFSEN</name> 3707 <description>USB OTG FS clock enable</description> 3708 <bitOffset>7</bitOffset> 3709 <bitWidth>1</bitWidth> 3710 <enumeratedValues derivedFrom="DCMIEN"/> 3711 </field> 3712 <field> 3713 <name>RNGEN</name> 3714 <description>Random number generator clock 3715 enable</description> 3716 <bitOffset>6</bitOffset> 3717 <bitWidth>1</bitWidth> 3718 <enumeratedValues derivedFrom="DCMIEN"/> 3719 </field> 3720 <field> 3721 <name>DCMIEN</name> 3722 <description>Camera interface enable</description> 3723 <bitOffset>0</bitOffset> 3724 <bitWidth>1</bitWidth> 3725 <enumeratedValues><name>DCMIEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>The selected clock is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>The selected clock is enabled</description><value>1</value></enumeratedValue></enumeratedValues> 3726 </field> 3727 </fields> 3728 </register> 3729 <register> 3730 <name>AHB3ENR</name> 3731 <displayName>AHB3ENR</displayName> 3732 <description>AHB3 peripheral clock enable 3733 register</description> 3734 <addressOffset>0x38</addressOffset> 3735 <size>0x20</size> 3736 <access>read-write</access> 3737 <resetValue>0x00000000</resetValue> 3738 <fields> 3739 <field> 3740 <name>FSMCEN</name> 3741 <description>Flexible static memory controller module 3742 clock enable</description> 3743 <bitOffset>0</bitOffset> 3744 <bitWidth>1</bitWidth> 3745 <enumeratedValues><name>FSMCEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>The selected clock is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>The selected clock is enabled</description><value>1</value></enumeratedValue></enumeratedValues> 3746 </field> 3747 </fields> 3748 </register> 3749 <register> 3750 <name>APB1ENR</name> 3751 <displayName>APB1ENR</displayName> 3752 <description>APB1 peripheral clock enable 3753 register</description> 3754 <addressOffset>0x40</addressOffset> 3755 <size>0x20</size> 3756 <access>read-write</access> 3757 <resetValue>0x00000000</resetValue> 3758 <fields> 3759 <field> 3760 <name>DACEN</name> 3761 <description>DAC interface clock enable</description> 3762 <bitOffset>29</bitOffset> 3763 <bitWidth>1</bitWidth> 3764 <enumeratedValues derivedFrom="TIM2EN"/> 3765 </field> 3766 <field> 3767 <name>PWREN</name> 3768 <description>Power interface clock 3769 enable</description> 3770 <bitOffset>28</bitOffset> 3771 <bitWidth>1</bitWidth> 3772 <enumeratedValues derivedFrom="TIM2EN"/> 3773 </field> 3774 <field> 3775 <name>CAN2EN</name> 3776 <description>CAN 2 clock enable</description> 3777 <bitOffset>26</bitOffset> 3778 <bitWidth>1</bitWidth> 3779 <enumeratedValues derivedFrom="TIM2EN"/> 3780 </field> 3781 <field> 3782 <name>CAN1EN</name> 3783 <description>CAN 1 clock enable</description> 3784 <bitOffset>25</bitOffset> 3785 <bitWidth>1</bitWidth> 3786 <enumeratedValues derivedFrom="TIM2EN"/> 3787 </field> 3788 <field> 3789 <name>I2C3EN</name> 3790 <description>I2C3 clock enable</description> 3791 <bitOffset>23</bitOffset> 3792 <bitWidth>1</bitWidth> 3793 <enumeratedValues derivedFrom="TIM2EN"/> 3794 </field> 3795 <field> 3796 <name>I2C2EN</name> 3797 <description>I2C2 clock enable</description> 3798 <bitOffset>22</bitOffset> 3799 <bitWidth>1</bitWidth> 3800 <enumeratedValues derivedFrom="TIM2EN"/> 3801 </field> 3802 <field> 3803 <name>I2C1EN</name> 3804 <description>I2C1 clock enable</description> 3805 <bitOffset>21</bitOffset> 3806 <bitWidth>1</bitWidth> 3807 <enumeratedValues derivedFrom="TIM2EN"/> 3808 </field> 3809 <field> 3810 <name>UART5EN</name> 3811 <description>UART5 clock enable</description> 3812 <bitOffset>20</bitOffset> 3813 <bitWidth>1</bitWidth> 3814 <enumeratedValues derivedFrom="TIM2EN"/> 3815 </field> 3816 <field> 3817 <name>UART4EN</name> 3818 <description>UART4 clock enable</description> 3819 <bitOffset>19</bitOffset> 3820 <bitWidth>1</bitWidth> 3821 <enumeratedValues derivedFrom="TIM2EN"/> 3822 </field> 3823 <field> 3824 <name>USART3EN</name> 3825 <description>USART3 clock enable</description> 3826 <bitOffset>18</bitOffset> 3827 <bitWidth>1</bitWidth> 3828 <enumeratedValues derivedFrom="TIM2EN"/> 3829 </field> 3830 <field> 3831 <name>USART2EN</name> 3832 <description>USART 2 clock enable</description> 3833 <bitOffset>17</bitOffset> 3834 <bitWidth>1</bitWidth> 3835 <enumeratedValues derivedFrom="TIM2EN"/> 3836 </field> 3837 <field> 3838 <name>SPI3EN</name> 3839 <description>SPI3 clock enable</description> 3840 <bitOffset>15</bitOffset> 3841 <bitWidth>1</bitWidth> 3842 <enumeratedValues derivedFrom="TIM2EN"/> 3843 </field> 3844 <field> 3845 <name>SPI2EN</name> 3846 <description>SPI2 clock enable</description> 3847 <bitOffset>14</bitOffset> 3848 <bitWidth>1</bitWidth> 3849 <enumeratedValues derivedFrom="TIM2EN"/> 3850 </field> 3851 <field> 3852 <name>WWDGEN</name> 3853 <description>Window watchdog clock 3854 enable</description> 3855 <bitOffset>11</bitOffset> 3856 <bitWidth>1</bitWidth> 3857 <enumeratedValues derivedFrom="TIM2EN"/> 3858 </field> 3859 <field> 3860 <name>TIM14EN</name> 3861 <description>TIM14 clock enable</description> 3862 <bitOffset>8</bitOffset> 3863 <bitWidth>1</bitWidth> 3864 <enumeratedValues derivedFrom="TIM2EN"/> 3865 </field> 3866 <field> 3867 <name>TIM13EN</name> 3868 <description>TIM13 clock enable</description> 3869 <bitOffset>7</bitOffset> 3870 <bitWidth>1</bitWidth> 3871 <enumeratedValues derivedFrom="TIM2EN"/> 3872 </field> 3873 <field> 3874 <name>TIM12EN</name> 3875 <description>TIM12 clock enable</description> 3876 <bitOffset>6</bitOffset> 3877 <bitWidth>1</bitWidth> 3878 <enumeratedValues derivedFrom="TIM2EN"/> 3879 </field> 3880 <field> 3881 <name>TIM7EN</name> 3882 <description>TIM7 clock enable</description> 3883 <bitOffset>5</bitOffset> 3884 <bitWidth>1</bitWidth> 3885 <enumeratedValues derivedFrom="TIM2EN"/> 3886 </field> 3887 <field> 3888 <name>TIM6EN</name> 3889 <description>TIM6 clock enable</description> 3890 <bitOffset>4</bitOffset> 3891 <bitWidth>1</bitWidth> 3892 <enumeratedValues derivedFrom="TIM2EN"/> 3893 </field> 3894 <field> 3895 <name>TIM5EN</name> 3896 <description>TIM5 clock enable</description> 3897 <bitOffset>3</bitOffset> 3898 <bitWidth>1</bitWidth> 3899 <enumeratedValues derivedFrom="TIM2EN"/> 3900 </field> 3901 <field> 3902 <name>TIM4EN</name> 3903 <description>TIM4 clock enable</description> 3904 <bitOffset>2</bitOffset> 3905 <bitWidth>1</bitWidth> 3906 <enumeratedValues derivedFrom="TIM2EN"/> 3907 </field> 3908 <field> 3909 <name>TIM3EN</name> 3910 <description>TIM3 clock enable</description> 3911 <bitOffset>1</bitOffset> 3912 <bitWidth>1</bitWidth> 3913 <enumeratedValues derivedFrom="TIM2EN"/> 3914 </field> 3915 <field> 3916 <name>TIM2EN</name> 3917 <description>TIM2 clock enable</description> 3918 <bitOffset>0</bitOffset> 3919 <bitWidth>1</bitWidth> 3920 <enumeratedValues><name>TIM2EN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>The selected clock is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>The selected clock is enabled</description><value>1</value></enumeratedValue></enumeratedValues> 3921 </field> 3922 </fields> 3923 </register> 3924 <register> 3925 <name>APB2ENR</name> 3926 <displayName>APB2ENR</displayName> 3927 <description>APB2 peripheral clock enable 3928 register</description> 3929 <addressOffset>0x44</addressOffset> 3930 <size>0x20</size> 3931 <access>read-write</access> 3932 <resetValue>0x00000000</resetValue> 3933 <fields> 3934 <field> 3935 <name>TIM11EN</name> 3936 <description>TIM11 clock enable</description> 3937 <bitOffset>18</bitOffset> 3938 <bitWidth>1</bitWidth> 3939 <enumeratedValues derivedFrom="TIM1EN"/> 3940 </field> 3941 <field> 3942 <name>TIM10EN</name> 3943 <description>TIM10 clock enable</description> 3944 <bitOffset>17</bitOffset> 3945 <bitWidth>1</bitWidth> 3946 <enumeratedValues derivedFrom="TIM1EN"/> 3947 </field> 3948 <field> 3949 <name>TIM9EN</name> 3950 <description>TIM9 clock enable</description> 3951 <bitOffset>16</bitOffset> 3952 <bitWidth>1</bitWidth> 3953 <enumeratedValues derivedFrom="TIM1EN"/> 3954 </field> 3955 <field> 3956 <name>SYSCFGEN</name> 3957 <description>System configuration controller clock 3958 enable</description> 3959 <bitOffset>14</bitOffset> 3960 <bitWidth>1</bitWidth> 3961 <enumeratedValues derivedFrom="TIM1EN"/> 3962 </field> 3963 <field> 3964 <name>SPI1EN</name> 3965 <description>SPI1 clock enable</description> 3966 <bitOffset>12</bitOffset> 3967 <bitWidth>1</bitWidth> 3968 <enumeratedValues derivedFrom="TIM1EN"/> 3969 </field> 3970 <field> 3971 <name>SDIOEN</name> 3972 <description>SDIO clock enable</description> 3973 <bitOffset>11</bitOffset> 3974 <bitWidth>1</bitWidth> 3975 <enumeratedValues derivedFrom="TIM1EN"/> 3976 </field> 3977 <field> 3978 <name>ADC3EN</name> 3979 <description>ADC3 clock enable</description> 3980 <bitOffset>10</bitOffset> 3981 <bitWidth>1</bitWidth> 3982 <enumeratedValues derivedFrom="TIM1EN"/> 3983 </field> 3984 <field> 3985 <name>ADC2EN</name> 3986 <description>ADC2 clock enable</description> 3987 <bitOffset>9</bitOffset> 3988 <bitWidth>1</bitWidth> 3989 <enumeratedValues derivedFrom="TIM1EN"/> 3990 </field> 3991 <field> 3992 <name>ADC1EN</name> 3993 <description>ADC1 clock enable</description> 3994 <bitOffset>8</bitOffset> 3995 <bitWidth>1</bitWidth> 3996 <enumeratedValues derivedFrom="TIM1EN"/> 3997 </field> 3998 <field> 3999 <name>USART6EN</name> 4000 <description>USART6 clock enable</description> 4001 <bitOffset>5</bitOffset> 4002 <bitWidth>1</bitWidth> 4003 <enumeratedValues derivedFrom="TIM1EN"/> 4004 </field> 4005 <field> 4006 <name>USART1EN</name> 4007 <description>USART1 clock enable</description> 4008 <bitOffset>4</bitOffset> 4009 <bitWidth>1</bitWidth> 4010 <enumeratedValues derivedFrom="TIM1EN"/> 4011 </field> 4012 <field> 4013 <name>TIM8EN</name> 4014 <description>TIM8 clock enable</description> 4015 <bitOffset>1</bitOffset> 4016 <bitWidth>1</bitWidth> 4017 <enumeratedValues derivedFrom="TIM1EN"/> 4018 </field> 4019 <field> 4020 <name>TIM1EN</name> 4021 <description>TIM1 clock enable</description> 4022 <bitOffset>0</bitOffset> 4023 <bitWidth>1</bitWidth> 4024 <enumeratedValues><name>TIM1EN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>The selected clock is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>The selected clock is enabled</description><value>1</value></enumeratedValue></enumeratedValues> 4025 </field> 4026 </fields> 4027 </register> 4028 <register> 4029 <name>AHB1LPENR</name> 4030 <displayName>AHB1LPENR</displayName> 4031 <description>AHB1 peripheral clock enable in low power 4032 mode register</description> 4033 <addressOffset>0x50</addressOffset> 4034 <size>0x20</size> 4035 <access>read-write</access> 4036 <resetValue>0x7E6791FF</resetValue> 4037 <fields> 4038 <field> 4039 <name>OTGHSULPILPEN</name> 4040 <description>USB OTG HS ULPI clock enable during 4041 Sleep mode</description> 4042 <bitOffset>30</bitOffset> 4043 <bitWidth>1</bitWidth> 4044 <enumeratedValues derivedFrom="GPIOALPEN"/> 4045 </field> 4046 <field> 4047 <name>OTGHSLPEN</name> 4048 <description>USB OTG HS clock enable during Sleep 4049 mode</description> 4050 <bitOffset>29</bitOffset> 4051 <bitWidth>1</bitWidth> 4052 <enumeratedValues derivedFrom="GPIOALPEN"/> 4053 </field> 4054 <field> 4055 <name>ETHMACPTPLPEN</name> 4056 <description>Ethernet PTP clock enable during Sleep 4057 mode</description> 4058 <bitOffset>28</bitOffset> 4059 <bitWidth>1</bitWidth> 4060 <enumeratedValues derivedFrom="GPIOALPEN"/> 4061 </field> 4062 <field> 4063 <name>ETHMACRXLPEN</name> 4064 <description>Ethernet reception clock enable during 4065 Sleep mode</description> 4066 <bitOffset>27</bitOffset> 4067 <bitWidth>1</bitWidth> 4068 <enumeratedValues derivedFrom="GPIOALPEN"/> 4069 </field> 4070 <field> 4071 <name>ETHMACTXLPEN</name> 4072 <description>Ethernet transmission clock enable 4073 during Sleep mode</description> 4074 <bitOffset>26</bitOffset> 4075 <bitWidth>1</bitWidth> 4076 <enumeratedValues derivedFrom="GPIOALPEN"/> 4077 </field> 4078 <field> 4079 <name>ETHMACLPEN</name> 4080 <description>Ethernet MAC clock enable during Sleep 4081 mode</description> 4082 <bitOffset>25</bitOffset> 4083 <bitWidth>1</bitWidth> 4084 <enumeratedValues derivedFrom="GPIOALPEN"/> 4085 </field> 4086 <field> 4087 <name>DMA2LPEN</name> 4088 <description>DMA2 clock enable during Sleep 4089 mode</description> 4090 <bitOffset>22</bitOffset> 4091 <bitWidth>1</bitWidth> 4092 <enumeratedValues derivedFrom="GPIOALPEN"/> 4093 </field> 4094 <field> 4095 <name>DMA1LPEN</name> 4096 <description>DMA1 clock enable during Sleep 4097 mode</description> 4098 <bitOffset>21</bitOffset> 4099 <bitWidth>1</bitWidth> 4100 <enumeratedValues derivedFrom="GPIOALPEN"/> 4101 </field> 4102 <field> 4103 <name>BKPSRAMLPEN</name> 4104 <description>Backup SRAM interface clock enable 4105 during Sleep mode</description> 4106 <bitOffset>18</bitOffset> 4107 <bitWidth>1</bitWidth> 4108 <enumeratedValues derivedFrom="GPIOALPEN"/> 4109 </field> 4110 <field> 4111 <name>SRAM2LPEN</name> 4112 <description>SRAM 2 interface clock enable during 4113 Sleep mode</description> 4114 <bitOffset>17</bitOffset> 4115 <bitWidth>1</bitWidth> 4116 <enumeratedValues derivedFrom="GPIOALPEN"/> 4117 </field> 4118 <field> 4119 <name>SRAM1LPEN</name> 4120 <description>SRAM 1interface clock enable during 4121 Sleep mode</description> 4122 <bitOffset>16</bitOffset> 4123 <bitWidth>1</bitWidth> 4124 <enumeratedValues derivedFrom="GPIOALPEN"/> 4125 </field> 4126 <field> 4127 <name>FLITFLPEN</name> 4128 <description>Flash interface clock enable during 4129 Sleep mode</description> 4130 <bitOffset>15</bitOffset> 4131 <bitWidth>1</bitWidth> 4132 <enumeratedValues derivedFrom="GPIOALPEN"/> 4133 </field> 4134 <field> 4135 <name>CRCLPEN</name> 4136 <description>CRC clock enable during Sleep 4137 mode</description> 4138 <bitOffset>12</bitOffset> 4139 <bitWidth>1</bitWidth> 4140 <enumeratedValues derivedFrom="GPIOALPEN"/> 4141 </field> 4142 <field> 4143 <name>GPIOILPEN</name> 4144 <description>IO port I clock enable during Sleep 4145 mode</description> 4146 <bitOffset>8</bitOffset> 4147 <bitWidth>1</bitWidth> 4148 <enumeratedValues derivedFrom="GPIOALPEN"/> 4149 </field> 4150 <field> 4151 <name>GPIOHLPEN</name> 4152 <description>IO port H clock enable during Sleep 4153 mode</description> 4154 <bitOffset>7</bitOffset> 4155 <bitWidth>1</bitWidth> 4156 <enumeratedValues derivedFrom="GPIOALPEN"/> 4157 </field> 4158 <field> 4159 <name>GPIOGLPEN</name> 4160 <description>IO port G clock enable during Sleep 4161 mode</description> 4162 <bitOffset>6</bitOffset> 4163 <bitWidth>1</bitWidth> 4164 <enumeratedValues derivedFrom="GPIOALPEN"/> 4165 </field> 4166 <field> 4167 <name>GPIOFLPEN</name> 4168 <description>IO port F clock enable during Sleep 4169 mode</description> 4170 <bitOffset>5</bitOffset> 4171 <bitWidth>1</bitWidth> 4172 <enumeratedValues derivedFrom="GPIOALPEN"/> 4173 </field> 4174 <field> 4175 <name>GPIOELPEN</name> 4176 <description>IO port E clock enable during Sleep 4177 mode</description> 4178 <bitOffset>4</bitOffset> 4179 <bitWidth>1</bitWidth> 4180 <enumeratedValues derivedFrom="GPIOALPEN"/> 4181 </field> 4182 <field> 4183 <name>GPIODLPEN</name> 4184 <description>IO port D clock enable during Sleep 4185 mode</description> 4186 <bitOffset>3</bitOffset> 4187 <bitWidth>1</bitWidth> 4188 <enumeratedValues derivedFrom="GPIOALPEN"/> 4189 </field> 4190 <field> 4191 <name>GPIOCLPEN</name> 4192 <description>IO port C clock enable during Sleep 4193 mode</description> 4194 <bitOffset>2</bitOffset> 4195 <bitWidth>1</bitWidth> 4196 <enumeratedValues derivedFrom="GPIOALPEN"/> 4197 </field> 4198 <field> 4199 <name>GPIOBLPEN</name> 4200 <description>IO port B clock enable during Sleep 4201 mode</description> 4202 <bitOffset>1</bitOffset> 4203 <bitWidth>1</bitWidth> 4204 <enumeratedValues derivedFrom="GPIOALPEN"/> 4205 </field> 4206 <field> 4207 <name>GPIOALPEN</name> 4208 <description>IO port A clock enable during sleep 4209 mode</description> 4210 <bitOffset>0</bitOffset> 4211 <bitWidth>1</bitWidth> 4212 <enumeratedValues><name>GPIOALPEN</name><usage>read-write</usage><enumeratedValue><name>DisabledInSleep</name><description>Selected module is disabled during Sleep mode</description><value>0</value></enumeratedValue><enumeratedValue><name>EnabledInSleep</name><description>Selected module is enabled during Sleep mode</description><value>1</value></enumeratedValue></enumeratedValues> 4213 </field> 4214 </fields> 4215 </register> 4216 <register> 4217 <name>AHB2LPENR</name> 4218 <displayName>AHB2LPENR</displayName> 4219 <description>AHB2 peripheral clock enable in low power 4220 mode register</description> 4221 <addressOffset>0x54</addressOffset> 4222 <size>0x20</size> 4223 <access>read-write</access> 4224 <resetValue>0x000000F1</resetValue> 4225 <fields> 4226 <field> 4227 <name>OTGFSLPEN</name> 4228 <description>USB OTG FS clock enable during Sleep 4229 mode</description> 4230 <bitOffset>7</bitOffset> 4231 <bitWidth>1</bitWidth> 4232 <enumeratedValues derivedFrom="DCMILPEN"/> 4233 </field> 4234 <field> 4235 <name>RNGLPEN</name> 4236 <description>Random number generator clock enable 4237 during Sleep mode</description> 4238 <bitOffset>6</bitOffset> 4239 <bitWidth>1</bitWidth> 4240 <enumeratedValues derivedFrom="DCMILPEN"/> 4241 </field> 4242 <field> 4243 <name>DCMILPEN</name> 4244 <description>Camera interface enable during Sleep 4245 mode</description> 4246 <bitOffset>0</bitOffset> 4247 <bitWidth>1</bitWidth> 4248 <enumeratedValues><name>DCMILPEN</name><usage>read-write</usage><enumeratedValue><name>DisabledInSleep</name><description>Selected module is disabled during Sleep mode</description><value>0</value></enumeratedValue><enumeratedValue><name>EnabledInSleep</name><description>Selected module is enabled during Sleep mode</description><value>1</value></enumeratedValue></enumeratedValues> 4249 </field> 4250 </fields> 4251 </register> 4252 <register> 4253 <name>AHB3LPENR</name> 4254 <displayName>AHB3LPENR</displayName> 4255 <description>AHB3 peripheral clock enable in low power 4256 mode register</description> 4257 <addressOffset>0x58</addressOffset> 4258 <size>0x20</size> 4259 <access>read-write</access> 4260 <resetValue>0x00000001</resetValue> 4261 <fields> 4262 <field> 4263 <name>FSMCLPEN</name> 4264 <description>Flexible static memory controller module 4265 clock enable during Sleep mode</description> 4266 <bitOffset>0</bitOffset> 4267 <bitWidth>1</bitWidth> 4268 <enumeratedValues><name>FSMCLPEN</name><usage>read-write</usage><enumeratedValue><name>DisabledInSleep</name><description>Selected module is disabled during Sleep mode</description><value>0</value></enumeratedValue><enumeratedValue><name>EnabledInSleep</name><description>Selected module is enabled during Sleep mode</description><value>1</value></enumeratedValue></enumeratedValues> 4269 </field> 4270 </fields> 4271 </register> 4272 <register> 4273 <name>APB1LPENR</name> 4274 <displayName>APB1LPENR</displayName> 4275 <description>APB1 peripheral clock enable in low power 4276 mode register</description> 4277 <addressOffset>0x60</addressOffset> 4278 <size>0x20</size> 4279 <access>read-write</access> 4280 <resetValue>0x36FEC9FF</resetValue> 4281 <fields> 4282 <field> 4283 <name>DACLPEN</name> 4284 <description>DAC interface clock enable during Sleep 4285 mode</description> 4286 <bitOffset>29</bitOffset> 4287 <bitWidth>1</bitWidth> 4288 <enumeratedValues derivedFrom="TIM2LPEN"/> 4289 </field> 4290 <field> 4291 <name>PWRLPEN</name> 4292 <description>Power interface clock enable during 4293 Sleep mode</description> 4294 <bitOffset>28</bitOffset> 4295 <bitWidth>1</bitWidth> 4296 <enumeratedValues derivedFrom="TIM2LPEN"/> 4297 </field> 4298 <field> 4299 <name>CAN2LPEN</name> 4300 <description>CAN 2 clock enable during Sleep 4301 mode</description> 4302 <bitOffset>26</bitOffset> 4303 <bitWidth>1</bitWidth> 4304 <enumeratedValues derivedFrom="TIM2LPEN"/> 4305 </field> 4306 <field> 4307 <name>CAN1LPEN</name> 4308 <description>CAN 1 clock enable during Sleep 4309 mode</description> 4310 <bitOffset>25</bitOffset> 4311 <bitWidth>1</bitWidth> 4312 <enumeratedValues derivedFrom="TIM2LPEN"/> 4313 </field> 4314 <field> 4315 <name>I2C3LPEN</name> 4316 <description>I2C3 clock enable during Sleep 4317 mode</description> 4318 <bitOffset>23</bitOffset> 4319 <bitWidth>1</bitWidth> 4320 <enumeratedValues derivedFrom="TIM2LPEN"/> 4321 </field> 4322 <field> 4323 <name>I2C2LPEN</name> 4324 <description>I2C2 clock enable during Sleep 4325 mode</description> 4326 <bitOffset>22</bitOffset> 4327 <bitWidth>1</bitWidth> 4328 <enumeratedValues derivedFrom="TIM2LPEN"/> 4329 </field> 4330 <field> 4331 <name>I2C1LPEN</name> 4332 <description>I2C1 clock enable during Sleep 4333 mode</description> 4334 <bitOffset>21</bitOffset> 4335 <bitWidth>1</bitWidth> 4336 <enumeratedValues derivedFrom="TIM2LPEN"/> 4337 </field> 4338 <field> 4339 <name>UART5LPEN</name> 4340 <description>UART5 clock enable during Sleep 4341 mode</description> 4342 <bitOffset>20</bitOffset> 4343 <bitWidth>1</bitWidth> 4344 <enumeratedValues derivedFrom="TIM2LPEN"/> 4345 </field> 4346 <field> 4347 <name>UART4LPEN</name> 4348 <description>UART4 clock enable during Sleep 4349 mode</description> 4350 <bitOffset>19</bitOffset> 4351 <bitWidth>1</bitWidth> 4352 <enumeratedValues derivedFrom="TIM2LPEN"/> 4353 </field> 4354 <field> 4355 <name>USART3LPEN</name> 4356 <description>USART3 clock enable during Sleep 4357 mode</description> 4358 <bitOffset>18</bitOffset> 4359 <bitWidth>1</bitWidth> 4360 <enumeratedValues derivedFrom="TIM2LPEN"/> 4361 </field> 4362 <field> 4363 <name>USART2LPEN</name> 4364 <description>USART2 clock enable during Sleep 4365 mode</description> 4366 <bitOffset>17</bitOffset> 4367 <bitWidth>1</bitWidth> 4368 <enumeratedValues derivedFrom="TIM2LPEN"/> 4369 </field> 4370 <field> 4371 <name>SPI3LPEN</name> 4372 <description>SPI3 clock enable during Sleep 4373 mode</description> 4374 <bitOffset>15</bitOffset> 4375 <bitWidth>1</bitWidth> 4376 <enumeratedValues derivedFrom="TIM2LPEN"/> 4377 </field> 4378 <field> 4379 <name>SPI2LPEN</name> 4380 <description>SPI2 clock enable during Sleep 4381 mode</description> 4382 <bitOffset>14</bitOffset> 4383 <bitWidth>1</bitWidth> 4384 <enumeratedValues derivedFrom="TIM2LPEN"/> 4385 </field> 4386 <field> 4387 <name>WWDGLPEN</name> 4388 <description>Window watchdog clock enable during 4389 Sleep mode</description> 4390 <bitOffset>11</bitOffset> 4391 <bitWidth>1</bitWidth> 4392 <enumeratedValues derivedFrom="TIM2LPEN"/> 4393 </field> 4394 <field> 4395 <name>TIM14LPEN</name> 4396 <description>TIM14 clock enable during Sleep 4397 mode</description> 4398 <bitOffset>8</bitOffset> 4399 <bitWidth>1</bitWidth> 4400 <enumeratedValues derivedFrom="TIM2LPEN"/> 4401 </field> 4402 <field> 4403 <name>TIM13LPEN</name> 4404 <description>TIM13 clock enable during Sleep 4405 mode</description> 4406 <bitOffset>7</bitOffset> 4407 <bitWidth>1</bitWidth> 4408 <enumeratedValues derivedFrom="TIM2LPEN"/> 4409 </field> 4410 <field> 4411 <name>TIM12LPEN</name> 4412 <description>TIM12 clock enable during Sleep 4413 mode</description> 4414 <bitOffset>6</bitOffset> 4415 <bitWidth>1</bitWidth> 4416 <enumeratedValues derivedFrom="TIM2LPEN"/> 4417 </field> 4418 <field> 4419 <name>TIM7LPEN</name> 4420 <description>TIM7 clock enable during Sleep 4421 mode</description> 4422 <bitOffset>5</bitOffset> 4423 <bitWidth>1</bitWidth> 4424 <enumeratedValues derivedFrom="TIM2LPEN"/> 4425 </field> 4426 <field> 4427 <name>TIM6LPEN</name> 4428 <description>TIM6 clock enable during Sleep 4429 mode</description> 4430 <bitOffset>4</bitOffset> 4431 <bitWidth>1</bitWidth> 4432 <enumeratedValues derivedFrom="TIM2LPEN"/> 4433 </field> 4434 <field> 4435 <name>TIM5LPEN</name> 4436 <description>TIM5 clock enable during Sleep 4437 mode</description> 4438 <bitOffset>3</bitOffset> 4439 <bitWidth>1</bitWidth> 4440 <enumeratedValues derivedFrom="TIM2LPEN"/> 4441 </field> 4442 <field> 4443 <name>TIM4LPEN</name> 4444 <description>TIM4 clock enable during Sleep 4445 mode</description> 4446 <bitOffset>2</bitOffset> 4447 <bitWidth>1</bitWidth> 4448 <enumeratedValues derivedFrom="TIM2LPEN"/> 4449 </field> 4450 <field> 4451 <name>TIM3LPEN</name> 4452 <description>TIM3 clock enable during Sleep 4453 mode</description> 4454 <bitOffset>1</bitOffset> 4455 <bitWidth>1</bitWidth> 4456 <enumeratedValues derivedFrom="TIM2LPEN"/> 4457 </field> 4458 <field> 4459 <name>TIM2LPEN</name> 4460 <description>TIM2 clock enable during Sleep 4461 mode</description> 4462 <bitOffset>0</bitOffset> 4463 <bitWidth>1</bitWidth> 4464 <enumeratedValues><name>TIM2LPEN</name><usage>read-write</usage><enumeratedValue><name>DisabledInSleep</name><description>Selected module is disabled during Sleep mode</description><value>0</value></enumeratedValue><enumeratedValue><name>EnabledInSleep</name><description>Selected module is enabled during Sleep mode</description><value>1</value></enumeratedValue></enumeratedValues> 4465 </field> 4466 </fields> 4467 </register> 4468 <register> 4469 <name>APB2LPENR</name> 4470 <displayName>APB2LPENR</displayName> 4471 <description>APB2 peripheral clock enabled in low power 4472 mode register</description> 4473 <addressOffset>0x64</addressOffset> 4474 <size>0x20</size> 4475 <access>read-write</access> 4476 <resetValue>0x00075F33</resetValue> 4477 <fields> 4478 <field> 4479 <name>TIM11LPEN</name> 4480 <description>TIM11 clock enable during Sleep 4481 mode</description> 4482 <bitOffset>18</bitOffset> 4483 <bitWidth>1</bitWidth> 4484 <enumeratedValues derivedFrom="TIM1LPEN"/> 4485 </field> 4486 <field> 4487 <name>TIM10LPEN</name> 4488 <description>TIM10 clock enable during Sleep 4489 mode</description> 4490 <bitOffset>17</bitOffset> 4491 <bitWidth>1</bitWidth> 4492 <enumeratedValues derivedFrom="TIM1LPEN"/> 4493 </field> 4494 <field> 4495 <name>TIM9LPEN</name> 4496 <description>TIM9 clock enable during sleep 4497 mode</description> 4498 <bitOffset>16</bitOffset> 4499 <bitWidth>1</bitWidth> 4500 <enumeratedValues derivedFrom="TIM1LPEN"/> 4501 </field> 4502 <field> 4503 <name>SYSCFGLPEN</name> 4504 <description>System configuration controller clock 4505 enable during Sleep mode</description> 4506 <bitOffset>14</bitOffset> 4507 <bitWidth>1</bitWidth> 4508 <enumeratedValues derivedFrom="TIM1LPEN"/> 4509 </field> 4510 <field> 4511 <name>SPI1LPEN</name> 4512 <description>SPI 1 clock enable during Sleep 4513 mode</description> 4514 <bitOffset>12</bitOffset> 4515 <bitWidth>1</bitWidth> 4516 <enumeratedValues derivedFrom="TIM1LPEN"/> 4517 </field> 4518 <field> 4519 <name>SDIOLPEN</name> 4520 <description>SDIO clock enable during Sleep 4521 mode</description> 4522 <bitOffset>11</bitOffset> 4523 <bitWidth>1</bitWidth> 4524 <enumeratedValues derivedFrom="TIM1LPEN"/> 4525 </field> 4526 <field> 4527 <name>ADC3LPEN</name> 4528 <description>ADC 3 clock enable during Sleep 4529 mode</description> 4530 <bitOffset>10</bitOffset> 4531 <bitWidth>1</bitWidth> 4532 <enumeratedValues derivedFrom="TIM1LPEN"/> 4533 </field> 4534 <field> 4535 <name>ADC2LPEN</name> 4536 <description>ADC2 clock enable during Sleep 4537 mode</description> 4538 <bitOffset>9</bitOffset> 4539 <bitWidth>1</bitWidth> 4540 <enumeratedValues derivedFrom="TIM1LPEN"/> 4541 </field> 4542 <field> 4543 <name>ADC1LPEN</name> 4544 <description>ADC1 clock enable during Sleep 4545 mode</description> 4546 <bitOffset>8</bitOffset> 4547 <bitWidth>1</bitWidth> 4548 <enumeratedValues derivedFrom="TIM1LPEN"/> 4549 </field> 4550 <field> 4551 <name>USART6LPEN</name> 4552 <description>USART6 clock enable during Sleep 4553 mode</description> 4554 <bitOffset>5</bitOffset> 4555 <bitWidth>1</bitWidth> 4556 <enumeratedValues derivedFrom="TIM1LPEN"/> 4557 </field> 4558 <field> 4559 <name>USART1LPEN</name> 4560 <description>USART1 clock enable during Sleep 4561 mode</description> 4562 <bitOffset>4</bitOffset> 4563 <bitWidth>1</bitWidth> 4564 <enumeratedValues derivedFrom="TIM1LPEN"/> 4565 </field> 4566 <field> 4567 <name>TIM8LPEN</name> 4568 <description>TIM8 clock enable during Sleep 4569 mode</description> 4570 <bitOffset>1</bitOffset> 4571 <bitWidth>1</bitWidth> 4572 <enumeratedValues derivedFrom="TIM1LPEN"/> 4573 </field> 4574 <field> 4575 <name>TIM1LPEN</name> 4576 <description>TIM1 clock enable during Sleep 4577 mode</description> 4578 <bitOffset>0</bitOffset> 4579 <bitWidth>1</bitWidth> 4580 <enumeratedValues><name>TIM1LPEN</name><usage>read-write</usage><enumeratedValue><name>DisabledInSleep</name><description>Selected module is disabled during Sleep mode</description><value>0</value></enumeratedValue><enumeratedValue><name>EnabledInSleep</name><description>Selected module is enabled during Sleep mode</description><value>1</value></enumeratedValue></enumeratedValues> 4581 </field> 4582 </fields> 4583 </register> 4584 <register> 4585 <name>BDCR</name> 4586 <displayName>BDCR</displayName> 4587 <description>Backup domain control register</description> 4588 <addressOffset>0x70</addressOffset> 4589 <size>0x20</size> 4590 <resetValue>0x00000000</resetValue> 4591 <fields> 4592 <field> 4593 <name>BDRST</name> 4594 <description>Backup domain software 4595 reset</description> 4596 <bitOffset>16</bitOffset> 4597 <bitWidth>1</bitWidth> 4598 <access>read-write</access> 4599 <enumeratedValues><name>BDRST</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Reset not activated</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Reset the entire RTC domain</description><value>1</value></enumeratedValue></enumeratedValues> 4600 </field> 4601 <field> 4602 <name>RTCEN</name> 4603 <description>RTC clock enable</description> 4604 <bitOffset>15</bitOffset> 4605 <bitWidth>1</bitWidth> 4606 <access>read-write</access> 4607 <enumeratedValues><name>RTCEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>RTC clock disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>RTC clock enabled</description><value>1</value></enumeratedValue></enumeratedValues> 4608 </field> 4609 <field> 4610 <name>LSEBYP</name> 4611 <description>External low-speed oscillator 4612 bypass</description> 4613 <bitOffset>2</bitOffset> 4614 <bitWidth>1</bitWidth> 4615 <access>read-write</access> 4616 <enumeratedValues><name>LSEBYP</name><usage>read-write</usage><enumeratedValue><name>NotBypassed</name><description>LSE crystal oscillator not bypassed</description><value>0</value></enumeratedValue><enumeratedValue><name>Bypassed</name><description>LSE crystal oscillator bypassed with external clock</description><value>1</value></enumeratedValue></enumeratedValues> 4617 </field> 4618 <field> 4619 <name>LSERDY</name> 4620 <description>External low-speed oscillator 4621 ready</description> 4622 <bitOffset>1</bitOffset> 4623 <bitWidth>1</bitWidth> 4624 <access>read-only</access> 4625 <enumeratedValues><name>LSERDYR</name><usage>read</usage><enumeratedValue><name>NotReady</name><description>LSE oscillator not ready</description><value>0</value></enumeratedValue><enumeratedValue><name>Ready</name><description>LSE oscillator ready</description><value>1</value></enumeratedValue></enumeratedValues> 4626 </field> 4627 <field> 4628 <name>LSEON</name> 4629 <description>External low-speed oscillator 4630 enable</description> 4631 <bitOffset>0</bitOffset> 4632 <bitWidth>1</bitWidth> 4633 <access>read-write</access> 4634 <enumeratedValues><name>LSEON</name><usage>read-write</usage><enumeratedValue><name>Off</name><description>LSE oscillator Off</description><value>0</value></enumeratedValue><enumeratedValue><name>On</name><description>LSE oscillator On</description><value>1</value></enumeratedValue></enumeratedValues> 4635 </field> 4636 <field><name>RTCSEL</name><description>RTC clock source selection</description><bitOffset>8</bitOffset><bitWidth>2</bitWidth><enumeratedValues><name>RTCSEL</name><usage>read-write</usage><enumeratedValue><name>NoClock</name><description>No clock</description><value>0</value></enumeratedValue><enumeratedValue><name>LSE</name><description>LSE oscillator clock used as RTC clock</description><value>1</value></enumeratedValue><enumeratedValue><name>LSI</name><description>LSI oscillator clock used as RTC clock</description><value>2</value></enumeratedValue><enumeratedValue><name>HSE</name><description>HSE oscillator clock divided by a prescaler used as RTC clock</description><value>3</value></enumeratedValue></enumeratedValues> 4637 </field></fields> 4638 </register> 4639 <register> 4640 <name>CSR</name> 4641 <displayName>CSR</displayName> 4642 <description>clock control & status 4643 register</description> 4644 <addressOffset>0x74</addressOffset> 4645 <size>0x20</size> 4646 <resetValue>0x0E000000</resetValue> 4647 <fields> 4648 <field> 4649 <name>LPWRRSTF</name> 4650 <description>Low-power reset flag</description> 4651 <bitOffset>31</bitOffset> 4652 <bitWidth>1</bitWidth> 4653 <access>read-write</access> 4654 <enumeratedValues derivedFrom="BORRSTFR"/> 4655 </field> 4656 <field> 4657 <name>WWDGRSTF</name> 4658 <description>Window watchdog reset flag</description> 4659 <bitOffset>30</bitOffset> 4660 <bitWidth>1</bitWidth> 4661 <access>read-write</access> 4662 <enumeratedValues derivedFrom="BORRSTFR"/> 4663 </field> 4664 <field> 4665 <name>WDGRSTF</name> 4666 <description>Independent watchdog reset 4667 flag</description> 4668 <bitOffset>29</bitOffset> 4669 <bitWidth>1</bitWidth> 4670 <access>read-write</access> 4671 <enumeratedValues derivedFrom="BORRSTFR"/> 4672 </field> 4673 <field> 4674 <name>SFTRSTF</name> 4675 <description>Software reset flag</description> 4676 <bitOffset>28</bitOffset> 4677 <bitWidth>1</bitWidth> 4678 <access>read-write</access> 4679 <enumeratedValues derivedFrom="BORRSTFR"/> 4680 </field> 4681 <field> 4682 <name>PORRSTF</name> 4683 <description>POR/PDR reset flag</description> 4684 <bitOffset>27</bitOffset> 4685 <bitWidth>1</bitWidth> 4686 <access>read-write</access> 4687 <enumeratedValues derivedFrom="BORRSTFR"/> 4688 </field> 4689 <field> 4690 <name>PADRSTF</name> 4691 <description>PIN reset flag</description> 4692 <bitOffset>26</bitOffset> 4693 <bitWidth>1</bitWidth> 4694 <access>read-write</access> 4695 <enumeratedValues derivedFrom="BORRSTFR"/> 4696 </field> 4697 <field> 4698 <name>BORRSTF</name> 4699 <description>BOR reset flag</description> 4700 <bitOffset>25</bitOffset> 4701 <bitWidth>1</bitWidth> 4702 <access>read-write</access> 4703 <enumeratedValues><name>BORRSTFR</name><usage>read</usage><enumeratedValue><name>NoReset</name><description>No reset has occured</description><value>0</value></enumeratedValue><enumeratedValue><name>Reset</name><description>A reset has occured</description><value>1</value></enumeratedValue></enumeratedValues> 4704 </field> 4705 <field> 4706 <name>RMVF</name> 4707 <description>Remove reset flag</description> 4708 <bitOffset>24</bitOffset> 4709 <bitWidth>1</bitWidth> 4710 <access>read-write</access> 4711 <enumeratedValues><name>RMVFW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clears the reset flag</description><value>1</value></enumeratedValue></enumeratedValues> 4712 </field> 4713 <field> 4714 <name>LSIRDY</name> 4715 <description>Internal low-speed oscillator 4716 ready</description> 4717 <bitOffset>1</bitOffset> 4718 <bitWidth>1</bitWidth> 4719 <access>read-only</access> 4720 <enumeratedValues><name>LSIRDYR</name><usage>read</usage><enumeratedValue><name>NotReady</name><description>LSI oscillator not ready</description><value>0</value></enumeratedValue><enumeratedValue><name>Ready</name><description>LSI oscillator ready</description><value>1</value></enumeratedValue></enumeratedValues> 4721 </field> 4722 <field> 4723 <name>LSION</name> 4724 <description>Internal low-speed oscillator 4725 enable</description> 4726 <bitOffset>0</bitOffset> 4727 <bitWidth>1</bitWidth> 4728 <access>read-write</access> 4729 <enumeratedValues><name>LSION</name><usage>read-write</usage><enumeratedValue><name>Off</name><description>LSI oscillator Off</description><value>0</value></enumeratedValue><enumeratedValue><name>On</name><description>LSI oscillator On</description><value>1</value></enumeratedValue></enumeratedValues> 4730 </field> 4731 </fields> 4732 </register> 4733 <register> 4734 <name>SSCGR</name> 4735 <displayName>SSCGR</displayName> 4736 <description>spread spectrum clock generation 4737 register</description> 4738 <addressOffset>0x80</addressOffset> 4739 <size>0x20</size> 4740 <access>read-write</access> 4741 <resetValue>0x00000000</resetValue> 4742 <fields> 4743 <field> 4744 <name>SSCGEN</name> 4745 <description>Spread spectrum modulation 4746 enable</description> 4747 <bitOffset>31</bitOffset> 4748 <bitWidth>1</bitWidth> 4749 <enumeratedValues><name>SSCGEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Spread spectrum modulation disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Spread spectrum modulation enabled</description><value>1</value></enumeratedValue></enumeratedValues> 4750 </field> 4751 <field> 4752 <name>SPREADSEL</name> 4753 <description>Spread Select</description> 4754 <bitOffset>30</bitOffset> 4755 <bitWidth>1</bitWidth> 4756 <enumeratedValues><name>SPREADSEL</name><usage>read-write</usage><enumeratedValue><name>Center</name><description>Center spread</description><value>0</value></enumeratedValue><enumeratedValue><name>Down</name><description>Down spread</description><value>1</value></enumeratedValue></enumeratedValues> 4757 </field> 4758 <field> 4759 <name>INCSTEP</name> 4760 <description>Incrementation step</description> 4761 <bitOffset>13</bitOffset> 4762 <bitWidth>15</bitWidth> 4763 <writeConstraint><range><minimum>0</minimum><maximum>32767</maximum></range></writeConstraint> 4764 </field> 4765 <field> 4766 <name>MODPER</name> 4767 <description>Modulation period</description> 4768 <bitOffset>0</bitOffset> 4769 <bitWidth>13</bitWidth> 4770 <writeConstraint><range><minimum>0</minimum><maximum>8191</maximum></range></writeConstraint> 4771 </field> 4772 </fields> 4773 </register> 4774 <register> 4775 <name>PLLI2SCFGR</name> 4776 <displayName>PLLI2SCFGR</displayName> 4777 <description>PLLI2S configuration register</description> 4778 <addressOffset>0x84</addressOffset> 4779 <size>0x20</size> 4780 <access>read-write</access> 4781 <resetValue>0x20003000</resetValue> 4782 <fields> 4783 <field> 4784 <name>PLLI2SR</name> 4785 <description>PLLI2S division factor for I2S 4786 clocks</description> 4787 <bitOffset>28</bitOffset> 4788 <bitWidth>3</bitWidth> 4789 <writeConstraint><range><minimum>2</minimum><maximum>7</maximum></range></writeConstraint> 4790 </field> 4791 <field> 4792 <name>PLLI2SN</name> 4793 <description>PLLI2S multiplication factor for 4794 VCO</description> 4795 <bitOffset>6</bitOffset> 4796 <bitWidth>9</bitWidth> 4797 <writeConstraint><range><minimum>50</minimum><maximum>432</maximum></range></writeConstraint> 4798 </field> 4799 </fields> 4800 </register> 4801 </registers> 4802 </peripheral> 4803 <peripheral> 4804 <name>GPIOI</name> 4805 <description>General-purpose I/Os</description> 4806 <groupName>GPIO</groupName> 4807 <baseAddress>0x40022000</baseAddress> 4808 <addressBlock> 4809 <offset>0x0</offset> 4810 <size>0x400</size> 4811 <usage>registers</usage> 4812 </addressBlock> 4813 <registers> 4814 <register> 4815 <name>MODER</name> 4816 <displayName>MODER</displayName> 4817 <description>GPIO port mode register</description> 4818 <addressOffset>0x0</addressOffset> 4819 <size>0x20</size> 4820 <access>read-write</access> 4821 <resetValue>0x00000000</resetValue> 4822 <fields> 4823 <field> 4824 <name>MODER15</name> 4825 <description>Port x configuration bits (y = 4826 0..15)</description> 4827 <bitOffset>30</bitOffset> 4828 <bitWidth>2</bitWidth> 4829 <enumeratedValues derivedFrom="MODER0"/> 4830 </field> 4831 <field> 4832 <name>MODER14</name> 4833 <description>Port x configuration bits (y = 4834 0..15)</description> 4835 <bitOffset>28</bitOffset> 4836 <bitWidth>2</bitWidth> 4837 <enumeratedValues derivedFrom="MODER0"/> 4838 </field> 4839 <field> 4840 <name>MODER13</name> 4841 <description>Port x configuration bits (y = 4842 0..15)</description> 4843 <bitOffset>26</bitOffset> 4844 <bitWidth>2</bitWidth> 4845 <enumeratedValues derivedFrom="MODER0"/> 4846 </field> 4847 <field> 4848 <name>MODER12</name> 4849 <description>Port x configuration bits (y = 4850 0..15)</description> 4851 <bitOffset>24</bitOffset> 4852 <bitWidth>2</bitWidth> 4853 <enumeratedValues derivedFrom="MODER0"/> 4854 </field> 4855 <field> 4856 <name>MODER11</name> 4857 <description>Port x configuration bits (y = 4858 0..15)</description> 4859 <bitOffset>22</bitOffset> 4860 <bitWidth>2</bitWidth> 4861 <enumeratedValues derivedFrom="MODER0"/> 4862 </field> 4863 <field> 4864 <name>MODER10</name> 4865 <description>Port x configuration bits (y = 4866 0..15)</description> 4867 <bitOffset>20</bitOffset> 4868 <bitWidth>2</bitWidth> 4869 <enumeratedValues derivedFrom="MODER0"/> 4870 </field> 4871 <field> 4872 <name>MODER9</name> 4873 <description>Port x configuration bits (y = 4874 0..15)</description> 4875 <bitOffset>18</bitOffset> 4876 <bitWidth>2</bitWidth> 4877 <enumeratedValues derivedFrom="MODER0"/> 4878 </field> 4879 <field> 4880 <name>MODER8</name> 4881 <description>Port x configuration bits (y = 4882 0..15)</description> 4883 <bitOffset>16</bitOffset> 4884 <bitWidth>2</bitWidth> 4885 <enumeratedValues derivedFrom="MODER0"/> 4886 </field> 4887 <field> 4888 <name>MODER7</name> 4889 <description>Port x configuration bits (y = 4890 0..15)</description> 4891 <bitOffset>14</bitOffset> 4892 <bitWidth>2</bitWidth> 4893 <enumeratedValues derivedFrom="MODER0"/> 4894 </field> 4895 <field> 4896 <name>MODER6</name> 4897 <description>Port x configuration bits (y = 4898 0..15)</description> 4899 <bitOffset>12</bitOffset> 4900 <bitWidth>2</bitWidth> 4901 <enumeratedValues derivedFrom="MODER0"/> 4902 </field> 4903 <field> 4904 <name>MODER5</name> 4905 <description>Port x configuration bits (y = 4906 0..15)</description> 4907 <bitOffset>10</bitOffset> 4908 <bitWidth>2</bitWidth> 4909 <enumeratedValues derivedFrom="MODER0"/> 4910 </field> 4911 <field> 4912 <name>MODER4</name> 4913 <description>Port x configuration bits (y = 4914 0..15)</description> 4915 <bitOffset>8</bitOffset> 4916 <bitWidth>2</bitWidth> 4917 <enumeratedValues derivedFrom="MODER0"/> 4918 </field> 4919 <field> 4920 <name>MODER3</name> 4921 <description>Port x configuration bits (y = 4922 0..15)</description> 4923 <bitOffset>6</bitOffset> 4924 <bitWidth>2</bitWidth> 4925 <enumeratedValues derivedFrom="MODER0"/> 4926 </field> 4927 <field> 4928 <name>MODER2</name> 4929 <description>Port x configuration bits (y = 4930 0..15)</description> 4931 <bitOffset>4</bitOffset> 4932 <bitWidth>2</bitWidth> 4933 <enumeratedValues derivedFrom="MODER0"/> 4934 </field> 4935 <field> 4936 <name>MODER1</name> 4937 <description>Port x configuration bits (y = 4938 0..15)</description> 4939 <bitOffset>2</bitOffset> 4940 <bitWidth>2</bitWidth> 4941 <enumeratedValues derivedFrom="MODER0"/> 4942 </field> 4943 <field> 4944 <name>MODER0</name> 4945 <description>Port x configuration bits (y = 4946 0..15)</description> 4947 <bitOffset>0</bitOffset> 4948 <bitWidth>2</bitWidth> 4949 <enumeratedValues><name>MODER0</name><usage>read-write</usage><enumeratedValue><name>Input</name><description>Input mode (reset state)</description><value>0</value></enumeratedValue><enumeratedValue><name>Output</name><description>General purpose output mode</description><value>1</value></enumeratedValue><enumeratedValue><name>Alternate</name><description>Alternate function mode</description><value>2</value></enumeratedValue><enumeratedValue><name>Analog</name><description>Analog mode</description><value>3</value></enumeratedValue></enumeratedValues> 4950 </field> 4951 </fields> 4952 </register> 4953 <register> 4954 <name>OTYPER</name> 4955 <displayName>OTYPER</displayName> 4956 <description>GPIO port output type register</description> 4957 <addressOffset>0x4</addressOffset> 4958 <size>0x20</size> 4959 <access>read-write</access> 4960 <resetValue>0x00000000</resetValue> 4961 <fields> 4962 <field> 4963 <name>OT15</name> 4964 <description>Port x configuration bits (y = 4965 0..15)</description> 4966 <bitOffset>15</bitOffset> 4967 <bitWidth>1</bitWidth> 4968 <enumeratedValues derivedFrom="OT0"/> 4969 </field> 4970 <field> 4971 <name>OT14</name> 4972 <description>Port x configuration bits (y = 4973 0..15)</description> 4974 <bitOffset>14</bitOffset> 4975 <bitWidth>1</bitWidth> 4976 <enumeratedValues derivedFrom="OT0"/> 4977 </field> 4978 <field> 4979 <name>OT13</name> 4980 <description>Port x configuration bits (y = 4981 0..15)</description> 4982 <bitOffset>13</bitOffset> 4983 <bitWidth>1</bitWidth> 4984 <enumeratedValues derivedFrom="OT0"/> 4985 </field> 4986 <field> 4987 <name>OT12</name> 4988 <description>Port x configuration bits (y = 4989 0..15)</description> 4990 <bitOffset>12</bitOffset> 4991 <bitWidth>1</bitWidth> 4992 <enumeratedValues derivedFrom="OT0"/> 4993 </field> 4994 <field> 4995 <name>OT11</name> 4996 <description>Port x configuration bits (y = 4997 0..15)</description> 4998 <bitOffset>11</bitOffset> 4999 <bitWidth>1</bitWidth> 5000 <enumeratedValues derivedFrom="OT0"/> 5001 </field> 5002 <field> 5003 <name>OT10</name> 5004 <description>Port x configuration bits (y = 5005 0..15)</description> 5006 <bitOffset>10</bitOffset> 5007 <bitWidth>1</bitWidth> 5008 <enumeratedValues derivedFrom="OT0"/> 5009 </field> 5010 <field> 5011 <name>OT9</name> 5012 <description>Port x configuration bits (y = 5013 0..15)</description> 5014 <bitOffset>9</bitOffset> 5015 <bitWidth>1</bitWidth> 5016 <enumeratedValues derivedFrom="OT0"/> 5017 </field> 5018 <field> 5019 <name>OT8</name> 5020 <description>Port x configuration bits (y = 5021 0..15)</description> 5022 <bitOffset>8</bitOffset> 5023 <bitWidth>1</bitWidth> 5024 <enumeratedValues derivedFrom="OT0"/> 5025 </field> 5026 <field> 5027 <name>OT7</name> 5028 <description>Port x configuration bits (y = 5029 0..15)</description> 5030 <bitOffset>7</bitOffset> 5031 <bitWidth>1</bitWidth> 5032 <enumeratedValues derivedFrom="OT0"/> 5033 </field> 5034 <field> 5035 <name>OT6</name> 5036 <description>Port x configuration bits (y = 5037 0..15)</description> 5038 <bitOffset>6</bitOffset> 5039 <bitWidth>1</bitWidth> 5040 <enumeratedValues derivedFrom="OT0"/> 5041 </field> 5042 <field> 5043 <name>OT5</name> 5044 <description>Port x configuration bits (y = 5045 0..15)</description> 5046 <bitOffset>5</bitOffset> 5047 <bitWidth>1</bitWidth> 5048 <enumeratedValues derivedFrom="OT0"/> 5049 </field> 5050 <field> 5051 <name>OT4</name> 5052 <description>Port x configuration bits (y = 5053 0..15)</description> 5054 <bitOffset>4</bitOffset> 5055 <bitWidth>1</bitWidth> 5056 <enumeratedValues derivedFrom="OT0"/> 5057 </field> 5058 <field> 5059 <name>OT3</name> 5060 <description>Port x configuration bits (y = 5061 0..15)</description> 5062 <bitOffset>3</bitOffset> 5063 <bitWidth>1</bitWidth> 5064 <enumeratedValues derivedFrom="OT0"/> 5065 </field> 5066 <field> 5067 <name>OT2</name> 5068 <description>Port x configuration bits (y = 5069 0..15)</description> 5070 <bitOffset>2</bitOffset> 5071 <bitWidth>1</bitWidth> 5072 <enumeratedValues derivedFrom="OT0"/> 5073 </field> 5074 <field> 5075 <name>OT1</name> 5076 <description>Port x configuration bits (y = 5077 0..15)</description> 5078 <bitOffset>1</bitOffset> 5079 <bitWidth>1</bitWidth> 5080 <enumeratedValues derivedFrom="OT0"/> 5081 </field> 5082 <field> 5083 <name>OT0</name> 5084 <description>Port x configuration bits (y = 5085 0..15)</description> 5086 <bitOffset>0</bitOffset> 5087 <bitWidth>1</bitWidth> 5088 <enumeratedValues><name>OT0</name><usage>read-write</usage><enumeratedValue><name>PushPull</name><description>Output push-pull (reset state)</description><value>0</value></enumeratedValue><enumeratedValue><name>OpenDrain</name><description>Output open-drain</description><value>1</value></enumeratedValue></enumeratedValues> 5089 </field> 5090 </fields> 5091 </register> 5092 <register> 5093 <name>OSPEEDR</name> 5094 <displayName>OSPEEDR</displayName> 5095 <description>GPIO port output speed 5096 register</description> 5097 <addressOffset>0x8</addressOffset> 5098 <size>0x20</size> 5099 <access>read-write</access> 5100 <resetValue>0x00000000</resetValue> 5101 <fields> 5102 <field> 5103 <name>OSPEEDR15</name> 5104 <description>Port x configuration bits (y = 5105 0..15)</description> 5106 <bitOffset>30</bitOffset> 5107 <bitWidth>2</bitWidth> 5108 <enumeratedValues derivedFrom="OSPEEDR0"/> 5109 </field> 5110 <field> 5111 <name>OSPEEDR14</name> 5112 <description>Port x configuration bits (y = 5113 0..15)</description> 5114 <bitOffset>28</bitOffset> 5115 <bitWidth>2</bitWidth> 5116 <enumeratedValues derivedFrom="OSPEEDR0"/> 5117 </field> 5118 <field> 5119 <name>OSPEEDR13</name> 5120 <description>Port x configuration bits (y = 5121 0..15)</description> 5122 <bitOffset>26</bitOffset> 5123 <bitWidth>2</bitWidth> 5124 <enumeratedValues derivedFrom="OSPEEDR0"/> 5125 </field> 5126 <field> 5127 <name>OSPEEDR12</name> 5128 <description>Port x configuration bits (y = 5129 0..15)</description> 5130 <bitOffset>24</bitOffset> 5131 <bitWidth>2</bitWidth> 5132 <enumeratedValues derivedFrom="OSPEEDR0"/> 5133 </field> 5134 <field> 5135 <name>OSPEEDR11</name> 5136 <description>Port x configuration bits (y = 5137 0..15)</description> 5138 <bitOffset>22</bitOffset> 5139 <bitWidth>2</bitWidth> 5140 <enumeratedValues derivedFrom="OSPEEDR0"/> 5141 </field> 5142 <field> 5143 <name>OSPEEDR10</name> 5144 <description>Port x configuration bits (y = 5145 0..15)</description> 5146 <bitOffset>20</bitOffset> 5147 <bitWidth>2</bitWidth> 5148 <enumeratedValues derivedFrom="OSPEEDR0"/> 5149 </field> 5150 <field> 5151 <name>OSPEEDR9</name> 5152 <description>Port x configuration bits (y = 5153 0..15)</description> 5154 <bitOffset>18</bitOffset> 5155 <bitWidth>2</bitWidth> 5156 <enumeratedValues derivedFrom="OSPEEDR0"/> 5157 </field> 5158 <field> 5159 <name>OSPEEDR8</name> 5160 <description>Port x configuration bits (y = 5161 0..15)</description> 5162 <bitOffset>16</bitOffset> 5163 <bitWidth>2</bitWidth> 5164 <enumeratedValues derivedFrom="OSPEEDR0"/> 5165 </field> 5166 <field> 5167 <name>OSPEEDR7</name> 5168 <description>Port x configuration bits (y = 5169 0..15)</description> 5170 <bitOffset>14</bitOffset> 5171 <bitWidth>2</bitWidth> 5172 <enumeratedValues derivedFrom="OSPEEDR0"/> 5173 </field> 5174 <field> 5175 <name>OSPEEDR6</name> 5176 <description>Port x configuration bits (y = 5177 0..15)</description> 5178 <bitOffset>12</bitOffset> 5179 <bitWidth>2</bitWidth> 5180 <enumeratedValues derivedFrom="OSPEEDR0"/> 5181 </field> 5182 <field> 5183 <name>OSPEEDR5</name> 5184 <description>Port x configuration bits (y = 5185 0..15)</description> 5186 <bitOffset>10</bitOffset> 5187 <bitWidth>2</bitWidth> 5188 <enumeratedValues derivedFrom="OSPEEDR0"/> 5189 </field> 5190 <field> 5191 <name>OSPEEDR4</name> 5192 <description>Port x configuration bits (y = 5193 0..15)</description> 5194 <bitOffset>8</bitOffset> 5195 <bitWidth>2</bitWidth> 5196 <enumeratedValues derivedFrom="OSPEEDR0"/> 5197 </field> 5198 <field> 5199 <name>OSPEEDR3</name> 5200 <description>Port x configuration bits (y = 5201 0..15)</description> 5202 <bitOffset>6</bitOffset> 5203 <bitWidth>2</bitWidth> 5204 <enumeratedValues derivedFrom="OSPEEDR0"/> 5205 </field> 5206 <field> 5207 <name>OSPEEDR2</name> 5208 <description>Port x configuration bits (y = 5209 0..15)</description> 5210 <bitOffset>4</bitOffset> 5211 <bitWidth>2</bitWidth> 5212 <enumeratedValues derivedFrom="OSPEEDR0"/> 5213 </field> 5214 <field> 5215 <name>OSPEEDR1</name> 5216 <description>Port x configuration bits (y = 5217 0..15)</description> 5218 <bitOffset>2</bitOffset> 5219 <bitWidth>2</bitWidth> 5220 <enumeratedValues derivedFrom="OSPEEDR0"/> 5221 </field> 5222 <field> 5223 <name>OSPEEDR0</name> 5224 <description>Port x configuration bits (y = 5225 0..15)</description> 5226 <bitOffset>0</bitOffset> 5227 <bitWidth>2</bitWidth> 5228 <enumeratedValues><name>OSPEEDR0</name><usage>read-write</usage><enumeratedValue><name>LowSpeed</name><description>Low speed</description><value>0</value></enumeratedValue><enumeratedValue><name>MediumSpeed</name><description>Medium speed</description><value>1</value></enumeratedValue><enumeratedValue><name>HighSpeed</name><description>High speed</description><value>2</value></enumeratedValue><enumeratedValue><name>VeryHighSpeed</name><description>Very high speed</description><value>3</value></enumeratedValue></enumeratedValues> 5229 </field> 5230 </fields> 5231 </register> 5232 <register> 5233 <name>PUPDR</name> 5234 <displayName>PUPDR</displayName> 5235 <description>GPIO port pull-up/pull-down 5236 register</description> 5237 <addressOffset>0xC</addressOffset> 5238 <size>0x20</size> 5239 <access>read-write</access> 5240 <resetValue>0x00000000</resetValue> 5241 <fields> 5242 <field> 5243 <name>PUPDR15</name> 5244 <description>Port x configuration bits (y = 5245 0..15)</description> 5246 <bitOffset>30</bitOffset> 5247 <bitWidth>2</bitWidth> 5248 <enumeratedValues derivedFrom="PUPDR0"/> 5249 </field> 5250 <field> 5251 <name>PUPDR14</name> 5252 <description>Port x configuration bits (y = 5253 0..15)</description> 5254 <bitOffset>28</bitOffset> 5255 <bitWidth>2</bitWidth> 5256 <enumeratedValues derivedFrom="PUPDR0"/> 5257 </field> 5258 <field> 5259 <name>PUPDR13</name> 5260 <description>Port x configuration bits (y = 5261 0..15)</description> 5262 <bitOffset>26</bitOffset> 5263 <bitWidth>2</bitWidth> 5264 <enumeratedValues derivedFrom="PUPDR0"/> 5265 </field> 5266 <field> 5267 <name>PUPDR12</name> 5268 <description>Port x configuration bits (y = 5269 0..15)</description> 5270 <bitOffset>24</bitOffset> 5271 <bitWidth>2</bitWidth> 5272 <enumeratedValues derivedFrom="PUPDR0"/> 5273 </field> 5274 <field> 5275 <name>PUPDR11</name> 5276 <description>Port x configuration bits (y = 5277 0..15)</description> 5278 <bitOffset>22</bitOffset> 5279 <bitWidth>2</bitWidth> 5280 <enumeratedValues derivedFrom="PUPDR0"/> 5281 </field> 5282 <field> 5283 <name>PUPDR10</name> 5284 <description>Port x configuration bits (y = 5285 0..15)</description> 5286 <bitOffset>20</bitOffset> 5287 <bitWidth>2</bitWidth> 5288 <enumeratedValues derivedFrom="PUPDR0"/> 5289 </field> 5290 <field> 5291 <name>PUPDR9</name> 5292 <description>Port x configuration bits (y = 5293 0..15)</description> 5294 <bitOffset>18</bitOffset> 5295 <bitWidth>2</bitWidth> 5296 <enumeratedValues derivedFrom="PUPDR0"/> 5297 </field> 5298 <field> 5299 <name>PUPDR8</name> 5300 <description>Port x configuration bits (y = 5301 0..15)</description> 5302 <bitOffset>16</bitOffset> 5303 <bitWidth>2</bitWidth> 5304 <enumeratedValues derivedFrom="PUPDR0"/> 5305 </field> 5306 <field> 5307 <name>PUPDR7</name> 5308 <description>Port x configuration bits (y = 5309 0..15)</description> 5310 <bitOffset>14</bitOffset> 5311 <bitWidth>2</bitWidth> 5312 <enumeratedValues derivedFrom="PUPDR0"/> 5313 </field> 5314 <field> 5315 <name>PUPDR6</name> 5316 <description>Port x configuration bits (y = 5317 0..15)</description> 5318 <bitOffset>12</bitOffset> 5319 <bitWidth>2</bitWidth> 5320 <enumeratedValues derivedFrom="PUPDR0"/> 5321 </field> 5322 <field> 5323 <name>PUPDR5</name> 5324 <description>Port x configuration bits (y = 5325 0..15)</description> 5326 <bitOffset>10</bitOffset> 5327 <bitWidth>2</bitWidth> 5328 <enumeratedValues derivedFrom="PUPDR0"/> 5329 </field> 5330 <field> 5331 <name>PUPDR4</name> 5332 <description>Port x configuration bits (y = 5333 0..15)</description> 5334 <bitOffset>8</bitOffset> 5335 <bitWidth>2</bitWidth> 5336 <enumeratedValues derivedFrom="PUPDR0"/> 5337 </field> 5338 <field> 5339 <name>PUPDR3</name> 5340 <description>Port x configuration bits (y = 5341 0..15)</description> 5342 <bitOffset>6</bitOffset> 5343 <bitWidth>2</bitWidth> 5344 <enumeratedValues derivedFrom="PUPDR0"/> 5345 </field> 5346 <field> 5347 <name>PUPDR2</name> 5348 <description>Port x configuration bits (y = 5349 0..15)</description> 5350 <bitOffset>4</bitOffset> 5351 <bitWidth>2</bitWidth> 5352 <enumeratedValues derivedFrom="PUPDR0"/> 5353 </field> 5354 <field> 5355 <name>PUPDR1</name> 5356 <description>Port x configuration bits (y = 5357 0..15)</description> 5358 <bitOffset>2</bitOffset> 5359 <bitWidth>2</bitWidth> 5360 <enumeratedValues derivedFrom="PUPDR0"/> 5361 </field> 5362 <field> 5363 <name>PUPDR0</name> 5364 <description>Port x configuration bits (y = 5365 0..15)</description> 5366 <bitOffset>0</bitOffset> 5367 <bitWidth>2</bitWidth> 5368 <enumeratedValues><name>PUPDR0</name><usage>read-write</usage><enumeratedValue><name>Floating</name><description>No pull-up, pull-down</description><value>0</value></enumeratedValue><enumeratedValue><name>PullUp</name><description>Pull-up</description><value>1</value></enumeratedValue><enumeratedValue><name>PullDown</name><description>Pull-down</description><value>2</value></enumeratedValue></enumeratedValues> 5369 </field> 5370 </fields> 5371 </register> 5372 <register> 5373 <name>IDR</name> 5374 <displayName>IDR</displayName> 5375 <description>GPIO port input data register</description> 5376 <addressOffset>0x10</addressOffset> 5377 <size>0x20</size> 5378 <access>read-only</access> 5379 <resetValue>0x00000000</resetValue> 5380 <fields> 5381 <field> 5382 <name>IDR15</name> 5383 <description>Port input data (y = 5384 0..15)</description> 5385 <bitOffset>15</bitOffset> 5386 <bitWidth>1</bitWidth> 5387 <enumeratedValues derivedFrom="IDR0"/> 5388 </field> 5389 <field> 5390 <name>IDR14</name> 5391 <description>Port input data (y = 5392 0..15)</description> 5393 <bitOffset>14</bitOffset> 5394 <bitWidth>1</bitWidth> 5395 <enumeratedValues derivedFrom="IDR0"/> 5396 </field> 5397 <field> 5398 <name>IDR13</name> 5399 <description>Port input data (y = 5400 0..15)</description> 5401 <bitOffset>13</bitOffset> 5402 <bitWidth>1</bitWidth> 5403 <enumeratedValues derivedFrom="IDR0"/> 5404 </field> 5405 <field> 5406 <name>IDR12</name> 5407 <description>Port input data (y = 5408 0..15)</description> 5409 <bitOffset>12</bitOffset> 5410 <bitWidth>1</bitWidth> 5411 <enumeratedValues derivedFrom="IDR0"/> 5412 </field> 5413 <field> 5414 <name>IDR11</name> 5415 <description>Port input data (y = 5416 0..15)</description> 5417 <bitOffset>11</bitOffset> 5418 <bitWidth>1</bitWidth> 5419 <enumeratedValues derivedFrom="IDR0"/> 5420 </field> 5421 <field> 5422 <name>IDR10</name> 5423 <description>Port input data (y = 5424 0..15)</description> 5425 <bitOffset>10</bitOffset> 5426 <bitWidth>1</bitWidth> 5427 <enumeratedValues derivedFrom="IDR0"/> 5428 </field> 5429 <field> 5430 <name>IDR9</name> 5431 <description>Port input data (y = 5432 0..15)</description> 5433 <bitOffset>9</bitOffset> 5434 <bitWidth>1</bitWidth> 5435 <enumeratedValues derivedFrom="IDR0"/> 5436 </field> 5437 <field> 5438 <name>IDR8</name> 5439 <description>Port input data (y = 5440 0..15)</description> 5441 <bitOffset>8</bitOffset> 5442 <bitWidth>1</bitWidth> 5443 <enumeratedValues derivedFrom="IDR0"/> 5444 </field> 5445 <field> 5446 <name>IDR7</name> 5447 <description>Port input data (y = 5448 0..15)</description> 5449 <bitOffset>7</bitOffset> 5450 <bitWidth>1</bitWidth> 5451 <enumeratedValues derivedFrom="IDR0"/> 5452 </field> 5453 <field> 5454 <name>IDR6</name> 5455 <description>Port input data (y = 5456 0..15)</description> 5457 <bitOffset>6</bitOffset> 5458 <bitWidth>1</bitWidth> 5459 <enumeratedValues derivedFrom="IDR0"/> 5460 </field> 5461 <field> 5462 <name>IDR5</name> 5463 <description>Port input data (y = 5464 0..15)</description> 5465 <bitOffset>5</bitOffset> 5466 <bitWidth>1</bitWidth> 5467 <enumeratedValues derivedFrom="IDR0"/> 5468 </field> 5469 <field> 5470 <name>IDR4</name> 5471 <description>Port input data (y = 5472 0..15)</description> 5473 <bitOffset>4</bitOffset> 5474 <bitWidth>1</bitWidth> 5475 <enumeratedValues derivedFrom="IDR0"/> 5476 </field> 5477 <field> 5478 <name>IDR3</name> 5479 <description>Port input data (y = 5480 0..15)</description> 5481 <bitOffset>3</bitOffset> 5482 <bitWidth>1</bitWidth> 5483 <enumeratedValues derivedFrom="IDR0"/> 5484 </field> 5485 <field> 5486 <name>IDR2</name> 5487 <description>Port input data (y = 5488 0..15)</description> 5489 <bitOffset>2</bitOffset> 5490 <bitWidth>1</bitWidth> 5491 <enumeratedValues derivedFrom="IDR0"/> 5492 </field> 5493 <field> 5494 <name>IDR1</name> 5495 <description>Port input data (y = 5496 0..15)</description> 5497 <bitOffset>1</bitOffset> 5498 <bitWidth>1</bitWidth> 5499 <enumeratedValues derivedFrom="IDR0"/> 5500 </field> 5501 <field> 5502 <name>IDR0</name> 5503 <description>Port input data (y = 5504 0..15)</description> 5505 <bitOffset>0</bitOffset> 5506 <bitWidth>1</bitWidth> 5507 <enumeratedValues><name>IDR0</name><usage>read-write</usage><enumeratedValue><name>High</name><description>Input is logic high</description><value>1</value></enumeratedValue><enumeratedValue><name>Low</name><description>Input is logic low</description><value>0</value></enumeratedValue></enumeratedValues> 5508 </field> 5509 </fields> 5510 </register> 5511 <register> 5512 <name>ODR</name> 5513 <displayName>ODR</displayName> 5514 <description>GPIO port output data register</description> 5515 <addressOffset>0x14</addressOffset> 5516 <size>0x20</size> 5517 <access>read-write</access> 5518 <resetValue>0x00000000</resetValue> 5519 <fields> 5520 <field> 5521 <name>ODR15</name> 5522 <description>Port output data (y = 5523 0..15)</description> 5524 <bitOffset>15</bitOffset> 5525 <bitWidth>1</bitWidth> 5526 <enumeratedValues derivedFrom="ODR0"/> 5527 </field> 5528 <field> 5529 <name>ODR14</name> 5530 <description>Port output data (y = 5531 0..15)</description> 5532 <bitOffset>14</bitOffset> 5533 <bitWidth>1</bitWidth> 5534 <enumeratedValues derivedFrom="ODR0"/> 5535 </field> 5536 <field> 5537 <name>ODR13</name> 5538 <description>Port output data (y = 5539 0..15)</description> 5540 <bitOffset>13</bitOffset> 5541 <bitWidth>1</bitWidth> 5542 <enumeratedValues derivedFrom="ODR0"/> 5543 </field> 5544 <field> 5545 <name>ODR12</name> 5546 <description>Port output data (y = 5547 0..15)</description> 5548 <bitOffset>12</bitOffset> 5549 <bitWidth>1</bitWidth> 5550 <enumeratedValues derivedFrom="ODR0"/> 5551 </field> 5552 <field> 5553 <name>ODR11</name> 5554 <description>Port output data (y = 5555 0..15)</description> 5556 <bitOffset>11</bitOffset> 5557 <bitWidth>1</bitWidth> 5558 <enumeratedValues derivedFrom="ODR0"/> 5559 </field> 5560 <field> 5561 <name>ODR10</name> 5562 <description>Port output data (y = 5563 0..15)</description> 5564 <bitOffset>10</bitOffset> 5565 <bitWidth>1</bitWidth> 5566 <enumeratedValues derivedFrom="ODR0"/> 5567 </field> 5568 <field> 5569 <name>ODR9</name> 5570 <description>Port output data (y = 5571 0..15)</description> 5572 <bitOffset>9</bitOffset> 5573 <bitWidth>1</bitWidth> 5574 <enumeratedValues derivedFrom="ODR0"/> 5575 </field> 5576 <field> 5577 <name>ODR8</name> 5578 <description>Port output data (y = 5579 0..15)</description> 5580 <bitOffset>8</bitOffset> 5581 <bitWidth>1</bitWidth> 5582 <enumeratedValues derivedFrom="ODR0"/> 5583 </field> 5584 <field> 5585 <name>ODR7</name> 5586 <description>Port output data (y = 5587 0..15)</description> 5588 <bitOffset>7</bitOffset> 5589 <bitWidth>1</bitWidth> 5590 <enumeratedValues derivedFrom="ODR0"/> 5591 </field> 5592 <field> 5593 <name>ODR6</name> 5594 <description>Port output data (y = 5595 0..15)</description> 5596 <bitOffset>6</bitOffset> 5597 <bitWidth>1</bitWidth> 5598 <enumeratedValues derivedFrom="ODR0"/> 5599 </field> 5600 <field> 5601 <name>ODR5</name> 5602 <description>Port output data (y = 5603 0..15)</description> 5604 <bitOffset>5</bitOffset> 5605 <bitWidth>1</bitWidth> 5606 <enumeratedValues derivedFrom="ODR0"/> 5607 </field> 5608 <field> 5609 <name>ODR4</name> 5610 <description>Port output data (y = 5611 0..15)</description> 5612 <bitOffset>4</bitOffset> 5613 <bitWidth>1</bitWidth> 5614 <enumeratedValues derivedFrom="ODR0"/> 5615 </field> 5616 <field> 5617 <name>ODR3</name> 5618 <description>Port output data (y = 5619 0..15)</description> 5620 <bitOffset>3</bitOffset> 5621 <bitWidth>1</bitWidth> 5622 <enumeratedValues derivedFrom="ODR0"/> 5623 </field> 5624 <field> 5625 <name>ODR2</name> 5626 <description>Port output data (y = 5627 0..15)</description> 5628 <bitOffset>2</bitOffset> 5629 <bitWidth>1</bitWidth> 5630 <enumeratedValues derivedFrom="ODR0"/> 5631 </field> 5632 <field> 5633 <name>ODR1</name> 5634 <description>Port output data (y = 5635 0..15)</description> 5636 <bitOffset>1</bitOffset> 5637 <bitWidth>1</bitWidth> 5638 <enumeratedValues derivedFrom="ODR0"/> 5639 </field> 5640 <field> 5641 <name>ODR0</name> 5642 <description>Port output data (y = 5643 0..15)</description> 5644 <bitOffset>0</bitOffset> 5645 <bitWidth>1</bitWidth> 5646 <enumeratedValues><name>ODR0</name><usage>read-write</usage><enumeratedValue><name>High</name><description>Set output to logic high</description><value>1</value></enumeratedValue><enumeratedValue><name>Low</name><description>Set output to logic low</description><value>0</value></enumeratedValue></enumeratedValues> 5647 </field> 5648 </fields> 5649 </register> 5650 <register> 5651 <name>BSRR</name> 5652 <displayName>BSRR</displayName> 5653 <description>GPIO port bit set/reset 5654 register</description> 5655 <addressOffset>0x18</addressOffset> 5656 <size>0x20</size> 5657 <access>write-only</access> 5658 <resetValue>0x00000000</resetValue> 5659 <fields> 5660 <field> 5661 <name>BR15</name> 5662 <description>Port x reset bit y (y = 5663 0..15)</description> 5664 <bitOffset>31</bitOffset> 5665 <bitWidth>1</bitWidth> 5666 <enumeratedValues derivedFrom="BR0W"/> 5667 </field> 5668 <field> 5669 <name>BR14</name> 5670 <description>Port x reset bit y (y = 5671 0..15)</description> 5672 <bitOffset>30</bitOffset> 5673 <bitWidth>1</bitWidth> 5674 <enumeratedValues derivedFrom="BR0W"/> 5675 </field> 5676 <field> 5677 <name>BR13</name> 5678 <description>Port x reset bit y (y = 5679 0..15)</description> 5680 <bitOffset>29</bitOffset> 5681 <bitWidth>1</bitWidth> 5682 <enumeratedValues derivedFrom="BR0W"/> 5683 </field> 5684 <field> 5685 <name>BR12</name> 5686 <description>Port x reset bit y (y = 5687 0..15)</description> 5688 <bitOffset>28</bitOffset> 5689 <bitWidth>1</bitWidth> 5690 <enumeratedValues derivedFrom="BR0W"/> 5691 </field> 5692 <field> 5693 <name>BR11</name> 5694 <description>Port x reset bit y (y = 5695 0..15)</description> 5696 <bitOffset>27</bitOffset> 5697 <bitWidth>1</bitWidth> 5698 <enumeratedValues derivedFrom="BR0W"/> 5699 </field> 5700 <field> 5701 <name>BR10</name> 5702 <description>Port x reset bit y (y = 5703 0..15)</description> 5704 <bitOffset>26</bitOffset> 5705 <bitWidth>1</bitWidth> 5706 <enumeratedValues derivedFrom="BR0W"/> 5707 </field> 5708 <field> 5709 <name>BR9</name> 5710 <description>Port x reset bit y (y = 5711 0..15)</description> 5712 <bitOffset>25</bitOffset> 5713 <bitWidth>1</bitWidth> 5714 <enumeratedValues derivedFrom="BR0W"/> 5715 </field> 5716 <field> 5717 <name>BR8</name> 5718 <description>Port x reset bit y (y = 5719 0..15)</description> 5720 <bitOffset>24</bitOffset> 5721 <bitWidth>1</bitWidth> 5722 <enumeratedValues derivedFrom="BR0W"/> 5723 </field> 5724 <field> 5725 <name>BR7</name> 5726 <description>Port x reset bit y (y = 5727 0..15)</description> 5728 <bitOffset>23</bitOffset> 5729 <bitWidth>1</bitWidth> 5730 <enumeratedValues derivedFrom="BR0W"/> 5731 </field> 5732 <field> 5733 <name>BR6</name> 5734 <description>Port x reset bit y (y = 5735 0..15)</description> 5736 <bitOffset>22</bitOffset> 5737 <bitWidth>1</bitWidth> 5738 <enumeratedValues derivedFrom="BR0W"/> 5739 </field> 5740 <field> 5741 <name>BR5</name> 5742 <description>Port x reset bit y (y = 5743 0..15)</description> 5744 <bitOffset>21</bitOffset> 5745 <bitWidth>1</bitWidth> 5746 <enumeratedValues derivedFrom="BR0W"/> 5747 </field> 5748 <field> 5749 <name>BR4</name> 5750 <description>Port x reset bit y (y = 5751 0..15)</description> 5752 <bitOffset>20</bitOffset> 5753 <bitWidth>1</bitWidth> 5754 <enumeratedValues derivedFrom="BR0W"/> 5755 </field> 5756 <field> 5757 <name>BR3</name> 5758 <description>Port x reset bit y (y = 5759 0..15)</description> 5760 <bitOffset>19</bitOffset> 5761 <bitWidth>1</bitWidth> 5762 <enumeratedValues derivedFrom="BR0W"/> 5763 </field> 5764 <field> 5765 <name>BR2</name> 5766 <description>Port x reset bit y (y = 5767 0..15)</description> 5768 <bitOffset>18</bitOffset> 5769 <bitWidth>1</bitWidth> 5770 <enumeratedValues derivedFrom="BR0W"/> 5771 </field> 5772 <field> 5773 <name>BR1</name> 5774 <description>Port x reset bit y (y = 5775 0..15)</description> 5776 <bitOffset>17</bitOffset> 5777 <bitWidth>1</bitWidth> 5778 <enumeratedValues derivedFrom="BR0W"/> 5779 </field> 5780 <field> 5781 <name>BR0</name> 5782 <description>Port x set bit y (y= 5783 0..15)</description> 5784 <bitOffset>16</bitOffset> 5785 <bitWidth>1</bitWidth> 5786 <enumeratedValues><name>BR0W</name><usage>write</usage><enumeratedValue><name>Reset</name><description>Resets the corresponding ODRx bit</description><value>1</value></enumeratedValue></enumeratedValues> 5787 </field> 5788 <field> 5789 <name>BS15</name> 5790 <description>Port x set bit y (y= 5791 0..15)</description> 5792 <bitOffset>15</bitOffset> 5793 <bitWidth>1</bitWidth> 5794 <enumeratedValues derivedFrom="BS0W"/> 5795 </field> 5796 <field> 5797 <name>BS14</name> 5798 <description>Port x set bit y (y= 5799 0..15)</description> 5800 <bitOffset>14</bitOffset> 5801 <bitWidth>1</bitWidth> 5802 <enumeratedValues derivedFrom="BS0W"/> 5803 </field> 5804 <field> 5805 <name>BS13</name> 5806 <description>Port x set bit y (y= 5807 0..15)</description> 5808 <bitOffset>13</bitOffset> 5809 <bitWidth>1</bitWidth> 5810 <enumeratedValues derivedFrom="BS0W"/> 5811 </field> 5812 <field> 5813 <name>BS12</name> 5814 <description>Port x set bit y (y= 5815 0..15)</description> 5816 <bitOffset>12</bitOffset> 5817 <bitWidth>1</bitWidth> 5818 <enumeratedValues derivedFrom="BS0W"/> 5819 </field> 5820 <field> 5821 <name>BS11</name> 5822 <description>Port x set bit y (y= 5823 0..15)</description> 5824 <bitOffset>11</bitOffset> 5825 <bitWidth>1</bitWidth> 5826 <enumeratedValues derivedFrom="BS0W"/> 5827 </field> 5828 <field> 5829 <name>BS10</name> 5830 <description>Port x set bit y (y= 5831 0..15)</description> 5832 <bitOffset>10</bitOffset> 5833 <bitWidth>1</bitWidth> 5834 <enumeratedValues derivedFrom="BS0W"/> 5835 </field> 5836 <field> 5837 <name>BS9</name> 5838 <description>Port x set bit y (y= 5839 0..15)</description> 5840 <bitOffset>9</bitOffset> 5841 <bitWidth>1</bitWidth> 5842 <enumeratedValues derivedFrom="BS0W"/> 5843 </field> 5844 <field> 5845 <name>BS8</name> 5846 <description>Port x set bit y (y= 5847 0..15)</description> 5848 <bitOffset>8</bitOffset> 5849 <bitWidth>1</bitWidth> 5850 <enumeratedValues derivedFrom="BS0W"/> 5851 </field> 5852 <field> 5853 <name>BS7</name> 5854 <description>Port x set bit y (y= 5855 0..15)</description> 5856 <bitOffset>7</bitOffset> 5857 <bitWidth>1</bitWidth> 5858 <enumeratedValues derivedFrom="BS0W"/> 5859 </field> 5860 <field> 5861 <name>BS6</name> 5862 <description>Port x set bit y (y= 5863 0..15)</description> 5864 <bitOffset>6</bitOffset> 5865 <bitWidth>1</bitWidth> 5866 <enumeratedValues derivedFrom="BS0W"/> 5867 </field> 5868 <field> 5869 <name>BS5</name> 5870 <description>Port x set bit y (y= 5871 0..15)</description> 5872 <bitOffset>5</bitOffset> 5873 <bitWidth>1</bitWidth> 5874 <enumeratedValues derivedFrom="BS0W"/> 5875 </field> 5876 <field> 5877 <name>BS4</name> 5878 <description>Port x set bit y (y= 5879 0..15)</description> 5880 <bitOffset>4</bitOffset> 5881 <bitWidth>1</bitWidth> 5882 <enumeratedValues derivedFrom="BS0W"/> 5883 </field> 5884 <field> 5885 <name>BS3</name> 5886 <description>Port x set bit y (y= 5887 0..15)</description> 5888 <bitOffset>3</bitOffset> 5889 <bitWidth>1</bitWidth> 5890 <enumeratedValues derivedFrom="BS0W"/> 5891 </field> 5892 <field> 5893 <name>BS2</name> 5894 <description>Port x set bit y (y= 5895 0..15)</description> 5896 <bitOffset>2</bitOffset> 5897 <bitWidth>1</bitWidth> 5898 <enumeratedValues derivedFrom="BS0W"/> 5899 </field> 5900 <field> 5901 <name>BS1</name> 5902 <description>Port x set bit y (y= 5903 0..15)</description> 5904 <bitOffset>1</bitOffset> 5905 <bitWidth>1</bitWidth> 5906 <enumeratedValues derivedFrom="BS0W"/> 5907 </field> 5908 <field> 5909 <name>BS0</name> 5910 <description>Port x set bit y (y= 5911 0..15)</description> 5912 <bitOffset>0</bitOffset> 5913 <bitWidth>1</bitWidth> 5914 <enumeratedValues><name>BS0W</name><usage>write</usage><enumeratedValue><name>Set</name><description>Sets the corresponding ODRx bit</description><value>1</value></enumeratedValue></enumeratedValues> 5915 </field> 5916 </fields> 5917 </register> 5918 <register> 5919 <name>LCKR</name> 5920 <displayName>LCKR</displayName> 5921 <description>GPIO port configuration lock 5922 register</description> 5923 <addressOffset>0x1C</addressOffset> 5924 <size>0x20</size> 5925 <access>read-write</access> 5926 <resetValue>0x00000000</resetValue> 5927 <fields> 5928 <field> 5929 <name>LCKK</name> 5930 <description>Port x lock bit y (y= 5931 0..15)</description> 5932 <bitOffset>16</bitOffset> 5933 <bitWidth>1</bitWidth> 5934 <enumeratedValues><name>LCKK</name><usage>read-write</usage><enumeratedValue><name>NotActive</name><description>Port configuration lock key not active</description><value>0</value></enumeratedValue><enumeratedValue><name>Active</name><description>Port configuration lock key active</description><value>1</value></enumeratedValue></enumeratedValues> 5935 </field> 5936 <field> 5937 <name>LCK15</name> 5938 <description>Port x lock bit y (y= 5939 0..15)</description> 5940 <bitOffset>15</bitOffset> 5941 <bitWidth>1</bitWidth> 5942 <enumeratedValues derivedFrom="LCK10"/> 5943 </field> 5944 <field> 5945 <name>LCK14</name> 5946 <description>Port x lock bit y (y= 5947 0..15)</description> 5948 <bitOffset>14</bitOffset> 5949 <bitWidth>1</bitWidth> 5950 <enumeratedValues derivedFrom="LCK10"/> 5951 </field> 5952 <field> 5953 <name>LCK13</name> 5954 <description>Port x lock bit y (y= 5955 0..15)</description> 5956 <bitOffset>13</bitOffset> 5957 <bitWidth>1</bitWidth> 5958 <enumeratedValues derivedFrom="LCK10"/> 5959 </field> 5960 <field> 5961 <name>LCK12</name> 5962 <description>Port x lock bit y (y= 5963 0..15)</description> 5964 <bitOffset>12</bitOffset> 5965 <bitWidth>1</bitWidth> 5966 <enumeratedValues derivedFrom="LCK10"/> 5967 </field> 5968 <field> 5969 <name>LCK11</name> 5970 <description>Port x lock bit y (y= 5971 0..15)</description> 5972 <bitOffset>11</bitOffset> 5973 <bitWidth>1</bitWidth> 5974 <enumeratedValues derivedFrom="LCK10"/> 5975 </field> 5976 <field> 5977 <name>LCK10</name> 5978 <description>Port x lock bit y (y= 5979 0..15)</description> 5980 <bitOffset>10</bitOffset> 5981 <bitWidth>1</bitWidth> 5982 <enumeratedValues><name>LCK10</name><usage>read-write</usage><enumeratedValue><name>Unlocked</name><description>Port configuration not locked</description><value>0</value></enumeratedValue><enumeratedValue><name>Locked</name><description>Port configuration locked</description><value>1</value></enumeratedValue></enumeratedValues> 5983 </field> 5984 <field> 5985 <name>LCK9</name> 5986 <description>Port x lock bit y (y= 5987 0..15)</description> 5988 <bitOffset>9</bitOffset> 5989 <bitWidth>1</bitWidth> 5990 <enumeratedValues derivedFrom="LCK0"/> 5991 </field> 5992 <field> 5993 <name>LCK8</name> 5994 <description>Port x lock bit y (y= 5995 0..15)</description> 5996 <bitOffset>8</bitOffset> 5997 <bitWidth>1</bitWidth> 5998 <enumeratedValues derivedFrom="LCK0"/> 5999 </field> 6000 <field> 6001 <name>LCK7</name> 6002 <description>Port x lock bit y (y= 6003 0..15)</description> 6004 <bitOffset>7</bitOffset> 6005 <bitWidth>1</bitWidth> 6006 <enumeratedValues derivedFrom="LCK0"/> 6007 </field> 6008 <field> 6009 <name>LCK6</name> 6010 <description>Port x lock bit y (y= 6011 0..15)</description> 6012 <bitOffset>6</bitOffset> 6013 <bitWidth>1</bitWidth> 6014 <enumeratedValues derivedFrom="LCK0"/> 6015 </field> 6016 <field> 6017 <name>LCK5</name> 6018 <description>Port x lock bit y (y= 6019 0..15)</description> 6020 <bitOffset>5</bitOffset> 6021 <bitWidth>1</bitWidth> 6022 <enumeratedValues derivedFrom="LCK0"/> 6023 </field> 6024 <field> 6025 <name>LCK4</name> 6026 <description>Port x lock bit y (y= 6027 0..15)</description> 6028 <bitOffset>4</bitOffset> 6029 <bitWidth>1</bitWidth> 6030 <enumeratedValues derivedFrom="LCK0"/> 6031 </field> 6032 <field> 6033 <name>LCK3</name> 6034 <description>Port x lock bit y (y= 6035 0..15)</description> 6036 <bitOffset>3</bitOffset> 6037 <bitWidth>1</bitWidth> 6038 <enumeratedValues derivedFrom="LCK0"/> 6039 </field> 6040 <field> 6041 <name>LCK2</name> 6042 <description>Port x lock bit y (y= 6043 0..15)</description> 6044 <bitOffset>2</bitOffset> 6045 <bitWidth>1</bitWidth> 6046 <enumeratedValues derivedFrom="LCK0"/> 6047 </field> 6048 <field> 6049 <name>LCK1</name> 6050 <description>Port x lock bit y (y= 6051 0..15)</description> 6052 <bitOffset>1</bitOffset> 6053 <bitWidth>1</bitWidth> 6054 <enumeratedValues derivedFrom="LCK0"/> 6055 </field> 6056 <field> 6057 <name>LCK0</name> 6058 <description>Port x lock bit y (y= 6059 0..15)</description> 6060 <bitOffset>0</bitOffset> 6061 <bitWidth>1</bitWidth> 6062 <enumeratedValues><name>LCK0</name><usage>read-write</usage><enumeratedValue><name>Unlocked</name><description>Port configuration not locked</description><value>0</value></enumeratedValue><enumeratedValue><name>Locked</name><description>Port configuration locked</description><value>1</value></enumeratedValue></enumeratedValues> 6063 </field> 6064 </fields> 6065 </register> 6066 <register> 6067 <name>AFRL</name> 6068 <displayName>AFRL</displayName> 6069 <description>GPIO alternate function low 6070 register</description> 6071 <addressOffset>0x20</addressOffset> 6072 <size>0x20</size> 6073 <access>read-write</access> 6074 <resetValue>0x00000000</resetValue> 6075 <fields> 6076 <field> 6077 <name>AFRL7</name> 6078 <description>Alternate function selection for port x 6079 bit y (y = 0..7)</description> 6080 <bitOffset>28</bitOffset> 6081 <bitWidth>4</bitWidth> 6082 <enumeratedValues derivedFrom="AFRL0"/> 6083 </field> 6084 <field> 6085 <name>AFRL6</name> 6086 <description>Alternate function selection for port x 6087 bit y (y = 0..7)</description> 6088 <bitOffset>24</bitOffset> 6089 <bitWidth>4</bitWidth> 6090 <enumeratedValues derivedFrom="AFRL0"/> 6091 </field> 6092 <field> 6093 <name>AFRL5</name> 6094 <description>Alternate function selection for port x 6095 bit y (y = 0..7)</description> 6096 <bitOffset>20</bitOffset> 6097 <bitWidth>4</bitWidth> 6098 <enumeratedValues derivedFrom="AFRL0"/> 6099 </field> 6100 <field> 6101 <name>AFRL4</name> 6102 <description>Alternate function selection for port x 6103 bit y (y = 0..7)</description> 6104 <bitOffset>16</bitOffset> 6105 <bitWidth>4</bitWidth> 6106 <enumeratedValues derivedFrom="AFRL0"/> 6107 </field> 6108 <field> 6109 <name>AFRL3</name> 6110 <description>Alternate function selection for port x 6111 bit y (y = 0..7)</description> 6112 <bitOffset>12</bitOffset> 6113 <bitWidth>4</bitWidth> 6114 <enumeratedValues derivedFrom="AFRL0"/> 6115 </field> 6116 <field> 6117 <name>AFRL2</name> 6118 <description>Alternate function selection for port x 6119 bit y (y = 0..7)</description> 6120 <bitOffset>8</bitOffset> 6121 <bitWidth>4</bitWidth> 6122 <enumeratedValues derivedFrom="AFRL0"/> 6123 </field> 6124 <field> 6125 <name>AFRL1</name> 6126 <description>Alternate function selection for port x 6127 bit y (y = 0..7)</description> 6128 <bitOffset>4</bitOffset> 6129 <bitWidth>4</bitWidth> 6130 <enumeratedValues derivedFrom="AFRL0"/> 6131 </field> 6132 <field> 6133 <name>AFRL0</name> 6134 <description>Alternate function selection for port x 6135 bit y (y = 0..7)</description> 6136 <bitOffset>0</bitOffset> 6137 <bitWidth>4</bitWidth> 6138 <enumeratedValues><name>AFRL0</name><usage>read-write</usage><enumeratedValue><name>AF0</name><description>AF0</description><value>0</value></enumeratedValue><enumeratedValue><name>AF1</name><description>AF1</description><value>1</value></enumeratedValue><enumeratedValue><name>AF2</name><description>AF2</description><value>2</value></enumeratedValue><enumeratedValue><name>AF3</name><description>AF3</description><value>3</value></enumeratedValue><enumeratedValue><name>AF4</name><description>AF4</description><value>4</value></enumeratedValue><enumeratedValue><name>AF5</name><description>AF5</description><value>5</value></enumeratedValue><enumeratedValue><name>AF6</name><description>AF6</description><value>6</value></enumeratedValue><enumeratedValue><name>AF7</name><description>AF7</description><value>7</value></enumeratedValue><enumeratedValue><name>AF8</name><description>AF8</description><value>8</value></enumeratedValue><enumeratedValue><name>AF9</name><description>AF9</description><value>9</value></enumeratedValue><enumeratedValue><name>AF10</name><description>AF10</description><value>10</value></enumeratedValue><enumeratedValue><name>AF11</name><description>AF11</description><value>11</value></enumeratedValue><enumeratedValue><name>AF12</name><description>AF12</description><value>12</value></enumeratedValue><enumeratedValue><name>AF13</name><description>AF13</description><value>13</value></enumeratedValue><enumeratedValue><name>AF14</name><description>AF14</description><value>14</value></enumeratedValue><enumeratedValue><name>AF15</name><description>AF15</description><value>15</value></enumeratedValue></enumeratedValues> 6139 </field> 6140 </fields> 6141 </register> 6142 <register> 6143 <name>AFRH</name> 6144 <displayName>AFRH</displayName> 6145 <description>GPIO alternate function high 6146 register</description> 6147 <addressOffset>0x24</addressOffset> 6148 <size>0x20</size> 6149 <access>read-write</access> 6150 <resetValue>0x00000000</resetValue> 6151 <fields> 6152 <field> 6153 <name>AFRH15</name> 6154 <description>Alternate function selection for port x 6155 bit y (y = 8..15)</description> 6156 <bitOffset>28</bitOffset> 6157 <bitWidth>4</bitWidth> 6158 <enumeratedValues derivedFrom="AFRH8"/> 6159 </field> 6160 <field> 6161 <name>AFRH14</name> 6162 <description>Alternate function selection for port x 6163 bit y (y = 8..15)</description> 6164 <bitOffset>24</bitOffset> 6165 <bitWidth>4</bitWidth> 6166 <enumeratedValues derivedFrom="AFRH8"/> 6167 </field> 6168 <field> 6169 <name>AFRH13</name> 6170 <description>Alternate function selection for port x 6171 bit y (y = 8..15)</description> 6172 <bitOffset>20</bitOffset> 6173 <bitWidth>4</bitWidth> 6174 <enumeratedValues derivedFrom="AFRH8"/> 6175 </field> 6176 <field> 6177 <name>AFRH12</name> 6178 <description>Alternate function selection for port x 6179 bit y (y = 8..15)</description> 6180 <bitOffset>16</bitOffset> 6181 <bitWidth>4</bitWidth> 6182 <enumeratedValues derivedFrom="AFRH8"/> 6183 </field> 6184 <field> 6185 <name>AFRH11</name> 6186 <description>Alternate function selection for port x 6187 bit y (y = 8..15)</description> 6188 <bitOffset>12</bitOffset> 6189 <bitWidth>4</bitWidth> 6190 <enumeratedValues derivedFrom="AFRH8"/> 6191 </field> 6192 <field> 6193 <name>AFRH10</name> 6194 <description>Alternate function selection for port x 6195 bit y (y = 8..15)</description> 6196 <bitOffset>8</bitOffset> 6197 <bitWidth>4</bitWidth> 6198 <enumeratedValues derivedFrom="AFRH8"/> 6199 </field> 6200 <field> 6201 <name>AFRH9</name> 6202 <description>Alternate function selection for port x 6203 bit y (y = 8..15)</description> 6204 <bitOffset>4</bitOffset> 6205 <bitWidth>4</bitWidth> 6206 <enumeratedValues derivedFrom="AFRH8"/> 6207 </field> 6208 <field> 6209 <name>AFRH8</name> 6210 <description>Alternate function selection for port x 6211 bit y (y = 8..15)</description> 6212 <bitOffset>0</bitOffset> 6213 <bitWidth>4</bitWidth> 6214 <enumeratedValues><name>AFRH8</name><usage>read-write</usage><enumeratedValue><name>AF0</name><description>AF0</description><value>0</value></enumeratedValue><enumeratedValue><name>AF1</name><description>AF1</description><value>1</value></enumeratedValue><enumeratedValue><name>AF2</name><description>AF2</description><value>2</value></enumeratedValue><enumeratedValue><name>AF3</name><description>AF3</description><value>3</value></enumeratedValue><enumeratedValue><name>AF4</name><description>AF4</description><value>4</value></enumeratedValue><enumeratedValue><name>AF5</name><description>AF5</description><value>5</value></enumeratedValue><enumeratedValue><name>AF6</name><description>AF6</description><value>6</value></enumeratedValue><enumeratedValue><name>AF7</name><description>AF7</description><value>7</value></enumeratedValue><enumeratedValue><name>AF8</name><description>AF8</description><value>8</value></enumeratedValue><enumeratedValue><name>AF9</name><description>AF9</description><value>9</value></enumeratedValue><enumeratedValue><name>AF10</name><description>AF10</description><value>10</value></enumeratedValue><enumeratedValue><name>AF11</name><description>AF11</description><value>11</value></enumeratedValue><enumeratedValue><name>AF12</name><description>AF12</description><value>12</value></enumeratedValue><enumeratedValue><name>AF13</name><description>AF13</description><value>13</value></enumeratedValue><enumeratedValue><name>AF14</name><description>AF14</description><value>14</value></enumeratedValue><enumeratedValue><name>AF15</name><description>AF15</description><value>15</value></enumeratedValue></enumeratedValues> 6215 </field> 6216 </fields> 6217 </register> 6218 </registers> 6219 </peripheral> 6220 <peripheral derivedFrom="GPIOI"> 6221 <name>GPIOH</name> 6222 <baseAddress>0x40021C00</baseAddress> 6223 </peripheral> 6224 <peripheral derivedFrom="GPIOI"> 6225 <name>GPIOG</name> 6226 <baseAddress>0x40021800</baseAddress> 6227 </peripheral> 6228 <peripheral derivedFrom="GPIOI"> 6229 <name>GPIOF</name> 6230 <baseAddress>0x40021400</baseAddress> 6231 </peripheral> 6232 <peripheral derivedFrom="GPIOI"> 6233 <name>GPIOE</name> 6234 <baseAddress>0x40021000</baseAddress> 6235 </peripheral> 6236 <peripheral derivedFrom="GPIOI"> 6237 <name>GPIOD</name> 6238 <baseAddress>0X40020C00</baseAddress> 6239 </peripheral> 6240 <peripheral derivedFrom="GPIOI"> 6241 <name>GPIOC</name> 6242 <baseAddress>0x40020800</baseAddress> 6243 </peripheral> 6244 <peripheral derivedFrom="GPIOI"> 6245 <name>GPIOJ</name> 6246 <baseAddress>0x40022400</baseAddress> 6247 </peripheral> 6248 <peripheral derivedFrom="GPIOI"> 6249 <name>GPIOK</name> 6250 <baseAddress>0x40022800</baseAddress> 6251 </peripheral> 6252 <peripheral> 6253 <name>GPIOB</name> 6254 <description>General-purpose I/Os</description> 6255 <groupName>GPIO</groupName> 6256 <baseAddress>0x40020400</baseAddress> 6257 <addressBlock> 6258 <offset>0x0</offset> 6259 <size>0x400</size> 6260 <usage>registers</usage> 6261 </addressBlock> 6262 <registers> 6263 <register> 6264 <name>MODER</name> 6265 <displayName>MODER</displayName> 6266 <description>GPIO port mode register</description> 6267 <addressOffset>0x0</addressOffset> 6268 <size>0x20</size> 6269 <access>read-write</access> 6270 <resetValue>0x00000280</resetValue> 6271 <fields> 6272 <field> 6273 <name>MODER15</name> 6274 <description>Port x configuration bits (y = 6275 0..15)</description> 6276 <bitOffset>30</bitOffset> 6277 <bitWidth>2</bitWidth> 6278 <enumeratedValues derivedFrom="MODER0"/> 6279 </field> 6280 <field> 6281 <name>MODER14</name> 6282 <description>Port x configuration bits (y = 6283 0..15)</description> 6284 <bitOffset>28</bitOffset> 6285 <bitWidth>2</bitWidth> 6286 <enumeratedValues derivedFrom="MODER0"/> 6287 </field> 6288 <field> 6289 <name>MODER13</name> 6290 <description>Port x configuration bits (y = 6291 0..15)</description> 6292 <bitOffset>26</bitOffset> 6293 <bitWidth>2</bitWidth> 6294 <enumeratedValues derivedFrom="MODER0"/> 6295 </field> 6296 <field> 6297 <name>MODER12</name> 6298 <description>Port x configuration bits (y = 6299 0..15)</description> 6300 <bitOffset>24</bitOffset> 6301 <bitWidth>2</bitWidth> 6302 <enumeratedValues derivedFrom="MODER0"/> 6303 </field> 6304 <field> 6305 <name>MODER11</name> 6306 <description>Port x configuration bits (y = 6307 0..15)</description> 6308 <bitOffset>22</bitOffset> 6309 <bitWidth>2</bitWidth> 6310 <enumeratedValues derivedFrom="MODER0"/> 6311 </field> 6312 <field> 6313 <name>MODER10</name> 6314 <description>Port x configuration bits (y = 6315 0..15)</description> 6316 <bitOffset>20</bitOffset> 6317 <bitWidth>2</bitWidth> 6318 <enumeratedValues derivedFrom="MODER0"/> 6319 </field> 6320 <field> 6321 <name>MODER9</name> 6322 <description>Port x configuration bits (y = 6323 0..15)</description> 6324 <bitOffset>18</bitOffset> 6325 <bitWidth>2</bitWidth> 6326 <enumeratedValues derivedFrom="MODER0"/> 6327 </field> 6328 <field> 6329 <name>MODER8</name> 6330 <description>Port x configuration bits (y = 6331 0..15)</description> 6332 <bitOffset>16</bitOffset> 6333 <bitWidth>2</bitWidth> 6334 <enumeratedValues derivedFrom="MODER0"/> 6335 </field> 6336 <field> 6337 <name>MODER7</name> 6338 <description>Port x configuration bits (y = 6339 0..15)</description> 6340 <bitOffset>14</bitOffset> 6341 <bitWidth>2</bitWidth> 6342 <enumeratedValues derivedFrom="MODER0"/> 6343 </field> 6344 <field> 6345 <name>MODER6</name> 6346 <description>Port x configuration bits (y = 6347 0..15)</description> 6348 <bitOffset>12</bitOffset> 6349 <bitWidth>2</bitWidth> 6350 <enumeratedValues derivedFrom="MODER0"/> 6351 </field> 6352 <field> 6353 <name>MODER5</name> 6354 <description>Port x configuration bits (y = 6355 0..15)</description> 6356 <bitOffset>10</bitOffset> 6357 <bitWidth>2</bitWidth> 6358 <enumeratedValues derivedFrom="MODER0"/> 6359 </field> 6360 <field> 6361 <name>MODER4</name> 6362 <description>Port x configuration bits (y = 6363 0..15)</description> 6364 <bitOffset>8</bitOffset> 6365 <bitWidth>2</bitWidth> 6366 <enumeratedValues derivedFrom="MODER0"/> 6367 </field> 6368 <field> 6369 <name>MODER3</name> 6370 <description>Port x configuration bits (y = 6371 0..15)</description> 6372 <bitOffset>6</bitOffset> 6373 <bitWidth>2</bitWidth> 6374 <enumeratedValues derivedFrom="MODER0"/> 6375 </field> 6376 <field> 6377 <name>MODER2</name> 6378 <description>Port x configuration bits (y = 6379 0..15)</description> 6380 <bitOffset>4</bitOffset> 6381 <bitWidth>2</bitWidth> 6382 <enumeratedValues derivedFrom="MODER0"/> 6383 </field> 6384 <field> 6385 <name>MODER1</name> 6386 <description>Port x configuration bits (y = 6387 0..15)</description> 6388 <bitOffset>2</bitOffset> 6389 <bitWidth>2</bitWidth> 6390 <enumeratedValues derivedFrom="MODER0"/> 6391 </field> 6392 <field> 6393 <name>MODER0</name> 6394 <description>Port x configuration bits (y = 6395 0..15)</description> 6396 <bitOffset>0</bitOffset> 6397 <bitWidth>2</bitWidth> 6398 <enumeratedValues><name>MODER0</name><usage>read-write</usage><enumeratedValue><name>Input</name><description>Input mode (reset state)</description><value>0</value></enumeratedValue><enumeratedValue><name>Output</name><description>General purpose output mode</description><value>1</value></enumeratedValue><enumeratedValue><name>Alternate</name><description>Alternate function mode</description><value>2</value></enumeratedValue><enumeratedValue><name>Analog</name><description>Analog mode</description><value>3</value></enumeratedValue></enumeratedValues> 6399 </field> 6400 </fields> 6401 </register> 6402 <register> 6403 <name>OTYPER</name> 6404 <displayName>OTYPER</displayName> 6405 <description>GPIO port output type register</description> 6406 <addressOffset>0x4</addressOffset> 6407 <size>0x20</size> 6408 <access>read-write</access> 6409 <resetValue>0x00000000</resetValue> 6410 <fields> 6411 <field> 6412 <name>OT15</name> 6413 <description>Port x configuration bits (y = 6414 0..15)</description> 6415 <bitOffset>15</bitOffset> 6416 <bitWidth>1</bitWidth> 6417 <enumeratedValues derivedFrom="OT0"/> 6418 </field> 6419 <field> 6420 <name>OT14</name> 6421 <description>Port x configuration bits (y = 6422 0..15)</description> 6423 <bitOffset>14</bitOffset> 6424 <bitWidth>1</bitWidth> 6425 <enumeratedValues derivedFrom="OT0"/> 6426 </field> 6427 <field> 6428 <name>OT13</name> 6429 <description>Port x configuration bits (y = 6430 0..15)</description> 6431 <bitOffset>13</bitOffset> 6432 <bitWidth>1</bitWidth> 6433 <enumeratedValues derivedFrom="OT0"/> 6434 </field> 6435 <field> 6436 <name>OT12</name> 6437 <description>Port x configuration bits (y = 6438 0..15)</description> 6439 <bitOffset>12</bitOffset> 6440 <bitWidth>1</bitWidth> 6441 <enumeratedValues derivedFrom="OT0"/> 6442 </field> 6443 <field> 6444 <name>OT11</name> 6445 <description>Port x configuration bits (y = 6446 0..15)</description> 6447 <bitOffset>11</bitOffset> 6448 <bitWidth>1</bitWidth> 6449 <enumeratedValues derivedFrom="OT0"/> 6450 </field> 6451 <field> 6452 <name>OT10</name> 6453 <description>Port x configuration bits (y = 6454 0..15)</description> 6455 <bitOffset>10</bitOffset> 6456 <bitWidth>1</bitWidth> 6457 <enumeratedValues derivedFrom="OT0"/> 6458 </field> 6459 <field> 6460 <name>OT9</name> 6461 <description>Port x configuration bits (y = 6462 0..15)</description> 6463 <bitOffset>9</bitOffset> 6464 <bitWidth>1</bitWidth> 6465 <enumeratedValues derivedFrom="OT0"/> 6466 </field> 6467 <field> 6468 <name>OT8</name> 6469 <description>Port x configuration bits (y = 6470 0..15)</description> 6471 <bitOffset>8</bitOffset> 6472 <bitWidth>1</bitWidth> 6473 <enumeratedValues derivedFrom="OT0"/> 6474 </field> 6475 <field> 6476 <name>OT7</name> 6477 <description>Port x configuration bits (y = 6478 0..15)</description> 6479 <bitOffset>7</bitOffset> 6480 <bitWidth>1</bitWidth> 6481 <enumeratedValues derivedFrom="OT0"/> 6482 </field> 6483 <field> 6484 <name>OT6</name> 6485 <description>Port x configuration bits (y = 6486 0..15)</description> 6487 <bitOffset>6</bitOffset> 6488 <bitWidth>1</bitWidth> 6489 <enumeratedValues derivedFrom="OT0"/> 6490 </field> 6491 <field> 6492 <name>OT5</name> 6493 <description>Port x configuration bits (y = 6494 0..15)</description> 6495 <bitOffset>5</bitOffset> 6496 <bitWidth>1</bitWidth> 6497 <enumeratedValues derivedFrom="OT0"/> 6498 </field> 6499 <field> 6500 <name>OT4</name> 6501 <description>Port x configuration bits (y = 6502 0..15)</description> 6503 <bitOffset>4</bitOffset> 6504 <bitWidth>1</bitWidth> 6505 <enumeratedValues derivedFrom="OT0"/> 6506 </field> 6507 <field> 6508 <name>OT3</name> 6509 <description>Port x configuration bits (y = 6510 0..15)</description> 6511 <bitOffset>3</bitOffset> 6512 <bitWidth>1</bitWidth> 6513 <enumeratedValues derivedFrom="OT0"/> 6514 </field> 6515 <field> 6516 <name>OT2</name> 6517 <description>Port x configuration bits (y = 6518 0..15)</description> 6519 <bitOffset>2</bitOffset> 6520 <bitWidth>1</bitWidth> 6521 <enumeratedValues derivedFrom="OT0"/> 6522 </field> 6523 <field> 6524 <name>OT1</name> 6525 <description>Port x configuration bits (y = 6526 0..15)</description> 6527 <bitOffset>1</bitOffset> 6528 <bitWidth>1</bitWidth> 6529 <enumeratedValues derivedFrom="OT0"/> 6530 </field> 6531 <field> 6532 <name>OT0</name> 6533 <description>Port x configuration bits (y = 6534 0..15)</description> 6535 <bitOffset>0</bitOffset> 6536 <bitWidth>1</bitWidth> 6537 <enumeratedValues><name>OT0</name><usage>read-write</usage><enumeratedValue><name>PushPull</name><description>Output push-pull (reset state)</description><value>0</value></enumeratedValue><enumeratedValue><name>OpenDrain</name><description>Output open-drain</description><value>1</value></enumeratedValue></enumeratedValues> 6538 </field> 6539 </fields> 6540 </register> 6541 <register> 6542 <name>OSPEEDR</name> 6543 <displayName>OSPEEDR</displayName> 6544 <description>GPIO port output speed 6545 register</description> 6546 <addressOffset>0x8</addressOffset> 6547 <size>0x20</size> 6548 <access>read-write</access> 6549 <resetValue>0x000000C0</resetValue> 6550 <fields> 6551 <field> 6552 <name>OSPEEDR15</name> 6553 <description>Port x configuration bits (y = 6554 0..15)</description> 6555 <bitOffset>30</bitOffset> 6556 <bitWidth>2</bitWidth> 6557 <enumeratedValues derivedFrom="OSPEEDR0"/> 6558 </field> 6559 <field> 6560 <name>OSPEEDR14</name> 6561 <description>Port x configuration bits (y = 6562 0..15)</description> 6563 <bitOffset>28</bitOffset> 6564 <bitWidth>2</bitWidth> 6565 <enumeratedValues derivedFrom="OSPEEDR0"/> 6566 </field> 6567 <field> 6568 <name>OSPEEDR13</name> 6569 <description>Port x configuration bits (y = 6570 0..15)</description> 6571 <bitOffset>26</bitOffset> 6572 <bitWidth>2</bitWidth> 6573 <enumeratedValues derivedFrom="OSPEEDR0"/> 6574 </field> 6575 <field> 6576 <name>OSPEEDR12</name> 6577 <description>Port x configuration bits (y = 6578 0..15)</description> 6579 <bitOffset>24</bitOffset> 6580 <bitWidth>2</bitWidth> 6581 <enumeratedValues derivedFrom="OSPEEDR0"/> 6582 </field> 6583 <field> 6584 <name>OSPEEDR11</name> 6585 <description>Port x configuration bits (y = 6586 0..15)</description> 6587 <bitOffset>22</bitOffset> 6588 <bitWidth>2</bitWidth> 6589 <enumeratedValues derivedFrom="OSPEEDR0"/> 6590 </field> 6591 <field> 6592 <name>OSPEEDR10</name> 6593 <description>Port x configuration bits (y = 6594 0..15)</description> 6595 <bitOffset>20</bitOffset> 6596 <bitWidth>2</bitWidth> 6597 <enumeratedValues derivedFrom="OSPEEDR0"/> 6598 </field> 6599 <field> 6600 <name>OSPEEDR9</name> 6601 <description>Port x configuration bits (y = 6602 0..15)</description> 6603 <bitOffset>18</bitOffset> 6604 <bitWidth>2</bitWidth> 6605 <enumeratedValues derivedFrom="OSPEEDR0"/> 6606 </field> 6607 <field> 6608 <name>OSPEEDR8</name> 6609 <description>Port x configuration bits (y = 6610 0..15)</description> 6611 <bitOffset>16</bitOffset> 6612 <bitWidth>2</bitWidth> 6613 <enumeratedValues derivedFrom="OSPEEDR0"/> 6614 </field> 6615 <field> 6616 <name>OSPEEDR7</name> 6617 <description>Port x configuration bits (y = 6618 0..15)</description> 6619 <bitOffset>14</bitOffset> 6620 <bitWidth>2</bitWidth> 6621 <enumeratedValues derivedFrom="OSPEEDR0"/> 6622 </field> 6623 <field> 6624 <name>OSPEEDR6</name> 6625 <description>Port x configuration bits (y = 6626 0..15)</description> 6627 <bitOffset>12</bitOffset> 6628 <bitWidth>2</bitWidth> 6629 <enumeratedValues derivedFrom="OSPEEDR0"/> 6630 </field> 6631 <field> 6632 <name>OSPEEDR5</name> 6633 <description>Port x configuration bits (y = 6634 0..15)</description> 6635 <bitOffset>10</bitOffset> 6636 <bitWidth>2</bitWidth> 6637 <enumeratedValues derivedFrom="OSPEEDR0"/> 6638 </field> 6639 <field> 6640 <name>OSPEEDR4</name> 6641 <description>Port x configuration bits (y = 6642 0..15)</description> 6643 <bitOffset>8</bitOffset> 6644 <bitWidth>2</bitWidth> 6645 <enumeratedValues derivedFrom="OSPEEDR0"/> 6646 </field> 6647 <field> 6648 <name>OSPEEDR3</name> 6649 <description>Port x configuration bits (y = 6650 0..15)</description> 6651 <bitOffset>6</bitOffset> 6652 <bitWidth>2</bitWidth> 6653 <enumeratedValues derivedFrom="OSPEEDR0"/> 6654 </field> 6655 <field> 6656 <name>OSPEEDR2</name> 6657 <description>Port x configuration bits (y = 6658 0..15)</description> 6659 <bitOffset>4</bitOffset> 6660 <bitWidth>2</bitWidth> 6661 <enumeratedValues derivedFrom="OSPEEDR0"/> 6662 </field> 6663 <field> 6664 <name>OSPEEDR1</name> 6665 <description>Port x configuration bits (y = 6666 0..15)</description> 6667 <bitOffset>2</bitOffset> 6668 <bitWidth>2</bitWidth> 6669 <enumeratedValues derivedFrom="OSPEEDR0"/> 6670 </field> 6671 <field> 6672 <name>OSPEEDR0</name> 6673 <description>Port x configuration bits (y = 6674 0..15)</description> 6675 <bitOffset>0</bitOffset> 6676 <bitWidth>2</bitWidth> 6677 <enumeratedValues><name>OSPEEDR0</name><usage>read-write</usage><enumeratedValue><name>LowSpeed</name><description>Low speed</description><value>0</value></enumeratedValue><enumeratedValue><name>MediumSpeed</name><description>Medium speed</description><value>1</value></enumeratedValue><enumeratedValue><name>HighSpeed</name><description>High speed</description><value>2</value></enumeratedValue><enumeratedValue><name>VeryHighSpeed</name><description>Very high speed</description><value>3</value></enumeratedValue></enumeratedValues> 6678 </field> 6679 </fields> 6680 </register> 6681 <register> 6682 <name>PUPDR</name> 6683 <displayName>PUPDR</displayName> 6684 <description>GPIO port pull-up/pull-down 6685 register</description> 6686 <addressOffset>0xC</addressOffset> 6687 <size>0x20</size> 6688 <access>read-write</access> 6689 <resetValue>0x00000100</resetValue> 6690 <fields> 6691 <field> 6692 <name>PUPDR15</name> 6693 <description>Port x configuration bits (y = 6694 0..15)</description> 6695 <bitOffset>30</bitOffset> 6696 <bitWidth>2</bitWidth> 6697 <enumeratedValues derivedFrom="PUPDR0"/> 6698 </field> 6699 <field> 6700 <name>PUPDR14</name> 6701 <description>Port x configuration bits (y = 6702 0..15)</description> 6703 <bitOffset>28</bitOffset> 6704 <bitWidth>2</bitWidth> 6705 <enumeratedValues derivedFrom="PUPDR0"/> 6706 </field> 6707 <field> 6708 <name>PUPDR13</name> 6709 <description>Port x configuration bits (y = 6710 0..15)</description> 6711 <bitOffset>26</bitOffset> 6712 <bitWidth>2</bitWidth> 6713 <enumeratedValues derivedFrom="PUPDR0"/> 6714 </field> 6715 <field> 6716 <name>PUPDR12</name> 6717 <description>Port x configuration bits (y = 6718 0..15)</description> 6719 <bitOffset>24</bitOffset> 6720 <bitWidth>2</bitWidth> 6721 <enumeratedValues derivedFrom="PUPDR0"/> 6722 </field> 6723 <field> 6724 <name>PUPDR11</name> 6725 <description>Port x configuration bits (y = 6726 0..15)</description> 6727 <bitOffset>22</bitOffset> 6728 <bitWidth>2</bitWidth> 6729 <enumeratedValues derivedFrom="PUPDR0"/> 6730 </field> 6731 <field> 6732 <name>PUPDR10</name> 6733 <description>Port x configuration bits (y = 6734 0..15)</description> 6735 <bitOffset>20</bitOffset> 6736 <bitWidth>2</bitWidth> 6737 <enumeratedValues derivedFrom="PUPDR0"/> 6738 </field> 6739 <field> 6740 <name>PUPDR9</name> 6741 <description>Port x configuration bits (y = 6742 0..15)</description> 6743 <bitOffset>18</bitOffset> 6744 <bitWidth>2</bitWidth> 6745 <enumeratedValues derivedFrom="PUPDR0"/> 6746 </field> 6747 <field> 6748 <name>PUPDR8</name> 6749 <description>Port x configuration bits (y = 6750 0..15)</description> 6751 <bitOffset>16</bitOffset> 6752 <bitWidth>2</bitWidth> 6753 <enumeratedValues derivedFrom="PUPDR0"/> 6754 </field> 6755 <field> 6756 <name>PUPDR7</name> 6757 <description>Port x configuration bits (y = 6758 0..15)</description> 6759 <bitOffset>14</bitOffset> 6760 <bitWidth>2</bitWidth> 6761 <enumeratedValues derivedFrom="PUPDR0"/> 6762 </field> 6763 <field> 6764 <name>PUPDR6</name> 6765 <description>Port x configuration bits (y = 6766 0..15)</description> 6767 <bitOffset>12</bitOffset> 6768 <bitWidth>2</bitWidth> 6769 <enumeratedValues derivedFrom="PUPDR0"/> 6770 </field> 6771 <field> 6772 <name>PUPDR5</name> 6773 <description>Port x configuration bits (y = 6774 0..15)</description> 6775 <bitOffset>10</bitOffset> 6776 <bitWidth>2</bitWidth> 6777 <enumeratedValues derivedFrom="PUPDR0"/> 6778 </field> 6779 <field> 6780 <name>PUPDR4</name> 6781 <description>Port x configuration bits (y = 6782 0..15)</description> 6783 <bitOffset>8</bitOffset> 6784 <bitWidth>2</bitWidth> 6785 <enumeratedValues derivedFrom="PUPDR0"/> 6786 </field> 6787 <field> 6788 <name>PUPDR3</name> 6789 <description>Port x configuration bits (y = 6790 0..15)</description> 6791 <bitOffset>6</bitOffset> 6792 <bitWidth>2</bitWidth> 6793 <enumeratedValues derivedFrom="PUPDR0"/> 6794 </field> 6795 <field> 6796 <name>PUPDR2</name> 6797 <description>Port x configuration bits (y = 6798 0..15)</description> 6799 <bitOffset>4</bitOffset> 6800 <bitWidth>2</bitWidth> 6801 <enumeratedValues derivedFrom="PUPDR0"/> 6802 </field> 6803 <field> 6804 <name>PUPDR1</name> 6805 <description>Port x configuration bits (y = 6806 0..15)</description> 6807 <bitOffset>2</bitOffset> 6808 <bitWidth>2</bitWidth> 6809 <enumeratedValues derivedFrom="PUPDR0"/> 6810 </field> 6811 <field> 6812 <name>PUPDR0</name> 6813 <description>Port x configuration bits (y = 6814 0..15)</description> 6815 <bitOffset>0</bitOffset> 6816 <bitWidth>2</bitWidth> 6817 <enumeratedValues><name>PUPDR0</name><usage>read-write</usage><enumeratedValue><name>Floating</name><description>No pull-up, pull-down</description><value>0</value></enumeratedValue><enumeratedValue><name>PullUp</name><description>Pull-up</description><value>1</value></enumeratedValue><enumeratedValue><name>PullDown</name><description>Pull-down</description><value>2</value></enumeratedValue></enumeratedValues> 6818 </field> 6819 </fields> 6820 </register> 6821 <register> 6822 <name>IDR</name> 6823 <displayName>IDR</displayName> 6824 <description>GPIO port input data register</description> 6825 <addressOffset>0x10</addressOffset> 6826 <size>0x20</size> 6827 <access>read-only</access> 6828 <resetValue>0x00000000</resetValue> 6829 <fields> 6830 <field> 6831 <name>IDR15</name> 6832 <description>Port input data (y = 6833 0..15)</description> 6834 <bitOffset>15</bitOffset> 6835 <bitWidth>1</bitWidth> 6836 <enumeratedValues derivedFrom="IDR0"/> 6837 </field> 6838 <field> 6839 <name>IDR14</name> 6840 <description>Port input data (y = 6841 0..15)</description> 6842 <bitOffset>14</bitOffset> 6843 <bitWidth>1</bitWidth> 6844 <enumeratedValues derivedFrom="IDR0"/> 6845 </field> 6846 <field> 6847 <name>IDR13</name> 6848 <description>Port input data (y = 6849 0..15)</description> 6850 <bitOffset>13</bitOffset> 6851 <bitWidth>1</bitWidth> 6852 <enumeratedValues derivedFrom="IDR0"/> 6853 </field> 6854 <field> 6855 <name>IDR12</name> 6856 <description>Port input data (y = 6857 0..15)</description> 6858 <bitOffset>12</bitOffset> 6859 <bitWidth>1</bitWidth> 6860 <enumeratedValues derivedFrom="IDR0"/> 6861 </field> 6862 <field> 6863 <name>IDR11</name> 6864 <description>Port input data (y = 6865 0..15)</description> 6866 <bitOffset>11</bitOffset> 6867 <bitWidth>1</bitWidth> 6868 <enumeratedValues derivedFrom="IDR0"/> 6869 </field> 6870 <field> 6871 <name>IDR10</name> 6872 <description>Port input data (y = 6873 0..15)</description> 6874 <bitOffset>10</bitOffset> 6875 <bitWidth>1</bitWidth> 6876 <enumeratedValues derivedFrom="IDR0"/> 6877 </field> 6878 <field> 6879 <name>IDR9</name> 6880 <description>Port input data (y = 6881 0..15)</description> 6882 <bitOffset>9</bitOffset> 6883 <bitWidth>1</bitWidth> 6884 <enumeratedValues derivedFrom="IDR0"/> 6885 </field> 6886 <field> 6887 <name>IDR8</name> 6888 <description>Port input data (y = 6889 0..15)</description> 6890 <bitOffset>8</bitOffset> 6891 <bitWidth>1</bitWidth> 6892 <enumeratedValues derivedFrom="IDR0"/> 6893 </field> 6894 <field> 6895 <name>IDR7</name> 6896 <description>Port input data (y = 6897 0..15)</description> 6898 <bitOffset>7</bitOffset> 6899 <bitWidth>1</bitWidth> 6900 <enumeratedValues derivedFrom="IDR0"/> 6901 </field> 6902 <field> 6903 <name>IDR6</name> 6904 <description>Port input data (y = 6905 0..15)</description> 6906 <bitOffset>6</bitOffset> 6907 <bitWidth>1</bitWidth> 6908 <enumeratedValues derivedFrom="IDR0"/> 6909 </field> 6910 <field> 6911 <name>IDR5</name> 6912 <description>Port input data (y = 6913 0..15)</description> 6914 <bitOffset>5</bitOffset> 6915 <bitWidth>1</bitWidth> 6916 <enumeratedValues derivedFrom="IDR0"/> 6917 </field> 6918 <field> 6919 <name>IDR4</name> 6920 <description>Port input data (y = 6921 0..15)</description> 6922 <bitOffset>4</bitOffset> 6923 <bitWidth>1</bitWidth> 6924 <enumeratedValues derivedFrom="IDR0"/> 6925 </field> 6926 <field> 6927 <name>IDR3</name> 6928 <description>Port input data (y = 6929 0..15)</description> 6930 <bitOffset>3</bitOffset> 6931 <bitWidth>1</bitWidth> 6932 <enumeratedValues derivedFrom="IDR0"/> 6933 </field> 6934 <field> 6935 <name>IDR2</name> 6936 <description>Port input data (y = 6937 0..15)</description> 6938 <bitOffset>2</bitOffset> 6939 <bitWidth>1</bitWidth> 6940 <enumeratedValues derivedFrom="IDR0"/> 6941 </field> 6942 <field> 6943 <name>IDR1</name> 6944 <description>Port input data (y = 6945 0..15)</description> 6946 <bitOffset>1</bitOffset> 6947 <bitWidth>1</bitWidth> 6948 <enumeratedValues derivedFrom="IDR0"/> 6949 </field> 6950 <field> 6951 <name>IDR0</name> 6952 <description>Port input data (y = 6953 0..15)</description> 6954 <bitOffset>0</bitOffset> 6955 <bitWidth>1</bitWidth> 6956 <enumeratedValues><name>IDR0</name><usage>read-write</usage><enumeratedValue><name>High</name><description>Input is logic high</description><value>1</value></enumeratedValue><enumeratedValue><name>Low</name><description>Input is logic low</description><value>0</value></enumeratedValue></enumeratedValues> 6957 </field> 6958 </fields> 6959 </register> 6960 <register> 6961 <name>ODR</name> 6962 <displayName>ODR</displayName> 6963 <description>GPIO port output data register</description> 6964 <addressOffset>0x14</addressOffset> 6965 <size>0x20</size> 6966 <access>read-write</access> 6967 <resetValue>0x00000000</resetValue> 6968 <fields> 6969 <field> 6970 <name>ODR15</name> 6971 <description>Port output data (y = 6972 0..15)</description> 6973 <bitOffset>15</bitOffset> 6974 <bitWidth>1</bitWidth> 6975 <enumeratedValues derivedFrom="ODR0"/> 6976 </field> 6977 <field> 6978 <name>ODR14</name> 6979 <description>Port output data (y = 6980 0..15)</description> 6981 <bitOffset>14</bitOffset> 6982 <bitWidth>1</bitWidth> 6983 <enumeratedValues derivedFrom="ODR0"/> 6984 </field> 6985 <field> 6986 <name>ODR13</name> 6987 <description>Port output data (y = 6988 0..15)</description> 6989 <bitOffset>13</bitOffset> 6990 <bitWidth>1</bitWidth> 6991 <enumeratedValues derivedFrom="ODR0"/> 6992 </field> 6993 <field> 6994 <name>ODR12</name> 6995 <description>Port output data (y = 6996 0..15)</description> 6997 <bitOffset>12</bitOffset> 6998 <bitWidth>1</bitWidth> 6999 <enumeratedValues derivedFrom="ODR0"/> 7000 </field> 7001 <field> 7002 <name>ODR11</name> 7003 <description>Port output data (y = 7004 0..15)</description> 7005 <bitOffset>11</bitOffset> 7006 <bitWidth>1</bitWidth> 7007 <enumeratedValues derivedFrom="ODR0"/> 7008 </field> 7009 <field> 7010 <name>ODR10</name> 7011 <description>Port output data (y = 7012 0..15)</description> 7013 <bitOffset>10</bitOffset> 7014 <bitWidth>1</bitWidth> 7015 <enumeratedValues derivedFrom="ODR0"/> 7016 </field> 7017 <field> 7018 <name>ODR9</name> 7019 <description>Port output data (y = 7020 0..15)</description> 7021 <bitOffset>9</bitOffset> 7022 <bitWidth>1</bitWidth> 7023 <enumeratedValues derivedFrom="ODR0"/> 7024 </field> 7025 <field> 7026 <name>ODR8</name> 7027 <description>Port output data (y = 7028 0..15)</description> 7029 <bitOffset>8</bitOffset> 7030 <bitWidth>1</bitWidth> 7031 <enumeratedValues derivedFrom="ODR0"/> 7032 </field> 7033 <field> 7034 <name>ODR7</name> 7035 <description>Port output data (y = 7036 0..15)</description> 7037 <bitOffset>7</bitOffset> 7038 <bitWidth>1</bitWidth> 7039 <enumeratedValues derivedFrom="ODR0"/> 7040 </field> 7041 <field> 7042 <name>ODR6</name> 7043 <description>Port output data (y = 7044 0..15)</description> 7045 <bitOffset>6</bitOffset> 7046 <bitWidth>1</bitWidth> 7047 <enumeratedValues derivedFrom="ODR0"/> 7048 </field> 7049 <field> 7050 <name>ODR5</name> 7051 <description>Port output data (y = 7052 0..15)</description> 7053 <bitOffset>5</bitOffset> 7054 <bitWidth>1</bitWidth> 7055 <enumeratedValues derivedFrom="ODR0"/> 7056 </field> 7057 <field> 7058 <name>ODR4</name> 7059 <description>Port output data (y = 7060 0..15)</description> 7061 <bitOffset>4</bitOffset> 7062 <bitWidth>1</bitWidth> 7063 <enumeratedValues derivedFrom="ODR0"/> 7064 </field> 7065 <field> 7066 <name>ODR3</name> 7067 <description>Port output data (y = 7068 0..15)</description> 7069 <bitOffset>3</bitOffset> 7070 <bitWidth>1</bitWidth> 7071 <enumeratedValues derivedFrom="ODR0"/> 7072 </field> 7073 <field> 7074 <name>ODR2</name> 7075 <description>Port output data (y = 7076 0..15)</description> 7077 <bitOffset>2</bitOffset> 7078 <bitWidth>1</bitWidth> 7079 <enumeratedValues derivedFrom="ODR0"/> 7080 </field> 7081 <field> 7082 <name>ODR1</name> 7083 <description>Port output data (y = 7084 0..15)</description> 7085 <bitOffset>1</bitOffset> 7086 <bitWidth>1</bitWidth> 7087 <enumeratedValues derivedFrom="ODR0"/> 7088 </field> 7089 <field> 7090 <name>ODR0</name> 7091 <description>Port output data (y = 7092 0..15)</description> 7093 <bitOffset>0</bitOffset> 7094 <bitWidth>1</bitWidth> 7095 <enumeratedValues><name>ODR0</name><usage>read-write</usage><enumeratedValue><name>High</name><description>Set output to logic high</description><value>1</value></enumeratedValue><enumeratedValue><name>Low</name><description>Set output to logic low</description><value>0</value></enumeratedValue></enumeratedValues> 7096 </field> 7097 </fields> 7098 </register> 7099 <register> 7100 <name>BSRR</name> 7101 <displayName>BSRR</displayName> 7102 <description>GPIO port bit set/reset 7103 register</description> 7104 <addressOffset>0x18</addressOffset> 7105 <size>0x20</size> 7106 <access>write-only</access> 7107 <resetValue>0x00000000</resetValue> 7108 <fields> 7109 <field> 7110 <name>BR15</name> 7111 <description>Port x reset bit y (y = 7112 0..15)</description> 7113 <bitOffset>31</bitOffset> 7114 <bitWidth>1</bitWidth> 7115 <enumeratedValues derivedFrom="BR0W"/> 7116 </field> 7117 <field> 7118 <name>BR14</name> 7119 <description>Port x reset bit y (y = 7120 0..15)</description> 7121 <bitOffset>30</bitOffset> 7122 <bitWidth>1</bitWidth> 7123 <enumeratedValues derivedFrom="BR0W"/> 7124 </field> 7125 <field> 7126 <name>BR13</name> 7127 <description>Port x reset bit y (y = 7128 0..15)</description> 7129 <bitOffset>29</bitOffset> 7130 <bitWidth>1</bitWidth> 7131 <enumeratedValues derivedFrom="BR0W"/> 7132 </field> 7133 <field> 7134 <name>BR12</name> 7135 <description>Port x reset bit y (y = 7136 0..15)</description> 7137 <bitOffset>28</bitOffset> 7138 <bitWidth>1</bitWidth> 7139 <enumeratedValues derivedFrom="BR0W"/> 7140 </field> 7141 <field> 7142 <name>BR11</name> 7143 <description>Port x reset bit y (y = 7144 0..15)</description> 7145 <bitOffset>27</bitOffset> 7146 <bitWidth>1</bitWidth> 7147 <enumeratedValues derivedFrom="BR0W"/> 7148 </field> 7149 <field> 7150 <name>BR10</name> 7151 <description>Port x reset bit y (y = 7152 0..15)</description> 7153 <bitOffset>26</bitOffset> 7154 <bitWidth>1</bitWidth> 7155 <enumeratedValues derivedFrom="BR0W"/> 7156 </field> 7157 <field> 7158 <name>BR9</name> 7159 <description>Port x reset bit y (y = 7160 0..15)</description> 7161 <bitOffset>25</bitOffset> 7162 <bitWidth>1</bitWidth> 7163 <enumeratedValues derivedFrom="BR0W"/> 7164 </field> 7165 <field> 7166 <name>BR8</name> 7167 <description>Port x reset bit y (y = 7168 0..15)</description> 7169 <bitOffset>24</bitOffset> 7170 <bitWidth>1</bitWidth> 7171 <enumeratedValues derivedFrom="BR0W"/> 7172 </field> 7173 <field> 7174 <name>BR7</name> 7175 <description>Port x reset bit y (y = 7176 0..15)</description> 7177 <bitOffset>23</bitOffset> 7178 <bitWidth>1</bitWidth> 7179 <enumeratedValues derivedFrom="BR0W"/> 7180 </field> 7181 <field> 7182 <name>BR6</name> 7183 <description>Port x reset bit y (y = 7184 0..15)</description> 7185 <bitOffset>22</bitOffset> 7186 <bitWidth>1</bitWidth> 7187 <enumeratedValues derivedFrom="BR0W"/> 7188 </field> 7189 <field> 7190 <name>BR5</name> 7191 <description>Port x reset bit y (y = 7192 0..15)</description> 7193 <bitOffset>21</bitOffset> 7194 <bitWidth>1</bitWidth> 7195 <enumeratedValues derivedFrom="BR0W"/> 7196 </field> 7197 <field> 7198 <name>BR4</name> 7199 <description>Port x reset bit y (y = 7200 0..15)</description> 7201 <bitOffset>20</bitOffset> 7202 <bitWidth>1</bitWidth> 7203 <enumeratedValues derivedFrom="BR0W"/> 7204 </field> 7205 <field> 7206 <name>BR3</name> 7207 <description>Port x reset bit y (y = 7208 0..15)</description> 7209 <bitOffset>19</bitOffset> 7210 <bitWidth>1</bitWidth> 7211 <enumeratedValues derivedFrom="BR0W"/> 7212 </field> 7213 <field> 7214 <name>BR2</name> 7215 <description>Port x reset bit y (y = 7216 0..15)</description> 7217 <bitOffset>18</bitOffset> 7218 <bitWidth>1</bitWidth> 7219 <enumeratedValues derivedFrom="BR0W"/> 7220 </field> 7221 <field> 7222 <name>BR1</name> 7223 <description>Port x reset bit y (y = 7224 0..15)</description> 7225 <bitOffset>17</bitOffset> 7226 <bitWidth>1</bitWidth> 7227 <enumeratedValues derivedFrom="BR0W"/> 7228 </field> 7229 <field> 7230 <name>BR0</name> 7231 <description>Port x set bit y (y= 7232 0..15)</description> 7233 <bitOffset>16</bitOffset> 7234 <bitWidth>1</bitWidth> 7235 <enumeratedValues><name>BR0W</name><usage>write</usage><enumeratedValue><name>Reset</name><description>Resets the corresponding ODRx bit</description><value>1</value></enumeratedValue></enumeratedValues> 7236 </field> 7237 <field> 7238 <name>BS15</name> 7239 <description>Port x set bit y (y= 7240 0..15)</description> 7241 <bitOffset>15</bitOffset> 7242 <bitWidth>1</bitWidth> 7243 <enumeratedValues derivedFrom="BS0W"/> 7244 </field> 7245 <field> 7246 <name>BS14</name> 7247 <description>Port x set bit y (y= 7248 0..15)</description> 7249 <bitOffset>14</bitOffset> 7250 <bitWidth>1</bitWidth> 7251 <enumeratedValues derivedFrom="BS0W"/> 7252 </field> 7253 <field> 7254 <name>BS13</name> 7255 <description>Port x set bit y (y= 7256 0..15)</description> 7257 <bitOffset>13</bitOffset> 7258 <bitWidth>1</bitWidth> 7259 <enumeratedValues derivedFrom="BS0W"/> 7260 </field> 7261 <field> 7262 <name>BS12</name> 7263 <description>Port x set bit y (y= 7264 0..15)</description> 7265 <bitOffset>12</bitOffset> 7266 <bitWidth>1</bitWidth> 7267 <enumeratedValues derivedFrom="BS0W"/> 7268 </field> 7269 <field> 7270 <name>BS11</name> 7271 <description>Port x set bit y (y= 7272 0..15)</description> 7273 <bitOffset>11</bitOffset> 7274 <bitWidth>1</bitWidth> 7275 <enumeratedValues derivedFrom="BS0W"/> 7276 </field> 7277 <field> 7278 <name>BS10</name> 7279 <description>Port x set bit y (y= 7280 0..15)</description> 7281 <bitOffset>10</bitOffset> 7282 <bitWidth>1</bitWidth> 7283 <enumeratedValues derivedFrom="BS0W"/> 7284 </field> 7285 <field> 7286 <name>BS9</name> 7287 <description>Port x set bit y (y= 7288 0..15)</description> 7289 <bitOffset>9</bitOffset> 7290 <bitWidth>1</bitWidth> 7291 <enumeratedValues derivedFrom="BS0W"/> 7292 </field> 7293 <field> 7294 <name>BS8</name> 7295 <description>Port x set bit y (y= 7296 0..15)</description> 7297 <bitOffset>8</bitOffset> 7298 <bitWidth>1</bitWidth> 7299 <enumeratedValues derivedFrom="BS0W"/> 7300 </field> 7301 <field> 7302 <name>BS7</name> 7303 <description>Port x set bit y (y= 7304 0..15)</description> 7305 <bitOffset>7</bitOffset> 7306 <bitWidth>1</bitWidth> 7307 <enumeratedValues derivedFrom="BS0W"/> 7308 </field> 7309 <field> 7310 <name>BS6</name> 7311 <description>Port x set bit y (y= 7312 0..15)</description> 7313 <bitOffset>6</bitOffset> 7314 <bitWidth>1</bitWidth> 7315 <enumeratedValues derivedFrom="BS0W"/> 7316 </field> 7317 <field> 7318 <name>BS5</name> 7319 <description>Port x set bit y (y= 7320 0..15)</description> 7321 <bitOffset>5</bitOffset> 7322 <bitWidth>1</bitWidth> 7323 <enumeratedValues derivedFrom="BS0W"/> 7324 </field> 7325 <field> 7326 <name>BS4</name> 7327 <description>Port x set bit y (y= 7328 0..15)</description> 7329 <bitOffset>4</bitOffset> 7330 <bitWidth>1</bitWidth> 7331 <enumeratedValues derivedFrom="BS0W"/> 7332 </field> 7333 <field> 7334 <name>BS3</name> 7335 <description>Port x set bit y (y= 7336 0..15)</description> 7337 <bitOffset>3</bitOffset> 7338 <bitWidth>1</bitWidth> 7339 <enumeratedValues derivedFrom="BS0W"/> 7340 </field> 7341 <field> 7342 <name>BS2</name> 7343 <description>Port x set bit y (y= 7344 0..15)</description> 7345 <bitOffset>2</bitOffset> 7346 <bitWidth>1</bitWidth> 7347 <enumeratedValues derivedFrom="BS0W"/> 7348 </field> 7349 <field> 7350 <name>BS1</name> 7351 <description>Port x set bit y (y= 7352 0..15)</description> 7353 <bitOffset>1</bitOffset> 7354 <bitWidth>1</bitWidth> 7355 <enumeratedValues derivedFrom="BS0W"/> 7356 </field> 7357 <field> 7358 <name>BS0</name> 7359 <description>Port x set bit y (y= 7360 0..15)</description> 7361 <bitOffset>0</bitOffset> 7362 <bitWidth>1</bitWidth> 7363 <enumeratedValues><name>BS0W</name><usage>write</usage><enumeratedValue><name>Set</name><description>Sets the corresponding ODRx bit</description><value>1</value></enumeratedValue></enumeratedValues> 7364 </field> 7365 </fields> 7366 </register> 7367 <register> 7368 <name>LCKR</name> 7369 <displayName>LCKR</displayName> 7370 <description>GPIO port configuration lock 7371 register</description> 7372 <addressOffset>0x1C</addressOffset> 7373 <size>0x20</size> 7374 <access>read-write</access> 7375 <resetValue>0x00000000</resetValue> 7376 <fields> 7377 <field> 7378 <name>LCKK</name> 7379 <description>Port x lock bit y (y= 7380 0..15)</description> 7381 <bitOffset>16</bitOffset> 7382 <bitWidth>1</bitWidth> 7383 <enumeratedValues><name>LCKK</name><usage>read-write</usage><enumeratedValue><name>NotActive</name><description>Port configuration lock key not active</description><value>0</value></enumeratedValue><enumeratedValue><name>Active</name><description>Port configuration lock key active</description><value>1</value></enumeratedValue></enumeratedValues> 7384 </field> 7385 <field> 7386 <name>LCK15</name> 7387 <description>Port x lock bit y (y= 7388 0..15)</description> 7389 <bitOffset>15</bitOffset> 7390 <bitWidth>1</bitWidth> 7391 <enumeratedValues derivedFrom="LCK10"/> 7392 </field> 7393 <field> 7394 <name>LCK14</name> 7395 <description>Port x lock bit y (y= 7396 0..15)</description> 7397 <bitOffset>14</bitOffset> 7398 <bitWidth>1</bitWidth> 7399 <enumeratedValues derivedFrom="LCK10"/> 7400 </field> 7401 <field> 7402 <name>LCK13</name> 7403 <description>Port x lock bit y (y= 7404 0..15)</description> 7405 <bitOffset>13</bitOffset> 7406 <bitWidth>1</bitWidth> 7407 <enumeratedValues derivedFrom="LCK10"/> 7408 </field> 7409 <field> 7410 <name>LCK12</name> 7411 <description>Port x lock bit y (y= 7412 0..15)</description> 7413 <bitOffset>12</bitOffset> 7414 <bitWidth>1</bitWidth> 7415 <enumeratedValues derivedFrom="LCK10"/> 7416 </field> 7417 <field> 7418 <name>LCK11</name> 7419 <description>Port x lock bit y (y= 7420 0..15)</description> 7421 <bitOffset>11</bitOffset> 7422 <bitWidth>1</bitWidth> 7423 <enumeratedValues derivedFrom="LCK10"/> 7424 </field> 7425 <field> 7426 <name>LCK10</name> 7427 <description>Port x lock bit y (y= 7428 0..15)</description> 7429 <bitOffset>10</bitOffset> 7430 <bitWidth>1</bitWidth> 7431 <enumeratedValues><name>LCK10</name><usage>read-write</usage><enumeratedValue><name>Unlocked</name><description>Port configuration not locked</description><value>0</value></enumeratedValue><enumeratedValue><name>Locked</name><description>Port configuration locked</description><value>1</value></enumeratedValue></enumeratedValues> 7432 </field> 7433 <field> 7434 <name>LCK9</name> 7435 <description>Port x lock bit y (y= 7436 0..15)</description> 7437 <bitOffset>9</bitOffset> 7438 <bitWidth>1</bitWidth> 7439 <enumeratedValues derivedFrom="LCK0"/> 7440 </field> 7441 <field> 7442 <name>LCK8</name> 7443 <description>Port x lock bit y (y= 7444 0..15)</description> 7445 <bitOffset>8</bitOffset> 7446 <bitWidth>1</bitWidth> 7447 <enumeratedValues derivedFrom="LCK0"/> 7448 </field> 7449 <field> 7450 <name>LCK7</name> 7451 <description>Port x lock bit y (y= 7452 0..15)</description> 7453 <bitOffset>7</bitOffset> 7454 <bitWidth>1</bitWidth> 7455 <enumeratedValues derivedFrom="LCK0"/> 7456 </field> 7457 <field> 7458 <name>LCK6</name> 7459 <description>Port x lock bit y (y= 7460 0..15)</description> 7461 <bitOffset>6</bitOffset> 7462 <bitWidth>1</bitWidth> 7463 <enumeratedValues derivedFrom="LCK0"/> 7464 </field> 7465 <field> 7466 <name>LCK5</name> 7467 <description>Port x lock bit y (y= 7468 0..15)</description> 7469 <bitOffset>5</bitOffset> 7470 <bitWidth>1</bitWidth> 7471 <enumeratedValues derivedFrom="LCK0"/> 7472 </field> 7473 <field> 7474 <name>LCK4</name> 7475 <description>Port x lock bit y (y= 7476 0..15)</description> 7477 <bitOffset>4</bitOffset> 7478 <bitWidth>1</bitWidth> 7479 <enumeratedValues derivedFrom="LCK0"/> 7480 </field> 7481 <field> 7482 <name>LCK3</name> 7483 <description>Port x lock bit y (y= 7484 0..15)</description> 7485 <bitOffset>3</bitOffset> 7486 <bitWidth>1</bitWidth> 7487 <enumeratedValues derivedFrom="LCK0"/> 7488 </field> 7489 <field> 7490 <name>LCK2</name> 7491 <description>Port x lock bit y (y= 7492 0..15)</description> 7493 <bitOffset>2</bitOffset> 7494 <bitWidth>1</bitWidth> 7495 <enumeratedValues derivedFrom="LCK0"/> 7496 </field> 7497 <field> 7498 <name>LCK1</name> 7499 <description>Port x lock bit y (y= 7500 0..15)</description> 7501 <bitOffset>1</bitOffset> 7502 <bitWidth>1</bitWidth> 7503 <enumeratedValues derivedFrom="LCK0"/> 7504 </field> 7505 <field> 7506 <name>LCK0</name> 7507 <description>Port x lock bit y (y= 7508 0..15)</description> 7509 <bitOffset>0</bitOffset> 7510 <bitWidth>1</bitWidth> 7511 <enumeratedValues><name>LCK0</name><usage>read-write</usage><enumeratedValue><name>Unlocked</name><description>Port configuration not locked</description><value>0</value></enumeratedValue><enumeratedValue><name>Locked</name><description>Port configuration locked</description><value>1</value></enumeratedValue></enumeratedValues> 7512 </field> 7513 </fields> 7514 </register> 7515 <register> 7516 <name>AFRL</name> 7517 <displayName>AFRL</displayName> 7518 <description>GPIO alternate function low 7519 register</description> 7520 <addressOffset>0x20</addressOffset> 7521 <size>0x20</size> 7522 <access>read-write</access> 7523 <resetValue>0x00000000</resetValue> 7524 <fields> 7525 <field> 7526 <name>AFRL7</name> 7527 <description>Alternate function selection for port x 7528 bit y (y = 0..7)</description> 7529 <bitOffset>28</bitOffset> 7530 <bitWidth>4</bitWidth> 7531 <enumeratedValues derivedFrom="AFRL0"/> 7532 </field> 7533 <field> 7534 <name>AFRL6</name> 7535 <description>Alternate function selection for port x 7536 bit y (y = 0..7)</description> 7537 <bitOffset>24</bitOffset> 7538 <bitWidth>4</bitWidth> 7539 <enumeratedValues derivedFrom="AFRL0"/> 7540 </field> 7541 <field> 7542 <name>AFRL5</name> 7543 <description>Alternate function selection for port x 7544 bit y (y = 0..7)</description> 7545 <bitOffset>20</bitOffset> 7546 <bitWidth>4</bitWidth> 7547 <enumeratedValues derivedFrom="AFRL0"/> 7548 </field> 7549 <field> 7550 <name>AFRL4</name> 7551 <description>Alternate function selection for port x 7552 bit y (y = 0..7)</description> 7553 <bitOffset>16</bitOffset> 7554 <bitWidth>4</bitWidth> 7555 <enumeratedValues derivedFrom="AFRL0"/> 7556 </field> 7557 <field> 7558 <name>AFRL3</name> 7559 <description>Alternate function selection for port x 7560 bit y (y = 0..7)</description> 7561 <bitOffset>12</bitOffset> 7562 <bitWidth>4</bitWidth> 7563 <enumeratedValues derivedFrom="AFRL0"/> 7564 </field> 7565 <field> 7566 <name>AFRL2</name> 7567 <description>Alternate function selection for port x 7568 bit y (y = 0..7)</description> 7569 <bitOffset>8</bitOffset> 7570 <bitWidth>4</bitWidth> 7571 <enumeratedValues derivedFrom="AFRL0"/> 7572 </field> 7573 <field> 7574 <name>AFRL1</name> 7575 <description>Alternate function selection for port x 7576 bit y (y = 0..7)</description> 7577 <bitOffset>4</bitOffset> 7578 <bitWidth>4</bitWidth> 7579 <enumeratedValues derivedFrom="AFRL0"/> 7580 </field> 7581 <field> 7582 <name>AFRL0</name> 7583 <description>Alternate function selection for port x 7584 bit y (y = 0..7)</description> 7585 <bitOffset>0</bitOffset> 7586 <bitWidth>4</bitWidth> 7587 <enumeratedValues><name>AFRL0</name><usage>read-write</usage><enumeratedValue><name>AF0</name><description>AF0</description><value>0</value></enumeratedValue><enumeratedValue><name>AF1</name><description>AF1</description><value>1</value></enumeratedValue><enumeratedValue><name>AF2</name><description>AF2</description><value>2</value></enumeratedValue><enumeratedValue><name>AF3</name><description>AF3</description><value>3</value></enumeratedValue><enumeratedValue><name>AF4</name><description>AF4</description><value>4</value></enumeratedValue><enumeratedValue><name>AF5</name><description>AF5</description><value>5</value></enumeratedValue><enumeratedValue><name>AF6</name><description>AF6</description><value>6</value></enumeratedValue><enumeratedValue><name>AF7</name><description>AF7</description><value>7</value></enumeratedValue><enumeratedValue><name>AF8</name><description>AF8</description><value>8</value></enumeratedValue><enumeratedValue><name>AF9</name><description>AF9</description><value>9</value></enumeratedValue><enumeratedValue><name>AF10</name><description>AF10</description><value>10</value></enumeratedValue><enumeratedValue><name>AF11</name><description>AF11</description><value>11</value></enumeratedValue><enumeratedValue><name>AF12</name><description>AF12</description><value>12</value></enumeratedValue><enumeratedValue><name>AF13</name><description>AF13</description><value>13</value></enumeratedValue><enumeratedValue><name>AF14</name><description>AF14</description><value>14</value></enumeratedValue><enumeratedValue><name>AF15</name><description>AF15</description><value>15</value></enumeratedValue></enumeratedValues> 7588 </field> 7589 </fields> 7590 </register> 7591 <register> 7592 <name>AFRH</name> 7593 <displayName>AFRH</displayName> 7594 <description>GPIO alternate function high 7595 register</description> 7596 <addressOffset>0x24</addressOffset> 7597 <size>0x20</size> 7598 <access>read-write</access> 7599 <resetValue>0x00000000</resetValue> 7600 <fields> 7601 <field> 7602 <name>AFRH15</name> 7603 <description>Alternate function selection for port x 7604 bit y (y = 8..15)</description> 7605 <bitOffset>28</bitOffset> 7606 <bitWidth>4</bitWidth> 7607 <enumeratedValues derivedFrom="AFRH8"/> 7608 </field> 7609 <field> 7610 <name>AFRH14</name> 7611 <description>Alternate function selection for port x 7612 bit y (y = 8..15)</description> 7613 <bitOffset>24</bitOffset> 7614 <bitWidth>4</bitWidth> 7615 <enumeratedValues derivedFrom="AFRH8"/> 7616 </field> 7617 <field> 7618 <name>AFRH13</name> 7619 <description>Alternate function selection for port x 7620 bit y (y = 8..15)</description> 7621 <bitOffset>20</bitOffset> 7622 <bitWidth>4</bitWidth> 7623 <enumeratedValues derivedFrom="AFRH8"/> 7624 </field> 7625 <field> 7626 <name>AFRH12</name> 7627 <description>Alternate function selection for port x 7628 bit y (y = 8..15)</description> 7629 <bitOffset>16</bitOffset> 7630 <bitWidth>4</bitWidth> 7631 <enumeratedValues derivedFrom="AFRH8"/> 7632 </field> 7633 <field> 7634 <name>AFRH11</name> 7635 <description>Alternate function selection for port x 7636 bit y (y = 8..15)</description> 7637 <bitOffset>12</bitOffset> 7638 <bitWidth>4</bitWidth> 7639 <enumeratedValues derivedFrom="AFRH8"/> 7640 </field> 7641 <field> 7642 <name>AFRH10</name> 7643 <description>Alternate function selection for port x 7644 bit y (y = 8..15)</description> 7645 <bitOffset>8</bitOffset> 7646 <bitWidth>4</bitWidth> 7647 <enumeratedValues derivedFrom="AFRH8"/> 7648 </field> 7649 <field> 7650 <name>AFRH9</name> 7651 <description>Alternate function selection for port x 7652 bit y (y = 8..15)</description> 7653 <bitOffset>4</bitOffset> 7654 <bitWidth>4</bitWidth> 7655 <enumeratedValues derivedFrom="AFRH8"/> 7656 </field> 7657 <field> 7658 <name>AFRH8</name> 7659 <description>Alternate function selection for port x 7660 bit y (y = 8..15)</description> 7661 <bitOffset>0</bitOffset> 7662 <bitWidth>4</bitWidth> 7663 <enumeratedValues><name>AFRH8</name><usage>read-write</usage><enumeratedValue><name>AF0</name><description>AF0</description><value>0</value></enumeratedValue><enumeratedValue><name>AF1</name><description>AF1</description><value>1</value></enumeratedValue><enumeratedValue><name>AF2</name><description>AF2</description><value>2</value></enumeratedValue><enumeratedValue><name>AF3</name><description>AF3</description><value>3</value></enumeratedValue><enumeratedValue><name>AF4</name><description>AF4</description><value>4</value></enumeratedValue><enumeratedValue><name>AF5</name><description>AF5</description><value>5</value></enumeratedValue><enumeratedValue><name>AF6</name><description>AF6</description><value>6</value></enumeratedValue><enumeratedValue><name>AF7</name><description>AF7</description><value>7</value></enumeratedValue><enumeratedValue><name>AF8</name><description>AF8</description><value>8</value></enumeratedValue><enumeratedValue><name>AF9</name><description>AF9</description><value>9</value></enumeratedValue><enumeratedValue><name>AF10</name><description>AF10</description><value>10</value></enumeratedValue><enumeratedValue><name>AF11</name><description>AF11</description><value>11</value></enumeratedValue><enumeratedValue><name>AF12</name><description>AF12</description><value>12</value></enumeratedValue><enumeratedValue><name>AF13</name><description>AF13</description><value>13</value></enumeratedValue><enumeratedValue><name>AF14</name><description>AF14</description><value>14</value></enumeratedValue><enumeratedValue><name>AF15</name><description>AF15</description><value>15</value></enumeratedValue></enumeratedValues> 7664 </field> 7665 </fields> 7666 </register> 7667 </registers> 7668 </peripheral> 7669 <peripheral> 7670 <name>GPIOA</name> 7671 <description>General-purpose I/Os</description> 7672 <groupName>GPIO</groupName> 7673 <baseAddress>0x40020000</baseAddress> 7674 <addressBlock> 7675 <offset>0x0</offset> 7676 <size>0x400</size> 7677 <usage>registers</usage> 7678 </addressBlock> 7679 <registers> 7680 <register> 7681 <name>MODER</name> 7682 <displayName>MODER</displayName> 7683 <description>GPIO port mode register</description> 7684 <addressOffset>0x0</addressOffset> 7685 <size>0x20</size> 7686 <access>read-write</access> 7687 <resetValue>0xA8000000</resetValue> 7688 <fields> 7689 <field> 7690 <name>MODER15</name> 7691 <description>Port x configuration bits (y = 7692 0..15)</description> 7693 <bitOffset>30</bitOffset> 7694 <bitWidth>2</bitWidth> 7695 <enumeratedValues derivedFrom="MODER0"/> 7696 </field> 7697 <field> 7698 <name>MODER14</name> 7699 <description>Port x configuration bits (y = 7700 0..15)</description> 7701 <bitOffset>28</bitOffset> 7702 <bitWidth>2</bitWidth> 7703 <enumeratedValues derivedFrom="MODER0"/> 7704 </field> 7705 <field> 7706 <name>MODER13</name> 7707 <description>Port x configuration bits (y = 7708 0..15)</description> 7709 <bitOffset>26</bitOffset> 7710 <bitWidth>2</bitWidth> 7711 <enumeratedValues derivedFrom="MODER0"/> 7712 </field> 7713 <field> 7714 <name>MODER12</name> 7715 <description>Port x configuration bits (y = 7716 0..15)</description> 7717 <bitOffset>24</bitOffset> 7718 <bitWidth>2</bitWidth> 7719 <enumeratedValues derivedFrom="MODER0"/> 7720 </field> 7721 <field> 7722 <name>MODER11</name> 7723 <description>Port x configuration bits (y = 7724 0..15)</description> 7725 <bitOffset>22</bitOffset> 7726 <bitWidth>2</bitWidth> 7727 <enumeratedValues derivedFrom="MODER0"/> 7728 </field> 7729 <field> 7730 <name>MODER10</name> 7731 <description>Port x configuration bits (y = 7732 0..15)</description> 7733 <bitOffset>20</bitOffset> 7734 <bitWidth>2</bitWidth> 7735 <enumeratedValues derivedFrom="MODER0"/> 7736 </field> 7737 <field> 7738 <name>MODER9</name> 7739 <description>Port x configuration bits (y = 7740 0..15)</description> 7741 <bitOffset>18</bitOffset> 7742 <bitWidth>2</bitWidth> 7743 <enumeratedValues derivedFrom="MODER0"/> 7744 </field> 7745 <field> 7746 <name>MODER8</name> 7747 <description>Port x configuration bits (y = 7748 0..15)</description> 7749 <bitOffset>16</bitOffset> 7750 <bitWidth>2</bitWidth> 7751 <enumeratedValues derivedFrom="MODER0"/> 7752 </field> 7753 <field> 7754 <name>MODER7</name> 7755 <description>Port x configuration bits (y = 7756 0..15)</description> 7757 <bitOffset>14</bitOffset> 7758 <bitWidth>2</bitWidth> 7759 <enumeratedValues derivedFrom="MODER0"/> 7760 </field> 7761 <field> 7762 <name>MODER6</name> 7763 <description>Port x configuration bits (y = 7764 0..15)</description> 7765 <bitOffset>12</bitOffset> 7766 <bitWidth>2</bitWidth> 7767 <enumeratedValues derivedFrom="MODER0"/> 7768 </field> 7769 <field> 7770 <name>MODER5</name> 7771 <description>Port x configuration bits (y = 7772 0..15)</description> 7773 <bitOffset>10</bitOffset> 7774 <bitWidth>2</bitWidth> 7775 <enumeratedValues derivedFrom="MODER0"/> 7776 </field> 7777 <field> 7778 <name>MODER4</name> 7779 <description>Port x configuration bits (y = 7780 0..15)</description> 7781 <bitOffset>8</bitOffset> 7782 <bitWidth>2</bitWidth> 7783 <enumeratedValues derivedFrom="MODER0"/> 7784 </field> 7785 <field> 7786 <name>MODER3</name> 7787 <description>Port x configuration bits (y = 7788 0..15)</description> 7789 <bitOffset>6</bitOffset> 7790 <bitWidth>2</bitWidth> 7791 <enumeratedValues derivedFrom="MODER0"/> 7792 </field> 7793 <field> 7794 <name>MODER2</name> 7795 <description>Port x configuration bits (y = 7796 0..15)</description> 7797 <bitOffset>4</bitOffset> 7798 <bitWidth>2</bitWidth> 7799 <enumeratedValues derivedFrom="MODER0"/> 7800 </field> 7801 <field> 7802 <name>MODER1</name> 7803 <description>Port x configuration bits (y = 7804 0..15)</description> 7805 <bitOffset>2</bitOffset> 7806 <bitWidth>2</bitWidth> 7807 <enumeratedValues derivedFrom="MODER0"/> 7808 </field> 7809 <field> 7810 <name>MODER0</name> 7811 <description>Port x configuration bits (y = 7812 0..15)</description> 7813 <bitOffset>0</bitOffset> 7814 <bitWidth>2</bitWidth> 7815 <enumeratedValues><name>MODER0</name><usage>read-write</usage><enumeratedValue><name>Input</name><description>Input mode (reset state)</description><value>0</value></enumeratedValue><enumeratedValue><name>Output</name><description>General purpose output mode</description><value>1</value></enumeratedValue><enumeratedValue><name>Alternate</name><description>Alternate function mode</description><value>2</value></enumeratedValue><enumeratedValue><name>Analog</name><description>Analog mode</description><value>3</value></enumeratedValue></enumeratedValues> 7816 </field> 7817 </fields> 7818 </register> 7819 <register> 7820 <name>OTYPER</name> 7821 <displayName>OTYPER</displayName> 7822 <description>GPIO port output type register</description> 7823 <addressOffset>0x4</addressOffset> 7824 <size>0x20</size> 7825 <access>read-write</access> 7826 <resetValue>0x00000000</resetValue> 7827 <fields> 7828 <field> 7829 <name>OT15</name> 7830 <description>Port x configuration bits (y = 7831 0..15)</description> 7832 <bitOffset>15</bitOffset> 7833 <bitWidth>1</bitWidth> 7834 <enumeratedValues derivedFrom="OT0"/> 7835 </field> 7836 <field> 7837 <name>OT14</name> 7838 <description>Port x configuration bits (y = 7839 0..15)</description> 7840 <bitOffset>14</bitOffset> 7841 <bitWidth>1</bitWidth> 7842 <enumeratedValues derivedFrom="OT0"/> 7843 </field> 7844 <field> 7845 <name>OT13</name> 7846 <description>Port x configuration bits (y = 7847 0..15)</description> 7848 <bitOffset>13</bitOffset> 7849 <bitWidth>1</bitWidth> 7850 <enumeratedValues derivedFrom="OT0"/> 7851 </field> 7852 <field> 7853 <name>OT12</name> 7854 <description>Port x configuration bits (y = 7855 0..15)</description> 7856 <bitOffset>12</bitOffset> 7857 <bitWidth>1</bitWidth> 7858 <enumeratedValues derivedFrom="OT0"/> 7859 </field> 7860 <field> 7861 <name>OT11</name> 7862 <description>Port x configuration bits (y = 7863 0..15)</description> 7864 <bitOffset>11</bitOffset> 7865 <bitWidth>1</bitWidth> 7866 <enumeratedValues derivedFrom="OT0"/> 7867 </field> 7868 <field> 7869 <name>OT10</name> 7870 <description>Port x configuration bits (y = 7871 0..15)</description> 7872 <bitOffset>10</bitOffset> 7873 <bitWidth>1</bitWidth> 7874 <enumeratedValues derivedFrom="OT0"/> 7875 </field> 7876 <field> 7877 <name>OT9</name> 7878 <description>Port x configuration bits (y = 7879 0..15)</description> 7880 <bitOffset>9</bitOffset> 7881 <bitWidth>1</bitWidth> 7882 <enumeratedValues derivedFrom="OT0"/> 7883 </field> 7884 <field> 7885 <name>OT8</name> 7886 <description>Port x configuration bits (y = 7887 0..15)</description> 7888 <bitOffset>8</bitOffset> 7889 <bitWidth>1</bitWidth> 7890 <enumeratedValues derivedFrom="OT0"/> 7891 </field> 7892 <field> 7893 <name>OT7</name> 7894 <description>Port x configuration bits (y = 7895 0..15)</description> 7896 <bitOffset>7</bitOffset> 7897 <bitWidth>1</bitWidth> 7898 <enumeratedValues derivedFrom="OT0"/> 7899 </field> 7900 <field> 7901 <name>OT6</name> 7902 <description>Port x configuration bits (y = 7903 0..15)</description> 7904 <bitOffset>6</bitOffset> 7905 <bitWidth>1</bitWidth> 7906 <enumeratedValues derivedFrom="OT0"/> 7907 </field> 7908 <field> 7909 <name>OT5</name> 7910 <description>Port x configuration bits (y = 7911 0..15)</description> 7912 <bitOffset>5</bitOffset> 7913 <bitWidth>1</bitWidth> 7914 <enumeratedValues derivedFrom="OT0"/> 7915 </field> 7916 <field> 7917 <name>OT4</name> 7918 <description>Port x configuration bits (y = 7919 0..15)</description> 7920 <bitOffset>4</bitOffset> 7921 <bitWidth>1</bitWidth> 7922 <enumeratedValues derivedFrom="OT0"/> 7923 </field> 7924 <field> 7925 <name>OT3</name> 7926 <description>Port x configuration bits (y = 7927 0..15)</description> 7928 <bitOffset>3</bitOffset> 7929 <bitWidth>1</bitWidth> 7930 <enumeratedValues derivedFrom="OT0"/> 7931 </field> 7932 <field> 7933 <name>OT2</name> 7934 <description>Port x configuration bits (y = 7935 0..15)</description> 7936 <bitOffset>2</bitOffset> 7937 <bitWidth>1</bitWidth> 7938 <enumeratedValues derivedFrom="OT0"/> 7939 </field> 7940 <field> 7941 <name>OT1</name> 7942 <description>Port x configuration bits (y = 7943 0..15)</description> 7944 <bitOffset>1</bitOffset> 7945 <bitWidth>1</bitWidth> 7946 <enumeratedValues derivedFrom="OT0"/> 7947 </field> 7948 <field> 7949 <name>OT0</name> 7950 <description>Port x configuration bits (y = 7951 0..15)</description> 7952 <bitOffset>0</bitOffset> 7953 <bitWidth>1</bitWidth> 7954 <enumeratedValues><name>OT0</name><usage>read-write</usage><enumeratedValue><name>PushPull</name><description>Output push-pull (reset state)</description><value>0</value></enumeratedValue><enumeratedValue><name>OpenDrain</name><description>Output open-drain</description><value>1</value></enumeratedValue></enumeratedValues> 7955 </field> 7956 </fields> 7957 </register> 7958 <register> 7959 <name>OSPEEDR</name> 7960 <displayName>OSPEEDR</displayName> 7961 <description>GPIO port output speed 7962 register</description> 7963 <addressOffset>0x8</addressOffset> 7964 <size>0x20</size> 7965 <access>read-write</access> 7966 <resetValue>0x00000000</resetValue> 7967 <fields> 7968 <field> 7969 <name>OSPEEDR15</name> 7970 <description>Port x configuration bits (y = 7971 0..15)</description> 7972 <bitOffset>30</bitOffset> 7973 <bitWidth>2</bitWidth> 7974 <enumeratedValues derivedFrom="OSPEEDR0"/> 7975 </field> 7976 <field> 7977 <name>OSPEEDR14</name> 7978 <description>Port x configuration bits (y = 7979 0..15)</description> 7980 <bitOffset>28</bitOffset> 7981 <bitWidth>2</bitWidth> 7982 <enumeratedValues derivedFrom="OSPEEDR0"/> 7983 </field> 7984 <field> 7985 <name>OSPEEDR13</name> 7986 <description>Port x configuration bits (y = 7987 0..15)</description> 7988 <bitOffset>26</bitOffset> 7989 <bitWidth>2</bitWidth> 7990 <enumeratedValues derivedFrom="OSPEEDR0"/> 7991 </field> 7992 <field> 7993 <name>OSPEEDR12</name> 7994 <description>Port x configuration bits (y = 7995 0..15)</description> 7996 <bitOffset>24</bitOffset> 7997 <bitWidth>2</bitWidth> 7998 <enumeratedValues derivedFrom="OSPEEDR0"/> 7999 </field> 8000 <field> 8001 <name>OSPEEDR11</name> 8002 <description>Port x configuration bits (y = 8003 0..15)</description> 8004 <bitOffset>22</bitOffset> 8005 <bitWidth>2</bitWidth> 8006 <enumeratedValues derivedFrom="OSPEEDR0"/> 8007 </field> 8008 <field> 8009 <name>OSPEEDR10</name> 8010 <description>Port x configuration bits (y = 8011 0..15)</description> 8012 <bitOffset>20</bitOffset> 8013 <bitWidth>2</bitWidth> 8014 <enumeratedValues derivedFrom="OSPEEDR0"/> 8015 </field> 8016 <field> 8017 <name>OSPEEDR9</name> 8018 <description>Port x configuration bits (y = 8019 0..15)</description> 8020 <bitOffset>18</bitOffset> 8021 <bitWidth>2</bitWidth> 8022 <enumeratedValues derivedFrom="OSPEEDR0"/> 8023 </field> 8024 <field> 8025 <name>OSPEEDR8</name> 8026 <description>Port x configuration bits (y = 8027 0..15)</description> 8028 <bitOffset>16</bitOffset> 8029 <bitWidth>2</bitWidth> 8030 <enumeratedValues derivedFrom="OSPEEDR0"/> 8031 </field> 8032 <field> 8033 <name>OSPEEDR7</name> 8034 <description>Port x configuration bits (y = 8035 0..15)</description> 8036 <bitOffset>14</bitOffset> 8037 <bitWidth>2</bitWidth> 8038 <enumeratedValues derivedFrom="OSPEEDR0"/> 8039 </field> 8040 <field> 8041 <name>OSPEEDR6</name> 8042 <description>Port x configuration bits (y = 8043 0..15)</description> 8044 <bitOffset>12</bitOffset> 8045 <bitWidth>2</bitWidth> 8046 <enumeratedValues derivedFrom="OSPEEDR0"/> 8047 </field> 8048 <field> 8049 <name>OSPEEDR5</name> 8050 <description>Port x configuration bits (y = 8051 0..15)</description> 8052 <bitOffset>10</bitOffset> 8053 <bitWidth>2</bitWidth> 8054 <enumeratedValues derivedFrom="OSPEEDR0"/> 8055 </field> 8056 <field> 8057 <name>OSPEEDR4</name> 8058 <description>Port x configuration bits (y = 8059 0..15)</description> 8060 <bitOffset>8</bitOffset> 8061 <bitWidth>2</bitWidth> 8062 <enumeratedValues derivedFrom="OSPEEDR0"/> 8063 </field> 8064 <field> 8065 <name>OSPEEDR3</name> 8066 <description>Port x configuration bits (y = 8067 0..15)</description> 8068 <bitOffset>6</bitOffset> 8069 <bitWidth>2</bitWidth> 8070 <enumeratedValues derivedFrom="OSPEEDR0"/> 8071 </field> 8072 <field> 8073 <name>OSPEEDR2</name> 8074 <description>Port x configuration bits (y = 8075 0..15)</description> 8076 <bitOffset>4</bitOffset> 8077 <bitWidth>2</bitWidth> 8078 <enumeratedValues derivedFrom="OSPEEDR0"/> 8079 </field> 8080 <field> 8081 <name>OSPEEDR1</name> 8082 <description>Port x configuration bits (y = 8083 0..15)</description> 8084 <bitOffset>2</bitOffset> 8085 <bitWidth>2</bitWidth> 8086 <enumeratedValues derivedFrom="OSPEEDR0"/> 8087 </field> 8088 <field> 8089 <name>OSPEEDR0</name> 8090 <description>Port x configuration bits (y = 8091 0..15)</description> 8092 <bitOffset>0</bitOffset> 8093 <bitWidth>2</bitWidth> 8094 <enumeratedValues><name>OSPEEDR0</name><usage>read-write</usage><enumeratedValue><name>LowSpeed</name><description>Low speed</description><value>0</value></enumeratedValue><enumeratedValue><name>MediumSpeed</name><description>Medium speed</description><value>1</value></enumeratedValue><enumeratedValue><name>HighSpeed</name><description>High speed</description><value>2</value></enumeratedValue><enumeratedValue><name>VeryHighSpeed</name><description>Very high speed</description><value>3</value></enumeratedValue></enumeratedValues> 8095 </field> 8096 </fields> 8097 </register> 8098 <register> 8099 <name>PUPDR</name> 8100 <displayName>PUPDR</displayName> 8101 <description>GPIO port pull-up/pull-down 8102 register</description> 8103 <addressOffset>0xC</addressOffset> 8104 <size>0x20</size> 8105 <access>read-write</access> 8106 <resetValue>0x64000000</resetValue> 8107 <fields> 8108 <field> 8109 <name>PUPDR15</name> 8110 <description>Port x configuration bits (y = 8111 0..15)</description> 8112 <bitOffset>30</bitOffset> 8113 <bitWidth>2</bitWidth> 8114 <enumeratedValues derivedFrom="PUPDR0"/> 8115 </field> 8116 <field> 8117 <name>PUPDR14</name> 8118 <description>Port x configuration bits (y = 8119 0..15)</description> 8120 <bitOffset>28</bitOffset> 8121 <bitWidth>2</bitWidth> 8122 <enumeratedValues derivedFrom="PUPDR0"/> 8123 </field> 8124 <field> 8125 <name>PUPDR13</name> 8126 <description>Port x configuration bits (y = 8127 0..15)</description> 8128 <bitOffset>26</bitOffset> 8129 <bitWidth>2</bitWidth> 8130 <enumeratedValues derivedFrom="PUPDR0"/> 8131 </field> 8132 <field> 8133 <name>PUPDR12</name> 8134 <description>Port x configuration bits (y = 8135 0..15)</description> 8136 <bitOffset>24</bitOffset> 8137 <bitWidth>2</bitWidth> 8138 <enumeratedValues derivedFrom="PUPDR0"/> 8139 </field> 8140 <field> 8141 <name>PUPDR11</name> 8142 <description>Port x configuration bits (y = 8143 0..15)</description> 8144 <bitOffset>22</bitOffset> 8145 <bitWidth>2</bitWidth> 8146 <enumeratedValues derivedFrom="PUPDR0"/> 8147 </field> 8148 <field> 8149 <name>PUPDR10</name> 8150 <description>Port x configuration bits (y = 8151 0..15)</description> 8152 <bitOffset>20</bitOffset> 8153 <bitWidth>2</bitWidth> 8154 <enumeratedValues derivedFrom="PUPDR0"/> 8155 </field> 8156 <field> 8157 <name>PUPDR9</name> 8158 <description>Port x configuration bits (y = 8159 0..15)</description> 8160 <bitOffset>18</bitOffset> 8161 <bitWidth>2</bitWidth> 8162 <enumeratedValues derivedFrom="PUPDR0"/> 8163 </field> 8164 <field> 8165 <name>PUPDR8</name> 8166 <description>Port x configuration bits (y = 8167 0..15)</description> 8168 <bitOffset>16</bitOffset> 8169 <bitWidth>2</bitWidth> 8170 <enumeratedValues derivedFrom="PUPDR0"/> 8171 </field> 8172 <field> 8173 <name>PUPDR7</name> 8174 <description>Port x configuration bits (y = 8175 0..15)</description> 8176 <bitOffset>14</bitOffset> 8177 <bitWidth>2</bitWidth> 8178 <enumeratedValues derivedFrom="PUPDR0"/> 8179 </field> 8180 <field> 8181 <name>PUPDR6</name> 8182 <description>Port x configuration bits (y = 8183 0..15)</description> 8184 <bitOffset>12</bitOffset> 8185 <bitWidth>2</bitWidth> 8186 <enumeratedValues derivedFrom="PUPDR0"/> 8187 </field> 8188 <field> 8189 <name>PUPDR5</name> 8190 <description>Port x configuration bits (y = 8191 0..15)</description> 8192 <bitOffset>10</bitOffset> 8193 <bitWidth>2</bitWidth> 8194 <enumeratedValues derivedFrom="PUPDR0"/> 8195 </field> 8196 <field> 8197 <name>PUPDR4</name> 8198 <description>Port x configuration bits (y = 8199 0..15)</description> 8200 <bitOffset>8</bitOffset> 8201 <bitWidth>2</bitWidth> 8202 <enumeratedValues derivedFrom="PUPDR0"/> 8203 </field> 8204 <field> 8205 <name>PUPDR3</name> 8206 <description>Port x configuration bits (y = 8207 0..15)</description> 8208 <bitOffset>6</bitOffset> 8209 <bitWidth>2</bitWidth> 8210 <enumeratedValues derivedFrom="PUPDR0"/> 8211 </field> 8212 <field> 8213 <name>PUPDR2</name> 8214 <description>Port x configuration bits (y = 8215 0..15)</description> 8216 <bitOffset>4</bitOffset> 8217 <bitWidth>2</bitWidth> 8218 <enumeratedValues derivedFrom="PUPDR0"/> 8219 </field> 8220 <field> 8221 <name>PUPDR1</name> 8222 <description>Port x configuration bits (y = 8223 0..15)</description> 8224 <bitOffset>2</bitOffset> 8225 <bitWidth>2</bitWidth> 8226 <enumeratedValues derivedFrom="PUPDR0"/> 8227 </field> 8228 <field> 8229 <name>PUPDR0</name> 8230 <description>Port x configuration bits (y = 8231 0..15)</description> 8232 <bitOffset>0</bitOffset> 8233 <bitWidth>2</bitWidth> 8234 <enumeratedValues><name>PUPDR0</name><usage>read-write</usage><enumeratedValue><name>Floating</name><description>No pull-up, pull-down</description><value>0</value></enumeratedValue><enumeratedValue><name>PullUp</name><description>Pull-up</description><value>1</value></enumeratedValue><enumeratedValue><name>PullDown</name><description>Pull-down</description><value>2</value></enumeratedValue></enumeratedValues> 8235 </field> 8236 </fields> 8237 </register> 8238 <register> 8239 <name>IDR</name> 8240 <displayName>IDR</displayName> 8241 <description>GPIO port input data register</description> 8242 <addressOffset>0x10</addressOffset> 8243 <size>0x20</size> 8244 <access>read-only</access> 8245 <resetValue>0x00000000</resetValue> 8246 <fields> 8247 <field> 8248 <name>IDR15</name> 8249 <description>Port input data (y = 8250 0..15)</description> 8251 <bitOffset>15</bitOffset> 8252 <bitWidth>1</bitWidth> 8253 <enumeratedValues derivedFrom="IDR0"/> 8254 </field> 8255 <field> 8256 <name>IDR14</name> 8257 <description>Port input data (y = 8258 0..15)</description> 8259 <bitOffset>14</bitOffset> 8260 <bitWidth>1</bitWidth> 8261 <enumeratedValues derivedFrom="IDR0"/> 8262 </field> 8263 <field> 8264 <name>IDR13</name> 8265 <description>Port input data (y = 8266 0..15)</description> 8267 <bitOffset>13</bitOffset> 8268 <bitWidth>1</bitWidth> 8269 <enumeratedValues derivedFrom="IDR0"/> 8270 </field> 8271 <field> 8272 <name>IDR12</name> 8273 <description>Port input data (y = 8274 0..15)</description> 8275 <bitOffset>12</bitOffset> 8276 <bitWidth>1</bitWidth> 8277 <enumeratedValues derivedFrom="IDR0"/> 8278 </field> 8279 <field> 8280 <name>IDR11</name> 8281 <description>Port input data (y = 8282 0..15)</description> 8283 <bitOffset>11</bitOffset> 8284 <bitWidth>1</bitWidth> 8285 <enumeratedValues derivedFrom="IDR0"/> 8286 </field> 8287 <field> 8288 <name>IDR10</name> 8289 <description>Port input data (y = 8290 0..15)</description> 8291 <bitOffset>10</bitOffset> 8292 <bitWidth>1</bitWidth> 8293 <enumeratedValues derivedFrom="IDR0"/> 8294 </field> 8295 <field> 8296 <name>IDR9</name> 8297 <description>Port input data (y = 8298 0..15)</description> 8299 <bitOffset>9</bitOffset> 8300 <bitWidth>1</bitWidth> 8301 <enumeratedValues derivedFrom="IDR0"/> 8302 </field> 8303 <field> 8304 <name>IDR8</name> 8305 <description>Port input data (y = 8306 0..15)</description> 8307 <bitOffset>8</bitOffset> 8308 <bitWidth>1</bitWidth> 8309 <enumeratedValues derivedFrom="IDR0"/> 8310 </field> 8311 <field> 8312 <name>IDR7</name> 8313 <description>Port input data (y = 8314 0..15)</description> 8315 <bitOffset>7</bitOffset> 8316 <bitWidth>1</bitWidth> 8317 <enumeratedValues derivedFrom="IDR0"/> 8318 </field> 8319 <field> 8320 <name>IDR6</name> 8321 <description>Port input data (y = 8322 0..15)</description> 8323 <bitOffset>6</bitOffset> 8324 <bitWidth>1</bitWidth> 8325 <enumeratedValues derivedFrom="IDR0"/> 8326 </field> 8327 <field> 8328 <name>IDR5</name> 8329 <description>Port input data (y = 8330 0..15)</description> 8331 <bitOffset>5</bitOffset> 8332 <bitWidth>1</bitWidth> 8333 <enumeratedValues derivedFrom="IDR0"/> 8334 </field> 8335 <field> 8336 <name>IDR4</name> 8337 <description>Port input data (y = 8338 0..15)</description> 8339 <bitOffset>4</bitOffset> 8340 <bitWidth>1</bitWidth> 8341 <enumeratedValues derivedFrom="IDR0"/> 8342 </field> 8343 <field> 8344 <name>IDR3</name> 8345 <description>Port input data (y = 8346 0..15)</description> 8347 <bitOffset>3</bitOffset> 8348 <bitWidth>1</bitWidth> 8349 <enumeratedValues derivedFrom="IDR0"/> 8350 </field> 8351 <field> 8352 <name>IDR2</name> 8353 <description>Port input data (y = 8354 0..15)</description> 8355 <bitOffset>2</bitOffset> 8356 <bitWidth>1</bitWidth> 8357 <enumeratedValues derivedFrom="IDR0"/> 8358 </field> 8359 <field> 8360 <name>IDR1</name> 8361 <description>Port input data (y = 8362 0..15)</description> 8363 <bitOffset>1</bitOffset> 8364 <bitWidth>1</bitWidth> 8365 <enumeratedValues derivedFrom="IDR0"/> 8366 </field> 8367 <field> 8368 <name>IDR0</name> 8369 <description>Port input data (y = 8370 0..15)</description> 8371 <bitOffset>0</bitOffset> 8372 <bitWidth>1</bitWidth> 8373 <enumeratedValues><name>IDR0</name><usage>read-write</usage><enumeratedValue><name>High</name><description>Input is logic high</description><value>1</value></enumeratedValue><enumeratedValue><name>Low</name><description>Input is logic low</description><value>0</value></enumeratedValue></enumeratedValues> 8374 </field> 8375 </fields> 8376 </register> 8377 <register> 8378 <name>ODR</name> 8379 <displayName>ODR</displayName> 8380 <description>GPIO port output data register</description> 8381 <addressOffset>0x14</addressOffset> 8382 <size>0x20</size> 8383 <access>read-write</access> 8384 <resetValue>0x00000000</resetValue> 8385 <fields> 8386 <field> 8387 <name>ODR15</name> 8388 <description>Port output data (y = 8389 0..15)</description> 8390 <bitOffset>15</bitOffset> 8391 <bitWidth>1</bitWidth> 8392 <enumeratedValues derivedFrom="ODR0"/> 8393 </field> 8394 <field> 8395 <name>ODR14</name> 8396 <description>Port output data (y = 8397 0..15)</description> 8398 <bitOffset>14</bitOffset> 8399 <bitWidth>1</bitWidth> 8400 <enumeratedValues derivedFrom="ODR0"/> 8401 </field> 8402 <field> 8403 <name>ODR13</name> 8404 <description>Port output data (y = 8405 0..15)</description> 8406 <bitOffset>13</bitOffset> 8407 <bitWidth>1</bitWidth> 8408 <enumeratedValues derivedFrom="ODR0"/> 8409 </field> 8410 <field> 8411 <name>ODR12</name> 8412 <description>Port output data (y = 8413 0..15)</description> 8414 <bitOffset>12</bitOffset> 8415 <bitWidth>1</bitWidth> 8416 <enumeratedValues derivedFrom="ODR0"/> 8417 </field> 8418 <field> 8419 <name>ODR11</name> 8420 <description>Port output data (y = 8421 0..15)</description> 8422 <bitOffset>11</bitOffset> 8423 <bitWidth>1</bitWidth> 8424 <enumeratedValues derivedFrom="ODR0"/> 8425 </field> 8426 <field> 8427 <name>ODR10</name> 8428 <description>Port output data (y = 8429 0..15)</description> 8430 <bitOffset>10</bitOffset> 8431 <bitWidth>1</bitWidth> 8432 <enumeratedValues derivedFrom="ODR0"/> 8433 </field> 8434 <field> 8435 <name>ODR9</name> 8436 <description>Port output data (y = 8437 0..15)</description> 8438 <bitOffset>9</bitOffset> 8439 <bitWidth>1</bitWidth> 8440 <enumeratedValues derivedFrom="ODR0"/> 8441 </field> 8442 <field> 8443 <name>ODR8</name> 8444 <description>Port output data (y = 8445 0..15)</description> 8446 <bitOffset>8</bitOffset> 8447 <bitWidth>1</bitWidth> 8448 <enumeratedValues derivedFrom="ODR0"/> 8449 </field> 8450 <field> 8451 <name>ODR7</name> 8452 <description>Port output data (y = 8453 0..15)</description> 8454 <bitOffset>7</bitOffset> 8455 <bitWidth>1</bitWidth> 8456 <enumeratedValues derivedFrom="ODR0"/> 8457 </field> 8458 <field> 8459 <name>ODR6</name> 8460 <description>Port output data (y = 8461 0..15)</description> 8462 <bitOffset>6</bitOffset> 8463 <bitWidth>1</bitWidth> 8464 <enumeratedValues derivedFrom="ODR0"/> 8465 </field> 8466 <field> 8467 <name>ODR5</name> 8468 <description>Port output data (y = 8469 0..15)</description> 8470 <bitOffset>5</bitOffset> 8471 <bitWidth>1</bitWidth> 8472 <enumeratedValues derivedFrom="ODR0"/> 8473 </field> 8474 <field> 8475 <name>ODR4</name> 8476 <description>Port output data (y = 8477 0..15)</description> 8478 <bitOffset>4</bitOffset> 8479 <bitWidth>1</bitWidth> 8480 <enumeratedValues derivedFrom="ODR0"/> 8481 </field> 8482 <field> 8483 <name>ODR3</name> 8484 <description>Port output data (y = 8485 0..15)</description> 8486 <bitOffset>3</bitOffset> 8487 <bitWidth>1</bitWidth> 8488 <enumeratedValues derivedFrom="ODR0"/> 8489 </field> 8490 <field> 8491 <name>ODR2</name> 8492 <description>Port output data (y = 8493 0..15)</description> 8494 <bitOffset>2</bitOffset> 8495 <bitWidth>1</bitWidth> 8496 <enumeratedValues derivedFrom="ODR0"/> 8497 </field> 8498 <field> 8499 <name>ODR1</name> 8500 <description>Port output data (y = 8501 0..15)</description> 8502 <bitOffset>1</bitOffset> 8503 <bitWidth>1</bitWidth> 8504 <enumeratedValues derivedFrom="ODR0"/> 8505 </field> 8506 <field> 8507 <name>ODR0</name> 8508 <description>Port output data (y = 8509 0..15)</description> 8510 <bitOffset>0</bitOffset> 8511 <bitWidth>1</bitWidth> 8512 <enumeratedValues><name>ODR0</name><usage>read-write</usage><enumeratedValue><name>High</name><description>Set output to logic high</description><value>1</value></enumeratedValue><enumeratedValue><name>Low</name><description>Set output to logic low</description><value>0</value></enumeratedValue></enumeratedValues> 8513 </field> 8514 </fields> 8515 </register> 8516 <register> 8517 <name>BSRR</name> 8518 <displayName>BSRR</displayName> 8519 <description>GPIO port bit set/reset 8520 register</description> 8521 <addressOffset>0x18</addressOffset> 8522 <size>0x20</size> 8523 <access>write-only</access> 8524 <resetValue>0x00000000</resetValue> 8525 <fields> 8526 <field> 8527 <name>BR15</name> 8528 <description>Port x reset bit y (y = 8529 0..15)</description> 8530 <bitOffset>31</bitOffset> 8531 <bitWidth>1</bitWidth> 8532 <enumeratedValues derivedFrom="BR0W"/> 8533 </field> 8534 <field> 8535 <name>BR14</name> 8536 <description>Port x reset bit y (y = 8537 0..15)</description> 8538 <bitOffset>30</bitOffset> 8539 <bitWidth>1</bitWidth> 8540 <enumeratedValues derivedFrom="BR0W"/> 8541 </field> 8542 <field> 8543 <name>BR13</name> 8544 <description>Port x reset bit y (y = 8545 0..15)</description> 8546 <bitOffset>29</bitOffset> 8547 <bitWidth>1</bitWidth> 8548 <enumeratedValues derivedFrom="BR0W"/> 8549 </field> 8550 <field> 8551 <name>BR12</name> 8552 <description>Port x reset bit y (y = 8553 0..15)</description> 8554 <bitOffset>28</bitOffset> 8555 <bitWidth>1</bitWidth> 8556 <enumeratedValues derivedFrom="BR0W"/> 8557 </field> 8558 <field> 8559 <name>BR11</name> 8560 <description>Port x reset bit y (y = 8561 0..15)</description> 8562 <bitOffset>27</bitOffset> 8563 <bitWidth>1</bitWidth> 8564 <enumeratedValues derivedFrom="BR0W"/> 8565 </field> 8566 <field> 8567 <name>BR10</name> 8568 <description>Port x reset bit y (y = 8569 0..15)</description> 8570 <bitOffset>26</bitOffset> 8571 <bitWidth>1</bitWidth> 8572 <enumeratedValues derivedFrom="BR0W"/> 8573 </field> 8574 <field> 8575 <name>BR9</name> 8576 <description>Port x reset bit y (y = 8577 0..15)</description> 8578 <bitOffset>25</bitOffset> 8579 <bitWidth>1</bitWidth> 8580 <enumeratedValues derivedFrom="BR0W"/> 8581 </field> 8582 <field> 8583 <name>BR8</name> 8584 <description>Port x reset bit y (y = 8585 0..15)</description> 8586 <bitOffset>24</bitOffset> 8587 <bitWidth>1</bitWidth> 8588 <enumeratedValues derivedFrom="BR0W"/> 8589 </field> 8590 <field> 8591 <name>BR7</name> 8592 <description>Port x reset bit y (y = 8593 0..15)</description> 8594 <bitOffset>23</bitOffset> 8595 <bitWidth>1</bitWidth> 8596 <enumeratedValues derivedFrom="BR0W"/> 8597 </field> 8598 <field> 8599 <name>BR6</name> 8600 <description>Port x reset bit y (y = 8601 0..15)</description> 8602 <bitOffset>22</bitOffset> 8603 <bitWidth>1</bitWidth> 8604 <enumeratedValues derivedFrom="BR0W"/> 8605 </field> 8606 <field> 8607 <name>BR5</name> 8608 <description>Port x reset bit y (y = 8609 0..15)</description> 8610 <bitOffset>21</bitOffset> 8611 <bitWidth>1</bitWidth> 8612 <enumeratedValues derivedFrom="BR0W"/> 8613 </field> 8614 <field> 8615 <name>BR4</name> 8616 <description>Port x reset bit y (y = 8617 0..15)</description> 8618 <bitOffset>20</bitOffset> 8619 <bitWidth>1</bitWidth> 8620 <enumeratedValues derivedFrom="BR0W"/> 8621 </field> 8622 <field> 8623 <name>BR3</name> 8624 <description>Port x reset bit y (y = 8625 0..15)</description> 8626 <bitOffset>19</bitOffset> 8627 <bitWidth>1</bitWidth> 8628 <enumeratedValues derivedFrom="BR0W"/> 8629 </field> 8630 <field> 8631 <name>BR2</name> 8632 <description>Port x reset bit y (y = 8633 0..15)</description> 8634 <bitOffset>18</bitOffset> 8635 <bitWidth>1</bitWidth> 8636 <enumeratedValues derivedFrom="BR0W"/> 8637 </field> 8638 <field> 8639 <name>BR1</name> 8640 <description>Port x reset bit y (y = 8641 0..15)</description> 8642 <bitOffset>17</bitOffset> 8643 <bitWidth>1</bitWidth> 8644 <enumeratedValues derivedFrom="BR0W"/> 8645 </field> 8646 <field> 8647 <name>BR0</name> 8648 <description>Port x set bit y (y= 8649 0..15)</description> 8650 <bitOffset>16</bitOffset> 8651 <bitWidth>1</bitWidth> 8652 <enumeratedValues><name>BR0W</name><usage>write</usage><enumeratedValue><name>Reset</name><description>Resets the corresponding ODRx bit</description><value>1</value></enumeratedValue></enumeratedValues> 8653 </field> 8654 <field> 8655 <name>BS15</name> 8656 <description>Port x set bit y (y= 8657 0..15)</description> 8658 <bitOffset>15</bitOffset> 8659 <bitWidth>1</bitWidth> 8660 <enumeratedValues derivedFrom="BS0W"/> 8661 </field> 8662 <field> 8663 <name>BS14</name> 8664 <description>Port x set bit y (y= 8665 0..15)</description> 8666 <bitOffset>14</bitOffset> 8667 <bitWidth>1</bitWidth> 8668 <enumeratedValues derivedFrom="BS0W"/> 8669 </field> 8670 <field> 8671 <name>BS13</name> 8672 <description>Port x set bit y (y= 8673 0..15)</description> 8674 <bitOffset>13</bitOffset> 8675 <bitWidth>1</bitWidth> 8676 <enumeratedValues derivedFrom="BS0W"/> 8677 </field> 8678 <field> 8679 <name>BS12</name> 8680 <description>Port x set bit y (y= 8681 0..15)</description> 8682 <bitOffset>12</bitOffset> 8683 <bitWidth>1</bitWidth> 8684 <enumeratedValues derivedFrom="BS0W"/> 8685 </field> 8686 <field> 8687 <name>BS11</name> 8688 <description>Port x set bit y (y= 8689 0..15)</description> 8690 <bitOffset>11</bitOffset> 8691 <bitWidth>1</bitWidth> 8692 <enumeratedValues derivedFrom="BS0W"/> 8693 </field> 8694 <field> 8695 <name>BS10</name> 8696 <description>Port x set bit y (y= 8697 0..15)</description> 8698 <bitOffset>10</bitOffset> 8699 <bitWidth>1</bitWidth> 8700 <enumeratedValues derivedFrom="BS0W"/> 8701 </field> 8702 <field> 8703 <name>BS9</name> 8704 <description>Port x set bit y (y= 8705 0..15)</description> 8706 <bitOffset>9</bitOffset> 8707 <bitWidth>1</bitWidth> 8708 <enumeratedValues derivedFrom="BS0W"/> 8709 </field> 8710 <field> 8711 <name>BS8</name> 8712 <description>Port x set bit y (y= 8713 0..15)</description> 8714 <bitOffset>8</bitOffset> 8715 <bitWidth>1</bitWidth> 8716 <enumeratedValues derivedFrom="BS0W"/> 8717 </field> 8718 <field> 8719 <name>BS7</name> 8720 <description>Port x set bit y (y= 8721 0..15)</description> 8722 <bitOffset>7</bitOffset> 8723 <bitWidth>1</bitWidth> 8724 <enumeratedValues derivedFrom="BS0W"/> 8725 </field> 8726 <field> 8727 <name>BS6</name> 8728 <description>Port x set bit y (y= 8729 0..15)</description> 8730 <bitOffset>6</bitOffset> 8731 <bitWidth>1</bitWidth> 8732 <enumeratedValues derivedFrom="BS0W"/> 8733 </field> 8734 <field> 8735 <name>BS5</name> 8736 <description>Port x set bit y (y= 8737 0..15)</description> 8738 <bitOffset>5</bitOffset> 8739 <bitWidth>1</bitWidth> 8740 <enumeratedValues derivedFrom="BS0W"/> 8741 </field> 8742 <field> 8743 <name>BS4</name> 8744 <description>Port x set bit y (y= 8745 0..15)</description> 8746 <bitOffset>4</bitOffset> 8747 <bitWidth>1</bitWidth> 8748 <enumeratedValues derivedFrom="BS0W"/> 8749 </field> 8750 <field> 8751 <name>BS3</name> 8752 <description>Port x set bit y (y= 8753 0..15)</description> 8754 <bitOffset>3</bitOffset> 8755 <bitWidth>1</bitWidth> 8756 <enumeratedValues derivedFrom="BS0W"/> 8757 </field> 8758 <field> 8759 <name>BS2</name> 8760 <description>Port x set bit y (y= 8761 0..15)</description> 8762 <bitOffset>2</bitOffset> 8763 <bitWidth>1</bitWidth> 8764 <enumeratedValues derivedFrom="BS0W"/> 8765 </field> 8766 <field> 8767 <name>BS1</name> 8768 <description>Port x set bit y (y= 8769 0..15)</description> 8770 <bitOffset>1</bitOffset> 8771 <bitWidth>1</bitWidth> 8772 <enumeratedValues derivedFrom="BS0W"/> 8773 </field> 8774 <field> 8775 <name>BS0</name> 8776 <description>Port x set bit y (y= 8777 0..15)</description> 8778 <bitOffset>0</bitOffset> 8779 <bitWidth>1</bitWidth> 8780 <enumeratedValues><name>BS0W</name><usage>write</usage><enumeratedValue><name>Set</name><description>Sets the corresponding ODRx bit</description><value>1</value></enumeratedValue></enumeratedValues> 8781 </field> 8782 </fields> 8783 </register> 8784 <register> 8785 <name>LCKR</name> 8786 <displayName>LCKR</displayName> 8787 <description>GPIO port configuration lock 8788 register</description> 8789 <addressOffset>0x1C</addressOffset> 8790 <size>0x20</size> 8791 <access>read-write</access> 8792 <resetValue>0x00000000</resetValue> 8793 <fields> 8794 <field> 8795 <name>LCKK</name> 8796 <description>Port x lock bit y (y= 8797 0..15)</description> 8798 <bitOffset>16</bitOffset> 8799 <bitWidth>1</bitWidth> 8800 <enumeratedValues><name>LCKK</name><usage>read-write</usage><enumeratedValue><name>NotActive</name><description>Port configuration lock key not active</description><value>0</value></enumeratedValue><enumeratedValue><name>Active</name><description>Port configuration lock key active</description><value>1</value></enumeratedValue></enumeratedValues> 8801 </field> 8802 <field> 8803 <name>LCK15</name> 8804 <description>Port x lock bit y (y= 8805 0..15)</description> 8806 <bitOffset>15</bitOffset> 8807 <bitWidth>1</bitWidth> 8808 <enumeratedValues derivedFrom="LCK10"/> 8809 </field> 8810 <field> 8811 <name>LCK14</name> 8812 <description>Port x lock bit y (y= 8813 0..15)</description> 8814 <bitOffset>14</bitOffset> 8815 <bitWidth>1</bitWidth> 8816 <enumeratedValues derivedFrom="LCK10"/> 8817 </field> 8818 <field> 8819 <name>LCK13</name> 8820 <description>Port x lock bit y (y= 8821 0..15)</description> 8822 <bitOffset>13</bitOffset> 8823 <bitWidth>1</bitWidth> 8824 <enumeratedValues derivedFrom="LCK10"/> 8825 </field> 8826 <field> 8827 <name>LCK12</name> 8828 <description>Port x lock bit y (y= 8829 0..15)</description> 8830 <bitOffset>12</bitOffset> 8831 <bitWidth>1</bitWidth> 8832 <enumeratedValues derivedFrom="LCK10"/> 8833 </field> 8834 <field> 8835 <name>LCK11</name> 8836 <description>Port x lock bit y (y= 8837 0..15)</description> 8838 <bitOffset>11</bitOffset> 8839 <bitWidth>1</bitWidth> 8840 <enumeratedValues derivedFrom="LCK10"/> 8841 </field> 8842 <field> 8843 <name>LCK10</name> 8844 <description>Port x lock bit y (y= 8845 0..15)</description> 8846 <bitOffset>10</bitOffset> 8847 <bitWidth>1</bitWidth> 8848 <enumeratedValues><name>LCK10</name><usage>read-write</usage><enumeratedValue><name>Unlocked</name><description>Port configuration not locked</description><value>0</value></enumeratedValue><enumeratedValue><name>Locked</name><description>Port configuration locked</description><value>1</value></enumeratedValue></enumeratedValues> 8849 </field> 8850 <field> 8851 <name>LCK9</name> 8852 <description>Port x lock bit y (y= 8853 0..15)</description> 8854 <bitOffset>9</bitOffset> 8855 <bitWidth>1</bitWidth> 8856 <enumeratedValues derivedFrom="LCK0"/> 8857 </field> 8858 <field> 8859 <name>LCK8</name> 8860 <description>Port x lock bit y (y= 8861 0..15)</description> 8862 <bitOffset>8</bitOffset> 8863 <bitWidth>1</bitWidth> 8864 <enumeratedValues derivedFrom="LCK0"/> 8865 </field> 8866 <field> 8867 <name>LCK7</name> 8868 <description>Port x lock bit y (y= 8869 0..15)</description> 8870 <bitOffset>7</bitOffset> 8871 <bitWidth>1</bitWidth> 8872 <enumeratedValues derivedFrom="LCK0"/> 8873 </field> 8874 <field> 8875 <name>LCK6</name> 8876 <description>Port x lock bit y (y= 8877 0..15)</description> 8878 <bitOffset>6</bitOffset> 8879 <bitWidth>1</bitWidth> 8880 <enumeratedValues derivedFrom="LCK0"/> 8881 </field> 8882 <field> 8883 <name>LCK5</name> 8884 <description>Port x lock bit y (y= 8885 0..15)</description> 8886 <bitOffset>5</bitOffset> 8887 <bitWidth>1</bitWidth> 8888 <enumeratedValues derivedFrom="LCK0"/> 8889 </field> 8890 <field> 8891 <name>LCK4</name> 8892 <description>Port x lock bit y (y= 8893 0..15)</description> 8894 <bitOffset>4</bitOffset> 8895 <bitWidth>1</bitWidth> 8896 <enumeratedValues derivedFrom="LCK0"/> 8897 </field> 8898 <field> 8899 <name>LCK3</name> 8900 <description>Port x lock bit y (y= 8901 0..15)</description> 8902 <bitOffset>3</bitOffset> 8903 <bitWidth>1</bitWidth> 8904 <enumeratedValues derivedFrom="LCK0"/> 8905 </field> 8906 <field> 8907 <name>LCK2</name> 8908 <description>Port x lock bit y (y= 8909 0..15)</description> 8910 <bitOffset>2</bitOffset> 8911 <bitWidth>1</bitWidth> 8912 <enumeratedValues derivedFrom="LCK0"/> 8913 </field> 8914 <field> 8915 <name>LCK1</name> 8916 <description>Port x lock bit y (y= 8917 0..15)</description> 8918 <bitOffset>1</bitOffset> 8919 <bitWidth>1</bitWidth> 8920 <enumeratedValues derivedFrom="LCK0"/> 8921 </field> 8922 <field> 8923 <name>LCK0</name> 8924 <description>Port x lock bit y (y= 8925 0..15)</description> 8926 <bitOffset>0</bitOffset> 8927 <bitWidth>1</bitWidth> 8928 <enumeratedValues><name>LCK0</name><usage>read-write</usage><enumeratedValue><name>Unlocked</name><description>Port configuration not locked</description><value>0</value></enumeratedValue><enumeratedValue><name>Locked</name><description>Port configuration locked</description><value>1</value></enumeratedValue></enumeratedValues> 8929 </field> 8930 </fields> 8931 </register> 8932 <register> 8933 <name>AFRL</name> 8934 <displayName>AFRL</displayName> 8935 <description>GPIO alternate function low 8936 register</description> 8937 <addressOffset>0x20</addressOffset> 8938 <size>0x20</size> 8939 <access>read-write</access> 8940 <resetValue>0x00000000</resetValue> 8941 <fields> 8942 <field> 8943 <name>AFRL7</name> 8944 <description>Alternate function selection for port x 8945 bit y (y = 0..7)</description> 8946 <bitOffset>28</bitOffset> 8947 <bitWidth>4</bitWidth> 8948 <enumeratedValues derivedFrom="AFRL0"/> 8949 </field> 8950 <field> 8951 <name>AFRL6</name> 8952 <description>Alternate function selection for port x 8953 bit y (y = 0..7)</description> 8954 <bitOffset>24</bitOffset> 8955 <bitWidth>4</bitWidth> 8956 <enumeratedValues derivedFrom="AFRL0"/> 8957 </field> 8958 <field> 8959 <name>AFRL5</name> 8960 <description>Alternate function selection for port x 8961 bit y (y = 0..7)</description> 8962 <bitOffset>20</bitOffset> 8963 <bitWidth>4</bitWidth> 8964 <enumeratedValues derivedFrom="AFRL0"/> 8965 </field> 8966 <field> 8967 <name>AFRL4</name> 8968 <description>Alternate function selection for port x 8969 bit y (y = 0..7)</description> 8970 <bitOffset>16</bitOffset> 8971 <bitWidth>4</bitWidth> 8972 <enumeratedValues derivedFrom="AFRL0"/> 8973 </field> 8974 <field> 8975 <name>AFRL3</name> 8976 <description>Alternate function selection for port x 8977 bit y (y = 0..7)</description> 8978 <bitOffset>12</bitOffset> 8979 <bitWidth>4</bitWidth> 8980 <enumeratedValues derivedFrom="AFRL0"/> 8981 </field> 8982 <field> 8983 <name>AFRL2</name> 8984 <description>Alternate function selection for port x 8985 bit y (y = 0..7)</description> 8986 <bitOffset>8</bitOffset> 8987 <bitWidth>4</bitWidth> 8988 <enumeratedValues derivedFrom="AFRL0"/> 8989 </field> 8990 <field> 8991 <name>AFRL1</name> 8992 <description>Alternate function selection for port x 8993 bit y (y = 0..7)</description> 8994 <bitOffset>4</bitOffset> 8995 <bitWidth>4</bitWidth> 8996 <enumeratedValues derivedFrom="AFRL0"/> 8997 </field> 8998 <field> 8999 <name>AFRL0</name> 9000 <description>Alternate function selection for port x 9001 bit y (y = 0..7)</description> 9002 <bitOffset>0</bitOffset> 9003 <bitWidth>4</bitWidth> 9004 <enumeratedValues><name>AFRL0</name><usage>read-write</usage><enumeratedValue><name>AF0</name><description>AF0</description><value>0</value></enumeratedValue><enumeratedValue><name>AF1</name><description>AF1</description><value>1</value></enumeratedValue><enumeratedValue><name>AF2</name><description>AF2</description><value>2</value></enumeratedValue><enumeratedValue><name>AF3</name><description>AF3</description><value>3</value></enumeratedValue><enumeratedValue><name>AF4</name><description>AF4</description><value>4</value></enumeratedValue><enumeratedValue><name>AF5</name><description>AF5</description><value>5</value></enumeratedValue><enumeratedValue><name>AF6</name><description>AF6</description><value>6</value></enumeratedValue><enumeratedValue><name>AF7</name><description>AF7</description><value>7</value></enumeratedValue><enumeratedValue><name>AF8</name><description>AF8</description><value>8</value></enumeratedValue><enumeratedValue><name>AF9</name><description>AF9</description><value>9</value></enumeratedValue><enumeratedValue><name>AF10</name><description>AF10</description><value>10</value></enumeratedValue><enumeratedValue><name>AF11</name><description>AF11</description><value>11</value></enumeratedValue><enumeratedValue><name>AF12</name><description>AF12</description><value>12</value></enumeratedValue><enumeratedValue><name>AF13</name><description>AF13</description><value>13</value></enumeratedValue><enumeratedValue><name>AF14</name><description>AF14</description><value>14</value></enumeratedValue><enumeratedValue><name>AF15</name><description>AF15</description><value>15</value></enumeratedValue></enumeratedValues> 9005 </field> 9006 </fields> 9007 </register> 9008 <register> 9009 <name>AFRH</name> 9010 <displayName>AFRH</displayName> 9011 <description>GPIO alternate function high 9012 register</description> 9013 <addressOffset>0x24</addressOffset> 9014 <size>0x20</size> 9015 <access>read-write</access> 9016 <resetValue>0x00000000</resetValue> 9017 <fields> 9018 <field> 9019 <name>AFRH15</name> 9020 <description>Alternate function selection for port x 9021 bit y (y = 8..15)</description> 9022 <bitOffset>28</bitOffset> 9023 <bitWidth>4</bitWidth> 9024 <enumeratedValues derivedFrom="AFRH8"/> 9025 </field> 9026 <field> 9027 <name>AFRH14</name> 9028 <description>Alternate function selection for port x 9029 bit y (y = 8..15)</description> 9030 <bitOffset>24</bitOffset> 9031 <bitWidth>4</bitWidth> 9032 <enumeratedValues derivedFrom="AFRH8"/> 9033 </field> 9034 <field> 9035 <name>AFRH13</name> 9036 <description>Alternate function selection for port x 9037 bit y (y = 8..15)</description> 9038 <bitOffset>20</bitOffset> 9039 <bitWidth>4</bitWidth> 9040 <enumeratedValues derivedFrom="AFRH8"/> 9041 </field> 9042 <field> 9043 <name>AFRH12</name> 9044 <description>Alternate function selection for port x 9045 bit y (y = 8..15)</description> 9046 <bitOffset>16</bitOffset> 9047 <bitWidth>4</bitWidth> 9048 <enumeratedValues derivedFrom="AFRH8"/> 9049 </field> 9050 <field> 9051 <name>AFRH11</name> 9052 <description>Alternate function selection for port x 9053 bit y (y = 8..15)</description> 9054 <bitOffset>12</bitOffset> 9055 <bitWidth>4</bitWidth> 9056 <enumeratedValues derivedFrom="AFRH8"/> 9057 </field> 9058 <field> 9059 <name>AFRH10</name> 9060 <description>Alternate function selection for port x 9061 bit y (y = 8..15)</description> 9062 <bitOffset>8</bitOffset> 9063 <bitWidth>4</bitWidth> 9064 <enumeratedValues derivedFrom="AFRH8"/> 9065 </field> 9066 <field> 9067 <name>AFRH9</name> 9068 <description>Alternate function selection for port x 9069 bit y (y = 8..15)</description> 9070 <bitOffset>4</bitOffset> 9071 <bitWidth>4</bitWidth> 9072 <enumeratedValues derivedFrom="AFRH8"/> 9073 </field> 9074 <field> 9075 <name>AFRH8</name> 9076 <description>Alternate function selection for port x 9077 bit y (y = 8..15)</description> 9078 <bitOffset>0</bitOffset> 9079 <bitWidth>4</bitWidth> 9080 <enumeratedValues><name>AFRH8</name><usage>read-write</usage><enumeratedValue><name>AF0</name><description>AF0</description><value>0</value></enumeratedValue><enumeratedValue><name>AF1</name><description>AF1</description><value>1</value></enumeratedValue><enumeratedValue><name>AF2</name><description>AF2</description><value>2</value></enumeratedValue><enumeratedValue><name>AF3</name><description>AF3</description><value>3</value></enumeratedValue><enumeratedValue><name>AF4</name><description>AF4</description><value>4</value></enumeratedValue><enumeratedValue><name>AF5</name><description>AF5</description><value>5</value></enumeratedValue><enumeratedValue><name>AF6</name><description>AF6</description><value>6</value></enumeratedValue><enumeratedValue><name>AF7</name><description>AF7</description><value>7</value></enumeratedValue><enumeratedValue><name>AF8</name><description>AF8</description><value>8</value></enumeratedValue><enumeratedValue><name>AF9</name><description>AF9</description><value>9</value></enumeratedValue><enumeratedValue><name>AF10</name><description>AF10</description><value>10</value></enumeratedValue><enumeratedValue><name>AF11</name><description>AF11</description><value>11</value></enumeratedValue><enumeratedValue><name>AF12</name><description>AF12</description><value>12</value></enumeratedValue><enumeratedValue><name>AF13</name><description>AF13</description><value>13</value></enumeratedValue><enumeratedValue><name>AF14</name><description>AF14</description><value>14</value></enumeratedValue><enumeratedValue><name>AF15</name><description>AF15</description><value>15</value></enumeratedValue></enumeratedValues> 9081 </field> 9082 </fields> 9083 </register> 9084 </registers> 9085 </peripheral> 9086 <peripheral> 9087 <name>SYSCFG</name> 9088 <description>System configuration controller</description> 9089 <groupName>SYSCFG</groupName> 9090 <baseAddress>0x40013800</baseAddress> 9091 <addressBlock> 9092 <offset>0x0</offset> 9093 <size>0x400</size> 9094 <usage>registers</usage> 9095 </addressBlock> 9096 <registers> 9097 <register> 9098 <name>MEMRM</name> 9099 <displayName>MEMRM</displayName> 9100 <description>memory remap register</description> 9101 <addressOffset>0x0</addressOffset> 9102 <size>0x20</size> 9103 <access>read-write</access> 9104 <resetValue>0x00000000</resetValue> 9105 <fields> 9106 <field> 9107 <name>MEM_MODE</name> 9108 <description>MEM_MODE</description> 9109 <bitOffset>0</bitOffset> 9110 <bitWidth>2</bitWidth> 9111 </field> 9112 </fields> 9113 </register> 9114 <register> 9115 <name>PMC</name> 9116 <displayName>PMC</displayName> 9117 <description>peripheral mode configuration 9118 register</description> 9119 <addressOffset>0x4</addressOffset> 9120 <size>0x20</size> 9121 <access>read-write</access> 9122 <resetValue>0x00000000</resetValue> 9123 <fields> 9124 <field> 9125 <name>MII_RMII_SEL</name> 9126 <description>Ethernet PHY interface 9127 selection</description> 9128 <bitOffset>23</bitOffset> 9129 <bitWidth>1</bitWidth> 9130 </field> 9131 </fields> 9132 </register> 9133 <register> 9134 <name>EXTICR1</name> 9135 <displayName>EXTICR1</displayName> 9136 <description>external interrupt configuration register 9137 1</description> 9138 <addressOffset>0x8</addressOffset> 9139 <size>0x20</size> 9140 <access>read-write</access> 9141 <resetValue>0x0000</resetValue> 9142 <fields> 9143 <field> 9144 <name>EXTI3</name> 9145 <description>EXTI x configuration (x = 0 to 9146 3)</description> 9147 <bitOffset>12</bitOffset> 9148 <bitWidth>4</bitWidth> 9149 </field> 9150 <field> 9151 <name>EXTI2</name> 9152 <description>EXTI x configuration (x = 0 to 9153 3)</description> 9154 <bitOffset>8</bitOffset> 9155 <bitWidth>4</bitWidth> 9156 </field> 9157 <field> 9158 <name>EXTI1</name> 9159 <description>EXTI x configuration (x = 0 to 9160 3)</description> 9161 <bitOffset>4</bitOffset> 9162 <bitWidth>4</bitWidth> 9163 </field> 9164 <field> 9165 <name>EXTI0</name> 9166 <description>EXTI x configuration (x = 0 to 9167 3)</description> 9168 <bitOffset>0</bitOffset> 9169 <bitWidth>4</bitWidth> 9170 </field> 9171 </fields> 9172 </register> 9173 <register> 9174 <name>EXTICR2</name> 9175 <displayName>EXTICR2</displayName> 9176 <description>external interrupt configuration register 9177 2</description> 9178 <addressOffset>0xC</addressOffset> 9179 <size>0x20</size> 9180 <access>read-write</access> 9181 <resetValue>0x0000</resetValue> 9182 <fields> 9183 <field> 9184 <name>EXTI7</name> 9185 <description>EXTI x configuration (x = 4 to 9186 7)</description> 9187 <bitOffset>12</bitOffset> 9188 <bitWidth>4</bitWidth> 9189 </field> 9190 <field> 9191 <name>EXTI6</name> 9192 <description>EXTI x configuration (x = 4 to 9193 7)</description> 9194 <bitOffset>8</bitOffset> 9195 <bitWidth>4</bitWidth> 9196 </field> 9197 <field> 9198 <name>EXTI5</name> 9199 <description>EXTI x configuration (x = 4 to 9200 7)</description> 9201 <bitOffset>4</bitOffset> 9202 <bitWidth>4</bitWidth> 9203 </field> 9204 <field> 9205 <name>EXTI4</name> 9206 <description>EXTI x configuration (x = 4 to 9207 7)</description> 9208 <bitOffset>0</bitOffset> 9209 <bitWidth>4</bitWidth> 9210 </field> 9211 </fields> 9212 </register> 9213 <register> 9214 <name>EXTICR3</name> 9215 <displayName>EXTICR3</displayName> 9216 <description>external interrupt configuration register 9217 3</description> 9218 <addressOffset>0x10</addressOffset> 9219 <size>0x20</size> 9220 <access>read-write</access> 9221 <resetValue>0x0000</resetValue> 9222 <fields> 9223 <field> 9224 <name>EXTI11</name> 9225 <description>EXTI x configuration (x = 8 to 9226 11)</description> 9227 <bitOffset>12</bitOffset> 9228 <bitWidth>4</bitWidth> 9229 </field> 9230 <field> 9231 <name>EXTI10</name> 9232 <description>EXTI10</description> 9233 <bitOffset>8</bitOffset> 9234 <bitWidth>4</bitWidth> 9235 </field> 9236 <field> 9237 <name>EXTI9</name> 9238 <description>EXTI x configuration (x = 8 to 9239 11)</description> 9240 <bitOffset>4</bitOffset> 9241 <bitWidth>4</bitWidth> 9242 </field> 9243 <field> 9244 <name>EXTI8</name> 9245 <description>EXTI x configuration (x = 8 to 9246 11)</description> 9247 <bitOffset>0</bitOffset> 9248 <bitWidth>4</bitWidth> 9249 </field> 9250 </fields> 9251 </register> 9252 <register> 9253 <name>EXTICR4</name> 9254 <displayName>EXTICR4</displayName> 9255 <description>external interrupt configuration register 9256 4</description> 9257 <addressOffset>0x14</addressOffset> 9258 <size>0x20</size> 9259 <access>read-write</access> 9260 <resetValue>0x0000</resetValue> 9261 <fields> 9262 <field> 9263 <name>EXTI15</name> 9264 <description>EXTI x configuration (x = 12 to 9265 15)</description> 9266 <bitOffset>12</bitOffset> 9267 <bitWidth>4</bitWidth> 9268 </field> 9269 <field> 9270 <name>EXTI14</name> 9271 <description>EXTI x configuration (x = 12 to 9272 15)</description> 9273 <bitOffset>8</bitOffset> 9274 <bitWidth>4</bitWidth> 9275 </field> 9276 <field> 9277 <name>EXTI13</name> 9278 <description>EXTI x configuration (x = 12 to 9279 15)</description> 9280 <bitOffset>4</bitOffset> 9281 <bitWidth>4</bitWidth> 9282 </field> 9283 <field> 9284 <name>EXTI12</name> 9285 <description>EXTI x configuration (x = 12 to 9286 15)</description> 9287 <bitOffset>0</bitOffset> 9288 <bitWidth>4</bitWidth> 9289 </field> 9290 </fields> 9291 </register> 9292 <register> 9293 <name>CMPCR</name> 9294 <displayName>CMPCR</displayName> 9295 <description>Compensation cell control 9296 register</description> 9297 <addressOffset>0x20</addressOffset> 9298 <size>0x20</size> 9299 <access>read-only</access> 9300 <resetValue>0x00000000</resetValue> 9301 <fields> 9302 <field> 9303 <name>READY</name> 9304 <description>READY</description> 9305 <bitOffset>8</bitOffset> 9306 <bitWidth>1</bitWidth> 9307 </field> 9308 <field> 9309 <name>CMP_PD</name> 9310 <description>Compensation cell 9311 power-down</description> 9312 <bitOffset>0</bitOffset> 9313 <bitWidth>1</bitWidth> 9314 </field> 9315 </fields> 9316 </register> 9317 </registers> 9318 </peripheral> 9319 <peripheral> 9320 <name>SPI1</name> 9321 <description>Serial peripheral interface</description> 9322 <groupName>SPI</groupName> 9323 <baseAddress>0x40013000</baseAddress> 9324 <addressBlock> 9325 <offset>0x0</offset> 9326 <size>0x400</size> 9327 <usage>registers</usage> 9328 </addressBlock> 9329 <interrupt> 9330 <name>SPI1</name> 9331 <description>SPI1 global interrupt</description> 9332 <value>35</value> 9333 </interrupt> 9334 <registers> 9335 <register> 9336 <name>CR1</name> 9337 <displayName>CR1</displayName> 9338 <description>control register 1</description> 9339 <addressOffset>0x0</addressOffset> 9340 <size>0x20</size> 9341 <access>read-write</access> 9342 <resetValue>0x0000</resetValue> 9343 <fields> 9344 <field> 9345 <name>BIDIMODE</name> 9346 <description>Bidirectional data mode 9347 enable</description> 9348 <bitOffset>15</bitOffset> 9349 <bitWidth>1</bitWidth> 9350 <enumeratedValues><name>BIDIMODE</name><usage>read-write</usage><enumeratedValue><name>Unidirectional</name><description>2-line unidirectional data mode selected</description><value>0</value></enumeratedValue><enumeratedValue><name>Bidirectional</name><description>1-line bidirectional data mode selected</description><value>1</value></enumeratedValue></enumeratedValues> 9351 </field> 9352 <field> 9353 <name>BIDIOE</name> 9354 <description>Output enable in bidirectional 9355 mode</description> 9356 <bitOffset>14</bitOffset> 9357 <bitWidth>1</bitWidth> 9358 <enumeratedValues><name>BIDIOE</name><usage>read-write</usage><enumeratedValue><name>OutputDisabled</name><description>Output disabled (receive-only mode)</description><value>0</value></enumeratedValue><enumeratedValue><name>OutputEnabled</name><description>Output enabled (transmit-only mode)</description><value>1</value></enumeratedValue></enumeratedValues> 9359 </field> 9360 <field> 9361 <name>CRCEN</name> 9362 <description>Hardware CRC calculation 9363 enable</description> 9364 <bitOffset>13</bitOffset> 9365 <bitWidth>1</bitWidth> 9366 <enumeratedValues><name>CRCEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>CRC calculation disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>CRC calculation enabled</description><value>1</value></enumeratedValue></enumeratedValues> 9367 </field> 9368 <field> 9369 <name>CRCNEXT</name> 9370 <description>CRC transfer next</description> 9371 <bitOffset>12</bitOffset> 9372 <bitWidth>1</bitWidth> 9373 <enumeratedValues><name>CRCNEXT</name><usage>read-write</usage><enumeratedValue><name>TxBuffer</name><description>Next transmit value is from Tx buffer</description><value>0</value></enumeratedValue><enumeratedValue><name>CRC</name><description>Next transmit value is from Tx CRC register</description><value>1</value></enumeratedValue></enumeratedValues> 9374 </field> 9375 <field> 9376 <name>DFF</name> 9377 <description>Data frame format</description> 9378 <bitOffset>11</bitOffset> 9379 <bitWidth>1</bitWidth> 9380 <enumeratedValues><name>DFF</name><usage>read-write</usage><enumeratedValue><name>EightBit</name><description>8-bit data frame format is selected for transmission/reception</description><value>0</value></enumeratedValue><enumeratedValue><name>SixteenBit</name><description>16-bit data frame format is selected for transmission/reception</description><value>1</value></enumeratedValue></enumeratedValues> 9381 </field> 9382 <field> 9383 <name>RXONLY</name> 9384 <description>Receive only</description> 9385 <bitOffset>10</bitOffset> 9386 <bitWidth>1</bitWidth> 9387 <enumeratedValues><name>RXONLY</name><usage>read-write</usage><enumeratedValue><name>FullDuplex</name><description>Full duplex (Transmit and receive)</description><value>0</value></enumeratedValue><enumeratedValue><name>OutputDisabled</name><description>Output disabled (Receive-only mode)</description><value>1</value></enumeratedValue></enumeratedValues> 9388 </field> 9389 <field> 9390 <name>SSM</name> 9391 <description>Software slave management</description> 9392 <bitOffset>9</bitOffset> 9393 <bitWidth>1</bitWidth> 9394 <enumeratedValues><name>SSM</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Software slave management disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Software slave management enabled</description><value>1</value></enumeratedValue></enumeratedValues> 9395 </field> 9396 <field> 9397 <name>SSI</name> 9398 <description>Internal slave select</description> 9399 <bitOffset>8</bitOffset> 9400 <bitWidth>1</bitWidth> 9401 <enumeratedValues><name>SSI</name><usage>read-write</usage><enumeratedValue><name>SlaveSelected</name><description>0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored</description><value>0</value></enumeratedValue><enumeratedValue><name>SlaveNotSelected</name><description>1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored</description><value>1</value></enumeratedValue></enumeratedValues> 9402 </field> 9403 <field> 9404 <name>LSBFIRST</name> 9405 <description>Frame format</description> 9406 <bitOffset>7</bitOffset> 9407 <bitWidth>1</bitWidth> 9408 <enumeratedValues><name>LSBFIRST</name><usage>read-write</usage><enumeratedValue><name>MSBFirst</name><description>Data is transmitted/received with the MSB first</description><value>0</value></enumeratedValue><enumeratedValue><name>LSBFirst</name><description>Data is transmitted/received with the LSB first</description><value>1</value></enumeratedValue></enumeratedValues> 9409 </field> 9410 <field> 9411 <name>SPE</name> 9412 <description>SPI enable</description> 9413 <bitOffset>6</bitOffset> 9414 <bitWidth>1</bitWidth> 9415 <enumeratedValues><name>SPE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Peripheral disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Peripheral enabled</description><value>1</value></enumeratedValue></enumeratedValues> 9416 </field> 9417 <field> 9418 <name>BR</name> 9419 <description>Baud rate control</description> 9420 <bitOffset>3</bitOffset> 9421 <bitWidth>3</bitWidth> 9422 <enumeratedValues><name>BR</name><usage>read-write</usage><enumeratedValue><name>Div2</name><description>f_PCLK / 2</description><value>0</value></enumeratedValue><enumeratedValue><name>Div4</name><description>f_PCLK / 4</description><value>1</value></enumeratedValue><enumeratedValue><name>Div8</name><description>f_PCLK / 8</description><value>2</value></enumeratedValue><enumeratedValue><name>Div16</name><description>f_PCLK / 16</description><value>3</value></enumeratedValue><enumeratedValue><name>Div32</name><description>f_PCLK / 32</description><value>4</value></enumeratedValue><enumeratedValue><name>Div64</name><description>f_PCLK / 64</description><value>5</value></enumeratedValue><enumeratedValue><name>Div128</name><description>f_PCLK / 128</description><value>6</value></enumeratedValue><enumeratedValue><name>Div256</name><description>f_PCLK / 256</description><value>7</value></enumeratedValue></enumeratedValues> 9423 </field> 9424 <field> 9425 <name>MSTR</name> 9426 <description>Master selection</description> 9427 <bitOffset>2</bitOffset> 9428 <bitWidth>1</bitWidth> 9429 <enumeratedValues><name>MSTR</name><usage>read-write</usage><enumeratedValue><name>Slave</name><description>Slave configuration</description><value>0</value></enumeratedValue><enumeratedValue><name>Master</name><description>Master configuration</description><value>1</value></enumeratedValue></enumeratedValues> 9430 </field> 9431 <field> 9432 <name>CPOL</name> 9433 <description>Clock polarity</description> 9434 <bitOffset>1</bitOffset> 9435 <bitWidth>1</bitWidth> 9436 <enumeratedValues><name>CPOL</name><usage>read-write</usage><enumeratedValue><name>IdleLow</name><description>CK to 0 when idle</description><value>0</value></enumeratedValue><enumeratedValue><name>IdleHigh</name><description>CK to 1 when idle</description><value>1</value></enumeratedValue></enumeratedValues> 9437 </field> 9438 <field> 9439 <name>CPHA</name> 9440 <description>Clock phase</description> 9441 <bitOffset>0</bitOffset> 9442 <bitWidth>1</bitWidth> 9443 <enumeratedValues><name>CPHA</name><usage>read-write</usage><enumeratedValue><name>FirstEdge</name><description>The first clock transition is the first data capture edge</description><value>0</value></enumeratedValue><enumeratedValue><name>SecondEdge</name><description>The second clock transition is the first data capture edge</description><value>1</value></enumeratedValue></enumeratedValues> 9444 </field> 9445 </fields> 9446 </register> 9447 <register> 9448 <name>CR2</name> 9449 <displayName>CR2</displayName> 9450 <description>control register 2</description> 9451 <addressOffset>0x4</addressOffset> 9452 <size>0x20</size> 9453 <access>read-write</access> 9454 <resetValue>0x0000</resetValue> 9455 <fields> 9456 <field> 9457 <name>TXEIE</name> 9458 <description>Tx buffer empty interrupt 9459 enable</description> 9460 <bitOffset>7</bitOffset> 9461 <bitWidth>1</bitWidth> 9462 <enumeratedValues><name>TXEIE</name><usage>read-write</usage><enumeratedValue><name>Masked</name><description>TXE interrupt masked</description><value>0</value></enumeratedValue><enumeratedValue><name>NotMasked</name><description>TXE interrupt not masked</description><value>1</value></enumeratedValue></enumeratedValues> 9463 </field> 9464 <field> 9465 <name>RXNEIE</name> 9466 <description>RX buffer not empty interrupt 9467 enable</description> 9468 <bitOffset>6</bitOffset> 9469 <bitWidth>1</bitWidth> 9470 <enumeratedValues><name>RXNEIE</name><usage>read-write</usage><enumeratedValue><name>Masked</name><description>RXE interrupt masked</description><value>0</value></enumeratedValue><enumeratedValue><name>NotMasked</name><description>RXE interrupt not masked</description><value>1</value></enumeratedValue></enumeratedValues> 9471 </field> 9472 <field> 9473 <name>ERRIE</name> 9474 <description>Error interrupt enable</description> 9475 <bitOffset>5</bitOffset> 9476 <bitWidth>1</bitWidth> 9477 <enumeratedValues><name>ERRIE</name><usage>read-write</usage><enumeratedValue><name>Masked</name><description>Error interrupt masked</description><value>0</value></enumeratedValue><enumeratedValue><name>NotMasked</name><description>Error interrupt not masked</description><value>1</value></enumeratedValue></enumeratedValues> 9478 </field> 9479 <field> 9480 <name>FRF</name> 9481 <description>Frame format</description> 9482 <bitOffset>4</bitOffset> 9483 <bitWidth>1</bitWidth> 9484 <enumeratedValues><name>FRF</name><usage>read-write</usage><enumeratedValue><name>Motorola</name><description>SPI Motorola mode</description><value>0</value></enumeratedValue><enumeratedValue><name>TI</name><description>SPI TI mode</description><value>1</value></enumeratedValue></enumeratedValues> 9485 </field> 9486 <field> 9487 <name>SSOE</name> 9488 <description>SS output enable</description> 9489 <bitOffset>2</bitOffset> 9490 <bitWidth>1</bitWidth> 9491 <enumeratedValues><name>SSOE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>SS output is disabled in master mode</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>SS output is enabled in master mode</description><value>1</value></enumeratedValue></enumeratedValues> 9492 </field> 9493 <field> 9494 <name>TXDMAEN</name> 9495 <description>Tx buffer DMA enable</description> 9496 <bitOffset>1</bitOffset> 9497 <bitWidth>1</bitWidth> 9498 <enumeratedValues><name>TXDMAEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Tx buffer DMA disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Tx buffer DMA enabled</description><value>1</value></enumeratedValue></enumeratedValues> 9499 </field> 9500 <field> 9501 <name>RXDMAEN</name> 9502 <description>Rx buffer DMA enable</description> 9503 <bitOffset>0</bitOffset> 9504 <bitWidth>1</bitWidth> 9505 <enumeratedValues><name>RXDMAEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Rx buffer DMA disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Rx buffer DMA enabled</description><value>1</value></enumeratedValue></enumeratedValues> 9506 </field> 9507 </fields> 9508 </register> 9509 <register> 9510 <name>SR</name> 9511 <displayName>SR</displayName> 9512 <description>status register</description> 9513 <addressOffset>0x8</addressOffset> 9514 <size>0x20</size> 9515 <resetValue>0x0002</resetValue> 9516 <fields> 9517 <field> 9518 <name>FRE</name> 9519 <description>TI frame format error</description> 9520 <bitOffset>8</bitOffset> 9521 <bitWidth>1</bitWidth> 9522 <access>read-only</access> 9523 <enumeratedValues><name>FRER</name><usage>read</usage><enumeratedValue><name>NoError</name><description>No frame format error</description><value>0</value></enumeratedValue><enumeratedValue><name>Error</name><description>A frame format error occurred</description><value>1</value></enumeratedValue></enumeratedValues> 9524 </field> 9525 <field> 9526 <name>BSY</name> 9527 <description>Busy flag</description> 9528 <bitOffset>7</bitOffset> 9529 <bitWidth>1</bitWidth> 9530 <access>read-only</access> 9531 <enumeratedValues><name>BSYR</name><usage>read</usage><enumeratedValue><name>NotBusy</name><description>SPI not busy</description><value>0</value></enumeratedValue><enumeratedValue><name>Busy</name><description>SPI busy</description><value>1</value></enumeratedValue></enumeratedValues> 9532 </field> 9533 <field> 9534 <name>OVR</name> 9535 <description>Overrun flag</description> 9536 <bitOffset>6</bitOffset> 9537 <bitWidth>1</bitWidth> 9538 <access>read-only</access> 9539 <enumeratedValues><name>OVRR</name><usage>read</usage><enumeratedValue><name>NoOverrun</name><description>No overrun occurred</description><value>0</value></enumeratedValue><enumeratedValue><name>Overrun</name><description>Overrun occurred</description><value>1</value></enumeratedValue></enumeratedValues> 9540 </field> 9541 <field> 9542 <name>MODF</name> 9543 <description>Mode fault</description> 9544 <bitOffset>5</bitOffset> 9545 <bitWidth>1</bitWidth> 9546 <access>read-only</access> 9547 <enumeratedValues><name>MODFR</name><usage>read</usage><enumeratedValue><name>NoFault</name><description>No mode fault occurred</description><value>0</value></enumeratedValue><enumeratedValue><name>Fault</name><description>Mode fault occurred</description><value>1</value></enumeratedValue></enumeratedValues> 9548 </field> 9549 <field> 9550 <name>CRCERR</name> 9551 <description>CRC error flag</description> 9552 <bitOffset>4</bitOffset> 9553 <bitWidth>1</bitWidth> 9554 <access>read-write</access> 9555 <enumeratedValues><name>CRCERR</name><usage>read-write</usage><enumeratedValue><name>Match</name><description>CRC value received matches the SPIx_RXCRCR value</description><value>0</value></enumeratedValue><enumeratedValue><name>NoMatch</name><description>CRC value received does not match the SPIx_RXCRCR value</description><value>1</value></enumeratedValue></enumeratedValues> 9556 </field> 9557 <field> 9558 <name>UDR</name> 9559 <description>Underrun flag</description> 9560 <bitOffset>3</bitOffset> 9561 <bitWidth>1</bitWidth> 9562 <access>read-only</access> 9563 <enumeratedValues><name>UDRR</name><usage>read</usage><enumeratedValue><name>NoUnderrun</name><description>No underrun occurred</description><value>0</value></enumeratedValue><enumeratedValue><name>Underrun</name><description>Underrun occurred</description><value>1</value></enumeratedValue></enumeratedValues> 9564 </field> 9565 <field> 9566 <name>CHSIDE</name> 9567 <description>Channel side</description> 9568 <bitOffset>2</bitOffset> 9569 <bitWidth>1</bitWidth> 9570 <access>read-only</access> 9571 <enumeratedValues><name>CHSIDE</name><usage>read-write</usage><enumeratedValue><name>Left</name><description>Channel left has to be transmitted or has been received</description><value>0</value></enumeratedValue><enumeratedValue><name>Right</name><description>Channel right has to be transmitted or has been received</description><value>1</value></enumeratedValue></enumeratedValues> 9572 </field> 9573 <field> 9574 <name>TXE</name> 9575 <description>Transmit buffer empty</description> 9576 <bitOffset>1</bitOffset> 9577 <bitWidth>1</bitWidth> 9578 <access>read-only</access> 9579 <enumeratedValues><name>TXE</name><usage>read-write</usage><enumeratedValue><name>NotEmpty</name><description>Tx buffer not empty</description><value>0</value></enumeratedValue><enumeratedValue><name>Empty</name><description>Tx buffer empty</description><value>1</value></enumeratedValue></enumeratedValues> 9580 </field> 9581 <field> 9582 <name>RXNE</name> 9583 <description>Receive buffer not empty</description> 9584 <bitOffset>0</bitOffset> 9585 <bitWidth>1</bitWidth> 9586 <access>read-only</access> 9587 <enumeratedValues><name>RXNE</name><usage>read-write</usage><enumeratedValue><name>Empty</name><description>Rx buffer empty</description><value>0</value></enumeratedValue><enumeratedValue><name>NotEmpty</name><description>Rx buffer not empty</description><value>1</value></enumeratedValue></enumeratedValues> 9588 </field> 9589 </fields> 9590 </register> 9591 <register> 9592 <name>DR</name> 9593 <displayName>DR</displayName> 9594 <description>data register</description> 9595 <addressOffset>0xC</addressOffset> 9596 <size>0x20</size> 9597 <access>read-write</access> 9598 <resetValue>0x0000</resetValue> 9599 <fields> 9600 <field> 9601 <name>DR</name> 9602 <description>Data register</description> 9603 <bitOffset>0</bitOffset> 9604 <bitWidth>16</bitWidth> 9605 <writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint> 9606 </field> 9607 </fields> 9608 </register> 9609 <register> 9610 <name>CRCPR</name> 9611 <displayName>CRCPR</displayName> 9612 <description>CRC polynomial register</description> 9613 <addressOffset>0x10</addressOffset> 9614 <size>0x20</size> 9615 <access>read-write</access> 9616 <resetValue>0x0007</resetValue> 9617 <fields> 9618 <field> 9619 <name>CRCPOLY</name> 9620 <description>CRC polynomial register</description> 9621 <bitOffset>0</bitOffset> 9622 <bitWidth>16</bitWidth> 9623 <writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint> 9624 </field> 9625 </fields> 9626 </register> 9627 <register> 9628 <name>RXCRCR</name> 9629 <displayName>RXCRCR</displayName> 9630 <description>RX CRC register</description> 9631 <addressOffset>0x14</addressOffset> 9632 <size>0x20</size> 9633 <access>read-only</access> 9634 <resetValue>0x0000</resetValue> 9635 <fields> 9636 <field> 9637 <name>RxCRC</name> 9638 <description>Rx CRC register</description> 9639 <bitOffset>0</bitOffset> 9640 <bitWidth>16</bitWidth> 9641 <writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint> 9642 </field> 9643 </fields> 9644 </register> 9645 <register> 9646 <name>TXCRCR</name> 9647 <displayName>TXCRCR</displayName> 9648 <description>TX CRC register</description> 9649 <addressOffset>0x18</addressOffset> 9650 <size>0x20</size> 9651 <access>read-only</access> 9652 <resetValue>0x0000</resetValue> 9653 <fields> 9654 <field> 9655 <name>TxCRC</name> 9656 <description>Tx CRC register</description> 9657 <bitOffset>0</bitOffset> 9658 <bitWidth>16</bitWidth> 9659 <writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint> 9660 </field> 9661 </fields> 9662 </register> 9663 <register> 9664 <name>I2SCFGR</name> 9665 <displayName>I2SCFGR</displayName> 9666 <description>I2S configuration register</description> 9667 <addressOffset>0x1C</addressOffset> 9668 <size>0x20</size> 9669 <access>read-write</access> 9670 <resetValue>0x0000</resetValue> 9671 <fields> 9672 <field> 9673 <name>I2SMOD</name> 9674 <description>I2S mode selection</description> 9675 <bitOffset>11</bitOffset> 9676 <bitWidth>1</bitWidth> 9677 <enumeratedValues><name>I2SMOD</name><usage>read-write</usage><enumeratedValue><name>SPIMode</name><description>SPI mode is selected</description><value>0</value></enumeratedValue><enumeratedValue><name>I2SMode</name><description>I2S mode is selected</description><value>1</value></enumeratedValue></enumeratedValues> 9678 </field> 9679 <field> 9680 <name>I2SE</name> 9681 <description>I2S Enable</description> 9682 <bitOffset>10</bitOffset> 9683 <bitWidth>1</bitWidth> 9684 <enumeratedValues><name>I2SE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>I2S peripheral is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>I2S peripheral is enabled</description><value>1</value></enumeratedValue></enumeratedValues> 9685 </field> 9686 <field> 9687 <name>I2SCFG</name> 9688 <description>I2S configuration mode</description> 9689 <bitOffset>8</bitOffset> 9690 <bitWidth>2</bitWidth> 9691 <enumeratedValues><name>I2SCFG</name><usage>read-write</usage><enumeratedValue><name>SlaveTx</name><description>Slave - transmit</description><value>0</value></enumeratedValue><enumeratedValue><name>SlaveRx</name><description>Slave - receive</description><value>1</value></enumeratedValue><enumeratedValue><name>MasterTx</name><description>Master - transmit</description><value>2</value></enumeratedValue><enumeratedValue><name>MasterRx</name><description>Master - receive</description><value>3</value></enumeratedValue></enumeratedValues> 9692 </field> 9693 <field> 9694 <name>PCMSYNC</name> 9695 <description>PCM frame synchronization</description> 9696 <bitOffset>7</bitOffset> 9697 <bitWidth>1</bitWidth> 9698 <enumeratedValues><name>PCMSYNC</name><usage>read-write</usage><enumeratedValue><name>Short</name><description>Short frame synchronisation</description><value>0</value></enumeratedValue><enumeratedValue><name>Long</name><description>Long frame synchronisation</description><value>1</value></enumeratedValue></enumeratedValues> 9699 </field> 9700 <field> 9701 <name>I2SSTD</name> 9702 <description>I2S standard selection</description> 9703 <bitOffset>4</bitOffset> 9704 <bitWidth>2</bitWidth> 9705 <enumeratedValues><name>I2SSTD</name><usage>read-write</usage><enumeratedValue><name>Philips</name><description>I2S Philips standard</description><value>0</value></enumeratedValue><enumeratedValue><name>MSB</name><description>MSB justified standard</description><value>1</value></enumeratedValue><enumeratedValue><name>LSB</name><description>LSB justified standard</description><value>2</value></enumeratedValue><enumeratedValue><name>PCM</name><description>PCM standard</description><value>3</value></enumeratedValue></enumeratedValues> 9706 </field> 9707 <field> 9708 <name>CKPOL</name> 9709 <description>Steady state clock 9710 polarity</description> 9711 <bitOffset>3</bitOffset> 9712 <bitWidth>1</bitWidth> 9713 <enumeratedValues><name>CKPOL</name><usage>read-write</usage><enumeratedValue><name>IdleLow</name><description>I2S clock inactive state is low level</description><value>0</value></enumeratedValue><enumeratedValue><name>IdleHigh</name><description>I2S clock inactive state is high level</description><value>1</value></enumeratedValue></enumeratedValues> 9714 </field> 9715 <field> 9716 <name>DATLEN</name> 9717 <description>Data length to be 9718 transferred</description> 9719 <bitOffset>1</bitOffset> 9720 <bitWidth>2</bitWidth> 9721 <enumeratedValues><name>DATLEN</name><usage>read-write</usage><enumeratedValue><name>SixteenBit</name><description>16-bit data length</description><value>0</value></enumeratedValue><enumeratedValue><name>TwentyFourBit</name><description>24-bit data length</description><value>1</value></enumeratedValue><enumeratedValue><name>ThirtyTwoBit</name><description>32-bit data length</description><value>2</value></enumeratedValue></enumeratedValues> 9722 </field> 9723 <field> 9724 <name>CHLEN</name> 9725 <description>Channel length (number of bits per audio 9726 channel)</description> 9727 <bitOffset>0</bitOffset> 9728 <bitWidth>1</bitWidth> 9729 <enumeratedValues><name>CHLEN</name><usage>read-write</usage><enumeratedValue><name>SixteenBit</name><description>16-bit wide</description><value>0</value></enumeratedValue><enumeratedValue><name>ThirtyTwoBit</name><description>32-bit wide</description><value>1</value></enumeratedValue></enumeratedValues> 9730 </field> 9731 </fields> 9732 </register> 9733 <register> 9734 <name>I2SPR</name> 9735 <displayName>I2SPR</displayName> 9736 <description>I2S prescaler register</description> 9737 <addressOffset>0x20</addressOffset> 9738 <size>0x20</size> 9739 <access>read-write</access> 9740 <resetValue>00000010</resetValue> 9741 <fields> 9742 <field> 9743 <name>MCKOE</name> 9744 <description>Master clock output enable</description> 9745 <bitOffset>9</bitOffset> 9746 <bitWidth>1</bitWidth> 9747 <enumeratedValues><name>MCKOE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Master clock output is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Master clock output is enabled</description><value>1</value></enumeratedValue></enumeratedValues> 9748 </field> 9749 <field> 9750 <name>ODD</name> 9751 <description>Odd factor for the 9752 prescaler</description> 9753 <bitOffset>8</bitOffset> 9754 <bitWidth>1</bitWidth> 9755 <enumeratedValues><name>ODD</name><usage>read-write</usage><enumeratedValue><name>Even</name><description>Real divider value is I2SDIV * 2</description><value>0</value></enumeratedValue><enumeratedValue><name>Odd</name><description>Real divider value is (I2SDIV * 2) + 1</description><value>1</value></enumeratedValue></enumeratedValues> 9756 </field> 9757 <field> 9758 <name>I2SDIV</name> 9759 <description>I2S Linear prescaler</description> 9760 <bitOffset>0</bitOffset> 9761 <bitWidth>8</bitWidth> 9762 <writeConstraint><range><minimum>2</minimum><maximum>255</maximum></range></writeConstraint> 9763 </field> 9764 </fields> 9765 </register> 9766 </registers> 9767 </peripheral> 9768 <peripheral derivedFrom="SPI1"> 9769 <name>SPI2</name> 9770 <baseAddress>0x40003800</baseAddress> 9771 <interrupt> 9772 <name>SPI2</name> 9773 <description>SPI2 global interrupt</description> 9774 <value>36</value> 9775 </interrupt> 9776 </peripheral> 9777 <peripheral derivedFrom="SPI1"> 9778 <name>SPI3</name> 9779 <baseAddress>0x40003C00</baseAddress> 9780 <interrupt> 9781 <name>SPI3</name> 9782 <description>SPI3 global interrupt</description> 9783 <value>51</value> 9784 </interrupt> 9785 </peripheral> 9786 <peripheral derivedFrom="SPI1"> 9787 <name>I2S2ext</name> 9788 <baseAddress>0x40003400</baseAddress> 9789 </peripheral> 9790 <peripheral derivedFrom="SPI1"> 9791 <name>I2S3ext</name> 9792 <baseAddress>0x40004000</baseAddress> 9793 </peripheral> 9794 <peripheral derivedFrom="SPI1"> 9795 <name>SPI4</name> 9796 <baseAddress>0x40013400</baseAddress> 9797 <interrupt> 9798 <name>SPI1</name> 9799 <description>SPI1 global interrupt</description> 9800 <value>35</value> 9801 </interrupt> 9802 </peripheral> 9803 <peripheral derivedFrom="SPI1"> 9804 <name>SPI5</name> 9805 <baseAddress>0x40015000</baseAddress> 9806 <interrupt> 9807 <name>SPI1</name> 9808 <description>SPI1 global interrupt</description> 9809 <value>35</value> 9810 </interrupt> 9811 </peripheral> 9812 <peripheral derivedFrom="SPI1"> 9813 <name>SPI6</name> 9814 <baseAddress>0x40015400</baseAddress> 9815 <interrupt> 9816 <name>SPI3</name> 9817 <description>SPI3 global interrupt</description> 9818 <value>51</value> 9819 </interrupt> 9820 </peripheral> 9821 <peripheral> 9822 <name>SDIO</name> 9823 <description>Secure digital input/output 9824 interface</description> 9825 <groupName>SDIO</groupName> 9826 <baseAddress>0x40012C00</baseAddress> 9827 <addressBlock> 9828 <offset>0x0</offset> 9829 <size>0x400</size> 9830 <usage>registers</usage> 9831 </addressBlock> 9832 <interrupt> 9833 <name>SDIO</name> 9834 <description>SDIO global interrupt</description> 9835 <value>49</value> 9836 </interrupt> 9837 <registers> 9838 <register> 9839 <name>POWER</name> 9840 <displayName>POWER</displayName> 9841 <description>power control register</description> 9842 <addressOffset>0x0</addressOffset> 9843 <size>0x20</size> 9844 <access>read-write</access> 9845 <resetValue>0x00000000</resetValue> 9846 <fields> 9847 <field> 9848 <name>PWRCTRL</name> 9849 <description>PWRCTRL</description> 9850 <bitOffset>0</bitOffset> 9851 <bitWidth>2</bitWidth> 9852 <enumeratedValues><name>PWRCTRL</name><usage>read-write</usage><enumeratedValue><name>PowerOff</name><description>Power off</description><value>0</value></enumeratedValue><enumeratedValue><name>PowerOn</name><description>Power on</description><value>3</value></enumeratedValue></enumeratedValues> 9853 </field> 9854 </fields> 9855 </register> 9856 <register> 9857 <name>CLKCR</name> 9858 <displayName>CLKCR</displayName> 9859 <description>SDI clock control register</description> 9860 <addressOffset>0x4</addressOffset> 9861 <size>0x20</size> 9862 <access>read-write</access> 9863 <resetValue>0x00000000</resetValue> 9864 <fields> 9865 <field> 9866 <name>HWFC_EN</name> 9867 <description>HW Flow Control enable</description> 9868 <bitOffset>14</bitOffset> 9869 <bitWidth>1</bitWidth> 9870 <enumeratedValues><name>HWFC_EN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>HW Flow Control is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>HW Flow Control is enabled</description><value>1</value></enumeratedValue></enumeratedValues> 9871 </field> 9872 <field> 9873 <name>NEGEDGE</name> 9874 <description>SDIO_CK dephasing selection 9875 bit</description> 9876 <bitOffset>13</bitOffset> 9877 <bitWidth>1</bitWidth> 9878 <enumeratedValues><name>NEGEDGE</name><usage>read-write</usage><enumeratedValue><name>Rising</name><description>SDIO_CK generated on the rising edge</description><value>0</value></enumeratedValue><enumeratedValue><name>Falling</name><description>SDIO_CK generated on the falling edge</description><value>1</value></enumeratedValue></enumeratedValues> 9879 </field> 9880 <field> 9881 <name>WIDBUS</name> 9882 <description>Wide bus mode enable bit</description> 9883 <bitOffset>11</bitOffset> 9884 <bitWidth>2</bitWidth> 9885 <enumeratedValues><name>WIDBUS</name><usage>read-write</usage><enumeratedValue><name>BusWidth1</name><description>1 lane wide bus</description><value>0</value></enumeratedValue><enumeratedValue><name>BusWidth4</name><description>4 lane wide bus</description><value>1</value></enumeratedValue><enumeratedValue><name>BusWidth8</name><description>8 lane wide bus</description><value>2</value></enumeratedValue></enumeratedValues> 9886 </field> 9887 <field> 9888 <name>BYPASS</name> 9889 <description>Clock divider bypass enable 9890 bit</description> 9891 <bitOffset>10</bitOffset> 9892 <bitWidth>1</bitWidth> 9893 <enumeratedValues><name>BYPASS</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>SDIOCLK is divided according to the CLKDIV value before driving the SDIO_CK output signal.</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>SDIOCLK directly drives the SDIO_CK output signal</description><value>1</value></enumeratedValue></enumeratedValues> 9894 </field> 9895 <field> 9896 <name>PWRSAV</name> 9897 <description>Power saving configuration 9898 bit</description> 9899 <bitOffset>9</bitOffset> 9900 <bitWidth>1</bitWidth> 9901 <enumeratedValues><name>PWRSAV</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>SDIO_CK is only enabled when the bus is active</description><value>1</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>SDIO_CK clock is always enabled</description><value>0</value></enumeratedValue></enumeratedValues> 9902 </field> 9903 <field> 9904 <name>CLKEN</name> 9905 <description>Clock enable bit</description> 9906 <bitOffset>8</bitOffset> 9907 <bitWidth>1</bitWidth> 9908 <enumeratedValues><name>CLKEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Disable clock</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Enable clock</description><value>1</value></enumeratedValue></enumeratedValues> 9909 </field> 9910 <field> 9911 <name>CLKDIV</name> 9912 <description>Clock divide factor</description> 9913 <bitOffset>0</bitOffset> 9914 <bitWidth>8</bitWidth> 9915 <writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint> 9916 </field> 9917 </fields> 9918 </register> 9919 <register> 9920 <name>ARG</name> 9921 <displayName>ARG</displayName> 9922 <description>argument register</description> 9923 <addressOffset>0x8</addressOffset> 9924 <size>0x20</size> 9925 <access>read-write</access> 9926 <resetValue>0x00000000</resetValue> 9927 <fields> 9928 <field> 9929 <name>CMDARG</name> 9930 <description>Command argument</description> 9931 <bitOffset>0</bitOffset> 9932 <bitWidth>32</bitWidth> 9933 <writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint> 9934 </field> 9935 </fields> 9936 </register> 9937 <register> 9938 <name>CMD</name> 9939 <displayName>CMD</displayName> 9940 <description>command register</description> 9941 <addressOffset>0xC</addressOffset> 9942 <size>0x20</size> 9943 <access>read-write</access> 9944 <resetValue>0x00000000</resetValue> 9945 <fields> 9946 <field> 9947 <name>CE_ATACMD</name> 9948 <description>CE-ATA command</description> 9949 <bitOffset>14</bitOffset> 9950 <bitWidth>1</bitWidth> 9951 <enumeratedValues><name>CE_ATACMD</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>CE-ATA command disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>CE-ATA command enabled</description><value>1</value></enumeratedValue></enumeratedValues> 9952 </field> 9953 <field> 9954 <name>nIEN</name> 9955 <description>not Interrupt Enable</description> 9956 <bitOffset>13</bitOffset> 9957 <bitWidth>1</bitWidth> 9958 <enumeratedValues><name>nIEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Interrupts to the CE-ATA not disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt to the CE-ATA are disabled</description><value>1</value></enumeratedValue></enumeratedValues> 9959 </field> 9960 <field> 9961 <name>ENCMDcompl</name> 9962 <description>Enable CMD completion</description> 9963 <bitOffset>12</bitOffset> 9964 <bitWidth>1</bitWidth> 9965 <enumeratedValues><name>ENCMDcompl</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Command complete signal disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Command complete signal enabled</description><value>1</value></enumeratedValue></enumeratedValues> 9966 </field> 9967 <field> 9968 <name>SDIOSuspend</name> 9969 <description>SD I/O suspend command</description> 9970 <bitOffset>11</bitOffset> 9971 <bitWidth>1</bitWidth> 9972 <enumeratedValues><name>SDIOSuspend</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Next command is not a SDIO suspend command</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Next command send is a SDIO suspend command</description><value>1</value></enumeratedValue></enumeratedValues> 9973 </field> 9974 <field> 9975 <name>CPSMEN</name> 9976 <description>Command path state machine (CPSM) Enable 9977 bit</description> 9978 <bitOffset>10</bitOffset> 9979 <bitWidth>1</bitWidth> 9980 <enumeratedValues><name>CPSMEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Command path state machine disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Command path state machine enabled</description><value>1</value></enumeratedValue></enumeratedValues> 9981 </field> 9982 <field> 9983 <name>WAITPEND</name> 9984 <description>CPSM Waits for ends of data transfer 9985 (CmdPend internal signal).</description> 9986 <bitOffset>9</bitOffset> 9987 <bitWidth>1</bitWidth> 9988 <enumeratedValues><name>WAITPEND</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Don't wait for data end</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Wait for end of data transfer signal before sending command</description><value>1</value></enumeratedValue></enumeratedValues> 9989 </field> 9990 <field> 9991 <name>WAITINT</name> 9992 <description>CPSM waits for interrupt 9993 request</description> 9994 <bitOffset>8</bitOffset> 9995 <bitWidth>1</bitWidth> 9996 <enumeratedValues><name>WAITINT</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Don't wait for interrupt request</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Wait for interrupt request</description><value>1</value></enumeratedValue></enumeratedValues> 9997 </field> 9998 <field> 9999 <name>WAITRESP</name> 10000 <description>Wait for response bits</description> 10001 <bitOffset>6</bitOffset> 10002 <bitWidth>2</bitWidth> 10003 <enumeratedValues><name>WAITRESP</name><usage>read-write</usage><enumeratedValue><name>NoResponse</name><description>No response</description><value>0</value></enumeratedValue><enumeratedValue><name>ShortResponse</name><description>Short response</description><value>1</value></enumeratedValue><enumeratedValue><name>NoResponse2</name><description>No reponse</description><value>2</value></enumeratedValue><enumeratedValue><name>LongResponse</name><description>Long reponse</description><value>3</value></enumeratedValue></enumeratedValues> 10004 </field> 10005 <field> 10006 <name>CMDINDEX</name> 10007 <description>Command index</description> 10008 <bitOffset>0</bitOffset> 10009 <bitWidth>6</bitWidth> 10010 <writeConstraint><range><minimum>0</minimum><maximum>63</maximum></range></writeConstraint> 10011 </field> 10012 </fields> 10013 </register> 10014 <register> 10015 <name>RESPCMD</name> 10016 <displayName>RESPCMD</displayName> 10017 <description>command response register</description> 10018 <addressOffset>0x10</addressOffset> 10019 <size>0x20</size> 10020 <access>read-only</access> 10021 <resetValue>0x00000000</resetValue> 10022 <fields> 10023 <field> 10024 <name>RESPCMD</name> 10025 <description>Response command index</description> 10026 <bitOffset>0</bitOffset> 10027 <bitWidth>6</bitWidth> 10028 <writeConstraint><range><minimum>0</minimum><maximum>63</maximum></range></writeConstraint> 10029 </field> 10030 </fields> 10031 </register> 10032 <register> 10033 <name>RESP1</name> 10034 <displayName>RESP1</displayName> 10035 <description>response 1..4 register</description> 10036 <addressOffset>0x14</addressOffset> 10037 <size>0x20</size> 10038 <access>read-only</access> 10039 <resetValue>0x00000000</resetValue> 10040 <fields> 10041 <field> 10042 <name>CARDSTATUS1</name> 10043 <description>see Table 132.</description> 10044 <bitOffset>0</bitOffset> 10045 <bitWidth>32</bitWidth> 10046 <writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint> 10047 </field> 10048 </fields> 10049 </register> 10050 <register> 10051 <name>RESP2</name> 10052 <displayName>RESP2</displayName> 10053 <description>response 1..4 register</description> 10054 <addressOffset>0x18</addressOffset> 10055 <size>0x20</size> 10056 <access>read-only</access> 10057 <resetValue>0x00000000</resetValue> 10058 <fields> 10059 <field> 10060 <name>CARDSTATUS2</name> 10061 <description>see Table 132.</description> 10062 <bitOffset>0</bitOffset> 10063 <bitWidth>32</bitWidth> 10064 <writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint> 10065 </field> 10066 </fields> 10067 </register> 10068 <register> 10069 <name>RESP3</name> 10070 <displayName>RESP3</displayName> 10071 <description>response 1..4 register</description> 10072 <addressOffset>0x1C</addressOffset> 10073 <size>0x20</size> 10074 <access>read-only</access> 10075 <resetValue>0x00000000</resetValue> 10076 <fields> 10077 <field> 10078 <name>CARDSTATUS3</name> 10079 <description>see Table 132.</description> 10080 <bitOffset>0</bitOffset> 10081 <bitWidth>32</bitWidth> 10082 <writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint> 10083 </field> 10084 </fields> 10085 </register> 10086 <register> 10087 <name>RESP4</name> 10088 <displayName>RESP4</displayName> 10089 <description>response 1..4 register</description> 10090 <addressOffset>0x20</addressOffset> 10091 <size>0x20</size> 10092 <access>read-only</access> 10093 <resetValue>0x00000000</resetValue> 10094 <fields> 10095 <field> 10096 <name>CARDSTATUS4</name> 10097 <description>see Table 132.</description> 10098 <bitOffset>0</bitOffset> 10099 <bitWidth>32</bitWidth> 10100 <writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint> 10101 </field> 10102 </fields> 10103 </register> 10104 <register> 10105 <name>DTIMER</name> 10106 <displayName>DTIMER</displayName> 10107 <description>data timer register</description> 10108 <addressOffset>0x24</addressOffset> 10109 <size>0x20</size> 10110 <access>read-write</access> 10111 <resetValue>0x00000000</resetValue> 10112 <fields> 10113 <field> 10114 <name>DATATIME</name> 10115 <description>Data timeout period</description> 10116 <bitOffset>0</bitOffset> 10117 <bitWidth>32</bitWidth> 10118 <writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint> 10119 </field> 10120 </fields> 10121 </register> 10122 <register> 10123 <name>DLEN</name> 10124 <displayName>DLEN</displayName> 10125 <description>data length register</description> 10126 <addressOffset>0x28</addressOffset> 10127 <size>0x20</size> 10128 <access>read-write</access> 10129 <resetValue>0x00000000</resetValue> 10130 <fields> 10131 <field> 10132 <name>DATALENGTH</name> 10133 <description>Data length value</description> 10134 <bitOffset>0</bitOffset> 10135 <bitWidth>25</bitWidth> 10136 <writeConstraint><range><minimum>0</minimum><maximum>33554431</maximum></range></writeConstraint> 10137 </field> 10138 </fields> 10139 </register> 10140 <register> 10141 <name>DCTRL</name> 10142 <displayName>DCTRL</displayName> 10143 <description>data control register</description> 10144 <addressOffset>0x2C</addressOffset> 10145 <size>0x20</size> 10146 <access>read-write</access> 10147 <resetValue>0x00000000</resetValue> 10148 <fields> 10149 <field> 10150 <name>SDIOEN</name> 10151 <description>SD I/O enable functions</description> 10152 <bitOffset>11</bitOffset> 10153 <bitWidth>1</bitWidth> 10154 <enumeratedValues><name>SDIOEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>SDIO operations disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>SDIO operations enabled</description><value>1</value></enumeratedValue></enumeratedValues> 10155 </field> 10156 <field> 10157 <name>RWMOD</name> 10158 <description>Read wait mode</description> 10159 <bitOffset>10</bitOffset> 10160 <bitWidth>1</bitWidth> 10161 <enumeratedValues><name>RWMOD</name><usage>read-write</usage><enumeratedValue><name>D2</name><description>Read wait control stopping using SDIO_D2</description><value>0</value></enumeratedValue><enumeratedValue><name>Ck</name><description>Read wait control using SDIO_CK</description><value>1</value></enumeratedValue></enumeratedValues> 10162 </field> 10163 <field> 10164 <name>RWSTOP</name> 10165 <description>Read wait stop</description> 10166 <bitOffset>9</bitOffset> 10167 <bitWidth>1</bitWidth> 10168 <enumeratedValues><name>RWSTOP</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Read wait in progress if RWSTART is enabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Enable for read wait stop if RWSTART is enabled</description><value>1</value></enumeratedValue></enumeratedValues> 10169 </field> 10170 <field> 10171 <name>RWSTART</name> 10172 <description>Read wait start</description> 10173 <bitOffset>8</bitOffset> 10174 <bitWidth>1</bitWidth> 10175 <enumeratedValues><name>RWSTART</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Don't start read wait operation</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Read wait operation starts</description><value>1</value></enumeratedValue></enumeratedValues> 10176 </field> 10177 <field> 10178 <name>DBLOCKSIZE</name> 10179 <description>Data block size</description> 10180 <bitOffset>4</bitOffset> 10181 <bitWidth>4</bitWidth> 10182 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 10183 </field> 10184 <field> 10185 <name>DMAEN</name> 10186 <description>DMA enable bit</description> 10187 <bitOffset>3</bitOffset> 10188 <bitWidth>1</bitWidth> 10189 <enumeratedValues><name>DMAEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Dma disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Dma enabled</description><value>1</value></enumeratedValue></enumeratedValues> 10190 </field> 10191 <field> 10192 <name>DTMODE</name> 10193 <description>Data transfer mode selection 1: Stream 10194 or SDIO multibyte data transfer.</description> 10195 <bitOffset>2</bitOffset> 10196 <bitWidth>1</bitWidth> 10197 <enumeratedValues><name>DTMODE</name><usage>read-write</usage><enumeratedValue><name>BlockMode</name><description>Bloack data transfer</description><value>0</value></enumeratedValue><enumeratedValue><name>StreamMode</name><description>Stream or SDIO multibyte data transfer</description><value>1</value></enumeratedValue></enumeratedValues> 10198 </field> 10199 <field> 10200 <name>DTDIR</name> 10201 <description>Data transfer direction 10202 selection</description> 10203 <bitOffset>1</bitOffset> 10204 <bitWidth>1</bitWidth> 10205 <enumeratedValues><name>DTDIR</name><usage>read-write</usage><enumeratedValue><name>ControllerToCard</name><description>From controller to card</description><value>0</value></enumeratedValue><enumeratedValue><name>CardToController</name><description>From card to controller</description><value>1</value></enumeratedValue></enumeratedValues> 10206 </field> 10207 <field> 10208 <name>DTEN</name> 10209 <description>DTEN</description> 10210 <bitOffset>0</bitOffset> 10211 <bitWidth>1</bitWidth> 10212 <enumeratedValues><name>DTEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Start transfer</description><value>1</value></enumeratedValue></enumeratedValues> 10213 </field> 10214 </fields> 10215 </register> 10216 <register> 10217 <name>DCOUNT</name> 10218 <displayName>DCOUNT</displayName> 10219 <description>data counter register</description> 10220 <addressOffset>0x30</addressOffset> 10221 <size>0x20</size> 10222 <access>read-only</access> 10223 <resetValue>0x00000000</resetValue> 10224 <fields> 10225 <field> 10226 <name>DATACOUNT</name> 10227 <description>Data count value</description> 10228 <bitOffset>0</bitOffset> 10229 <bitWidth>25</bitWidth> 10230 <writeConstraint><range><minimum>0</minimum><maximum>33554431</maximum></range></writeConstraint> 10231 </field> 10232 </fields> 10233 </register> 10234 <register> 10235 <name>STA</name> 10236 <displayName>STA</displayName> 10237 <description>status register</description> 10238 <addressOffset>0x34</addressOffset> 10239 <size>0x20</size> 10240 <access>read-only</access> 10241 <resetValue>0x00000000</resetValue> 10242 <fields> 10243 <field> 10244 <name>CEATAEND</name> 10245 <description>CE-ATA command completion signal 10246 received for CMD61</description> 10247 <bitOffset>23</bitOffset> 10248 <bitWidth>1</bitWidth> 10249 <enumeratedValues><name>CEATAEND</name><usage>read-write</usage><enumeratedValue><name>NotReceived</name><description>Completion signal not received</description><value>0</value></enumeratedValue><enumeratedValue><name>Received</name><description>CE-ATA command completion signal received for CMD61</description><value>1</value></enumeratedValue></enumeratedValues> 10250 </field> 10251 <field> 10252 <name>SDIOIT</name> 10253 <description>SDIO interrupt received</description> 10254 <bitOffset>22</bitOffset> 10255 <bitWidth>1</bitWidth> 10256 <enumeratedValues><name>SDIOIT</name><usage>read-write</usage><enumeratedValue><name>NotReceived</name><description>SDIO interrupt not receieved</description><value>0</value></enumeratedValue><enumeratedValue><name>Received</name><description>SDIO interrupt received</description><value>1</value></enumeratedValue></enumeratedValues> 10257 </field> 10258 <field> 10259 <name>RXDAVL</name> 10260 <description>Data available in receive 10261 FIFO</description> 10262 <bitOffset>21</bitOffset> 10263 <bitWidth>1</bitWidth> 10264 <enumeratedValues><name>RXDAVL</name><usage>read-write</usage><enumeratedValue><name>NotAvailable</name><description>Data not available in receive FIFO</description><value>0</value></enumeratedValue><enumeratedValue><name>Available</name><description>Data available in receive FIFO</description><value>1</value></enumeratedValue></enumeratedValues> 10265 </field> 10266 <field> 10267 <name>TXDAVL</name> 10268 <description>Data available in transmit 10269 FIFO</description> 10270 <bitOffset>20</bitOffset> 10271 <bitWidth>1</bitWidth> 10272 <enumeratedValues><name>TXDAVL</name><usage>read-write</usage><enumeratedValue><name>NotAvailable</name><description>Data not available in transmit FIFO</description><value>0</value></enumeratedValue><enumeratedValue><name>Available</name><description>Data available in transmit FIFO</description><value>1</value></enumeratedValue></enumeratedValues> 10273 </field> 10274 <field> 10275 <name>RXFIFOE</name> 10276 <description>Receive FIFO empty</description> 10277 <bitOffset>19</bitOffset> 10278 <bitWidth>1</bitWidth> 10279 <enumeratedValues><name>RXFIFOE</name><usage>read-write</usage><enumeratedValue><name>NotEmpty</name><description>Receive FIFO not empty</description><value>0</value></enumeratedValue><enumeratedValue><name>Empty</name><description>Receive FIFO empty</description><value>1</value></enumeratedValue></enumeratedValues> 10280 </field> 10281 <field> 10282 <name>TXFIFOE</name> 10283 <description>Transmit FIFO empty</description> 10284 <bitOffset>18</bitOffset> 10285 <bitWidth>1</bitWidth> 10286 <enumeratedValues><name>TXFIFOE</name><usage>read-write</usage><enumeratedValue><name>NotEmpty</name><description>Transmit FIFO not empty</description><value>0</value></enumeratedValue><enumeratedValue><name>Empty</name><description>Transmit FIFO empty. When HW Flow Control is enabled, TXFIFOE signals becomes activated when the FIFO contains 2 words.</description><value>1</value></enumeratedValue></enumeratedValues> 10287 </field> 10288 <field> 10289 <name>RXFIFOF</name> 10290 <description>Receive FIFO full</description> 10291 <bitOffset>17</bitOffset> 10292 <bitWidth>1</bitWidth> 10293 <enumeratedValues><name>RXFIFOF</name><usage>read-write</usage><enumeratedValue><name>NotFull</name><description>Transmit FIFO not full</description><value>0</value></enumeratedValue><enumeratedValue><name>Full</name><description>Receive FIFO full. When HW Flow Control is enabled, RXFIFOF signals becomes activated 2 words before the FIFO is full.</description><value>1</value></enumeratedValue></enumeratedValues> 10294 </field> 10295 <field> 10296 <name>TXFIFOF</name> 10297 <description>Transmit FIFO full</description> 10298 <bitOffset>16</bitOffset> 10299 <bitWidth>1</bitWidth> 10300 <enumeratedValues><name>TXFIFOF</name><usage>read-write</usage><enumeratedValue><name>NotFull</name><description>Transmit FIFO not full</description><value>0</value></enumeratedValue><enumeratedValue><name>Full</name><description>Transmit FIFO full</description><value>1</value></enumeratedValue></enumeratedValues> 10301 </field> 10302 <field> 10303 <name>RXFIFOHF</name> 10304 <description>Receive FIFO half full: there are at 10305 least 8 words in the FIFO</description> 10306 <bitOffset>15</bitOffset> 10307 <bitWidth>1</bitWidth> 10308 <enumeratedValues><name>RXFIFOHF</name><usage>read-write</usage><enumeratedValue><name>NotHalfFull</name><description>Receive FIFO not half full</description><value>0</value></enumeratedValue><enumeratedValue><name>HalfFull</name><description>Receive FIFO half full. At least 8 words in the FIFO</description><value>1</value></enumeratedValue></enumeratedValues> 10309 </field> 10310 <field> 10311 <name>TXFIFOHE</name> 10312 <description>Transmit FIFO half empty: at least 8 10313 words can be written into the FIFO</description> 10314 <bitOffset>14</bitOffset> 10315 <bitWidth>1</bitWidth> 10316 <enumeratedValues><name>TXFIFOHE</name><usage>read-write</usage><enumeratedValue><name>NotHalfEmpty</name><description>Transmit FIFO not half empty</description><value>0</value></enumeratedValue><enumeratedValue><name>HalfEmpty</name><description>Transmit FIFO half empty. At least 8 words can be written into the FIFO</description><value>1</value></enumeratedValue></enumeratedValues> 10317 </field> 10318 <field> 10319 <name>RXACT</name> 10320 <description>Data receive in progress</description> 10321 <bitOffset>13</bitOffset> 10322 <bitWidth>1</bitWidth> 10323 <enumeratedValues><name>RXACT</name><usage>read-write</usage><enumeratedValue><name>NotInProgress</name><description>Data receive not in progress</description><value>0</value></enumeratedValue><enumeratedValue><name>InProgress</name><description>Data receive in progress</description><value>1</value></enumeratedValue></enumeratedValues> 10324 </field> 10325 <field> 10326 <name>TXACT</name> 10327 <description>Data transmit in progress</description> 10328 <bitOffset>12</bitOffset> 10329 <bitWidth>1</bitWidth> 10330 <enumeratedValues><name>TXACT</name><usage>read-write</usage><enumeratedValue><name>NotInProgress</name><description>Data transmit is not in progress</description><value>0</value></enumeratedValue><enumeratedValue><name>InProgress</name><description>Data transmit in progress</description><value>1</value></enumeratedValue></enumeratedValues> 10331 </field> 10332 <field> 10333 <name>CMDACT</name> 10334 <description>Command transfer in 10335 progress</description> 10336 <bitOffset>11</bitOffset> 10337 <bitWidth>1</bitWidth> 10338 <enumeratedValues><name>CMDACT</name><usage>read-write</usage><enumeratedValue><name>NotInProgress</name><description>Command transfer not in progress</description><value>0</value></enumeratedValue><enumeratedValue><name>InProgress</name><description>Command tranfer in progress</description><value>1</value></enumeratedValue></enumeratedValues> 10339 </field> 10340 <field> 10341 <name>DBCKEND</name> 10342 <description>Data block sent/received (CRC check 10343 passed)</description> 10344 <bitOffset>10</bitOffset> 10345 <bitWidth>1</bitWidth> 10346 <enumeratedValues><name>DBCKEND</name><usage>read-write</usage><enumeratedValue><name>NotTransferred</name><description>Data block not sent/received (CRC check failed)</description><value>0</value></enumeratedValue><enumeratedValue><name>Transferred</name><description>Data block sent/received (CRC check passed)</description><value>1</value></enumeratedValue></enumeratedValues> 10347 </field> 10348 <field> 10349 <name>STBITERR</name> 10350 <description>Start bit not detected on all data 10351 signals in wide bus mode</description> 10352 <bitOffset>9</bitOffset> 10353 <bitWidth>1</bitWidth> 10354 <enumeratedValues><name>STBITERR</name><usage>read-write</usage><enumeratedValue><name>Detected</name><description>No start bit detected error</description><value>0</value></enumeratedValue><enumeratedValue><name>NotDetected</name><description>Start bit not detected error</description><value>1</value></enumeratedValue></enumeratedValues> 10355 </field> 10356 <field> 10357 <name>DATAEND</name> 10358 <description>Data end (data counter, SDIDCOUNT, is 10359 zero)</description> 10360 <bitOffset>8</bitOffset> 10361 <bitWidth>1</bitWidth> 10362 <enumeratedValues><name>DATAEND</name><usage>read-write</usage><enumeratedValue><name>Done</name><description>Data end (DCOUNT, is zero)</description><value>1</value></enumeratedValue><enumeratedValue><name>NotDone</name><description>Not done</description><value>0</value></enumeratedValue></enumeratedValues> 10363 </field> 10364 <field> 10365 <name>CMDSENT</name> 10366 <description>Command sent (no response 10367 required)</description> 10368 <bitOffset>7</bitOffset> 10369 <bitWidth>1</bitWidth> 10370 <enumeratedValues><name>CMDSENT</name><usage>read-write</usage><enumeratedValue><name>NotSent</name><description>Command not sent</description><value>0</value></enumeratedValue><enumeratedValue><name>Sent</name><description>Command sent (no response required)</description><value>1</value></enumeratedValue></enumeratedValues> 10371 </field> 10372 <field> 10373 <name>CMDREND</name> 10374 <description>Command response received (CRC check 10375 passed)</description> 10376 <bitOffset>6</bitOffset> 10377 <bitWidth>1</bitWidth> 10378 <enumeratedValues><name>CMDREND</name><usage>read-write</usage><enumeratedValue><name>NotDone</name><description>Command not done</description><value>0</value></enumeratedValue><enumeratedValue><name>Done</name><description>Command response received (CRC check passed)</description><value>1</value></enumeratedValue></enumeratedValues> 10379 </field> 10380 <field> 10381 <name>RXOVERR</name> 10382 <description>Received FIFO overrun 10383 error</description> 10384 <bitOffset>5</bitOffset> 10385 <bitWidth>1</bitWidth> 10386 <enumeratedValues><name>RXOVERR</name><usage>read-write</usage><enumeratedValue><name>NoOverrun</name><description>No FIFO overrun error</description><value>0</value></enumeratedValue><enumeratedValue><name>Overrun</name><description>Receive FIFO overrun error</description><value>1</value></enumeratedValue></enumeratedValues> 10387 </field> 10388 <field> 10389 <name>TXUNDERR</name> 10390 <description>Transmit FIFO underrun 10391 error</description> 10392 <bitOffset>4</bitOffset> 10393 <bitWidth>1</bitWidth> 10394 <enumeratedValues><name>TXUNDERR</name><usage>read-write</usage><enumeratedValue><name>NoUnderrun</name><description>No transmit FIFO underrun error</description><value>0</value></enumeratedValue><enumeratedValue><name>Underrun</name><description>Transmit FIFO underrun error</description><value>1</value></enumeratedValue></enumeratedValues> 10395 </field> 10396 <field> 10397 <name>DTIMEOUT</name> 10398 <description>Data timeout</description> 10399 <bitOffset>3</bitOffset> 10400 <bitWidth>1</bitWidth> 10401 <enumeratedValues><name>DTIMEOUT</name><usage>read-write</usage><enumeratedValue><name>NoTimeout</name><description>No data timeout</description><value>0</value></enumeratedValue><enumeratedValue><name>Timeout</name><description>Data timeout</description><value>1</value></enumeratedValue></enumeratedValues> 10402 </field> 10403 <field> 10404 <name>CTIMEOUT</name> 10405 <description>Command response timeout</description> 10406 <bitOffset>2</bitOffset> 10407 <bitWidth>1</bitWidth> 10408 <enumeratedValues><name>CTIMEOUT</name><usage>read-write</usage><enumeratedValue><name>NoTimeout</name><description>No Command timeout</description><value>0</value></enumeratedValue><enumeratedValue><name>Timeout</name><description>Command timeout</description><value>1</value></enumeratedValue></enumeratedValues> 10409 </field> 10410 <field> 10411 <name>DCRCFAIL</name> 10412 <description>Data block sent/received (CRC check 10413 failed)</description> 10414 <bitOffset>1</bitOffset> 10415 <bitWidth>1</bitWidth> 10416 <enumeratedValues><name>DCRCFAIL</name><usage>read-write</usage><enumeratedValue><name>NotFailed</name><description>No Data block sent/received crc check fail</description><value>0</value></enumeratedValue><enumeratedValue><name>Failed</name><description>Data block sent/received crc failed</description><value>1</value></enumeratedValue></enumeratedValues> 10417 </field> 10418 <field> 10419 <name>CCRCFAIL</name> 10420 <description>Command response received (CRC check 10421 failed)</description> 10422 <bitOffset>0</bitOffset> 10423 <bitWidth>1</bitWidth> 10424 <enumeratedValues><name>CCRCFAIL</name><usage>read-write</usage><enumeratedValue><name>NotFailed</name><description>Command response received, crc check passed</description><value>0</value></enumeratedValue><enumeratedValue><name>Failed</name><description>Command response received, crc check failed</description><value>1</value></enumeratedValue></enumeratedValues> 10425 </field> 10426 </fields> 10427 </register> 10428 <register> 10429 <name>ICR</name> 10430 <displayName>ICR</displayName> 10431 <description>interrupt clear register</description> 10432 <addressOffset>0x38</addressOffset> 10433 <size>0x20</size> 10434 <access>read-write</access> 10435 <resetValue>0x00000000</resetValue> 10436 <fields> 10437 <field> 10438 <name>CEATAENDC</name> 10439 <description>CEATAEND flag clear bit</description> 10440 <bitOffset>23</bitOffset> 10441 <bitWidth>1</bitWidth> 10442 <enumeratedValues derivedFrom="CCRCFAILCW"/> 10443 </field> 10444 <field> 10445 <name>SDIOITC</name> 10446 <description>SDIOIT flag clear bit</description> 10447 <bitOffset>22</bitOffset> 10448 <bitWidth>1</bitWidth> 10449 <enumeratedValues derivedFrom="CCRCFAILCW"/> 10450 </field> 10451 <field> 10452 <name>DBCKENDC</name> 10453 <description>DBCKEND flag clear bit</description> 10454 <bitOffset>10</bitOffset> 10455 <bitWidth>1</bitWidth> 10456 <enumeratedValues derivedFrom="CCRCFAILCW"/> 10457 </field> 10458 <field> 10459 <name>STBITERRC</name> 10460 <description>STBITERR flag clear bit</description> 10461 <bitOffset>9</bitOffset> 10462 <bitWidth>1</bitWidth> 10463 <enumeratedValues derivedFrom="CCRCFAILCW"/> 10464 </field> 10465 <field> 10466 <name>DATAENDC</name> 10467 <description>DATAEND flag clear bit</description> 10468 <bitOffset>8</bitOffset> 10469 <bitWidth>1</bitWidth> 10470 <enumeratedValues derivedFrom="CCRCFAILCW"/> 10471 </field> 10472 <field> 10473 <name>CMDSENTC</name> 10474 <description>CMDSENT flag clear bit</description> 10475 <bitOffset>7</bitOffset> 10476 <bitWidth>1</bitWidth> 10477 <enumeratedValues derivedFrom="CCRCFAILCW"/> 10478 </field> 10479 <field> 10480 <name>CMDRENDC</name> 10481 <description>CMDREND flag clear bit</description> 10482 <bitOffset>6</bitOffset> 10483 <bitWidth>1</bitWidth> 10484 <enumeratedValues derivedFrom="CCRCFAILCW"/> 10485 </field> 10486 <field> 10487 <name>RXOVERRC</name> 10488 <description>RXOVERR flag clear bit</description> 10489 <bitOffset>5</bitOffset> 10490 <bitWidth>1</bitWidth> 10491 <enumeratedValues derivedFrom="CCRCFAILCW"/> 10492 </field> 10493 <field> 10494 <name>TXUNDERRC</name> 10495 <description>TXUNDERR flag clear bit</description> 10496 <bitOffset>4</bitOffset> 10497 <bitWidth>1</bitWidth> 10498 <enumeratedValues derivedFrom="CCRCFAILCW"/> 10499 </field> 10500 <field> 10501 <name>DTIMEOUTC</name> 10502 <description>DTIMEOUT flag clear bit</description> 10503 <bitOffset>3</bitOffset> 10504 <bitWidth>1</bitWidth> 10505 <enumeratedValues derivedFrom="CCRCFAILCW"/> 10506 </field> 10507 <field> 10508 <name>CTIMEOUTC</name> 10509 <description>CTIMEOUT flag clear bit</description> 10510 <bitOffset>2</bitOffset> 10511 <bitWidth>1</bitWidth> 10512 <enumeratedValues derivedFrom="CCRCFAILCW"/> 10513 </field> 10514 <field> 10515 <name>DCRCFAILC</name> 10516 <description>DCRCFAIL flag clear bit</description> 10517 <bitOffset>1</bitOffset> 10518 <bitWidth>1</bitWidth> 10519 <enumeratedValues derivedFrom="CCRCFAILCW"/> 10520 </field> 10521 <field> 10522 <name>CCRCFAILC</name> 10523 <description>CCRCFAIL flag clear bit</description> 10524 <bitOffset>0</bitOffset> 10525 <bitWidth>1</bitWidth> 10526 <enumeratedValues><name>CCRCFAILCW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clear flag</description><value>1</value></enumeratedValue></enumeratedValues> 10527 </field> 10528 </fields> 10529 </register> 10530 <register> 10531 <name>MASK</name> 10532 <displayName>MASK</displayName> 10533 <description>mask register</description> 10534 <addressOffset>0x3C</addressOffset> 10535 <size>0x20</size> 10536 <access>read-write</access> 10537 <resetValue>0x00000000</resetValue> 10538 <fields> 10539 <field> 10540 <name>CEATAENDIE</name> 10541 <description>CE-ATA command completion signal 10542 received interrupt enable</description> 10543 <bitOffset>23</bitOffset> 10544 <bitWidth>1</bitWidth> 10545 <enumeratedValues derivedFrom="CCRCFAILIE"/> 10546 </field> 10547 <field> 10548 <name>SDIOITIE</name> 10549 <description>SDIO mode interrupt received interrupt 10550 enable</description> 10551 <bitOffset>22</bitOffset> 10552 <bitWidth>1</bitWidth> 10553 <enumeratedValues derivedFrom="CCRCFAILIE"/> 10554 </field> 10555 <field> 10556 <name>RXDAVLIE</name> 10557 <description>Data available in Rx FIFO interrupt 10558 enable</description> 10559 <bitOffset>21</bitOffset> 10560 <bitWidth>1</bitWidth> 10561 <enumeratedValues derivedFrom="CCRCFAILIE"/> 10562 </field> 10563 <field> 10564 <name>TXDAVLIE</name> 10565 <description>Data available in Tx FIFO interrupt 10566 enable</description> 10567 <bitOffset>20</bitOffset> 10568 <bitWidth>1</bitWidth> 10569 <enumeratedValues derivedFrom="CCRCFAILIE"/> 10570 </field> 10571 <field> 10572 <name>RXFIFOEIE</name> 10573 <description>Rx FIFO empty interrupt 10574 enable</description> 10575 <bitOffset>19</bitOffset> 10576 <bitWidth>1</bitWidth> 10577 <enumeratedValues derivedFrom="CCRCFAILIE"/> 10578 </field> 10579 <field> 10580 <name>TXFIFOEIE</name> 10581 <description>Tx FIFO empty interrupt 10582 enable</description> 10583 <bitOffset>18</bitOffset> 10584 <bitWidth>1</bitWidth> 10585 <enumeratedValues derivedFrom="CCRCFAILIE"/> 10586 </field> 10587 <field> 10588 <name>RXFIFOFIE</name> 10589 <description>Rx FIFO full interrupt 10590 enable</description> 10591 <bitOffset>17</bitOffset> 10592 <bitWidth>1</bitWidth> 10593 <enumeratedValues derivedFrom="CCRCFAILIE"/> 10594 </field> 10595 <field> 10596 <name>TXFIFOFIE</name> 10597 <description>Tx FIFO full interrupt 10598 enable</description> 10599 <bitOffset>16</bitOffset> 10600 <bitWidth>1</bitWidth> 10601 <enumeratedValues derivedFrom="CCRCFAILIE"/> 10602 </field> 10603 <field> 10604 <name>RXFIFOHFIE</name> 10605 <description>Rx FIFO half full interrupt 10606 enable</description> 10607 <bitOffset>15</bitOffset> 10608 <bitWidth>1</bitWidth> 10609 <enumeratedValues derivedFrom="CCRCFAILIE"/> 10610 </field> 10611 <field> 10612 <name>TXFIFOHEIE</name> 10613 <description>Tx FIFO half empty interrupt 10614 enable</description> 10615 <bitOffset>14</bitOffset> 10616 <bitWidth>1</bitWidth> 10617 <enumeratedValues derivedFrom="CCRCFAILIE"/> 10618 </field> 10619 <field> 10620 <name>RXACTIE</name> 10621 <description>Data receive acting interrupt 10622 enable</description> 10623 <bitOffset>13</bitOffset> 10624 <bitWidth>1</bitWidth> 10625 <enumeratedValues derivedFrom="CCRCFAILIE"/> 10626 </field> 10627 <field> 10628 <name>TXACTIE</name> 10629 <description>Data transmit acting interrupt 10630 enable</description> 10631 <bitOffset>12</bitOffset> 10632 <bitWidth>1</bitWidth> 10633 <enumeratedValues derivedFrom="CCRCFAILIE"/> 10634 </field> 10635 <field> 10636 <name>CMDACTIE</name> 10637 <description>Command acting interrupt 10638 enable</description> 10639 <bitOffset>11</bitOffset> 10640 <bitWidth>1</bitWidth> 10641 <enumeratedValues derivedFrom="CCRCFAILIE"/> 10642 </field> 10643 <field> 10644 <name>DBCKENDIE</name> 10645 <description>Data block end interrupt 10646 enable</description> 10647 <bitOffset>10</bitOffset> 10648 <bitWidth>1</bitWidth> 10649 <enumeratedValues derivedFrom="CCRCFAILIE"/> 10650 </field> 10651 <field> 10652 <name>STBITERRIE</name> 10653 <description>Start bit error interrupt 10654 enable</description> 10655 <bitOffset>9</bitOffset> 10656 <bitWidth>1</bitWidth> 10657 <enumeratedValues derivedFrom="CCRCFAILIE"/> 10658 </field> 10659 <field> 10660 <name>DATAENDIE</name> 10661 <description>Data end interrupt enable</description> 10662 <bitOffset>8</bitOffset> 10663 <bitWidth>1</bitWidth> 10664 <enumeratedValues derivedFrom="CCRCFAILIE"/> 10665 </field> 10666 <field> 10667 <name>CMDSENTIE</name> 10668 <description>Command sent interrupt 10669 enable</description> 10670 <bitOffset>7</bitOffset> 10671 <bitWidth>1</bitWidth> 10672 <enumeratedValues derivedFrom="CCRCFAILIE"/> 10673 </field> 10674 <field> 10675 <name>CMDRENDIE</name> 10676 <description>Command response received interrupt 10677 enable</description> 10678 <bitOffset>6</bitOffset> 10679 <bitWidth>1</bitWidth> 10680 <enumeratedValues derivedFrom="CCRCFAILIE"/> 10681 </field> 10682 <field> 10683 <name>RXOVERRIE</name> 10684 <description>Rx FIFO overrun error interrupt 10685 enable</description> 10686 <bitOffset>5</bitOffset> 10687 <bitWidth>1</bitWidth> 10688 <enumeratedValues derivedFrom="CCRCFAILIE"/> 10689 </field> 10690 <field> 10691 <name>TXUNDERRIE</name> 10692 <description>Tx FIFO underrun error interrupt 10693 enable</description> 10694 <bitOffset>4</bitOffset> 10695 <bitWidth>1</bitWidth> 10696 <enumeratedValues derivedFrom="CCRCFAILIE"/> 10697 </field> 10698 <field> 10699 <name>DTIMEOUTIE</name> 10700 <description>Data timeout interrupt 10701 enable</description> 10702 <bitOffset>3</bitOffset> 10703 <bitWidth>1</bitWidth> 10704 <enumeratedValues derivedFrom="CCRCFAILIE"/> 10705 </field> 10706 <field> 10707 <name>CTIMEOUTIE</name> 10708 <description>Command timeout interrupt 10709 enable</description> 10710 <bitOffset>2</bitOffset> 10711 <bitWidth>1</bitWidth> 10712 <enumeratedValues derivedFrom="CCRCFAILIE"/> 10713 </field> 10714 <field> 10715 <name>DCRCFAILIE</name> 10716 <description>Data CRC fail interrupt 10717 enable</description> 10718 <bitOffset>1</bitOffset> 10719 <bitWidth>1</bitWidth> 10720 <enumeratedValues derivedFrom="CCRCFAILIE"/> 10721 </field> 10722 <field> 10723 <name>CCRCFAILIE</name> 10724 <description>Command CRC fail interrupt 10725 enable</description> 10726 <bitOffset>0</bitOffset> 10727 <bitWidth>1</bitWidth> 10728 <enumeratedValues><name>CCRCFAILIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 10729 </field> 10730 </fields> 10731 </register> 10732 <register> 10733 <name>FIFOCNT</name> 10734 <displayName>FIFOCNT</displayName> 10735 <description>FIFO counter register</description> 10736 <addressOffset>0x48</addressOffset> 10737 <size>0x20</size> 10738 <access>read-only</access> 10739 <resetValue>0x00000000</resetValue> 10740 <fields> 10741 <field> 10742 <name>FIFOCOUNT</name> 10743 <description>Remaining number of words to be written 10744 to or read from the FIFO.</description> 10745 <bitOffset>0</bitOffset> 10746 <bitWidth>24</bitWidth> 10747 <writeConstraint><range><minimum>0</minimum><maximum>16777215</maximum></range></writeConstraint> 10748 </field> 10749 </fields> 10750 </register> 10751 <register> 10752 <name>FIFO</name> 10753 <displayName>FIFO</displayName> 10754 <description>data FIFO register</description> 10755 <addressOffset>0x80</addressOffset> 10756 <size>0x20</size> 10757 <access>read-write</access> 10758 <resetValue>0x00000000</resetValue> 10759 <fields> 10760 <field> 10761 <name>FIFOData</name> 10762 <description>Receive and transmit FIFO 10763 data</description> 10764 <bitOffset>0</bitOffset> 10765 <bitWidth>32</bitWidth> 10766 <writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint> 10767 </field> 10768 </fields> 10769 </register> 10770 </registers> 10771 </peripheral> 10772 <peripheral> 10773 <name>ADC1</name> 10774 <description>Analog-to-digital converter</description> 10775 <groupName>ADC</groupName> 10776 <baseAddress>0x40012000</baseAddress> 10777 <addressBlock> 10778 <offset>0x0</offset> 10779 <size>0x51</size> 10780 <usage>registers</usage> 10781 </addressBlock> 10782 <interrupt> 10783 <name>ADC</name> 10784 <description>ADC1 global interrupt</description> 10785 <value>18</value> 10786 </interrupt> 10787 <registers> 10788 <register> 10789 <name>SR</name> 10790 <displayName>SR</displayName> 10791 <description>status register</description> 10792 <addressOffset>0x0</addressOffset> 10793 <size>0x20</size> 10794 <access>read-write</access> 10795 <resetValue>0x00000000</resetValue> 10796 <fields> 10797 <field> 10798 <name>OVR</name> 10799 <description>Overrun</description> 10800 <bitOffset>5</bitOffset> 10801 <bitWidth>1</bitWidth> 10802 <enumeratedValues><name>OVR</name><usage>read-write</usage><enumeratedValue><name>NoOverrun</name><description>No overrun occurred</description><value>0</value></enumeratedValue><enumeratedValue><name>Overrun</name><description>Overrun occurred</description><value>1</value></enumeratedValue></enumeratedValues> 10803 </field> 10804 <field> 10805 <name>STRT</name> 10806 <description>Regular channel start flag</description> 10807 <bitOffset>4</bitOffset> 10808 <bitWidth>1</bitWidth> 10809 <enumeratedValues><name>STRT</name><usage>read-write</usage><enumeratedValue><name>NotStarted</name><description>No regular channel conversion started</description><value>0</value></enumeratedValue><enumeratedValue><name>Started</name><description>Regular channel conversion has started</description><value>1</value></enumeratedValue></enumeratedValues> 10810 </field> 10811 <field> 10812 <name>JSTRT</name> 10813 <description>Injected channel start 10814 flag</description> 10815 <bitOffset>3</bitOffset> 10816 <bitWidth>1</bitWidth> 10817 <enumeratedValues><name>JSTRT</name><usage>read-write</usage><enumeratedValue><name>NotStarted</name><description>No injected channel conversion started</description><value>0</value></enumeratedValue><enumeratedValue><name>Started</name><description>Injected channel conversion has started</description><value>1</value></enumeratedValue></enumeratedValues> 10818 </field> 10819 <field> 10820 <name>JEOC</name> 10821 <description>Injected channel end of 10822 conversion</description> 10823 <bitOffset>2</bitOffset> 10824 <bitWidth>1</bitWidth> 10825 <enumeratedValues><name>JEOC</name><usage>read-write</usage><enumeratedValue><name>NotComplete</name><description>Conversion is not complete</description><value>0</value></enumeratedValue><enumeratedValue><name>Complete</name><description>Conversion complete</description><value>1</value></enumeratedValue></enumeratedValues> 10826 </field> 10827 <field> 10828 <name>EOC</name> 10829 <description>Regular channel end of 10830 conversion</description> 10831 <bitOffset>1</bitOffset> 10832 <bitWidth>1</bitWidth> 10833 <enumeratedValues><name>EOC</name><usage>read-write</usage><enumeratedValue><name>NotComplete</name><description>Conversion is not complete</description><value>0</value></enumeratedValue><enumeratedValue><name>Complete</name><description>Conversion complete</description><value>1</value></enumeratedValue></enumeratedValues> 10834 </field> 10835 <field> 10836 <name>AWD</name> 10837 <description>Analog watchdog flag</description> 10838 <bitOffset>0</bitOffset> 10839 <bitWidth>1</bitWidth> 10840 <enumeratedValues><name>AWD</name><usage>read-write</usage><enumeratedValue><name>NoEvent</name><description>No analog watchdog event occurred</description><value>0</value></enumeratedValue><enumeratedValue><name>Event</name><description>Analog watchdog event occurred</description><value>1</value></enumeratedValue></enumeratedValues> 10841 </field> 10842 </fields> 10843 </register> 10844 <register> 10845 <name>CR1</name> 10846 <displayName>CR1</displayName> 10847 <description>control register 1</description> 10848 <addressOffset>0x4</addressOffset> 10849 <size>0x20</size> 10850 <access>read-write</access> 10851 <resetValue>0x00000000</resetValue> 10852 <fields> 10853 <field> 10854 <name>OVRIE</name> 10855 <description>Overrun interrupt enable</description> 10856 <bitOffset>26</bitOffset> 10857 <bitWidth>1</bitWidth> 10858 <enumeratedValues><name>OVRIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Overrun interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Overrun interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 10859 </field> 10860 <field> 10861 <name>RES</name> 10862 <description>Resolution</description> 10863 <bitOffset>24</bitOffset> 10864 <bitWidth>2</bitWidth> 10865 <enumeratedValues><name>RES</name><usage>read-write</usage><enumeratedValue><name>TwelveBit</name><description>12-bit (15 ADCCLK cycles)</description><value>0</value></enumeratedValue><enumeratedValue><name>TenBit</name><description>10-bit (13 ADCCLK cycles)</description><value>1</value></enumeratedValue><enumeratedValue><name>EightBit</name><description>8-bit (11 ADCCLK cycles)</description><value>2</value></enumeratedValue><enumeratedValue><name>SixBit</name><description>6-bit (9 ADCCLK cycles)</description><value>3</value></enumeratedValue></enumeratedValues> 10866 </field> 10867 <field> 10868 <name>AWDEN</name> 10869 <description>Analog watchdog enable on regular 10870 channels</description> 10871 <bitOffset>23</bitOffset> 10872 <bitWidth>1</bitWidth> 10873 <enumeratedValues><name>AWDEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Analog watchdog disabled on regular channels</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Analog watchdog enabled on regular channels</description><value>1</value></enumeratedValue></enumeratedValues> 10874 </field> 10875 <field> 10876 <name>JAWDEN</name> 10877 <description>Analog watchdog enable on injected 10878 channels</description> 10879 <bitOffset>22</bitOffset> 10880 <bitWidth>1</bitWidth> 10881 <enumeratedValues><name>JAWDEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Analog watchdog disabled on injected channels</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Analog watchdog enabled on injected channels</description><value>1</value></enumeratedValue></enumeratedValues> 10882 </field> 10883 <field> 10884 <name>DISCNUM</name> 10885 <description>Discontinuous mode channel 10886 count</description> 10887 <bitOffset>13</bitOffset> 10888 <bitWidth>3</bitWidth> 10889 <writeConstraint><range><minimum>0</minimum><maximum>7</maximum></range></writeConstraint> 10890 </field> 10891 <field> 10892 <name>JDISCEN</name> 10893 <description>Discontinuous mode on injected 10894 channels</description> 10895 <bitOffset>12</bitOffset> 10896 <bitWidth>1</bitWidth> 10897 <enumeratedValues><name>JDISCEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Discontinuous mode on injected channels disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Discontinuous mode on injected channels enabled</description><value>1</value></enumeratedValue></enumeratedValues> 10898 </field> 10899 <field> 10900 <name>DISCEN</name> 10901 <description>Discontinuous mode on regular 10902 channels</description> 10903 <bitOffset>11</bitOffset> 10904 <bitWidth>1</bitWidth> 10905 <enumeratedValues><name>DISCEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Discontinuous mode on regular channels disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Discontinuous mode on regular channels enabled</description><value>1</value></enumeratedValue></enumeratedValues> 10906 </field> 10907 <field> 10908 <name>JAUTO</name> 10909 <description>Automatic injected group 10910 conversion</description> 10911 <bitOffset>10</bitOffset> 10912 <bitWidth>1</bitWidth> 10913 <enumeratedValues><name>JAUTO</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Automatic injected group conversion disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Automatic injected group conversion enabled</description><value>1</value></enumeratedValue></enumeratedValues> 10914 </field> 10915 <field> 10916 <name>AWDSGL</name> 10917 <description>Enable the watchdog on a single channel 10918 in scan mode</description> 10919 <bitOffset>9</bitOffset> 10920 <bitWidth>1</bitWidth> 10921 <enumeratedValues><name>AWDSGL</name><usage>read-write</usage><enumeratedValue><name>AllChannels</name><description>Analog watchdog enabled on all channels</description><value>0</value></enumeratedValue><enumeratedValue><name>SingleChannel</name><description>Analog watchdog enabled on a single channel</description><value>1</value></enumeratedValue></enumeratedValues> 10922 </field> 10923 <field> 10924 <name>SCAN</name> 10925 <description>Scan mode</description> 10926 <bitOffset>8</bitOffset> 10927 <bitWidth>1</bitWidth> 10928 <enumeratedValues><name>SCAN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Scan mode disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Scan mode enabled</description><value>1</value></enumeratedValue></enumeratedValues> 10929 </field> 10930 <field> 10931 <name>JEOCIE</name> 10932 <description>Interrupt enable for injected 10933 channels</description> 10934 <bitOffset>7</bitOffset> 10935 <bitWidth>1</bitWidth> 10936 <enumeratedValues><name>JEOCIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>JEOC interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>JEOC interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 10937 </field> 10938 <field> 10939 <name>AWDIE</name> 10940 <description>Analog watchdog interrupt 10941 enable</description> 10942 <bitOffset>6</bitOffset> 10943 <bitWidth>1</bitWidth> 10944 <enumeratedValues><name>AWDIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Analogue watchdog interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Analogue watchdog interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 10945 </field> 10946 <field> 10947 <name>EOCIE</name> 10948 <description>Interrupt enable for EOC</description> 10949 <bitOffset>5</bitOffset> 10950 <bitWidth>1</bitWidth> 10951 <enumeratedValues><name>EOCIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>EOC interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>EOC interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 10952 </field> 10953 <field> 10954 <name>AWDCH</name> 10955 <description>Analog watchdog channel select 10956 bits</description> 10957 <bitOffset>0</bitOffset> 10958 <bitWidth>5</bitWidth> 10959 <writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint> 10960 </field> 10961 </fields> 10962 </register> 10963 <register> 10964 <name>CR2</name> 10965 <displayName>CR2</displayName> 10966 <description>control register 2</description> 10967 <addressOffset>0x8</addressOffset> 10968 <size>0x20</size> 10969 <access>read-write</access> 10970 <resetValue>0x00000000</resetValue> 10971 <fields> 10972 <field> 10973 <name>SWSTART</name> 10974 <description>Start conversion of regular 10975 channels</description> 10976 <bitOffset>30</bitOffset> 10977 <bitWidth>1</bitWidth> 10978 <enumeratedValues><name>SWSTARTW</name><usage>write</usage><enumeratedValue><name>Start</name><description>Starts conversion of regular channels</description><value>1</value></enumeratedValue></enumeratedValues> 10979 </field> 10980 <field> 10981 <name>EXTEN</name> 10982 <description>External trigger enable for regular 10983 channels</description> 10984 <bitOffset>28</bitOffset> 10985 <bitWidth>2</bitWidth> 10986 <enumeratedValues><name>EXTEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Trigger detection disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>RisingEdge</name><description>Trigger detection on the rising edge</description><value>1</value></enumeratedValue><enumeratedValue><name>FallingEdge</name><description>Trigger detection on the falling edge</description><value>2</value></enumeratedValue><enumeratedValue><name>BothEdges</name><description>Trigger detection on both the rising and falling edges</description><value>3</value></enumeratedValue></enumeratedValues> 10987 </field> 10988 <field> 10989 <name>EXTSEL</name> 10990 <description>External event select for regular 10991 group</description> 10992 <bitOffset>24</bitOffset> 10993 <bitWidth>4</bitWidth> 10994 <enumeratedValues><name>EXTSEL</name><usage>read-write</usage><enumeratedValue><name>TIM1CC1</name><description>Timer 1 CC1 event</description><value>0</value></enumeratedValue><enumeratedValue><name>TIM1CC2</name><description>Timer 1 CC2 event</description><value>1</value></enumeratedValue><enumeratedValue><name>TIM1CC3</name><description>Timer 1 CC3 event</description><value>2</value></enumeratedValue><enumeratedValue><name>TIM2CC2</name><description>Timer 2 CC2 event</description><value>3</value></enumeratedValue><enumeratedValue><name>TIM2CC3</name><description>Timer 2 CC3 event</description><value>4</value></enumeratedValue><enumeratedValue><name>TIM2CC4</name><description>Timer 2 CC4 event</description><value>5</value></enumeratedValue><enumeratedValue><name>TIM2TRGO</name><description>Timer 2 TRGO event</description><value>6</value></enumeratedValue></enumeratedValues> 10995 </field> 10996 <field> 10997 <name>JSWSTART</name> 10998 <description>Start conversion of injected 10999 channels</description> 11000 <bitOffset>22</bitOffset> 11001 <bitWidth>1</bitWidth> 11002 <enumeratedValues><name>JSWSTARTW</name><usage>write</usage><enumeratedValue><name>Start</name><description>Starts conversion of injected channels</description><value>1</value></enumeratedValue></enumeratedValues> 11003 </field> 11004 <field> 11005 <name>JEXTEN</name> 11006 <description>External trigger enable for injected 11007 channels</description> 11008 <bitOffset>20</bitOffset> 11009 <bitWidth>2</bitWidth> 11010 <enumeratedValues><name>JEXTEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Trigger detection disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>RisingEdge</name><description>Trigger detection on the rising edge</description><value>1</value></enumeratedValue><enumeratedValue><name>FallingEdge</name><description>Trigger detection on the falling edge</description><value>2</value></enumeratedValue><enumeratedValue><name>BothEdges</name><description>Trigger detection on both the rising and falling edges</description><value>3</value></enumeratedValue></enumeratedValues> 11011 </field> 11012 <field> 11013 <name>JEXTSEL</name> 11014 <description>External event select for injected 11015 group</description> 11016 <bitOffset>16</bitOffset> 11017 <bitWidth>4</bitWidth> 11018 <enumeratedValues><name>JEXTSEL</name><usage>read-write</usage><enumeratedValue><name>TIM1TRGO</name><description>Timer 1 TRGO event</description><value>0</value></enumeratedValue><enumeratedValue><name>TIM1CC4</name><description>Timer 1 CC4 event</description><value>1</value></enumeratedValue><enumeratedValue><name>TIM2TRGO</name><description>Timer 2 TRGO event</description><value>2</value></enumeratedValue><enumeratedValue><name>TIM2CC1</name><description>Timer 2 CC1 event</description><value>3</value></enumeratedValue><enumeratedValue><name>TIM3CC4</name><description>Timer 3 CC4 event</description><value>4</value></enumeratedValue><enumeratedValue><name>TIM4TRGO</name><description>Timer 4 TRGO event</description><value>5</value></enumeratedValue><enumeratedValue><name>TIM8CC4</name><description>Timer 8 CC4 event</description><value>7</value></enumeratedValue><enumeratedValue><name>TIM1TRGO2</name><description>Timer 1 TRGO(2) event</description><value>8</value></enumeratedValue><enumeratedValue><name>TIM8TRGO</name><description>Timer 8 TRGO event</description><value>9</value></enumeratedValue><enumeratedValue><name>TIM8TRGO2</name><description>Timer 8 TRGO(2) event</description><value>10</value></enumeratedValue><enumeratedValue><name>TIM3CC3</name><description>Timer 3 CC3 event</description><value>11</value></enumeratedValue><enumeratedValue><name>TIM5TRGO</name><description>Timer 5 TRGO event</description><value>12</value></enumeratedValue><enumeratedValue><name>TIM3CC1</name><description>Timer 3 CC1 event</description><value>13</value></enumeratedValue><enumeratedValue><name>TIM6TRGO</name><description>Timer 6 TRGO event</description><value>14</value></enumeratedValue></enumeratedValues> 11019 </field> 11020 <field> 11021 <name>ALIGN</name> 11022 <description>Data alignment</description> 11023 <bitOffset>11</bitOffset> 11024 <bitWidth>1</bitWidth> 11025 <enumeratedValues><name>ALIGN</name><usage>read-write</usage><enumeratedValue><name>Right</name><description>Right alignment</description><value>0</value></enumeratedValue><enumeratedValue><name>Left</name><description>Left alignment</description><value>1</value></enumeratedValue></enumeratedValues> 11026 </field> 11027 <field> 11028 <name>EOCS</name> 11029 <description>End of conversion 11030 selection</description> 11031 <bitOffset>10</bitOffset> 11032 <bitWidth>1</bitWidth> 11033 <enumeratedValues><name>EOCS</name><usage>read-write</usage><enumeratedValue><name>EachSequence</name><description>The EOC bit is set at the end of each sequence of regular conversions</description><value>0</value></enumeratedValue><enumeratedValue><name>EachConversion</name><description>The EOC bit is set at the end of each regular conversion</description><value>1</value></enumeratedValue></enumeratedValues> 11034 </field> 11035 <field> 11036 <name>DDS</name> 11037 <description>DMA disable selection (for single ADC 11038 mode)</description> 11039 <bitOffset>9</bitOffset> 11040 <bitWidth>1</bitWidth> 11041 <enumeratedValues><name>DDS</name><usage>read-write</usage><enumeratedValue><name>Single</name><description>No new DMA request is issued after the last transfer</description><value>0</value></enumeratedValue><enumeratedValue><name>Continuous</name><description>DMA requests are issued as long as data are converted and DMA=1</description><value>1</value></enumeratedValue></enumeratedValues> 11042 </field> 11043 <field> 11044 <name>DMA</name> 11045 <description>Direct memory access mode (for single 11046 ADC mode)</description> 11047 <bitOffset>8</bitOffset> 11048 <bitWidth>1</bitWidth> 11049 <enumeratedValues><name>DMA</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>DMA mode disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>DMA mode enabled</description><value>1</value></enumeratedValue></enumeratedValues> 11050 </field> 11051 <field> 11052 <name>CONT</name> 11053 <description>Continuous conversion</description> 11054 <bitOffset>1</bitOffset> 11055 <bitWidth>1</bitWidth> 11056 <enumeratedValues><name>CONT</name><usage>read-write</usage><enumeratedValue><name>Single</name><description>Single conversion mode</description><value>0</value></enumeratedValue><enumeratedValue><name>Continuous</name><description>Continuous conversion mode</description><value>1</value></enumeratedValue></enumeratedValues> 11057 </field> 11058 <field> 11059 <name>ADON</name> 11060 <description>A/D Converter ON / OFF</description> 11061 <bitOffset>0</bitOffset> 11062 <bitWidth>1</bitWidth> 11063 <enumeratedValues><name>ADON</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Disable ADC conversion and go to power down mode</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Enable ADC</description><value>1</value></enumeratedValue></enumeratedValues> 11064 </field> 11065 </fields> 11066 </register> 11067 <register> 11068 <name>SMPR1</name> 11069 <displayName>SMPR1</displayName> 11070 <description>sample time register 1</description> 11071 <addressOffset>0xC</addressOffset> 11072 <size>0x20</size> 11073 <access>read-write</access> 11074 <resetValue>0x00000000</resetValue> 11075 <fields> 11076 <field> 11077 <name>SMP18</name> 11078 <description>Channel 18 sampling time selection</description> 11079 <bitOffset>24</bitOffset> 11080 <bitWidth>3</bitWidth> 11081 <enumeratedValues derivedFrom="SMP10"/> 11082 </field> 11083 <field><name>SMP17</name><description>Channel 17 sampling time selection</description><bitOffset>21</bitOffset><bitWidth>3</bitWidth><enumeratedValues derivedFrom="SMP10"/> 11084 </field> 11085 <field><name>SMP16</name><description>Channel 16 sampling time selection</description><bitOffset>18</bitOffset><bitWidth>3</bitWidth><enumeratedValues derivedFrom="SMP10"/> 11086 </field> 11087 <field><name>SMP15</name><description>Channel 15 sampling time selection</description><bitOffset>15</bitOffset><bitWidth>3</bitWidth><enumeratedValues derivedFrom="SMP10"/> 11088 </field> 11089 <field><name>SMP14</name><description>Channel 14 sampling time selection</description><bitOffset>12</bitOffset><bitWidth>3</bitWidth><enumeratedValues derivedFrom="SMP10"/> 11090 </field> 11091 <field><name>SMP13</name><description>Channel 13 sampling time selection</description><bitOffset>9</bitOffset><bitWidth>3</bitWidth><enumeratedValues derivedFrom="SMP10"/> 11092 </field> 11093 <field><name>SMP12</name><description>Channel 12 sampling time selection</description><bitOffset>6</bitOffset><bitWidth>3</bitWidth><enumeratedValues derivedFrom="SMP10"/> 11094 </field> 11095 <field><name>SMP11</name><description>Channel 11 sampling time selection</description><bitOffset>3</bitOffset><bitWidth>3</bitWidth><enumeratedValues derivedFrom="SMP10"/> 11096 </field> 11097 <field><name>SMP10</name><description>Channel 10 sampling time selection</description><bitOffset>0</bitOffset><bitWidth>3</bitWidth><enumeratedValues><name>SMP10</name><usage>read-write</usage><enumeratedValue><name>Cycles3</name><description>3 cycles</description><value>0</value></enumeratedValue><enumeratedValue><name>Cycles15</name><description>15 cycles</description><value>1</value></enumeratedValue><enumeratedValue><name>Cycles28</name><description>28 cycles</description><value>2</value></enumeratedValue><enumeratedValue><name>Cycles56</name><description>56 cycles</description><value>3</value></enumeratedValue><enumeratedValue><name>Cycles84</name><description>84 cycles</description><value>4</value></enumeratedValue><enumeratedValue><name>Cycles112</name><description>112 cycles</description><value>5</value></enumeratedValue><enumeratedValue><name>Cycles144</name><description>144 cycles</description><value>6</value></enumeratedValue><enumeratedValue><name>Cycles480</name><description>480 cycles</description><value>7</value></enumeratedValue></enumeratedValues> 11098 </field> 11099 </fields> 11100 </register> 11101 <register> 11102 <name>SMPR2</name> 11103 <displayName>SMPR2</displayName> 11104 <description>sample time register 2</description> 11105 <addressOffset>0x10</addressOffset> 11106 <size>0x20</size> 11107 <access>read-write</access> 11108 <resetValue>0x00000000</resetValue> 11109 <fields> 11110 <field> 11111 <name>SMP9</name> 11112 <description>Channel 9 sampling time selection</description> 11113 <bitOffset>27</bitOffset> 11114 <bitWidth>3</bitWidth> 11115 <enumeratedValues derivedFrom="SMP0"/> 11116 </field> 11117 <field><name>SMP8</name><description>Channel 8 sampling time selection</description><bitOffset>24</bitOffset><bitWidth>3</bitWidth><enumeratedValues derivedFrom="SMP0"/> 11118 </field> 11119 <field><name>SMP7</name><description>Channel 7 sampling time selection</description><bitOffset>21</bitOffset><bitWidth>3</bitWidth><enumeratedValues derivedFrom="SMP0"/> 11120 </field> 11121 <field><name>SMP6</name><description>Channel 6 sampling time selection</description><bitOffset>18</bitOffset><bitWidth>3</bitWidth><enumeratedValues derivedFrom="SMP0"/> 11122 </field> 11123 <field><name>SMP5</name><description>Channel 5 sampling time selection</description><bitOffset>15</bitOffset><bitWidth>3</bitWidth><enumeratedValues derivedFrom="SMP0"/> 11124 </field> 11125 <field><name>SMP4</name><description>Channel 4 sampling time selection</description><bitOffset>12</bitOffset><bitWidth>3</bitWidth><enumeratedValues derivedFrom="SMP0"/> 11126 </field> 11127 <field><name>SMP3</name><description>Channel 3 sampling time selection</description><bitOffset>9</bitOffset><bitWidth>3</bitWidth><enumeratedValues derivedFrom="SMP0"/> 11128 </field> 11129 <field><name>SMP2</name><description>Channel 2 sampling time selection</description><bitOffset>6</bitOffset><bitWidth>3</bitWidth><enumeratedValues derivedFrom="SMP0"/> 11130 </field> 11131 <field><name>SMP1</name><description>Channel 1 sampling time selection</description><bitOffset>3</bitOffset><bitWidth>3</bitWidth><enumeratedValues derivedFrom="SMP0"/> 11132 </field> 11133 <field><name>SMP0</name><description>Channel 0 sampling time selection</description><bitOffset>0</bitOffset><bitWidth>3</bitWidth><enumeratedValues><name>SMP0</name><usage>read-write</usage><enumeratedValue><name>Cycles3</name><description>3 cycles</description><value>0</value></enumeratedValue><enumeratedValue><name>Cycles15</name><description>15 cycles</description><value>1</value></enumeratedValue><enumeratedValue><name>Cycles28</name><description>28 cycles</description><value>2</value></enumeratedValue><enumeratedValue><name>Cycles56</name><description>56 cycles</description><value>3</value></enumeratedValue><enumeratedValue><name>Cycles84</name><description>84 cycles</description><value>4</value></enumeratedValue><enumeratedValue><name>Cycles112</name><description>112 cycles</description><value>5</value></enumeratedValue><enumeratedValue><name>Cycles144</name><description>144 cycles</description><value>6</value></enumeratedValue><enumeratedValue><name>Cycles480</name><description>480 cycles</description><value>7</value></enumeratedValue></enumeratedValues> 11134 </field> 11135 </fields> 11136 </register> 11137 <register> 11138 <dim>4</dim><dimIncrement>0x4</dimIncrement><dimIndex>1,2,3,4</dimIndex><name>JOFR%s</name> 11139 <displayName>JOFR1</displayName> 11140 <description>injected channel data offset register 11141 x</description> 11142 <addressOffset>0x14</addressOffset> 11143 <size>0x20</size> 11144 <access>read-write</access> 11145 <resetValue>0x00000000</resetValue> 11146 <fields> 11147 <field> 11148 <name>JOFFSET</name> 11149 <description>Data offset for injected channel 11150 x</description> 11151 <bitOffset>0</bitOffset> 11152 <bitWidth>12</bitWidth> 11153 <writeConstraint><range><minimum>0</minimum><maximum>4095</maximum></range></writeConstraint> 11154 </field> 11155 </fields> 11156 </register> 11157 <register> 11158 <name>HTR</name> 11159 <displayName>HTR</displayName> 11160 <description>watchdog higher threshold 11161 register</description> 11162 <addressOffset>0x24</addressOffset> 11163 <size>0x20</size> 11164 <access>read-write</access> 11165 <resetValue>0x00000FFF</resetValue> 11166 <fields> 11167 <field> 11168 <name>HT</name> 11169 <description>Analog watchdog higher 11170 threshold</description> 11171 <bitOffset>0</bitOffset> 11172 <bitWidth>12</bitWidth> 11173 <writeConstraint><range><minimum>0</minimum><maximum>4095</maximum></range></writeConstraint> 11174 </field> 11175 </fields> 11176 </register> 11177 <register> 11178 <name>LTR</name> 11179 <displayName>LTR</displayName> 11180 <description>watchdog lower threshold 11181 register</description> 11182 <addressOffset>0x28</addressOffset> 11183 <size>0x20</size> 11184 <access>read-write</access> 11185 <resetValue>0x00000000</resetValue> 11186 <fields> 11187 <field> 11188 <name>LT</name> 11189 <description>Analog watchdog lower 11190 threshold</description> 11191 <bitOffset>0</bitOffset> 11192 <bitWidth>12</bitWidth> 11193 <writeConstraint><range><minimum>0</minimum><maximum>4095</maximum></range></writeConstraint> 11194 </field> 11195 </fields> 11196 </register> 11197 <register> 11198 <name>SQR1</name> 11199 <displayName>SQR1</displayName> 11200 <description>regular sequence register 1</description> 11201 <addressOffset>0x2C</addressOffset> 11202 <size>0x20</size> 11203 <access>read-write</access> 11204 <resetValue>0x00000000</resetValue> 11205 <fields> 11206 <field> 11207 <name>L</name> 11208 <description>Regular channel sequence 11209 length</description> 11210 <bitOffset>20</bitOffset> 11211 <bitWidth>4</bitWidth> 11212 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 11213 </field> 11214 <field> 11215 <name>SQ16</name> 11216 <description>16th conversion in regular 11217 sequence</description> 11218 <bitOffset>15</bitOffset> 11219 <bitWidth>5</bitWidth> 11220 <writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint> 11221 </field> 11222 <field> 11223 <name>SQ15</name> 11224 <description>15th conversion in regular 11225 sequence</description> 11226 <bitOffset>10</bitOffset> 11227 <bitWidth>5</bitWidth> 11228 <writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint> 11229 </field> 11230 <field> 11231 <name>SQ14</name> 11232 <description>14th conversion in regular 11233 sequence</description> 11234 <bitOffset>5</bitOffset> 11235 <bitWidth>5</bitWidth> 11236 <writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint> 11237 </field> 11238 <field> 11239 <name>SQ13</name> 11240 <description>13th conversion in regular 11241 sequence</description> 11242 <bitOffset>0</bitOffset> 11243 <bitWidth>5</bitWidth> 11244 <writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint> 11245 </field> 11246 </fields> 11247 </register> 11248 <register> 11249 <name>SQR2</name> 11250 <displayName>SQR2</displayName> 11251 <description>regular sequence register 2</description> 11252 <addressOffset>0x30</addressOffset> 11253 <size>0x20</size> 11254 <access>read-write</access> 11255 <resetValue>0x00000000</resetValue> 11256 <fields> 11257 <field> 11258 <name>SQ12</name> 11259 <description>12th conversion in regular 11260 sequence</description> 11261 <bitOffset>25</bitOffset> 11262 <bitWidth>5</bitWidth> 11263 <writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint> 11264 </field> 11265 <field> 11266 <name>SQ11</name> 11267 <description>11th conversion in regular 11268 sequence</description> 11269 <bitOffset>20</bitOffset> 11270 <bitWidth>5</bitWidth> 11271 <writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint> 11272 </field> 11273 <field> 11274 <name>SQ10</name> 11275 <description>10th conversion in regular 11276 sequence</description> 11277 <bitOffset>15</bitOffset> 11278 <bitWidth>5</bitWidth> 11279 <writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint> 11280 </field> 11281 <field> 11282 <name>SQ9</name> 11283 <description>9th conversion in regular 11284 sequence</description> 11285 <bitOffset>10</bitOffset> 11286 <bitWidth>5</bitWidth> 11287 <writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint> 11288 </field> 11289 <field> 11290 <name>SQ8</name> 11291 <description>8th conversion in regular 11292 sequence</description> 11293 <bitOffset>5</bitOffset> 11294 <bitWidth>5</bitWidth> 11295 <writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint> 11296 </field> 11297 <field> 11298 <name>SQ7</name> 11299 <description>7th conversion in regular 11300 sequence</description> 11301 <bitOffset>0</bitOffset> 11302 <bitWidth>5</bitWidth> 11303 <writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint> 11304 </field> 11305 </fields> 11306 </register> 11307 <register> 11308 <name>SQR3</name> 11309 <displayName>SQR3</displayName> 11310 <description>regular sequence register 3</description> 11311 <addressOffset>0x34</addressOffset> 11312 <size>0x20</size> 11313 <access>read-write</access> 11314 <resetValue>0x00000000</resetValue> 11315 <fields> 11316 <field> 11317 <name>SQ6</name> 11318 <description>6th conversion in regular 11319 sequence</description> 11320 <bitOffset>25</bitOffset> 11321 <bitWidth>5</bitWidth> 11322 <writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint> 11323 </field> 11324 <field> 11325 <name>SQ5</name> 11326 <description>5th conversion in regular 11327 sequence</description> 11328 <bitOffset>20</bitOffset> 11329 <bitWidth>5</bitWidth> 11330 <writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint> 11331 </field> 11332 <field> 11333 <name>SQ4</name> 11334 <description>4th conversion in regular 11335 sequence</description> 11336 <bitOffset>15</bitOffset> 11337 <bitWidth>5</bitWidth> 11338 <writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint> 11339 </field> 11340 <field> 11341 <name>SQ3</name> 11342 <description>3rd conversion in regular 11343 sequence</description> 11344 <bitOffset>10</bitOffset> 11345 <bitWidth>5</bitWidth> 11346 <writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint> 11347 </field> 11348 <field> 11349 <name>SQ2</name> 11350 <description>2nd conversion in regular 11351 sequence</description> 11352 <bitOffset>5</bitOffset> 11353 <bitWidth>5</bitWidth> 11354 <writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint> 11355 </field> 11356 <field> 11357 <name>SQ1</name> 11358 <description>1st conversion in regular 11359 sequence</description> 11360 <bitOffset>0</bitOffset> 11361 <bitWidth>5</bitWidth> 11362 <writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint> 11363 </field> 11364 </fields> 11365 </register> 11366 <register> 11367 <name>JSQR</name> 11368 <displayName>JSQR</displayName> 11369 <description>injected sequence register</description> 11370 <addressOffset>0x38</addressOffset> 11371 <size>0x20</size> 11372 <access>read-write</access> 11373 <resetValue>0x00000000</resetValue> 11374 <fields> 11375 <field> 11376 <name>JL</name> 11377 <description>Injected sequence length</description> 11378 <bitOffset>20</bitOffset> 11379 <bitWidth>2</bitWidth> 11380 <writeConstraint><range><minimum>0</minimum><maximum>3</maximum></range></writeConstraint> 11381 </field> 11382 <field> 11383 <name>JSQ4</name> 11384 <description>4th conversion in injected 11385 sequence</description> 11386 <bitOffset>15</bitOffset> 11387 <bitWidth>5</bitWidth> 11388 <writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint> 11389 </field> 11390 <field> 11391 <name>JSQ3</name> 11392 <description>3rd conversion in injected 11393 sequence</description> 11394 <bitOffset>10</bitOffset> 11395 <bitWidth>5</bitWidth> 11396 <writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint> 11397 </field> 11398 <field> 11399 <name>JSQ2</name> 11400 <description>2nd conversion in injected 11401 sequence</description> 11402 <bitOffset>5</bitOffset> 11403 <bitWidth>5</bitWidth> 11404 <writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint> 11405 </field> 11406 <field> 11407 <name>JSQ1</name> 11408 <description>1st conversion in injected 11409 sequence</description> 11410 <bitOffset>0</bitOffset> 11411 <bitWidth>5</bitWidth> 11412 <writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint> 11413 </field> 11414 </fields> 11415 </register> 11416 <register> 11417 <dim>4</dim><dimIncrement>0x4</dimIncrement><dimIndex>1,2,3,4</dimIndex><name>JDR%s</name> 11418 <displayName>JDR1</displayName> 11419 <description>injected data register x</description> 11420 <addressOffset>0x3C</addressOffset> 11421 <size>0x20</size> 11422 <access>read-only</access> 11423 <resetValue>0x00000000</resetValue> 11424 <fields> 11425 <field> 11426 <name>JDATA</name> 11427 <description>Injected data</description> 11428 <bitOffset>0</bitOffset> 11429 <bitWidth>16</bitWidth> 11430 </field> 11431 </fields> 11432 </register> 11433 <register> 11434 <name>DR</name> 11435 <displayName>DR</displayName> 11436 <description>regular data register</description> 11437 <addressOffset>0x4C</addressOffset> 11438 <size>0x20</size> 11439 <access>read-only</access> 11440 <resetValue>0x00000000</resetValue> 11441 <fields> 11442 <field> 11443 <name>DATA</name> 11444 <description>Regular data</description> 11445 <bitOffset>0</bitOffset> 11446 <bitWidth>16</bitWidth> 11447 </field> 11448 </fields> 11449 </register> 11450 </registers> 11451 </peripheral> 11452 <peripheral derivedFrom="ADC1"> 11453 <name>ADC2</name> 11454 <baseAddress>0x40012100</baseAddress> 11455 <interrupt> 11456 <name>ADC</name> 11457 <description>ADC2 global interrupts</description> 11458 <value>18</value> 11459 </interrupt> 11460 </peripheral> 11461 <peripheral derivedFrom="ADC1"> 11462 <name>ADC3</name> 11463 <baseAddress>0x40012200</baseAddress> 11464 <interrupt> 11465 <name>ADC</name> 11466 <description>ADC3 global interrupts</description> 11467 <value>18</value> 11468 </interrupt> 11469 </peripheral> 11470 <peripheral derivedFrom="USART1"> 11471 <name>USART6</name> 11472 <baseAddress>0x40011400</baseAddress> 11473 <interrupt> 11474 <name>USART6</name> 11475 <description>USART6 global interrupt</description> 11476 <value>71</value> 11477 </interrupt> 11478 </peripheral> 11479 <peripheral> 11480 <name>USART1</name> 11481 <description>Universal synchronous asynchronous receiver 11482 transmitter</description> 11483 <groupName>USART</groupName> 11484 <baseAddress>0x40011000</baseAddress> 11485 <addressBlock> 11486 <offset>0x0</offset> 11487 <size>0x400</size> 11488 <usage>registers</usage> 11489 </addressBlock> 11490 <interrupt> 11491 <name>USART1</name> 11492 <description>USART1 global interrupt</description> 11493 <value>37</value> 11494 </interrupt> 11495 <registers> 11496 <register> 11497 <name>SR</name> 11498 <displayName>SR</displayName> 11499 <description>Status register</description> 11500 <addressOffset>0x0</addressOffset> 11501 <size>0x20</size> 11502 <resetValue>0x00C00000</resetValue> 11503 <fields> 11504 <field> 11505 <name>CTS</name> 11506 <description>CTS flag</description> 11507 <bitOffset>9</bitOffset> 11508 <bitWidth>1</bitWidth> 11509 <access>read-write</access> 11510 </field> 11511 <field> 11512 <name>LBD</name> 11513 <description>LIN break detection flag</description> 11514 <bitOffset>8</bitOffset> 11515 <bitWidth>1</bitWidth> 11516 <access>read-write</access> 11517 </field> 11518 <field> 11519 <name>TXE</name> 11520 <description>Transmit data register 11521 empty</description> 11522 <bitOffset>7</bitOffset> 11523 <bitWidth>1</bitWidth> 11524 <access>read-only</access> 11525 </field> 11526 <field> 11527 <name>TC</name> 11528 <description>Transmission complete</description> 11529 <bitOffset>6</bitOffset> 11530 <bitWidth>1</bitWidth> 11531 <access>read-write</access> 11532 </field> 11533 <field> 11534 <name>RXNE</name> 11535 <description>Read data register not 11536 empty</description> 11537 <bitOffset>5</bitOffset> 11538 <bitWidth>1</bitWidth> 11539 <access>read-write</access> 11540 </field> 11541 <field> 11542 <name>IDLE</name> 11543 <description>IDLE line detected</description> 11544 <bitOffset>4</bitOffset> 11545 <bitWidth>1</bitWidth> 11546 <access>read-only</access> 11547 </field> 11548 <field> 11549 <name>ORE</name> 11550 <description>Overrun error</description> 11551 <bitOffset>3</bitOffset> 11552 <bitWidth>1</bitWidth> 11553 <access>read-only</access> 11554 </field> 11555 <field> 11556 <name>NF</name> 11557 <description>Noise detected flag</description> 11558 <bitOffset>2</bitOffset> 11559 <bitWidth>1</bitWidth> 11560 <access>read-only</access> 11561 </field> 11562 <field> 11563 <name>FE</name> 11564 <description>Framing error</description> 11565 <bitOffset>1</bitOffset> 11566 <bitWidth>1</bitWidth> 11567 <access>read-only</access> 11568 </field> 11569 <field> 11570 <name>PE</name> 11571 <description>Parity error</description> 11572 <bitOffset>0</bitOffset> 11573 <bitWidth>1</bitWidth> 11574 <access>read-only</access> 11575 </field> 11576 </fields> 11577 </register> 11578 <register> 11579 <name>DR</name> 11580 <displayName>DR</displayName> 11581 <description>Data register</description> 11582 <addressOffset>0x4</addressOffset> 11583 <size>0x20</size> 11584 <access>read-write</access> 11585 <resetValue>0x00000000</resetValue> 11586 <fields> 11587 <field> 11588 <name>DR</name> 11589 <description>Data value</description> 11590 <bitOffset>0</bitOffset> 11591 <bitWidth>9</bitWidth> 11592 <writeConstraint><range><minimum>0</minimum><maximum>511</maximum></range></writeConstraint> 11593 </field> 11594 </fields> 11595 </register> 11596 <register> 11597 <name>BRR</name> 11598 <displayName>BRR</displayName> 11599 <description>Baud rate register</description> 11600 <addressOffset>0x8</addressOffset> 11601 <size>0x20</size> 11602 <access>read-write</access> 11603 <resetValue>0x0000</resetValue> 11604 <fields> 11605 <field> 11606 <name>DIV_Mantissa</name> 11607 <description>mantissa of USARTDIV</description> 11608 <bitOffset>4</bitOffset> 11609 <bitWidth>12</bitWidth> 11610 <writeConstraint><range><minimum>0</minimum><maximum>4095</maximum></range></writeConstraint> 11611 </field> 11612 <field> 11613 <name>DIV_Fraction</name> 11614 <description>fraction of USARTDIV</description> 11615 <bitOffset>0</bitOffset> 11616 <bitWidth>4</bitWidth> 11617 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 11618 </field> 11619 </fields> 11620 </register> 11621 <register> 11622 <name>CR1</name> 11623 <displayName>CR1</displayName> 11624 <description>Control register 1</description> 11625 <addressOffset>0xC</addressOffset> 11626 <size>0x20</size> 11627 <access>read-write</access> 11628 <resetValue>0x0000</resetValue> 11629 <fields> 11630 <field> 11631 <name>OVER8</name> 11632 <description>Oversampling mode</description> 11633 <bitOffset>15</bitOffset> 11634 <bitWidth>1</bitWidth> 11635 <enumeratedValues><name>OVER8</name><usage>read-write</usage><enumeratedValue><name>Oversample16</name><description>Oversampling by 16</description><value>0</value></enumeratedValue><enumeratedValue><name>Oversample8</name><description>Oversampling by 8</description><value>1</value></enumeratedValue></enumeratedValues> 11636 </field> 11637 <field> 11638 <name>UE</name> 11639 <description>USART enable</description> 11640 <bitOffset>13</bitOffset> 11641 <bitWidth>1</bitWidth> 11642 <enumeratedValues><name>UE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>USART prescaler and outputs disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>USART enabled</description><value>1</value></enumeratedValue></enumeratedValues> 11643 </field> 11644 <field> 11645 <name>M</name> 11646 <description>Word length</description> 11647 <bitOffset>12</bitOffset> 11648 <bitWidth>1</bitWidth> 11649 <enumeratedValues><name>M</name><usage>read-write</usage><enumeratedValue><name>M8</name><description>8 data bits</description><value>0</value></enumeratedValue><enumeratedValue><name>M9</name><description>9 data bits</description><value>1</value></enumeratedValue></enumeratedValues> 11650 </field> 11651 <field> 11652 <name>WAKE</name> 11653 <description>Wakeup method</description> 11654 <bitOffset>11</bitOffset> 11655 <bitWidth>1</bitWidth> 11656 <enumeratedValues><name>WAKE</name><usage>read-write</usage><enumeratedValue><name>IdleLine</name><description>USART wakeup on idle line</description><value>0</value></enumeratedValue><enumeratedValue><name>AddressMark</name><description>USART wakeup on address mark</description><value>1</value></enumeratedValue></enumeratedValues> 11657 </field> 11658 <field> 11659 <name>PCE</name> 11660 <description>Parity control enable</description> 11661 <bitOffset>10</bitOffset> 11662 <bitWidth>1</bitWidth> 11663 <enumeratedValues><name>PCE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Parity control disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Parity control enabled</description><value>1</value></enumeratedValue></enumeratedValues> 11664 </field> 11665 <field> 11666 <name>PS</name> 11667 <description>Parity selection</description> 11668 <bitOffset>9</bitOffset> 11669 <bitWidth>1</bitWidth> 11670 <enumeratedValues><name>PS</name><usage>read-write</usage><enumeratedValue><name>Even</name><description>Even parity</description><value>0</value></enumeratedValue><enumeratedValue><name>Odd</name><description>Odd parity</description><value>1</value></enumeratedValue></enumeratedValues> 11671 </field> 11672 <field> 11673 <name>PEIE</name> 11674 <description>PE interrupt enable</description> 11675 <bitOffset>8</bitOffset> 11676 <bitWidth>1</bitWidth> 11677 <enumeratedValues><name>PEIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>PE interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>PE interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 11678 </field> 11679 <field> 11680 <name>TXEIE</name> 11681 <description>TXE interrupt enable</description> 11682 <bitOffset>7</bitOffset> 11683 <bitWidth>1</bitWidth> 11684 <enumeratedValues><name>TXEIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>TXE interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>TXE interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 11685 </field> 11686 <field> 11687 <name>TCIE</name> 11688 <description>Transmission complete interrupt 11689 enable</description> 11690 <bitOffset>6</bitOffset> 11691 <bitWidth>1</bitWidth> 11692 <enumeratedValues><name>TCIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>TC interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>TC interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 11693 </field> 11694 <field> 11695 <name>RXNEIE</name> 11696 <description>RXNE interrupt enable</description> 11697 <bitOffset>5</bitOffset> 11698 <bitWidth>1</bitWidth> 11699 <enumeratedValues><name>RXNEIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>RXNE interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>RXNE interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 11700 </field> 11701 <field> 11702 <name>IDLEIE</name> 11703 <description>IDLE interrupt enable</description> 11704 <bitOffset>4</bitOffset> 11705 <bitWidth>1</bitWidth> 11706 <enumeratedValues><name>IDLEIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>IDLE interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>IDLE interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 11707 </field> 11708 <field> 11709 <name>TE</name> 11710 <description>Transmitter enable</description> 11711 <bitOffset>3</bitOffset> 11712 <bitWidth>1</bitWidth> 11713 <enumeratedValues><name>TE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Transmitter disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Transmitter enabled</description><value>1</value></enumeratedValue></enumeratedValues> 11714 </field> 11715 <field> 11716 <name>RE</name> 11717 <description>Receiver enable</description> 11718 <bitOffset>2</bitOffset> 11719 <bitWidth>1</bitWidth> 11720 <enumeratedValues><name>RE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Receiver disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Receiver enabled</description><value>1</value></enumeratedValue></enumeratedValues> 11721 </field> 11722 <field> 11723 <name>RWU</name> 11724 <description>Receiver wakeup</description> 11725 <bitOffset>1</bitOffset> 11726 <bitWidth>1</bitWidth> 11727 <enumeratedValues><name>RWU</name><usage>read-write</usage><enumeratedValue><name>Active</name><description>Receiver in active mode</description><value>0</value></enumeratedValue><enumeratedValue><name>Mute</name><description>Receiver in mute mode</description><value>1</value></enumeratedValue></enumeratedValues> 11728 </field> 11729 <field> 11730 <name>SBK</name> 11731 <description>Send break</description> 11732 <bitOffset>0</bitOffset> 11733 <bitWidth>1</bitWidth> 11734 <enumeratedValues><name>SBK</name><usage>read-write</usage><enumeratedValue><name>NoBreak</name><description>No break character is transmitted</description><value>0</value></enumeratedValue><enumeratedValue><name>Break</name><description>Break character transmitted</description><value>1</value></enumeratedValue></enumeratedValues> 11735 </field> 11736 </fields> 11737 </register> 11738 <register> 11739 <name>CR2</name> 11740 <displayName>CR2</displayName> 11741 <description>Control register 2</description> 11742 <addressOffset>0x10</addressOffset> 11743 <size>0x20</size> 11744 <access>read-write</access> 11745 <resetValue>0x0000</resetValue> 11746 <fields> 11747 <field> 11748 <name>LINEN</name> 11749 <description>LIN mode enable</description> 11750 <bitOffset>14</bitOffset> 11751 <bitWidth>1</bitWidth> 11752 <enumeratedValues><name>LINEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>LIN mode disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>LIN mode enabled</description><value>1</value></enumeratedValue></enumeratedValues> 11753 </field> 11754 <field> 11755 <name>STOP</name> 11756 <description>STOP bits</description> 11757 <bitOffset>12</bitOffset> 11758 <bitWidth>2</bitWidth> 11759 <enumeratedValues><name>STOP</name><usage>read-write</usage><enumeratedValue><name>Stop1</name><description>1 stop bit</description><value>0</value></enumeratedValue><enumeratedValue><name>Stop0p5</name><description>0.5 stop bits</description><value>1</value></enumeratedValue><enumeratedValue><name>Stop2</name><description>2 stop bits</description><value>2</value></enumeratedValue><enumeratedValue><name>Stop1p5</name><description>1.5 stop bits</description><value>3</value></enumeratedValue></enumeratedValues> 11760 </field> 11761 <field> 11762 <name>CLKEN</name> 11763 <description>Clock enable</description> 11764 <bitOffset>11</bitOffset> 11765 <bitWidth>1</bitWidth> 11766 <enumeratedValues><name>CLKEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>CK pin disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>CK pin enabled</description><value>1</value></enumeratedValue></enumeratedValues> 11767 </field> 11768 <field> 11769 <name>CPOL</name> 11770 <description>Clock polarity</description> 11771 <bitOffset>10</bitOffset> 11772 <bitWidth>1</bitWidth> 11773 <enumeratedValues><name>CPOL</name><usage>read-write</usage><enumeratedValue><name>Low</name><description>Steady low value on CK pin outside transmission window</description><value>0</value></enumeratedValue><enumeratedValue><name>High</name><description>Steady high value on CK pin outside transmission window</description><value>1</value></enumeratedValue></enumeratedValues> 11774 </field> 11775 <field> 11776 <name>CPHA</name> 11777 <description>Clock phase</description> 11778 <bitOffset>9</bitOffset> 11779 <bitWidth>1</bitWidth> 11780 <enumeratedValues><name>CPHA</name><usage>read-write</usage><enumeratedValue><name>First</name><description>The first clock transition is the first data capture edge</description><value>0</value></enumeratedValue><enumeratedValue><name>Second</name><description>The second clock transition is the first data capture edge</description><value>1</value></enumeratedValue></enumeratedValues> 11781 </field> 11782 <field> 11783 <name>LBCL</name> 11784 <description>Last bit clock pulse</description> 11785 <bitOffset>8</bitOffset> 11786 <bitWidth>1</bitWidth> 11787 </field> 11788 <field> 11789 <name>LBDIE</name> 11790 <description>LIN break detection interrupt 11791 enable</description> 11792 <bitOffset>6</bitOffset> 11793 <bitWidth>1</bitWidth> 11794 <enumeratedValues><name>LBDIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>LIN break detection interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>LIN break detection interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 11795 </field> 11796 <field> 11797 <name>LBDL</name> 11798 <description>lin break detection length</description> 11799 <bitOffset>5</bitOffset> 11800 <bitWidth>1</bitWidth> 11801 <enumeratedValues><name>LBDL</name><usage>read-write</usage><enumeratedValue><name>LBDL10</name><description>10-bit break detection</description><value>0</value></enumeratedValue><enumeratedValue><name>LBDL11</name><description>11-bit break detection</description><value>1</value></enumeratedValue></enumeratedValues> 11802 </field> 11803 <field> 11804 <name>ADD</name> 11805 <description>Address of the USART node</description> 11806 <bitOffset>0</bitOffset> 11807 <bitWidth>4</bitWidth> 11808 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 11809 </field> 11810 </fields> 11811 </register> 11812 <register> 11813 <name>CR3</name> 11814 <displayName>CR3</displayName> 11815 <description>Control register 3</description> 11816 <addressOffset>0x14</addressOffset> 11817 <size>0x20</size> 11818 <access>read-write</access> 11819 <resetValue>0x0000</resetValue> 11820 <fields> 11821 <field> 11822 <name>ONEBIT</name> 11823 <description>One sample bit method 11824 enable</description> 11825 <bitOffset>11</bitOffset> 11826 <bitWidth>1</bitWidth> 11827 <enumeratedValues><name>ONEBIT</name><usage>read-write</usage><enumeratedValue><name>Sample3</name><description>Three sample bit method</description><value>0</value></enumeratedValue><enumeratedValue><name>Sample1</name><description>One sample bit method</description><value>1</value></enumeratedValue></enumeratedValues> 11828 </field> 11829 <field> 11830 <name>CTSIE</name> 11831 <description>CTS interrupt enable</description> 11832 <bitOffset>10</bitOffset> 11833 <bitWidth>1</bitWidth> 11834 <enumeratedValues><name>CTSIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>CTS interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>CTS interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 11835 </field> 11836 <field> 11837 <name>CTSE</name> 11838 <description>CTS enable</description> 11839 <bitOffset>9</bitOffset> 11840 <bitWidth>1</bitWidth> 11841 <enumeratedValues><name>CTSE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>CTS hardware flow control disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>CTS hardware flow control enabled</description><value>1</value></enumeratedValue></enumeratedValues> 11842 </field> 11843 <field> 11844 <name>RTSE</name> 11845 <description>RTS enable</description> 11846 <bitOffset>8</bitOffset> 11847 <bitWidth>1</bitWidth> 11848 <enumeratedValues><name>RTSE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>RTS hardware flow control disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>RTS hardware flow control enabled</description><value>1</value></enumeratedValue></enumeratedValues> 11849 </field> 11850 <field> 11851 <name>DMAT</name> 11852 <description>DMA enable transmitter</description> 11853 <bitOffset>7</bitOffset> 11854 <bitWidth>1</bitWidth> 11855 <enumeratedValues><name>DMAT</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>DMA mode is disabled for transmission</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>DMA mode is enabled for transmission</description><value>1</value></enumeratedValue></enumeratedValues> 11856 </field> 11857 <field> 11858 <name>DMAR</name> 11859 <description>DMA enable receiver</description> 11860 <bitOffset>6</bitOffset> 11861 <bitWidth>1</bitWidth> 11862 <enumeratedValues><name>DMAR</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>DMA mode is disabled for reception</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>DMA mode is enabled for reception</description><value>1</value></enumeratedValue></enumeratedValues> 11863 </field> 11864 <field> 11865 <name>SCEN</name> 11866 <description>Smartcard mode enable</description> 11867 <bitOffset>5</bitOffset> 11868 <bitWidth>1</bitWidth> 11869 <enumeratedValues><name>SCEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Smartcard mode disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Smartcard mode enabled</description><value>1</value></enumeratedValue></enumeratedValues> 11870 </field> 11871 <field> 11872 <name>NACK</name> 11873 <description>Smartcard NACK enable</description> 11874 <bitOffset>4</bitOffset> 11875 <bitWidth>1</bitWidth> 11876 <enumeratedValues><name>NACK</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>NACK transmission in case of parity error is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>NACK transmission during parity error is enabled</description><value>1</value></enumeratedValue></enumeratedValues> 11877 </field> 11878 <field> 11879 <name>HDSEL</name> 11880 <description>Half-duplex selection</description> 11881 <bitOffset>3</bitOffset> 11882 <bitWidth>1</bitWidth> 11883 <enumeratedValues><name>HDSEL</name><usage>read-write</usage><enumeratedValue><name>FullDuplex</name><description>Half duplex mode is not selected</description><value>0</value></enumeratedValue><enumeratedValue><name>HalfDuplex</name><description>Half duplex mode is selected</description><value>1</value></enumeratedValue></enumeratedValues> 11884 </field> 11885 <field> 11886 <name>IRLP</name> 11887 <description>IrDA low-power</description> 11888 <bitOffset>2</bitOffset> 11889 <bitWidth>1</bitWidth> 11890 <enumeratedValues><name>IRLP</name><usage>read-write</usage><enumeratedValue><name>Normal</name><description>Normal mode</description><value>0</value></enumeratedValue><enumeratedValue><name>LowPower</name><description>Low-power mode</description><value>1</value></enumeratedValue></enumeratedValues> 11891 </field> 11892 <field> 11893 <name>IREN</name> 11894 <description>IrDA mode enable</description> 11895 <bitOffset>1</bitOffset> 11896 <bitWidth>1</bitWidth> 11897 <enumeratedValues><name>IREN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>IrDA disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>IrDA enabled</description><value>1</value></enumeratedValue></enumeratedValues> 11898 </field> 11899 <field> 11900 <name>EIE</name> 11901 <description>Error interrupt enable</description> 11902 <bitOffset>0</bitOffset> 11903 <bitWidth>1</bitWidth> 11904 <enumeratedValues><name>EIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Error interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Error interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 11905 </field> 11906 </fields> 11907 </register> 11908 <register> 11909 <name>GTPR</name> 11910 <displayName>GTPR</displayName> 11911 <description>Guard time and prescaler 11912 register</description> 11913 <addressOffset>0x18</addressOffset> 11914 <size>0x20</size> 11915 <access>read-write</access> 11916 <resetValue>0x0000</resetValue> 11917 <fields> 11918 <field> 11919 <name>GT</name> 11920 <description>Guard time value</description> 11921 <bitOffset>8</bitOffset> 11922 <bitWidth>8</bitWidth> 11923 </field> 11924 <field> 11925 <name>PSC</name> 11926 <description>Prescaler value</description> 11927 <bitOffset>0</bitOffset> 11928 <bitWidth>8</bitWidth> 11929 </field> 11930 </fields> 11931 </register> 11932 </registers> 11933 </peripheral> 11934 <peripheral derivedFrom="USART1"> 11935 <name>USART2</name> 11936 <baseAddress>0x40004400</baseAddress> 11937 <interrupt> 11938 <name>USART2</name> 11939 <description>USART2 global interrupt</description> 11940 <value>38</value> 11941 </interrupt> 11942 </peripheral> 11943 <peripheral derivedFrom="USART1"> 11944 <name>USART3</name> 11945 <baseAddress>0x40004800</baseAddress> 11946 <interrupt> 11947 <name>USART3</name> 11948 <description>USART3 global interrupt</description> 11949 <value>39</value> 11950 </interrupt> 11951 </peripheral> 11952 <peripheral> 11953 <name>DAC</name> 11954 <description>Digital-to-analog converter</description> 11955 <groupName>DAC</groupName> 11956 <baseAddress>0x40007400</baseAddress> 11957 <addressBlock> 11958 <offset>0x0</offset> 11959 <size>0x400</size> 11960 <usage>registers</usage> 11961 </addressBlock> 11962 <interrupt> 11963 <name>TIM6_DAC</name> 11964 <description>TIM6 global interrupt, DAC1 and DAC2 underrun 11965 error interrupt</description> 11966 <value>54</value> 11967 </interrupt> 11968 <registers> 11969 <register> 11970 <name>CR</name> 11971 <displayName>CR</displayName> 11972 <description>control register</description> 11973 <addressOffset>0x0</addressOffset> 11974 <size>0x20</size> 11975 <access>read-write</access> 11976 <resetValue>0x00000000</resetValue> 11977 <fields> 11978 <field> 11979 <name>DMAUDRIE2</name> 11980 <description>DAC channel2 DMA underrun interrupt 11981 enable</description> 11982 <bitOffset>29</bitOffset> 11983 <bitWidth>1</bitWidth> 11984 <enumeratedValues derivedFrom="DMAUDRIE1"/> 11985 </field> 11986 <field> 11987 <name>DMAEN2</name> 11988 <description>DAC channel2 DMA enable</description> 11989 <bitOffset>28</bitOffset> 11990 <bitWidth>1</bitWidth> 11991 <enumeratedValues derivedFrom="DMAEN1"/> 11992 </field> 11993 <field> 11994 <name>MAMP2</name> 11995 <description>DAC channel2 mask/amplitude 11996 selector</description> 11997 <bitOffset>24</bitOffset> 11998 <bitWidth>4</bitWidth> 11999 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 12000 </field> 12001 <field> 12002 <name>WAVE2</name> 12003 <description>DAC channel2 noise/triangle wave 12004 generation enable</description> 12005 <bitOffset>22</bitOffset> 12006 <bitWidth>2</bitWidth> 12007 <enumeratedValues><name>WAVE2</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Wave generation disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Noise</name><description>Noise wave generation enabled</description><value>1</value></enumeratedValue><enumeratedValue><name>Triangle</name><description>Triangle wave generation enabled</description><value>2</value></enumeratedValue></enumeratedValues> 12008 </field> 12009 <field> 12010 <name>TSEL2</name> 12011 <description>DAC channel2 trigger 12012 selection</description> 12013 <bitOffset>19</bitOffset> 12014 <bitWidth>3</bitWidth> 12015 <enumeratedValues><name>TSEL2</name><usage>read-write</usage><enumeratedValue><name>TIM6_TRGO</name><description>Timer 6 TRGO event</description><value>0</value></enumeratedValue><enumeratedValue><name>TIM8_TRGO</name><description>Timer 8 TRGO event</description><value>1</value></enumeratedValue><enumeratedValue><name>TIM7_TRGO</name><description>Timer 7 TRGO event</description><value>2</value></enumeratedValue><enumeratedValue><name>TIM5_TRGO</name><description>Timer 5 TRGO event</description><value>3</value></enumeratedValue><enumeratedValue><name>TIM2_TRGO</name><description>Timer 2 TRGO event</description><value>4</value></enumeratedValue><enumeratedValue><name>TIM4_TRGO</name><description>Timer 4 TRGO event</description><value>5</value></enumeratedValue><enumeratedValue><name>EXTI9</name><description>EXTI line9</description><value>6</value></enumeratedValue><enumeratedValue><name>SOFTWARE</name><description>Software trigger</description><value>7</value></enumeratedValue></enumeratedValues> 12016 </field> 12017 <field> 12018 <name>TEN2</name> 12019 <description>DAC channel2 trigger 12020 enable</description> 12021 <bitOffset>18</bitOffset> 12022 <bitWidth>1</bitWidth> 12023 <enumeratedValues derivedFrom="TEN1"/> 12024 </field> 12025 <field> 12026 <name>BOFF2</name> 12027 <description>DAC channel2 output buffer 12028 disable</description> 12029 <bitOffset>17</bitOffset> 12030 <bitWidth>1</bitWidth> 12031 <enumeratedValues derivedFrom="BOFF1"/> 12032 </field> 12033 <field> 12034 <name>EN2</name> 12035 <description>DAC channel2 enable</description> 12036 <bitOffset>16</bitOffset> 12037 <bitWidth>1</bitWidth> 12038 <enumeratedValues derivedFrom="EN1"/> 12039 </field> 12040 <field> 12041 <name>DMAUDRIE1</name> 12042 <description>DAC channel1 DMA Underrun Interrupt 12043 enable</description> 12044 <bitOffset>13</bitOffset> 12045 <bitWidth>1</bitWidth> 12046 <enumeratedValues><name>DMAUDRIE1</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>DAC channel X DMA Underrun Interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>DAC channel X DMA Underrun Interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 12047 </field> 12048 <field> 12049 <name>DMAEN1</name> 12050 <description>DAC channel1 DMA enable</description> 12051 <bitOffset>12</bitOffset> 12052 <bitWidth>1</bitWidth> 12053 <enumeratedValues><name>DMAEN1</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>DAC channel X DMA mode disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>DAC channel X DMA mode enabled</description><value>1</value></enumeratedValue></enumeratedValues> 12054 </field> 12055 <field> 12056 <name>MAMP1</name> 12057 <description>DAC channel1 mask/amplitude 12058 selector</description> 12059 <bitOffset>8</bitOffset> 12060 <bitWidth>4</bitWidth> 12061 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 12062 </field> 12063 <field> 12064 <name>WAVE1</name> 12065 <description>DAC channel1 noise/triangle wave 12066 generation enable</description> 12067 <bitOffset>6</bitOffset> 12068 <bitWidth>2</bitWidth> 12069 <enumeratedValues><name>WAVE1</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Wave generation disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Noise</name><description>Noise wave generation enabled</description><value>1</value></enumeratedValue><enumeratedValue><name>Triangle</name><description>Triangle wave generation enabled</description><value>2</value></enumeratedValue></enumeratedValues> 12070 </field> 12071 <field> 12072 <name>TSEL1</name> 12073 <description>DAC channel1 trigger 12074 selection</description> 12075 <bitOffset>3</bitOffset> 12076 <bitWidth>3</bitWidth> 12077 <enumeratedValues><name>TSEL1</name><usage>read-write</usage><enumeratedValue><name>TIM6_TRGO</name><description>Timer 6 TRGO event</description><value>0</value></enumeratedValue><enumeratedValue><name>TIM3_TRGO</name><description>Timer 3 TRGO event</description><value>1</value></enumeratedValue><enumeratedValue><name>TIM7_TRGO</name><description>Timer 7 TRGO event</description><value>2</value></enumeratedValue><enumeratedValue><name>TIM15_TRGO</name><description>Timer 15 TRGO event</description><value>3</value></enumeratedValue><enumeratedValue><name>TIM2_TRGO</name><description>Timer 2 TRGO event</description><value>4</value></enumeratedValue><enumeratedValue><name>EXTI9</name><description>EXTI line9</description><value>6</value></enumeratedValue><enumeratedValue><name>SOFTWARE</name><description>Software trigger</description><value>7</value></enumeratedValue></enumeratedValues> 12078 </field> 12079 <field> 12080 <name>TEN1</name> 12081 <description>DAC channel1 trigger 12082 enable</description> 12083 <bitOffset>2</bitOffset> 12084 <bitWidth>1</bitWidth> 12085 <enumeratedValues><name>TEN1</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>DAC channel X trigger disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>DAC channel X trigger enabled</description><value>1</value></enumeratedValue></enumeratedValues> 12086 </field> 12087 <field> 12088 <name>BOFF1</name> 12089 <description>DAC channel1 output buffer 12090 disable</description> 12091 <bitOffset>1</bitOffset> 12092 <bitWidth>1</bitWidth> 12093 <enumeratedValues><name>BOFF1</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>DAC channel X output buffer enabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>DAC channel X output buffer disabled</description><value>1</value></enumeratedValue></enumeratedValues> 12094 </field> 12095 <field> 12096 <name>EN1</name> 12097 <description>DAC channel1 enable</description> 12098 <bitOffset>0</bitOffset> 12099 <bitWidth>1</bitWidth> 12100 <enumeratedValues><name>EN1</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>DAC channel X disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>DAC channel X enabled</description><value>1</value></enumeratedValue></enumeratedValues> 12101 </field> 12102 </fields> 12103 </register> 12104 <register> 12105 <name>SWTRIGR</name> 12106 <displayName>SWTRIGR</displayName> 12107 <description>software trigger register</description> 12108 <addressOffset>0x4</addressOffset> 12109 <size>0x20</size> 12110 <access>write-only</access> 12111 <resetValue>0x00000000</resetValue> 12112 <fields> 12113 <field> 12114 <name>SWTRIG2</name> 12115 <description>DAC channel2 software 12116 trigger</description> 12117 <bitOffset>1</bitOffset> 12118 <bitWidth>1</bitWidth> 12119 <enumeratedValues derivedFrom="SWTRIG1"/> 12120 </field> 12121 <field> 12122 <name>SWTRIG1</name> 12123 <description>DAC channel1 software 12124 trigger</description> 12125 <bitOffset>0</bitOffset> 12126 <bitWidth>1</bitWidth> 12127 <enumeratedValues><name>SWTRIG1</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>DAC channel X software trigger disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>DAC channel X software trigger enabled</description><value>1</value></enumeratedValue></enumeratedValues> 12128 </field> 12129 </fields> 12130 </register> 12131 <register> 12132 <name>DHR12R1</name> 12133 <displayName>DHR12R1</displayName> 12134 <description>channel1 12-bit right-aligned data holding 12135 register</description> 12136 <addressOffset>0x8</addressOffset> 12137 <size>0x20</size> 12138 <access>read-write</access> 12139 <resetValue>0x00000000</resetValue> 12140 <fields> 12141 <field> 12142 <name>DACC1DHR</name> 12143 <description>DAC channel1 12-bit right-aligned 12144 data</description> 12145 <bitOffset>0</bitOffset> 12146 <bitWidth>12</bitWidth> 12147 <writeConstraint><range><minimum>0</minimum><maximum>4095</maximum></range></writeConstraint> 12148 </field> 12149 </fields> 12150 </register> 12151 <register> 12152 <name>DHR12L1</name> 12153 <displayName>DHR12L1</displayName> 12154 <description>channel1 12-bit left aligned data holding 12155 register</description> 12156 <addressOffset>0xC</addressOffset> 12157 <size>0x20</size> 12158 <access>read-write</access> 12159 <resetValue>0x00000000</resetValue> 12160 <fields> 12161 <field> 12162 <name>DACC1DHR</name> 12163 <description>DAC channel1 12-bit left-aligned 12164 data</description> 12165 <bitOffset>4</bitOffset> 12166 <bitWidth>12</bitWidth> 12167 <writeConstraint><range><minimum>0</minimum><maximum>4095</maximum></range></writeConstraint> 12168 </field> 12169 </fields> 12170 </register> 12171 <register> 12172 <name>DHR8R1</name> 12173 <displayName>DHR8R1</displayName> 12174 <description>channel1 8-bit right aligned data holding 12175 register</description> 12176 <addressOffset>0x10</addressOffset> 12177 <size>0x20</size> 12178 <access>read-write</access> 12179 <resetValue>0x00000000</resetValue> 12180 <fields> 12181 <field> 12182 <name>DACC1DHR</name> 12183 <description>DAC channel1 8-bit right-aligned 12184 data</description> 12185 <bitOffset>0</bitOffset> 12186 <bitWidth>8</bitWidth> 12187 <writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint> 12188 </field> 12189 </fields> 12190 </register> 12191 <register> 12192 <name>DHR12R2</name> 12193 <displayName>DHR12R2</displayName> 12194 <description>channel2 12-bit right aligned data holding 12195 register</description> 12196 <addressOffset>0x14</addressOffset> 12197 <size>0x20</size> 12198 <access>read-write</access> 12199 <resetValue>0x00000000</resetValue> 12200 <fields> 12201 <field> 12202 <name>DACC2DHR</name> 12203 <description>DAC channel2 12-bit right-aligned 12204 data</description> 12205 <bitOffset>0</bitOffset> 12206 <bitWidth>12</bitWidth> 12207 <writeConstraint><range><minimum>0</minimum><maximum>4095</maximum></range></writeConstraint> 12208 </field> 12209 </fields> 12210 </register> 12211 <register> 12212 <name>DHR12L2</name> 12213 <displayName>DHR12L2</displayName> 12214 <description>channel2 12-bit left aligned data holding 12215 register</description> 12216 <addressOffset>0x18</addressOffset> 12217 <size>0x20</size> 12218 <access>read-write</access> 12219 <resetValue>0x00000000</resetValue> 12220 <fields> 12221 <field> 12222 <name>DACC2DHR</name> 12223 <description>DAC channel2 12-bit left-aligned 12224 data</description> 12225 <bitOffset>4</bitOffset> 12226 <bitWidth>12</bitWidth> 12227 <writeConstraint><range><minimum>0</minimum><maximum>4095</maximum></range></writeConstraint> 12228 </field> 12229 </fields> 12230 </register> 12231 <register> 12232 <name>DHR8R2</name> 12233 <displayName>DHR8R2</displayName> 12234 <description>channel2 8-bit right-aligned data holding 12235 register</description> 12236 <addressOffset>0x1C</addressOffset> 12237 <size>0x20</size> 12238 <access>read-write</access> 12239 <resetValue>0x00000000</resetValue> 12240 <fields> 12241 <field> 12242 <name>DACC2DHR</name> 12243 <description>DAC channel2 8-bit right-aligned 12244 data</description> 12245 <bitOffset>0</bitOffset> 12246 <bitWidth>8</bitWidth> 12247 <writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint> 12248 </field> 12249 </fields> 12250 </register> 12251 <register> 12252 <name>DHR12RD</name> 12253 <displayName>DHR12RD</displayName> 12254 <description>Dual DAC 12-bit right-aligned data holding 12255 register</description> 12256 <addressOffset>0x20</addressOffset> 12257 <size>0x20</size> 12258 <access>read-write</access> 12259 <resetValue>0x00000000</resetValue> 12260 <fields> 12261 <field> 12262 <name>DACC2DHR</name> 12263 <description>DAC channel2 12-bit right-aligned 12264 data</description> 12265 <bitOffset>16</bitOffset> 12266 <bitWidth>12</bitWidth> 12267 <writeConstraint><range><minimum>0</minimum><maximum>4095</maximum></range></writeConstraint> 12268 </field> 12269 <field> 12270 <name>DACC1DHR</name> 12271 <description>DAC channel1 12-bit right-aligned 12272 data</description> 12273 <bitOffset>0</bitOffset> 12274 <bitWidth>12</bitWidth> 12275 <writeConstraint><range><minimum>0</minimum><maximum>4095</maximum></range></writeConstraint> 12276 </field> 12277 </fields> 12278 </register> 12279 <register> 12280 <name>DHR12LD</name> 12281 <displayName>DHR12LD</displayName> 12282 <description>DUAL DAC 12-bit left aligned data holding 12283 register</description> 12284 <addressOffset>0x24</addressOffset> 12285 <size>0x20</size> 12286 <access>read-write</access> 12287 <resetValue>0x00000000</resetValue> 12288 <fields> 12289 <field> 12290 <name>DACC2DHR</name> 12291 <description>DAC channel2 12-bit left-aligned 12292 data</description> 12293 <bitOffset>20</bitOffset> 12294 <bitWidth>12</bitWidth> 12295 <writeConstraint><range><minimum>0</minimum><maximum>4095</maximum></range></writeConstraint> 12296 </field> 12297 <field> 12298 <name>DACC1DHR</name> 12299 <description>DAC channel1 12-bit left-aligned 12300 data</description> 12301 <bitOffset>4</bitOffset> 12302 <bitWidth>12</bitWidth> 12303 <writeConstraint><range><minimum>0</minimum><maximum>4095</maximum></range></writeConstraint> 12304 </field> 12305 </fields> 12306 </register> 12307 <register> 12308 <name>DHR8RD</name> 12309 <displayName>DHR8RD</displayName> 12310 <description>DUAL DAC 8-bit right aligned data holding 12311 register</description> 12312 <addressOffset>0x28</addressOffset> 12313 <size>0x20</size> 12314 <access>read-write</access> 12315 <resetValue>0x00000000</resetValue> 12316 <fields> 12317 <field> 12318 <name>DACC2DHR</name> 12319 <description>DAC channel2 8-bit right-aligned 12320 data</description> 12321 <bitOffset>8</bitOffset> 12322 <bitWidth>8</bitWidth> 12323 <writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint> 12324 </field> 12325 <field> 12326 <name>DACC1DHR</name> 12327 <description>DAC channel1 8-bit right-aligned 12328 data</description> 12329 <bitOffset>0</bitOffset> 12330 <bitWidth>8</bitWidth> 12331 <writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint> 12332 </field> 12333 </fields> 12334 </register> 12335 <register> 12336 <name>DOR1</name> 12337 <displayName>DOR1</displayName> 12338 <description>channel1 data output register</description> 12339 <addressOffset>0x2C</addressOffset> 12340 <size>0x20</size> 12341 <access>read-only</access> 12342 <resetValue>0x00000000</resetValue> 12343 <fields> 12344 <field> 12345 <name>DACC1DOR</name> 12346 <description>DAC channel1 data output</description> 12347 <bitOffset>0</bitOffset> 12348 <bitWidth>12</bitWidth> 12349 </field> 12350 </fields> 12351 </register> 12352 <register> 12353 <name>DOR2</name> 12354 <displayName>DOR2</displayName> 12355 <description>channel2 data output register</description> 12356 <addressOffset>0x30</addressOffset> 12357 <size>0x20</size> 12358 <access>read-only</access> 12359 <resetValue>0x00000000</resetValue> 12360 <fields> 12361 <field> 12362 <name>DACC2DOR</name> 12363 <description>DAC channel2 data output</description> 12364 <bitOffset>0</bitOffset> 12365 <bitWidth>12</bitWidth> 12366 </field> 12367 </fields> 12368 </register> 12369 <register> 12370 <name>SR</name> 12371 <displayName>SR</displayName> 12372 <description>status register</description> 12373 <addressOffset>0x34</addressOffset> 12374 <size>0x20</size> 12375 <access>read-write</access> 12376 <resetValue>0x00000000</resetValue> 12377 <fields> 12378 <field> 12379 <name>DMAUDR2</name> 12380 <description>DAC channel2 DMA underrun 12381 flag</description> 12382 <bitOffset>29</bitOffset> 12383 <bitWidth>1</bitWidth> 12384 <enumeratedValues derivedFrom="DMAUDR1"/> 12385 </field> 12386 <field> 12387 <name>DMAUDR1</name> 12388 <description>DAC channel1 DMA underrun 12389 flag</description> 12390 <bitOffset>13</bitOffset> 12391 <bitWidth>1</bitWidth> 12392 <enumeratedValues><name>DMAUDR1</name><usage>read-write</usage><enumeratedValue><name>NoUnderrun</name><description>No DMA underrun error condition occurred for DAC channel X</description><value>0</value></enumeratedValue><enumeratedValue><name>Underrun</name><description>DMA underrun error condition occurred for DAC channel X</description><value>1</value></enumeratedValue></enumeratedValues> 12393 </field> 12394 </fields> 12395 </register> 12396 </registers> 12397 </peripheral> 12398 <peripheral> 12399 <name>PWR</name> 12400 <description>Power control</description> 12401 <groupName>PWR</groupName> 12402 <baseAddress>0x40007000</baseAddress> 12403 <addressBlock> 12404 <offset>0x0</offset> 12405 <size>0x400</size> 12406 <usage>registers</usage> 12407 </addressBlock> 12408 <interrupt> 12409 <name>PVD</name> 12410 <description>PVD through EXTI line detection 12411 interrupt</description> 12412 <value>1</value> 12413 </interrupt> 12414 <registers> 12415 <register> 12416 <name>CR</name> 12417 <displayName>CR</displayName> 12418 <description>power control register</description> 12419 <addressOffset>0x0</addressOffset> 12420 <size>0x20</size> 12421 <access>read-write</access> 12422 <resetValue>0x00000000</resetValue> 12423 <fields> 12424 <field> 12425 <name>FPDS</name> 12426 <description>Flash power down in Stop 12427 mode</description> 12428 <bitOffset>9</bitOffset> 12429 <bitWidth>1</bitWidth> 12430 </field> 12431 <field> 12432 <name>DBP</name> 12433 <description>Disable backup domain write 12434 protection</description> 12435 <bitOffset>8</bitOffset> 12436 <bitWidth>1</bitWidth> 12437 </field> 12438 <field> 12439 <name>PLS</name> 12440 <description>PVD level selection</description> 12441 <bitOffset>5</bitOffset> 12442 <bitWidth>3</bitWidth> 12443 </field> 12444 <field> 12445 <name>PVDE</name> 12446 <description>Power voltage detector 12447 enable</description> 12448 <bitOffset>4</bitOffset> 12449 <bitWidth>1</bitWidth> 12450 </field> 12451 <field> 12452 <name>CSBF</name> 12453 <description>Clear standby flag</description> 12454 <bitOffset>3</bitOffset> 12455 <bitWidth>1</bitWidth> 12456 </field> 12457 <field> 12458 <name>CWUF</name> 12459 <description>Clear wakeup flag</description> 12460 <bitOffset>2</bitOffset> 12461 <bitWidth>1</bitWidth> 12462 </field> 12463 <field> 12464 <name>PDDS</name> 12465 <description>Power down deepsleep</description> 12466 <bitOffset>1</bitOffset> 12467 <bitWidth>1</bitWidth> 12468 </field> 12469 <field> 12470 <name>LPDS</name> 12471 <description>Low-power deep sleep</description> 12472 <bitOffset>0</bitOffset> 12473 <bitWidth>1</bitWidth> 12474 </field> 12475 </fields> 12476 </register> 12477 <register> 12478 <name>CSR</name> 12479 <displayName>CSR</displayName> 12480 <description>power control/status register</description> 12481 <addressOffset>0x4</addressOffset> 12482 <size>0x20</size> 12483 <resetValue>0x00000000</resetValue> 12484 <fields> 12485 <field> 12486 <name>WUF</name> 12487 <description>Wakeup flag</description> 12488 <bitOffset>0</bitOffset> 12489 <bitWidth>1</bitWidth> 12490 <access>read-only</access> 12491 </field> 12492 <field> 12493 <name>SBF</name> 12494 <description>Standby flag</description> 12495 <bitOffset>1</bitOffset> 12496 <bitWidth>1</bitWidth> 12497 <access>read-only</access> 12498 </field> 12499 <field> 12500 <name>PVDO</name> 12501 <description>PVD output</description> 12502 <bitOffset>2</bitOffset> 12503 <bitWidth>1</bitWidth> 12504 <access>read-only</access> 12505 </field> 12506 <field> 12507 <name>BRR</name> 12508 <description>Backup regulator ready</description> 12509 <bitOffset>3</bitOffset> 12510 <bitWidth>1</bitWidth> 12511 <access>read-only</access> 12512 </field> 12513 <field> 12514 <name>EWUP</name> 12515 <description>Enable WKUP pin</description> 12516 <bitOffset>8</bitOffset> 12517 <bitWidth>1</bitWidth> 12518 <access>read-write</access> 12519 </field> 12520 <field> 12521 <name>BRE</name> 12522 <description>Backup regulator enable</description> 12523 <bitOffset>9</bitOffset> 12524 <bitWidth>1</bitWidth> 12525 <access>read-write</access> 12526 </field> 12527 <field> 12528 <name>VOSRDY</name> 12529 <description>Regulator voltage scaling output 12530 selection ready bit</description> 12531 <bitOffset>14</bitOffset> 12532 <bitWidth>1</bitWidth> 12533 <access>read-write</access> 12534 </field> 12535 </fields> 12536 </register> 12537 </registers> 12538 </peripheral> 12539 <peripheral derivedFrom="I2C1"> 12540 <name>I2C3</name> 12541 <baseAddress>0x40005C00</baseAddress> 12542 <interrupt> 12543 <name>I2C3_EV</name> 12544 <description>I2C3 event interrupt</description> 12545 <value>72</value> 12546 </interrupt> 12547 <interrupt> 12548 <name>I2C3_ER</name> 12549 <description>I2C3 error interrupt</description> 12550 <value>73</value> 12551 </interrupt> 12552 </peripheral> 12553 <peripheral derivedFrom="I2C1"> 12554 <name>I2C2</name> 12555 <baseAddress>0x40005800</baseAddress> 12556 <interrupt> 12557 <name>I2C2_EV</name> 12558 <description>I2C2 event interrupt</description> 12559 <value>33</value> 12560 </interrupt> 12561 <interrupt> 12562 <name>I2C2_ER</name> 12563 <description>I2C2 error interrupt</description> 12564 <value>34</value> 12565 </interrupt> 12566 </peripheral> 12567 <peripheral> 12568 <name>I2C1</name> 12569 <description>Inter-integrated circuit</description> 12570 <groupName>I2C</groupName> 12571 <baseAddress>0x40005400</baseAddress> 12572 <addressBlock> 12573 <offset>0x0</offset> 12574 <size>0x400</size> 12575 <usage>registers</usage> 12576 </addressBlock> 12577 <interrupt> 12578 <name>I2C1_EV</name> 12579 <description>I2C1 event interrupt</description> 12580 <value>31</value> 12581 </interrupt> 12582 <interrupt> 12583 <name>I2C1_ER</name> 12584 <description>I2C1 error interrupt</description> 12585 <value>32</value> 12586 </interrupt> 12587 <registers> 12588 <register> 12589 <name>CR1</name> 12590 <displayName>CR1</displayName> 12591 <description>Control register 1</description> 12592 <addressOffset>0x0</addressOffset> 12593 <size>0x20</size> 12594 <access>read-write</access> 12595 <resetValue>0x0000</resetValue> 12596 <fields> 12597 <field> 12598 <name>SWRST</name> 12599 <description>Software reset</description> 12600 <bitOffset>15</bitOffset> 12601 <bitWidth>1</bitWidth> 12602 <enumeratedValues><name>SWRST</name><usage>read-write</usage><enumeratedValue><name>NotReset</name><description>I2C peripheral not under reset</description><value>0</value></enumeratedValue><enumeratedValue><name>Reset</name><description>I2C peripheral under reset</description><value>1</value></enumeratedValue></enumeratedValues> 12603 </field> 12604 <field> 12605 <name>ALERT</name> 12606 <description>SMBus alert</description> 12607 <bitOffset>13</bitOffset> 12608 <bitWidth>1</bitWidth> 12609 <enumeratedValues><name>ALERT</name><usage>read-write</usage><enumeratedValue><name>Release</name><description>SMBA pin released high</description><value>0</value></enumeratedValue><enumeratedValue><name>Drive</name><description>SMBA pin driven low</description><value>1</value></enumeratedValue></enumeratedValues> 12610 </field> 12611 <field> 12612 <name>PEC</name> 12613 <description>Packet error checking</description> 12614 <bitOffset>12</bitOffset> 12615 <bitWidth>1</bitWidth> 12616 <enumeratedValues><name>PEC</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>No PEC transfer</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>PEC transfer</description><value>1</value></enumeratedValue></enumeratedValues> 12617 </field> 12618 <field> 12619 <name>POS</name> 12620 <description>Acknowledge/PEC Position (for data 12621 reception)</description> 12622 <bitOffset>11</bitOffset> 12623 <bitWidth>1</bitWidth> 12624 <enumeratedValues><name>POS</name><usage>read-write</usage><enumeratedValue><name>Current</name><description>ACK bit controls the (N)ACK of the current byte being received</description><value>0</value></enumeratedValue><enumeratedValue><name>Next</name><description>ACK bit controls the (N)ACK of the next byte to be received</description><value>1</value></enumeratedValue></enumeratedValues> 12625 </field> 12626 <field> 12627 <name>ACK</name> 12628 <description>Acknowledge enable</description> 12629 <bitOffset>10</bitOffset> 12630 <bitWidth>1</bitWidth> 12631 <enumeratedValues><name>ACK</name><usage>read-write</usage><enumeratedValue><name>NAK</name><description>No acknowledge returned</description><value>0</value></enumeratedValue><enumeratedValue><name>ACK</name><description>Acknowledge returned after a byte is received</description><value>1</value></enumeratedValue></enumeratedValues> 12632 </field> 12633 <field> 12634 <name>STOP</name> 12635 <description>Stop generation</description> 12636 <bitOffset>9</bitOffset> 12637 <bitWidth>1</bitWidth> 12638 <enumeratedValues><name>STOP</name><usage>read-write</usage><enumeratedValue><name>NoStop</name><description>No Stop generation</description><value>0</value></enumeratedValue><enumeratedValue><name>Stop</name><description>In master mode: stop generation after current byte/start, in slave mode: release SCL and SDA after current byte</description><value>1</value></enumeratedValue></enumeratedValues> 12639 </field> 12640 <field> 12641 <name>START</name> 12642 <description>Start generation</description> 12643 <bitOffset>8</bitOffset> 12644 <bitWidth>1</bitWidth> 12645 <enumeratedValues><name>START</name><usage>read-write</usage><enumeratedValue><name>NoStart</name><description>No Start generation</description><value>0</value></enumeratedValue><enumeratedValue><name>Start</name><description>In master mode: repeated start generation, in slave mode: start generation when bus is free</description><value>1</value></enumeratedValue></enumeratedValues> 12646 </field> 12647 <field> 12648 <name>NOSTRETCH</name> 12649 <description>Clock stretching disable (Slave 12650 mode)</description> 12651 <bitOffset>7</bitOffset> 12652 <bitWidth>1</bitWidth> 12653 <enumeratedValues><name>NOSTRETCH</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>Clock stretching enabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>Clock stretching disabled</description><value>1</value></enumeratedValue></enumeratedValues> 12654 </field> 12655 <field> 12656 <name>ENGC</name> 12657 <description>General call enable</description> 12658 <bitOffset>6</bitOffset> 12659 <bitWidth>1</bitWidth> 12660 <enumeratedValues><name>ENGC</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>General call disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>General call enabled</description><value>1</value></enumeratedValue></enumeratedValues> 12661 </field> 12662 <field> 12663 <name>ENPEC</name> 12664 <description>PEC enable</description> 12665 <bitOffset>5</bitOffset> 12666 <bitWidth>1</bitWidth> 12667 <enumeratedValues><name>ENPEC</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>PEC calculation disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>PEC calculation enabled</description><value>1</value></enumeratedValue></enumeratedValues> 12668 </field> 12669 <field> 12670 <name>ENARP</name> 12671 <description>ARP enable</description> 12672 <bitOffset>4</bitOffset> 12673 <bitWidth>1</bitWidth> 12674 <enumeratedValues><name>ENARP</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>ARP disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>ARP enabled</description><value>1</value></enumeratedValue></enumeratedValues> 12675 </field> 12676 <field> 12677 <name>SMBTYPE</name> 12678 <description>SMBus type</description> 12679 <bitOffset>3</bitOffset> 12680 <bitWidth>1</bitWidth> 12681 <enumeratedValues><name>SMBTYPE</name><usage>read-write</usage><enumeratedValue><name>Device</name><description>SMBus Device</description><value>0</value></enumeratedValue><enumeratedValue><name>Host</name><description>SMBus Host</description><value>1</value></enumeratedValue></enumeratedValues> 12682 </field> 12683 <field> 12684 <name>SMBUS</name> 12685 <description>SMBus mode</description> 12686 <bitOffset>1</bitOffset> 12687 <bitWidth>1</bitWidth> 12688 <enumeratedValues><name>SMBUS</name><usage>read-write</usage><enumeratedValue><name>I2C</name><description>I2C Mode</description><value>0</value></enumeratedValue><enumeratedValue><name>SMBus</name><description>SMBus</description><value>1</value></enumeratedValue></enumeratedValues> 12689 </field> 12690 <field> 12691 <name>PE</name> 12692 <description>Peripheral enable</description> 12693 <bitOffset>0</bitOffset> 12694 <bitWidth>1</bitWidth> 12695 <enumeratedValues><name>PE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Peripheral disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Peripheral enabled</description><value>1</value></enumeratedValue></enumeratedValues> 12696 </field> 12697 </fields> 12698 </register> 12699 <register> 12700 <name>CR2</name> 12701 <displayName>CR2</displayName> 12702 <description>Control register 2</description> 12703 <addressOffset>0x4</addressOffset> 12704 <size>0x20</size> 12705 <access>read-write</access> 12706 <resetValue>0x0000</resetValue> 12707 <fields> 12708 <field> 12709 <name>LAST</name> 12710 <description>DMA last transfer</description> 12711 <bitOffset>12</bitOffset> 12712 <bitWidth>1</bitWidth> 12713 <enumeratedValues><name>LAST</name><usage>read-write</usage><enumeratedValue><name>NotLast</name><description>Next DMA EOT is not the last transfer</description><value>0</value></enumeratedValue><enumeratedValue><name>Last</name><description>Next DMA EOT is the last transfer</description><value>1</value></enumeratedValue></enumeratedValues> 12714 </field> 12715 <field> 12716 <name>DMAEN</name> 12717 <description>DMA requests enable</description> 12718 <bitOffset>11</bitOffset> 12719 <bitWidth>1</bitWidth> 12720 <enumeratedValues><name>DMAEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>DMA requests disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>DMA request enabled when TxE=1 or RxNE=1</description><value>1</value></enumeratedValue></enumeratedValues> 12721 </field> 12722 <field> 12723 <name>ITBUFEN</name> 12724 <description>Buffer interrupt enable</description> 12725 <bitOffset>10</bitOffset> 12726 <bitWidth>1</bitWidth> 12727 <enumeratedValues><name>ITBUFEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>TxE=1 or RxNE=1 does not generate any interrupt</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>TxE=1 or RxNE=1 generates Event interrupt</description><value>1</value></enumeratedValue></enumeratedValues> 12728 </field> 12729 <field> 12730 <name>ITEVTEN</name> 12731 <description>Event interrupt enable</description> 12732 <bitOffset>9</bitOffset> 12733 <bitWidth>1</bitWidth> 12734 <enumeratedValues><name>ITEVTEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Event interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Event interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 12735 </field> 12736 <field> 12737 <name>ITERREN</name> 12738 <description>Error interrupt enable</description> 12739 <bitOffset>8</bitOffset> 12740 <bitWidth>1</bitWidth> 12741 <enumeratedValues><name>ITERREN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Error interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Error interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 12742 </field> 12743 <field> 12744 <name>FREQ</name> 12745 <description>Peripheral clock frequency</description> 12746 <bitOffset>0</bitOffset> 12747 <bitWidth>6</bitWidth> 12748 <writeConstraint><range><minimum>2</minimum><maximum>50</maximum></range></writeConstraint> 12749 </field> 12750 </fields> 12751 </register> 12752 <register> 12753 <name>OAR1</name> 12754 <displayName>OAR1</displayName> 12755 <description>Own address register 1</description> 12756 <addressOffset>0x8</addressOffset> 12757 <size>0x20</size> 12758 <access>read-write</access> 12759 <resetValue>0x0000</resetValue> 12760 <fields> 12761 <field> 12762 <name>ADDMODE</name> 12763 <description>Addressing mode (slave 12764 mode)</description> 12765 <bitOffset>15</bitOffset> 12766 <bitWidth>1</bitWidth> 12767 <enumeratedValues><name>ADDMODE</name><usage>read-write</usage><enumeratedValue><name>ADD7</name><description>7-bit slave address</description><value>0</value></enumeratedValue><enumeratedValue><name>ADD10</name><description>10-bit slave address</description><value>1</value></enumeratedValue></enumeratedValues> 12768 </field> 12769 <field><name>ADD</name><description>Interface address</description><bitOffset>0</bitOffset><bitWidth>10</bitWidth><writeConstraint><range><minimum>0</minimum><maximum>1023</maximum></range></writeConstraint> 12770 </field></fields> 12771 </register> 12772 <register> 12773 <name>OAR2</name> 12774 <displayName>OAR2</displayName> 12775 <description>Own address register 2</description> 12776 <addressOffset>0xC</addressOffset> 12777 <size>0x20</size> 12778 <access>read-write</access> 12779 <resetValue>0x0000</resetValue> 12780 <fields> 12781 <field> 12782 <name>ADD2</name> 12783 <description>Interface address</description> 12784 <bitOffset>1</bitOffset> 12785 <bitWidth>7</bitWidth> 12786 <writeConstraint><range><minimum>0</minimum><maximum>127</maximum></range></writeConstraint> 12787 </field> 12788 <field> 12789 <name>ENDUAL</name> 12790 <description>Dual addressing mode 12791 enable</description> 12792 <bitOffset>0</bitOffset> 12793 <bitWidth>1</bitWidth> 12794 <enumeratedValues><name>ENDUAL</name><usage>read-write</usage><enumeratedValue><name>Single</name><description>Single addressing mode</description><value>0</value></enumeratedValue><enumeratedValue><name>Dual</name><description>Dual addressing mode</description><value>1</value></enumeratedValue></enumeratedValues> 12795 </field> 12796 </fields> 12797 </register> 12798 <register> 12799 <name>DR</name> 12800 <displayName>DR</displayName> 12801 <description>Data register</description> 12802 <addressOffset>0x10</addressOffset> 12803 <size>0x20</size> 12804 <access>read-write</access> 12805 <resetValue>0x0000</resetValue> 12806 <fields> 12807 <field> 12808 <name>DR</name> 12809 <description>8-bit data register</description> 12810 <bitOffset>0</bitOffset> 12811 <bitWidth>8</bitWidth> 12812 <writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint> 12813 </field> 12814 </fields> 12815 </register> 12816 <register> 12817 <name>SR1</name> 12818 <displayName>SR1</displayName> 12819 <description>Status register 1</description> 12820 <addressOffset>0x14</addressOffset> 12821 <size>0x20</size> 12822 <resetValue>0x0000</resetValue> 12823 <fields> 12824 <field> 12825 <name>SMBALERT</name> 12826 <description>SMBus alert</description> 12827 <bitOffset>15</bitOffset> 12828 <bitWidth>1</bitWidth> 12829 <access>read-write</access> 12830 <enumeratedValues><name>SMBALERT</name><usage>read-write</usage><enumeratedValue><name>NoAlert</name><description>No SMBALERT occured</description><value>0</value></enumeratedValue><enumeratedValue><name>Alert</name><description>SMBALERT occurred</description><value>1</value></enumeratedValue></enumeratedValues> 12831 </field> 12832 <field> 12833 <name>TIMEOUT</name> 12834 <description>Timeout or Tlow error</description> 12835 <bitOffset>14</bitOffset> 12836 <bitWidth>1</bitWidth> 12837 <access>read-write</access> 12838 <enumeratedValues><name>TIMEOUT</name><usage>read-write</usage><enumeratedValue><name>NoTimeout</name><description>No Timeout error</description><value>0</value></enumeratedValue><enumeratedValue><name>Timeout</name><description>SCL remained LOW for 25 ms</description><value>1</value></enumeratedValue></enumeratedValues> 12839 </field> 12840 <field> 12841 <name>PECERR</name> 12842 <description>PEC Error in reception</description> 12843 <bitOffset>12</bitOffset> 12844 <bitWidth>1</bitWidth> 12845 <access>read-write</access> 12846 <enumeratedValues><name>PECERR</name><usage>read-write</usage><enumeratedValue><name>NoError</name><description>no PEC error: receiver returns ACK after PEC reception (if ACK=1)</description><value>0</value></enumeratedValue><enumeratedValue><name>Error</name><description>PEC error: receiver returns NACK after PEC reception (whatever ACK)</description><value>1</value></enumeratedValue></enumeratedValues> 12847 </field> 12848 <field> 12849 <name>OVR</name> 12850 <description>Overrun/Underrun</description> 12851 <bitOffset>11</bitOffset> 12852 <bitWidth>1</bitWidth> 12853 <access>read-write</access> 12854 <enumeratedValues><name>OVR</name><usage>read-write</usage><enumeratedValue><name>NoOverrun</name><description>No overrun/underrun occured</description><value>0</value></enumeratedValue><enumeratedValue><name>Overrun</name><description>Overrun/underrun occured</description><value>1</value></enumeratedValue></enumeratedValues> 12855 </field> 12856 <field> 12857 <name>AF</name> 12858 <description>Acknowledge failure</description> 12859 <bitOffset>10</bitOffset> 12860 <bitWidth>1</bitWidth> 12861 <access>read-write</access> 12862 <enumeratedValues><name>AF</name><usage>read-write</usage><enumeratedValue><name>NoFailure</name><description>No acknowledge failure</description><value>0</value></enumeratedValue><enumeratedValue><name>Failure</name><description>Acknowledge failure</description><value>1</value></enumeratedValue></enumeratedValues> 12863 </field> 12864 <field> 12865 <name>ARLO</name> 12866 <description>Arbitration lost (master 12867 mode)</description> 12868 <bitOffset>9</bitOffset> 12869 <bitWidth>1</bitWidth> 12870 <access>read-write</access> 12871 <enumeratedValues><name>ARLO</name><usage>read-write</usage><enumeratedValue><name>NoLost</name><description>No Arbitration Lost detected</description><value>0</value></enumeratedValue><enumeratedValue><name>Lost</name><description>Arbitration Lost detected</description><value>1</value></enumeratedValue></enumeratedValues> 12872 </field> 12873 <field> 12874 <name>BERR</name> 12875 <description>Bus error</description> 12876 <bitOffset>8</bitOffset> 12877 <bitWidth>1</bitWidth> 12878 <access>read-write</access> 12879 <enumeratedValues><name>BERR</name><usage>read-write</usage><enumeratedValue><name>NoError</name><description>No misplaced Start or Stop condition</description><value>0</value></enumeratedValue><enumeratedValue><name>Error</name><description>Misplaced Start or Stop condition</description><value>1</value></enumeratedValue></enumeratedValues> 12880 </field> 12881 <field> 12882 <name>TxE</name> 12883 <description>Data register empty 12884 (transmitters)</description> 12885 <bitOffset>7</bitOffset> 12886 <bitWidth>1</bitWidth> 12887 <access>read-only</access> 12888 <enumeratedValues><name>TxE</name><usage>read-write</usage><enumeratedValue><name>NotEmpty</name><description>Data register not empty</description><value>0</value></enumeratedValue><enumeratedValue><name>Empty</name><description>Data register empty</description><value>1</value></enumeratedValue></enumeratedValues> 12889 </field> 12890 <field> 12891 <name>RxNE</name> 12892 <description>Data register not empty 12893 (receivers)</description> 12894 <bitOffset>6</bitOffset> 12895 <bitWidth>1</bitWidth> 12896 <access>read-only</access> 12897 <enumeratedValues><name>RxNE</name><usage>read-write</usage><enumeratedValue><name>Empty</name><description>Data register empty</description><value>0</value></enumeratedValue><enumeratedValue><name>NotEmpty</name><description>Data register not empty</description><value>1</value></enumeratedValue></enumeratedValues> 12898 </field> 12899 <field> 12900 <name>STOPF</name> 12901 <description>Stop detection (slave 12902 mode)</description> 12903 <bitOffset>4</bitOffset> 12904 <bitWidth>1</bitWidth> 12905 <access>read-only</access> 12906 <enumeratedValues><name>STOPF</name><usage>read-write</usage><enumeratedValue><name>NoStop</name><description>No Stop condition detected</description><value>0</value></enumeratedValue><enumeratedValue><name>Stop</name><description>Stop condition detected</description><value>1</value></enumeratedValue></enumeratedValues> 12907 </field> 12908 <field> 12909 <name>ADD10</name> 12910 <description>10-bit header sent (Master 12911 mode)</description> 12912 <bitOffset>3</bitOffset> 12913 <bitWidth>1</bitWidth> 12914 <access>read-only</access> 12915 </field> 12916 <field> 12917 <name>BTF</name> 12918 <description>Byte transfer finished</description> 12919 <bitOffset>2</bitOffset> 12920 <bitWidth>1</bitWidth> 12921 <access>read-only</access> 12922 <enumeratedValues><name>BTF</name><usage>read-write</usage><enumeratedValue><name>NotFinished</name><description>Data byte transfer not done</description><value>0</value></enumeratedValue><enumeratedValue><name>Finished</name><description>Data byte transfer successful</description><value>1</value></enumeratedValue></enumeratedValues> 12923 </field> 12924 <field> 12925 <name>ADDR</name> 12926 <description>Address sent (master mode)/matched 12927 (slave mode)</description> 12928 <bitOffset>1</bitOffset> 12929 <bitWidth>1</bitWidth> 12930 <access>read-only</access> 12931 <enumeratedValues><name>ADDR</name><usage>read-write</usage><enumeratedValue><name>NotMatch</name><description>Adress mismatched or not received</description><value>0</value></enumeratedValue><enumeratedValue><name>Match</name><description>Received slave address matched with one of the enabled slave addresses</description><value>1</value></enumeratedValue></enumeratedValues> 12932 </field> 12933 <field> 12934 <name>SB</name> 12935 <description>Start bit (Master mode)</description> 12936 <bitOffset>0</bitOffset> 12937 <bitWidth>1</bitWidth> 12938 <access>read-only</access> 12939 <enumeratedValues><name>SB</name><usage>read-write</usage><enumeratedValue><name>NoStart</name><description>No Start condition</description><value>0</value></enumeratedValue><enumeratedValue><name>Start</name><description>Start condition generated</description><value>1</value></enumeratedValue></enumeratedValues> 12940 </field> 12941 </fields> 12942 </register> 12943 <register> 12944 <name>SR2</name> 12945 <displayName>SR2</displayName> 12946 <description>Status register 2</description> 12947 <addressOffset>0x18</addressOffset> 12948 <size>0x20</size> 12949 <access>read-only</access> 12950 <resetValue>0x0000</resetValue> 12951 <fields> 12952 <field> 12953 <name>PEC</name> 12954 <description>acket error checking 12955 register</description> 12956 <bitOffset>8</bitOffset> 12957 <bitWidth>8</bitWidth> 12958 </field> 12959 <field> 12960 <name>DUALF</name> 12961 <description>Dual flag (Slave mode)</description> 12962 <bitOffset>7</bitOffset> 12963 <bitWidth>1</bitWidth> 12964 </field> 12965 <field> 12966 <name>SMBHOST</name> 12967 <description>SMBus host header (Slave 12968 mode)</description> 12969 <bitOffset>6</bitOffset> 12970 <bitWidth>1</bitWidth> 12971 </field> 12972 <field> 12973 <name>SMBDEFAULT</name> 12974 <description>SMBus device default address (Slave 12975 mode)</description> 12976 <bitOffset>5</bitOffset> 12977 <bitWidth>1</bitWidth> 12978 </field> 12979 <field> 12980 <name>GENCALL</name> 12981 <description>General call address (Slave 12982 mode)</description> 12983 <bitOffset>4</bitOffset> 12984 <bitWidth>1</bitWidth> 12985 </field> 12986 <field> 12987 <name>TRA</name> 12988 <description>Transmitter/receiver</description> 12989 <bitOffset>2</bitOffset> 12990 <bitWidth>1</bitWidth> 12991 </field> 12992 <field> 12993 <name>BUSY</name> 12994 <description>Bus busy</description> 12995 <bitOffset>1</bitOffset> 12996 <bitWidth>1</bitWidth> 12997 </field> 12998 <field> 12999 <name>MSL</name> 13000 <description>Master/slave</description> 13001 <bitOffset>0</bitOffset> 13002 <bitWidth>1</bitWidth> 13003 </field> 13004 </fields> 13005 </register> 13006 <register> 13007 <name>CCR</name> 13008 <displayName>CCR</displayName> 13009 <description>Clock control register</description> 13010 <addressOffset>0x1C</addressOffset> 13011 <size>0x20</size> 13012 <access>read-write</access> 13013 <resetValue>0x0000</resetValue> 13014 <fields> 13015 <field> 13016 <name>F_S</name> 13017 <description>I2C master mode selection</description> 13018 <bitOffset>15</bitOffset> 13019 <bitWidth>1</bitWidth> 13020 <enumeratedValues><name>F_S</name><usage>read-write</usage><enumeratedValue><name>Standard</name><description>Standard mode I2C</description><value>0</value></enumeratedValue><enumeratedValue><name>Fast</name><description>Fast mode I2C</description><value>1</value></enumeratedValue></enumeratedValues> 13021 </field> 13022 <field> 13023 <name>DUTY</name> 13024 <description>Fast mode duty cycle</description> 13025 <bitOffset>14</bitOffset> 13026 <bitWidth>1</bitWidth> 13027 <enumeratedValues><name>DUTY</name><usage>read-write</usage><enumeratedValue><name>Duty2_1</name><description>Duty cycle t_low/t_high = 2/1</description><value>0</value></enumeratedValue><enumeratedValue><name>Duty16_9</name><description>Duty cycle t_low/t_high = 16/9</description><value>1</value></enumeratedValue></enumeratedValues> 13028 </field> 13029 <field> 13030 <name>CCR</name> 13031 <description>Clock control register in Fast/Standard 13032 mode (Master mode)</description> 13033 <bitOffset>0</bitOffset> 13034 <bitWidth>12</bitWidth> 13035 <writeConstraint><range><minimum>1</minimum><maximum>4095</maximum></range></writeConstraint> 13036 </field> 13037 </fields> 13038 </register> 13039 <register> 13040 <name>TRISE</name> 13041 <displayName>TRISE</displayName> 13042 <description>TRISE register</description> 13043 <addressOffset>0x20</addressOffset> 13044 <size>0x20</size> 13045 <access>read-write</access> 13046 <resetValue>0x0002</resetValue> 13047 <fields> 13048 <field> 13049 <name>TRISE</name> 13050 <description>Maximum rise time in Fast/Standard mode 13051 (Master mode)</description> 13052 <bitOffset>0</bitOffset> 13053 <bitWidth>6</bitWidth> 13054 <writeConstraint><range><minimum>0</minimum><maximum>63</maximum></range></writeConstraint> 13055 </field> 13056 </fields> 13057 </register> 13058 </registers> 13059 </peripheral> 13060 <peripheral> 13061 <name>IWDG</name> 13062 <description>Independent watchdog</description> 13063 <groupName>IWDG</groupName> 13064 <baseAddress>0x40003000</baseAddress> 13065 <addressBlock> 13066 <offset>0x0</offset> 13067 <size>0x400</size> 13068 <usage>registers</usage> 13069 </addressBlock> 13070 <registers> 13071 <register> 13072 <name>KR</name> 13073 <displayName>KR</displayName> 13074 <description>Key register</description> 13075 <addressOffset>0x0</addressOffset> 13076 <size>0x20</size> 13077 <access>write-only</access> 13078 <resetValue>0x00000000</resetValue> 13079 <fields> 13080 <field> 13081 <name>KEY</name> 13082 <description>Key value (write only, read 13083 0000h)</description> 13084 <bitOffset>0</bitOffset> 13085 <bitWidth>16</bitWidth> 13086 <enumeratedValues><name>KEY</name><usage>read-write</usage><enumeratedValue><name>Enable</name><description>Enable access to PR, RLR and WINR registers (0x5555)</description><value>21845</value></enumeratedValue><enumeratedValue><name>Reset</name><description>Reset the watchdog value (0xAAAA)</description><value>43690</value></enumeratedValue><enumeratedValue><name>Start</name><description>Start the watchdog (0xCCCC)</description><value>52428</value></enumeratedValue></enumeratedValues> 13087 </field> 13088 </fields> 13089 </register> 13090 <register> 13091 <name>PR</name> 13092 <displayName>PR</displayName> 13093 <description>Prescaler register</description> 13094 <addressOffset>0x4</addressOffset> 13095 <size>0x20</size> 13096 <access>read-write</access> 13097 <resetValue>0x00000000</resetValue> 13098 <fields> 13099 <field> 13100 <name>PR</name> 13101 <description>Prescaler divider</description> 13102 <bitOffset>0</bitOffset> 13103 <bitWidth>3</bitWidth> 13104 <enumeratedValues><name>PR</name><usage>read-write</usage><enumeratedValue><name>DivideBy4</name><description>Divider /4</description><value>0</value></enumeratedValue><enumeratedValue><name>DivideBy8</name><description>Divider /8</description><value>1</value></enumeratedValue><enumeratedValue><name>DivideBy16</name><description>Divider /16</description><value>2</value></enumeratedValue><enumeratedValue><name>DivideBy32</name><description>Divider /32</description><value>3</value></enumeratedValue><enumeratedValue><name>DivideBy64</name><description>Divider /64</description><value>4</value></enumeratedValue><enumeratedValue><name>DivideBy128</name><description>Divider /128</description><value>5</value></enumeratedValue><enumeratedValue><name>DivideBy256</name><description>Divider /256</description><value>6</value></enumeratedValue><enumeratedValue><name>DivideBy256bis</name><description>Divider /256</description><value>7</value></enumeratedValue></enumeratedValues> 13105 </field> 13106 </fields> 13107 </register> 13108 <register> 13109 <name>RLR</name> 13110 <displayName>RLR</displayName> 13111 <description>Reload register</description> 13112 <addressOffset>0x8</addressOffset> 13113 <size>0x20</size> 13114 <access>read-write</access> 13115 <resetValue>0x00000FFF</resetValue> 13116 <fields> 13117 <field> 13118 <name>RL</name> 13119 <description>Watchdog counter reload 13120 value</description> 13121 <bitOffset>0</bitOffset> 13122 <bitWidth>12</bitWidth> 13123 <writeConstraint><range><minimum>0</minimum><maximum>4095</maximum></range></writeConstraint> 13124 </field> 13125 </fields> 13126 </register> 13127 <register> 13128 <name>SR</name> 13129 <displayName>SR</displayName> 13130 <description>Status register</description> 13131 <addressOffset>0xC</addressOffset> 13132 <size>0x20</size> 13133 <access>read-only</access> 13134 <resetValue>0x00000000</resetValue> 13135 <fields> 13136 <field> 13137 <name>RVU</name> 13138 <description>Watchdog counter reload value 13139 update</description> 13140 <bitOffset>1</bitOffset> 13141 <bitWidth>1</bitWidth> 13142 </field> 13143 <field> 13144 <name>PVU</name> 13145 <description>Watchdog prescaler value 13146 update</description> 13147 <bitOffset>0</bitOffset> 13148 <bitWidth>1</bitWidth> 13149 </field> 13150 </fields> 13151 </register> 13152 </registers> 13153 </peripheral> 13154 <peripheral> 13155 <name>WWDG</name> 13156 <description>Window watchdog</description> 13157 <groupName>WWDG</groupName> 13158 <baseAddress>0x40002C00</baseAddress> 13159 <addressBlock> 13160 <offset>0x0</offset> 13161 <size>0x400</size> 13162 <usage>registers</usage> 13163 </addressBlock> 13164 <interrupt> 13165 <name>WWDG</name> 13166 <description>Window Watchdog interrupt</description> 13167 <value>0</value> 13168 </interrupt> 13169 <registers> 13170 <register> 13171 <name>CR</name> 13172 <displayName>CR</displayName> 13173 <description>Control register</description> 13174 <addressOffset>0x0</addressOffset> 13175 <size>0x20</size> 13176 <access>read-write</access> 13177 <resetValue>0x7F</resetValue> 13178 <fields> 13179 <field> 13180 <name>WDGA</name> 13181 <description>Activation bit</description> 13182 <bitOffset>7</bitOffset> 13183 <bitWidth>1</bitWidth> 13184 <enumeratedValues><name>WDGA</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Watchdog disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Watchdog enabled</description><value>1</value></enumeratedValue></enumeratedValues> 13185 </field> 13186 <field> 13187 <name>T</name> 13188 <description>7-bit counter (MSB to LSB)</description> 13189 <bitOffset>0</bitOffset> 13190 <bitWidth>7</bitWidth> 13191 <writeConstraint><range><minimum>0</minimum><maximum>127</maximum></range></writeConstraint> 13192 </field> 13193 </fields> 13194 </register> 13195 <register> 13196 <name>CFR</name> 13197 <displayName>CFR</displayName> 13198 <description>Configuration register</description> 13199 <addressOffset>0x4</addressOffset> 13200 <size>0x20</size> 13201 <access>read-write</access> 13202 <resetValue>0x7F</resetValue> 13203 <fields> 13204 <field> 13205 <name>EWI</name> 13206 <description>Early wakeup interrupt</description> 13207 <bitOffset>9</bitOffset> 13208 <bitWidth>1</bitWidth> 13209 <enumeratedValues><name>EWIW</name><usage>write</usage><enumeratedValue><name>Enable</name><description>interrupt occurs whenever the counter reaches the value 0x40</description><value>1</value></enumeratedValue></enumeratedValues> 13210 </field> 13211 <field> 13212 <name>W</name> 13213 <description>7-bit window value</description> 13214 <bitOffset>0</bitOffset> 13215 <bitWidth>7</bitWidth> 13216 <writeConstraint><range><minimum>0</minimum><maximum>127</maximum></range></writeConstraint> 13217 </field> 13218 <field><name>WDGTB</name><description>Timer base</description><bitOffset>7</bitOffset><bitWidth>2</bitWidth><enumeratedValues><name>WDGTB</name><usage>read-write</usage><enumeratedValue><name>Div1</name><description>Counter clock (PCLK1 div 4096) div 1</description><value>0</value></enumeratedValue><enumeratedValue><name>Div2</name><description>Counter clock (PCLK1 div 4096) div 2</description><value>1</value></enumeratedValue><enumeratedValue><name>Div4</name><description>Counter clock (PCLK1 div 4096) div 4</description><value>2</value></enumeratedValue><enumeratedValue><name>Div8</name><description>Counter clock (PCLK1 div 4096) div 8</description><value>3</value></enumeratedValue></enumeratedValues> 13219 </field></fields> 13220 </register> 13221 <register> 13222 <name>SR</name> 13223 <displayName>SR</displayName> 13224 <description>Status register</description> 13225 <addressOffset>0x8</addressOffset> 13226 <size>0x20</size> 13227 <access>read-write</access> 13228 <resetValue>0x00</resetValue> 13229 <fields> 13230 <field> 13231 <name>EWIF</name> 13232 <description>Early wakeup interrupt 13233 flag</description> 13234 <bitOffset>0</bitOffset> 13235 <bitWidth>1</bitWidth> 13236 <enumeratedValues><name>EWIFR</name><usage>read</usage><enumeratedValue><name>Pending</name><description>The EWI Interrupt Service Routine has been triggered</description><value>1</value></enumeratedValue><enumeratedValue><name>Finished</name><description>The EWI Interrupt Service Routine has been serviced</description><value>0</value></enumeratedValue></enumeratedValues> 13237 <enumeratedValues><name>EWIFW</name><usage>write</usage><enumeratedValue><name>Finished</name><description>The EWI Interrupt Service Routine has been serviced</description><value>0</value></enumeratedValue></enumeratedValues> 13238 </field> 13239 </fields> 13240 </register> 13241 </registers> 13242 </peripheral> 13243 <peripheral> 13244 <name>RTC</name> 13245 <description>Real-time clock</description> 13246 <groupName>RTC</groupName> 13247 <baseAddress>0x40002800</baseAddress> 13248 <addressBlock> 13249 <offset>0x0</offset> 13250 <size>0x400</size> 13251 <usage>registers</usage> 13252 </addressBlock> 13253 <interrupt> 13254 <name>RTC_WKUP</name> 13255 <description>RTC Wakeup interrupt through the EXTI 13256 line</description> 13257 <value>3</value> 13258 </interrupt> 13259 <interrupt> 13260 <name>RTC_Alarm</name> 13261 <description>RTC Alarms (A and B) through EXTI line 13262 interrupt</description> 13263 <value>41</value> 13264 </interrupt> 13265 <registers> 13266 <register> 13267 <name>TR</name> 13268 <displayName>TR</displayName> 13269 <description>time register</description> 13270 <addressOffset>0x0</addressOffset> 13271 <size>0x20</size> 13272 <access>read-write</access> 13273 <resetValue>0x00000000</resetValue> 13274 <fields> 13275 <field> 13276 <name>PM</name> 13277 <description>AM/PM notation</description> 13278 <bitOffset>22</bitOffset> 13279 <bitWidth>1</bitWidth> 13280 <enumeratedValues><name>PM</name><usage>read-write</usage><enumeratedValue><name>AM</name><description>AM or 24-hour format</description><value>0</value></enumeratedValue><enumeratedValue><name>PM</name><description>PM</description><value>1</value></enumeratedValue></enumeratedValues> 13281 </field> 13282 <field> 13283 <name>HT</name> 13284 <description>Hour tens in BCD format</description> 13285 <bitOffset>20</bitOffset> 13286 <bitWidth>2</bitWidth> 13287 <writeConstraint><range><minimum>0</minimum><maximum>3</maximum></range></writeConstraint> 13288 </field> 13289 <field> 13290 <name>HU</name> 13291 <description>Hour units in BCD format</description> 13292 <bitOffset>16</bitOffset> 13293 <bitWidth>4</bitWidth> 13294 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 13295 </field> 13296 <field> 13297 <name>MNT</name> 13298 <description>Minute tens in BCD format</description> 13299 <bitOffset>12</bitOffset> 13300 <bitWidth>3</bitWidth> 13301 <writeConstraint><range><minimum>0</minimum><maximum>7</maximum></range></writeConstraint> 13302 </field> 13303 <field> 13304 <name>MNU</name> 13305 <description>Minute units in BCD format</description> 13306 <bitOffset>8</bitOffset> 13307 <bitWidth>4</bitWidth> 13308 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 13309 </field> 13310 <field> 13311 <name>ST</name> 13312 <description>Second tens in BCD format</description> 13313 <bitOffset>4</bitOffset> 13314 <bitWidth>3</bitWidth> 13315 <writeConstraint><range><minimum>0</minimum><maximum>7</maximum></range></writeConstraint> 13316 </field> 13317 <field> 13318 <name>SU</name> 13319 <description>Second units in BCD format</description> 13320 <bitOffset>0</bitOffset> 13321 <bitWidth>4</bitWidth> 13322 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 13323 </field> 13324 </fields> 13325 </register> 13326 <register> 13327 <name>DR</name> 13328 <displayName>DR</displayName> 13329 <description>date register</description> 13330 <addressOffset>0x4</addressOffset> 13331 <size>0x20</size> 13332 <access>read-write</access> 13333 <resetValue>0x00002101</resetValue> 13334 <fields> 13335 <field> 13336 <name>YT</name> 13337 <description>Year tens in BCD format</description> 13338 <bitOffset>20</bitOffset> 13339 <bitWidth>4</bitWidth> 13340 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 13341 </field> 13342 <field> 13343 <name>YU</name> 13344 <description>Year units in BCD format</description> 13345 <bitOffset>16</bitOffset> 13346 <bitWidth>4</bitWidth> 13347 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 13348 </field> 13349 <field> 13350 <name>WDU</name> 13351 <description>Week day units</description> 13352 <bitOffset>13</bitOffset> 13353 <bitWidth>3</bitWidth> 13354 <writeConstraint><range><minimum>1</minimum><maximum>7</maximum></range></writeConstraint> 13355 </field> 13356 <field> 13357 <name>MT</name> 13358 <description>Month tens in BCD format</description> 13359 <bitOffset>12</bitOffset> 13360 <bitWidth>1</bitWidth> 13361 <writeConstraint><range><minimum>0</minimum><maximum>1</maximum></range></writeConstraint> 13362 </field> 13363 <field> 13364 <name>MU</name> 13365 <description>Month units in BCD format</description> 13366 <bitOffset>8</bitOffset> 13367 <bitWidth>4</bitWidth> 13368 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 13369 </field> 13370 <field> 13371 <name>DT</name> 13372 <description>Date tens in BCD format</description> 13373 <bitOffset>4</bitOffset> 13374 <bitWidth>2</bitWidth> 13375 <writeConstraint><range><minimum>0</minimum><maximum>3</maximum></range></writeConstraint> 13376 </field> 13377 <field> 13378 <name>DU</name> 13379 <description>Date units in BCD format</description> 13380 <bitOffset>0</bitOffset> 13381 <bitWidth>4</bitWidth> 13382 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 13383 </field> 13384 </fields> 13385 </register> 13386 <register> 13387 <name>CR</name> 13388 <displayName>CR</displayName> 13389 <description>control register</description> 13390 <addressOffset>0x8</addressOffset> 13391 <size>0x20</size> 13392 <access>read-write</access> 13393 <resetValue>0x00000000</resetValue> 13394 <fields> 13395 <field> 13396 <name>COE</name> 13397 <description>Calibration output enable</description> 13398 <bitOffset>23</bitOffset> 13399 <bitWidth>1</bitWidth> 13400 <enumeratedValues><name>COE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Calibration output disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Calibration output enabled</description><value>1</value></enumeratedValue></enumeratedValues> 13401 </field> 13402 <field> 13403 <name>OSEL</name> 13404 <description>Output selection</description> 13405 <bitOffset>21</bitOffset> 13406 <bitWidth>2</bitWidth> 13407 <enumeratedValues><name>OSEL</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Output disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>AlarmA</name><description>Alarm A output enabled</description><value>1</value></enumeratedValue><enumeratedValue><name>AlarmB</name><description>Alarm B output enabled</description><value>2</value></enumeratedValue><enumeratedValue><name>Wakeup</name><description>Wakeup output enabled</description><value>3</value></enumeratedValue></enumeratedValues> 13408 </field> 13409 <field> 13410 <name>POL</name> 13411 <description>Output polarity</description> 13412 <bitOffset>20</bitOffset> 13413 <bitWidth>1</bitWidth> 13414 <enumeratedValues><name>POL</name><usage>read-write</usage><enumeratedValue><name>High</name><description>The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])</description><value>0</value></enumeratedValue><enumeratedValue><name>Low</name><description>The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])</description><value>1</value></enumeratedValue></enumeratedValues> 13415 </field> 13416 <field> 13417 <name>BKP</name> 13418 <description>Backup</description> 13419 <bitOffset>18</bitOffset> 13420 <bitWidth>1</bitWidth> 13421 <enumeratedValues><name>BKP</name><usage>read-write</usage><enumeratedValue><name>DST_Not_Changed</name><description>Daylight Saving Time change has not been performed</description><value>0</value></enumeratedValue><enumeratedValue><name>DST_Changed</name><description>Daylight Saving Time change has been performed</description><value>1</value></enumeratedValue></enumeratedValues> 13422 </field> 13423 <field> 13424 <name>SUB1H</name> 13425 <description>Subtract 1 hour (winter time 13426 change)</description> 13427 <bitOffset>17</bitOffset> 13428 <bitWidth>1</bitWidth> 13429 <enumeratedValues><name>SUB1HW</name><usage>write</usage><enumeratedValue><name>Sub1</name><description>Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode</description><value>1</value></enumeratedValue></enumeratedValues> 13430 </field> 13431 <field> 13432 <name>ADD1H</name> 13433 <description>Add 1 hour (summer time 13434 change)</description> 13435 <bitOffset>16</bitOffset> 13436 <bitWidth>1</bitWidth> 13437 <enumeratedValues><name>ADD1HW</name><usage>write</usage><enumeratedValue><name>Add1</name><description>Adds 1 hour to the current time. This can be used for summer time change outside initialization mode</description><value>1</value></enumeratedValue></enumeratedValues> 13438 </field> 13439 <field> 13440 <name>TSIE</name> 13441 <description>Time-stamp interrupt 13442 enable</description> 13443 <bitOffset>15</bitOffset> 13444 <bitWidth>1</bitWidth> 13445 <enumeratedValues><name>TSIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Time-stamp Interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Time-stamp Interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 13446 </field> 13447 <field> 13448 <name>WUTIE</name> 13449 <description>Wakeup timer interrupt 13450 enable</description> 13451 <bitOffset>14</bitOffset> 13452 <bitWidth>1</bitWidth> 13453 <enumeratedValues><name>WUTIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Wakeup timer interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Wakeup timer interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 13454 </field> 13455 <field> 13456 <name>ALRBIE</name> 13457 <description>Alarm B interrupt enable</description> 13458 <bitOffset>13</bitOffset> 13459 <bitWidth>1</bitWidth> 13460 <enumeratedValues><name>ALRBIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Alarm B Interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Alarm B Interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 13461 </field> 13462 <field> 13463 <name>ALRAIE</name> 13464 <description>Alarm A interrupt enable</description> 13465 <bitOffset>12</bitOffset> 13466 <bitWidth>1</bitWidth> 13467 <enumeratedValues><name>ALRAIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Alarm A interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Alarm A interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 13468 </field> 13469 <field> 13470 <name>TSE</name> 13471 <description>Time stamp enable</description> 13472 <bitOffset>11</bitOffset> 13473 <bitWidth>1</bitWidth> 13474 <enumeratedValues><name>TSE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Timestamp disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Timestamp enabled</description><value>1</value></enumeratedValue></enumeratedValues> 13475 </field> 13476 <field> 13477 <name>WUTE</name> 13478 <description>Wakeup timer enable</description> 13479 <bitOffset>10</bitOffset> 13480 <bitWidth>1</bitWidth> 13481 <enumeratedValues><name>WUTE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Wakeup timer disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Wakeup timer enabled</description><value>1</value></enumeratedValue></enumeratedValues> 13482 </field> 13483 <field> 13484 <name>ALRBE</name> 13485 <description>Alarm B enable</description> 13486 <bitOffset>9</bitOffset> 13487 <bitWidth>1</bitWidth> 13488 <enumeratedValues><name>ALRBE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Alarm B disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Alarm B enabled</description><value>1</value></enumeratedValue></enumeratedValues> 13489 </field> 13490 <field> 13491 <name>ALRAE</name> 13492 <description>Alarm A enable</description> 13493 <bitOffset>8</bitOffset> 13494 <bitWidth>1</bitWidth> 13495 <enumeratedValues><name>ALRAE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Alarm A disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Alarm A enabled</description><value>1</value></enumeratedValue></enumeratedValues> 13496 </field> 13497 <field> 13498 <name>DCE</name> 13499 <description>Coarse digital calibration 13500 enable</description> 13501 <bitOffset>7</bitOffset> 13502 <bitWidth>1</bitWidth> 13503 </field> 13504 <field> 13505 <name>FMT</name> 13506 <description>Hour format</description> 13507 <bitOffset>6</bitOffset> 13508 <bitWidth>1</bitWidth> 13509 <enumeratedValues><name>FMT</name><usage>read-write</usage><enumeratedValue><name>Twenty_Four_Hour</name><description>24 hour/day format</description><value>0</value></enumeratedValue><enumeratedValue><name>AM_PM</name><description>AM/PM hour format</description><value>1</value></enumeratedValue></enumeratedValues> 13510 </field> 13511 <field> 13512 <name>REFCKON</name> 13513 <description>Reference clock detection enable (50 or 13514 60 Hz)</description> 13515 <bitOffset>4</bitOffset> 13516 <bitWidth>1</bitWidth> 13517 <enumeratedValues><name>REFCKON</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>RTC_REFIN detection disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>RTC_REFIN detection enabled</description><value>1</value></enumeratedValue></enumeratedValues> 13518 </field> 13519 <field> 13520 <name>TSEDGE</name> 13521 <description>Time-stamp event active 13522 edge</description> 13523 <bitOffset>3</bitOffset> 13524 <bitWidth>1</bitWidth> 13525 <enumeratedValues><name>TSEDGE</name><usage>read-write</usage><enumeratedValue><name>RisingEdge</name><description>RTC_TS input rising edge generates a time-stamp event</description><value>0</value></enumeratedValue><enumeratedValue><name>FallingEdge</name><description>RTC_TS input falling edge generates a time-stamp event</description><value>1</value></enumeratedValue></enumeratedValues> 13526 </field> 13527 <field> 13528 <name>WUCKSEL</name> 13529 <description>Wakeup clock selection</description> 13530 <bitOffset>0</bitOffset> 13531 <bitWidth>3</bitWidth> 13532 <enumeratedValues><name>WUCKSEL</name><usage>read-write</usage><enumeratedValue><name>Div16</name><description>RTC/16 clock is selected</description><value>0</value></enumeratedValue><enumeratedValue><name>Div8</name><description>RTC/8 clock is selected</description><value>1</value></enumeratedValue><enumeratedValue><name>Div4</name><description>RTC/4 clock is selected</description><value>2</value></enumeratedValue><enumeratedValue><name>Div2</name><description>RTC/2 clock is selected</description><value>3</value></enumeratedValue><enumeratedValue><name>ClockSpare</name><description>ck_spre (usually 1 Hz) clock is selected</description><value>4</value></enumeratedValue><enumeratedValue><name>ClockSpareWithOffset</name><description>ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value</description><value>6</value></enumeratedValue></enumeratedValues> 13533 </field> 13534 <field><name>BYPSHAD</name><description>Bypass the shadow registers</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth><access>read-write</access><enumeratedValues><name>BYPSHAD</name><usage>read-write</usage><enumeratedValue><name>ShadowReg</name><description>Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles</description><value>0</value></enumeratedValue><enumeratedValue><name>BypassShadowReg</name><description>Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters</description><value>1</value></enumeratedValue></enumeratedValues> 13535 </field> 13536 <field><name>COSEL</name><description>Calibration output selection</description><bitOffset>19</bitOffset><bitWidth>1</bitWidth><access>read-write</access><enumeratedValues><name>COSEL</name><usage>read-write</usage><enumeratedValue><name>CalFreq_512Hz</name><description>Calibration output is 512 Hz (with default prescaler setting)</description><value>0</value></enumeratedValue><enumeratedValue><name>CalFreq_1Hz</name><description>Calibration output is 1 Hz (with default prescaler setting)</description><value>1</value></enumeratedValue></enumeratedValues> 13537 </field> 13538 </fields> 13539 </register> 13540 <register> 13541 <name>ISR</name> 13542 <displayName>ISR</displayName> 13543 <description>initialization and status 13544 register</description> 13545 <addressOffset>0xC</addressOffset> 13546 <size>0x20</size> 13547 <resetValue>0x00000007</resetValue> 13548 <fields> 13549 <field> 13550 <name>ALRAWF</name> 13551 <description>Alarm A write flag</description> 13552 <bitOffset>0</bitOffset> 13553 <bitWidth>1</bitWidth> 13554 <access>read-only</access> 13555 <enumeratedValues><name>ALRAWFR</name><usage>read</usage><enumeratedValue><name>UpdateNotAllowed</name><description>Alarm update not allowed</description><value>0</value></enumeratedValue><enumeratedValue><name>UpdateAllowed</name><description>Alarm update allowed</description><value>1</value></enumeratedValue></enumeratedValues> 13556 </field> 13557 <field> 13558 <name>ALRBWF</name> 13559 <description>Alarm B write flag</description> 13560 <bitOffset>1</bitOffset> 13561 <bitWidth>1</bitWidth> 13562 <access>read-only</access> 13563 <enumeratedValues derivedFrom="ALRAWFR"/> 13564 </field> 13565 <field> 13566 <name>WUTWF</name> 13567 <description>Wakeup timer write flag</description> 13568 <bitOffset>2</bitOffset> 13569 <bitWidth>1</bitWidth> 13570 <access>read-only</access> 13571 <enumeratedValues><name>WUTWFR</name><usage>read</usage><enumeratedValue><name>UpdateNotAllowed</name><description>Wakeup timer configuration update not allowed</description><value>0</value></enumeratedValue><enumeratedValue><name>UpdateAllowed</name><description>Wakeup timer configuration update allowed</description><value>1</value></enumeratedValue></enumeratedValues> 13572 </field> 13573 <field> 13574 <name>SHPF</name> 13575 <description>Shift operation pending</description> 13576 <bitOffset>3</bitOffset> 13577 <bitWidth>1</bitWidth> 13578 <access>read-write</access> 13579 <enumeratedValues><name>SHPFR</name><usage>read</usage><enumeratedValue><name>NoShiftPending</name><description>No shift operation is pending</description><value>0</value></enumeratedValue><enumeratedValue><name>ShiftPending</name><description>A shift operation is pending</description><value>1</value></enumeratedValue></enumeratedValues> 13580 </field> 13581 <field> 13582 <name>INITS</name> 13583 <description>Initialization status flag</description> 13584 <bitOffset>4</bitOffset> 13585 <bitWidth>1</bitWidth> 13586 <access>read-only</access> 13587 <enumeratedValues><name>INITSR</name><usage>read</usage><enumeratedValue><name>NotInitalized</name><description>Calendar has not been initialized</description><value>0</value></enumeratedValue><enumeratedValue><name>Initalized</name><description>Calendar has been initialized</description><value>1</value></enumeratedValue></enumeratedValues> 13588 </field> 13589 <field> 13590 <name>RSF</name> 13591 <description>Registers synchronization 13592 flag</description> 13593 <bitOffset>5</bitOffset> 13594 <bitWidth>1</bitWidth> 13595 <access>read-write</access> 13596 <enumeratedValues><name>RSFR</name><usage>read</usage><enumeratedValue><name>NotSynced</name><description>Calendar shadow registers not yet synchronized</description><value>0</value></enumeratedValue><enumeratedValue><name>Synced</name><description>Calendar shadow registers synchronized</description><value>1</value></enumeratedValue></enumeratedValues> 13597 <enumeratedValues><name>RSFW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>This flag is cleared by software by writing 0</description><value>0</value></enumeratedValue></enumeratedValues> 13598 </field> 13599 <field> 13600 <name>INITF</name> 13601 <description>Initialization flag</description> 13602 <bitOffset>6</bitOffset> 13603 <bitWidth>1</bitWidth> 13604 <access>read-only</access> 13605 <enumeratedValues><name>INITFR</name><usage>read</usage><enumeratedValue><name>NotAllowed</name><description>Calendar registers update is not allowed</description><value>0</value></enumeratedValue><enumeratedValue><name>Allowed</name><description>Calendar registers update is allowed</description><value>1</value></enumeratedValue></enumeratedValues> 13606 </field> 13607 <field> 13608 <name>INIT</name> 13609 <description>Initialization mode</description> 13610 <bitOffset>7</bitOffset> 13611 <bitWidth>1</bitWidth> 13612 <access>read-write</access> 13613 <enumeratedValues><name>INIT</name><usage>read-write</usage><enumeratedValue><name>FreeRunningMode</name><description>Free running mode</description><value>0</value></enumeratedValue><enumeratedValue><name>InitMode</name><description>Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset.</description><value>1</value></enumeratedValue></enumeratedValues> 13614 </field> 13615 <field> 13616 <name>ALRAF</name> 13617 <description>Alarm A flag</description> 13618 <bitOffset>8</bitOffset> 13619 <bitWidth>1</bitWidth> 13620 <access>read-write</access> 13621 <enumeratedValues><name>ALRAFR</name><usage>read</usage><enumeratedValue><name>Match</name><description>This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR)</description><value>1</value></enumeratedValue></enumeratedValues> 13622 <enumeratedValues><name>ALRAFW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>This flag is cleared by software by writing 0</description><value>0</value></enumeratedValue></enumeratedValues> 13623 </field> 13624 <field> 13625 <name>ALRBF</name> 13626 <description>Alarm B flag</description> 13627 <bitOffset>9</bitOffset> 13628 <bitWidth>1</bitWidth> 13629 <access>read-write</access> 13630 <enumeratedValues><name>ALRBFR</name><usage>read</usage><enumeratedValue><name>Match</name><description>This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR)</description><value>1</value></enumeratedValue></enumeratedValues> 13631 <enumeratedValues><name>ALRBFW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>This flag is cleared by software by writing 0</description><value>0</value></enumeratedValue></enumeratedValues> 13632 </field> 13633 <field> 13634 <name>WUTF</name> 13635 <description>Wakeup timer flag</description> 13636 <bitOffset>10</bitOffset> 13637 <bitWidth>1</bitWidth> 13638 <access>read-write</access> 13639 <enumeratedValues><name>WUTFR</name><usage>read</usage><enumeratedValue><name>Zero</name><description>This flag is set by hardware when the wakeup auto-reload counter reaches 0</description><value>1</value></enumeratedValue></enumeratedValues> 13640 <enumeratedValues><name>WUTFW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>This flag is cleared by software by writing 0</description><value>0</value></enumeratedValue></enumeratedValues> 13641 </field> 13642 <field> 13643 <name>TSF</name> 13644 <description>Time-stamp flag</description> 13645 <bitOffset>11</bitOffset> 13646 <bitWidth>1</bitWidth> 13647 <access>read-write</access> 13648 <enumeratedValues><name>TSFR</name><usage>read</usage><enumeratedValue><name>TimestampEvent</name><description>This flag is set by hardware when a time-stamp event occurs</description><value>1</value></enumeratedValue></enumeratedValues> 13649 <enumeratedValues><name>TSFW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>This flag is cleared by software by writing 0</description><value>0</value></enumeratedValue></enumeratedValues> 13650 </field> 13651 <field> 13652 <name>TSOVF</name> 13653 <description>Time-stamp overflow flag</description> 13654 <bitOffset>12</bitOffset> 13655 <bitWidth>1</bitWidth> 13656 <access>read-write</access> 13657 <enumeratedValues><name>TSOVFR</name><usage>read</usage><enumeratedValue><name>Overflow</name><description>This flag is set by hardware when a time-stamp event occurs while TSF is already set</description><value>1</value></enumeratedValue></enumeratedValues> 13658 <enumeratedValues><name>TSOVFW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>This flag is cleared by software by writing 0</description><value>0</value></enumeratedValue></enumeratedValues> 13659 </field> 13660 <field> 13661 <name>TAMP1F</name> 13662 <description>Tamper detection flag</description> 13663 <bitOffset>13</bitOffset> 13664 <bitWidth>1</bitWidth> 13665 <access>read-write</access> 13666 <enumeratedValues><name>TAMP1FR</name><usage>read</usage><enumeratedValue><name>Tampered</name><description>This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input</description><value>1</value></enumeratedValue></enumeratedValues> 13667 <enumeratedValues><name>TAMP1FW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Flag cleared by software writing 0</description><value>0</value></enumeratedValue></enumeratedValues> 13668 </field> 13669 <field> 13670 <name>TAMP2F</name> 13671 <description>TAMPER2 detection flag</description> 13672 <bitOffset>14</bitOffset> 13673 <bitWidth>1</bitWidth> 13674 <access>read-write</access> 13675 <enumeratedValues derivedFrom="TAMP1FR"/> 13676 <enumeratedValues derivedFrom="TAMP1FW"/> 13677 </field> 13678 <field> 13679 <name>RECALPF</name> 13680 <description>Recalibration pending Flag</description> 13681 <bitOffset>16</bitOffset> 13682 <bitWidth>1</bitWidth> 13683 <access>read-only</access> 13684 <enumeratedValues><name>RECALPFR</name><usage>read</usage><enumeratedValue><name>Pending</name><description>The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0</description><value>1</value></enumeratedValue></enumeratedValues> 13685 </field> 13686 </fields> 13687 </register> 13688 <register> 13689 <name>PRER</name> 13690 <displayName>PRER</displayName> 13691 <description>prescaler register</description> 13692 <addressOffset>0x10</addressOffset> 13693 <size>0x20</size> 13694 <access>read-write</access> 13695 <resetValue>0x007F00FF</resetValue> 13696 <fields> 13697 <field> 13698 <name>PREDIV_A</name> 13699 <description>Asynchronous prescaler 13700 factor</description> 13701 <bitOffset>16</bitOffset> 13702 <bitWidth>7</bitWidth> 13703 <writeConstraint><range><minimum>0</minimum><maximum>127</maximum></range></writeConstraint> 13704 </field> 13705 <field> 13706 <name>PREDIV_S</name> 13707 <description>Synchronous prescaler 13708 factor</description> 13709 <bitOffset>0</bitOffset> 13710 <bitWidth>15</bitWidth> 13711 <writeConstraint><range><minimum>0</minimum><maximum>32767</maximum></range></writeConstraint> 13712 </field> 13713 </fields> 13714 </register> 13715 <register> 13716 <name>WUTR</name> 13717 <displayName>WUTR</displayName> 13718 <description>wakeup timer register</description> 13719 <addressOffset>0x14</addressOffset> 13720 <size>0x20</size> 13721 <access>read-write</access> 13722 <resetValue>0x0000FFFF</resetValue> 13723 <fields> 13724 <field> 13725 <name>WUT</name> 13726 <description>Wakeup auto-reload value 13727 bits</description> 13728 <bitOffset>0</bitOffset> 13729 <bitWidth>16</bitWidth> 13730 <writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint> 13731 </field> 13732 </fields> 13733 </register> 13734 <register> 13735 <name>CALIBR</name> 13736 <displayName>CALIBR</displayName> 13737 <description>calibration register</description> 13738 <addressOffset>0x18</addressOffset> 13739 <size>0x20</size> 13740 <access>read-write</access> 13741 <resetValue>0x00000000</resetValue> 13742 <fields> 13743 <field> 13744 <name>DCS</name> 13745 <description>Digital calibration sign</description> 13746 <bitOffset>7</bitOffset> 13747 <bitWidth>1</bitWidth> 13748 </field> 13749 <field> 13750 <name>DC</name> 13751 <description>Digital calibration</description> 13752 <bitOffset>0</bitOffset> 13753 <bitWidth>5</bitWidth> 13754 </field> 13755 </fields> 13756 </register> 13757 <register> 13758 <name>ALRMAR</name> 13759 <displayName>ALRMAR</displayName> 13760 <description>alarm A register</description> 13761 <addressOffset>0x1C</addressOffset> 13762 <size>0x20</size> 13763 <access>read-write</access> 13764 <resetValue>0x00000000</resetValue> 13765 <fields> 13766 <field> 13767 <name>MSK4</name> 13768 <description>Alarm A date mask</description> 13769 <bitOffset>31</bitOffset> 13770 <bitWidth>1</bitWidth> 13771 <enumeratedValues derivedFrom="MSK1"/> 13772 </field> 13773 <field> 13774 <name>WDSEL</name> 13775 <description>Week day selection</description> 13776 <bitOffset>30</bitOffset> 13777 <bitWidth>1</bitWidth> 13778 <enumeratedValues><name>WDSEL</name><usage>read-write</usage><enumeratedValue><name>DateUnits</name><description>DU[3:0] represents the date units</description><value>0</value></enumeratedValue><enumeratedValue><name>WeekDay</name><description>DU[3:0] represents the week day. DT[1:0] is don’t care.</description><value>1</value></enumeratedValue></enumeratedValues> 13779 </field> 13780 <field> 13781 <name>DT</name> 13782 <description>Date tens in BCD format</description> 13783 <bitOffset>28</bitOffset> 13784 <bitWidth>2</bitWidth> 13785 <writeConstraint><range><minimum>0</minimum><maximum>3</maximum></range></writeConstraint> 13786 </field> 13787 <field> 13788 <name>DU</name> 13789 <description>Date units or day in BCD 13790 format</description> 13791 <bitOffset>24</bitOffset> 13792 <bitWidth>4</bitWidth> 13793 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 13794 </field> 13795 <field> 13796 <name>MSK3</name> 13797 <description>Alarm A hours mask</description> 13798 <bitOffset>23</bitOffset> 13799 <bitWidth>1</bitWidth> 13800 <enumeratedValues derivedFrom="MSK1"/> 13801 </field> 13802 <field> 13803 <name>PM</name> 13804 <description>AM/PM notation</description> 13805 <bitOffset>22</bitOffset> 13806 <bitWidth>1</bitWidth> 13807 <enumeratedValues><name>PM</name><usage>read-write</usage><enumeratedValue><name>AM</name><description>AM or 24-hour format</description><value>0</value></enumeratedValue><enumeratedValue><name>PM</name><description>PM</description><value>1</value></enumeratedValue></enumeratedValues> 13808 </field> 13809 <field> 13810 <name>HT</name> 13811 <description>Hour tens in BCD format</description> 13812 <bitOffset>20</bitOffset> 13813 <bitWidth>2</bitWidth> 13814 <writeConstraint><range><minimum>0</minimum><maximum>3</maximum></range></writeConstraint> 13815 </field> 13816 <field> 13817 <name>HU</name> 13818 <description>Hour units in BCD format</description> 13819 <bitOffset>16</bitOffset> 13820 <bitWidth>4</bitWidth> 13821 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 13822 </field> 13823 <field> 13824 <name>MSK2</name> 13825 <description>Alarm A minutes mask</description> 13826 <bitOffset>15</bitOffset> 13827 <bitWidth>1</bitWidth> 13828 <enumeratedValues derivedFrom="MSK1"/> 13829 </field> 13830 <field> 13831 <name>MNT</name> 13832 <description>Minute tens in BCD format</description> 13833 <bitOffset>12</bitOffset> 13834 <bitWidth>3</bitWidth> 13835 <writeConstraint><range><minimum>0</minimum><maximum>7</maximum></range></writeConstraint> 13836 </field> 13837 <field> 13838 <name>MNU</name> 13839 <description>Minute units in BCD format</description> 13840 <bitOffset>8</bitOffset> 13841 <bitWidth>4</bitWidth> 13842 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 13843 </field> 13844 <field> 13845 <name>MSK1</name> 13846 <description>Alarm A seconds mask</description> 13847 <bitOffset>7</bitOffset> 13848 <bitWidth>1</bitWidth> 13849 <enumeratedValues><name>MSK1</name><usage>read-write</usage><enumeratedValue><name>Mask</name><description>Alarm set if the date/day match</description><value>0</value></enumeratedValue><enumeratedValue><name>NotMask</name><description>Date/day don’t care in Alarm comparison</description><value>1</value></enumeratedValue></enumeratedValues> 13850 </field> 13851 <field> 13852 <name>ST</name> 13853 <description>Second tens in BCD format</description> 13854 <bitOffset>4</bitOffset> 13855 <bitWidth>3</bitWidth> 13856 <writeConstraint><range><minimum>0</minimum><maximum>7</maximum></range></writeConstraint> 13857 </field> 13858 <field> 13859 <name>SU</name> 13860 <description>Second units in BCD format</description> 13861 <bitOffset>0</bitOffset> 13862 <bitWidth>4</bitWidth> 13863 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 13864 </field> 13865 </fields> 13866 </register> 13867 <register> 13868 <name>ALRMBR</name> 13869 <displayName>ALRMBR</displayName> 13870 <description>alarm B register</description> 13871 <addressOffset>0x20</addressOffset> 13872 <size>0x20</size> 13873 <access>read-write</access> 13874 <resetValue>0x00000000</resetValue> 13875 <fields> 13876 <field> 13877 <name>MSK4</name> 13878 <description>Alarm B date mask</description> 13879 <bitOffset>31</bitOffset> 13880 <bitWidth>1</bitWidth> 13881 <enumeratedValues derivedFrom="MSK1"/> 13882 </field> 13883 <field> 13884 <name>WDSEL</name> 13885 <description>Week day selection</description> 13886 <bitOffset>30</bitOffset> 13887 <bitWidth>1</bitWidth> 13888 <enumeratedValues><name>WDSEL</name><usage>read-write</usage><enumeratedValue><name>DateUnits</name><description>DU[3:0] represents the date units</description><value>0</value></enumeratedValue><enumeratedValue><name>WeekDay</name><description>DU[3:0] represents the week day. DT[1:0] is don’t care.</description><value>1</value></enumeratedValue></enumeratedValues> 13889 </field> 13890 <field> 13891 <name>DT</name> 13892 <description>Date tens in BCD format</description> 13893 <bitOffset>28</bitOffset> 13894 <bitWidth>2</bitWidth> 13895 <writeConstraint><range><minimum>0</minimum><maximum>3</maximum></range></writeConstraint> 13896 </field> 13897 <field> 13898 <name>DU</name> 13899 <description>Date units or day in BCD 13900 format</description> 13901 <bitOffset>24</bitOffset> 13902 <bitWidth>4</bitWidth> 13903 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 13904 </field> 13905 <field> 13906 <name>MSK3</name> 13907 <description>Alarm B hours mask</description> 13908 <bitOffset>23</bitOffset> 13909 <bitWidth>1</bitWidth> 13910 <enumeratedValues derivedFrom="MSK1"/> 13911 </field> 13912 <field> 13913 <name>PM</name> 13914 <description>AM/PM notation</description> 13915 <bitOffset>22</bitOffset> 13916 <bitWidth>1</bitWidth> 13917 <enumeratedValues><name>PM</name><usage>read-write</usage><enumeratedValue><name>AM</name><description>AM or 24-hour format</description><value>0</value></enumeratedValue><enumeratedValue><name>PM</name><description>PM</description><value>1</value></enumeratedValue></enumeratedValues> 13918 </field> 13919 <field> 13920 <name>HT</name> 13921 <description>Hour tens in BCD format</description> 13922 <bitOffset>20</bitOffset> 13923 <bitWidth>2</bitWidth> 13924 <writeConstraint><range><minimum>0</minimum><maximum>3</maximum></range></writeConstraint> 13925 </field> 13926 <field> 13927 <name>HU</name> 13928 <description>Hour units in BCD format</description> 13929 <bitOffset>16</bitOffset> 13930 <bitWidth>4</bitWidth> 13931 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 13932 </field> 13933 <field> 13934 <name>MSK2</name> 13935 <description>Alarm B minutes mask</description> 13936 <bitOffset>15</bitOffset> 13937 <bitWidth>1</bitWidth> 13938 <enumeratedValues derivedFrom="MSK1"/> 13939 </field> 13940 <field> 13941 <name>MNT</name> 13942 <description>Minute tens in BCD format</description> 13943 <bitOffset>12</bitOffset> 13944 <bitWidth>3</bitWidth> 13945 <writeConstraint><range><minimum>0</minimum><maximum>7</maximum></range></writeConstraint> 13946 </field> 13947 <field> 13948 <name>MNU</name> 13949 <description>Minute units in BCD format</description> 13950 <bitOffset>8</bitOffset> 13951 <bitWidth>4</bitWidth> 13952 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 13953 </field> 13954 <field> 13955 <name>MSK1</name> 13956 <description>Alarm B seconds mask</description> 13957 <bitOffset>7</bitOffset> 13958 <bitWidth>1</bitWidth> 13959 <enumeratedValues><name>MSK1</name><usage>read-write</usage><enumeratedValue><name>Mask</name><description>Alarm set if the date/day match</description><value>0</value></enumeratedValue><enumeratedValue><name>NotMask</name><description>Date/day don’t care in Alarm comparison</description><value>1</value></enumeratedValue></enumeratedValues> 13960 </field> 13961 <field> 13962 <name>ST</name> 13963 <description>Second tens in BCD format</description> 13964 <bitOffset>4</bitOffset> 13965 <bitWidth>3</bitWidth> 13966 <writeConstraint><range><minimum>0</minimum><maximum>7</maximum></range></writeConstraint> 13967 </field> 13968 <field> 13969 <name>SU</name> 13970 <description>Second units in BCD format</description> 13971 <bitOffset>0</bitOffset> 13972 <bitWidth>4</bitWidth> 13973 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 13974 </field> 13975 </fields> 13976 </register> 13977 <register> 13978 <name>WPR</name> 13979 <displayName>WPR</displayName> 13980 <description>write protection register</description> 13981 <addressOffset>0x24</addressOffset> 13982 <size>0x20</size> 13983 <access>write-only</access> 13984 <resetValue>0x00000000</resetValue> 13985 <fields> 13986 <field> 13987 <name>KEY</name> 13988 <description>Write protection key</description> 13989 <bitOffset>0</bitOffset> 13990 <bitWidth>8</bitWidth> 13991 <writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint> 13992 </field> 13993 </fields> 13994 </register> 13995 <register> 13996 <name>SSR</name> 13997 <displayName>SSR</displayName> 13998 <description>sub second register</description> 13999 <addressOffset>0x28</addressOffset> 14000 <size>0x20</size> 14001 <access>read-only</access> 14002 <resetValue>0x00000000</resetValue> 14003 <fields> 14004 <field> 14005 <name>SS</name> 14006 <description>Sub second value</description> 14007 <bitOffset>0</bitOffset> 14008 <bitWidth>16</bitWidth> 14009 <writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint> 14010 </field> 14011 </fields> 14012 </register> 14013 <register> 14014 <name>SHIFTR</name> 14015 <displayName>SHIFTR</displayName> 14016 <description>shift control register</description> 14017 <addressOffset>0x2C</addressOffset> 14018 <size>0x20</size> 14019 <access>write-only</access> 14020 <resetValue>0x00000000</resetValue> 14021 <fields> 14022 <field> 14023 <name>ADD1S</name> 14024 <description>Add one second</description> 14025 <bitOffset>31</bitOffset> 14026 <bitWidth>1</bitWidth> 14027 <enumeratedValues><name>ADD1SW</name><usage>write</usage><enumeratedValue><name>Add1</name><description>Add one second to the clock/calendar</description><value>1</value></enumeratedValue></enumeratedValues> 14028 </field> 14029 <field> 14030 <name>SUBFS</name> 14031 <description>Subtract a fraction of a 14032 second</description> 14033 <bitOffset>0</bitOffset> 14034 <bitWidth>15</bitWidth> 14035 <writeConstraint><range><minimum>0</minimum><maximum>32767</maximum></range></writeConstraint> 14036 </field> 14037 </fields> 14038 </register> 14039 <register> 14040 <name>TSTR</name> 14041 <displayName>TSTR</displayName> 14042 <description>time stamp time register</description> 14043 <addressOffset>0x30</addressOffset> 14044 <size>0x20</size> 14045 <access>read-only</access> 14046 <resetValue>0x00000000</resetValue> 14047 <fields> 14048 <field> 14049 <name>ALARMOUTTYPE</name> 14050 <description>AFO_ALARM output type</description> 14051 <bitOffset>18</bitOffset> 14052 <bitWidth>1</bitWidth> 14053 </field> 14054 <field> 14055 <name>TSINSEL</name> 14056 <description>TIMESTAMP mapping</description> 14057 <bitOffset>17</bitOffset> 14058 <bitWidth>1</bitWidth> 14059 </field> 14060 <field> 14061 <name>TAMP1INSEL</name> 14062 <description>TAMPER1 mapping</description> 14063 <bitOffset>16</bitOffset> 14064 <bitWidth>1</bitWidth> 14065 </field> 14066 <field> 14067 <name>TAMPIE</name> 14068 <description>Tamper interrupt enable</description> 14069 <bitOffset>2</bitOffset> 14070 <bitWidth>1</bitWidth> 14071 </field> 14072 <field> 14073 <name>TAMP1TRG</name> 14074 <description>Active level for tamper 1</description> 14075 <bitOffset>1</bitOffset> 14076 <bitWidth>1</bitWidth> 14077 </field> 14078 <field> 14079 <name>TAMP1E</name> 14080 <description>Tamper 1 detection enable</description> 14081 <bitOffset>0</bitOffset> 14082 <bitWidth>1</bitWidth> 14083 </field> 14084 </fields> 14085 </register> 14086 <register> 14087 <name>TSDR</name> 14088 <displayName>TSDR</displayName> 14089 <description>time stamp date register</description> 14090 <addressOffset>0x34</addressOffset> 14091 <size>0x20</size> 14092 <access>read-only</access> 14093 <resetValue>0x00000000</resetValue> 14094 <fields> 14095 <field> 14096 <name>WDU</name> 14097 <description>Week day units</description> 14098 <bitOffset>13</bitOffset> 14099 <bitWidth>3</bitWidth> 14100 </field> 14101 <field> 14102 <name>MT</name> 14103 <description>Month tens in BCD format</description> 14104 <bitOffset>12</bitOffset> 14105 <bitWidth>1</bitWidth> 14106 </field> 14107 <field> 14108 <name>MU</name> 14109 <description>Month units in BCD format</description> 14110 <bitOffset>8</bitOffset> 14111 <bitWidth>4</bitWidth> 14112 </field> 14113 <field> 14114 <name>DT</name> 14115 <description>Date tens in BCD format</description> 14116 <bitOffset>4</bitOffset> 14117 <bitWidth>2</bitWidth> 14118 </field> 14119 <field> 14120 <name>DU</name> 14121 <description>Date units in BCD format</description> 14122 <bitOffset>0</bitOffset> 14123 <bitWidth>4</bitWidth> 14124 </field> 14125 </fields> 14126 </register> 14127 <register> 14128 <name>TSSSR</name> 14129 <displayName>TSSSR</displayName> 14130 <description>timestamp sub second register</description> 14131 <addressOffset>0x38</addressOffset> 14132 <size>0x20</size> 14133 <access>read-only</access> 14134 <resetValue>0x00000000</resetValue> 14135 <fields> 14136 <field> 14137 <name>SS</name> 14138 <description>Sub second value</description> 14139 <bitOffset>0</bitOffset> 14140 <bitWidth>16</bitWidth> 14141 </field> 14142 </fields> 14143 </register> 14144 <register> 14145 <name>CALR</name> 14146 <displayName>CALR</displayName> 14147 <description>calibration register</description> 14148 <addressOffset>0x3C</addressOffset> 14149 <size>0x20</size> 14150 <access>read-write</access> 14151 <resetValue>0x00000000</resetValue> 14152 <fields> 14153 <field> 14154 <name>CALP</name> 14155 <description>Increase frequency of RTC by 488.5 14156 ppm</description> 14157 <bitOffset>15</bitOffset> 14158 <bitWidth>1</bitWidth> 14159 <enumeratedValues><name>CALP</name><usage>read-write</usage><enumeratedValue><name>NoChange</name><description>No RTCCLK pulses are added</description><value>0</value></enumeratedValue><enumeratedValue><name>IncreaseFreq</name><description>One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm)</description><value>1</value></enumeratedValue></enumeratedValues> 14160 </field> 14161 <field> 14162 <name>CALW8</name> 14163 <description>Use an 8-second calibration cycle 14164 period</description> 14165 <bitOffset>14</bitOffset> 14166 <bitWidth>1</bitWidth> 14167 <enumeratedValues><name>CALW8</name><usage>read-write</usage><enumeratedValue><name>Eight_Second</name><description>When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected</description><value>1</value></enumeratedValue></enumeratedValues> 14168 </field> 14169 <field> 14170 <name>CALW16</name> 14171 <description>Use a 16-second calibration cycle 14172 period</description> 14173 <bitOffset>13</bitOffset> 14174 <bitWidth>1</bitWidth> 14175 <enumeratedValues><name>CALW16</name><usage>read-write</usage><enumeratedValue><name>Sixteen_Second</name><description>When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1</description><value>1</value></enumeratedValue></enumeratedValues> 14176 </field> 14177 <field> 14178 <name>CALM</name> 14179 <description>Calibration minus</description> 14180 <bitOffset>0</bitOffset> 14181 <bitWidth>9</bitWidth> 14182 <writeConstraint><range><minimum>0</minimum><maximum>511</maximum></range></writeConstraint> 14183 </field> 14184 </fields> 14185 </register> 14186 <register> 14187 <name>TAFCR</name> 14188 <displayName>TAFCR</displayName> 14189 <description>tamper and alternate function configuration 14190 register</description> 14191 <addressOffset>0x40</addressOffset> 14192 <size>0x20</size> 14193 <access>read-write</access> 14194 <resetValue>0x00000000</resetValue> 14195 <fields> 14196 <field> 14197 <name>ALARMOUTTYPE</name> 14198 <description>AFO_ALARM output type</description> 14199 <bitOffset>18</bitOffset> 14200 <bitWidth>1</bitWidth> 14201 </field> 14202 <field> 14203 <name>TSINSEL</name> 14204 <description>TIMESTAMP mapping</description> 14205 <bitOffset>17</bitOffset> 14206 <bitWidth>1</bitWidth> 14207 </field> 14208 <field> 14209 <name>TAMP1INSEL</name> 14210 <description>TAMPER1 mapping</description> 14211 <bitOffset>16</bitOffset> 14212 <bitWidth>1</bitWidth> 14213 </field> 14214 <field> 14215 <name>TAMPPUDIS</name> 14216 <description>TAMPER pull-up disable</description> 14217 <bitOffset>15</bitOffset> 14218 <bitWidth>1</bitWidth> 14219 </field> 14220 <field> 14221 <name>TAMPPRCH</name> 14222 <description>Tamper precharge duration</description> 14223 <bitOffset>13</bitOffset> 14224 <bitWidth>2</bitWidth> 14225 </field> 14226 <field> 14227 <name>TAMPFLT</name> 14228 <description>Tamper filter count</description> 14229 <bitOffset>11</bitOffset> 14230 <bitWidth>2</bitWidth> 14231 </field> 14232 <field> 14233 <name>TAMPFREQ</name> 14234 <description>Tamper sampling frequency</description> 14235 <bitOffset>8</bitOffset> 14236 <bitWidth>3</bitWidth> 14237 </field> 14238 <field> 14239 <name>TAMPTS</name> 14240 <description>Activate timestamp on tamper detection 14241 event</description> 14242 <bitOffset>7</bitOffset> 14243 <bitWidth>1</bitWidth> 14244 </field> 14245 <field> 14246 <name>TAMP2TRG</name> 14247 <description>Active level for tamper 2</description> 14248 <bitOffset>4</bitOffset> 14249 <bitWidth>1</bitWidth> 14250 </field> 14251 <field> 14252 <name>TAMP2E</name> 14253 <description>Tamper 2 detection enable</description> 14254 <bitOffset>3</bitOffset> 14255 <bitWidth>1</bitWidth> 14256 </field> 14257 <field> 14258 <name>TAMPIE</name> 14259 <description>Tamper interrupt enable</description> 14260 <bitOffset>2</bitOffset> 14261 <bitWidth>1</bitWidth> 14262 </field> 14263 <field> 14264 <name>TAMP1TRG</name> 14265 <description>Active level for tamper 1</description> 14266 <bitOffset>1</bitOffset> 14267 <bitWidth>1</bitWidth> 14268 </field> 14269 <field> 14270 <name>TAMP1E</name> 14271 <description>Tamper 1 detection enable</description> 14272 <bitOffset>0</bitOffset> 14273 <bitWidth>1</bitWidth> 14274 </field> 14275 </fields> 14276 </register> 14277 <register> 14278 <name>ALRMASSR</name> 14279 <displayName>ALRMASSR</displayName> 14280 <description>alarm A sub second register</description> 14281 <addressOffset>0x44</addressOffset> 14282 <size>0x20</size> 14283 <access>read-write</access> 14284 <resetValue>0x00000000</resetValue> 14285 <fields> 14286 <field> 14287 <name>MASKSS</name> 14288 <description>Mask the most-significant bits starting 14289 at this bit</description> 14290 <bitOffset>24</bitOffset> 14291 <bitWidth>4</bitWidth> 14292 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 14293 </field> 14294 <field> 14295 <name>SS</name> 14296 <description>Sub seconds value</description> 14297 <bitOffset>0</bitOffset> 14298 <bitWidth>15</bitWidth> 14299 <writeConstraint><range><minimum>0</minimum><maximum>32767</maximum></range></writeConstraint> 14300 </field> 14301 </fields> 14302 </register> 14303 <register> 14304 <name>ALRMBSSR</name> 14305 <displayName>ALRMBSSR</displayName> 14306 <description>alarm B sub second register</description> 14307 <addressOffset>0x48</addressOffset> 14308 <size>0x20</size> 14309 <access>read-write</access> 14310 <resetValue>0x00000000</resetValue> 14311 <fields> 14312 <field> 14313 <name>MASKSS</name> 14314 <description>Mask the most-significant bits starting 14315 at this bit</description> 14316 <bitOffset>24</bitOffset> 14317 <bitWidth>4</bitWidth> 14318 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 14319 </field> 14320 <field> 14321 <name>SS</name> 14322 <description>Sub seconds value</description> 14323 <bitOffset>0</bitOffset> 14324 <bitWidth>15</bitWidth> 14325 <writeConstraint><range><minimum>0</minimum><maximum>32767</maximum></range></writeConstraint> 14326 </field> 14327 </fields> 14328 </register> 14329 <register> 14330 <dim>20</dim><dimIncrement>0x4</dimIncrement><dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19</dimIndex><name>BKP%sR</name> 14331 <displayName>BKP0R</displayName> 14332 <description>backup register</description> 14333 <addressOffset>0x50</addressOffset> 14334 <size>0x20</size> 14335 <access>read-write</access> 14336 <resetValue>0x00000000</resetValue> 14337 <fields> 14338 <field> 14339 <name>BKP</name> 14340 <description>BKP</description> 14341 <bitOffset>0</bitOffset> 14342 <bitWidth>32</bitWidth> 14343 <writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint> 14344 </field> 14345 </fields> 14346 </register> 14347 </registers> 14348 </peripheral> 14349 <peripheral> 14350 <name>UART4</name> 14351 <description>Universal synchronous asynchronous receiver 14352 transmitter</description> 14353 <groupName>USART</groupName> 14354 <baseAddress>0x40004C00</baseAddress> 14355 <addressBlock> 14356 <offset>0x0</offset> 14357 <size>0x400</size> 14358 <usage>registers</usage> 14359 </addressBlock> 14360 <interrupt> 14361 <name>UART4</name> 14362 <description>UART4 global interrupt</description> 14363 <value>52</value> 14364 </interrupt> 14365 <registers> 14366 <register> 14367 <name>SR</name> 14368 <displayName>SR</displayName> 14369 <description>Status register</description> 14370 <addressOffset>0x0</addressOffset> 14371 <size>0x20</size> 14372 <resetValue>0x00C00000</resetValue> 14373 <fields> 14374 <field> 14375 <name>LBD</name> 14376 <description>LIN break detection flag</description> 14377 <bitOffset>8</bitOffset> 14378 <bitWidth>1</bitWidth> 14379 <access>read-write</access> 14380 </field> 14381 <field> 14382 <name>TXE</name> 14383 <description>Transmit data register 14384 empty</description> 14385 <bitOffset>7</bitOffset> 14386 <bitWidth>1</bitWidth> 14387 <access>read-only</access> 14388 </field> 14389 <field> 14390 <name>TC</name> 14391 <description>Transmission complete</description> 14392 <bitOffset>6</bitOffset> 14393 <bitWidth>1</bitWidth> 14394 <access>read-write</access> 14395 </field> 14396 <field> 14397 <name>RXNE</name> 14398 <description>Read data register not 14399 empty</description> 14400 <bitOffset>5</bitOffset> 14401 <bitWidth>1</bitWidth> 14402 <access>read-write</access> 14403 </field> 14404 <field> 14405 <name>IDLE</name> 14406 <description>IDLE line detected</description> 14407 <bitOffset>4</bitOffset> 14408 <bitWidth>1</bitWidth> 14409 <access>read-only</access> 14410 </field> 14411 <field> 14412 <name>ORE</name> 14413 <description>Overrun error</description> 14414 <bitOffset>3</bitOffset> 14415 <bitWidth>1</bitWidth> 14416 <access>read-only</access> 14417 </field> 14418 <field> 14419 <name>NF</name> 14420 <description>Noise detected flag</description> 14421 <bitOffset>2</bitOffset> 14422 <bitWidth>1</bitWidth> 14423 <access>read-only</access> 14424 </field> 14425 <field> 14426 <name>FE</name> 14427 <description>Framing error</description> 14428 <bitOffset>1</bitOffset> 14429 <bitWidth>1</bitWidth> 14430 <access>read-only</access> 14431 </field> 14432 <field> 14433 <name>PE</name> 14434 <description>Parity error</description> 14435 <bitOffset>0</bitOffset> 14436 <bitWidth>1</bitWidth> 14437 <access>read-only</access> 14438 </field> 14439 </fields> 14440 </register> 14441 <register> 14442 <name>DR</name> 14443 <displayName>DR</displayName> 14444 <description>Data register</description> 14445 <addressOffset>0x4</addressOffset> 14446 <size>0x20</size> 14447 <access>read-write</access> 14448 <resetValue>0x00000000</resetValue> 14449 <fields> 14450 <field> 14451 <name>DR</name> 14452 <description>Data value</description> 14453 <bitOffset>0</bitOffset> 14454 <bitWidth>9</bitWidth> 14455 <writeConstraint><range><minimum>0</minimum><maximum>511</maximum></range></writeConstraint> 14456 </field> 14457 </fields> 14458 </register> 14459 <register> 14460 <name>BRR</name> 14461 <displayName>BRR</displayName> 14462 <description>Baud rate register</description> 14463 <addressOffset>0x8</addressOffset> 14464 <size>0x20</size> 14465 <access>read-write</access> 14466 <resetValue>0x0000</resetValue> 14467 <fields> 14468 <field> 14469 <name>DIV_Mantissa</name> 14470 <description>mantissa of USARTDIV</description> 14471 <bitOffset>4</bitOffset> 14472 <bitWidth>12</bitWidth> 14473 <writeConstraint><range><minimum>0</minimum><maximum>4095</maximum></range></writeConstraint> 14474 </field> 14475 <field> 14476 <name>DIV_Fraction</name> 14477 <description>fraction of USARTDIV</description> 14478 <bitOffset>0</bitOffset> 14479 <bitWidth>4</bitWidth> 14480 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 14481 </field> 14482 </fields> 14483 </register> 14484 <register> 14485 <name>CR1</name> 14486 <displayName>CR1</displayName> 14487 <description>Control register 1</description> 14488 <addressOffset>0xC</addressOffset> 14489 <size>0x20</size> 14490 <access>read-write</access> 14491 <resetValue>0x0000</resetValue> 14492 <fields> 14493 <field> 14494 <name>OVER8</name> 14495 <description>Oversampling mode</description> 14496 <bitOffset>15</bitOffset> 14497 <bitWidth>1</bitWidth> 14498 <enumeratedValues><name>OVER8</name><usage>read-write</usage><enumeratedValue><name>Oversample16</name><description>Oversampling by 16</description><value>0</value></enumeratedValue><enumeratedValue><name>Oversample8</name><description>Oversampling by 8</description><value>1</value></enumeratedValue></enumeratedValues> 14499 </field> 14500 <field> 14501 <name>UE</name> 14502 <description>USART enable</description> 14503 <bitOffset>13</bitOffset> 14504 <bitWidth>1</bitWidth> 14505 <enumeratedValues><name>UE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>USART prescaler and outputs disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>USART enabled</description><value>1</value></enumeratedValue></enumeratedValues> 14506 </field> 14507 <field> 14508 <name>M</name> 14509 <description>Word length</description> 14510 <bitOffset>12</bitOffset> 14511 <bitWidth>1</bitWidth> 14512 <enumeratedValues><name>M</name><usage>read-write</usage><enumeratedValue><name>M8</name><description>8 data bits</description><value>0</value></enumeratedValue><enumeratedValue><name>M9</name><description>9 data bits</description><value>1</value></enumeratedValue></enumeratedValues> 14513 </field> 14514 <field> 14515 <name>WAKE</name> 14516 <description>Wakeup method</description> 14517 <bitOffset>11</bitOffset> 14518 <bitWidth>1</bitWidth> 14519 <enumeratedValues><name>WAKE</name><usage>read-write</usage><enumeratedValue><name>IdleLine</name><description>USART wakeup on idle line</description><value>0</value></enumeratedValue><enumeratedValue><name>AddressMark</name><description>USART wakeup on address mark</description><value>1</value></enumeratedValue></enumeratedValues> 14520 </field> 14521 <field> 14522 <name>PCE</name> 14523 <description>Parity control enable</description> 14524 <bitOffset>10</bitOffset> 14525 <bitWidth>1</bitWidth> 14526 <enumeratedValues><name>PCE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Parity control disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Parity control enabled</description><value>1</value></enumeratedValue></enumeratedValues> 14527 </field> 14528 <field> 14529 <name>PS</name> 14530 <description>Parity selection</description> 14531 <bitOffset>9</bitOffset> 14532 <bitWidth>1</bitWidth> 14533 <enumeratedValues><name>PS</name><usage>read-write</usage><enumeratedValue><name>Even</name><description>Even parity</description><value>0</value></enumeratedValue><enumeratedValue><name>Odd</name><description>Odd parity</description><value>1</value></enumeratedValue></enumeratedValues> 14534 </field> 14535 <field> 14536 <name>PEIE</name> 14537 <description>PE interrupt enable</description> 14538 <bitOffset>8</bitOffset> 14539 <bitWidth>1</bitWidth> 14540 <enumeratedValues><name>PEIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>PE interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>PE interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 14541 </field> 14542 <field> 14543 <name>TXEIE</name> 14544 <description>TXE interrupt enable</description> 14545 <bitOffset>7</bitOffset> 14546 <bitWidth>1</bitWidth> 14547 <enumeratedValues><name>TXEIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>TXE interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>TXE interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 14548 </field> 14549 <field> 14550 <name>TCIE</name> 14551 <description>Transmission complete interrupt 14552 enable</description> 14553 <bitOffset>6</bitOffset> 14554 <bitWidth>1</bitWidth> 14555 <enumeratedValues><name>TCIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>TC interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>TC interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 14556 </field> 14557 <field> 14558 <name>RXNEIE</name> 14559 <description>RXNE interrupt enable</description> 14560 <bitOffset>5</bitOffset> 14561 <bitWidth>1</bitWidth> 14562 <enumeratedValues><name>RXNEIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>RXNE interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>RXNE interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 14563 </field> 14564 <field> 14565 <name>IDLEIE</name> 14566 <description>IDLE interrupt enable</description> 14567 <bitOffset>4</bitOffset> 14568 <bitWidth>1</bitWidth> 14569 <enumeratedValues><name>IDLEIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>IDLE interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>IDLE interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 14570 </field> 14571 <field> 14572 <name>TE</name> 14573 <description>Transmitter enable</description> 14574 <bitOffset>3</bitOffset> 14575 <bitWidth>1</bitWidth> 14576 <enumeratedValues><name>TE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Transmitter disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Transmitter enabled</description><value>1</value></enumeratedValue></enumeratedValues> 14577 </field> 14578 <field> 14579 <name>RE</name> 14580 <description>Receiver enable</description> 14581 <bitOffset>2</bitOffset> 14582 <bitWidth>1</bitWidth> 14583 <enumeratedValues><name>RE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Receiver disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Receiver enabled</description><value>1</value></enumeratedValue></enumeratedValues> 14584 </field> 14585 <field> 14586 <name>RWU</name> 14587 <description>Receiver wakeup</description> 14588 <bitOffset>1</bitOffset> 14589 <bitWidth>1</bitWidth> 14590 <enumeratedValues><name>RWU</name><usage>read-write</usage><enumeratedValue><name>Active</name><description>Receiver in active mode</description><value>0</value></enumeratedValue><enumeratedValue><name>Mute</name><description>Receiver in mute mode</description><value>1</value></enumeratedValue></enumeratedValues> 14591 </field> 14592 <field> 14593 <name>SBK</name> 14594 <description>Send break</description> 14595 <bitOffset>0</bitOffset> 14596 <bitWidth>1</bitWidth> 14597 <enumeratedValues><name>SBK</name><usage>read-write</usage><enumeratedValue><name>NoBreak</name><description>No break character is transmitted</description><value>0</value></enumeratedValue><enumeratedValue><name>Break</name><description>Break character transmitted</description><value>1</value></enumeratedValue></enumeratedValues> 14598 </field> 14599 </fields> 14600 </register> 14601 <register> 14602 <name>CR2</name> 14603 <displayName>CR2</displayName> 14604 <description>Control register 2</description> 14605 <addressOffset>0x10</addressOffset> 14606 <size>0x20</size> 14607 <access>read-write</access> 14608 <resetValue>0x0000</resetValue> 14609 <fields> 14610 <field> 14611 <name>LINEN</name> 14612 <description>LIN mode enable</description> 14613 <bitOffset>14</bitOffset> 14614 <bitWidth>1</bitWidth> 14615 <enumeratedValues><name>LINEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>LIN mode disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>LIN mode enabled</description><value>1</value></enumeratedValue></enumeratedValues> 14616 </field> 14617 <field> 14618 <name>STOP</name> 14619 <description>STOP bits</description> 14620 <bitOffset>12</bitOffset> 14621 <bitWidth>2</bitWidth> 14622 <enumeratedValues><name>STOP</name><usage>read-write</usage><enumeratedValue><name>Stop1</name><description>1 stop bit</description><value>0</value></enumeratedValue><enumeratedValue><name>Stop2</name><description>2 stop bits</description><value>2</value></enumeratedValue></enumeratedValues> 14623 </field> 14624 <field> 14625 <name>LBDIE</name> 14626 <description>LIN break detection interrupt 14627 enable</description> 14628 <bitOffset>6</bitOffset> 14629 <bitWidth>1</bitWidth> 14630 <enumeratedValues><name>LBDIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>LIN break detection interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>LIN break detection interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 14631 </field> 14632 <field> 14633 <name>LBDL</name> 14634 <description>lin break detection length</description> 14635 <bitOffset>5</bitOffset> 14636 <bitWidth>1</bitWidth> 14637 <enumeratedValues><name>LBDL</name><usage>read-write</usage><enumeratedValue><name>LBDL10</name><description>10-bit break detection</description><value>0</value></enumeratedValue><enumeratedValue><name>LBDL11</name><description>11-bit break detection</description><value>1</value></enumeratedValue></enumeratedValues> 14638 </field> 14639 <field> 14640 <name>ADD</name> 14641 <description>Address of the USART node</description> 14642 <bitOffset>0</bitOffset> 14643 <bitWidth>4</bitWidth> 14644 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 14645 </field> 14646 </fields> 14647 </register> 14648 <register> 14649 <name>CR3</name> 14650 <displayName>CR3</displayName> 14651 <description>Control register 3</description> 14652 <addressOffset>0x14</addressOffset> 14653 <size>0x20</size> 14654 <access>read-write</access> 14655 <resetValue>0x0000</resetValue> 14656 <fields> 14657 <field> 14658 <name>ONEBIT</name> 14659 <description>One sample bit method 14660 enable</description> 14661 <bitOffset>11</bitOffset> 14662 <bitWidth>1</bitWidth> 14663 <enumeratedValues><name>ONEBIT</name><usage>read-write</usage><enumeratedValue><name>Sample3</name><description>Three sample bit method</description><value>0</value></enumeratedValue><enumeratedValue><name>Sample1</name><description>One sample bit method</description><value>1</value></enumeratedValue></enumeratedValues> 14664 </field> 14665 <field> 14666 <name>DMAT</name> 14667 <description>DMA enable transmitter</description> 14668 <bitOffset>7</bitOffset> 14669 <bitWidth>1</bitWidth> 14670 <enumeratedValues><name>DMAT</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>DMA mode is disabled for transmission</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>DMA mode is enabled for transmission</description><value>1</value></enumeratedValue></enumeratedValues> 14671 </field> 14672 <field> 14673 <name>DMAR</name> 14674 <description>DMA enable receiver</description> 14675 <bitOffset>6</bitOffset> 14676 <bitWidth>1</bitWidth> 14677 <enumeratedValues><name>DMAR</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>DMA mode is disabled for reception</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>DMA mode is enabled for reception</description><value>1</value></enumeratedValue></enumeratedValues> 14678 </field> 14679 <field> 14680 <name>HDSEL</name> 14681 <description>Half-duplex selection</description> 14682 <bitOffset>3</bitOffset> 14683 <bitWidth>1</bitWidth> 14684 <enumeratedValues><name>HDSEL</name><usage>read-write</usage><enumeratedValue><name>FullDuplex</name><description>Half duplex mode is not selected</description><value>0</value></enumeratedValue><enumeratedValue><name>HalfDuplex</name><description>Half duplex mode is selected</description><value>1</value></enumeratedValue></enumeratedValues> 14685 </field> 14686 <field> 14687 <name>IRLP</name> 14688 <description>IrDA low-power</description> 14689 <bitOffset>2</bitOffset> 14690 <bitWidth>1</bitWidth> 14691 <enumeratedValues><name>IRLP</name><usage>read-write</usage><enumeratedValue><name>Normal</name><description>Normal mode</description><value>0</value></enumeratedValue><enumeratedValue><name>LowPower</name><description>Low-power mode</description><value>1</value></enumeratedValue></enumeratedValues> 14692 </field> 14693 <field> 14694 <name>IREN</name> 14695 <description>IrDA mode enable</description> 14696 <bitOffset>1</bitOffset> 14697 <bitWidth>1</bitWidth> 14698 <enumeratedValues><name>IREN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>IrDA disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>IrDA enabled</description><value>1</value></enumeratedValue></enumeratedValues> 14699 </field> 14700 <field> 14701 <name>EIE</name> 14702 <description>Error interrupt enable</description> 14703 <bitOffset>0</bitOffset> 14704 <bitWidth>1</bitWidth> 14705 <enumeratedValues><name>EIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Error interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Error interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 14706 </field> 14707 </fields> 14708 </register> 14709 </registers> 14710 </peripheral> 14711 <peripheral derivedFrom="UART4"> 14712 <name>UART5</name> 14713 <baseAddress>0x40005000</baseAddress> 14714 <interrupt> 14715 <name>UART5</name> 14716 <description>UART5 global interrupt</description> 14717 <value>53</value> 14718 </interrupt> 14719 </peripheral> 14720 <peripheral derivedFrom="UART4"> 14721 <name>UART7</name> 14722 <baseAddress>0x40007800</baseAddress> 14723 <interrupt> 14724 <name>UART4</name> 14725 <description>UART4 global interrupt</description> 14726 <value>52</value> 14727 </interrupt> 14728 </peripheral> 14729 <peripheral derivedFrom="UART4"> 14730 <name>UART8</name> 14731 <baseAddress>0x40007C00</baseAddress> 14732 <interrupt> 14733 <name>UART5</name> 14734 <description>UART5 global interrupt</description> 14735 <value>53</value> 14736 </interrupt> 14737 </peripheral> 14738 <peripheral> 14739 <name>ADC_Common</name> 14740 <description>Common ADC registers</description> 14741 <groupName>ADC</groupName> 14742 <baseAddress>0x40012300</baseAddress> 14743 <addressBlock> 14744 <offset>0x0</offset> 14745 <size>0x400</size> 14746 <usage>registers</usage> 14747 </addressBlock> 14748 <registers> 14749 <register> 14750 <name>CSR</name> 14751 <displayName>CSR</displayName> 14752 <description>ADC Common status register</description> 14753 <addressOffset>0x0</addressOffset> 14754 <size>0x20</size> 14755 <access>read-only</access> 14756 <resetValue>0x00000000</resetValue> 14757 <fields> 14758 <field> 14759 <name>OVR3</name> 14760 <description>Overrun flag of ADC3</description> 14761 <bitOffset>21</bitOffset> 14762 <bitWidth>1</bitWidth> 14763 <enumeratedValues derivedFrom="OVR1"/> 14764 </field> 14765 <field> 14766 <name>STRT3</name> 14767 <description>Regular channel Start flag of ADC 14768 3</description> 14769 <bitOffset>20</bitOffset> 14770 <bitWidth>1</bitWidth> 14771 <enumeratedValues derivedFrom="STRT1"/> 14772 </field> 14773 <field> 14774 <name>JSTRT3</name> 14775 <description>Injected channel Start flag of ADC 14776 3</description> 14777 <bitOffset>19</bitOffset> 14778 <bitWidth>1</bitWidth> 14779 <enumeratedValues derivedFrom="JSTRT1"/> 14780 </field> 14781 <field> 14782 <name>JEOC3</name> 14783 <description>Injected channel end of conversion of 14784 ADC 3</description> 14785 <bitOffset>18</bitOffset> 14786 <bitWidth>1</bitWidth> 14787 <enumeratedValues derivedFrom="JEOC1"/> 14788 </field> 14789 <field> 14790 <name>EOC3</name> 14791 <description>End of conversion of ADC 3</description> 14792 <bitOffset>17</bitOffset> 14793 <bitWidth>1</bitWidth> 14794 <enumeratedValues derivedFrom="EOC1"/> 14795 </field> 14796 <field> 14797 <name>AWD3</name> 14798 <description>Analog watchdog flag of ADC 14799 3</description> 14800 <bitOffset>16</bitOffset> 14801 <bitWidth>1</bitWidth> 14802 <enumeratedValues derivedFrom="AWD1"/> 14803 </field> 14804 <field> 14805 <name>OVR2</name> 14806 <description>Overrun flag of ADC 2</description> 14807 <bitOffset>13</bitOffset> 14808 <bitWidth>1</bitWidth> 14809 <enumeratedValues derivedFrom="OVR1"/> 14810 </field> 14811 <field> 14812 <name>STRT2</name> 14813 <description>Regular channel Start flag of ADC 14814 2</description> 14815 <bitOffset>12</bitOffset> 14816 <bitWidth>1</bitWidth> 14817 <enumeratedValues derivedFrom="STRT1"/> 14818 </field> 14819 <field> 14820 <name>JSTRT2</name> 14821 <description>Injected channel Start flag of ADC 14822 2</description> 14823 <bitOffset>11</bitOffset> 14824 <bitWidth>1</bitWidth> 14825 <enumeratedValues derivedFrom="JSTRT1"/> 14826 </field> 14827 <field> 14828 <name>JEOC2</name> 14829 <description>Injected channel end of conversion of 14830 ADC 2</description> 14831 <bitOffset>10</bitOffset> 14832 <bitWidth>1</bitWidth> 14833 <enumeratedValues derivedFrom="JEOC1"/> 14834 </field> 14835 <field> 14836 <name>EOC2</name> 14837 <description>End of conversion of ADC 2</description> 14838 <bitOffset>9</bitOffset> 14839 <bitWidth>1</bitWidth> 14840 <enumeratedValues derivedFrom="EOC1"/> 14841 </field> 14842 <field> 14843 <name>AWD2</name> 14844 <description>Analog watchdog flag of ADC 14845 2</description> 14846 <bitOffset>8</bitOffset> 14847 <bitWidth>1</bitWidth> 14848 <enumeratedValues derivedFrom="AWD1"/> 14849 </field> 14850 <field> 14851 <name>OVR1</name> 14852 <description>Overrun flag of ADC 1</description> 14853 <bitOffset>5</bitOffset> 14854 <bitWidth>1</bitWidth> 14855 <enumeratedValues><name>OVR1</name><usage>read-write</usage><enumeratedValue><name>NoOverrun</name><description>No overrun occurred</description><value>0</value></enumeratedValue><enumeratedValue><name>Overrun</name><description>Overrun occurred</description><value>1</value></enumeratedValue></enumeratedValues> 14856 </field> 14857 <field> 14858 <name>STRT1</name> 14859 <description>Regular channel Start flag of ADC 14860 1</description> 14861 <bitOffset>4</bitOffset> 14862 <bitWidth>1</bitWidth> 14863 <enumeratedValues><name>STRT1</name><usage>read-write</usage><enumeratedValue><name>NotStarted</name><description>No regular channel conversion started</description><value>0</value></enumeratedValue><enumeratedValue><name>Started</name><description>Regular channel conversion has started</description><value>1</value></enumeratedValue></enumeratedValues> 14864 </field> 14865 <field> 14866 <name>JSTRT1</name> 14867 <description>Injected channel Start flag of ADC 14868 1</description> 14869 <bitOffset>3</bitOffset> 14870 <bitWidth>1</bitWidth> 14871 <enumeratedValues><name>JSTRT1</name><usage>read-write</usage><enumeratedValue><name>NotStarted</name><description>No injected channel conversion started</description><value>0</value></enumeratedValue><enumeratedValue><name>Started</name><description>Injected channel conversion has started</description><value>1</value></enumeratedValue></enumeratedValues> 14872 </field> 14873 <field> 14874 <name>JEOC1</name> 14875 <description>Injected channel end of conversion of 14876 ADC 1</description> 14877 <bitOffset>2</bitOffset> 14878 <bitWidth>1</bitWidth> 14879 <enumeratedValues><name>JEOC1</name><usage>read-write</usage><enumeratedValue><name>NotComplete</name><description>Conversion is not complete</description><value>0</value></enumeratedValue><enumeratedValue><name>Complete</name><description>Conversion complete</description><value>1</value></enumeratedValue></enumeratedValues> 14880 </field> 14881 <field> 14882 <name>EOC1</name> 14883 <description>End of conversion of ADC 1</description> 14884 <bitOffset>1</bitOffset> 14885 <bitWidth>1</bitWidth> 14886 <enumeratedValues><name>EOC1</name><usage>read-write</usage><enumeratedValue><name>NotComplete</name><description>Conversion is not complete</description><value>0</value></enumeratedValue><enumeratedValue><name>Complete</name><description>Conversion complete</description><value>1</value></enumeratedValue></enumeratedValues> 14887 </field> 14888 <field> 14889 <name>AWD1</name> 14890 <description>Analog watchdog flag of ADC 14891 1</description> 14892 <bitOffset>0</bitOffset> 14893 <bitWidth>1</bitWidth> 14894 <enumeratedValues><name>AWD1</name><usage>read-write</usage><enumeratedValue><name>NoEvent</name><description>No analog watchdog event occurred</description><value>0</value></enumeratedValue><enumeratedValue><name>Event</name><description>Analog watchdog event occurred</description><value>1</value></enumeratedValue></enumeratedValues> 14895 </field> 14896 </fields> 14897 </register> 14898 <register> 14899 <name>CCR</name> 14900 <displayName>CCR</displayName> 14901 <description>ADC common control register</description> 14902 <addressOffset>0x4</addressOffset> 14903 <size>0x20</size> 14904 <access>read-write</access> 14905 <resetValue>0x00000000</resetValue> 14906 <fields> 14907 <field> 14908 <name>TSVREFE</name> 14909 <description>Temperature sensor and VREFINT 14910 enable</description> 14911 <bitOffset>23</bitOffset> 14912 <bitWidth>1</bitWidth> 14913 <enumeratedValues><name>TSVREFE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Temperature sensor and V_REFINT channel disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Temperature sensor and V_REFINT channel enabled</description><value>1</value></enumeratedValue></enumeratedValues> 14914 </field> 14915 <field> 14916 <name>VBATE</name> 14917 <description>VBAT enable</description> 14918 <bitOffset>22</bitOffset> 14919 <bitWidth>1</bitWidth> 14920 <enumeratedValues><name>VBATE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>V_BAT channel disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>V_BAT channel enabled</description><value>1</value></enumeratedValue></enumeratedValues> 14921 </field> 14922 <field> 14923 <name>ADCPRE</name> 14924 <description>ADC prescaler</description> 14925 <bitOffset>16</bitOffset> 14926 <bitWidth>2</bitWidth> 14927 <enumeratedValues><name>ADCPRE</name><usage>read-write</usage><enumeratedValue><name>Div2</name><description>PCLK2 divided by 2</description><value>0</value></enumeratedValue><enumeratedValue><name>Div4</name><description>PCLK2 divided by 4</description><value>1</value></enumeratedValue><enumeratedValue><name>Div6</name><description>PCLK2 divided by 6</description><value>2</value></enumeratedValue><enumeratedValue><name>Div8</name><description>PCLK2 divided by 8</description><value>3</value></enumeratedValue></enumeratedValues> 14928 </field> 14929 <field> 14930 <name>DMA</name> 14931 <description>Direct memory access mode for multi ADC 14932 mode</description> 14933 <bitOffset>14</bitOffset> 14934 <bitWidth>2</bitWidth> 14935 <enumeratedValues><name>DMA</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>DMA mode disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Mode1</name><description>DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)</description><value>1</value></enumeratedValue><enumeratedValue><name>Mode2</name><description>DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)</description><value>2</value></enumeratedValue><enumeratedValue><name>Mode3</name><description>DMA mode 3 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)</description><value>3</value></enumeratedValue></enumeratedValues> 14936 </field> 14937 <field> 14938 <name>DDS</name> 14939 <description>DMA disable selection for multi-ADC 14940 mode</description> 14941 <bitOffset>13</bitOffset> 14942 <bitWidth>1</bitWidth> 14943 <enumeratedValues><name>DDS</name><usage>read-write</usage><enumeratedValue><name>Single</name><description>No new DMA request is issued after the last transfer</description><value>0</value></enumeratedValue><enumeratedValue><name>Continuous</name><description>DMA requests are issued as long as data are converted and DMA=01, 10 or 11</description><value>1</value></enumeratedValue></enumeratedValues> 14944 </field> 14945 <field> 14946 <name>DELAY</name> 14947 <description>Delay between 2 sampling 14948 phases</description> 14949 <bitOffset>8</bitOffset> 14950 <bitWidth>4</bitWidth> 14951 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 14952 </field> 14953 <field> 14954 <name>MULTI</name> 14955 <description>Multi ADC mode selection</description> 14956 <bitOffset>0</bitOffset> 14957 <bitWidth>5</bitWidth> 14958 <enumeratedValues><name>MULTI</name><usage>read-write</usage><enumeratedValue><name>Independent</name><description>All the ADCs independent: independent mode</description><value>0</value></enumeratedValue><enumeratedValue><name>DualRJ</name><description>Dual ADC1 and ADC2, combined regular and injected simultaneous mode</description><value>1</value></enumeratedValue><enumeratedValue><name>DualRA</name><description>Dual ADC1 and ADC2, combined regular and alternate trigger mode</description><value>2</value></enumeratedValue><enumeratedValue><name>DualJ</name><description>Dual ADC1 and ADC2, injected simultaneous mode only</description><value>5</value></enumeratedValue><enumeratedValue><name>DualR</name><description>Dual ADC1 and ADC2, regular simultaneous mode only</description><value>6</value></enumeratedValue><enumeratedValue><name>DualI</name><description>Dual ADC1 and ADC2, interleaved mode only</description><value>7</value></enumeratedValue><enumeratedValue><name>DualA</name><description>Dual ADC1 and ADC2, alternate trigger mode only</description><value>9</value></enumeratedValue><enumeratedValue><name>TripleRJ</name><description>Triple ADC, regular and injected simultaneous mode</description><value>17</value></enumeratedValue><enumeratedValue><name>TripleRA</name><description>Triple ADC, regular and alternate trigger mode</description><value>18</value></enumeratedValue><enumeratedValue><name>TripleJ</name><description>Triple ADC, injected simultaneous mode only</description><value>21</value></enumeratedValue><enumeratedValue><name>TripleR</name><description>Triple ADC, regular simultaneous mode only</description><value>22</value></enumeratedValue><enumeratedValue><name>TripleI</name><description>Triple ADC, interleaved mode only</description><value>23</value></enumeratedValue><enumeratedValue><name>TripleA</name><description>Triple ADC, alternate trigger mode only</description><value>24</value></enumeratedValue></enumeratedValues> 14959 </field> 14960 </fields> 14961 </register> 14962 <register> 14963 <name>CDR</name> 14964 <displayName>CDR</displayName> 14965 <description>ADC common regular data register for dual 14966 and triple modes</description> 14967 <addressOffset>0x8</addressOffset> 14968 <size>0x20</size> 14969 <access>read-only</access> 14970 <resetValue>0x00000000</resetValue> 14971 <fields> 14972 <field> 14973 <name>DATA2</name> 14974 <description>2nd data item of a pair of regular 14975 conversions</description> 14976 <bitOffset>16</bitOffset> 14977 <bitWidth>16</bitWidth> 14978 </field> 14979 <field> 14980 <name>DATA1</name> 14981 <description>1st data item of a pair of regular 14982 conversions</description> 14983 <bitOffset>0</bitOffset> 14984 <bitWidth>16</bitWidth> 14985 </field> 14986 </fields> 14987 </register> 14988 </registers> 14989 </peripheral> 14990 <peripheral> 14991 <name>TIM1</name> 14992 <description>Advanced-timers</description> 14993 <groupName>TIM</groupName> 14994 <baseAddress>0x40010000</baseAddress> 14995 <addressBlock> 14996 <offset>0x0</offset> 14997 <size>0x400</size> 14998 <usage>registers</usage> 14999 </addressBlock> 15000 <interrupt> 15001 <name>TIM1_BRK_TIM9</name> 15002 <description>TIM1 Break interrupt and TIM9 global 15003 interrupt</description> 15004 <value>24</value> 15005 </interrupt> 15006 <interrupt> 15007 <name>TIM1_UP_TIM10</name> 15008 <description>TIM1 Update interrupt and TIM10 global 15009 interrupt</description> 15010 <value>25</value> 15011 </interrupt> 15012 <interrupt> 15013 <name>TIM1_TRG_COM_TIM11</name> 15014 <description>TIM1 Trigger and Commutation interrupts and 15015 TIM11 global interrupt</description> 15016 <value>26</value> 15017 </interrupt> 15018 <interrupt> 15019 <name>TIM1_CC</name> 15020 <description>TIM1 Capture Compare interrupt</description> 15021 <value>27</value> 15022 </interrupt> 15023 <registers> 15024 <register> 15025 <name>CR1</name> 15026 <displayName>CR1</displayName> 15027 <description>control register 1</description> 15028 <addressOffset>0x0</addressOffset> 15029 <size>0x20</size> 15030 <access>read-write</access> 15031 <resetValue>0x0000</resetValue> 15032 <fields> 15033 <field> 15034 <name>CKD</name> 15035 <description>Clock division</description> 15036 <bitOffset>8</bitOffset> 15037 <bitWidth>2</bitWidth> 15038 <enumeratedValues><name>CKD</name><usage>read-write</usage><enumeratedValue><name>Div1</name><description>t_DTS = t_CK_INT</description><value>0</value></enumeratedValue><enumeratedValue><name>Div2</name><description>t_DTS = 2 × t_CK_INT</description><value>1</value></enumeratedValue><enumeratedValue><name>Div4</name><description>t_DTS = 4 × t_CK_INT</description><value>2</value></enumeratedValue></enumeratedValues> 15039 </field> 15040 <field> 15041 <name>ARPE</name> 15042 <description>Auto-reload preload enable</description> 15043 <bitOffset>7</bitOffset> 15044 <bitWidth>1</bitWidth> 15045 <enumeratedValues><name>ARPE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>TIMx_APRR register is not buffered</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>TIMx_APRR register is buffered</description><value>1</value></enumeratedValue></enumeratedValues> 15046 </field> 15047 <field> 15048 <name>CMS</name> 15049 <description>Center-aligned mode 15050 selection</description> 15051 <bitOffset>5</bitOffset> 15052 <bitWidth>2</bitWidth> 15053 <enumeratedValues><name>CMS</name><usage>read-write</usage><enumeratedValue><name>EdgeAligned</name><description>The counter counts up or down depending on the direction bit</description><value>0</value></enumeratedValue><enumeratedValue><name>CenterAligned1</name><description>The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.</description><value>1</value></enumeratedValue><enumeratedValue><name>CenterAligned2</name><description>The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.</description><value>2</value></enumeratedValue><enumeratedValue><name>CenterAligned3</name><description>The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.</description><value>3</value></enumeratedValue></enumeratedValues> 15054 </field> 15055 <field> 15056 <name>DIR</name> 15057 <description>Direction</description> 15058 <bitOffset>4</bitOffset> 15059 <bitWidth>1</bitWidth> 15060 <enumeratedValues><name>DIR</name><usage>read-write</usage><enumeratedValue><name>Up</name><description>Counter used as upcounter</description><value>0</value></enumeratedValue><enumeratedValue><name>Down</name><description>Counter used as downcounter</description><value>1</value></enumeratedValue></enumeratedValues> 15061 </field> 15062 <field> 15063 <name>OPM</name> 15064 <description>One-pulse mode</description> 15065 <bitOffset>3</bitOffset> 15066 <bitWidth>1</bitWidth> 15067 <enumeratedValues><name>OPM</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Counter is not stopped at update event</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Counter stops counting at the next update event (clearing the CEN bit)</description><value>1</value></enumeratedValue></enumeratedValues> 15068 </field> 15069 <field> 15070 <name>URS</name> 15071 <description>Update request source</description> 15072 <bitOffset>2</bitOffset> 15073 <bitWidth>1</bitWidth> 15074 <enumeratedValues><name>URS</name><usage>read-write</usage><enumeratedValue><name>AnyEvent</name><description>Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request</description><value>0</value></enumeratedValue><enumeratedValue><name>CounterOnly</name><description>Only counter overflow/underflow generates an update interrupt or DMA request</description><value>1</value></enumeratedValue></enumeratedValues> 15075 </field> 15076 <field> 15077 <name>UDIS</name> 15078 <description>Update disable</description> 15079 <bitOffset>1</bitOffset> 15080 <bitWidth>1</bitWidth> 15081 <enumeratedValues><name>UDIS</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>Update event enabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>Update event disabled</description><value>1</value></enumeratedValue></enumeratedValues> 15082 </field> 15083 <field> 15084 <name>CEN</name> 15085 <description>Counter enable</description> 15086 <bitOffset>0</bitOffset> 15087 <bitWidth>1</bitWidth> 15088 <enumeratedValues><name>CEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Counter disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Counter enabled</description><value>1</value></enumeratedValue></enumeratedValues> 15089 </field> 15090 </fields> 15091 </register> 15092 <register> 15093 <name>CR2</name> 15094 <displayName>CR2</displayName> 15095 <description>control register 2</description> 15096 <addressOffset>0x4</addressOffset> 15097 <size>0x20</size> 15098 <access>read-write</access> 15099 <resetValue>0x0000</resetValue> 15100 <fields> 15101 <field> 15102 <name>OIS4</name> 15103 <description>Output Idle state 4</description> 15104 <bitOffset>14</bitOffset> 15105 <bitWidth>1</bitWidth> 15106 </field> 15107 <field> 15108 <name>OIS3N</name> 15109 <description>Output Idle state 3</description> 15110 <bitOffset>13</bitOffset> 15111 <bitWidth>1</bitWidth> 15112 </field> 15113 <field> 15114 <name>OIS3</name> 15115 <description>Output Idle state 3</description> 15116 <bitOffset>12</bitOffset> 15117 <bitWidth>1</bitWidth> 15118 </field> 15119 <field> 15120 <name>OIS2N</name> 15121 <description>Output Idle state 2</description> 15122 <bitOffset>11</bitOffset> 15123 <bitWidth>1</bitWidth> 15124 </field> 15125 <field> 15126 <name>OIS2</name> 15127 <description>Output Idle state 2</description> 15128 <bitOffset>10</bitOffset> 15129 <bitWidth>1</bitWidth> 15130 </field> 15131 <field> 15132 <name>OIS1N</name> 15133 <description>Output Idle state 1</description> 15134 <bitOffset>9</bitOffset> 15135 <bitWidth>1</bitWidth> 15136 </field> 15137 <field> 15138 <name>OIS1</name> 15139 <description>Output Idle state 1</description> 15140 <bitOffset>8</bitOffset> 15141 <bitWidth>1</bitWidth> 15142 </field> 15143 <field> 15144 <name>TI1S</name> 15145 <description>TI1 selection</description> 15146 <bitOffset>7</bitOffset> 15147 <bitWidth>1</bitWidth> 15148 <enumeratedValues><name>TI1S</name><usage>read-write</usage><enumeratedValue><name>Normal</name><description>The TIMx_CH1 pin is connected to TI1 input</description><value>0</value></enumeratedValue><enumeratedValue><name>XOR</name><description>The TIMx_CH1, CH2, CH3 pins are connected to TI1 input</description><value>1</value></enumeratedValue></enumeratedValues> 15149 </field> 15150 <field> 15151 <name>MMS</name> 15152 <description>Master mode selection</description> 15153 <bitOffset>4</bitOffset> 15154 <bitWidth>3</bitWidth> 15155 <enumeratedValues><name>MMS</name><usage>read-write</usage><enumeratedValue><name>Reset</name><description>The UG bit from the TIMx_EGR register is used as trigger output</description><value>0</value></enumeratedValue><enumeratedValue><name>Enable</name><description>The counter enable signal, CNT_EN, is used as trigger output</description><value>1</value></enumeratedValue><enumeratedValue><name>Update</name><description>The update event is selected as trigger output</description><value>2</value></enumeratedValue><enumeratedValue><name>ComparePulse</name><description>The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred</description><value>3</value></enumeratedValue><enumeratedValue><name>CompareOC1</name><description>OC1REF signal is used as trigger output</description><value>4</value></enumeratedValue><enumeratedValue><name>CompareOC2</name><description>OC2REF signal is used as trigger output</description><value>5</value></enumeratedValue><enumeratedValue><name>CompareOC3</name><description>OC3REF signal is used as trigger output</description><value>6</value></enumeratedValue><enumeratedValue><name>CompareOC4</name><description>OC4REF signal is used as trigger output</description><value>7</value></enumeratedValue></enumeratedValues> 15156 </field> 15157 <field> 15158 <name>CCDS</name> 15159 <description>Capture/compare DMA 15160 selection</description> 15161 <bitOffset>3</bitOffset> 15162 <bitWidth>1</bitWidth> 15163 <enumeratedValues><name>CCDS</name><usage>read-write</usage><enumeratedValue><name>OnCompare</name><description>CCx DMA request sent when CCx event occurs</description><value>0</value></enumeratedValue><enumeratedValue><name>OnUpdate</name><description>CCx DMA request sent when update event occurs</description><value>1</value></enumeratedValue></enumeratedValues> 15164 </field> 15165 <field> 15166 <name>CCUS</name> 15167 <description>Capture/compare control update 15168 selection</description> 15169 <bitOffset>2</bitOffset> 15170 <bitWidth>1</bitWidth> 15171 </field> 15172 <field> 15173 <name>CCPC</name> 15174 <description>Capture/compare preloaded 15175 control</description> 15176 <bitOffset>0</bitOffset> 15177 <bitWidth>1</bitWidth> 15178 </field> 15179 </fields> 15180 </register> 15181 <register> 15182 <name>SMCR</name> 15183 <displayName>SMCR</displayName> 15184 <description>slave mode control register</description> 15185 <addressOffset>0x8</addressOffset> 15186 <size>0x20</size> 15187 <access>read-write</access> 15188 <resetValue>0x0000</resetValue> 15189 <fields> 15190 <field> 15191 <name>ETP</name> 15192 <description>External trigger polarity</description> 15193 <bitOffset>15</bitOffset> 15194 <bitWidth>1</bitWidth> 15195 <enumeratedValues><name>ETP</name><usage>read-write</usage><enumeratedValue><name>NotInverted</name><description>ETR is noninverted, active at high level or rising edge</description><value>0</value></enumeratedValue><enumeratedValue><name>Inverted</name><description>ETR is inverted, active at low level or falling edge</description><value>1</value></enumeratedValue></enumeratedValues> 15196 </field> 15197 <field> 15198 <name>ECE</name> 15199 <description>External clock enable</description> 15200 <bitOffset>14</bitOffset> 15201 <bitWidth>1</bitWidth> 15202 <enumeratedValues><name>ECE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>External clock mode 2 disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.</description><value>1</value></enumeratedValue></enumeratedValues> 15203 </field> 15204 <field> 15205 <name>ETPS</name> 15206 <description>External trigger prescaler</description> 15207 <bitOffset>12</bitOffset> 15208 <bitWidth>2</bitWidth> 15209 <enumeratedValues><name>ETPS</name><usage>read-write</usage><enumeratedValue><name>Div1</name><description>Prescaler OFF</description><value>0</value></enumeratedValue><enumeratedValue><name>Div2</name><description>ETRP frequency divided by 2</description><value>1</value></enumeratedValue><enumeratedValue><name>Div4</name><description>ETRP frequency divided by 4</description><value>2</value></enumeratedValue><enumeratedValue><name>Div8</name><description>ETRP frequency divided by 8</description><value>3</value></enumeratedValue></enumeratedValues> 15210 </field> 15211 <field> 15212 <name>ETF</name> 15213 <description>External trigger filter</description> 15214 <bitOffset>8</bitOffset> 15215 <bitWidth>4</bitWidth> 15216 <enumeratedValues><name>ETF</name><usage>read-write</usage><enumeratedValue><name>NoFilter</name><description>No filter, sampling is done at fDTS</description><value>0</value></enumeratedValue><enumeratedValue><name>FCK_INT_N2</name><description>fSAMPLING=fCK_INT, N=2</description><value>1</value></enumeratedValue><enumeratedValue><name>FCK_INT_N4</name><description>fSAMPLING=fCK_INT, N=4</description><value>2</value></enumeratedValue><enumeratedValue><name>FCK_INT_N8</name><description>fSAMPLING=fCK_INT, N=8</description><value>3</value></enumeratedValue><enumeratedValue><name>FDTS_Div2_N6</name><description>fSAMPLING=fDTS/2, N=6</description><value>4</value></enumeratedValue><enumeratedValue><name>FDTS_Div2_N8</name><description>fSAMPLING=fDTS/2, N=8</description><value>5</value></enumeratedValue><enumeratedValue><name>FDTS_Div4_N6</name><description>fSAMPLING=fDTS/4, N=6</description><value>6</value></enumeratedValue><enumeratedValue><name>FDTS_Div4_N8</name><description>fSAMPLING=fDTS/4, N=8</description><value>7</value></enumeratedValue><enumeratedValue><name>FDTS_Div8_N6</name><description>fSAMPLING=fDTS/8, N=6</description><value>8</value></enumeratedValue><enumeratedValue><name>FDTS_Div8_N8</name><description>fSAMPLING=fDTS/8, N=8</description><value>9</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N5</name><description>fSAMPLING=fDTS/16, N=5</description><value>10</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N6</name><description>fSAMPLING=fDTS/16, N=6</description><value>11</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N8</name><description>fSAMPLING=fDTS/16, N=8</description><value>12</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N5</name><description>fSAMPLING=fDTS/32, N=5</description><value>13</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N6</name><description>fSAMPLING=fDTS/32, N=6</description><value>14</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N8</name><description>fSAMPLING=fDTS/32, N=8</description><value>15</value></enumeratedValue></enumeratedValues> 15217 </field> 15218 <field> 15219 <name>MSM</name> 15220 <description>Master/Slave mode</description> 15221 <bitOffset>7</bitOffset> 15222 <bitWidth>1</bitWidth> 15223 <enumeratedValues><name>MSM</name><usage>read-write</usage><enumeratedValue><name>NoSync</name><description>No action</description><value>0</value></enumeratedValue><enumeratedValue><name>Sync</name><description>The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.</description><value>1</value></enumeratedValue></enumeratedValues> 15224 </field> 15225 <field> 15226 <name>TS</name> 15227 <description>Trigger selection</description> 15228 <bitOffset>4</bitOffset> 15229 <bitWidth>3</bitWidth> 15230 <enumeratedValues><name>TS</name><usage>read-write</usage><enumeratedValue><name>ITR0</name><description>Internal Trigger 0 (ITR0)</description><value>0</value></enumeratedValue><enumeratedValue><name>ITR1</name><description>Internal Trigger 1 (ITR1)</description><value>1</value></enumeratedValue><enumeratedValue><name>ITR2</name><description>Internal Trigger 2 (ITR2)</description><value>2</value></enumeratedValue><enumeratedValue><name>TI1F_ED</name><description>TI1 Edge Detector (TI1F_ED)</description><value>4</value></enumeratedValue><enumeratedValue><name>TI1FP1</name><description>Filtered Timer Input 1 (TI1FP1)</description><value>5</value></enumeratedValue><enumeratedValue><name>TI2FP2</name><description>Filtered Timer Input 2 (TI2FP2)</description><value>6</value></enumeratedValue><enumeratedValue><name>ETRF</name><description>External Trigger input (ETRF)</description><value>7</value></enumeratedValue></enumeratedValues> 15231 </field> 15232 <field> 15233 <name>SMS</name> 15234 <description>Slave mode selection</description> 15235 <bitOffset>0</bitOffset> 15236 <bitWidth>3</bitWidth> 15237 <enumeratedValues><name>SMS</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.</description><value>0</value></enumeratedValue><enumeratedValue><name>Encoder_Mode_1</name><description>Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.</description><value>1</value></enumeratedValue><enumeratedValue><name>Encoder_Mode_2</name><description>Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.</description><value>2</value></enumeratedValue><enumeratedValue><name>Encoder_Mode_3</name><description>Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.</description><value>3</value></enumeratedValue><enumeratedValue><name>Reset_Mode</name><description>Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.</description><value>4</value></enumeratedValue><enumeratedValue><name>Gated_Mode</name><description>Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.</description><value>5</value></enumeratedValue><enumeratedValue><name>Trigger_Mode</name><description>Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.</description><value>6</value></enumeratedValue><enumeratedValue><name>Ext_Clock_Mode</name><description>External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.</description><value>7</value></enumeratedValue></enumeratedValues> 15238 </field> 15239 </fields> 15240 </register> 15241 <register> 15242 <name>DIER</name> 15243 <displayName>DIER</displayName> 15244 <description>DMA/Interrupt enable register</description> 15245 <addressOffset>0xC</addressOffset> 15246 <size>0x20</size> 15247 <access>read-write</access> 15248 <resetValue>0x0000</resetValue> 15249 <fields> 15250 <field> 15251 <name>TDE</name> 15252 <description>Trigger DMA request enable</description> 15253 <bitOffset>14</bitOffset> 15254 <bitWidth>1</bitWidth> 15255 <enumeratedValues><name>TDE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Trigger DMA request disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Trigger DMA request enabled</description><value>1</value></enumeratedValue></enumeratedValues> 15256 </field> 15257 <field> 15258 <name>COMDE</name> 15259 <description>COM DMA request enable</description> 15260 <bitOffset>13</bitOffset> 15261 <bitWidth>1</bitWidth> 15262 </field> 15263 <field> 15264 <name>CC4DE</name> 15265 <description>Capture/Compare 4 DMA request 15266 enable</description> 15267 <bitOffset>12</bitOffset> 15268 <bitWidth>1</bitWidth> 15269 <enumeratedValues derivedFrom="CC1DE"/> 15270 </field> 15271 <field> 15272 <name>CC3DE</name> 15273 <description>Capture/Compare 3 DMA request 15274 enable</description> 15275 <bitOffset>11</bitOffset> 15276 <bitWidth>1</bitWidth> 15277 <enumeratedValues derivedFrom="CC1DE"/> 15278 </field> 15279 <field> 15280 <name>CC2DE</name> 15281 <description>Capture/Compare 2 DMA request 15282 enable</description> 15283 <bitOffset>10</bitOffset> 15284 <bitWidth>1</bitWidth> 15285 <enumeratedValues derivedFrom="CC1DE"/> 15286 </field> 15287 <field> 15288 <name>CC1DE</name> 15289 <description>Capture/Compare 1 DMA request 15290 enable</description> 15291 <bitOffset>9</bitOffset> 15292 <bitWidth>1</bitWidth> 15293 <enumeratedValues><name>CC1DE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>CCx DMA request disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>CCx DMA request enabled</description><value>1</value></enumeratedValue></enumeratedValues> 15294 </field> 15295 <field> 15296 <name>UDE</name> 15297 <description>Update DMA request enable</description> 15298 <bitOffset>8</bitOffset> 15299 <bitWidth>1</bitWidth> 15300 <enumeratedValues><name>UDE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Update DMA request disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Update DMA request enabled</description><value>1</value></enumeratedValue></enumeratedValues> 15301 </field> 15302 <field> 15303 <name>TIE</name> 15304 <description>Trigger interrupt enable</description> 15305 <bitOffset>6</bitOffset> 15306 <bitWidth>1</bitWidth> 15307 <enumeratedValues><name>TIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Trigger interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Trigger interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 15308 </field> 15309 <field> 15310 <name>CC4IE</name> 15311 <description>Capture/Compare 4 interrupt 15312 enable</description> 15313 <bitOffset>4</bitOffset> 15314 <bitWidth>1</bitWidth> 15315 <enumeratedValues derivedFrom="CC1IE"/> 15316 </field> 15317 <field> 15318 <name>CC3IE</name> 15319 <description>Capture/Compare 3 interrupt 15320 enable</description> 15321 <bitOffset>3</bitOffset> 15322 <bitWidth>1</bitWidth> 15323 <enumeratedValues derivedFrom="CC1IE"/> 15324 </field> 15325 <field> 15326 <name>CC2IE</name> 15327 <description>Capture/Compare 2 interrupt 15328 enable</description> 15329 <bitOffset>2</bitOffset> 15330 <bitWidth>1</bitWidth> 15331 <enumeratedValues derivedFrom="CC1IE"/> 15332 </field> 15333 <field> 15334 <name>CC1IE</name> 15335 <description>Capture/Compare 1 interrupt 15336 enable</description> 15337 <bitOffset>1</bitOffset> 15338 <bitWidth>1</bitWidth> 15339 <enumeratedValues><name>CC1IE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>CCx interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>CCx interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 15340 </field> 15341 <field> 15342 <name>UIE</name> 15343 <description>Update interrupt enable</description> 15344 <bitOffset>0</bitOffset> 15345 <bitWidth>1</bitWidth> 15346 <enumeratedValues><name>UIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Update interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Update interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 15347 </field> 15348 <field> 15349 <name>BIE</name> 15350 <description>Break interrupt enable</description> 15351 <bitOffset>7</bitOffset> 15352 <bitWidth>1</bitWidth> 15353 </field> 15354 <field> 15355 <name>COMIE</name> 15356 <description>COM interrupt enable</description> 15357 <bitOffset>5</bitOffset> 15358 <bitWidth>1</bitWidth> 15359 </field> 15360 </fields> 15361 </register> 15362 <register> 15363 <name>SR</name> 15364 <displayName>SR</displayName> 15365 <description>status register</description> 15366 <addressOffset>0x10</addressOffset> 15367 <size>0x20</size> 15368 <access>read-write</access> 15369 <resetValue>0x0000</resetValue> 15370 <fields> 15371 <field> 15372 <name>CC4OF</name> 15373 <description>Capture/Compare 4 overcapture 15374 flag</description> 15375 <bitOffset>12</bitOffset> 15376 <bitWidth>1</bitWidth> 15377 <enumeratedValues derivedFrom="CC1OFR"/> 15378 <enumeratedValues derivedFrom="CC1OFW"/> 15379 </field> 15380 <field> 15381 <name>CC3OF</name> 15382 <description>Capture/Compare 3 overcapture 15383 flag</description> 15384 <bitOffset>11</bitOffset> 15385 <bitWidth>1</bitWidth> 15386 <enumeratedValues derivedFrom="CC1OFR"/> 15387 <enumeratedValues derivedFrom="CC1OFW"/> 15388 </field> 15389 <field> 15390 <name>CC2OF</name> 15391 <description>Capture/compare 2 overcapture 15392 flag</description> 15393 <bitOffset>10</bitOffset> 15394 <bitWidth>1</bitWidth> 15395 <enumeratedValues derivedFrom="CC1OFR"/> 15396 <enumeratedValues derivedFrom="CC1OFW"/> 15397 </field> 15398 <field> 15399 <name>CC1OF</name> 15400 <description>Capture/Compare 1 overcapture 15401 flag</description> 15402 <bitOffset>9</bitOffset> 15403 <bitWidth>1</bitWidth> 15404 <enumeratedValues><name>CC1OFR</name><usage>read</usage><enumeratedValue><name>Overcapture</name><description>The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set</description><value>1</value></enumeratedValue></enumeratedValues> 15405 <enumeratedValues><name>CC1OFW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clear flag</description><value>0</value></enumeratedValue></enumeratedValues> 15406 </field> 15407 <field> 15408 <name>BIF</name> 15409 <description>Break interrupt flag</description> 15410 <bitOffset>7</bitOffset> 15411 <bitWidth>1</bitWidth> 15412 </field> 15413 <field> 15414 <name>TIF</name> 15415 <description>Trigger interrupt flag</description> 15416 <bitOffset>6</bitOffset> 15417 <bitWidth>1</bitWidth> 15418 <enumeratedValues><name>TIFR</name><usage>read</usage><enumeratedValue><name>NoTrigger</name><description>No trigger event occurred</description><value>0</value></enumeratedValue><enumeratedValue><name>Trigger</name><description>Trigger interrupt pending</description><value>1</value></enumeratedValue></enumeratedValues> 15419 <enumeratedValues><name>TIFW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clear flag</description><value>0</value></enumeratedValue></enumeratedValues> 15420 </field> 15421 <field> 15422 <name>COMIF</name> 15423 <description>COM interrupt flag</description> 15424 <bitOffset>5</bitOffset> 15425 <bitWidth>1</bitWidth> 15426 </field> 15427 <field> 15428 <name>CC4IF</name> 15429 <description>Capture/Compare 4 interrupt 15430 flag</description> 15431 <bitOffset>4</bitOffset> 15432 <bitWidth>1</bitWidth> 15433 <enumeratedValues derivedFrom="CC1IFR"/> 15434 <enumeratedValues derivedFrom="CC1IFW"/> 15435 </field> 15436 <field> 15437 <name>CC3IF</name> 15438 <description>Capture/Compare 3 interrupt 15439 flag</description> 15440 <bitOffset>3</bitOffset> 15441 <bitWidth>1</bitWidth> 15442 <enumeratedValues derivedFrom="CC1IFR"/> 15443 <enumeratedValues derivedFrom="CC1IFW"/> 15444 </field> 15445 <field> 15446 <name>CC2IF</name> 15447 <description>Capture/Compare 2 interrupt 15448 flag</description> 15449 <bitOffset>2</bitOffset> 15450 <bitWidth>1</bitWidth> 15451 <enumeratedValues derivedFrom="CC1IFR"/> 15452 <enumeratedValues derivedFrom="CC1IFW"/> 15453 </field> 15454 <field> 15455 <name>CC1IF</name> 15456 <description>Capture/compare 1 interrupt 15457 flag</description> 15458 <bitOffset>1</bitOffset> 15459 <bitWidth>1</bitWidth> 15460 <enumeratedValues><name>CC1IFR</name><usage>read</usage><enumeratedValue><name>Match</name><description>If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.</description><value>1</value></enumeratedValue></enumeratedValues> 15461 <enumeratedValues><name>CC1IFW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clear flag</description><value>0</value></enumeratedValue></enumeratedValues> 15462 </field> 15463 <field> 15464 <name>UIF</name> 15465 <description>Update interrupt flag</description> 15466 <bitOffset>0</bitOffset> 15467 <bitWidth>1</bitWidth> 15468 <enumeratedValues><name>UIF</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>No update occurred</description><value>0</value></enumeratedValue><enumeratedValue><name>UpdatePending</name><description>Update interrupt pending.</description><value>1</value></enumeratedValue></enumeratedValues> 15469 </field> 15470 </fields> 15471 </register> 15472 <register> 15473 <name>EGR</name> 15474 <displayName>EGR</displayName> 15475 <description>event generation register</description> 15476 <addressOffset>0x14</addressOffset> 15477 <size>0x20</size> 15478 <access>write-only</access> 15479 <resetValue>0x0000</resetValue> 15480 <fields> 15481 <field> 15482 <name>BG</name> 15483 <description>Break generation</description> 15484 <bitOffset>7</bitOffset> 15485 <bitWidth>1</bitWidth> 15486 </field> 15487 <field> 15488 <name>TG</name> 15489 <description>Trigger generation</description> 15490 <bitOffset>6</bitOffset> 15491 <bitWidth>1</bitWidth> 15492 <enumeratedValues><name>TGW</name><usage>write</usage><enumeratedValue><name>Trigger</name><description>The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.</description><value>1</value></enumeratedValue></enumeratedValues> 15493 </field> 15494 <field> 15495 <name>COMG</name> 15496 <description>Capture/Compare control update 15497 generation</description> 15498 <bitOffset>5</bitOffset> 15499 <bitWidth>1</bitWidth> 15500 </field> 15501 <field> 15502 <name>CC4G</name> 15503 <description>Capture/compare 4 15504 generation</description> 15505 <bitOffset>4</bitOffset> 15506 <bitWidth>1</bitWidth> 15507 <enumeratedValues derivedFrom="CC1GW"/> 15508 </field> 15509 <field> 15510 <name>CC3G</name> 15511 <description>Capture/compare 3 15512 generation</description> 15513 <bitOffset>3</bitOffset> 15514 <bitWidth>1</bitWidth> 15515 <enumeratedValues derivedFrom="CC1GW"/> 15516 </field> 15517 <field> 15518 <name>CC2G</name> 15519 <description>Capture/compare 2 15520 generation</description> 15521 <bitOffset>2</bitOffset> 15522 <bitWidth>1</bitWidth> 15523 <enumeratedValues derivedFrom="CC1GW"/> 15524 </field> 15525 <field> 15526 <name>CC1G</name> 15527 <description>Capture/compare 1 15528 generation</description> 15529 <bitOffset>1</bitOffset> 15530 <bitWidth>1</bitWidth> 15531 <enumeratedValues><name>CC1GW</name><usage>write</usage><enumeratedValue><name>Trigger</name><description>If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.</description><value>1</value></enumeratedValue></enumeratedValues> 15532 </field> 15533 <field> 15534 <name>UG</name> 15535 <description>Update generation</description> 15536 <bitOffset>0</bitOffset> 15537 <bitWidth>1</bitWidth> 15538 <enumeratedValues><name>UG</name><usage>read-write</usage><enumeratedValue><name>Update</name><description>Re-initializes the timer counter and generates an update of the registers.</description><value>1</value></enumeratedValue></enumeratedValues> 15539 </field> 15540 </fields> 15541 </register> 15542 <register> 15543 <name>CCMR1_Output</name> 15544 <displayName>CCMR1_Output</displayName> 15545 <description>capture/compare mode register 1 (output 15546 mode)</description> 15547 <addressOffset>0x18</addressOffset> 15548 <size>0x20</size> 15549 <access>read-write</access> 15550 <resetValue>0x00000000</resetValue> 15551 <fields> 15552 <field> 15553 <name>OC2CE</name> 15554 <description>Output Compare 2 clear 15555 enable</description> 15556 <bitOffset>15</bitOffset> 15557 <bitWidth>1</bitWidth> 15558 </field> 15559 <field> 15560 <name>OC2M</name> 15561 <description>Output Compare 2 mode</description> 15562 <bitOffset>12</bitOffset> 15563 <bitWidth>3</bitWidth> 15564 <enumeratedValues derivedFrom="OC1M"/> 15565 </field> 15566 <field> 15567 <name>OC2PE</name> 15568 <description>Output Compare 2 preload 15569 enable</description> 15570 <bitOffset>11</bitOffset> 15571 <bitWidth>1</bitWidth> 15572 <enumeratedValues><name>OC2PE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Preload register on CCR2 enabled. Preload value is loaded into active register on each update event</description><value>1</value></enumeratedValue></enumeratedValues> 15573 </field> 15574 <field> 15575 <name>OC2FE</name> 15576 <description>Output Compare 2 fast 15577 enable</description> 15578 <bitOffset>10</bitOffset> 15579 <bitWidth>1</bitWidth> 15580 </field> 15581 <field> 15582 <name>CC2S</name> 15583 <description>Capture/Compare 2 15584 selection</description> 15585 <bitOffset>8</bitOffset> 15586 <bitWidth>2</bitWidth> 15587 <enumeratedValues><name>CC2S</name><usage>read-write</usage><enumeratedValue><name>Output</name><description>CC2 channel is configured as output</description><value>0</value></enumeratedValue></enumeratedValues> 15588 </field> 15589 <field> 15590 <name>OC1CE</name> 15591 <description>Output Compare 1 clear 15592 enable</description> 15593 <bitOffset>7</bitOffset> 15594 <bitWidth>1</bitWidth> 15595 </field> 15596 <field> 15597 <name>OC1M</name> 15598 <description>Output Compare 1 mode</description> 15599 <bitOffset>4</bitOffset> 15600 <bitWidth>3</bitWidth> 15601 <enumeratedValues><name>OC1M</name><usage>read-write</usage><enumeratedValue><name>Frozen</name><description>The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs</description><value>0</value></enumeratedValue><enumeratedValue><name>ActiveOnMatch</name><description>Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register</description><value>1</value></enumeratedValue><enumeratedValue><name>InactiveOnMatch</name><description>Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register</description><value>2</value></enumeratedValue><enumeratedValue><name>Toggle</name><description>OCyREF toggles when TIMx_CNT=TIMx_CCRy</description><value>3</value></enumeratedValue><enumeratedValue><name>ForceInactive</name><description>OCyREF is forced low</description><value>4</value></enumeratedValue><enumeratedValue><name>ForceActive</name><description>OCyREF is forced high</description><value>5</value></enumeratedValue><enumeratedValue><name>PwmMode1</name><description>In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active</description><value>6</value></enumeratedValue><enumeratedValue><name>PwmMode2</name><description>Inversely to PwmMode1</description><value>7</value></enumeratedValue></enumeratedValues> 15602 </field> 15603 <field> 15604 <name>OC1PE</name> 15605 <description>Output Compare 1 preload 15606 enable</description> 15607 <bitOffset>3</bitOffset> 15608 <bitWidth>1</bitWidth> 15609 <enumeratedValues><name>OC1PE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Preload register on CCR1 enabled. Preload value is loaded into active register on each update event</description><value>1</value></enumeratedValue></enumeratedValues> 15610 </field> 15611 <field> 15612 <name>OC1FE</name> 15613 <description>Output Compare 1 fast 15614 enable</description> 15615 <bitOffset>2</bitOffset> 15616 <bitWidth>1</bitWidth> 15617 </field> 15618 <field> 15619 <name>CC1S</name> 15620 <description>Capture/Compare 1 15621 selection</description> 15622 <bitOffset>0</bitOffset> 15623 <bitWidth>2</bitWidth> 15624 <enumeratedValues><name>CC1S</name><usage>read-write</usage><enumeratedValue><name>Output</name><description>CC1 channel is configured as output</description><value>0</value></enumeratedValue></enumeratedValues> 15625 </field> 15626 </fields> 15627 </register> 15628 <register> 15629 <name>CCMR1_Input</name> 15630 <displayName>CCMR1_Input</displayName> 15631 <description>capture/compare mode register 1 (input 15632 mode)</description> 15633 <alternateRegister>CCMR1_Output</alternateRegister> 15634 <addressOffset>0x18</addressOffset> 15635 <size>0x20</size> 15636 <access>read-write</access> 15637 <resetValue>0x00000000</resetValue> 15638 <fields> 15639 <field> 15640 <name>IC2F</name> 15641 <description>Input capture 2 filter</description> 15642 <bitOffset>12</bitOffset> 15643 <bitWidth>4</bitWidth> 15644 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 15645 </field> 15646 <field> 15647 <name>IC2PSC</name> 15648 <description>Input capture 2 prescaler</description> 15649 <bitOffset>10</bitOffset> 15650 <bitWidth>2</bitWidth> 15651 </field> 15652 <field> 15653 <name>CC2S</name> 15654 <description>Capture/Compare 2 15655 selection</description> 15656 <bitOffset>8</bitOffset> 15657 <bitWidth>2</bitWidth> 15658 <enumeratedValues><name>CC2S</name><usage>read-write</usage><enumeratedValue><name>TI2</name><description>CC2 channel is configured as input, IC2 is mapped on TI2</description><value>1</value></enumeratedValue><enumeratedValue><name>TI1</name><description>CC2 channel is configured as input, IC2 is mapped on TI1</description><value>2</value></enumeratedValue><enumeratedValue><name>TRC</name><description>CC2 channel is configured as input, IC2 is mapped on TRC</description><value>3</value></enumeratedValue></enumeratedValues> 15659 </field> 15660 <field> 15661 <name>IC1F</name> 15662 <description>Input capture 1 filter</description> 15663 <bitOffset>4</bitOffset> 15664 <bitWidth>4</bitWidth> 15665 <enumeratedValues><name>IC1F</name><usage>read-write</usage><enumeratedValue><name>NoFilter</name><description>No filter, sampling is done at fDTS</description><value>0</value></enumeratedValue><enumeratedValue><name>FCK_INT_N2</name><description>fSAMPLING=fCK_INT, N=2</description><value>1</value></enumeratedValue><enumeratedValue><name>FCK_INT_N4</name><description>fSAMPLING=fCK_INT, N=4</description><value>2</value></enumeratedValue><enumeratedValue><name>FCK_INT_N8</name><description>fSAMPLING=fCK_INT, N=8</description><value>3</value></enumeratedValue><enumeratedValue><name>FDTS_Div2_N6</name><description>fSAMPLING=fDTS/2, N=6</description><value>4</value></enumeratedValue><enumeratedValue><name>FDTS_Div2_N8</name><description>fSAMPLING=fDTS/2, N=8</description><value>5</value></enumeratedValue><enumeratedValue><name>FDTS_Div4_N6</name><description>fSAMPLING=fDTS/4, N=6</description><value>6</value></enumeratedValue><enumeratedValue><name>FDTS_Div4_N8</name><description>fSAMPLING=fDTS/4, N=8</description><value>7</value></enumeratedValue><enumeratedValue><name>FDTS_Div8_N6</name><description>fSAMPLING=fDTS/8, N=6</description><value>8</value></enumeratedValue><enumeratedValue><name>FDTS_Div8_N8</name><description>fSAMPLING=fDTS/8, N=8</description><value>9</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N5</name><description>fSAMPLING=fDTS/16, N=5</description><value>10</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N6</name><description>fSAMPLING=fDTS/16, N=6</description><value>11</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N8</name><description>fSAMPLING=fDTS/16, N=8</description><value>12</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N5</name><description>fSAMPLING=fDTS/32, N=5</description><value>13</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N6</name><description>fSAMPLING=fDTS/32, N=6</description><value>14</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N8</name><description>fSAMPLING=fDTS/32, N=8</description><value>15</value></enumeratedValue></enumeratedValues> 15666 </field> 15667 <field> 15668 <name>IC1PSC</name> 15669 <description>Input capture 1 prescaler</description> 15670 <bitOffset>2</bitOffset> 15671 <bitWidth>2</bitWidth> 15672 </field> 15673 <field> 15674 <name>CC1S</name> 15675 <description>Capture/Compare 1 15676 selection</description> 15677 <bitOffset>0</bitOffset> 15678 <bitWidth>2</bitWidth> 15679 <enumeratedValues><name>CC1S</name><usage>read-write</usage><enumeratedValue><name>TI1</name><description>CC1 channel is configured as input, IC1 is mapped on TI1</description><value>1</value></enumeratedValue><enumeratedValue><name>TI2</name><description>CC1 channel is configured as input, IC1 is mapped on TI2</description><value>2</value></enumeratedValue><enumeratedValue><name>TRC</name><description>CC1 channel is configured as input, IC1 is mapped on TRC</description><value>3</value></enumeratedValue></enumeratedValues> 15680 </field> 15681 </fields> 15682 </register> 15683 <register> 15684 <name>CCMR2_Output</name> 15685 <displayName>CCMR2_Output</displayName> 15686 <description>capture/compare mode register 2 (output 15687 mode)</description> 15688 <addressOffset>0x1C</addressOffset> 15689 <size>0x20</size> 15690 <access>read-write</access> 15691 <resetValue>0x00000000</resetValue> 15692 <fields> 15693 <field> 15694 <name>OC4CE</name> 15695 <description>Output compare 4 clear 15696 enable</description> 15697 <bitOffset>15</bitOffset> 15698 <bitWidth>1</bitWidth> 15699 </field> 15700 <field> 15701 <name>OC4M</name> 15702 <description>Output compare 4 mode</description> 15703 <bitOffset>12</bitOffset> 15704 <bitWidth>3</bitWidth> 15705 <enumeratedValues derivedFrom="OC3M"/> 15706 </field> 15707 <field> 15708 <name>OC4PE</name> 15709 <description>Output compare 4 preload 15710 enable</description> 15711 <bitOffset>11</bitOffset> 15712 <bitWidth>1</bitWidth> 15713 <enumeratedValues><name>OC4PE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Preload register on CCR4 disabled. New values written to CCR4 are taken into account immediately</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Preload register on CCR4 enabled. Preload value is loaded into active register on each update event</description><value>1</value></enumeratedValue></enumeratedValues> 15714 </field> 15715 <field> 15716 <name>OC4FE</name> 15717 <description>Output compare 4 fast 15718 enable</description> 15719 <bitOffset>10</bitOffset> 15720 <bitWidth>1</bitWidth> 15721 </field> 15722 <field> 15723 <name>CC4S</name> 15724 <description>Capture/Compare 4 15725 selection</description> 15726 <bitOffset>8</bitOffset> 15727 <bitWidth>2</bitWidth> 15728 <enumeratedValues><name>CC4S</name><usage>read-write</usage><enumeratedValue><name>Output</name><description>CC4 channel is configured as output</description><value>0</value></enumeratedValue></enumeratedValues> 15729 </field> 15730 <field> 15731 <name>OC3CE</name> 15732 <description>Output compare 3 clear 15733 enable</description> 15734 <bitOffset>7</bitOffset> 15735 <bitWidth>1</bitWidth> 15736 </field> 15737 <field> 15738 <name>OC3M</name> 15739 <description>Output compare 3 mode</description> 15740 <bitOffset>4</bitOffset> 15741 <bitWidth>3</bitWidth> 15742 <enumeratedValues><name>OC3M</name><usage>read-write</usage><enumeratedValue><name>Frozen</name><description>The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs</description><value>0</value></enumeratedValue><enumeratedValue><name>ActiveOnMatch</name><description>Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register</description><value>1</value></enumeratedValue><enumeratedValue><name>InactiveOnMatch</name><description>Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register</description><value>2</value></enumeratedValue><enumeratedValue><name>Toggle</name><description>OCyREF toggles when TIMx_CNT=TIMx_CCRy</description><value>3</value></enumeratedValue><enumeratedValue><name>ForceInactive</name><description>OCyREF is forced low</description><value>4</value></enumeratedValue><enumeratedValue><name>ForceActive</name><description>OCyREF is forced high</description><value>5</value></enumeratedValue><enumeratedValue><name>PwmMode1</name><description>In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active</description><value>6</value></enumeratedValue><enumeratedValue><name>PwmMode2</name><description>Inversely to PwmMode1</description><value>7</value></enumeratedValue></enumeratedValues> 15743 </field> 15744 <field> 15745 <name>OC3PE</name> 15746 <description>Output compare 3 preload 15747 enable</description> 15748 <bitOffset>3</bitOffset> 15749 <bitWidth>1</bitWidth> 15750 <enumeratedValues><name>OC3PE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Preload register on CCR3 enabled. Preload value is loaded into active register on each update event</description><value>1</value></enumeratedValue></enumeratedValues> 15751 </field> 15752 <field> 15753 <name>OC3FE</name> 15754 <description>Output compare 3 fast 15755 enable</description> 15756 <bitOffset>2</bitOffset> 15757 <bitWidth>1</bitWidth> 15758 </field> 15759 <field> 15760 <name>CC3S</name> 15761 <description>Capture/Compare 3 15762 selection</description> 15763 <bitOffset>0</bitOffset> 15764 <bitWidth>2</bitWidth> 15765 <enumeratedValues><name>CC3S</name><usage>read-write</usage><enumeratedValue><name>Output</name><description>CC3 channel is configured as output</description><value>0</value></enumeratedValue></enumeratedValues> 15766 </field> 15767 </fields> 15768 </register> 15769 <register> 15770 <name>CCMR2_Input</name> 15771 <displayName>CCMR2_Input</displayName> 15772 <description>capture/compare mode register 2 (input 15773 mode)</description> 15774 <alternateRegister>CCMR2_Output</alternateRegister> 15775 <addressOffset>0x1C</addressOffset> 15776 <size>0x20</size> 15777 <access>read-write</access> 15778 <resetValue>0x00000000</resetValue> 15779 <fields> 15780 <field> 15781 <name>IC4F</name> 15782 <description>Input capture 4 filter</description> 15783 <bitOffset>12</bitOffset> 15784 <bitWidth>4</bitWidth> 15785 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 15786 </field> 15787 <field> 15788 <name>IC4PSC</name> 15789 <description>Input capture 4 prescaler</description> 15790 <bitOffset>10</bitOffset> 15791 <bitWidth>2</bitWidth> 15792 <writeConstraint><range><minimum>0</minimum><maximum>3</maximum></range></writeConstraint> 15793 </field> 15794 <field> 15795 <name>CC4S</name> 15796 <description>Capture/Compare 4 15797 selection</description> 15798 <bitOffset>8</bitOffset> 15799 <bitWidth>2</bitWidth> 15800 <enumeratedValues><name>CC4S</name><usage>read-write</usage><enumeratedValue><name>TI4</name><description>CC4 channel is configured as input, IC4 is mapped on TI4</description><value>1</value></enumeratedValue><enumeratedValue><name>TI3</name><description>CC4 channel is configured as input, IC4 is mapped on TI3</description><value>2</value></enumeratedValue><enumeratedValue><name>TRC</name><description>CC4 channel is configured as input, IC4 is mapped on TRC</description><value>3</value></enumeratedValue></enumeratedValues> 15801 </field> 15802 <field> 15803 <name>IC3F</name> 15804 <description>Input capture 3 filter</description> 15805 <bitOffset>4</bitOffset> 15806 <bitWidth>4</bitWidth> 15807 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 15808 </field> 15809 <field> 15810 <name>IC3PSC</name> 15811 <description>Input capture 3 prescaler</description> 15812 <bitOffset>2</bitOffset> 15813 <bitWidth>2</bitWidth> 15814 <writeConstraint><range><minimum>0</minimum><maximum>3</maximum></range></writeConstraint> 15815 </field> 15816 <field> 15817 <name>CC3S</name> 15818 <description>Capture/compare 3 15819 selection</description> 15820 <bitOffset>0</bitOffset> 15821 <bitWidth>2</bitWidth> 15822 <enumeratedValues><name>CC3S</name><usage>read-write</usage><enumeratedValue><name>TI3</name><description>CC3 channel is configured as input, IC3 is mapped on TI3</description><value>1</value></enumeratedValue><enumeratedValue><name>TI4</name><description>CC3 channel is configured as input, IC3 is mapped on TI4</description><value>2</value></enumeratedValue><enumeratedValue><name>TRC</name><description>CC3 channel is configured as input, IC3 is mapped on TRC</description><value>3</value></enumeratedValue></enumeratedValues> 15823 </field> 15824 </fields> 15825 </register> 15826 <register> 15827 <name>CCER</name> 15828 <displayName>CCER</displayName> 15829 <description>capture/compare enable 15830 register</description> 15831 <addressOffset>0x20</addressOffset> 15832 <size>0x20</size> 15833 <access>read-write</access> 15834 <resetValue>0x0000</resetValue> 15835 <fields> 15836 <field> 15837 <name>CC4P</name> 15838 <description>Capture/Compare 3 output 15839 Polarity</description> 15840 <bitOffset>13</bitOffset> 15841 <bitWidth>1</bitWidth> 15842 </field> 15843 <field> 15844 <name>CC4E</name> 15845 <description>Capture/Compare 4 output 15846 enable</description> 15847 <bitOffset>12</bitOffset> 15848 <bitWidth>1</bitWidth> 15849 </field> 15850 <field> 15851 <name>CC3NP</name> 15852 <description>Capture/Compare 3 output 15853 Polarity</description> 15854 <bitOffset>11</bitOffset> 15855 <bitWidth>1</bitWidth> 15856 </field> 15857 <field> 15858 <name>CC3NE</name> 15859 <description>Capture/Compare 3 complementary output 15860 enable</description> 15861 <bitOffset>10</bitOffset> 15862 <bitWidth>1</bitWidth> 15863 </field> 15864 <field> 15865 <name>CC3P</name> 15866 <description>Capture/Compare 3 output 15867 Polarity</description> 15868 <bitOffset>9</bitOffset> 15869 <bitWidth>1</bitWidth> 15870 </field> 15871 <field> 15872 <name>CC3E</name> 15873 <description>Capture/Compare 3 output 15874 enable</description> 15875 <bitOffset>8</bitOffset> 15876 <bitWidth>1</bitWidth> 15877 </field> 15878 <field> 15879 <name>CC2NP</name> 15880 <description>Capture/Compare 2 output 15881 Polarity</description> 15882 <bitOffset>7</bitOffset> 15883 <bitWidth>1</bitWidth> 15884 </field> 15885 <field> 15886 <name>CC2NE</name> 15887 <description>Capture/Compare 2 complementary output 15888 enable</description> 15889 <bitOffset>6</bitOffset> 15890 <bitWidth>1</bitWidth> 15891 </field> 15892 <field> 15893 <name>CC2P</name> 15894 <description>Capture/Compare 2 output 15895 Polarity</description> 15896 <bitOffset>5</bitOffset> 15897 <bitWidth>1</bitWidth> 15898 </field> 15899 <field> 15900 <name>CC2E</name> 15901 <description>Capture/Compare 2 output 15902 enable</description> 15903 <bitOffset>4</bitOffset> 15904 <bitWidth>1</bitWidth> 15905 </field> 15906 <field> 15907 <name>CC1NP</name> 15908 <description>Capture/Compare 1 output 15909 Polarity</description> 15910 <bitOffset>3</bitOffset> 15911 <bitWidth>1</bitWidth> 15912 </field> 15913 <field> 15914 <name>CC1NE</name> 15915 <description>Capture/Compare 1 complementary output 15916 enable</description> 15917 <bitOffset>2</bitOffset> 15918 <bitWidth>1</bitWidth> 15919 </field> 15920 <field> 15921 <name>CC1P</name> 15922 <description>Capture/Compare 1 output 15923 Polarity</description> 15924 <bitOffset>1</bitOffset> 15925 <bitWidth>1</bitWidth> 15926 </field> 15927 <field> 15928 <name>CC1E</name> 15929 <description>Capture/Compare 1 output 15930 enable</description> 15931 <bitOffset>0</bitOffset> 15932 <bitWidth>1</bitWidth> 15933 </field> 15934 </fields> 15935 </register> 15936 <register> 15937 <name>CNT</name> 15938 <displayName>CNT</displayName> 15939 <description>counter</description> 15940 <addressOffset>0x24</addressOffset> 15941 <size>0x20</size> 15942 <access>read-write</access> 15943 <resetValue>0x00000000</resetValue> 15944 <fields> 15945 <field> 15946 <name>CNT</name> 15947 <description>counter value</description> 15948 <bitOffset>0</bitOffset> 15949 <bitWidth>16</bitWidth> 15950 <writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint> 15951 </field> 15952 </fields> 15953 </register> 15954 <register> 15955 <name>PSC</name> 15956 <displayName>PSC</displayName> 15957 <description>prescaler</description> 15958 <addressOffset>0x28</addressOffset> 15959 <size>0x20</size> 15960 <access>read-write</access> 15961 <resetValue>0x0000</resetValue> 15962 <fields> 15963 <field> 15964 <name>PSC</name> 15965 <description>Prescaler value</description> 15966 <bitOffset>0</bitOffset> 15967 <bitWidth>16</bitWidth> 15968 <writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint> 15969 </field> 15970 </fields> 15971 </register> 15972 <register> 15973 <name>ARR</name> 15974 <displayName>ARR</displayName> 15975 <description>auto-reload register</description> 15976 <addressOffset>0x2C</addressOffset> 15977 <size>0x20</size> 15978 <access>read-write</access> 15979 <resetValue>0x00000000</resetValue> 15980 <fields> 15981 <field> 15982 <name>ARR</name> 15983 <description>Auto-reload value</description> 15984 <bitOffset>0</bitOffset> 15985 <bitWidth>16</bitWidth> 15986 <writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint> 15987 </field> 15988 </fields> 15989 </register> 15990 <register> 15991 <dim>4</dim><dimIncrement>0x4</dimIncrement><dimIndex>1,2,3,4</dimIndex><name>CCR%s</name> 15992 <displayName>CCR1</displayName> 15993 <description>capture/compare register</description> 15994 <addressOffset>0x34</addressOffset> 15995 <size>0x20</size> 15996 <access>read-write</access> 15997 <resetValue>0x00000000</resetValue> 15998 <fields> 15999 <field> 16000 <name>CCR</name> 16001 <description>Capture/Compare value</description> 16002 <bitOffset>0</bitOffset> 16003 <bitWidth>16</bitWidth> 16004 <writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint> 16005 </field> 16006 </fields> 16007 </register> 16008 <register> 16009 <name>DCR</name> 16010 <displayName>DCR</displayName> 16011 <description>DMA control register</description> 16012 <addressOffset>0x48</addressOffset> 16013 <size>0x20</size> 16014 <access>read-write</access> 16015 <resetValue>0x0000</resetValue> 16016 <fields> 16017 <field> 16018 <name>DBL</name> 16019 <description>DMA burst length</description> 16020 <bitOffset>8</bitOffset> 16021 <bitWidth>5</bitWidth> 16022 <writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint> 16023 </field> 16024 <field> 16025 <name>DBA</name> 16026 <description>DMA base address</description> 16027 <bitOffset>0</bitOffset> 16028 <bitWidth>5</bitWidth> 16029 <writeConstraint><range><minimum>0</minimum><maximum>31</maximum></range></writeConstraint> 16030 </field> 16031 </fields> 16032 </register> 16033 <register> 16034 <name>DMAR</name> 16035 <displayName>DMAR</displayName> 16036 <description>DMA address for full transfer</description> 16037 <addressOffset>0x4C</addressOffset> 16038 <size>0x20</size> 16039 <access>read-write</access> 16040 <resetValue>0x0000</resetValue> 16041 <fields> 16042 <field> 16043 <name>DMAB</name> 16044 <description>DMA register for burst 16045 accesses</description> 16046 <bitOffset>0</bitOffset> 16047 <bitWidth>16</bitWidth> 16048 </field> 16049 </fields> 16050 </register> 16051 <register> 16052 <name>RCR</name> 16053 <displayName>RCR</displayName> 16054 <description>repetition counter register</description> 16055 <addressOffset>0x30</addressOffset> 16056 <size>0x20</size> 16057 <access>read-write</access> 16058 <resetValue>0x0000</resetValue> 16059 <fields> 16060 <field> 16061 <name>REP</name> 16062 <description>Repetition counter value</description> 16063 <bitOffset>0</bitOffset> 16064 <bitWidth>8</bitWidth> 16065 </field> 16066 </fields> 16067 </register> 16068 <register> 16069 <name>BDTR</name> 16070 <displayName>BDTR</displayName> 16071 <description>break and dead-time register</description> 16072 <addressOffset>0x44</addressOffset> 16073 <size>0x20</size> 16074 <access>read-write</access> 16075 <resetValue>0x0000</resetValue> 16076 <fields> 16077 <field> 16078 <name>MOE</name> 16079 <description>Main output enable</description> 16080 <bitOffset>15</bitOffset> 16081 <bitWidth>1</bitWidth> 16082 <enumeratedValues><name>MOE</name><usage>read-write</usage><enumeratedValue><name>DisabledIdle</name><description>OC/OCN are disabled or forced idle depending on OSSI</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>OC/OCN are enabled if CCxE/CCxNE are set</description><value>1</value></enumeratedValue></enumeratedValues> 16083 </field> 16084 <field> 16085 <name>AOE</name> 16086 <description>Automatic output enable</description> 16087 <bitOffset>14</bitOffset> 16088 <bitWidth>1</bitWidth> 16089 </field> 16090 <field> 16091 <name>BKP</name> 16092 <description>Break polarity</description> 16093 <bitOffset>13</bitOffset> 16094 <bitWidth>1</bitWidth> 16095 </field> 16096 <field> 16097 <name>BKE</name> 16098 <description>Break enable</description> 16099 <bitOffset>12</bitOffset> 16100 <bitWidth>1</bitWidth> 16101 </field> 16102 <field> 16103 <name>OSSR</name> 16104 <description>Off-state selection for Run 16105 mode</description> 16106 <bitOffset>11</bitOffset> 16107 <bitWidth>1</bitWidth> 16108 <enumeratedValues><name>OSSR</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>When inactive, OC/OCN outputs are disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>IdleLevel</name><description>When inactive, OC/OCN outputs are enabled with their inactive level</description><value>1</value></enumeratedValue></enumeratedValues> 16109 </field> 16110 <field> 16111 <name>OSSI</name> 16112 <description>Off-state selection for Idle 16113 mode</description> 16114 <bitOffset>10</bitOffset> 16115 <bitWidth>1</bitWidth> 16116 <enumeratedValues><name>OSSI</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>When inactive, OC/OCN outputs are disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>IdleLevel</name><description>When inactive, OC/OCN outputs are forced to idle level</description><value>1</value></enumeratedValue></enumeratedValues> 16117 </field> 16118 <field> 16119 <name>LOCK</name> 16120 <description>Lock configuration</description> 16121 <bitOffset>8</bitOffset> 16122 <bitWidth>2</bitWidth> 16123 </field> 16124 <field> 16125 <name>DTG</name> 16126 <description>Dead-time generator setup</description> 16127 <bitOffset>0</bitOffset> 16128 <bitWidth>8</bitWidth> 16129 </field> 16130 </fields> 16131 </register> 16132 </registers> 16133 </peripheral> 16134 <peripheral derivedFrom="TIM1"> 16135 <name>TIM8</name> 16136 <baseAddress>0x40010400</baseAddress> 16137 <interrupt> 16138 <name>TIM8_BRK_TIM12</name> 16139 <description>TIM8 Break interrupt and TIM12 global 16140 interrupt</description> 16141 <value>43</value> 16142 </interrupt> 16143 <interrupt> 16144 <name>TIM8_UP_TIM13</name> 16145 <description>TIM8 Update interrupt and TIM13 global 16146 interrupt</description> 16147 <value>44</value> 16148 </interrupt> 16149 <interrupt> 16150 <name>TIM8_TRG_COM_TIM14</name> 16151 <description>TIM8 Trigger and Commutation interrupts and 16152 TIM14 global interrupt</description> 16153 <value>45</value> 16154 </interrupt> 16155 <interrupt> 16156 <name>TIM8_CC</name> 16157 <description>TIM8 Capture Compare interrupt</description> 16158 <value>46</value> 16159 </interrupt> 16160 </peripheral> 16161 <peripheral> 16162 <name>TIM2</name> 16163 <description>General purpose timers</description> 16164 <groupName>TIM</groupName> 16165 <baseAddress>0x40000000</baseAddress> 16166 <addressBlock> 16167 <offset>0x0</offset> 16168 <size>0x400</size> 16169 <usage>registers</usage> 16170 </addressBlock> 16171 <interrupt> 16172 <name>TIM2</name> 16173 <description>TIM2 global interrupt</description> 16174 <value>28</value> 16175 </interrupt> 16176 <registers> 16177 <register> 16178 <name>CR1</name> 16179 <displayName>CR1</displayName> 16180 <description>control register 1</description> 16181 <addressOffset>0x0</addressOffset> 16182 <size>0x20</size> 16183 <access>read-write</access> 16184 <resetValue>0x0000</resetValue> 16185 <fields> 16186 <field> 16187 <name>CKD</name> 16188 <description>Clock division</description> 16189 <bitOffset>8</bitOffset> 16190 <bitWidth>2</bitWidth> 16191 <enumeratedValues><name>CKD</name><usage>read-write</usage><enumeratedValue><name>Div1</name><description>t_DTS = t_CK_INT</description><value>0</value></enumeratedValue><enumeratedValue><name>Div2</name><description>t_DTS = 2 × t_CK_INT</description><value>1</value></enumeratedValue><enumeratedValue><name>Div4</name><description>t_DTS = 4 × t_CK_INT</description><value>2</value></enumeratedValue></enumeratedValues> 16192 </field> 16193 <field> 16194 <name>ARPE</name> 16195 <description>Auto-reload preload enable</description> 16196 <bitOffset>7</bitOffset> 16197 <bitWidth>1</bitWidth> 16198 <enumeratedValues><name>ARPE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>TIMx_APRR register is not buffered</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>TIMx_APRR register is buffered</description><value>1</value></enumeratedValue></enumeratedValues> 16199 </field> 16200 <field> 16201 <name>CMS</name> 16202 <description>Center-aligned mode 16203 selection</description> 16204 <bitOffset>5</bitOffset> 16205 <bitWidth>2</bitWidth> 16206 <enumeratedValues><name>CMS</name><usage>read-write</usage><enumeratedValue><name>EdgeAligned</name><description>The counter counts up or down depending on the direction bit</description><value>0</value></enumeratedValue><enumeratedValue><name>CenterAligned1</name><description>The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.</description><value>1</value></enumeratedValue><enumeratedValue><name>CenterAligned2</name><description>The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.</description><value>2</value></enumeratedValue><enumeratedValue><name>CenterAligned3</name><description>The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.</description><value>3</value></enumeratedValue></enumeratedValues> 16207 </field> 16208 <field> 16209 <name>DIR</name> 16210 <description>Direction</description> 16211 <bitOffset>4</bitOffset> 16212 <bitWidth>1</bitWidth> 16213 <enumeratedValues><name>DIR</name><usage>read-write</usage><enumeratedValue><name>Up</name><description>Counter used as upcounter</description><value>0</value></enumeratedValue><enumeratedValue><name>Down</name><description>Counter used as downcounter</description><value>1</value></enumeratedValue></enumeratedValues> 16214 </field> 16215 <field> 16216 <name>OPM</name> 16217 <description>One-pulse mode</description> 16218 <bitOffset>3</bitOffset> 16219 <bitWidth>1</bitWidth> 16220 <enumeratedValues><name>OPM</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Counter is not stopped at update event</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Counter stops counting at the next update event (clearing the CEN bit)</description><value>1</value></enumeratedValue></enumeratedValues> 16221 </field> 16222 <field> 16223 <name>URS</name> 16224 <description>Update request source</description> 16225 <bitOffset>2</bitOffset> 16226 <bitWidth>1</bitWidth> 16227 <enumeratedValues><name>URS</name><usage>read-write</usage><enumeratedValue><name>AnyEvent</name><description>Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request</description><value>0</value></enumeratedValue><enumeratedValue><name>CounterOnly</name><description>Only counter overflow/underflow generates an update interrupt or DMA request</description><value>1</value></enumeratedValue></enumeratedValues> 16228 </field> 16229 <field> 16230 <name>UDIS</name> 16231 <description>Update disable</description> 16232 <bitOffset>1</bitOffset> 16233 <bitWidth>1</bitWidth> 16234 <enumeratedValues><name>UDIS</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>Update event enabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>Update event disabled</description><value>1</value></enumeratedValue></enumeratedValues> 16235 </field> 16236 <field> 16237 <name>CEN</name> 16238 <description>Counter enable</description> 16239 <bitOffset>0</bitOffset> 16240 <bitWidth>1</bitWidth> 16241 <enumeratedValues><name>CEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Counter disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Counter enabled</description><value>1</value></enumeratedValue></enumeratedValues> 16242 </field> 16243 </fields> 16244 </register> 16245 <register> 16246 <name>CR2</name> 16247 <displayName>CR2</displayName> 16248 <description>control register 2</description> 16249 <addressOffset>0x4</addressOffset> 16250 <size>0x20</size> 16251 <access>read-write</access> 16252 <resetValue>0x0000</resetValue> 16253 <fields> 16254 <field> 16255 <name>TI1S</name> 16256 <description>TI1 selection</description> 16257 <bitOffset>7</bitOffset> 16258 <bitWidth>1</bitWidth> 16259 <enumeratedValues><name>TI1S</name><usage>read-write</usage><enumeratedValue><name>Normal</name><description>The TIMx_CH1 pin is connected to TI1 input</description><value>0</value></enumeratedValue><enumeratedValue><name>XOR</name><description>The TIMx_CH1, CH2, CH3 pins are connected to TI1 input</description><value>1</value></enumeratedValue></enumeratedValues> 16260 </field> 16261 <field> 16262 <name>MMS</name> 16263 <description>Master mode selection</description> 16264 <bitOffset>4</bitOffset> 16265 <bitWidth>3</bitWidth> 16266 <enumeratedValues><name>MMS</name><usage>read-write</usage><enumeratedValue><name>Reset</name><description>The UG bit from the TIMx_EGR register is used as trigger output</description><value>0</value></enumeratedValue><enumeratedValue><name>Enable</name><description>The counter enable signal, CNT_EN, is used as trigger output</description><value>1</value></enumeratedValue><enumeratedValue><name>Update</name><description>The update event is selected as trigger output</description><value>2</value></enumeratedValue><enumeratedValue><name>ComparePulse</name><description>The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred</description><value>3</value></enumeratedValue><enumeratedValue><name>CompareOC1</name><description>OC1REF signal is used as trigger output</description><value>4</value></enumeratedValue><enumeratedValue><name>CompareOC2</name><description>OC2REF signal is used as trigger output</description><value>5</value></enumeratedValue><enumeratedValue><name>CompareOC3</name><description>OC3REF signal is used as trigger output</description><value>6</value></enumeratedValue><enumeratedValue><name>CompareOC4</name><description>OC4REF signal is used as trigger output</description><value>7</value></enumeratedValue></enumeratedValues> 16267 </field> 16268 <field> 16269 <name>CCDS</name> 16270 <description>Capture/compare DMA 16271 selection</description> 16272 <bitOffset>3</bitOffset> 16273 <bitWidth>1</bitWidth> 16274 <enumeratedValues><name>CCDS</name><usage>read-write</usage><enumeratedValue><name>OnCompare</name><description>CCx DMA request sent when CCx event occurs</description><value>0</value></enumeratedValue><enumeratedValue><name>OnUpdate</name><description>CCx DMA request sent when update event occurs</description><value>1</value></enumeratedValue></enumeratedValues> 16275 </field> 16276 </fields> 16277 </register> 16278 <register> 16279 <name>SMCR</name> 16280 <displayName>SMCR</displayName> 16281 <description>slave mode control register</description> 16282 <addressOffset>0x8</addressOffset> 16283 <size>0x20</size> 16284 <access>read-write</access> 16285 <resetValue>0x0000</resetValue> 16286 <fields> 16287 <field> 16288 <name>ETP</name> 16289 <description>External trigger polarity</description> 16290 <bitOffset>15</bitOffset> 16291 <bitWidth>1</bitWidth> 16292 <enumeratedValues><name>ETP</name><usage>read-write</usage><enumeratedValue><name>NotInverted</name><description>ETR is noninverted, active at high level or rising edge</description><value>0</value></enumeratedValue><enumeratedValue><name>Inverted</name><description>ETR is inverted, active at low level or falling edge</description><value>1</value></enumeratedValue></enumeratedValues> 16293 </field> 16294 <field> 16295 <name>ECE</name> 16296 <description>External clock enable</description> 16297 <bitOffset>14</bitOffset> 16298 <bitWidth>1</bitWidth> 16299 <enumeratedValues><name>ECE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>External clock mode 2 disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.</description><value>1</value></enumeratedValue></enumeratedValues> 16300 </field> 16301 <field> 16302 <name>ETPS</name> 16303 <description>External trigger prescaler</description> 16304 <bitOffset>12</bitOffset> 16305 <bitWidth>2</bitWidth> 16306 <enumeratedValues><name>ETPS</name><usage>read-write</usage><enumeratedValue><name>Div1</name><description>Prescaler OFF</description><value>0</value></enumeratedValue><enumeratedValue><name>Div2</name><description>ETRP frequency divided by 2</description><value>1</value></enumeratedValue><enumeratedValue><name>Div4</name><description>ETRP frequency divided by 4</description><value>2</value></enumeratedValue><enumeratedValue><name>Div8</name><description>ETRP frequency divided by 8</description><value>3</value></enumeratedValue></enumeratedValues> 16307 </field> 16308 <field> 16309 <name>ETF</name> 16310 <description>External trigger filter</description> 16311 <bitOffset>8</bitOffset> 16312 <bitWidth>4</bitWidth> 16313 <enumeratedValues><name>ETF</name><usage>read-write</usage><enumeratedValue><name>NoFilter</name><description>No filter, sampling is done at fDTS</description><value>0</value></enumeratedValue><enumeratedValue><name>FCK_INT_N2</name><description>fSAMPLING=fCK_INT, N=2</description><value>1</value></enumeratedValue><enumeratedValue><name>FCK_INT_N4</name><description>fSAMPLING=fCK_INT, N=4</description><value>2</value></enumeratedValue><enumeratedValue><name>FCK_INT_N8</name><description>fSAMPLING=fCK_INT, N=8</description><value>3</value></enumeratedValue><enumeratedValue><name>FDTS_Div2_N6</name><description>fSAMPLING=fDTS/2, N=6</description><value>4</value></enumeratedValue><enumeratedValue><name>FDTS_Div2_N8</name><description>fSAMPLING=fDTS/2, N=8</description><value>5</value></enumeratedValue><enumeratedValue><name>FDTS_Div4_N6</name><description>fSAMPLING=fDTS/4, N=6</description><value>6</value></enumeratedValue><enumeratedValue><name>FDTS_Div4_N8</name><description>fSAMPLING=fDTS/4, N=8</description><value>7</value></enumeratedValue><enumeratedValue><name>FDTS_Div8_N6</name><description>fSAMPLING=fDTS/8, N=6</description><value>8</value></enumeratedValue><enumeratedValue><name>FDTS_Div8_N8</name><description>fSAMPLING=fDTS/8, N=8</description><value>9</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N5</name><description>fSAMPLING=fDTS/16, N=5</description><value>10</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N6</name><description>fSAMPLING=fDTS/16, N=6</description><value>11</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N8</name><description>fSAMPLING=fDTS/16, N=8</description><value>12</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N5</name><description>fSAMPLING=fDTS/32, N=5</description><value>13</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N6</name><description>fSAMPLING=fDTS/32, N=6</description><value>14</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N8</name><description>fSAMPLING=fDTS/32, N=8</description><value>15</value></enumeratedValue></enumeratedValues> 16314 </field> 16315 <field> 16316 <name>MSM</name> 16317 <description>Master/Slave mode</description> 16318 <bitOffset>7</bitOffset> 16319 <bitWidth>1</bitWidth> 16320 <enumeratedValues><name>MSM</name><usage>read-write</usage><enumeratedValue><name>NoSync</name><description>No action</description><value>0</value></enumeratedValue><enumeratedValue><name>Sync</name><description>The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.</description><value>1</value></enumeratedValue></enumeratedValues> 16321 </field> 16322 <field> 16323 <name>TS</name> 16324 <description>Trigger selection</description> 16325 <bitOffset>4</bitOffset> 16326 <bitWidth>3</bitWidth> 16327 <enumeratedValues><name>TS</name><usage>read-write</usage><enumeratedValue><name>ITR0</name><description>Internal Trigger 0 (ITR0)</description><value>0</value></enumeratedValue><enumeratedValue><name>ITR1</name><description>Internal Trigger 1 (ITR1)</description><value>1</value></enumeratedValue><enumeratedValue><name>ITR2</name><description>Internal Trigger 2 (ITR2)</description><value>2</value></enumeratedValue><enumeratedValue><name>TI1F_ED</name><description>TI1 Edge Detector (TI1F_ED)</description><value>4</value></enumeratedValue><enumeratedValue><name>TI1FP1</name><description>Filtered Timer Input 1 (TI1FP1)</description><value>5</value></enumeratedValue><enumeratedValue><name>TI2FP2</name><description>Filtered Timer Input 2 (TI2FP2)</description><value>6</value></enumeratedValue><enumeratedValue><name>ETRF</name><description>External Trigger input (ETRF)</description><value>7</value></enumeratedValue></enumeratedValues> 16328 </field> 16329 <field> 16330 <name>SMS</name> 16331 <description>Slave mode selection</description> 16332 <bitOffset>0</bitOffset> 16333 <bitWidth>3</bitWidth> 16334 <enumeratedValues><name>SMS</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.</description><value>0</value></enumeratedValue><enumeratedValue><name>Encoder_Mode_1</name><description>Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.</description><value>1</value></enumeratedValue><enumeratedValue><name>Encoder_Mode_2</name><description>Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.</description><value>2</value></enumeratedValue><enumeratedValue><name>Encoder_Mode_3</name><description>Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.</description><value>3</value></enumeratedValue><enumeratedValue><name>Reset_Mode</name><description>Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.</description><value>4</value></enumeratedValue><enumeratedValue><name>Gated_Mode</name><description>Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.</description><value>5</value></enumeratedValue><enumeratedValue><name>Trigger_Mode</name><description>Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.</description><value>6</value></enumeratedValue><enumeratedValue><name>Ext_Clock_Mode</name><description>External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.</description><value>7</value></enumeratedValue></enumeratedValues> 16335 </field> 16336 </fields> 16337 </register> 16338 <register> 16339 <name>DIER</name> 16340 <displayName>DIER</displayName> 16341 <description>DMA/Interrupt enable register</description> 16342 <addressOffset>0xC</addressOffset> 16343 <size>0x20</size> 16344 <access>read-write</access> 16345 <resetValue>0x0000</resetValue> 16346 <fields> 16347 <field> 16348 <name>TDE</name> 16349 <description>Trigger DMA request enable</description> 16350 <bitOffset>14</bitOffset> 16351 <bitWidth>1</bitWidth> 16352 <enumeratedValues><name>TDE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Trigger DMA request disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Trigger DMA request enabled</description><value>1</value></enumeratedValue></enumeratedValues> 16353 </field> 16354 <field> 16355 <name>CC4DE</name> 16356 <description>Capture/Compare 4 DMA request 16357 enable</description> 16358 <bitOffset>12</bitOffset> 16359 <bitWidth>1</bitWidth> 16360 <enumeratedValues derivedFrom="CC1DE"/> 16361 </field> 16362 <field> 16363 <name>CC3DE</name> 16364 <description>Capture/Compare 3 DMA request 16365 enable</description> 16366 <bitOffset>11</bitOffset> 16367 <bitWidth>1</bitWidth> 16368 <enumeratedValues derivedFrom="CC1DE"/> 16369 </field> 16370 <field> 16371 <name>CC2DE</name> 16372 <description>Capture/Compare 2 DMA request 16373 enable</description> 16374 <bitOffset>10</bitOffset> 16375 <bitWidth>1</bitWidth> 16376 <enumeratedValues derivedFrom="CC1DE"/> 16377 </field> 16378 <field> 16379 <name>CC1DE</name> 16380 <description>Capture/Compare 1 DMA request 16381 enable</description> 16382 <bitOffset>9</bitOffset> 16383 <bitWidth>1</bitWidth> 16384 <enumeratedValues><name>CC1DE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>CCx DMA request disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>CCx DMA request enabled</description><value>1</value></enumeratedValue></enumeratedValues> 16385 </field> 16386 <field> 16387 <name>UDE</name> 16388 <description>Update DMA request enable</description> 16389 <bitOffset>8</bitOffset> 16390 <bitWidth>1</bitWidth> 16391 <enumeratedValues><name>UDE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Update DMA request disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Update DMA request enabled</description><value>1</value></enumeratedValue></enumeratedValues> 16392 </field> 16393 <field> 16394 <name>TIE</name> 16395 <description>Trigger interrupt enable</description> 16396 <bitOffset>6</bitOffset> 16397 <bitWidth>1</bitWidth> 16398 <enumeratedValues><name>TIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Trigger interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Trigger interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 16399 </field> 16400 <field> 16401 <name>CC4IE</name> 16402 <description>Capture/Compare 4 interrupt 16403 enable</description> 16404 <bitOffset>4</bitOffset> 16405 <bitWidth>1</bitWidth> 16406 <enumeratedValues derivedFrom="CC1IE"/> 16407 </field> 16408 <field> 16409 <name>CC3IE</name> 16410 <description>Capture/Compare 3 interrupt 16411 enable</description> 16412 <bitOffset>3</bitOffset> 16413 <bitWidth>1</bitWidth> 16414 <enumeratedValues derivedFrom="CC1IE"/> 16415 </field> 16416 <field> 16417 <name>CC2IE</name> 16418 <description>Capture/Compare 2 interrupt 16419 enable</description> 16420 <bitOffset>2</bitOffset> 16421 <bitWidth>1</bitWidth> 16422 <enumeratedValues derivedFrom="CC1IE"/> 16423 </field> 16424 <field> 16425 <name>CC1IE</name> 16426 <description>Capture/Compare 1 interrupt 16427 enable</description> 16428 <bitOffset>1</bitOffset> 16429 <bitWidth>1</bitWidth> 16430 <enumeratedValues><name>CC1IE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>CCx interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>CCx interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 16431 </field> 16432 <field> 16433 <name>UIE</name> 16434 <description>Update interrupt enable</description> 16435 <bitOffset>0</bitOffset> 16436 <bitWidth>1</bitWidth> 16437 <enumeratedValues><name>UIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Update interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Update interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 16438 </field> 16439 </fields> 16440 </register> 16441 <register> 16442 <name>SR</name> 16443 <displayName>SR</displayName> 16444 <description>status register</description> 16445 <addressOffset>0x10</addressOffset> 16446 <size>0x20</size> 16447 <access>read-write</access> 16448 <resetValue>0x0000</resetValue> 16449 <fields> 16450 <field> 16451 <name>CC4OF</name> 16452 <description>Capture/Compare 4 overcapture 16453 flag</description> 16454 <bitOffset>12</bitOffset> 16455 <bitWidth>1</bitWidth> 16456 <enumeratedValues derivedFrom="CC1OFR"/> 16457 <enumeratedValues derivedFrom="CC1OFW"/> 16458 </field> 16459 <field> 16460 <name>CC3OF</name> 16461 <description>Capture/Compare 3 overcapture 16462 flag</description> 16463 <bitOffset>11</bitOffset> 16464 <bitWidth>1</bitWidth> 16465 <enumeratedValues derivedFrom="CC1OFR"/> 16466 <enumeratedValues derivedFrom="CC1OFW"/> 16467 </field> 16468 <field> 16469 <name>CC2OF</name> 16470 <description>Capture/compare 2 overcapture 16471 flag</description> 16472 <bitOffset>10</bitOffset> 16473 <bitWidth>1</bitWidth> 16474 <enumeratedValues derivedFrom="CC1OFR"/> 16475 <enumeratedValues derivedFrom="CC1OFW"/> 16476 </field> 16477 <field> 16478 <name>CC1OF</name> 16479 <description>Capture/Compare 1 overcapture 16480 flag</description> 16481 <bitOffset>9</bitOffset> 16482 <bitWidth>1</bitWidth> 16483 <enumeratedValues><name>CC1OFR</name><usage>read</usage><enumeratedValue><name>Overcapture</name><description>The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set</description><value>1</value></enumeratedValue></enumeratedValues> 16484 <enumeratedValues><name>CC1OFW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clear flag</description><value>0</value></enumeratedValue></enumeratedValues> 16485 </field> 16486 <field> 16487 <name>TIF</name> 16488 <description>Trigger interrupt flag</description> 16489 <bitOffset>6</bitOffset> 16490 <bitWidth>1</bitWidth> 16491 <enumeratedValues><name>TIFR</name><usage>read</usage><enumeratedValue><name>NoTrigger</name><description>No trigger event occurred</description><value>0</value></enumeratedValue><enumeratedValue><name>Trigger</name><description>Trigger interrupt pending</description><value>1</value></enumeratedValue></enumeratedValues> 16492 <enumeratedValues><name>TIFW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clear flag</description><value>0</value></enumeratedValue></enumeratedValues> 16493 </field> 16494 <field> 16495 <name>CC4IF</name> 16496 <description>Capture/Compare 4 interrupt 16497 flag</description> 16498 <bitOffset>4</bitOffset> 16499 <bitWidth>1</bitWidth> 16500 <enumeratedValues derivedFrom="CC1IFR"/> 16501 <enumeratedValues derivedFrom="CC1IFW"/> 16502 </field> 16503 <field> 16504 <name>CC3IF</name> 16505 <description>Capture/Compare 3 interrupt 16506 flag</description> 16507 <bitOffset>3</bitOffset> 16508 <bitWidth>1</bitWidth> 16509 <enumeratedValues derivedFrom="CC1IFR"/> 16510 <enumeratedValues derivedFrom="CC1IFW"/> 16511 </field> 16512 <field> 16513 <name>CC2IF</name> 16514 <description>Capture/Compare 2 interrupt 16515 flag</description> 16516 <bitOffset>2</bitOffset> 16517 <bitWidth>1</bitWidth> 16518 <enumeratedValues derivedFrom="CC1IFR"/> 16519 <enumeratedValues derivedFrom="CC1IFW"/> 16520 </field> 16521 <field> 16522 <name>CC1IF</name> 16523 <description>Capture/compare 1 interrupt 16524 flag</description> 16525 <bitOffset>1</bitOffset> 16526 <bitWidth>1</bitWidth> 16527 <enumeratedValues><name>CC1IFR</name><usage>read</usage><enumeratedValue><name>Match</name><description>If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.</description><value>1</value></enumeratedValue></enumeratedValues> 16528 <enumeratedValues><name>CC1IFW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clear flag</description><value>0</value></enumeratedValue></enumeratedValues> 16529 </field> 16530 <field> 16531 <name>UIF</name> 16532 <description>Update interrupt flag</description> 16533 <bitOffset>0</bitOffset> 16534 <bitWidth>1</bitWidth> 16535 <enumeratedValues><name>UIF</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>No update occurred</description><value>0</value></enumeratedValue><enumeratedValue><name>UpdatePending</name><description>Update interrupt pending.</description><value>1</value></enumeratedValue></enumeratedValues> 16536 </field> 16537 </fields> 16538 </register> 16539 <register> 16540 <name>EGR</name> 16541 <displayName>EGR</displayName> 16542 <description>event generation register</description> 16543 <addressOffset>0x14</addressOffset> 16544 <size>0x20</size> 16545 <access>write-only</access> 16546 <resetValue>0x0000</resetValue> 16547 <fields> 16548 <field> 16549 <name>TG</name> 16550 <description>Trigger generation</description> 16551 <bitOffset>6</bitOffset> 16552 <bitWidth>1</bitWidth> 16553 <enumeratedValues><name>TGW</name><usage>write</usage><enumeratedValue><name>Trigger</name><description>The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.</description><value>1</value></enumeratedValue></enumeratedValues> 16554 </field> 16555 <field> 16556 <name>CC4G</name> 16557 <description>Capture/compare 4 16558 generation</description> 16559 <bitOffset>4</bitOffset> 16560 <bitWidth>1</bitWidth> 16561 <enumeratedValues derivedFrom="CC1GW"/> 16562 </field> 16563 <field> 16564 <name>CC3G</name> 16565 <description>Capture/compare 3 16566 generation</description> 16567 <bitOffset>3</bitOffset> 16568 <bitWidth>1</bitWidth> 16569 <enumeratedValues derivedFrom="CC1GW"/> 16570 </field> 16571 <field> 16572 <name>CC2G</name> 16573 <description>Capture/compare 2 16574 generation</description> 16575 <bitOffset>2</bitOffset> 16576 <bitWidth>1</bitWidth> 16577 <enumeratedValues derivedFrom="CC1GW"/> 16578 </field> 16579 <field> 16580 <name>CC1G</name> 16581 <description>Capture/compare 1 16582 generation</description> 16583 <bitOffset>1</bitOffset> 16584 <bitWidth>1</bitWidth> 16585 <enumeratedValues><name>CC1GW</name><usage>write</usage><enumeratedValue><name>Trigger</name><description>If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.</description><value>1</value></enumeratedValue></enumeratedValues> 16586 </field> 16587 <field> 16588 <name>UG</name> 16589 <description>Update generation</description> 16590 <bitOffset>0</bitOffset> 16591 <bitWidth>1</bitWidth> 16592 <enumeratedValues><name>UG</name><usage>read-write</usage><enumeratedValue><name>Update</name><description>Re-initializes the timer counter and generates an update of the registers.</description><value>1</value></enumeratedValue></enumeratedValues> 16593 </field> 16594 </fields> 16595 </register> 16596 <register> 16597 <name>CCMR1_Output</name> 16598 <displayName>CCMR1_Output</displayName> 16599 <description>capture/compare mode register 1 (output 16600 mode)</description> 16601 <addressOffset>0x18</addressOffset> 16602 <size>0x20</size> 16603 <access>read-write</access> 16604 <resetValue>0x00000000</resetValue> 16605 <fields> 16606 <field> 16607 <name>OC2CE</name> 16608 <description>OC2CE</description> 16609 <bitOffset>15</bitOffset> 16610 <bitWidth>1</bitWidth> 16611 </field> 16612 <field> 16613 <name>OC2M</name> 16614 <description>OC2M</description> 16615 <bitOffset>12</bitOffset> 16616 <bitWidth>3</bitWidth> 16617 <enumeratedValues derivedFrom="OC1M"/> 16618 </field> 16619 <field> 16620 <name>OC2PE</name> 16621 <description>OC2PE</description> 16622 <bitOffset>11</bitOffset> 16623 <bitWidth>1</bitWidth> 16624 <enumeratedValues><name>OC2PE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Preload register on CCR2 enabled. Preload value is loaded into active register on each update event</description><value>1</value></enumeratedValue></enumeratedValues> 16625 </field> 16626 <field> 16627 <name>OC2FE</name> 16628 <description>OC2FE</description> 16629 <bitOffset>10</bitOffset> 16630 <bitWidth>1</bitWidth> 16631 </field> 16632 <field> 16633 <name>CC2S</name> 16634 <description>CC2S</description> 16635 <bitOffset>8</bitOffset> 16636 <bitWidth>2</bitWidth> 16637 <enumeratedValues><name>CC2S</name><usage>read-write</usage><enumeratedValue><name>Output</name><description>CC2 channel is configured as output</description><value>0</value></enumeratedValue></enumeratedValues> 16638 </field> 16639 <field> 16640 <name>OC1CE</name> 16641 <description>OC1CE</description> 16642 <bitOffset>7</bitOffset> 16643 <bitWidth>1</bitWidth> 16644 </field> 16645 <field> 16646 <name>OC1M</name> 16647 <description>OC1M</description> 16648 <bitOffset>4</bitOffset> 16649 <bitWidth>3</bitWidth> 16650 <enumeratedValues><name>OC1M</name><usage>read-write</usage><enumeratedValue><name>Frozen</name><description>The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs</description><value>0</value></enumeratedValue><enumeratedValue><name>ActiveOnMatch</name><description>Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register</description><value>1</value></enumeratedValue><enumeratedValue><name>InactiveOnMatch</name><description>Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register</description><value>2</value></enumeratedValue><enumeratedValue><name>Toggle</name><description>OCyREF toggles when TIMx_CNT=TIMx_CCRy</description><value>3</value></enumeratedValue><enumeratedValue><name>ForceInactive</name><description>OCyREF is forced low</description><value>4</value></enumeratedValue><enumeratedValue><name>ForceActive</name><description>OCyREF is forced high</description><value>5</value></enumeratedValue><enumeratedValue><name>PwmMode1</name><description>In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active</description><value>6</value></enumeratedValue><enumeratedValue><name>PwmMode2</name><description>Inversely to PwmMode1</description><value>7</value></enumeratedValue></enumeratedValues> 16651 </field> 16652 <field> 16653 <name>OC1PE</name> 16654 <description>OC1PE</description> 16655 <bitOffset>3</bitOffset> 16656 <bitWidth>1</bitWidth> 16657 <enumeratedValues><name>OC1PE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Preload register on CCR1 enabled. Preload value is loaded into active register on each update event</description><value>1</value></enumeratedValue></enumeratedValues> 16658 </field> 16659 <field> 16660 <name>OC1FE</name> 16661 <description>OC1FE</description> 16662 <bitOffset>2</bitOffset> 16663 <bitWidth>1</bitWidth> 16664 </field> 16665 <field> 16666 <name>CC1S</name> 16667 <description>CC1S</description> 16668 <bitOffset>0</bitOffset> 16669 <bitWidth>2</bitWidth> 16670 <enumeratedValues><name>CC1S</name><usage>read-write</usage><enumeratedValue><name>Output</name><description>CC1 channel is configured as output</description><value>0</value></enumeratedValue></enumeratedValues> 16671 </field> 16672 </fields> 16673 </register> 16674 <register> 16675 <name>CCMR1_Input</name> 16676 <displayName>CCMR1_Input</displayName> 16677 <description>capture/compare mode register 1 (input 16678 mode)</description> 16679 <alternateRegister>CCMR1_Output</alternateRegister> 16680 <addressOffset>0x18</addressOffset> 16681 <size>0x20</size> 16682 <access>read-write</access> 16683 <resetValue>0x00000000</resetValue> 16684 <fields> 16685 <field> 16686 <name>IC2F</name> 16687 <description>Input capture 2 filter</description> 16688 <bitOffset>12</bitOffset> 16689 <bitWidth>4</bitWidth> 16690 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 16691 </field> 16692 <field> 16693 <name>IC2PSC</name> 16694 <description>Input capture 2 prescaler</description> 16695 <bitOffset>10</bitOffset> 16696 <bitWidth>2</bitWidth> 16697 </field> 16698 <field> 16699 <name>CC2S</name> 16700 <description>Capture/Compare 2 16701 selection</description> 16702 <bitOffset>8</bitOffset> 16703 <bitWidth>2</bitWidth> 16704 <enumeratedValues><name>CC2S</name><usage>read-write</usage><enumeratedValue><name>TI2</name><description>CC2 channel is configured as input, IC2 is mapped on TI2</description><value>1</value></enumeratedValue><enumeratedValue><name>TI1</name><description>CC2 channel is configured as input, IC2 is mapped on TI1</description><value>2</value></enumeratedValue><enumeratedValue><name>TRC</name><description>CC2 channel is configured as input, IC2 is mapped on TRC</description><value>3</value></enumeratedValue></enumeratedValues> 16705 </field> 16706 <field> 16707 <name>IC1F</name> 16708 <description>Input capture 1 filter</description> 16709 <bitOffset>4</bitOffset> 16710 <bitWidth>4</bitWidth> 16711 <enumeratedValues><name>IC1F</name><usage>read-write</usage><enumeratedValue><name>NoFilter</name><description>No filter, sampling is done at fDTS</description><value>0</value></enumeratedValue><enumeratedValue><name>FCK_INT_N2</name><description>fSAMPLING=fCK_INT, N=2</description><value>1</value></enumeratedValue><enumeratedValue><name>FCK_INT_N4</name><description>fSAMPLING=fCK_INT, N=4</description><value>2</value></enumeratedValue><enumeratedValue><name>FCK_INT_N8</name><description>fSAMPLING=fCK_INT, N=8</description><value>3</value></enumeratedValue><enumeratedValue><name>FDTS_Div2_N6</name><description>fSAMPLING=fDTS/2, N=6</description><value>4</value></enumeratedValue><enumeratedValue><name>FDTS_Div2_N8</name><description>fSAMPLING=fDTS/2, N=8</description><value>5</value></enumeratedValue><enumeratedValue><name>FDTS_Div4_N6</name><description>fSAMPLING=fDTS/4, N=6</description><value>6</value></enumeratedValue><enumeratedValue><name>FDTS_Div4_N8</name><description>fSAMPLING=fDTS/4, N=8</description><value>7</value></enumeratedValue><enumeratedValue><name>FDTS_Div8_N6</name><description>fSAMPLING=fDTS/8, N=6</description><value>8</value></enumeratedValue><enumeratedValue><name>FDTS_Div8_N8</name><description>fSAMPLING=fDTS/8, N=8</description><value>9</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N5</name><description>fSAMPLING=fDTS/16, N=5</description><value>10</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N6</name><description>fSAMPLING=fDTS/16, N=6</description><value>11</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N8</name><description>fSAMPLING=fDTS/16, N=8</description><value>12</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N5</name><description>fSAMPLING=fDTS/32, N=5</description><value>13</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N6</name><description>fSAMPLING=fDTS/32, N=6</description><value>14</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N8</name><description>fSAMPLING=fDTS/32, N=8</description><value>15</value></enumeratedValue></enumeratedValues> 16712 </field> 16713 <field> 16714 <name>IC1PSC</name> 16715 <description>Input capture 1 prescaler</description> 16716 <bitOffset>2</bitOffset> 16717 <bitWidth>2</bitWidth> 16718 </field> 16719 <field> 16720 <name>CC1S</name> 16721 <description>Capture/Compare 1 16722 selection</description> 16723 <bitOffset>0</bitOffset> 16724 <bitWidth>2</bitWidth> 16725 <enumeratedValues><name>CC1S</name><usage>read-write</usage><enumeratedValue><name>TI1</name><description>CC1 channel is configured as input, IC1 is mapped on TI1</description><value>1</value></enumeratedValue><enumeratedValue><name>TI2</name><description>CC1 channel is configured as input, IC1 is mapped on TI2</description><value>2</value></enumeratedValue><enumeratedValue><name>TRC</name><description>CC1 channel is configured as input, IC1 is mapped on TRC</description><value>3</value></enumeratedValue></enumeratedValues> 16726 </field> 16727 </fields> 16728 </register> 16729 <register> 16730 <name>CCMR2_Output</name> 16731 <displayName>CCMR2_Output</displayName> 16732 <description>capture/compare mode register 2 (output 16733 mode)</description> 16734 <addressOffset>0x1C</addressOffset> 16735 <size>0x20</size> 16736 <access>read-write</access> 16737 <resetValue>0x00000000</resetValue> 16738 <fields> 16739 <field> 16740 <name>OC4CE</name> 16741 <description>O24CE</description> 16742 <bitOffset>15</bitOffset> 16743 <bitWidth>1</bitWidth> 16744 </field> 16745 <field> 16746 <name>OC4M</name> 16747 <description>OC4M</description> 16748 <bitOffset>12</bitOffset> 16749 <bitWidth>3</bitWidth> 16750 <enumeratedValues derivedFrom="OC3M"/> 16751 </field> 16752 <field> 16753 <name>OC4PE</name> 16754 <description>OC4PE</description> 16755 <bitOffset>11</bitOffset> 16756 <bitWidth>1</bitWidth> 16757 <enumeratedValues><name>OC4PE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Preload register on CCR4 disabled. New values written to CCR4 are taken into account immediately</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Preload register on CCR4 enabled. Preload value is loaded into active register on each update event</description><value>1</value></enumeratedValue></enumeratedValues> 16758 </field> 16759 <field> 16760 <name>OC4FE</name> 16761 <description>OC4FE</description> 16762 <bitOffset>10</bitOffset> 16763 <bitWidth>1</bitWidth> 16764 </field> 16765 <field> 16766 <name>CC4S</name> 16767 <description>CC4S</description> 16768 <bitOffset>8</bitOffset> 16769 <bitWidth>2</bitWidth> 16770 <enumeratedValues><name>CC4S</name><usage>read-write</usage><enumeratedValue><name>Output</name><description>CC4 channel is configured as output</description><value>0</value></enumeratedValue></enumeratedValues> 16771 </field> 16772 <field> 16773 <name>OC3CE</name> 16774 <description>OC3CE</description> 16775 <bitOffset>7</bitOffset> 16776 <bitWidth>1</bitWidth> 16777 </field> 16778 <field> 16779 <name>OC3M</name> 16780 <description>OC3M</description> 16781 <bitOffset>4</bitOffset> 16782 <bitWidth>3</bitWidth> 16783 <enumeratedValues><name>OC3M</name><usage>read-write</usage><enumeratedValue><name>Frozen</name><description>The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs</description><value>0</value></enumeratedValue><enumeratedValue><name>ActiveOnMatch</name><description>Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register</description><value>1</value></enumeratedValue><enumeratedValue><name>InactiveOnMatch</name><description>Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register</description><value>2</value></enumeratedValue><enumeratedValue><name>Toggle</name><description>OCyREF toggles when TIMx_CNT=TIMx_CCRy</description><value>3</value></enumeratedValue><enumeratedValue><name>ForceInactive</name><description>OCyREF is forced low</description><value>4</value></enumeratedValue><enumeratedValue><name>ForceActive</name><description>OCyREF is forced high</description><value>5</value></enumeratedValue><enumeratedValue><name>PwmMode1</name><description>In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active</description><value>6</value></enumeratedValue><enumeratedValue><name>PwmMode2</name><description>Inversely to PwmMode1</description><value>7</value></enumeratedValue></enumeratedValues> 16784 </field> 16785 <field> 16786 <name>OC3PE</name> 16787 <description>OC3PE</description> 16788 <bitOffset>3</bitOffset> 16789 <bitWidth>1</bitWidth> 16790 <enumeratedValues><name>OC3PE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Preload register on CCR3 enabled. Preload value is loaded into active register on each update event</description><value>1</value></enumeratedValue></enumeratedValues> 16791 </field> 16792 <field> 16793 <name>OC3FE</name> 16794 <description>OC3FE</description> 16795 <bitOffset>2</bitOffset> 16796 <bitWidth>1</bitWidth> 16797 </field> 16798 <field> 16799 <name>CC3S</name> 16800 <description>CC3S</description> 16801 <bitOffset>0</bitOffset> 16802 <bitWidth>2</bitWidth> 16803 <enumeratedValues><name>CC3S</name><usage>read-write</usage><enumeratedValue><name>Output</name><description>CC3 channel is configured as output</description><value>0</value></enumeratedValue></enumeratedValues> 16804 </field> 16805 </fields> 16806 </register> 16807 <register> 16808 <name>CCMR2_Input</name> 16809 <displayName>CCMR2_Input</displayName> 16810 <description>capture/compare mode register 2 (input 16811 mode)</description> 16812 <alternateRegister>CCMR2_Output</alternateRegister> 16813 <addressOffset>0x1C</addressOffset> 16814 <size>0x20</size> 16815 <access>read-write</access> 16816 <resetValue>0x00000000</resetValue> 16817 <fields> 16818 <field> 16819 <name>IC4F</name> 16820 <description>Input capture 4 filter</description> 16821 <bitOffset>12</bitOffset> 16822 <bitWidth>4</bitWidth> 16823 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 16824 </field> 16825 <field> 16826 <name>IC4PSC</name> 16827 <description>Input capture 4 prescaler</description> 16828 <bitOffset>10</bitOffset> 16829 <bitWidth>2</bitWidth> 16830 <writeConstraint><range><minimum>0</minimum><maximum>3</maximum></range></writeConstraint> 16831 </field> 16832 <field> 16833 <name>CC4S</name> 16834 <description>Capture/Compare 4 16835 selection</description> 16836 <bitOffset>8</bitOffset> 16837 <bitWidth>2</bitWidth> 16838 <enumeratedValues><name>CC4S</name><usage>read-write</usage><enumeratedValue><name>TI4</name><description>CC4 channel is configured as input, IC4 is mapped on TI4</description><value>1</value></enumeratedValue><enumeratedValue><name>TI3</name><description>CC4 channel is configured as input, IC4 is mapped on TI3</description><value>2</value></enumeratedValue><enumeratedValue><name>TRC</name><description>CC4 channel is configured as input, IC4 is mapped on TRC</description><value>3</value></enumeratedValue></enumeratedValues> 16839 </field> 16840 <field> 16841 <name>IC3F</name> 16842 <description>Input capture 3 filter</description> 16843 <bitOffset>4</bitOffset> 16844 <bitWidth>4</bitWidth> 16845 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 16846 </field> 16847 <field> 16848 <name>IC3PSC</name> 16849 <description>Input capture 3 prescaler</description> 16850 <bitOffset>2</bitOffset> 16851 <bitWidth>2</bitWidth> 16852 <writeConstraint><range><minimum>0</minimum><maximum>3</maximum></range></writeConstraint> 16853 </field> 16854 <field> 16855 <name>CC3S</name> 16856 <description>Capture/compare 3 16857 selection</description> 16858 <bitOffset>0</bitOffset> 16859 <bitWidth>2</bitWidth> 16860 <enumeratedValues><name>CC3S</name><usage>read-write</usage><enumeratedValue><name>TI3</name><description>CC3 channel is configured as input, IC3 is mapped on TI3</description><value>1</value></enumeratedValue><enumeratedValue><name>TI4</name><description>CC3 channel is configured as input, IC3 is mapped on TI4</description><value>2</value></enumeratedValue><enumeratedValue><name>TRC</name><description>CC3 channel is configured as input, IC3 is mapped on TRC</description><value>3</value></enumeratedValue></enumeratedValues> 16861 </field> 16862 </fields> 16863 </register> 16864 <register> 16865 <name>CCER</name> 16866 <displayName>CCER</displayName> 16867 <description>capture/compare enable 16868 register</description> 16869 <addressOffset>0x20</addressOffset> 16870 <size>0x20</size> 16871 <access>read-write</access> 16872 <resetValue>0x0000</resetValue> 16873 <fields> 16874 <field> 16875 <name>CC4NP</name> 16876 <description>Capture/Compare 4 output 16877 Polarity</description> 16878 <bitOffset>15</bitOffset> 16879 <bitWidth>1</bitWidth> 16880 </field> 16881 <field> 16882 <name>CC4P</name> 16883 <description>Capture/Compare 3 output 16884 Polarity</description> 16885 <bitOffset>13</bitOffset> 16886 <bitWidth>1</bitWidth> 16887 </field> 16888 <field> 16889 <name>CC4E</name> 16890 <description>Capture/Compare 4 output 16891 enable</description> 16892 <bitOffset>12</bitOffset> 16893 <bitWidth>1</bitWidth> 16894 </field> 16895 <field> 16896 <name>CC3NP</name> 16897 <description>Capture/Compare 3 output 16898 Polarity</description> 16899 <bitOffset>11</bitOffset> 16900 <bitWidth>1</bitWidth> 16901 </field> 16902 <field> 16903 <name>CC3P</name> 16904 <description>Capture/Compare 3 output 16905 Polarity</description> 16906 <bitOffset>9</bitOffset> 16907 <bitWidth>1</bitWidth> 16908 </field> 16909 <field> 16910 <name>CC3E</name> 16911 <description>Capture/Compare 3 output 16912 enable</description> 16913 <bitOffset>8</bitOffset> 16914 <bitWidth>1</bitWidth> 16915 </field> 16916 <field> 16917 <name>CC2NP</name> 16918 <description>Capture/Compare 2 output 16919 Polarity</description> 16920 <bitOffset>7</bitOffset> 16921 <bitWidth>1</bitWidth> 16922 </field> 16923 <field> 16924 <name>CC2P</name> 16925 <description>Capture/Compare 2 output 16926 Polarity</description> 16927 <bitOffset>5</bitOffset> 16928 <bitWidth>1</bitWidth> 16929 </field> 16930 <field> 16931 <name>CC2E</name> 16932 <description>Capture/Compare 2 output 16933 enable</description> 16934 <bitOffset>4</bitOffset> 16935 <bitWidth>1</bitWidth> 16936 </field> 16937 <field> 16938 <name>CC1NP</name> 16939 <description>Capture/Compare 1 output 16940 Polarity</description> 16941 <bitOffset>3</bitOffset> 16942 <bitWidth>1</bitWidth> 16943 </field> 16944 <field> 16945 <name>CC1P</name> 16946 <description>Capture/Compare 1 output 16947 Polarity</description> 16948 <bitOffset>1</bitOffset> 16949 <bitWidth>1</bitWidth> 16950 </field> 16951 <field> 16952 <name>CC1E</name> 16953 <description>Capture/Compare 1 output 16954 enable</description> 16955 <bitOffset>0</bitOffset> 16956 <bitWidth>1</bitWidth> 16957 </field> 16958 </fields> 16959 </register> 16960 <register> 16961 <name>CNT</name> 16962 <displayName>CNT</displayName> 16963 <description>counter</description> 16964 <addressOffset>0x24</addressOffset> 16965 <size>0x20</size> 16966 <access>read-write</access> 16967 <resetValue>0x00000000</resetValue> 16968 <fields> 16969 <field><name>CNT</name><description>Counter value</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth><writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint> 16970 </field></fields> 16971 </register> 16972 <register> 16973 <name>PSC</name> 16974 <displayName>PSC</displayName> 16975 <description>prescaler</description> 16976 <addressOffset>0x28</addressOffset> 16977 <size>0x20</size> 16978 <access>read-write</access> 16979 <resetValue>0x0000</resetValue> 16980 <fields> 16981 <field> 16982 <name>PSC</name> 16983 <description>Prescaler value</description> 16984 <bitOffset>0</bitOffset> 16985 <bitWidth>16</bitWidth> 16986 <writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint> 16987 </field> 16988 </fields> 16989 </register> 16990 <register> 16991 <name>ARR</name> 16992 <displayName>ARR</displayName> 16993 <description>auto-reload register</description> 16994 <addressOffset>0x2C</addressOffset> 16995 <size>0x20</size> 16996 <access>read-write</access> 16997 <resetValue>0x00000000</resetValue> 16998 <fields> 16999 <field><name>ARR</name><description>Auto-reload value</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth><writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint> 17000 </field></fields> 17001 </register> 17002 <register> 17003 <dim>4</dim><dimIncrement>0x4</dimIncrement><dimIndex>1,2,3,4</dimIndex><name>CCR%s</name> 17004 <displayName>CCR1</displayName> 17005 <description>capture/compare register</description> 17006 <addressOffset>0x34</addressOffset> 17007 <size>0x20</size> 17008 <access>read-write</access> 17009 <resetValue>0x00000000</resetValue> 17010 <fields> 17011 <field><name>CCR</name><description>Capture/Compare value</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth><writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint> 17012 </field></fields> 17013 </register> 17014 <register> 17015 <name>DCR</name> 17016 <displayName>DCR</displayName> 17017 <description>DMA control register</description> 17018 <addressOffset>0x48</addressOffset> 17019 <size>0x20</size> 17020 <access>read-write</access> 17021 <resetValue>0x0000</resetValue> 17022 <fields> 17023 <field> 17024 <name>DBL</name> 17025 <description>DMA burst length</description> 17026 <bitOffset>8</bitOffset> 17027 <bitWidth>5</bitWidth> 17028 <writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint> 17029 </field> 17030 <field> 17031 <name>DBA</name> 17032 <description>DMA base address</description> 17033 <bitOffset>0</bitOffset> 17034 <bitWidth>5</bitWidth> 17035 <writeConstraint><range><minimum>0</minimum><maximum>31</maximum></range></writeConstraint> 17036 </field> 17037 </fields> 17038 </register> 17039 <register> 17040 <name>DMAR</name> 17041 <displayName>DMAR</displayName> 17042 <description>DMA address for full transfer</description> 17043 <addressOffset>0x4C</addressOffset> 17044 <size>0x20</size> 17045 <access>read-write</access> 17046 <resetValue>0x0000</resetValue> 17047 <fields> 17048 <field> 17049 <name>DMAB</name> 17050 <description>DMA register for burst 17051 accesses</description> 17052 <bitOffset>0</bitOffset> 17053 <bitWidth>16</bitWidth> 17054 </field> 17055 </fields> 17056 </register> 17057 <register> 17058 <name>OR</name> 17059 <displayName>OR</displayName> 17060 <description>TIM5 option register</description> 17061 <addressOffset>0x50</addressOffset> 17062 <size>0x20</size> 17063 <access>read-write</access> 17064 <resetValue>0x0000</resetValue> 17065 <fields> 17066 <field> 17067 <name>ITR1_RMP</name> 17068 <description>Timer Input 4 remap</description> 17069 <bitOffset>10</bitOffset> 17070 <bitWidth>2</bitWidth> 17071 </field> 17072 </fields> 17073 </register> 17074 </registers> 17075 </peripheral> 17076 <peripheral> 17077 <name>TIM3</name> 17078 <description>General purpose timers</description> 17079 <groupName>TIM</groupName> 17080 <baseAddress>0x40000400</baseAddress> 17081 <addressBlock> 17082 <offset>0x0</offset> 17083 <size>0x400</size> 17084 <usage>registers</usage> 17085 </addressBlock> 17086 <interrupt> 17087 <name>TIM3</name> 17088 <description>TIM3 global interrupt</description> 17089 <value>29</value> 17090 </interrupt> 17091 <registers> 17092 <register> 17093 <name>CR1</name> 17094 <displayName>CR1</displayName> 17095 <description>control register 1</description> 17096 <addressOffset>0x0</addressOffset> 17097 <size>0x20</size> 17098 <access>read-write</access> 17099 <resetValue>0x0000</resetValue> 17100 <fields> 17101 <field> 17102 <name>CKD</name> 17103 <description>Clock division</description> 17104 <bitOffset>8</bitOffset> 17105 <bitWidth>2</bitWidth> 17106 <enumeratedValues><name>CKD</name><usage>read-write</usage><enumeratedValue><name>Div1</name><description>t_DTS = t_CK_INT</description><value>0</value></enumeratedValue><enumeratedValue><name>Div2</name><description>t_DTS = 2 × t_CK_INT</description><value>1</value></enumeratedValue><enumeratedValue><name>Div4</name><description>t_DTS = 4 × t_CK_INT</description><value>2</value></enumeratedValue></enumeratedValues> 17107 </field> 17108 <field> 17109 <name>ARPE</name> 17110 <description>Auto-reload preload enable</description> 17111 <bitOffset>7</bitOffset> 17112 <bitWidth>1</bitWidth> 17113 <enumeratedValues><name>ARPE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>TIMx_APRR register is not buffered</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>TIMx_APRR register is buffered</description><value>1</value></enumeratedValue></enumeratedValues> 17114 </field> 17115 <field> 17116 <name>CMS</name> 17117 <description>Center-aligned mode 17118 selection</description> 17119 <bitOffset>5</bitOffset> 17120 <bitWidth>2</bitWidth> 17121 <enumeratedValues><name>CMS</name><usage>read-write</usage><enumeratedValue><name>EdgeAligned</name><description>The counter counts up or down depending on the direction bit</description><value>0</value></enumeratedValue><enumeratedValue><name>CenterAligned1</name><description>The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.</description><value>1</value></enumeratedValue><enumeratedValue><name>CenterAligned2</name><description>The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.</description><value>2</value></enumeratedValue><enumeratedValue><name>CenterAligned3</name><description>The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.</description><value>3</value></enumeratedValue></enumeratedValues> 17122 </field> 17123 <field> 17124 <name>DIR</name> 17125 <description>Direction</description> 17126 <bitOffset>4</bitOffset> 17127 <bitWidth>1</bitWidth> 17128 <enumeratedValues><name>DIR</name><usage>read-write</usage><enumeratedValue><name>Up</name><description>Counter used as upcounter</description><value>0</value></enumeratedValue><enumeratedValue><name>Down</name><description>Counter used as downcounter</description><value>1</value></enumeratedValue></enumeratedValues> 17129 </field> 17130 <field> 17131 <name>OPM</name> 17132 <description>One-pulse mode</description> 17133 <bitOffset>3</bitOffset> 17134 <bitWidth>1</bitWidth> 17135 <enumeratedValues><name>OPM</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Counter is not stopped at update event</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Counter stops counting at the next update event (clearing the CEN bit)</description><value>1</value></enumeratedValue></enumeratedValues> 17136 </field> 17137 <field> 17138 <name>URS</name> 17139 <description>Update request source</description> 17140 <bitOffset>2</bitOffset> 17141 <bitWidth>1</bitWidth> 17142 <enumeratedValues><name>URS</name><usage>read-write</usage><enumeratedValue><name>AnyEvent</name><description>Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request</description><value>0</value></enumeratedValue><enumeratedValue><name>CounterOnly</name><description>Only counter overflow/underflow generates an update interrupt or DMA request</description><value>1</value></enumeratedValue></enumeratedValues> 17143 </field> 17144 <field> 17145 <name>UDIS</name> 17146 <description>Update disable</description> 17147 <bitOffset>1</bitOffset> 17148 <bitWidth>1</bitWidth> 17149 <enumeratedValues><name>UDIS</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>Update event enabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>Update event disabled</description><value>1</value></enumeratedValue></enumeratedValues> 17150 </field> 17151 <field> 17152 <name>CEN</name> 17153 <description>Counter enable</description> 17154 <bitOffset>0</bitOffset> 17155 <bitWidth>1</bitWidth> 17156 <enumeratedValues><name>CEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Counter disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Counter enabled</description><value>1</value></enumeratedValue></enumeratedValues> 17157 </field> 17158 </fields> 17159 </register> 17160 <register> 17161 <name>CR2</name> 17162 <displayName>CR2</displayName> 17163 <description>control register 2</description> 17164 <addressOffset>0x4</addressOffset> 17165 <size>0x20</size> 17166 <access>read-write</access> 17167 <resetValue>0x0000</resetValue> 17168 <fields> 17169 <field> 17170 <name>TI1S</name> 17171 <description>TI1 selection</description> 17172 <bitOffset>7</bitOffset> 17173 <bitWidth>1</bitWidth> 17174 <enumeratedValues><name>TI1S</name><usage>read-write</usage><enumeratedValue><name>Normal</name><description>The TIMx_CH1 pin is connected to TI1 input</description><value>0</value></enumeratedValue><enumeratedValue><name>XOR</name><description>The TIMx_CH1, CH2, CH3 pins are connected to TI1 input</description><value>1</value></enumeratedValue></enumeratedValues> 17175 </field> 17176 <field> 17177 <name>MMS</name> 17178 <description>Master mode selection</description> 17179 <bitOffset>4</bitOffset> 17180 <bitWidth>3</bitWidth> 17181 <enumeratedValues><name>MMS</name><usage>read-write</usage><enumeratedValue><name>Reset</name><description>The UG bit from the TIMx_EGR register is used as trigger output</description><value>0</value></enumeratedValue><enumeratedValue><name>Enable</name><description>The counter enable signal, CNT_EN, is used as trigger output</description><value>1</value></enumeratedValue><enumeratedValue><name>Update</name><description>The update event is selected as trigger output</description><value>2</value></enumeratedValue><enumeratedValue><name>ComparePulse</name><description>The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred</description><value>3</value></enumeratedValue><enumeratedValue><name>CompareOC1</name><description>OC1REF signal is used as trigger output</description><value>4</value></enumeratedValue><enumeratedValue><name>CompareOC2</name><description>OC2REF signal is used as trigger output</description><value>5</value></enumeratedValue><enumeratedValue><name>CompareOC3</name><description>OC3REF signal is used as trigger output</description><value>6</value></enumeratedValue><enumeratedValue><name>CompareOC4</name><description>OC4REF signal is used as trigger output</description><value>7</value></enumeratedValue></enumeratedValues> 17182 </field> 17183 <field> 17184 <name>CCDS</name> 17185 <description>Capture/compare DMA 17186 selection</description> 17187 <bitOffset>3</bitOffset> 17188 <bitWidth>1</bitWidth> 17189 <enumeratedValues><name>CCDS</name><usage>read-write</usage><enumeratedValue><name>OnCompare</name><description>CCx DMA request sent when CCx event occurs</description><value>0</value></enumeratedValue><enumeratedValue><name>OnUpdate</name><description>CCx DMA request sent when update event occurs</description><value>1</value></enumeratedValue></enumeratedValues> 17190 </field> 17191 </fields> 17192 </register> 17193 <register> 17194 <name>SMCR</name> 17195 <displayName>SMCR</displayName> 17196 <description>slave mode control register</description> 17197 <addressOffset>0x8</addressOffset> 17198 <size>0x20</size> 17199 <access>read-write</access> 17200 <resetValue>0x0000</resetValue> 17201 <fields> 17202 <field> 17203 <name>ETP</name> 17204 <description>External trigger polarity</description> 17205 <bitOffset>15</bitOffset> 17206 <bitWidth>1</bitWidth> 17207 <enumeratedValues><name>ETP</name><usage>read-write</usage><enumeratedValue><name>NotInverted</name><description>ETR is noninverted, active at high level or rising edge</description><value>0</value></enumeratedValue><enumeratedValue><name>Inverted</name><description>ETR is inverted, active at low level or falling edge</description><value>1</value></enumeratedValue></enumeratedValues> 17208 </field> 17209 <field> 17210 <name>ECE</name> 17211 <description>External clock enable</description> 17212 <bitOffset>14</bitOffset> 17213 <bitWidth>1</bitWidth> 17214 <enumeratedValues><name>ECE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>External clock mode 2 disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.</description><value>1</value></enumeratedValue></enumeratedValues> 17215 </field> 17216 <field> 17217 <name>ETPS</name> 17218 <description>External trigger prescaler</description> 17219 <bitOffset>12</bitOffset> 17220 <bitWidth>2</bitWidth> 17221 <enumeratedValues><name>ETPS</name><usage>read-write</usage><enumeratedValue><name>Div1</name><description>Prescaler OFF</description><value>0</value></enumeratedValue><enumeratedValue><name>Div2</name><description>ETRP frequency divided by 2</description><value>1</value></enumeratedValue><enumeratedValue><name>Div4</name><description>ETRP frequency divided by 4</description><value>2</value></enumeratedValue><enumeratedValue><name>Div8</name><description>ETRP frequency divided by 8</description><value>3</value></enumeratedValue></enumeratedValues> 17222 </field> 17223 <field> 17224 <name>ETF</name> 17225 <description>External trigger filter</description> 17226 <bitOffset>8</bitOffset> 17227 <bitWidth>4</bitWidth> 17228 <enumeratedValues><name>ETF</name><usage>read-write</usage><enumeratedValue><name>NoFilter</name><description>No filter, sampling is done at fDTS</description><value>0</value></enumeratedValue><enumeratedValue><name>FCK_INT_N2</name><description>fSAMPLING=fCK_INT, N=2</description><value>1</value></enumeratedValue><enumeratedValue><name>FCK_INT_N4</name><description>fSAMPLING=fCK_INT, N=4</description><value>2</value></enumeratedValue><enumeratedValue><name>FCK_INT_N8</name><description>fSAMPLING=fCK_INT, N=8</description><value>3</value></enumeratedValue><enumeratedValue><name>FDTS_Div2_N6</name><description>fSAMPLING=fDTS/2, N=6</description><value>4</value></enumeratedValue><enumeratedValue><name>FDTS_Div2_N8</name><description>fSAMPLING=fDTS/2, N=8</description><value>5</value></enumeratedValue><enumeratedValue><name>FDTS_Div4_N6</name><description>fSAMPLING=fDTS/4, N=6</description><value>6</value></enumeratedValue><enumeratedValue><name>FDTS_Div4_N8</name><description>fSAMPLING=fDTS/4, N=8</description><value>7</value></enumeratedValue><enumeratedValue><name>FDTS_Div8_N6</name><description>fSAMPLING=fDTS/8, N=6</description><value>8</value></enumeratedValue><enumeratedValue><name>FDTS_Div8_N8</name><description>fSAMPLING=fDTS/8, N=8</description><value>9</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N5</name><description>fSAMPLING=fDTS/16, N=5</description><value>10</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N6</name><description>fSAMPLING=fDTS/16, N=6</description><value>11</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N8</name><description>fSAMPLING=fDTS/16, N=8</description><value>12</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N5</name><description>fSAMPLING=fDTS/32, N=5</description><value>13</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N6</name><description>fSAMPLING=fDTS/32, N=6</description><value>14</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N8</name><description>fSAMPLING=fDTS/32, N=8</description><value>15</value></enumeratedValue></enumeratedValues> 17229 </field> 17230 <field> 17231 <name>MSM</name> 17232 <description>Master/Slave mode</description> 17233 <bitOffset>7</bitOffset> 17234 <bitWidth>1</bitWidth> 17235 <enumeratedValues><name>MSM</name><usage>read-write</usage><enumeratedValue><name>NoSync</name><description>No action</description><value>0</value></enumeratedValue><enumeratedValue><name>Sync</name><description>The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.</description><value>1</value></enumeratedValue></enumeratedValues> 17236 </field> 17237 <field> 17238 <name>TS</name> 17239 <description>Trigger selection</description> 17240 <bitOffset>4</bitOffset> 17241 <bitWidth>3</bitWidth> 17242 <enumeratedValues><name>TS</name><usage>read-write</usage><enumeratedValue><name>ITR0</name><description>Internal Trigger 0 (ITR0)</description><value>0</value></enumeratedValue><enumeratedValue><name>ITR1</name><description>Internal Trigger 1 (ITR1)</description><value>1</value></enumeratedValue><enumeratedValue><name>ITR2</name><description>Internal Trigger 2 (ITR2)</description><value>2</value></enumeratedValue><enumeratedValue><name>TI1F_ED</name><description>TI1 Edge Detector (TI1F_ED)</description><value>4</value></enumeratedValue><enumeratedValue><name>TI1FP1</name><description>Filtered Timer Input 1 (TI1FP1)</description><value>5</value></enumeratedValue><enumeratedValue><name>TI2FP2</name><description>Filtered Timer Input 2 (TI2FP2)</description><value>6</value></enumeratedValue><enumeratedValue><name>ETRF</name><description>External Trigger input (ETRF)</description><value>7</value></enumeratedValue></enumeratedValues> 17243 </field> 17244 <field> 17245 <name>SMS</name> 17246 <description>Slave mode selection</description> 17247 <bitOffset>0</bitOffset> 17248 <bitWidth>3</bitWidth> 17249 <enumeratedValues><name>SMS</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.</description><value>0</value></enumeratedValue><enumeratedValue><name>Encoder_Mode_1</name><description>Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.</description><value>1</value></enumeratedValue><enumeratedValue><name>Encoder_Mode_2</name><description>Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.</description><value>2</value></enumeratedValue><enumeratedValue><name>Encoder_Mode_3</name><description>Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.</description><value>3</value></enumeratedValue><enumeratedValue><name>Reset_Mode</name><description>Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.</description><value>4</value></enumeratedValue><enumeratedValue><name>Gated_Mode</name><description>Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.</description><value>5</value></enumeratedValue><enumeratedValue><name>Trigger_Mode</name><description>Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.</description><value>6</value></enumeratedValue><enumeratedValue><name>Ext_Clock_Mode</name><description>External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.</description><value>7</value></enumeratedValue></enumeratedValues> 17250 </field> 17251 </fields> 17252 </register> 17253 <register> 17254 <name>DIER</name> 17255 <displayName>DIER</displayName> 17256 <description>DMA/Interrupt enable register</description> 17257 <addressOffset>0xC</addressOffset> 17258 <size>0x20</size> 17259 <access>read-write</access> 17260 <resetValue>0x0000</resetValue> 17261 <fields> 17262 <field> 17263 <name>TDE</name> 17264 <description>Trigger DMA request enable</description> 17265 <bitOffset>14</bitOffset> 17266 <bitWidth>1</bitWidth> 17267 <enumeratedValues><name>TDE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Trigger DMA request disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Trigger DMA request enabled</description><value>1</value></enumeratedValue></enumeratedValues> 17268 </field> 17269 <field> 17270 <name>CC4DE</name> 17271 <description>Capture/Compare 4 DMA request 17272 enable</description> 17273 <bitOffset>12</bitOffset> 17274 <bitWidth>1</bitWidth> 17275 <enumeratedValues derivedFrom="CC1DE"/> 17276 </field> 17277 <field> 17278 <name>CC3DE</name> 17279 <description>Capture/Compare 3 DMA request 17280 enable</description> 17281 <bitOffset>11</bitOffset> 17282 <bitWidth>1</bitWidth> 17283 <enumeratedValues derivedFrom="CC1DE"/> 17284 </field> 17285 <field> 17286 <name>CC2DE</name> 17287 <description>Capture/Compare 2 DMA request 17288 enable</description> 17289 <bitOffset>10</bitOffset> 17290 <bitWidth>1</bitWidth> 17291 <enumeratedValues derivedFrom="CC1DE"/> 17292 </field> 17293 <field> 17294 <name>CC1DE</name> 17295 <description>Capture/Compare 1 DMA request 17296 enable</description> 17297 <bitOffset>9</bitOffset> 17298 <bitWidth>1</bitWidth> 17299 <enumeratedValues><name>CC1DE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>CCx DMA request disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>CCx DMA request enabled</description><value>1</value></enumeratedValue></enumeratedValues> 17300 </field> 17301 <field> 17302 <name>UDE</name> 17303 <description>Update DMA request enable</description> 17304 <bitOffset>8</bitOffset> 17305 <bitWidth>1</bitWidth> 17306 <enumeratedValues><name>UDE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Update DMA request disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Update DMA request enabled</description><value>1</value></enumeratedValue></enumeratedValues> 17307 </field> 17308 <field> 17309 <name>TIE</name> 17310 <description>Trigger interrupt enable</description> 17311 <bitOffset>6</bitOffset> 17312 <bitWidth>1</bitWidth> 17313 <enumeratedValues><name>TIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Trigger interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Trigger interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 17314 </field> 17315 <field> 17316 <name>CC4IE</name> 17317 <description>Capture/Compare 4 interrupt 17318 enable</description> 17319 <bitOffset>4</bitOffset> 17320 <bitWidth>1</bitWidth> 17321 <enumeratedValues derivedFrom="CC1IE"/> 17322 </field> 17323 <field> 17324 <name>CC3IE</name> 17325 <description>Capture/Compare 3 interrupt 17326 enable</description> 17327 <bitOffset>3</bitOffset> 17328 <bitWidth>1</bitWidth> 17329 <enumeratedValues derivedFrom="CC1IE"/> 17330 </field> 17331 <field> 17332 <name>CC2IE</name> 17333 <description>Capture/Compare 2 interrupt 17334 enable</description> 17335 <bitOffset>2</bitOffset> 17336 <bitWidth>1</bitWidth> 17337 <enumeratedValues derivedFrom="CC1IE"/> 17338 </field> 17339 <field> 17340 <name>CC1IE</name> 17341 <description>Capture/Compare 1 interrupt 17342 enable</description> 17343 <bitOffset>1</bitOffset> 17344 <bitWidth>1</bitWidth> 17345 <enumeratedValues><name>CC1IE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>CCx interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>CCx interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 17346 </field> 17347 <field> 17348 <name>UIE</name> 17349 <description>Update interrupt enable</description> 17350 <bitOffset>0</bitOffset> 17351 <bitWidth>1</bitWidth> 17352 <enumeratedValues><name>UIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Update interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Update interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 17353 </field> 17354 </fields> 17355 </register> 17356 <register> 17357 <name>SR</name> 17358 <displayName>SR</displayName> 17359 <description>status register</description> 17360 <addressOffset>0x10</addressOffset> 17361 <size>0x20</size> 17362 <access>read-write</access> 17363 <resetValue>0x0000</resetValue> 17364 <fields> 17365 <field> 17366 <name>CC4OF</name> 17367 <description>Capture/Compare 4 overcapture 17368 flag</description> 17369 <bitOffset>12</bitOffset> 17370 <bitWidth>1</bitWidth> 17371 <enumeratedValues derivedFrom="CC1OFR"/> 17372 <enumeratedValues derivedFrom="CC1OFW"/> 17373 </field> 17374 <field> 17375 <name>CC3OF</name> 17376 <description>Capture/Compare 3 overcapture 17377 flag</description> 17378 <bitOffset>11</bitOffset> 17379 <bitWidth>1</bitWidth> 17380 <enumeratedValues derivedFrom="CC1OFR"/> 17381 <enumeratedValues derivedFrom="CC1OFW"/> 17382 </field> 17383 <field> 17384 <name>CC2OF</name> 17385 <description>Capture/compare 2 overcapture 17386 flag</description> 17387 <bitOffset>10</bitOffset> 17388 <bitWidth>1</bitWidth> 17389 <enumeratedValues derivedFrom="CC1OFR"/> 17390 <enumeratedValues derivedFrom="CC1OFW"/> 17391 </field> 17392 <field> 17393 <name>CC1OF</name> 17394 <description>Capture/Compare 1 overcapture 17395 flag</description> 17396 <bitOffset>9</bitOffset> 17397 <bitWidth>1</bitWidth> 17398 <enumeratedValues><name>CC1OFR</name><usage>read</usage><enumeratedValue><name>Overcapture</name><description>The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set</description><value>1</value></enumeratedValue></enumeratedValues> 17399 <enumeratedValues><name>CC1OFW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clear flag</description><value>0</value></enumeratedValue></enumeratedValues> 17400 </field> 17401 <field> 17402 <name>TIF</name> 17403 <description>Trigger interrupt flag</description> 17404 <bitOffset>6</bitOffset> 17405 <bitWidth>1</bitWidth> 17406 <enumeratedValues><name>TIFR</name><usage>read</usage><enumeratedValue><name>NoTrigger</name><description>No trigger event occurred</description><value>0</value></enumeratedValue><enumeratedValue><name>Trigger</name><description>Trigger interrupt pending</description><value>1</value></enumeratedValue></enumeratedValues> 17407 <enumeratedValues><name>TIFW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clear flag</description><value>0</value></enumeratedValue></enumeratedValues> 17408 </field> 17409 <field> 17410 <name>CC4IF</name> 17411 <description>Capture/Compare 4 interrupt 17412 flag</description> 17413 <bitOffset>4</bitOffset> 17414 <bitWidth>1</bitWidth> 17415 <enumeratedValues derivedFrom="CC1IFR"/> 17416 <enumeratedValues derivedFrom="CC1IFW"/> 17417 </field> 17418 <field> 17419 <name>CC3IF</name> 17420 <description>Capture/Compare 3 interrupt 17421 flag</description> 17422 <bitOffset>3</bitOffset> 17423 <bitWidth>1</bitWidth> 17424 <enumeratedValues derivedFrom="CC1IFR"/> 17425 <enumeratedValues derivedFrom="CC1IFW"/> 17426 </field> 17427 <field> 17428 <name>CC2IF</name> 17429 <description>Capture/Compare 2 interrupt 17430 flag</description> 17431 <bitOffset>2</bitOffset> 17432 <bitWidth>1</bitWidth> 17433 <enumeratedValues derivedFrom="CC1IFR"/> 17434 <enumeratedValues derivedFrom="CC1IFW"/> 17435 </field> 17436 <field> 17437 <name>CC1IF</name> 17438 <description>Capture/compare 1 interrupt 17439 flag</description> 17440 <bitOffset>1</bitOffset> 17441 <bitWidth>1</bitWidth> 17442 <enumeratedValues><name>CC1IFR</name><usage>read</usage><enumeratedValue><name>Match</name><description>If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.</description><value>1</value></enumeratedValue></enumeratedValues> 17443 <enumeratedValues><name>CC1IFW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clear flag</description><value>0</value></enumeratedValue></enumeratedValues> 17444 </field> 17445 <field> 17446 <name>UIF</name> 17447 <description>Update interrupt flag</description> 17448 <bitOffset>0</bitOffset> 17449 <bitWidth>1</bitWidth> 17450 <enumeratedValues><name>UIF</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>No update occurred</description><value>0</value></enumeratedValue><enumeratedValue><name>UpdatePending</name><description>Update interrupt pending.</description><value>1</value></enumeratedValue></enumeratedValues> 17451 </field> 17452 </fields> 17453 </register> 17454 <register> 17455 <name>EGR</name> 17456 <displayName>EGR</displayName> 17457 <description>event generation register</description> 17458 <addressOffset>0x14</addressOffset> 17459 <size>0x20</size> 17460 <access>write-only</access> 17461 <resetValue>0x0000</resetValue> 17462 <fields> 17463 <field> 17464 <name>TG</name> 17465 <description>Trigger generation</description> 17466 <bitOffset>6</bitOffset> 17467 <bitWidth>1</bitWidth> 17468 <enumeratedValues><name>TGW</name><usage>write</usage><enumeratedValue><name>Trigger</name><description>The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.</description><value>1</value></enumeratedValue></enumeratedValues> 17469 </field> 17470 <field> 17471 <name>CC4G</name> 17472 <description>Capture/compare 4 17473 generation</description> 17474 <bitOffset>4</bitOffset> 17475 <bitWidth>1</bitWidth> 17476 <enumeratedValues derivedFrom="CC1GW"/> 17477 </field> 17478 <field> 17479 <name>CC3G</name> 17480 <description>Capture/compare 3 17481 generation</description> 17482 <bitOffset>3</bitOffset> 17483 <bitWidth>1</bitWidth> 17484 <enumeratedValues derivedFrom="CC1GW"/> 17485 </field> 17486 <field> 17487 <name>CC2G</name> 17488 <description>Capture/compare 2 17489 generation</description> 17490 <bitOffset>2</bitOffset> 17491 <bitWidth>1</bitWidth> 17492 <enumeratedValues derivedFrom="CC1GW"/> 17493 </field> 17494 <field> 17495 <name>CC1G</name> 17496 <description>Capture/compare 1 17497 generation</description> 17498 <bitOffset>1</bitOffset> 17499 <bitWidth>1</bitWidth> 17500 <enumeratedValues><name>CC1GW</name><usage>write</usage><enumeratedValue><name>Trigger</name><description>If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.</description><value>1</value></enumeratedValue></enumeratedValues> 17501 </field> 17502 <field> 17503 <name>UG</name> 17504 <description>Update generation</description> 17505 <bitOffset>0</bitOffset> 17506 <bitWidth>1</bitWidth> 17507 <enumeratedValues><name>UG</name><usage>read-write</usage><enumeratedValue><name>Update</name><description>Re-initializes the timer counter and generates an update of the registers.</description><value>1</value></enumeratedValue></enumeratedValues> 17508 </field> 17509 </fields> 17510 </register> 17511 <register> 17512 <name>CCMR1_Output</name> 17513 <displayName>CCMR1_Output</displayName> 17514 <description>capture/compare mode register 1 (output 17515 mode)</description> 17516 <addressOffset>0x18</addressOffset> 17517 <size>0x20</size> 17518 <access>read-write</access> 17519 <resetValue>0x00000000</resetValue> 17520 <fields> 17521 <field> 17522 <name>OC2CE</name> 17523 <description>OC2CE</description> 17524 <bitOffset>15</bitOffset> 17525 <bitWidth>1</bitWidth> 17526 </field> 17527 <field> 17528 <name>OC2M</name> 17529 <description>OC2M</description> 17530 <bitOffset>12</bitOffset> 17531 <bitWidth>3</bitWidth> 17532 <enumeratedValues derivedFrom="OC1M"/> 17533 </field> 17534 <field> 17535 <name>OC2PE</name> 17536 <description>OC2PE</description> 17537 <bitOffset>11</bitOffset> 17538 <bitWidth>1</bitWidth> 17539 <enumeratedValues><name>OC2PE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Preload register on CCR2 enabled. Preload value is loaded into active register on each update event</description><value>1</value></enumeratedValue></enumeratedValues> 17540 </field> 17541 <field> 17542 <name>OC2FE</name> 17543 <description>OC2FE</description> 17544 <bitOffset>10</bitOffset> 17545 <bitWidth>1</bitWidth> 17546 </field> 17547 <field> 17548 <name>CC2S</name> 17549 <description>CC2S</description> 17550 <bitOffset>8</bitOffset> 17551 <bitWidth>2</bitWidth> 17552 <enumeratedValues><name>CC2S</name><usage>read-write</usage><enumeratedValue><name>Output</name><description>CC2 channel is configured as output</description><value>0</value></enumeratedValue></enumeratedValues> 17553 </field> 17554 <field> 17555 <name>OC1CE</name> 17556 <description>OC1CE</description> 17557 <bitOffset>7</bitOffset> 17558 <bitWidth>1</bitWidth> 17559 </field> 17560 <field> 17561 <name>OC1M</name> 17562 <description>OC1M</description> 17563 <bitOffset>4</bitOffset> 17564 <bitWidth>3</bitWidth> 17565 <enumeratedValues><name>OC1M</name><usage>read-write</usage><enumeratedValue><name>Frozen</name><description>The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs</description><value>0</value></enumeratedValue><enumeratedValue><name>ActiveOnMatch</name><description>Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register</description><value>1</value></enumeratedValue><enumeratedValue><name>InactiveOnMatch</name><description>Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register</description><value>2</value></enumeratedValue><enumeratedValue><name>Toggle</name><description>OCyREF toggles when TIMx_CNT=TIMx_CCRy</description><value>3</value></enumeratedValue><enumeratedValue><name>ForceInactive</name><description>OCyREF is forced low</description><value>4</value></enumeratedValue><enumeratedValue><name>ForceActive</name><description>OCyREF is forced high</description><value>5</value></enumeratedValue><enumeratedValue><name>PwmMode1</name><description>In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active</description><value>6</value></enumeratedValue><enumeratedValue><name>PwmMode2</name><description>Inversely to PwmMode1</description><value>7</value></enumeratedValue></enumeratedValues> 17566 </field> 17567 <field> 17568 <name>OC1PE</name> 17569 <description>OC1PE</description> 17570 <bitOffset>3</bitOffset> 17571 <bitWidth>1</bitWidth> 17572 <enumeratedValues><name>OC1PE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Preload register on CCR1 enabled. Preload value is loaded into active register on each update event</description><value>1</value></enumeratedValue></enumeratedValues> 17573 </field> 17574 <field> 17575 <name>OC1FE</name> 17576 <description>OC1FE</description> 17577 <bitOffset>2</bitOffset> 17578 <bitWidth>1</bitWidth> 17579 </field> 17580 <field> 17581 <name>CC1S</name> 17582 <description>CC1S</description> 17583 <bitOffset>0</bitOffset> 17584 <bitWidth>2</bitWidth> 17585 <enumeratedValues><name>CC1S</name><usage>read-write</usage><enumeratedValue><name>Output</name><description>CC1 channel is configured as output</description><value>0</value></enumeratedValue></enumeratedValues> 17586 </field> 17587 </fields> 17588 </register> 17589 <register> 17590 <name>CCMR1_Input</name> 17591 <displayName>CCMR1_Input</displayName> 17592 <description>capture/compare mode register 1 (input 17593 mode)</description> 17594 <alternateRegister>CCMR1_Output</alternateRegister> 17595 <addressOffset>0x18</addressOffset> 17596 <size>0x20</size> 17597 <access>read-write</access> 17598 <resetValue>0x00000000</resetValue> 17599 <fields> 17600 <field> 17601 <name>IC2F</name> 17602 <description>Input capture 2 filter</description> 17603 <bitOffset>12</bitOffset> 17604 <bitWidth>4</bitWidth> 17605 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 17606 </field> 17607 <field> 17608 <name>IC2PSC</name> 17609 <description>Input capture 2 prescaler</description> 17610 <bitOffset>10</bitOffset> 17611 <bitWidth>2</bitWidth> 17612 </field> 17613 <field> 17614 <name>CC2S</name> 17615 <description>Capture/Compare 2 17616 selection</description> 17617 <bitOffset>8</bitOffset> 17618 <bitWidth>2</bitWidth> 17619 <enumeratedValues><name>CC2S</name><usage>read-write</usage><enumeratedValue><name>TI2</name><description>CC2 channel is configured as input, IC2 is mapped on TI2</description><value>1</value></enumeratedValue><enumeratedValue><name>TI1</name><description>CC2 channel is configured as input, IC2 is mapped on TI1</description><value>2</value></enumeratedValue><enumeratedValue><name>TRC</name><description>CC2 channel is configured as input, IC2 is mapped on TRC</description><value>3</value></enumeratedValue></enumeratedValues> 17620 </field> 17621 <field> 17622 <name>IC1F</name> 17623 <description>Input capture 1 filter</description> 17624 <bitOffset>4</bitOffset> 17625 <bitWidth>4</bitWidth> 17626 <enumeratedValues><name>IC1F</name><usage>read-write</usage><enumeratedValue><name>NoFilter</name><description>No filter, sampling is done at fDTS</description><value>0</value></enumeratedValue><enumeratedValue><name>FCK_INT_N2</name><description>fSAMPLING=fCK_INT, N=2</description><value>1</value></enumeratedValue><enumeratedValue><name>FCK_INT_N4</name><description>fSAMPLING=fCK_INT, N=4</description><value>2</value></enumeratedValue><enumeratedValue><name>FCK_INT_N8</name><description>fSAMPLING=fCK_INT, N=8</description><value>3</value></enumeratedValue><enumeratedValue><name>FDTS_Div2_N6</name><description>fSAMPLING=fDTS/2, N=6</description><value>4</value></enumeratedValue><enumeratedValue><name>FDTS_Div2_N8</name><description>fSAMPLING=fDTS/2, N=8</description><value>5</value></enumeratedValue><enumeratedValue><name>FDTS_Div4_N6</name><description>fSAMPLING=fDTS/4, N=6</description><value>6</value></enumeratedValue><enumeratedValue><name>FDTS_Div4_N8</name><description>fSAMPLING=fDTS/4, N=8</description><value>7</value></enumeratedValue><enumeratedValue><name>FDTS_Div8_N6</name><description>fSAMPLING=fDTS/8, N=6</description><value>8</value></enumeratedValue><enumeratedValue><name>FDTS_Div8_N8</name><description>fSAMPLING=fDTS/8, N=8</description><value>9</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N5</name><description>fSAMPLING=fDTS/16, N=5</description><value>10</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N6</name><description>fSAMPLING=fDTS/16, N=6</description><value>11</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N8</name><description>fSAMPLING=fDTS/16, N=8</description><value>12</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N5</name><description>fSAMPLING=fDTS/32, N=5</description><value>13</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N6</name><description>fSAMPLING=fDTS/32, N=6</description><value>14</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N8</name><description>fSAMPLING=fDTS/32, N=8</description><value>15</value></enumeratedValue></enumeratedValues> 17627 </field> 17628 <field> 17629 <name>IC1PSC</name> 17630 <description>Input capture 1 prescaler</description> 17631 <bitOffset>2</bitOffset> 17632 <bitWidth>2</bitWidth> 17633 </field> 17634 <field> 17635 <name>CC1S</name> 17636 <description>Capture/Compare 1 17637 selection</description> 17638 <bitOffset>0</bitOffset> 17639 <bitWidth>2</bitWidth> 17640 <enumeratedValues><name>CC1S</name><usage>read-write</usage><enumeratedValue><name>TI1</name><description>CC1 channel is configured as input, IC1 is mapped on TI1</description><value>1</value></enumeratedValue><enumeratedValue><name>TI2</name><description>CC1 channel is configured as input, IC1 is mapped on TI2</description><value>2</value></enumeratedValue><enumeratedValue><name>TRC</name><description>CC1 channel is configured as input, IC1 is mapped on TRC</description><value>3</value></enumeratedValue></enumeratedValues> 17641 </field> 17642 </fields> 17643 </register> 17644 <register> 17645 <name>CCMR2_Output</name> 17646 <displayName>CCMR2_Output</displayName> 17647 <description>capture/compare mode register 2 (output 17648 mode)</description> 17649 <addressOffset>0x1C</addressOffset> 17650 <size>0x20</size> 17651 <access>read-write</access> 17652 <resetValue>0x00000000</resetValue> 17653 <fields> 17654 <field> 17655 <name>OC4CE</name> 17656 <description>O24CE</description> 17657 <bitOffset>15</bitOffset> 17658 <bitWidth>1</bitWidth> 17659 </field> 17660 <field> 17661 <name>OC4M</name> 17662 <description>OC4M</description> 17663 <bitOffset>12</bitOffset> 17664 <bitWidth>3</bitWidth> 17665 <enumeratedValues derivedFrom="OC3M"/> 17666 </field> 17667 <field> 17668 <name>OC4PE</name> 17669 <description>OC4PE</description> 17670 <bitOffset>11</bitOffset> 17671 <bitWidth>1</bitWidth> 17672 <enumeratedValues><name>OC4PE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Preload register on CCR4 disabled. New values written to CCR4 are taken into account immediately</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Preload register on CCR4 enabled. Preload value is loaded into active register on each update event</description><value>1</value></enumeratedValue></enumeratedValues> 17673 </field> 17674 <field> 17675 <name>OC4FE</name> 17676 <description>OC4FE</description> 17677 <bitOffset>10</bitOffset> 17678 <bitWidth>1</bitWidth> 17679 </field> 17680 <field> 17681 <name>CC4S</name> 17682 <description>CC4S</description> 17683 <bitOffset>8</bitOffset> 17684 <bitWidth>2</bitWidth> 17685 <enumeratedValues><name>CC4S</name><usage>read-write</usage><enumeratedValue><name>Output</name><description>CC4 channel is configured as output</description><value>0</value></enumeratedValue></enumeratedValues> 17686 </field> 17687 <field> 17688 <name>OC3CE</name> 17689 <description>OC3CE</description> 17690 <bitOffset>7</bitOffset> 17691 <bitWidth>1</bitWidth> 17692 </field> 17693 <field> 17694 <name>OC3M</name> 17695 <description>OC3M</description> 17696 <bitOffset>4</bitOffset> 17697 <bitWidth>3</bitWidth> 17698 <enumeratedValues><name>OC3M</name><usage>read-write</usage><enumeratedValue><name>Frozen</name><description>The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs</description><value>0</value></enumeratedValue><enumeratedValue><name>ActiveOnMatch</name><description>Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register</description><value>1</value></enumeratedValue><enumeratedValue><name>InactiveOnMatch</name><description>Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register</description><value>2</value></enumeratedValue><enumeratedValue><name>Toggle</name><description>OCyREF toggles when TIMx_CNT=TIMx_CCRy</description><value>3</value></enumeratedValue><enumeratedValue><name>ForceInactive</name><description>OCyREF is forced low</description><value>4</value></enumeratedValue><enumeratedValue><name>ForceActive</name><description>OCyREF is forced high</description><value>5</value></enumeratedValue><enumeratedValue><name>PwmMode1</name><description>In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active</description><value>6</value></enumeratedValue><enumeratedValue><name>PwmMode2</name><description>Inversely to PwmMode1</description><value>7</value></enumeratedValue></enumeratedValues> 17699 </field> 17700 <field> 17701 <name>OC3PE</name> 17702 <description>OC3PE</description> 17703 <bitOffset>3</bitOffset> 17704 <bitWidth>1</bitWidth> 17705 <enumeratedValues><name>OC3PE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Preload register on CCR3 enabled. Preload value is loaded into active register on each update event</description><value>1</value></enumeratedValue></enumeratedValues> 17706 </field> 17707 <field> 17708 <name>OC3FE</name> 17709 <description>OC3FE</description> 17710 <bitOffset>2</bitOffset> 17711 <bitWidth>1</bitWidth> 17712 </field> 17713 <field> 17714 <name>CC3S</name> 17715 <description>CC3S</description> 17716 <bitOffset>0</bitOffset> 17717 <bitWidth>2</bitWidth> 17718 <enumeratedValues><name>CC3S</name><usage>read-write</usage><enumeratedValue><name>Output</name><description>CC3 channel is configured as output</description><value>0</value></enumeratedValue></enumeratedValues> 17719 </field> 17720 </fields> 17721 </register> 17722 <register> 17723 <name>CCMR2_Input</name> 17724 <displayName>CCMR2_Input</displayName> 17725 <description>capture/compare mode register 2 (input 17726 mode)</description> 17727 <alternateRegister>CCMR2_Output</alternateRegister> 17728 <addressOffset>0x1C</addressOffset> 17729 <size>0x20</size> 17730 <access>read-write</access> 17731 <resetValue>0x00000000</resetValue> 17732 <fields> 17733 <field> 17734 <name>IC4F</name> 17735 <description>Input capture 4 filter</description> 17736 <bitOffset>12</bitOffset> 17737 <bitWidth>4</bitWidth> 17738 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 17739 </field> 17740 <field> 17741 <name>IC4PSC</name> 17742 <description>Input capture 4 prescaler</description> 17743 <bitOffset>10</bitOffset> 17744 <bitWidth>2</bitWidth> 17745 <writeConstraint><range><minimum>0</minimum><maximum>3</maximum></range></writeConstraint> 17746 </field> 17747 <field> 17748 <name>CC4S</name> 17749 <description>Capture/Compare 4 17750 selection</description> 17751 <bitOffset>8</bitOffset> 17752 <bitWidth>2</bitWidth> 17753 <enumeratedValues><name>CC4S</name><usage>read-write</usage><enumeratedValue><name>TI4</name><description>CC4 channel is configured as input, IC4 is mapped on TI4</description><value>1</value></enumeratedValue><enumeratedValue><name>TI3</name><description>CC4 channel is configured as input, IC4 is mapped on TI3</description><value>2</value></enumeratedValue><enumeratedValue><name>TRC</name><description>CC4 channel is configured as input, IC4 is mapped on TRC</description><value>3</value></enumeratedValue></enumeratedValues> 17754 </field> 17755 <field> 17756 <name>IC3F</name> 17757 <description>Input capture 3 filter</description> 17758 <bitOffset>4</bitOffset> 17759 <bitWidth>4</bitWidth> 17760 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 17761 </field> 17762 <field> 17763 <name>IC3PSC</name> 17764 <description>Input capture 3 prescaler</description> 17765 <bitOffset>2</bitOffset> 17766 <bitWidth>2</bitWidth> 17767 <writeConstraint><range><minimum>0</minimum><maximum>3</maximum></range></writeConstraint> 17768 </field> 17769 <field> 17770 <name>CC3S</name> 17771 <description>Capture/compare 3 17772 selection</description> 17773 <bitOffset>0</bitOffset> 17774 <bitWidth>2</bitWidth> 17775 <enumeratedValues><name>CC3S</name><usage>read-write</usage><enumeratedValue><name>TI3</name><description>CC3 channel is configured as input, IC3 is mapped on TI3</description><value>1</value></enumeratedValue><enumeratedValue><name>TI4</name><description>CC3 channel is configured as input, IC3 is mapped on TI4</description><value>2</value></enumeratedValue><enumeratedValue><name>TRC</name><description>CC3 channel is configured as input, IC3 is mapped on TRC</description><value>3</value></enumeratedValue></enumeratedValues> 17776 </field> 17777 </fields> 17778 </register> 17779 <register> 17780 <name>CCER</name> 17781 <displayName>CCER</displayName> 17782 <description>capture/compare enable 17783 register</description> 17784 <addressOffset>0x20</addressOffset> 17785 <size>0x20</size> 17786 <access>read-write</access> 17787 <resetValue>0x0000</resetValue> 17788 <fields> 17789 <field> 17790 <name>CC4NP</name> 17791 <description>Capture/Compare 4 output 17792 Polarity</description> 17793 <bitOffset>15</bitOffset> 17794 <bitWidth>1</bitWidth> 17795 </field> 17796 <field> 17797 <name>CC4P</name> 17798 <description>Capture/Compare 3 output 17799 Polarity</description> 17800 <bitOffset>13</bitOffset> 17801 <bitWidth>1</bitWidth> 17802 </field> 17803 <field> 17804 <name>CC4E</name> 17805 <description>Capture/Compare 4 output 17806 enable</description> 17807 <bitOffset>12</bitOffset> 17808 <bitWidth>1</bitWidth> 17809 </field> 17810 <field> 17811 <name>CC3NP</name> 17812 <description>Capture/Compare 3 output 17813 Polarity</description> 17814 <bitOffset>11</bitOffset> 17815 <bitWidth>1</bitWidth> 17816 </field> 17817 <field> 17818 <name>CC3P</name> 17819 <description>Capture/Compare 3 output 17820 Polarity</description> 17821 <bitOffset>9</bitOffset> 17822 <bitWidth>1</bitWidth> 17823 </field> 17824 <field> 17825 <name>CC3E</name> 17826 <description>Capture/Compare 3 output 17827 enable</description> 17828 <bitOffset>8</bitOffset> 17829 <bitWidth>1</bitWidth> 17830 </field> 17831 <field> 17832 <name>CC2NP</name> 17833 <description>Capture/Compare 2 output 17834 Polarity</description> 17835 <bitOffset>7</bitOffset> 17836 <bitWidth>1</bitWidth> 17837 </field> 17838 <field> 17839 <name>CC2P</name> 17840 <description>Capture/Compare 2 output 17841 Polarity</description> 17842 <bitOffset>5</bitOffset> 17843 <bitWidth>1</bitWidth> 17844 </field> 17845 <field> 17846 <name>CC2E</name> 17847 <description>Capture/Compare 2 output 17848 enable</description> 17849 <bitOffset>4</bitOffset> 17850 <bitWidth>1</bitWidth> 17851 </field> 17852 <field> 17853 <name>CC1NP</name> 17854 <description>Capture/Compare 1 output 17855 Polarity</description> 17856 <bitOffset>3</bitOffset> 17857 <bitWidth>1</bitWidth> 17858 </field> 17859 <field> 17860 <name>CC1P</name> 17861 <description>Capture/Compare 1 output 17862 Polarity</description> 17863 <bitOffset>1</bitOffset> 17864 <bitWidth>1</bitWidth> 17865 </field> 17866 <field> 17867 <name>CC1E</name> 17868 <description>Capture/Compare 1 output 17869 enable</description> 17870 <bitOffset>0</bitOffset> 17871 <bitWidth>1</bitWidth> 17872 </field> 17873 </fields> 17874 </register> 17875 <register> 17876 <name>CNT</name> 17877 <displayName>CNT</displayName> 17878 <description>counter</description> 17879 <addressOffset>0x24</addressOffset> 17880 <size>0x20</size> 17881 <access>read-write</access> 17882 <resetValue>0x00000000</resetValue> 17883 <fields> 17884 <field> 17885 <name>CNT_H</name> 17886 <description>High counter value</description> 17887 <bitOffset>16</bitOffset> 17888 <bitWidth>16</bitWidth> 17889 </field> 17890 <field> 17891 <name>CNT</name> 17892 <description>Counter value</description> 17893 <bitOffset>0</bitOffset> 17894 <bitWidth>16</bitWidth> 17895 <writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint> 17896 </field> 17897 </fields> 17898 </register> 17899 <register> 17900 <name>PSC</name> 17901 <displayName>PSC</displayName> 17902 <description>prescaler</description> 17903 <addressOffset>0x28</addressOffset> 17904 <size>0x20</size> 17905 <access>read-write</access> 17906 <resetValue>0x0000</resetValue> 17907 <fields> 17908 <field> 17909 <name>PSC</name> 17910 <description>Prescaler value</description> 17911 <bitOffset>0</bitOffset> 17912 <bitWidth>16</bitWidth> 17913 <writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint> 17914 </field> 17915 </fields> 17916 </register> 17917 <register> 17918 <name>ARR</name> 17919 <displayName>ARR</displayName> 17920 <description>auto-reload register</description> 17921 <addressOffset>0x2C</addressOffset> 17922 <size>0x20</size> 17923 <access>read-write</access> 17924 <resetValue>0x00000000</resetValue> 17925 <fields> 17926 <field> 17927 <name>ARR_H</name> 17928 <description>High Auto-reload value</description> 17929 <bitOffset>16</bitOffset> 17930 <bitWidth>16</bitWidth> 17931 </field> 17932 <field> 17933 <name>ARR</name> 17934 <description>Auto-reload value</description> 17935 <bitOffset>0</bitOffset> 17936 <bitWidth>16</bitWidth> 17937 <writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint> 17938 </field> 17939 </fields> 17940 </register> 17941 <register> 17942 <dim>4</dim><dimIncrement>0x4</dimIncrement><dimIndex>1,2,3,4</dimIndex><name>CCR%s</name> 17943 <displayName>CCR1</displayName> 17944 <description>capture/compare register</description> 17945 <addressOffset>0x34</addressOffset> 17946 <size>0x20</size> 17947 <access>read-write</access> 17948 <resetValue>0x00000000</resetValue> 17949 <fields> 17950 <field> 17951 <name>CCR1_H</name> 17952 <description>High Capture/Compare 1 17953 value</description> 17954 <bitOffset>16</bitOffset> 17955 <bitWidth>16</bitWidth> 17956 </field> 17957 <field> 17958 <name>CCR</name> 17959 <description>Capture/Compare value</description> 17960 <bitOffset>0</bitOffset> 17961 <bitWidth>16</bitWidth> 17962 <writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint> 17963 </field> 17964 </fields> 17965 </register> 17966 <register> 17967 <name>DCR</name> 17968 <displayName>DCR</displayName> 17969 <description>DMA control register</description> 17970 <addressOffset>0x48</addressOffset> 17971 <size>0x20</size> 17972 <access>read-write</access> 17973 <resetValue>0x0000</resetValue> 17974 <fields> 17975 <field> 17976 <name>DBL</name> 17977 <description>DMA burst length</description> 17978 <bitOffset>8</bitOffset> 17979 <bitWidth>5</bitWidth> 17980 <writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint> 17981 </field> 17982 <field> 17983 <name>DBA</name> 17984 <description>DMA base address</description> 17985 <bitOffset>0</bitOffset> 17986 <bitWidth>5</bitWidth> 17987 <writeConstraint><range><minimum>0</minimum><maximum>31</maximum></range></writeConstraint> 17988 </field> 17989 </fields> 17990 </register> 17991 <register> 17992 <name>DMAR</name> 17993 <displayName>DMAR</displayName> 17994 <description>DMA address for full transfer</description> 17995 <addressOffset>0x4C</addressOffset> 17996 <size>0x20</size> 17997 <access>read-write</access> 17998 <resetValue>0x0000</resetValue> 17999 <fields> 18000 <field> 18001 <name>DMAB</name> 18002 <description>DMA register for burst 18003 accesses</description> 18004 <bitOffset>0</bitOffset> 18005 <bitWidth>16</bitWidth> 18006 </field> 18007 </fields> 18008 </register> 18009 </registers> 18010 </peripheral> 18011 <peripheral derivedFrom="TIM3"> 18012 <name>TIM4</name> 18013 <baseAddress>0x40000800</baseAddress> 18014 <interrupt> 18015 <name>TIM4</name> 18016 <description>TIM4 global interrupt</description> 18017 <value>30</value> 18018 </interrupt> 18019 </peripheral> 18020 <peripheral> 18021 <name>TIM5</name> 18022 <description>General-purpose-timers</description> 18023 <groupName>TIM</groupName> 18024 <baseAddress>0x40000C00</baseAddress> 18025 <addressBlock> 18026 <offset>0x0</offset> 18027 <size>0x400</size> 18028 <usage>registers</usage> 18029 </addressBlock> 18030 <interrupt> 18031 <name>TIM5</name> 18032 <description>TIM5 global interrupt</description> 18033 <value>50</value> 18034 </interrupt> 18035 <registers> 18036 <register> 18037 <name>CR1</name> 18038 <displayName>CR1</displayName> 18039 <description>control register 1</description> 18040 <addressOffset>0x0</addressOffset> 18041 <size>0x20</size> 18042 <access>read-write</access> 18043 <resetValue>0x0000</resetValue> 18044 <fields> 18045 <field> 18046 <name>CKD</name> 18047 <description>Clock division</description> 18048 <bitOffset>8</bitOffset> 18049 <bitWidth>2</bitWidth> 18050 <enumeratedValues><name>CKD</name><usage>read-write</usage><enumeratedValue><name>Div1</name><description>t_DTS = t_CK_INT</description><value>0</value></enumeratedValue><enumeratedValue><name>Div2</name><description>t_DTS = 2 × t_CK_INT</description><value>1</value></enumeratedValue><enumeratedValue><name>Div4</name><description>t_DTS = 4 × t_CK_INT</description><value>2</value></enumeratedValue></enumeratedValues> 18051 </field> 18052 <field> 18053 <name>ARPE</name> 18054 <description>Auto-reload preload enable</description> 18055 <bitOffset>7</bitOffset> 18056 <bitWidth>1</bitWidth> 18057 <enumeratedValues><name>ARPE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>TIMx_APRR register is not buffered</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>TIMx_APRR register is buffered</description><value>1</value></enumeratedValue></enumeratedValues> 18058 </field> 18059 <field> 18060 <name>CMS</name> 18061 <description>Center-aligned mode 18062 selection</description> 18063 <bitOffset>5</bitOffset> 18064 <bitWidth>2</bitWidth> 18065 <enumeratedValues><name>CMS</name><usage>read-write</usage><enumeratedValue><name>EdgeAligned</name><description>The counter counts up or down depending on the direction bit</description><value>0</value></enumeratedValue><enumeratedValue><name>CenterAligned1</name><description>The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.</description><value>1</value></enumeratedValue><enumeratedValue><name>CenterAligned2</name><description>The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.</description><value>2</value></enumeratedValue><enumeratedValue><name>CenterAligned3</name><description>The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.</description><value>3</value></enumeratedValue></enumeratedValues> 18066 </field> 18067 <field> 18068 <name>DIR</name> 18069 <description>Direction</description> 18070 <bitOffset>4</bitOffset> 18071 <bitWidth>1</bitWidth> 18072 <enumeratedValues><name>DIR</name><usage>read-write</usage><enumeratedValue><name>Up</name><description>Counter used as upcounter</description><value>0</value></enumeratedValue><enumeratedValue><name>Down</name><description>Counter used as downcounter</description><value>1</value></enumeratedValue></enumeratedValues> 18073 </field> 18074 <field> 18075 <name>OPM</name> 18076 <description>One-pulse mode</description> 18077 <bitOffset>3</bitOffset> 18078 <bitWidth>1</bitWidth> 18079 <enumeratedValues><name>OPM</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Counter is not stopped at update event</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Counter stops counting at the next update event (clearing the CEN bit)</description><value>1</value></enumeratedValue></enumeratedValues> 18080 </field> 18081 <field> 18082 <name>URS</name> 18083 <description>Update request source</description> 18084 <bitOffset>2</bitOffset> 18085 <bitWidth>1</bitWidth> 18086 <enumeratedValues><name>URS</name><usage>read-write</usage><enumeratedValue><name>AnyEvent</name><description>Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request</description><value>0</value></enumeratedValue><enumeratedValue><name>CounterOnly</name><description>Only counter overflow/underflow generates an update interrupt or DMA request</description><value>1</value></enumeratedValue></enumeratedValues> 18087 </field> 18088 <field> 18089 <name>UDIS</name> 18090 <description>Update disable</description> 18091 <bitOffset>1</bitOffset> 18092 <bitWidth>1</bitWidth> 18093 <enumeratedValues><name>UDIS</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>Update event enabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>Update event disabled</description><value>1</value></enumeratedValue></enumeratedValues> 18094 </field> 18095 <field> 18096 <name>CEN</name> 18097 <description>Counter enable</description> 18098 <bitOffset>0</bitOffset> 18099 <bitWidth>1</bitWidth> 18100 <enumeratedValues><name>CEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Counter disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Counter enabled</description><value>1</value></enumeratedValue></enumeratedValues> 18101 </field> 18102 </fields> 18103 </register> 18104 <register> 18105 <name>CR2</name> 18106 <displayName>CR2</displayName> 18107 <description>control register 2</description> 18108 <addressOffset>0x4</addressOffset> 18109 <size>0x20</size> 18110 <access>read-write</access> 18111 <resetValue>0x0000</resetValue> 18112 <fields> 18113 <field> 18114 <name>TI1S</name> 18115 <description>TI1 selection</description> 18116 <bitOffset>7</bitOffset> 18117 <bitWidth>1</bitWidth> 18118 <enumeratedValues><name>TI1S</name><usage>read-write</usage><enumeratedValue><name>Normal</name><description>The TIMx_CH1 pin is connected to TI1 input</description><value>0</value></enumeratedValue><enumeratedValue><name>XOR</name><description>The TIMx_CH1, CH2, CH3 pins are connected to TI1 input</description><value>1</value></enumeratedValue></enumeratedValues> 18119 </field> 18120 <field> 18121 <name>MMS</name> 18122 <description>Master mode selection</description> 18123 <bitOffset>4</bitOffset> 18124 <bitWidth>3</bitWidth> 18125 <enumeratedValues><name>MMS</name><usage>read-write</usage><enumeratedValue><name>Reset</name><description>The UG bit from the TIMx_EGR register is used as trigger output</description><value>0</value></enumeratedValue><enumeratedValue><name>Enable</name><description>The counter enable signal, CNT_EN, is used as trigger output</description><value>1</value></enumeratedValue><enumeratedValue><name>Update</name><description>The update event is selected as trigger output</description><value>2</value></enumeratedValue><enumeratedValue><name>ComparePulse</name><description>The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred</description><value>3</value></enumeratedValue><enumeratedValue><name>CompareOC1</name><description>OC1REF signal is used as trigger output</description><value>4</value></enumeratedValue><enumeratedValue><name>CompareOC2</name><description>OC2REF signal is used as trigger output</description><value>5</value></enumeratedValue><enumeratedValue><name>CompareOC3</name><description>OC3REF signal is used as trigger output</description><value>6</value></enumeratedValue><enumeratedValue><name>CompareOC4</name><description>OC4REF signal is used as trigger output</description><value>7</value></enumeratedValue></enumeratedValues> 18126 </field> 18127 <field> 18128 <name>CCDS</name> 18129 <description>Capture/compare DMA 18130 selection</description> 18131 <bitOffset>3</bitOffset> 18132 <bitWidth>1</bitWidth> 18133 <enumeratedValues><name>CCDS</name><usage>read-write</usage><enumeratedValue><name>OnCompare</name><description>CCx DMA request sent when CCx event occurs</description><value>0</value></enumeratedValue><enumeratedValue><name>OnUpdate</name><description>CCx DMA request sent when update event occurs</description><value>1</value></enumeratedValue></enumeratedValues> 18134 </field> 18135 </fields> 18136 </register> 18137 <register> 18138 <name>SMCR</name> 18139 <displayName>SMCR</displayName> 18140 <description>slave mode control register</description> 18141 <addressOffset>0x8</addressOffset> 18142 <size>0x20</size> 18143 <access>read-write</access> 18144 <resetValue>0x0000</resetValue> 18145 <fields> 18146 <field> 18147 <name>ETP</name> 18148 <description>External trigger polarity</description> 18149 <bitOffset>15</bitOffset> 18150 <bitWidth>1</bitWidth> 18151 <enumeratedValues><name>ETP</name><usage>read-write</usage><enumeratedValue><name>NotInverted</name><description>ETR is noninverted, active at high level or rising edge</description><value>0</value></enumeratedValue><enumeratedValue><name>Inverted</name><description>ETR is inverted, active at low level or falling edge</description><value>1</value></enumeratedValue></enumeratedValues> 18152 </field> 18153 <field> 18154 <name>ECE</name> 18155 <description>External clock enable</description> 18156 <bitOffset>14</bitOffset> 18157 <bitWidth>1</bitWidth> 18158 <enumeratedValues><name>ECE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>External clock mode 2 disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.</description><value>1</value></enumeratedValue></enumeratedValues> 18159 </field> 18160 <field> 18161 <name>ETPS</name> 18162 <description>External trigger prescaler</description> 18163 <bitOffset>12</bitOffset> 18164 <bitWidth>2</bitWidth> 18165 <enumeratedValues><name>ETPS</name><usage>read-write</usage><enumeratedValue><name>Div1</name><description>Prescaler OFF</description><value>0</value></enumeratedValue><enumeratedValue><name>Div2</name><description>ETRP frequency divided by 2</description><value>1</value></enumeratedValue><enumeratedValue><name>Div4</name><description>ETRP frequency divided by 4</description><value>2</value></enumeratedValue><enumeratedValue><name>Div8</name><description>ETRP frequency divided by 8</description><value>3</value></enumeratedValue></enumeratedValues> 18166 </field> 18167 <field> 18168 <name>ETF</name> 18169 <description>External trigger filter</description> 18170 <bitOffset>8</bitOffset> 18171 <bitWidth>4</bitWidth> 18172 <enumeratedValues><name>ETF</name><usage>read-write</usage><enumeratedValue><name>NoFilter</name><description>No filter, sampling is done at fDTS</description><value>0</value></enumeratedValue><enumeratedValue><name>FCK_INT_N2</name><description>fSAMPLING=fCK_INT, N=2</description><value>1</value></enumeratedValue><enumeratedValue><name>FCK_INT_N4</name><description>fSAMPLING=fCK_INT, N=4</description><value>2</value></enumeratedValue><enumeratedValue><name>FCK_INT_N8</name><description>fSAMPLING=fCK_INT, N=8</description><value>3</value></enumeratedValue><enumeratedValue><name>FDTS_Div2_N6</name><description>fSAMPLING=fDTS/2, N=6</description><value>4</value></enumeratedValue><enumeratedValue><name>FDTS_Div2_N8</name><description>fSAMPLING=fDTS/2, N=8</description><value>5</value></enumeratedValue><enumeratedValue><name>FDTS_Div4_N6</name><description>fSAMPLING=fDTS/4, N=6</description><value>6</value></enumeratedValue><enumeratedValue><name>FDTS_Div4_N8</name><description>fSAMPLING=fDTS/4, N=8</description><value>7</value></enumeratedValue><enumeratedValue><name>FDTS_Div8_N6</name><description>fSAMPLING=fDTS/8, N=6</description><value>8</value></enumeratedValue><enumeratedValue><name>FDTS_Div8_N8</name><description>fSAMPLING=fDTS/8, N=8</description><value>9</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N5</name><description>fSAMPLING=fDTS/16, N=5</description><value>10</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N6</name><description>fSAMPLING=fDTS/16, N=6</description><value>11</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N8</name><description>fSAMPLING=fDTS/16, N=8</description><value>12</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N5</name><description>fSAMPLING=fDTS/32, N=5</description><value>13</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N6</name><description>fSAMPLING=fDTS/32, N=6</description><value>14</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N8</name><description>fSAMPLING=fDTS/32, N=8</description><value>15</value></enumeratedValue></enumeratedValues> 18173 </field> 18174 <field> 18175 <name>MSM</name> 18176 <description>Master/Slave mode</description> 18177 <bitOffset>7</bitOffset> 18178 <bitWidth>1</bitWidth> 18179 <enumeratedValues><name>MSM</name><usage>read-write</usage><enumeratedValue><name>NoSync</name><description>No action</description><value>0</value></enumeratedValue><enumeratedValue><name>Sync</name><description>The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.</description><value>1</value></enumeratedValue></enumeratedValues> 18180 </field> 18181 <field> 18182 <name>TS</name> 18183 <description>Trigger selection</description> 18184 <bitOffset>4</bitOffset> 18185 <bitWidth>3</bitWidth> 18186 <enumeratedValues><name>TS</name><usage>read-write</usage><enumeratedValue><name>ITR0</name><description>Internal Trigger 0 (ITR0)</description><value>0</value></enumeratedValue><enumeratedValue><name>ITR1</name><description>Internal Trigger 1 (ITR1)</description><value>1</value></enumeratedValue><enumeratedValue><name>ITR2</name><description>Internal Trigger 2 (ITR2)</description><value>2</value></enumeratedValue><enumeratedValue><name>TI1F_ED</name><description>TI1 Edge Detector (TI1F_ED)</description><value>4</value></enumeratedValue><enumeratedValue><name>TI1FP1</name><description>Filtered Timer Input 1 (TI1FP1)</description><value>5</value></enumeratedValue><enumeratedValue><name>TI2FP2</name><description>Filtered Timer Input 2 (TI2FP2)</description><value>6</value></enumeratedValue><enumeratedValue><name>ETRF</name><description>External Trigger input (ETRF)</description><value>7</value></enumeratedValue></enumeratedValues> 18187 </field> 18188 <field> 18189 <name>SMS</name> 18190 <description>Slave mode selection</description> 18191 <bitOffset>0</bitOffset> 18192 <bitWidth>3</bitWidth> 18193 <enumeratedValues><name>SMS</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock.</description><value>0</value></enumeratedValue><enumeratedValue><name>Encoder_Mode_1</name><description>Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.</description><value>1</value></enumeratedValue><enumeratedValue><name>Encoder_Mode_2</name><description>Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.</description><value>2</value></enumeratedValue><enumeratedValue><name>Encoder_Mode_3</name><description>Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.</description><value>3</value></enumeratedValue><enumeratedValue><name>Reset_Mode</name><description>Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.</description><value>4</value></enumeratedValue><enumeratedValue><name>Gated_Mode</name><description>Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.</description><value>5</value></enumeratedValue><enumeratedValue><name>Trigger_Mode</name><description>Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.</description><value>6</value></enumeratedValue><enumeratedValue><name>Ext_Clock_Mode</name><description>External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.</description><value>7</value></enumeratedValue></enumeratedValues> 18194 </field> 18195 </fields> 18196 </register> 18197 <register> 18198 <name>DIER</name> 18199 <displayName>DIER</displayName> 18200 <description>DMA/Interrupt enable register</description> 18201 <addressOffset>0xC</addressOffset> 18202 <size>0x20</size> 18203 <access>read-write</access> 18204 <resetValue>0x0000</resetValue> 18205 <fields> 18206 <field> 18207 <name>TDE</name> 18208 <description>Trigger DMA request enable</description> 18209 <bitOffset>14</bitOffset> 18210 <bitWidth>1</bitWidth> 18211 <enumeratedValues><name>TDE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Trigger DMA request disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Trigger DMA request enabled</description><value>1</value></enumeratedValue></enumeratedValues> 18212 </field> 18213 <field> 18214 <name>CC4DE</name> 18215 <description>Capture/Compare 4 DMA request 18216 enable</description> 18217 <bitOffset>12</bitOffset> 18218 <bitWidth>1</bitWidth> 18219 <enumeratedValues derivedFrom="CC1DE"/> 18220 </field> 18221 <field> 18222 <name>CC3DE</name> 18223 <description>Capture/Compare 3 DMA request 18224 enable</description> 18225 <bitOffset>11</bitOffset> 18226 <bitWidth>1</bitWidth> 18227 <enumeratedValues derivedFrom="CC1DE"/> 18228 </field> 18229 <field> 18230 <name>CC2DE</name> 18231 <description>Capture/Compare 2 DMA request 18232 enable</description> 18233 <bitOffset>10</bitOffset> 18234 <bitWidth>1</bitWidth> 18235 <enumeratedValues derivedFrom="CC1DE"/> 18236 </field> 18237 <field> 18238 <name>CC1DE</name> 18239 <description>Capture/Compare 1 DMA request 18240 enable</description> 18241 <bitOffset>9</bitOffset> 18242 <bitWidth>1</bitWidth> 18243 <enumeratedValues><name>CC1DE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>CCx DMA request disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>CCx DMA request enabled</description><value>1</value></enumeratedValue></enumeratedValues> 18244 </field> 18245 <field> 18246 <name>UDE</name> 18247 <description>Update DMA request enable</description> 18248 <bitOffset>8</bitOffset> 18249 <bitWidth>1</bitWidth> 18250 <enumeratedValues><name>UDE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Update DMA request disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Update DMA request enabled</description><value>1</value></enumeratedValue></enumeratedValues> 18251 </field> 18252 <field> 18253 <name>TIE</name> 18254 <description>Trigger interrupt enable</description> 18255 <bitOffset>6</bitOffset> 18256 <bitWidth>1</bitWidth> 18257 <enumeratedValues><name>TIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Trigger interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Trigger interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 18258 </field> 18259 <field> 18260 <name>CC4IE</name> 18261 <description>Capture/Compare 4 interrupt 18262 enable</description> 18263 <bitOffset>4</bitOffset> 18264 <bitWidth>1</bitWidth> 18265 <enumeratedValues derivedFrom="CC1IE"/> 18266 </field> 18267 <field> 18268 <name>CC3IE</name> 18269 <description>Capture/Compare 3 interrupt 18270 enable</description> 18271 <bitOffset>3</bitOffset> 18272 <bitWidth>1</bitWidth> 18273 <enumeratedValues derivedFrom="CC1IE"/> 18274 </field> 18275 <field> 18276 <name>CC2IE</name> 18277 <description>Capture/Compare 2 interrupt 18278 enable</description> 18279 <bitOffset>2</bitOffset> 18280 <bitWidth>1</bitWidth> 18281 <enumeratedValues derivedFrom="CC1IE"/> 18282 </field> 18283 <field> 18284 <name>CC1IE</name> 18285 <description>Capture/Compare 1 interrupt 18286 enable</description> 18287 <bitOffset>1</bitOffset> 18288 <bitWidth>1</bitWidth> 18289 <enumeratedValues><name>CC1IE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>CCx interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>CCx interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 18290 </field> 18291 <field> 18292 <name>UIE</name> 18293 <description>Update interrupt enable</description> 18294 <bitOffset>0</bitOffset> 18295 <bitWidth>1</bitWidth> 18296 <enumeratedValues><name>UIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Update interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Update interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 18297 </field> 18298 </fields> 18299 </register> 18300 <register> 18301 <name>SR</name> 18302 <displayName>SR</displayName> 18303 <description>status register</description> 18304 <addressOffset>0x10</addressOffset> 18305 <size>0x20</size> 18306 <access>read-write</access> 18307 <resetValue>0x0000</resetValue> 18308 <fields> 18309 <field> 18310 <name>CC4OF</name> 18311 <description>Capture/Compare 4 overcapture 18312 flag</description> 18313 <bitOffset>12</bitOffset> 18314 <bitWidth>1</bitWidth> 18315 <enumeratedValues derivedFrom="CC1OFR"/> 18316 <enumeratedValues derivedFrom="CC1OFW"/> 18317 </field> 18318 <field> 18319 <name>CC3OF</name> 18320 <description>Capture/Compare 3 overcapture 18321 flag</description> 18322 <bitOffset>11</bitOffset> 18323 <bitWidth>1</bitWidth> 18324 <enumeratedValues derivedFrom="CC1OFR"/> 18325 <enumeratedValues derivedFrom="CC1OFW"/> 18326 </field> 18327 <field> 18328 <name>CC2OF</name> 18329 <description>Capture/compare 2 overcapture 18330 flag</description> 18331 <bitOffset>10</bitOffset> 18332 <bitWidth>1</bitWidth> 18333 <enumeratedValues derivedFrom="CC1OFR"/> 18334 <enumeratedValues derivedFrom="CC1OFW"/> 18335 </field> 18336 <field> 18337 <name>CC1OF</name> 18338 <description>Capture/Compare 1 overcapture 18339 flag</description> 18340 <bitOffset>9</bitOffset> 18341 <bitWidth>1</bitWidth> 18342 <enumeratedValues><name>CC1OFR</name><usage>read</usage><enumeratedValue><name>Overcapture</name><description>The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set</description><value>1</value></enumeratedValue></enumeratedValues> 18343 <enumeratedValues><name>CC1OFW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clear flag</description><value>0</value></enumeratedValue></enumeratedValues> 18344 </field> 18345 <field> 18346 <name>TIF</name> 18347 <description>Trigger interrupt flag</description> 18348 <bitOffset>6</bitOffset> 18349 <bitWidth>1</bitWidth> 18350 <enumeratedValues><name>TIFR</name><usage>read</usage><enumeratedValue><name>NoTrigger</name><description>No trigger event occurred</description><value>0</value></enumeratedValue><enumeratedValue><name>Trigger</name><description>Trigger interrupt pending</description><value>1</value></enumeratedValue></enumeratedValues> 18351 <enumeratedValues><name>TIFW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clear flag</description><value>0</value></enumeratedValue></enumeratedValues> 18352 </field> 18353 <field> 18354 <name>CC4IF</name> 18355 <description>Capture/Compare 4 interrupt 18356 flag</description> 18357 <bitOffset>4</bitOffset> 18358 <bitWidth>1</bitWidth> 18359 <enumeratedValues derivedFrom="CC1IFR"/> 18360 <enumeratedValues derivedFrom="CC1IFW"/> 18361 </field> 18362 <field> 18363 <name>CC3IF</name> 18364 <description>Capture/Compare 3 interrupt 18365 flag</description> 18366 <bitOffset>3</bitOffset> 18367 <bitWidth>1</bitWidth> 18368 <enumeratedValues derivedFrom="CC1IFR"/> 18369 <enumeratedValues derivedFrom="CC1IFW"/> 18370 </field> 18371 <field> 18372 <name>CC2IF</name> 18373 <description>Capture/Compare 2 interrupt 18374 flag</description> 18375 <bitOffset>2</bitOffset> 18376 <bitWidth>1</bitWidth> 18377 <enumeratedValues derivedFrom="CC1IFR"/> 18378 <enumeratedValues derivedFrom="CC1IFW"/> 18379 </field> 18380 <field> 18381 <name>CC1IF</name> 18382 <description>Capture/compare 1 interrupt 18383 flag</description> 18384 <bitOffset>1</bitOffset> 18385 <bitWidth>1</bitWidth> 18386 <enumeratedValues><name>CC1IFR</name><usage>read</usage><enumeratedValue><name>Match</name><description>If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.</description><value>1</value></enumeratedValue></enumeratedValues> 18387 <enumeratedValues><name>CC1IFW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clear flag</description><value>0</value></enumeratedValue></enumeratedValues> 18388 </field> 18389 <field> 18390 <name>UIF</name> 18391 <description>Update interrupt flag</description> 18392 <bitOffset>0</bitOffset> 18393 <bitWidth>1</bitWidth> 18394 <enumeratedValues><name>UIF</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>No update occurred</description><value>0</value></enumeratedValue><enumeratedValue><name>UpdatePending</name><description>Update interrupt pending.</description><value>1</value></enumeratedValue></enumeratedValues> 18395 </field> 18396 </fields> 18397 </register> 18398 <register> 18399 <name>EGR</name> 18400 <displayName>EGR</displayName> 18401 <description>event generation register</description> 18402 <addressOffset>0x14</addressOffset> 18403 <size>0x20</size> 18404 <access>write-only</access> 18405 <resetValue>0x0000</resetValue> 18406 <fields> 18407 <field> 18408 <name>TG</name> 18409 <description>Trigger generation</description> 18410 <bitOffset>6</bitOffset> 18411 <bitWidth>1</bitWidth> 18412 <enumeratedValues><name>TGW</name><usage>write</usage><enumeratedValue><name>Trigger</name><description>The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.</description><value>1</value></enumeratedValue></enumeratedValues> 18413 </field> 18414 <field> 18415 <name>CC4G</name> 18416 <description>Capture/compare 4 18417 generation</description> 18418 <bitOffset>4</bitOffset> 18419 <bitWidth>1</bitWidth> 18420 <enumeratedValues derivedFrom="CC1GW"/> 18421 </field> 18422 <field> 18423 <name>CC3G</name> 18424 <description>Capture/compare 3 18425 generation</description> 18426 <bitOffset>3</bitOffset> 18427 <bitWidth>1</bitWidth> 18428 <enumeratedValues derivedFrom="CC1GW"/> 18429 </field> 18430 <field> 18431 <name>CC2G</name> 18432 <description>Capture/compare 2 18433 generation</description> 18434 <bitOffset>2</bitOffset> 18435 <bitWidth>1</bitWidth> 18436 <enumeratedValues derivedFrom="CC1GW"/> 18437 </field> 18438 <field> 18439 <name>CC1G</name> 18440 <description>Capture/compare 1 18441 generation</description> 18442 <bitOffset>1</bitOffset> 18443 <bitWidth>1</bitWidth> 18444 <enumeratedValues><name>CC1GW</name><usage>write</usage><enumeratedValue><name>Trigger</name><description>If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.</description><value>1</value></enumeratedValue></enumeratedValues> 18445 </field> 18446 <field> 18447 <name>UG</name> 18448 <description>Update generation</description> 18449 <bitOffset>0</bitOffset> 18450 <bitWidth>1</bitWidth> 18451 <enumeratedValues><name>UG</name><usage>read-write</usage><enumeratedValue><name>Update</name><description>Re-initializes the timer counter and generates an update of the registers.</description><value>1</value></enumeratedValue></enumeratedValues> 18452 </field> 18453 </fields> 18454 </register> 18455 <register> 18456 <name>CCMR1_Output</name> 18457 <displayName>CCMR1_Output</displayName> 18458 <description>capture/compare mode register 1 (output 18459 mode)</description> 18460 <addressOffset>0x18</addressOffset> 18461 <size>0x20</size> 18462 <access>read-write</access> 18463 <resetValue>0x00000000</resetValue> 18464 <fields> 18465 <field> 18466 <name>OC2CE</name> 18467 <description>OC2CE</description> 18468 <bitOffset>15</bitOffset> 18469 <bitWidth>1</bitWidth> 18470 </field> 18471 <field> 18472 <name>OC2M</name> 18473 <description>OC2M</description> 18474 <bitOffset>12</bitOffset> 18475 <bitWidth>3</bitWidth> 18476 <enumeratedValues derivedFrom="OC1M"/> 18477 </field> 18478 <field> 18479 <name>OC2PE</name> 18480 <description>OC2PE</description> 18481 <bitOffset>11</bitOffset> 18482 <bitWidth>1</bitWidth> 18483 <enumeratedValues><name>OC2PE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Preload register on CCR2 enabled. Preload value is loaded into active register on each update event</description><value>1</value></enumeratedValue></enumeratedValues> 18484 </field> 18485 <field> 18486 <name>OC2FE</name> 18487 <description>OC2FE</description> 18488 <bitOffset>10</bitOffset> 18489 <bitWidth>1</bitWidth> 18490 </field> 18491 <field> 18492 <name>CC2S</name> 18493 <description>CC2S</description> 18494 <bitOffset>8</bitOffset> 18495 <bitWidth>2</bitWidth> 18496 <enumeratedValues><name>CC2S</name><usage>read-write</usage><enumeratedValue><name>Output</name><description>CC2 channel is configured as output</description><value>0</value></enumeratedValue></enumeratedValues> 18497 </field> 18498 <field> 18499 <name>OC1CE</name> 18500 <description>OC1CE</description> 18501 <bitOffset>7</bitOffset> 18502 <bitWidth>1</bitWidth> 18503 </field> 18504 <field> 18505 <name>OC1M</name> 18506 <description>OC1M</description> 18507 <bitOffset>4</bitOffset> 18508 <bitWidth>3</bitWidth> 18509 <enumeratedValues><name>OC1M</name><usage>read-write</usage><enumeratedValue><name>Frozen</name><description>The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs</description><value>0</value></enumeratedValue><enumeratedValue><name>ActiveOnMatch</name><description>Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register</description><value>1</value></enumeratedValue><enumeratedValue><name>InactiveOnMatch</name><description>Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register</description><value>2</value></enumeratedValue><enumeratedValue><name>Toggle</name><description>OCyREF toggles when TIMx_CNT=TIMx_CCRy</description><value>3</value></enumeratedValue><enumeratedValue><name>ForceInactive</name><description>OCyREF is forced low</description><value>4</value></enumeratedValue><enumeratedValue><name>ForceActive</name><description>OCyREF is forced high</description><value>5</value></enumeratedValue><enumeratedValue><name>PwmMode1</name><description>In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active</description><value>6</value></enumeratedValue><enumeratedValue><name>PwmMode2</name><description>Inversely to PwmMode1</description><value>7</value></enumeratedValue></enumeratedValues> 18510 </field> 18511 <field> 18512 <name>OC1PE</name> 18513 <description>OC1PE</description> 18514 <bitOffset>3</bitOffset> 18515 <bitWidth>1</bitWidth> 18516 <enumeratedValues><name>OC1PE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Preload register on CCR1 enabled. Preload value is loaded into active register on each update event</description><value>1</value></enumeratedValue></enumeratedValues> 18517 </field> 18518 <field> 18519 <name>OC1FE</name> 18520 <description>OC1FE</description> 18521 <bitOffset>2</bitOffset> 18522 <bitWidth>1</bitWidth> 18523 </field> 18524 <field> 18525 <name>CC1S</name> 18526 <description>CC1S</description> 18527 <bitOffset>0</bitOffset> 18528 <bitWidth>2</bitWidth> 18529 <enumeratedValues><name>CC1S</name><usage>read-write</usage><enumeratedValue><name>Output</name><description>CC1 channel is configured as output</description><value>0</value></enumeratedValue></enumeratedValues> 18530 </field> 18531 </fields> 18532 </register> 18533 <register> 18534 <name>CCMR1_Input</name> 18535 <displayName>CCMR1_Input</displayName> 18536 <description>capture/compare mode register 1 (input 18537 mode)</description> 18538 <alternateRegister>CCMR1_Output</alternateRegister> 18539 <addressOffset>0x18</addressOffset> 18540 <size>0x20</size> 18541 <access>read-write</access> 18542 <resetValue>0x00000000</resetValue> 18543 <fields> 18544 <field> 18545 <name>IC2F</name> 18546 <description>Input capture 2 filter</description> 18547 <bitOffset>12</bitOffset> 18548 <bitWidth>4</bitWidth> 18549 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 18550 </field> 18551 <field> 18552 <name>IC2PSC</name> 18553 <description>Input capture 2 prescaler</description> 18554 <bitOffset>10</bitOffset> 18555 <bitWidth>2</bitWidth> 18556 </field> 18557 <field> 18558 <name>CC2S</name> 18559 <description>Capture/Compare 2 18560 selection</description> 18561 <bitOffset>8</bitOffset> 18562 <bitWidth>2</bitWidth> 18563 <enumeratedValues><name>CC2S</name><usage>read-write</usage><enumeratedValue><name>TI2</name><description>CC2 channel is configured as input, IC2 is mapped on TI2</description><value>1</value></enumeratedValue><enumeratedValue><name>TI1</name><description>CC2 channel is configured as input, IC2 is mapped on TI1</description><value>2</value></enumeratedValue><enumeratedValue><name>TRC</name><description>CC2 channel is configured as input, IC2 is mapped on TRC</description><value>3</value></enumeratedValue></enumeratedValues> 18564 </field> 18565 <field> 18566 <name>IC1F</name> 18567 <description>Input capture 1 filter</description> 18568 <bitOffset>4</bitOffset> 18569 <bitWidth>4</bitWidth> 18570 <enumeratedValues><name>IC1F</name><usage>read-write</usage><enumeratedValue><name>NoFilter</name><description>No filter, sampling is done at fDTS</description><value>0</value></enumeratedValue><enumeratedValue><name>FCK_INT_N2</name><description>fSAMPLING=fCK_INT, N=2</description><value>1</value></enumeratedValue><enumeratedValue><name>FCK_INT_N4</name><description>fSAMPLING=fCK_INT, N=4</description><value>2</value></enumeratedValue><enumeratedValue><name>FCK_INT_N8</name><description>fSAMPLING=fCK_INT, N=8</description><value>3</value></enumeratedValue><enumeratedValue><name>FDTS_Div2_N6</name><description>fSAMPLING=fDTS/2, N=6</description><value>4</value></enumeratedValue><enumeratedValue><name>FDTS_Div2_N8</name><description>fSAMPLING=fDTS/2, N=8</description><value>5</value></enumeratedValue><enumeratedValue><name>FDTS_Div4_N6</name><description>fSAMPLING=fDTS/4, N=6</description><value>6</value></enumeratedValue><enumeratedValue><name>FDTS_Div4_N8</name><description>fSAMPLING=fDTS/4, N=8</description><value>7</value></enumeratedValue><enumeratedValue><name>FDTS_Div8_N6</name><description>fSAMPLING=fDTS/8, N=6</description><value>8</value></enumeratedValue><enumeratedValue><name>FDTS_Div8_N8</name><description>fSAMPLING=fDTS/8, N=8</description><value>9</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N5</name><description>fSAMPLING=fDTS/16, N=5</description><value>10</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N6</name><description>fSAMPLING=fDTS/16, N=6</description><value>11</value></enumeratedValue><enumeratedValue><name>FDTS_Div16_N8</name><description>fSAMPLING=fDTS/16, N=8</description><value>12</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N5</name><description>fSAMPLING=fDTS/32, N=5</description><value>13</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N6</name><description>fSAMPLING=fDTS/32, N=6</description><value>14</value></enumeratedValue><enumeratedValue><name>FDTS_Div32_N8</name><description>fSAMPLING=fDTS/32, N=8</description><value>15</value></enumeratedValue></enumeratedValues> 18571 </field> 18572 <field> 18573 <name>IC1PSC</name> 18574 <description>Input capture 1 prescaler</description> 18575 <bitOffset>2</bitOffset> 18576 <bitWidth>2</bitWidth> 18577 </field> 18578 <field> 18579 <name>CC1S</name> 18580 <description>Capture/Compare 1 18581 selection</description> 18582 <bitOffset>0</bitOffset> 18583 <bitWidth>2</bitWidth> 18584 <enumeratedValues><name>CC1S</name><usage>read-write</usage><enumeratedValue><name>TI1</name><description>CC1 channel is configured as input, IC1 is mapped on TI1</description><value>1</value></enumeratedValue><enumeratedValue><name>TI2</name><description>CC1 channel is configured as input, IC1 is mapped on TI2</description><value>2</value></enumeratedValue><enumeratedValue><name>TRC</name><description>CC1 channel is configured as input, IC1 is mapped on TRC</description><value>3</value></enumeratedValue></enumeratedValues> 18585 </field> 18586 </fields> 18587 </register> 18588 <register> 18589 <name>CCMR2_Output</name> 18590 <displayName>CCMR2_Output</displayName> 18591 <description>capture/compare mode register 2 (output 18592 mode)</description> 18593 <addressOffset>0x1C</addressOffset> 18594 <size>0x20</size> 18595 <access>read-write</access> 18596 <resetValue>0x00000000</resetValue> 18597 <fields> 18598 <field> 18599 <name>OC4CE</name> 18600 <description>O24CE</description> 18601 <bitOffset>15</bitOffset> 18602 <bitWidth>1</bitWidth> 18603 </field> 18604 <field> 18605 <name>OC4M</name> 18606 <description>OC4M</description> 18607 <bitOffset>12</bitOffset> 18608 <bitWidth>3</bitWidth> 18609 <enumeratedValues derivedFrom="OC3M"/> 18610 </field> 18611 <field> 18612 <name>OC4PE</name> 18613 <description>OC4PE</description> 18614 <bitOffset>11</bitOffset> 18615 <bitWidth>1</bitWidth> 18616 <enumeratedValues><name>OC4PE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Preload register on CCR4 disabled. New values written to CCR4 are taken into account immediately</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Preload register on CCR4 enabled. Preload value is loaded into active register on each update event</description><value>1</value></enumeratedValue></enumeratedValues> 18617 </field> 18618 <field> 18619 <name>OC4FE</name> 18620 <description>OC4FE</description> 18621 <bitOffset>10</bitOffset> 18622 <bitWidth>1</bitWidth> 18623 </field> 18624 <field> 18625 <name>CC4S</name> 18626 <description>CC4S</description> 18627 <bitOffset>8</bitOffset> 18628 <bitWidth>2</bitWidth> 18629 <enumeratedValues><name>CC4S</name><usage>read-write</usage><enumeratedValue><name>Output</name><description>CC4 channel is configured as output</description><value>0</value></enumeratedValue></enumeratedValues> 18630 </field> 18631 <field> 18632 <name>OC3CE</name> 18633 <description>OC3CE</description> 18634 <bitOffset>7</bitOffset> 18635 <bitWidth>1</bitWidth> 18636 </field> 18637 <field> 18638 <name>OC3M</name> 18639 <description>OC3M</description> 18640 <bitOffset>4</bitOffset> 18641 <bitWidth>3</bitWidth> 18642 <enumeratedValues><name>OC3M</name><usage>read-write</usage><enumeratedValue><name>Frozen</name><description>The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs</description><value>0</value></enumeratedValue><enumeratedValue><name>ActiveOnMatch</name><description>Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register</description><value>1</value></enumeratedValue><enumeratedValue><name>InactiveOnMatch</name><description>Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register</description><value>2</value></enumeratedValue><enumeratedValue><name>Toggle</name><description>OCyREF toggles when TIMx_CNT=TIMx_CCRy</description><value>3</value></enumeratedValue><enumeratedValue><name>ForceInactive</name><description>OCyREF is forced low</description><value>4</value></enumeratedValue><enumeratedValue><name>ForceActive</name><description>OCyREF is forced high</description><value>5</value></enumeratedValue><enumeratedValue><name>PwmMode1</name><description>In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active</description><value>6</value></enumeratedValue><enumeratedValue><name>PwmMode2</name><description>Inversely to PwmMode1</description><value>7</value></enumeratedValue></enumeratedValues> 18643 </field> 18644 <field> 18645 <name>OC3PE</name> 18646 <description>OC3PE</description> 18647 <bitOffset>3</bitOffset> 18648 <bitWidth>1</bitWidth> 18649 <enumeratedValues><name>OC3PE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Preload register on CCR3 enabled. Preload value is loaded into active register on each update event</description><value>1</value></enumeratedValue></enumeratedValues> 18650 </field> 18651 <field> 18652 <name>OC3FE</name> 18653 <description>OC3FE</description> 18654 <bitOffset>2</bitOffset> 18655 <bitWidth>1</bitWidth> 18656 </field> 18657 <field> 18658 <name>CC3S</name> 18659 <description>CC3S</description> 18660 <bitOffset>0</bitOffset> 18661 <bitWidth>2</bitWidth> 18662 <enumeratedValues><name>CC3S</name><usage>read-write</usage><enumeratedValue><name>Output</name><description>CC3 channel is configured as output</description><value>0</value></enumeratedValue></enumeratedValues> 18663 </field> 18664 </fields> 18665 </register> 18666 <register> 18667 <name>CCMR2_Input</name> 18668 <displayName>CCMR2_Input</displayName> 18669 <description>capture/compare mode register 2 (input 18670 mode)</description> 18671 <alternateRegister>CCMR2_Output</alternateRegister> 18672 <addressOffset>0x1C</addressOffset> 18673 <size>0x20</size> 18674 <access>read-write</access> 18675 <resetValue>0x00000000</resetValue> 18676 <fields> 18677 <field> 18678 <name>IC4F</name> 18679 <description>Input capture 4 filter</description> 18680 <bitOffset>12</bitOffset> 18681 <bitWidth>4</bitWidth> 18682 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 18683 </field> 18684 <field> 18685 <name>IC4PSC</name> 18686 <description>Input capture 4 prescaler</description> 18687 <bitOffset>10</bitOffset> 18688 <bitWidth>2</bitWidth> 18689 <writeConstraint><range><minimum>0</minimum><maximum>3</maximum></range></writeConstraint> 18690 </field> 18691 <field> 18692 <name>CC4S</name> 18693 <description>Capture/Compare 4 18694 selection</description> 18695 <bitOffset>8</bitOffset> 18696 <bitWidth>2</bitWidth> 18697 <enumeratedValues><name>CC4S</name><usage>read-write</usage><enumeratedValue><name>TI4</name><description>CC4 channel is configured as input, IC4 is mapped on TI4</description><value>1</value></enumeratedValue><enumeratedValue><name>TI3</name><description>CC4 channel is configured as input, IC4 is mapped on TI3</description><value>2</value></enumeratedValue><enumeratedValue><name>TRC</name><description>CC4 channel is configured as input, IC4 is mapped on TRC</description><value>3</value></enumeratedValue></enumeratedValues> 18698 </field> 18699 <field> 18700 <name>IC3F</name> 18701 <description>Input capture 3 filter</description> 18702 <bitOffset>4</bitOffset> 18703 <bitWidth>4</bitWidth> 18704 <writeConstraint><range><minimum>0</minimum><maximum>15</maximum></range></writeConstraint> 18705 </field> 18706 <field> 18707 <name>IC3PSC</name> 18708 <description>Input capture 3 prescaler</description> 18709 <bitOffset>2</bitOffset> 18710 <bitWidth>2</bitWidth> 18711 <writeConstraint><range><minimum>0</minimum><maximum>3</maximum></range></writeConstraint> 18712 </field> 18713 <field> 18714 <name>CC3S</name> 18715 <description>Capture/compare 3 18716 selection</description> 18717 <bitOffset>0</bitOffset> 18718 <bitWidth>2</bitWidth> 18719 <enumeratedValues><name>CC3S</name><usage>read-write</usage><enumeratedValue><name>TI3</name><description>CC3 channel is configured as input, IC3 is mapped on TI3</description><value>1</value></enumeratedValue><enumeratedValue><name>TI4</name><description>CC3 channel is configured as input, IC3 is mapped on TI4</description><value>2</value></enumeratedValue><enumeratedValue><name>TRC</name><description>CC3 channel is configured as input, IC3 is mapped on TRC</description><value>3</value></enumeratedValue></enumeratedValues> 18720 </field> 18721 </fields> 18722 </register> 18723 <register> 18724 <name>CCER</name> 18725 <displayName>CCER</displayName> 18726 <description>capture/compare enable 18727 register</description> 18728 <addressOffset>0x20</addressOffset> 18729 <size>0x20</size> 18730 <access>read-write</access> 18731 <resetValue>0x0000</resetValue> 18732 <fields> 18733 <field> 18734 <name>CC4NP</name> 18735 <description>Capture/Compare 4 output 18736 Polarity</description> 18737 <bitOffset>15</bitOffset> 18738 <bitWidth>1</bitWidth> 18739 </field> 18740 <field> 18741 <name>CC4P</name> 18742 <description>Capture/Compare 3 output 18743 Polarity</description> 18744 <bitOffset>13</bitOffset> 18745 <bitWidth>1</bitWidth> 18746 </field> 18747 <field> 18748 <name>CC4E</name> 18749 <description>Capture/Compare 4 output 18750 enable</description> 18751 <bitOffset>12</bitOffset> 18752 <bitWidth>1</bitWidth> 18753 </field> 18754 <field> 18755 <name>CC3NP</name> 18756 <description>Capture/Compare 3 output 18757 Polarity</description> 18758 <bitOffset>11</bitOffset> 18759 <bitWidth>1</bitWidth> 18760 </field> 18761 <field> 18762 <name>CC3P</name> 18763 <description>Capture/Compare 3 output 18764 Polarity</description> 18765 <bitOffset>9</bitOffset> 18766 <bitWidth>1</bitWidth> 18767 </field> 18768 <field> 18769 <name>CC3E</name> 18770 <description>Capture/Compare 3 output 18771 enable</description> 18772 <bitOffset>8</bitOffset> 18773 <bitWidth>1</bitWidth> 18774 </field> 18775 <field> 18776 <name>CC2NP</name> 18777 <description>Capture/Compare 2 output 18778 Polarity</description> 18779 <bitOffset>7</bitOffset> 18780 <bitWidth>1</bitWidth> 18781 </field> 18782 <field> 18783 <name>CC2P</name> 18784 <description>Capture/Compare 2 output 18785 Polarity</description> 18786 <bitOffset>5</bitOffset> 18787 <bitWidth>1</bitWidth> 18788 </field> 18789 <field> 18790 <name>CC2E</name> 18791 <description>Capture/Compare 2 output 18792 enable</description> 18793 <bitOffset>4</bitOffset> 18794 <bitWidth>1</bitWidth> 18795 </field> 18796 <field> 18797 <name>CC1NP</name> 18798 <description>Capture/Compare 1 output 18799 Polarity</description> 18800 <bitOffset>3</bitOffset> 18801 <bitWidth>1</bitWidth> 18802 </field> 18803 <field> 18804 <name>CC1P</name> 18805 <description>Capture/Compare 1 output 18806 Polarity</description> 18807 <bitOffset>1</bitOffset> 18808 <bitWidth>1</bitWidth> 18809 </field> 18810 <field> 18811 <name>CC1E</name> 18812 <description>Capture/Compare 1 output 18813 enable</description> 18814 <bitOffset>0</bitOffset> 18815 <bitWidth>1</bitWidth> 18816 </field> 18817 </fields> 18818 </register> 18819 <register> 18820 <name>CNT</name> 18821 <displayName>CNT</displayName> 18822 <description>counter</description> 18823 <addressOffset>0x24</addressOffset> 18824 <size>0x20</size> 18825 <access>read-write</access> 18826 <resetValue>0x00000000</resetValue> 18827 <fields> 18828 <field><name>CNT</name><description>Counter value</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth><writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint> 18829 </field></fields> 18830 </register> 18831 <register> 18832 <name>PSC</name> 18833 <displayName>PSC</displayName> 18834 <description>prescaler</description> 18835 <addressOffset>0x28</addressOffset> 18836 <size>0x20</size> 18837 <access>read-write</access> 18838 <resetValue>0x0000</resetValue> 18839 <fields> 18840 <field> 18841 <name>PSC</name> 18842 <description>Prescaler value</description> 18843 <bitOffset>0</bitOffset> 18844 <bitWidth>16</bitWidth> 18845 <writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint> 18846 </field> 18847 </fields> 18848 </register> 18849 <register> 18850 <name>ARR</name> 18851 <displayName>ARR</displayName> 18852 <description>auto-reload register</description> 18853 <addressOffset>0x2C</addressOffset> 18854 <size>0x20</size> 18855 <access>read-write</access> 18856 <resetValue>0x00000000</resetValue> 18857 <fields> 18858 <field><name>ARR</name><description>Auto-reload value</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth><writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint> 18859 </field></fields> 18860 </register> 18861 <register> 18862 <dim>4</dim><dimIncrement>0x4</dimIncrement><dimIndex>1,2,3,4</dimIndex><name>CCR%s</name> 18863 <displayName>CCR1</displayName> 18864 <description>capture/compare register</description> 18865 <addressOffset>0x34</addressOffset> 18866 <size>0x20</size> 18867 <access>read-write</access> 18868 <resetValue>0x00000000</resetValue> 18869 <fields> 18870 <field><name>CCR</name><description>Capture/Compare value</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth><writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint> 18871 </field></fields> 18872 </register> 18873 <register> 18874 <name>DCR</name> 18875 <displayName>DCR</displayName> 18876 <description>DMA control register</description> 18877 <addressOffset>0x48</addressOffset> 18878 <size>0x20</size> 18879 <access>read-write</access> 18880 <resetValue>0x0000</resetValue> 18881 <fields> 18882 <field> 18883 <name>DBL</name> 18884 <description>DMA burst length</description> 18885 <bitOffset>8</bitOffset> 18886 <bitWidth>5</bitWidth> 18887 <writeConstraint><range><minimum>0</minimum><maximum>18</maximum></range></writeConstraint> 18888 </field> 18889 <field> 18890 <name>DBA</name> 18891 <description>DMA base address</description> 18892 <bitOffset>0</bitOffset> 18893 <bitWidth>5</bitWidth> 18894 <writeConstraint><range><minimum>0</minimum><maximum>31</maximum></range></writeConstraint> 18895 </field> 18896 </fields> 18897 </register> 18898 <register> 18899 <name>DMAR</name> 18900 <displayName>DMAR</displayName> 18901 <description>DMA address for full transfer</description> 18902 <addressOffset>0x4C</addressOffset> 18903 <size>0x20</size> 18904 <access>read-write</access> 18905 <resetValue>0x0000</resetValue> 18906 <fields> 18907 <field> 18908 <name>DMAB</name> 18909 <description>DMA register for burst 18910 accesses</description> 18911 <bitOffset>0</bitOffset> 18912 <bitWidth>16</bitWidth> 18913 </field> 18914 </fields> 18915 </register> 18916 <register> 18917 <name>OR</name> 18918 <displayName>OR</displayName> 18919 <description>TIM5 option register</description> 18920 <addressOffset>0x50</addressOffset> 18921 <size>0x20</size> 18922 <access>read-write</access> 18923 <resetValue>0x0000</resetValue> 18924 <fields> 18925 <field> 18926 <name>IT4_RMP</name> 18927 <description>Timer Input 4 remap</description> 18928 <bitOffset>6</bitOffset> 18929 <bitWidth>2</bitWidth> 18930 </field> 18931 </fields> 18932 </register> 18933 </registers> 18934 </peripheral> 18935 <peripheral> 18936 <name>TIM9</name> 18937 <description>General purpose timers</description> 18938 <groupName>TIM</groupName> 18939 <baseAddress>0x40014000</baseAddress> 18940 <addressBlock> 18941 <offset>0x0</offset> 18942 <size>0x400</size> 18943 <usage>registers</usage> 18944 </addressBlock> 18945 <interrupt> 18946 <name>TIM1_BRK_TIM9</name> 18947 <description>TIM1 Break interrupt and TIM9 global 18948 interrupt</description> 18949 <value>24</value> 18950 </interrupt> 18951 <registers> 18952 <register> 18953 <name>CR1</name> 18954 <displayName>CR1</displayName> 18955 <description>control register 1</description> 18956 <addressOffset>0x0</addressOffset> 18957 <size>0x20</size> 18958 <access>read-write</access> 18959 <resetValue>0x0000</resetValue> 18960 <fields> 18961 <field> 18962 <name>CKD</name> 18963 <description>Clock division</description> 18964 <bitOffset>8</bitOffset> 18965 <bitWidth>2</bitWidth> 18966 <enumeratedValues><name>CKD</name><usage>read-write</usage><enumeratedValue><name>Div1</name><description>t_DTS = t_CK_INT</description><value>0</value></enumeratedValue><enumeratedValue><name>Div2</name><description>t_DTS = 2 × t_CK_INT</description><value>1</value></enumeratedValue><enumeratedValue><name>Div4</name><description>t_DTS = 4 × t_CK_INT</description><value>2</value></enumeratedValue></enumeratedValues> 18967 </field> 18968 <field> 18969 <name>ARPE</name> 18970 <description>Auto-reload preload enable</description> 18971 <bitOffset>7</bitOffset> 18972 <bitWidth>1</bitWidth> 18973 <enumeratedValues><name>ARPE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>TIMx_APRR register is not buffered</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>TIMx_APRR register is buffered</description><value>1</value></enumeratedValue></enumeratedValues> 18974 </field> 18975 <field> 18976 <name>OPM</name> 18977 <description>One-pulse mode</description> 18978 <bitOffset>3</bitOffset> 18979 <bitWidth>1</bitWidth> 18980 <enumeratedValues><name>OPM</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Counter is not stopped at update event</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Counter stops counting at the next update event (clearing the CEN bit)</description><value>1</value></enumeratedValue></enumeratedValues> 18981 </field> 18982 <field> 18983 <name>URS</name> 18984 <description>Update request source</description> 18985 <bitOffset>2</bitOffset> 18986 <bitWidth>1</bitWidth> 18987 <enumeratedValues><name>URS</name><usage>read-write</usage><enumeratedValue><name>AnyEvent</name><description>Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request</description><value>0</value></enumeratedValue><enumeratedValue><name>CounterOnly</name><description>Only counter overflow/underflow generates an update interrupt or DMA request</description><value>1</value></enumeratedValue></enumeratedValues> 18988 </field> 18989 <field> 18990 <name>UDIS</name> 18991 <description>Update disable</description> 18992 <bitOffset>1</bitOffset> 18993 <bitWidth>1</bitWidth> 18994 <enumeratedValues><name>UDIS</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>Update event enabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>Update event disabled</description><value>1</value></enumeratedValue></enumeratedValues> 18995 </field> 18996 <field> 18997 <name>CEN</name> 18998 <description>Counter enable</description> 18999 <bitOffset>0</bitOffset> 19000 <bitWidth>1</bitWidth> 19001 <enumeratedValues><name>CEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Counter disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Counter enabled</description><value>1</value></enumeratedValue></enumeratedValues> 19002 </field> 19003 </fields> 19004 </register> 19005 <register> 19006 <name>CR2</name> 19007 <displayName>CR2</displayName> 19008 <description>control register 2</description> 19009 <addressOffset>0x4</addressOffset> 19010 <size>0x20</size> 19011 <access>read-write</access> 19012 <resetValue>0x0000</resetValue> 19013 <fields> 19014 <field> 19015 <name>MMS</name> 19016 <description>Master mode selection</description> 19017 <bitOffset>4</bitOffset> 19018 <bitWidth>3</bitWidth> 19019 </field> 19020 </fields> 19021 </register> 19022 <register> 19023 <name>SMCR</name> 19024 <displayName>SMCR</displayName> 19025 <description>slave mode control register</description> 19026 <addressOffset>0x8</addressOffset> 19027 <size>0x20</size> 19028 <access>read-write</access> 19029 <resetValue>0x0000</resetValue> 19030 <fields> 19031 <field> 19032 <name>MSM</name> 19033 <description>Master/Slave mode</description> 19034 <bitOffset>7</bitOffset> 19035 <bitWidth>1</bitWidth> 19036 </field> 19037 <field> 19038 <name>TS</name> 19039 <description>Trigger selection</description> 19040 <bitOffset>4</bitOffset> 19041 <bitWidth>3</bitWidth> 19042 </field> 19043 <field> 19044 <name>SMS</name> 19045 <description>Slave mode selection</description> 19046 <bitOffset>0</bitOffset> 19047 <bitWidth>3</bitWidth> 19048 </field> 19049 </fields> 19050 </register> 19051 <register> 19052 <name>DIER</name> 19053 <displayName>DIER</displayName> 19054 <description>DMA/Interrupt enable register</description> 19055 <addressOffset>0xC</addressOffset> 19056 <size>0x20</size> 19057 <access>read-write</access> 19058 <resetValue>0x0000</resetValue> 19059 <fields> 19060 <field> 19061 <name>TIE</name> 19062 <description>Trigger interrupt enable</description> 19063 <bitOffset>6</bitOffset> 19064 <bitWidth>1</bitWidth> 19065 </field> 19066 <field> 19067 <name>CC2IE</name> 19068 <description>Capture/Compare 2 interrupt 19069 enable</description> 19070 <bitOffset>2</bitOffset> 19071 <bitWidth>1</bitWidth> 19072 </field> 19073 <field> 19074 <name>CC1IE</name> 19075 <description>Capture/Compare 1 interrupt 19076 enable</description> 19077 <bitOffset>1</bitOffset> 19078 <bitWidth>1</bitWidth> 19079 </field> 19080 <field> 19081 <name>UIE</name> 19082 <description>Update interrupt enable</description> 19083 <bitOffset>0</bitOffset> 19084 <bitWidth>1</bitWidth> 19085 <enumeratedValues><name>UIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Update interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Update interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 19086 </field> 19087 </fields> 19088 </register> 19089 <register> 19090 <name>SR</name> 19091 <displayName>SR</displayName> 19092 <description>status register</description> 19093 <addressOffset>0x10</addressOffset> 19094 <size>0x20</size> 19095 <access>read-write</access> 19096 <resetValue>0x0000</resetValue> 19097 <fields> 19098 <field> 19099 <name>CC2OF</name> 19100 <description>Capture/compare 2 overcapture 19101 flag</description> 19102 <bitOffset>10</bitOffset> 19103 <bitWidth>1</bitWidth> 19104 </field> 19105 <field> 19106 <name>CC1OF</name> 19107 <description>Capture/Compare 1 overcapture 19108 flag</description> 19109 <bitOffset>9</bitOffset> 19110 <bitWidth>1</bitWidth> 19111 </field> 19112 <field> 19113 <name>TIF</name> 19114 <description>Trigger interrupt flag</description> 19115 <bitOffset>6</bitOffset> 19116 <bitWidth>1</bitWidth> 19117 </field> 19118 <field> 19119 <name>CC2IF</name> 19120 <description>Capture/Compare 2 interrupt 19121 flag</description> 19122 <bitOffset>2</bitOffset> 19123 <bitWidth>1</bitWidth> 19124 </field> 19125 <field> 19126 <name>CC1IF</name> 19127 <description>Capture/compare 1 interrupt 19128 flag</description> 19129 <bitOffset>1</bitOffset> 19130 <bitWidth>1</bitWidth> 19131 </field> 19132 <field> 19133 <name>UIF</name> 19134 <description>Update interrupt flag</description> 19135 <bitOffset>0</bitOffset> 19136 <bitWidth>1</bitWidth> 19137 <enumeratedValues><name>UIF</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>No update occurred</description><value>0</value></enumeratedValue><enumeratedValue><name>UpdatePending</name><description>Update interrupt pending.</description><value>1</value></enumeratedValue></enumeratedValues> 19138 </field> 19139 </fields> 19140 </register> 19141 <register> 19142 <name>EGR</name> 19143 <displayName>EGR</displayName> 19144 <description>event generation register</description> 19145 <addressOffset>0x14</addressOffset> 19146 <size>0x20</size> 19147 <access>write-only</access> 19148 <resetValue>0x0000</resetValue> 19149 <fields> 19150 <field> 19151 <name>TG</name> 19152 <description>Trigger generation</description> 19153 <bitOffset>6</bitOffset> 19154 <bitWidth>1</bitWidth> 19155 </field> 19156 <field> 19157 <name>CC2G</name> 19158 <description>Capture/compare 2 19159 generation</description> 19160 <bitOffset>2</bitOffset> 19161 <bitWidth>1</bitWidth> 19162 </field> 19163 <field> 19164 <name>CC1G</name> 19165 <description>Capture/compare 1 19166 generation</description> 19167 <bitOffset>1</bitOffset> 19168 <bitWidth>1</bitWidth> 19169 </field> 19170 <field> 19171 <name>UG</name> 19172 <description>Update generation</description> 19173 <bitOffset>0</bitOffset> 19174 <bitWidth>1</bitWidth> 19175 <enumeratedValues><name>UG</name><usage>read-write</usage><enumeratedValue><name>Update</name><description>Re-initializes the timer counter and generates an update of the registers.</description><value>1</value></enumeratedValue></enumeratedValues> 19176 </field> 19177 </fields> 19178 </register> 19179 <register> 19180 <name>CCMR1_Output</name> 19181 <displayName>CCMR1_Output</displayName> 19182 <description>capture/compare mode register 1 (output 19183 mode)</description> 19184 <addressOffset>0x18</addressOffset> 19185 <size>0x20</size> 19186 <access>read-write</access> 19187 <resetValue>0x00000000</resetValue> 19188 <fields> 19189 <field> 19190 <name>OC2M</name> 19191 <description>Output Compare 2 mode</description> 19192 <bitOffset>12</bitOffset> 19193 <bitWidth>3</bitWidth> 19194 <enumeratedValues derivedFrom="OC1M"/> 19195 </field> 19196 <field> 19197 <name>OC2PE</name> 19198 <description>Output Compare 2 preload 19199 enable</description> 19200 <bitOffset>11</bitOffset> 19201 <bitWidth>1</bitWidth> 19202 </field> 19203 <field> 19204 <name>OC2FE</name> 19205 <description>Output Compare 2 fast 19206 enable</description> 19207 <bitOffset>10</bitOffset> 19208 <bitWidth>1</bitWidth> 19209 </field> 19210 <field> 19211 <name>CC2S</name> 19212 <description>Capture/Compare 2 19213 selection</description> 19214 <bitOffset>8</bitOffset> 19215 <bitWidth>2</bitWidth> 19216 </field> 19217 <field> 19218 <name>OC1M</name> 19219 <description>Output Compare 1 mode</description> 19220 <bitOffset>4</bitOffset> 19221 <bitWidth>3</bitWidth> 19222 <enumeratedValues><name>OC1M</name><usage>read-write</usage><enumeratedValue><name>Frozen</name><description>The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs</description><value>0</value></enumeratedValue><enumeratedValue><name>ActiveOnMatch</name><description>Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register</description><value>1</value></enumeratedValue><enumeratedValue><name>InactiveOnMatch</name><description>Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register</description><value>2</value></enumeratedValue><enumeratedValue><name>Toggle</name><description>OCyREF toggles when TIMx_CNT=TIMx_CCRy</description><value>3</value></enumeratedValue><enumeratedValue><name>ForceInactive</name><description>OCyREF is forced low</description><value>4</value></enumeratedValue><enumeratedValue><name>ForceActive</name><description>OCyREF is forced high</description><value>5</value></enumeratedValue><enumeratedValue><name>PwmMode1</name><description>In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active</description><value>6</value></enumeratedValue><enumeratedValue><name>PwmMode2</name><description>Inversely to PwmMode1</description><value>7</value></enumeratedValue></enumeratedValues> 19223 </field> 19224 <field> 19225 <name>OC1PE</name> 19226 <description>Output Compare 1 preload 19227 enable</description> 19228 <bitOffset>3</bitOffset> 19229 <bitWidth>1</bitWidth> 19230 </field> 19231 <field> 19232 <name>OC1FE</name> 19233 <description>Output Compare 1 fast 19234 enable</description> 19235 <bitOffset>2</bitOffset> 19236 <bitWidth>1</bitWidth> 19237 </field> 19238 <field> 19239 <name>CC1S</name> 19240 <description>Capture/Compare 1 19241 selection</description> 19242 <bitOffset>0</bitOffset> 19243 <bitWidth>2</bitWidth> 19244 </field> 19245 </fields> 19246 </register> 19247 <register> 19248 <name>CCMR1_Input</name> 19249 <displayName>CCMR1_Input</displayName> 19250 <description>capture/compare mode register 1 (input 19251 mode)</description> 19252 <alternateRegister>CCMR1_Output</alternateRegister> 19253 <addressOffset>0x18</addressOffset> 19254 <size>0x20</size> 19255 <access>read-write</access> 19256 <resetValue>0x00000000</resetValue> 19257 <fields> 19258 <field> 19259 <name>IC2F</name> 19260 <description>Input capture 2 filter</description> 19261 <bitOffset>12</bitOffset> 19262 <bitWidth>3</bitWidth> 19263 </field> 19264 <field> 19265 <name>IC2PSC</name> 19266 <description>Input capture 2 prescaler</description> 19267 <bitOffset>10</bitOffset> 19268 <bitWidth>2</bitWidth> 19269 </field> 19270 <field> 19271 <name>CC2S</name> 19272 <description>Capture/Compare 2 19273 selection</description> 19274 <bitOffset>8</bitOffset> 19275 <bitWidth>2</bitWidth> 19276 </field> 19277 <field> 19278 <name>IC1F</name> 19279 <description>Input capture 1 filter</description> 19280 <bitOffset>4</bitOffset> 19281 <bitWidth>3</bitWidth> 19282 </field> 19283 <field> 19284 <name>IC1PSC</name> 19285 <description>Input capture 1 prescaler</description> 19286 <bitOffset>2</bitOffset> 19287 <bitWidth>2</bitWidth> 19288 </field> 19289 <field> 19290 <name>CC1S</name> 19291 <description>Capture/Compare 1 19292 selection</description> 19293 <bitOffset>0</bitOffset> 19294 <bitWidth>2</bitWidth> 19295 </field> 19296 </fields> 19297 </register> 19298 <register> 19299 <name>CCER</name> 19300 <displayName>CCER</displayName> 19301 <description>capture/compare enable 19302 register</description> 19303 <addressOffset>0x20</addressOffset> 19304 <size>0x20</size> 19305 <access>read-write</access> 19306 <resetValue>0x0000</resetValue> 19307 <fields> 19308 <field> 19309 <name>CC2NP</name> 19310 <description>Capture/Compare 2 output 19311 Polarity</description> 19312 <bitOffset>7</bitOffset> 19313 <bitWidth>1</bitWidth> 19314 </field> 19315 <field> 19316 <name>CC2P</name> 19317 <description>Capture/Compare 2 output 19318 Polarity</description> 19319 <bitOffset>5</bitOffset> 19320 <bitWidth>1</bitWidth> 19321 </field> 19322 <field> 19323 <name>CC2E</name> 19324 <description>Capture/Compare 2 output 19325 enable</description> 19326 <bitOffset>4</bitOffset> 19327 <bitWidth>1</bitWidth> 19328 </field> 19329 <field> 19330 <name>CC1NP</name> 19331 <description>Capture/Compare 1 output 19332 Polarity</description> 19333 <bitOffset>3</bitOffset> 19334 <bitWidth>1</bitWidth> 19335 </field> 19336 <field> 19337 <name>CC1P</name> 19338 <description>Capture/Compare 1 output 19339 Polarity</description> 19340 <bitOffset>1</bitOffset> 19341 <bitWidth>1</bitWidth> 19342 </field> 19343 <field> 19344 <name>CC1E</name> 19345 <description>Capture/Compare 1 output 19346 enable</description> 19347 <bitOffset>0</bitOffset> 19348 <bitWidth>1</bitWidth> 19349 </field> 19350 </fields> 19351 </register> 19352 <register> 19353 <name>CNT</name> 19354 <displayName>CNT</displayName> 19355 <description>counter</description> 19356 <addressOffset>0x24</addressOffset> 19357 <size>0x20</size> 19358 <access>read-write</access> 19359 <resetValue>0x00000000</resetValue> 19360 <fields> 19361 <field> 19362 <name>CNT</name> 19363 <description>counter value</description> 19364 <bitOffset>0</bitOffset> 19365 <bitWidth>16</bitWidth> 19366 </field> 19367 </fields> 19368 </register> 19369 <register> 19370 <name>PSC</name> 19371 <displayName>PSC</displayName> 19372 <description>prescaler</description> 19373 <addressOffset>0x28</addressOffset> 19374 <size>0x20</size> 19375 <access>read-write</access> 19376 <resetValue>0x0000</resetValue> 19377 <fields> 19378 <field> 19379 <name>PSC</name> 19380 <description>Prescaler value</description> 19381 <bitOffset>0</bitOffset> 19382 <bitWidth>16</bitWidth> 19383 <writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint> 19384 </field> 19385 </fields> 19386 </register> 19387 <register> 19388 <name>ARR</name> 19389 <displayName>ARR</displayName> 19390 <description>auto-reload register</description> 19391 <addressOffset>0x2C</addressOffset> 19392 <size>0x20</size> 19393 <access>read-write</access> 19394 <resetValue>0x00000000</resetValue> 19395 <fields> 19396 <field> 19397 <name>ARR</name> 19398 <description>Auto-reload value</description> 19399 <bitOffset>0</bitOffset> 19400 <bitWidth>16</bitWidth> 19401 </field> 19402 </fields> 19403 </register> 19404 <register> 19405 <dim>2</dim><dimIncrement>0x4</dimIncrement><dimIndex>1,2</dimIndex><name>CCR%s</name> 19406 <displayName>CCR1</displayName> 19407 <description>capture/compare register</description> 19408 <addressOffset>0x34</addressOffset> 19409 <size>0x20</size> 19410 <access>read-write</access> 19411 <resetValue>0x00000000</resetValue> 19412 <fields> 19413 <field> 19414 <name>CCR</name> 19415 <description>Capture/Compare value</description> 19416 <bitOffset>0</bitOffset> 19417 <bitWidth>16</bitWidth> 19418 </field> 19419 </fields> 19420 </register> 19421 </registers> 19422 </peripheral> 19423 <peripheral derivedFrom="TIM9"> 19424 <name>TIM12</name> 19425 <baseAddress>0x40001800</baseAddress> 19426 <interrupt> 19427 <name>TIM8_BRK_TIM12</name> 19428 <description>TIM8 Break interrupt and TIM12 global 19429 interrupt</description> 19430 <value>43</value> 19431 </interrupt> 19432 </peripheral> 19433 <peripheral> 19434 <name>TIM10</name> 19435 <description>General-purpose-timers</description> 19436 <groupName>TIM</groupName> 19437 <baseAddress>0x40014400</baseAddress> 19438 <addressBlock> 19439 <offset>0x0</offset> 19440 <size>0x400</size> 19441 <usage>registers</usage> 19442 </addressBlock> 19443 <interrupt> 19444 <name>TIM1_UP_TIM10</name> 19445 <description>TIM1 Update interrupt and TIM10 global 19446 interrupt</description> 19447 <value>25</value> 19448 </interrupt> 19449 <registers> 19450 <register> 19451 <name>CR1</name> 19452 <displayName>CR1</displayName> 19453 <description>control register 1</description> 19454 <addressOffset>0x0</addressOffset> 19455 <size>0x20</size> 19456 <access>read-write</access> 19457 <resetValue>0x0000</resetValue> 19458 <fields> 19459 <field> 19460 <name>CKD</name> 19461 <description>Clock division</description> 19462 <bitOffset>8</bitOffset> 19463 <bitWidth>2</bitWidth> 19464 <enumeratedValues><name>CKD</name><usage>read-write</usage><enumeratedValue><name>Div1</name><description>t_DTS = t_CK_INT</description><value>0</value></enumeratedValue><enumeratedValue><name>Div2</name><description>t_DTS = 2 × t_CK_INT</description><value>1</value></enumeratedValue><enumeratedValue><name>Div4</name><description>t_DTS = 4 × t_CK_INT</description><value>2</value></enumeratedValue></enumeratedValues> 19465 </field> 19466 <field> 19467 <name>ARPE</name> 19468 <description>Auto-reload preload enable</description> 19469 <bitOffset>7</bitOffset> 19470 <bitWidth>1</bitWidth> 19471 <enumeratedValues><name>ARPE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>TIMx_APRR register is not buffered</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>TIMx_APRR register is buffered</description><value>1</value></enumeratedValue></enumeratedValues> 19472 </field> 19473 <field> 19474 <name>URS</name> 19475 <description>Update request source</description> 19476 <bitOffset>2</bitOffset> 19477 <bitWidth>1</bitWidth> 19478 <enumeratedValues><name>URS</name><usage>read-write</usage><enumeratedValue><name>AnyEvent</name><description>Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request</description><value>0</value></enumeratedValue><enumeratedValue><name>CounterOnly</name><description>Only counter overflow/underflow generates an update interrupt or DMA request</description><value>1</value></enumeratedValue></enumeratedValues> 19479 </field> 19480 <field> 19481 <name>UDIS</name> 19482 <description>Update disable</description> 19483 <bitOffset>1</bitOffset> 19484 <bitWidth>1</bitWidth> 19485 <enumeratedValues><name>UDIS</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>Update event enabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>Update event disabled</description><value>1</value></enumeratedValue></enumeratedValues> 19486 </field> 19487 <field> 19488 <name>CEN</name> 19489 <description>Counter enable</description> 19490 <bitOffset>0</bitOffset> 19491 <bitWidth>1</bitWidth> 19492 <enumeratedValues><name>CEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Counter disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Counter enabled</description><value>1</value></enumeratedValue></enumeratedValues> 19493 </field> 19494 <field><name>OPM</name><description>One-pulse mode</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth><access>read-write</access><enumeratedValues><name>OPM</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Counter is not stopped at update event</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Counter stops counting at the next update event (clearing the CEN bit)</description><value>1</value></enumeratedValue></enumeratedValues> 19495 </field> 19496 </fields> 19497 </register> 19498 <register> 19499 <name>DIER</name> 19500 <displayName>DIER</displayName> 19501 <description>DMA/Interrupt enable register</description> 19502 <addressOffset>0xC</addressOffset> 19503 <size>0x20</size> 19504 <access>read-write</access> 19505 <resetValue>0x0000</resetValue> 19506 <fields> 19507 <field> 19508 <name>CC1IE</name> 19509 <description>Capture/Compare 1 interrupt 19510 enable</description> 19511 <bitOffset>1</bitOffset> 19512 <bitWidth>1</bitWidth> 19513 </field> 19514 <field> 19515 <name>UIE</name> 19516 <description>Update interrupt enable</description> 19517 <bitOffset>0</bitOffset> 19518 <bitWidth>1</bitWidth> 19519 <enumeratedValues><name>UIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Update interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Update interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 19520 </field> 19521 </fields> 19522 </register> 19523 <register> 19524 <name>SR</name> 19525 <displayName>SR</displayName> 19526 <description>status register</description> 19527 <addressOffset>0x10</addressOffset> 19528 <size>0x20</size> 19529 <access>read-write</access> 19530 <resetValue>0x0000</resetValue> 19531 <fields> 19532 <field> 19533 <name>CC1OF</name> 19534 <description>Capture/Compare 1 overcapture 19535 flag</description> 19536 <bitOffset>9</bitOffset> 19537 <bitWidth>1</bitWidth> 19538 </field> 19539 <field> 19540 <name>CC1IF</name> 19541 <description>Capture/compare 1 interrupt 19542 flag</description> 19543 <bitOffset>1</bitOffset> 19544 <bitWidth>1</bitWidth> 19545 </field> 19546 <field> 19547 <name>UIF</name> 19548 <description>Update interrupt flag</description> 19549 <bitOffset>0</bitOffset> 19550 <bitWidth>1</bitWidth> 19551 <enumeratedValues><name>UIF</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>No update occurred</description><value>0</value></enumeratedValue><enumeratedValue><name>UpdatePending</name><description>Update interrupt pending.</description><value>1</value></enumeratedValue></enumeratedValues> 19552 </field> 19553 </fields> 19554 </register> 19555 <register> 19556 <name>EGR</name> 19557 <displayName>EGR</displayName> 19558 <description>event generation register</description> 19559 <addressOffset>0x14</addressOffset> 19560 <size>0x20</size> 19561 <access>write-only</access> 19562 <resetValue>0x0000</resetValue> 19563 <fields> 19564 <field> 19565 <name>CC1G</name> 19566 <description>Capture/compare 1 19567 generation</description> 19568 <bitOffset>1</bitOffset> 19569 <bitWidth>1</bitWidth> 19570 </field> 19571 <field> 19572 <name>UG</name> 19573 <description>Update generation</description> 19574 <bitOffset>0</bitOffset> 19575 <bitWidth>1</bitWidth> 19576 <enumeratedValues><name>UG</name><usage>read-write</usage><enumeratedValue><name>Update</name><description>Re-initializes the timer counter and generates an update of the registers.</description><value>1</value></enumeratedValue></enumeratedValues> 19577 </field> 19578 </fields> 19579 </register> 19580 <register> 19581 <name>CCMR1_Output</name> 19582 <displayName>CCMR1_Output</displayName> 19583 <description>capture/compare mode register 1 (output 19584 mode)</description> 19585 <addressOffset>0x18</addressOffset> 19586 <size>0x20</size> 19587 <access>read-write</access> 19588 <resetValue>0x00000000</resetValue> 19589 <fields> 19590 <field> 19591 <name>OC1M</name> 19592 <description>Output Compare 1 mode</description> 19593 <bitOffset>4</bitOffset> 19594 <bitWidth>3</bitWidth> 19595 <enumeratedValues><name>OC1M</name><usage>read-write</usage><enumeratedValue><name>Frozen</name><description>The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs</description><value>0</value></enumeratedValue><enumeratedValue><name>ActiveOnMatch</name><description>Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register</description><value>1</value></enumeratedValue><enumeratedValue><name>InactiveOnMatch</name><description>Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register</description><value>2</value></enumeratedValue><enumeratedValue><name>Toggle</name><description>OCyREF toggles when TIMx_CNT=TIMx_CCRy</description><value>3</value></enumeratedValue><enumeratedValue><name>ForceInactive</name><description>OCyREF is forced low</description><value>4</value></enumeratedValue><enumeratedValue><name>ForceActive</name><description>OCyREF is forced high</description><value>5</value></enumeratedValue><enumeratedValue><name>PwmMode1</name><description>In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active</description><value>6</value></enumeratedValue><enumeratedValue><name>PwmMode2</name><description>Inversely to PwmMode1</description><value>7</value></enumeratedValue></enumeratedValues> 19596 </field> 19597 <field> 19598 <name>OC1PE</name> 19599 <description>Output Compare 1 preload 19600 enable</description> 19601 <bitOffset>3</bitOffset> 19602 <bitWidth>1</bitWidth> 19603 </field> 19604 <field> 19605 <name>OC1FE</name> 19606 <description>Output Compare 1 fast 19607 enable</description> 19608 <bitOffset>2</bitOffset> 19609 <bitWidth>1</bitWidth> 19610 </field> 19611 <field> 19612 <name>CC1S</name> 19613 <description>Capture/Compare 1 19614 selection</description> 19615 <bitOffset>0</bitOffset> 19616 <bitWidth>2</bitWidth> 19617 </field> 19618 </fields> 19619 </register> 19620 <register> 19621 <name>CCMR1_Input</name> 19622 <displayName>CCMR1_Input</displayName> 19623 <description>capture/compare mode register 1 (input 19624 mode)</description> 19625 <alternateRegister>CCMR1_Output</alternateRegister> 19626 <addressOffset>0x18</addressOffset> 19627 <size>0x20</size> 19628 <access>read-write</access> 19629 <resetValue>0x00000000</resetValue> 19630 <fields> 19631 <field> 19632 <name>IC1F</name> 19633 <description>Input capture 1 filter</description> 19634 <bitOffset>4</bitOffset> 19635 <bitWidth>4</bitWidth> 19636 </field> 19637 <field> 19638 <name>IC1PSC</name> 19639 <description>Input capture 1 prescaler</description> 19640 <bitOffset>2</bitOffset> 19641 <bitWidth>2</bitWidth> 19642 </field> 19643 <field> 19644 <name>CC1S</name> 19645 <description>Capture/Compare 1 19646 selection</description> 19647 <bitOffset>0</bitOffset> 19648 <bitWidth>2</bitWidth> 19649 </field> 19650 </fields> 19651 </register> 19652 <register> 19653 <name>CCER</name> 19654 <displayName>CCER</displayName> 19655 <description>capture/compare enable 19656 register</description> 19657 <addressOffset>0x20</addressOffset> 19658 <size>0x20</size> 19659 <access>read-write</access> 19660 <resetValue>0x0000</resetValue> 19661 <fields> 19662 <field> 19663 <name>CC1NP</name> 19664 <description>Capture/Compare 1 output 19665 Polarity</description> 19666 <bitOffset>3</bitOffset> 19667 <bitWidth>1</bitWidth> 19668 </field> 19669 <field> 19670 <name>CC1P</name> 19671 <description>Capture/Compare 1 output 19672 Polarity</description> 19673 <bitOffset>1</bitOffset> 19674 <bitWidth>1</bitWidth> 19675 </field> 19676 <field> 19677 <name>CC1E</name> 19678 <description>Capture/Compare 1 output 19679 enable</description> 19680 <bitOffset>0</bitOffset> 19681 <bitWidth>1</bitWidth> 19682 </field> 19683 </fields> 19684 </register> 19685 <register> 19686 <name>CNT</name> 19687 <displayName>CNT</displayName> 19688 <description>counter</description> 19689 <addressOffset>0x24</addressOffset> 19690 <size>0x20</size> 19691 <access>read-write</access> 19692 <resetValue>0x00000000</resetValue> 19693 <fields> 19694 <field> 19695 <name>CNT</name> 19696 <description>counter value</description> 19697 <bitOffset>0</bitOffset> 19698 <bitWidth>16</bitWidth> 19699 </field> 19700 </fields> 19701 </register> 19702 <register> 19703 <name>PSC</name> 19704 <displayName>PSC</displayName> 19705 <description>prescaler</description> 19706 <addressOffset>0x28</addressOffset> 19707 <size>0x20</size> 19708 <access>read-write</access> 19709 <resetValue>0x0000</resetValue> 19710 <fields> 19711 <field> 19712 <name>PSC</name> 19713 <description>Prescaler value</description> 19714 <bitOffset>0</bitOffset> 19715 <bitWidth>16</bitWidth> 19716 <writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint> 19717 </field> 19718 </fields> 19719 </register> 19720 <register> 19721 <name>ARR</name> 19722 <displayName>ARR</displayName> 19723 <description>auto-reload register</description> 19724 <addressOffset>0x2C</addressOffset> 19725 <size>0x20</size> 19726 <access>read-write</access> 19727 <resetValue>0x00000000</resetValue> 19728 <fields> 19729 <field> 19730 <name>ARR</name> 19731 <description>Auto-reload value</description> 19732 <bitOffset>0</bitOffset> 19733 <bitWidth>16</bitWidth> 19734 </field> 19735 </fields> 19736 </register> 19737 <register> 19738 <dim>1</dim><dimIncrement>0x0</dimIncrement><dimIndex>1-1</dimIndex><name>CCR%s</name> 19739 <displayName>CCR1</displayName> 19740 <description>capture/compare register</description> 19741 <addressOffset>0x34</addressOffset> 19742 <size>0x20</size> 19743 <access>read-write</access> 19744 <resetValue>0x00000000</resetValue> 19745 <fields> 19746 <field> 19747 <name>CCR</name> 19748 <description>Capture/Compare value</description> 19749 <bitOffset>0</bitOffset> 19750 <bitWidth>16</bitWidth> 19751 </field> 19752 </fields> 19753 </register> 19754 </registers> 19755 </peripheral> 19756 <peripheral derivedFrom="TIM10"> 19757 <name>TIM13</name> 19758 <baseAddress>0x40001C00</baseAddress> 19759 <interrupt> 19760 <name>TIM8_UP_TIM13</name> 19761 <description>TIM8 Update interrupt and TIM13 global 19762 interrupt</description> 19763 <value>44</value> 19764 </interrupt> 19765 </peripheral> 19766 <peripheral derivedFrom="TIM10"> 19767 <name>TIM14</name> 19768 <baseAddress>0x40002000</baseAddress> 19769 <interrupt> 19770 <name>TIM8_TRG_COM_TIM14</name> 19771 <description>TIM8 Trigger and Commutation interrupts and 19772 TIM14 global interrupt</description> 19773 <value>45</value> 19774 </interrupt> 19775 </peripheral> 19776 <peripheral> 19777 <name>TIM11</name> 19778 <description>General-purpose-timers</description> 19779 <groupName>TIM</groupName> 19780 <baseAddress>0x40014800</baseAddress> 19781 <addressBlock> 19782 <offset>0x0</offset> 19783 <size>0x400</size> 19784 <usage>registers</usage> 19785 </addressBlock> 19786 <interrupt> 19787 <name>TIM1_TRG_COM_TIM11</name> 19788 <description>TIM1 Trigger and Commutation interrupts and 19789 TIM11 global interrupt</description> 19790 <value>26</value> 19791 </interrupt> 19792 <registers> 19793 <register> 19794 <name>CR1</name> 19795 <displayName>CR1</displayName> 19796 <description>control register 1</description> 19797 <addressOffset>0x0</addressOffset> 19798 <size>0x20</size> 19799 <access>read-write</access> 19800 <resetValue>0x0000</resetValue> 19801 <fields> 19802 <field> 19803 <name>CKD</name> 19804 <description>Clock division</description> 19805 <bitOffset>8</bitOffset> 19806 <bitWidth>2</bitWidth> 19807 <enumeratedValues><name>CKD</name><usage>read-write</usage><enumeratedValue><name>Div1</name><description>t_DTS = t_CK_INT</description><value>0</value></enumeratedValue><enumeratedValue><name>Div2</name><description>t_DTS = 2 × t_CK_INT</description><value>1</value></enumeratedValue><enumeratedValue><name>Div4</name><description>t_DTS = 4 × t_CK_INT</description><value>2</value></enumeratedValue></enumeratedValues> 19808 </field> 19809 <field> 19810 <name>ARPE</name> 19811 <description>Auto-reload preload enable</description> 19812 <bitOffset>7</bitOffset> 19813 <bitWidth>1</bitWidth> 19814 <enumeratedValues><name>ARPE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>TIMx_APRR register is not buffered</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>TIMx_APRR register is buffered</description><value>1</value></enumeratedValue></enumeratedValues> 19815 </field> 19816 <field> 19817 <name>URS</name> 19818 <description>Update request source</description> 19819 <bitOffset>2</bitOffset> 19820 <bitWidth>1</bitWidth> 19821 <enumeratedValues><name>URS</name><usage>read-write</usage><enumeratedValue><name>AnyEvent</name><description>Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request</description><value>0</value></enumeratedValue><enumeratedValue><name>CounterOnly</name><description>Only counter overflow/underflow generates an update interrupt or DMA request</description><value>1</value></enumeratedValue></enumeratedValues> 19822 </field> 19823 <field> 19824 <name>UDIS</name> 19825 <description>Update disable</description> 19826 <bitOffset>1</bitOffset> 19827 <bitWidth>1</bitWidth> 19828 <enumeratedValues><name>UDIS</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>Update event enabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>Update event disabled</description><value>1</value></enumeratedValue></enumeratedValues> 19829 </field> 19830 <field> 19831 <name>CEN</name> 19832 <description>Counter enable</description> 19833 <bitOffset>0</bitOffset> 19834 <bitWidth>1</bitWidth> 19835 <enumeratedValues><name>CEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Counter disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Counter enabled</description><value>1</value></enumeratedValue></enumeratedValues> 19836 </field> 19837 <field><name>OPM</name><description>One-pulse mode</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth><access>read-write</access><enumeratedValues><name>OPM</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Counter is not stopped at update event</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Counter stops counting at the next update event (clearing the CEN bit)</description><value>1</value></enumeratedValue></enumeratedValues> 19838 </field> 19839 </fields> 19840 </register> 19841 <register> 19842 <name>DIER</name> 19843 <displayName>DIER</displayName> 19844 <description>DMA/Interrupt enable register</description> 19845 <addressOffset>0xC</addressOffset> 19846 <size>0x20</size> 19847 <access>read-write</access> 19848 <resetValue>0x0000</resetValue> 19849 <fields> 19850 <field> 19851 <name>CC1IE</name> 19852 <description>Capture/Compare 1 interrupt 19853 enable</description> 19854 <bitOffset>1</bitOffset> 19855 <bitWidth>1</bitWidth> 19856 </field> 19857 <field> 19858 <name>UIE</name> 19859 <description>Update interrupt enable</description> 19860 <bitOffset>0</bitOffset> 19861 <bitWidth>1</bitWidth> 19862 <enumeratedValues><name>UIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Update interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Update interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 19863 </field> 19864 </fields> 19865 </register> 19866 <register> 19867 <name>SR</name> 19868 <displayName>SR</displayName> 19869 <description>status register</description> 19870 <addressOffset>0x10</addressOffset> 19871 <size>0x20</size> 19872 <access>read-write</access> 19873 <resetValue>0x0000</resetValue> 19874 <fields> 19875 <field> 19876 <name>CC1OF</name> 19877 <description>Capture/Compare 1 overcapture 19878 flag</description> 19879 <bitOffset>9</bitOffset> 19880 <bitWidth>1</bitWidth> 19881 </field> 19882 <field> 19883 <name>CC1IF</name> 19884 <description>Capture/compare 1 interrupt 19885 flag</description> 19886 <bitOffset>1</bitOffset> 19887 <bitWidth>1</bitWidth> 19888 </field> 19889 <field> 19890 <name>UIF</name> 19891 <description>Update interrupt flag</description> 19892 <bitOffset>0</bitOffset> 19893 <bitWidth>1</bitWidth> 19894 <enumeratedValues><name>UIF</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>No update occurred</description><value>0</value></enumeratedValue><enumeratedValue><name>UpdatePending</name><description>Update interrupt pending.</description><value>1</value></enumeratedValue></enumeratedValues> 19895 </field> 19896 </fields> 19897 </register> 19898 <register> 19899 <name>EGR</name> 19900 <displayName>EGR</displayName> 19901 <description>event generation register</description> 19902 <addressOffset>0x14</addressOffset> 19903 <size>0x20</size> 19904 <access>write-only</access> 19905 <resetValue>0x0000</resetValue> 19906 <fields> 19907 <field> 19908 <name>CC1G</name> 19909 <description>Capture/compare 1 19910 generation</description> 19911 <bitOffset>1</bitOffset> 19912 <bitWidth>1</bitWidth> 19913 </field> 19914 <field> 19915 <name>UG</name> 19916 <description>Update generation</description> 19917 <bitOffset>0</bitOffset> 19918 <bitWidth>1</bitWidth> 19919 <enumeratedValues><name>UG</name><usage>read-write</usage><enumeratedValue><name>Update</name><description>Re-initializes the timer counter and generates an update of the registers.</description><value>1</value></enumeratedValue></enumeratedValues> 19920 </field> 19921 </fields> 19922 </register> 19923 <register> 19924 <name>CCMR1_Output</name> 19925 <displayName>CCMR1_Output</displayName> 19926 <description>capture/compare mode register 1 (output 19927 mode)</description> 19928 <addressOffset>0x18</addressOffset> 19929 <size>0x20</size> 19930 <access>read-write</access> 19931 <resetValue>0x00000000</resetValue> 19932 <fields> 19933 <field> 19934 <name>OC1M</name> 19935 <description>Output Compare 1 mode</description> 19936 <bitOffset>4</bitOffset> 19937 <bitWidth>3</bitWidth> 19938 <enumeratedValues><name>OC1M</name><usage>read-write</usage><enumeratedValue><name>Frozen</name><description>The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs</description><value>0</value></enumeratedValue><enumeratedValue><name>ActiveOnMatch</name><description>Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register</description><value>1</value></enumeratedValue><enumeratedValue><name>InactiveOnMatch</name><description>Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register</description><value>2</value></enumeratedValue><enumeratedValue><name>Toggle</name><description>OCyREF toggles when TIMx_CNT=TIMx_CCRy</description><value>3</value></enumeratedValue><enumeratedValue><name>ForceInactive</name><description>OCyREF is forced low</description><value>4</value></enumeratedValue><enumeratedValue><name>ForceActive</name><description>OCyREF is forced high</description><value>5</value></enumeratedValue><enumeratedValue><name>PwmMode1</name><description>In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active</description><value>6</value></enumeratedValue><enumeratedValue><name>PwmMode2</name><description>Inversely to PwmMode1</description><value>7</value></enumeratedValue></enumeratedValues> 19939 </field> 19940 <field> 19941 <name>OC1PE</name> 19942 <description>Output Compare 1 preload 19943 enable</description> 19944 <bitOffset>3</bitOffset> 19945 <bitWidth>1</bitWidth> 19946 </field> 19947 <field> 19948 <name>OC1FE</name> 19949 <description>Output Compare 1 fast 19950 enable</description> 19951 <bitOffset>2</bitOffset> 19952 <bitWidth>1</bitWidth> 19953 </field> 19954 <field> 19955 <name>CC1S</name> 19956 <description>Capture/Compare 1 19957 selection</description> 19958 <bitOffset>0</bitOffset> 19959 <bitWidth>2</bitWidth> 19960 </field> 19961 </fields> 19962 </register> 19963 <register> 19964 <name>CCMR1_Input</name> 19965 <displayName>CCMR1_Input</displayName> 19966 <description>capture/compare mode register 1 (input 19967 mode)</description> 19968 <alternateRegister>CCMR1_Output</alternateRegister> 19969 <addressOffset>0x18</addressOffset> 19970 <size>0x20</size> 19971 <access>read-write</access> 19972 <resetValue>0x00000000</resetValue> 19973 <fields> 19974 <field> 19975 <name>IC1F</name> 19976 <description>Input capture 1 filter</description> 19977 <bitOffset>4</bitOffset> 19978 <bitWidth>4</bitWidth> 19979 </field> 19980 <field> 19981 <name>IC1PSC</name> 19982 <description>Input capture 1 prescaler</description> 19983 <bitOffset>2</bitOffset> 19984 <bitWidth>2</bitWidth> 19985 </field> 19986 <field> 19987 <name>CC1S</name> 19988 <description>Capture/Compare 1 19989 selection</description> 19990 <bitOffset>0</bitOffset> 19991 <bitWidth>2</bitWidth> 19992 </field> 19993 </fields> 19994 </register> 19995 <register> 19996 <name>CCER</name> 19997 <displayName>CCER</displayName> 19998 <description>capture/compare enable 19999 register</description> 20000 <addressOffset>0x20</addressOffset> 20001 <size>0x20</size> 20002 <access>read-write</access> 20003 <resetValue>0x0000</resetValue> 20004 <fields> 20005 <field> 20006 <name>CC1NP</name> 20007 <description>Capture/Compare 1 output 20008 Polarity</description> 20009 <bitOffset>3</bitOffset> 20010 <bitWidth>1</bitWidth> 20011 </field> 20012 <field> 20013 <name>CC1P</name> 20014 <description>Capture/Compare 1 output 20015 Polarity</description> 20016 <bitOffset>1</bitOffset> 20017 <bitWidth>1</bitWidth> 20018 </field> 20019 <field> 20020 <name>CC1E</name> 20021 <description>Capture/Compare 1 output 20022 enable</description> 20023 <bitOffset>0</bitOffset> 20024 <bitWidth>1</bitWidth> 20025 </field> 20026 </fields> 20027 </register> 20028 <register> 20029 <name>CNT</name> 20030 <displayName>CNT</displayName> 20031 <description>counter</description> 20032 <addressOffset>0x24</addressOffset> 20033 <size>0x20</size> 20034 <access>read-write</access> 20035 <resetValue>0x00000000</resetValue> 20036 <fields> 20037 <field> 20038 <name>CNT</name> 20039 <description>counter value</description> 20040 <bitOffset>0</bitOffset> 20041 <bitWidth>16</bitWidth> 20042 </field> 20043 </fields> 20044 </register> 20045 <register> 20046 <name>PSC</name> 20047 <displayName>PSC</displayName> 20048 <description>prescaler</description> 20049 <addressOffset>0x28</addressOffset> 20050 <size>0x20</size> 20051 <access>read-write</access> 20052 <resetValue>0x0000</resetValue> 20053 <fields> 20054 <field> 20055 <name>PSC</name> 20056 <description>Prescaler value</description> 20057 <bitOffset>0</bitOffset> 20058 <bitWidth>16</bitWidth> 20059 <writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint> 20060 </field> 20061 </fields> 20062 </register> 20063 <register> 20064 <name>ARR</name> 20065 <displayName>ARR</displayName> 20066 <description>auto-reload register</description> 20067 <addressOffset>0x2C</addressOffset> 20068 <size>0x20</size> 20069 <access>read-write</access> 20070 <resetValue>0x00000000</resetValue> 20071 <fields> 20072 <field> 20073 <name>ARR</name> 20074 <description>Auto-reload value</description> 20075 <bitOffset>0</bitOffset> 20076 <bitWidth>16</bitWidth> 20077 </field> 20078 </fields> 20079 </register> 20080 <register> 20081 <dim>1</dim><dimIncrement>0x0</dimIncrement><dimIndex>1-1</dimIndex><name>CCR%s</name> 20082 <displayName>CCR1</displayName> 20083 <description>capture/compare register</description> 20084 <addressOffset>0x34</addressOffset> 20085 <size>0x20</size> 20086 <access>read-write</access> 20087 <resetValue>0x00000000</resetValue> 20088 <fields> 20089 <field> 20090 <name>CCR</name> 20091 <description>Capture/Compare value</description> 20092 <bitOffset>0</bitOffset> 20093 <bitWidth>16</bitWidth> 20094 </field> 20095 </fields> 20096 </register> 20097 <register> 20098 <name>OR</name> 20099 <displayName>OR</displayName> 20100 <description>option register</description> 20101 <addressOffset>0x50</addressOffset> 20102 <size>0x20</size> 20103 <access>read-write</access> 20104 <resetValue>0x00000000</resetValue> 20105 <fields> 20106 <field> 20107 <name>RMP</name> 20108 <description>Input 1 remapping 20109 capability</description> 20110 <bitOffset>0</bitOffset> 20111 <bitWidth>2</bitWidth> 20112 </field> 20113 </fields> 20114 </register> 20115 </registers> 20116 </peripheral> 20117 <peripheral> 20118 <name>TIM6</name> 20119 <description>Basic timers</description> 20120 <groupName>TIM</groupName> 20121 <baseAddress>0x40001000</baseAddress> 20122 <addressBlock> 20123 <offset>0x0</offset> 20124 <size>0x400</size> 20125 <usage>registers</usage> 20126 </addressBlock> 20127 <interrupt> 20128 <name>TIM6_DAC</name> 20129 <description>TIM6 global interrupt, DAC1 and DAC2 underrun 20130 error interrupt</description> 20131 <value>54</value> 20132 </interrupt> 20133 <registers> 20134 <register> 20135 <name>CR1</name> 20136 <displayName>CR1</displayName> 20137 <description>control register 1</description> 20138 <addressOffset>0x0</addressOffset> 20139 <size>0x20</size> 20140 <access>read-write</access> 20141 <resetValue>0x0000</resetValue> 20142 <fields> 20143 <field> 20144 <name>ARPE</name> 20145 <description>Auto-reload preload enable</description> 20146 <bitOffset>7</bitOffset> 20147 <bitWidth>1</bitWidth> 20148 <enumeratedValues><name>ARPE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>TIMx_APRR register is not buffered</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>TIMx_APRR register is buffered</description><value>1</value></enumeratedValue></enumeratedValues> 20149 </field> 20150 <field> 20151 <name>OPM</name> 20152 <description>One-pulse mode</description> 20153 <bitOffset>3</bitOffset> 20154 <bitWidth>1</bitWidth> 20155 <enumeratedValues><name>OPM</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Counter is not stopped at update event</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Counter stops counting at the next update event (clearing the CEN bit)</description><value>1</value></enumeratedValue></enumeratedValues> 20156 </field> 20157 <field> 20158 <name>URS</name> 20159 <description>Update request source</description> 20160 <bitOffset>2</bitOffset> 20161 <bitWidth>1</bitWidth> 20162 <enumeratedValues><name>URS</name><usage>read-write</usage><enumeratedValue><name>AnyEvent</name><description>Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request</description><value>0</value></enumeratedValue><enumeratedValue><name>CounterOnly</name><description>Only counter overflow/underflow generates an update interrupt or DMA request</description><value>1</value></enumeratedValue></enumeratedValues> 20163 </field> 20164 <field> 20165 <name>UDIS</name> 20166 <description>Update disable</description> 20167 <bitOffset>1</bitOffset> 20168 <bitWidth>1</bitWidth> 20169 <enumeratedValues><name>UDIS</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>Update event enabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>Update event disabled</description><value>1</value></enumeratedValue></enumeratedValues> 20170 </field> 20171 <field> 20172 <name>CEN</name> 20173 <description>Counter enable</description> 20174 <bitOffset>0</bitOffset> 20175 <bitWidth>1</bitWidth> 20176 <enumeratedValues><name>CEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Counter disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Counter enabled</description><value>1</value></enumeratedValue></enumeratedValues> 20177 </field> 20178 </fields> 20179 </register> 20180 <register> 20181 <name>CR2</name> 20182 <displayName>CR2</displayName> 20183 <description>control register 2</description> 20184 <addressOffset>0x4</addressOffset> 20185 <size>0x20</size> 20186 <access>read-write</access> 20187 <resetValue>0x0000</resetValue> 20188 <fields> 20189 <field> 20190 <name>MMS</name> 20191 <description>Master mode selection</description> 20192 <bitOffset>4</bitOffset> 20193 <bitWidth>3</bitWidth> 20194 <enumeratedValues><name>MMS</name><usage>read-write</usage><enumeratedValue><name>Reset</name><description>Use UG bit from TIMx_EGR register</description><value>0</value></enumeratedValue><enumeratedValue><name>Enable</name><description>Use CNT bit from TIMx_CEN register</description><value>1</value></enumeratedValue><enumeratedValue><name>Update</name><description>Use the update event</description><value>2</value></enumeratedValue></enumeratedValues> 20195 </field> 20196 </fields> 20197 </register> 20198 <register> 20199 <name>DIER</name> 20200 <displayName>DIER</displayName> 20201 <description>DMA/Interrupt enable register</description> 20202 <addressOffset>0xC</addressOffset> 20203 <size>0x20</size> 20204 <access>read-write</access> 20205 <resetValue>0x0000</resetValue> 20206 <fields> 20207 <field> 20208 <name>UDE</name> 20209 <description>Update DMA request enable</description> 20210 <bitOffset>8</bitOffset> 20211 <bitWidth>1</bitWidth> 20212 <enumeratedValues><name>UDE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Update DMA request disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Update DMA request enabled</description><value>1</value></enumeratedValue></enumeratedValues> 20213 </field> 20214 <field> 20215 <name>UIE</name> 20216 <description>Update interrupt enable</description> 20217 <bitOffset>0</bitOffset> 20218 <bitWidth>1</bitWidth> 20219 <enumeratedValues><name>UIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Update interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Update interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 20220 </field> 20221 </fields> 20222 </register> 20223 <register> 20224 <name>SR</name> 20225 <displayName>SR</displayName> 20226 <description>status register</description> 20227 <addressOffset>0x10</addressOffset> 20228 <size>0x20</size> 20229 <access>read-write</access> 20230 <resetValue>0x0000</resetValue> 20231 <fields> 20232 <field> 20233 <name>UIF</name> 20234 <description>Update interrupt flag</description> 20235 <bitOffset>0</bitOffset> 20236 <bitWidth>1</bitWidth> 20237 <enumeratedValues><name>UIF</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>No update occurred</description><value>0</value></enumeratedValue><enumeratedValue><name>UpdatePending</name><description>Update interrupt pending.</description><value>1</value></enumeratedValue></enumeratedValues> 20238 </field> 20239 </fields> 20240 </register> 20241 <register> 20242 <name>EGR</name> 20243 <displayName>EGR</displayName> 20244 <description>event generation register</description> 20245 <addressOffset>0x14</addressOffset> 20246 <size>0x20</size> 20247 <access>write-only</access> 20248 <resetValue>0x0000</resetValue> 20249 <fields> 20250 <field> 20251 <name>UG</name> 20252 <description>Update generation</description> 20253 <bitOffset>0</bitOffset> 20254 <bitWidth>1</bitWidth> 20255 <enumeratedValues><name>UG</name><usage>read-write</usage><enumeratedValue><name>Update</name><description>Re-initializes the timer counter and generates an update of the registers.</description><value>1</value></enumeratedValue></enumeratedValues> 20256 </field> 20257 </fields> 20258 </register> 20259 <register> 20260 <name>CNT</name> 20261 <displayName>CNT</displayName> 20262 <description>counter</description> 20263 <addressOffset>0x24</addressOffset> 20264 <size>0x20</size> 20265 <access>read-write</access> 20266 <resetValue>0x00000000</resetValue> 20267 <fields> 20268 <field> 20269 <name>CNT</name> 20270 <description>Low counter value</description> 20271 <bitOffset>0</bitOffset> 20272 <bitWidth>16</bitWidth> 20273 <writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint> 20274 </field> 20275 </fields> 20276 </register> 20277 <register> 20278 <name>PSC</name> 20279 <displayName>PSC</displayName> 20280 <description>prescaler</description> 20281 <addressOffset>0x28</addressOffset> 20282 <size>0x20</size> 20283 <access>read-write</access> 20284 <resetValue>0x0000</resetValue> 20285 <fields> 20286 <field> 20287 <name>PSC</name> 20288 <description>Prescaler value</description> 20289 <bitOffset>0</bitOffset> 20290 <bitWidth>16</bitWidth> 20291 <writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint> 20292 </field> 20293 </fields> 20294 </register> 20295 <register> 20296 <name>ARR</name> 20297 <displayName>ARR</displayName> 20298 <description>auto-reload register</description> 20299 <addressOffset>0x2C</addressOffset> 20300 <size>0x20</size> 20301 <access>read-write</access> 20302 <resetValue>0x00000000</resetValue> 20303 <fields> 20304 <field> 20305 <name>ARR</name> 20306 <description>Low Auto-reload value</description> 20307 <bitOffset>0</bitOffset> 20308 <bitWidth>16</bitWidth> 20309 <writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint> 20310 </field> 20311 </fields> 20312 </register> 20313 </registers> 20314 </peripheral> 20315 <peripheral derivedFrom="TIM6"> 20316 <name>TIM7</name> 20317 <baseAddress>0x40001400</baseAddress> 20318 <interrupt> 20319 <name>TIM7</name> 20320 <description>TIM7 global interrupt</description> 20321 <value>55</value> 20322 </interrupt> 20323 </peripheral> 20324 <peripheral> 20325 <name>Ethernet_MAC</name> 20326 <description>Ethernet: media access control 20327 (MAC)</description> 20328 <groupName>Ethernet</groupName> 20329 <baseAddress>0x40028000</baseAddress> 20330 <addressBlock> 20331 <offset>0x0</offset> 20332 <size>0x61</size> 20333 <usage>registers</usage> 20334 </addressBlock> 20335 <interrupt> 20336 <name>ETH</name> 20337 <description>Ethernet global interrupt</description> 20338 <value>61</value> 20339 </interrupt> 20340 <interrupt> 20341 <name>ETH_WKUP</name> 20342 <description>Ethernet Wakeup through EXTI line 20343 interrupt</description> 20344 <value>62</value> 20345 </interrupt> 20346 <registers> 20347 <register> 20348 <name>MACCR</name> 20349 <displayName>MACCR</displayName> 20350 <description>Ethernet MAC configuration 20351 register</description> 20352 <addressOffset>0x0</addressOffset> 20353 <size>0x20</size> 20354 <access>read-write</access> 20355 <resetValue>0x0008000</resetValue> 20356 <fields> 20357 <field> 20358 <name>RE</name> 20359 <description>Receiver enable</description> 20360 <bitOffset>2</bitOffset> 20361 <bitWidth>1</bitWidth> 20362 <enumeratedValues><name>RE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>MAC receive state machine is disabled after the completion of the reception of the current frame</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>MAC receive state machine is enabled</description><value>1</value></enumeratedValue></enumeratedValues> 20363 </field> 20364 <field> 20365 <name>TE</name> 20366 <description>Transmitter enable</description> 20367 <bitOffset>3</bitOffset> 20368 <bitWidth>1</bitWidth> 20369 <enumeratedValues><name>TE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>MAC transmit state machine is disabled after completion of the transmission of the current frame</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>MAC transmit state machine is enabled</description><value>1</value></enumeratedValue></enumeratedValues> 20370 </field> 20371 <field> 20372 <name>DC</name> 20373 <description>Deferral check</description> 20374 <bitOffset>4</bitOffset> 20375 <bitWidth>1</bitWidth> 20376 <enumeratedValues><name>DC</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>MAC defers until CRS signal goes inactive</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Deferral check function enabled</description><value>1</value></enumeratedValue></enumeratedValues> 20377 </field> 20378 <field> 20379 <name>BL</name> 20380 <description>Back-off limit</description> 20381 <bitOffset>5</bitOffset> 20382 <bitWidth>2</bitWidth> 20383 <enumeratedValues><name>BL</name><usage>read-write</usage><enumeratedValue><name>BL10</name><description>For retransmission n, wait up to 2^min(n, 10) time slots</description><value>0</value></enumeratedValue><enumeratedValue><name>BL8</name><description>For retransmission n, wait up to 2^min(n, 8) time slots</description><value>1</value></enumeratedValue><enumeratedValue><name>BL4</name><description>For retransmission n, wait up to 2^min(n, 4) time slots</description><value>2</value></enumeratedValue><enumeratedValue><name>BL1</name><description>For retransmission n, wait up to 2^min(n, 1) time slots</description><value>3</value></enumeratedValue></enumeratedValues> 20384 </field> 20385 <field> 20386 <name>APCS</name> 20387 <description>Automatic pad/CRC stripping</description> 20388 <bitOffset>7</bitOffset> 20389 <bitWidth>1</bitWidth> 20390 <enumeratedValues><name>APCS</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>MAC passes all incoming frames unmodified</description><value>0</value></enumeratedValue><enumeratedValue><name>Strip</name><description>MAC strips the Pad/FCS field on incoming frames only for lengths less than or equal to 1500 bytes</description><value>1</value></enumeratedValue></enumeratedValues> 20391 </field> 20392 <field> 20393 <name>RD</name> 20394 <description>Retry disable</description> 20395 <bitOffset>9</bitOffset> 20396 <bitWidth>1</bitWidth> 20397 <enumeratedValues><name>RD</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>MAC attempts retries based on the settings of BL</description><value>0</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>MAC attempts only 1 transmission</description><value>1</value></enumeratedValue></enumeratedValues> 20398 </field> 20399 <field> 20400 <name>IPCO</name> 20401 <description>IPv4 checksum offload</description> 20402 <bitOffset>10</bitOffset> 20403 <bitWidth>1</bitWidth> 20404 <enumeratedValues><name>IPCO</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>IPv4 checksum offload disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Offload</name><description>IPv4 checksums are checked in received frames</description><value>1</value></enumeratedValue></enumeratedValues> 20405 </field> 20406 <field> 20407 <name>DM</name> 20408 <description>Duplex mode</description> 20409 <bitOffset>11</bitOffset> 20410 <bitWidth>1</bitWidth> 20411 <enumeratedValues><name>DM</name><usage>read-write</usage><enumeratedValue><name>HalfDuplex</name><description>MAC operates in half-duplex mode</description><value>0</value></enumeratedValue><enumeratedValue><name>FullDuplex</name><description>MAC operates in full-duplex mode</description><value>1</value></enumeratedValue></enumeratedValues> 20412 </field> 20413 <field> 20414 <name>LM</name> 20415 <description>Loopback mode</description> 20416 <bitOffset>12</bitOffset> 20417 <bitWidth>1</bitWidth> 20418 <enumeratedValues><name>LM</name><usage>read-write</usage><enumeratedValue><name>Normal</name><description>Normal mode</description><value>0</value></enumeratedValue><enumeratedValue><name>Loopback</name><description>MAC operates in loopback mode at the MII</description><value>1</value></enumeratedValue></enumeratedValues> 20419 </field> 20420 <field> 20421 <name>ROD</name> 20422 <description>Receive own disable</description> 20423 <bitOffset>13</bitOffset> 20424 <bitWidth>1</bitWidth> 20425 <enumeratedValues><name>ROD</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>MAC receives all packets from PHY while transmitting</description><value>0</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>MAC disables reception of frames in half-duplex mode</description><value>1</value></enumeratedValue></enumeratedValues> 20426 </field> 20427 <field> 20428 <name>FES</name> 20429 <description>Fast Ethernet speed</description> 20430 <bitOffset>14</bitOffset> 20431 <bitWidth>1</bitWidth> 20432 <enumeratedValues><name>FES</name><usage>read-write</usage><enumeratedValue><name>FES10</name><description>10 Mbit/s</description><value>0</value></enumeratedValue><enumeratedValue><name>FES100</name><description>100 Mbit/s</description><value>1</value></enumeratedValue></enumeratedValues> 20433 </field> 20434 <field> 20435 <name>CSD</name> 20436 <description>Carrier sense disable</description> 20437 <bitOffset>16</bitOffset> 20438 <bitWidth>1</bitWidth> 20439 <enumeratedValues><name>CSD</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>Errors generated due to loss of carrier</description><value>0</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>No error generated due to loss of carrier</description><value>1</value></enumeratedValue></enumeratedValues> 20440 </field> 20441 <field> 20442 <name>IFG</name> 20443 <description>Interframe gap</description> 20444 <bitOffset>17</bitOffset> 20445 <bitWidth>3</bitWidth> 20446 <enumeratedValues><name>IFG</name><usage>read-write</usage><enumeratedValue><name>IFG96</name><description>96 bit times</description><value>0</value></enumeratedValue><enumeratedValue><name>IFG88</name><description>88 bit times</description><value>1</value></enumeratedValue><enumeratedValue><name>IFG80</name><description>80 bit times</description><value>2</value></enumeratedValue><enumeratedValue><name>IFG72</name><description>72 bit times</description><value>3</value></enumeratedValue><enumeratedValue><name>IFG64</name><description>64 bit times</description><value>4</value></enumeratedValue><enumeratedValue><name>IFG56</name><description>56 bit times</description><value>5</value></enumeratedValue><enumeratedValue><name>IFG48</name><description>48 bit times</description><value>6</value></enumeratedValue><enumeratedValue><name>IFG40</name><description>40 bit times</description><value>7</value></enumeratedValue></enumeratedValues> 20447 </field> 20448 <field> 20449 <name>JD</name> 20450 <description>Jabber disable</description> 20451 <bitOffset>22</bitOffset> 20452 <bitWidth>1</bitWidth> 20453 <enumeratedValues><name>JD</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>Jabber enabled, transmit frames up to 2048 bytes</description><value>0</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>Jabber disabled, transmit frames up to 16384 bytes</description><value>1</value></enumeratedValue></enumeratedValues> 20454 </field> 20455 <field> 20456 <name>WD</name> 20457 <description>Watchdog disable</description> 20458 <bitOffset>23</bitOffset> 20459 <bitWidth>1</bitWidth> 20460 <enumeratedValues><name>WD</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>Watchdog enabled, receive frames limited to 2048 bytes</description><value>0</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>Watchdog disabled, receive frames may be up to to 16384 bytes</description><value>1</value></enumeratedValue></enumeratedValues> 20461 </field> 20462 <field> 20463 <name>CSTF</name> 20464 <description>CRC stripping for type frames</description> 20465 <bitOffset>25</bitOffset> 20466 <bitWidth>1</bitWidth> 20467 <enumeratedValues><name>CSTF</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>CRC not stripped</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>CRC stripped</description><value>1</value></enumeratedValue></enumeratedValues> 20468 </field> 20469 </fields> 20470 </register> 20471 <register> 20472 <name>MACFFR</name> 20473 <displayName>MACFFR</displayName> 20474 <description>Ethernet MAC frame filter 20475 register</description> 20476 <addressOffset>0x4</addressOffset> 20477 <size>0x20</size> 20478 <access>read-write</access> 20479 <resetValue>0x00000000</resetValue> 20480 <fields> 20481 <field> 20482 <name>PM</name> 20483 <description>Promiscuous mode</description> 20484 <bitOffset>0</bitOffset> 20485 <bitWidth>1</bitWidth> 20486 <enumeratedValues><name>PM</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Normal address filtering</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Address filters pass all incoming frames regardless of their destination or source address</description><value>1</value></enumeratedValue></enumeratedValues> 20487 </field> 20488 <field> 20489 <name>HU</name> 20490 <description>Hash unicast</description> 20491 <bitOffset>1</bitOffset> 20492 <bitWidth>1</bitWidth> 20493 <enumeratedValues><name>HU</name><usage>read-write</usage><enumeratedValue><name>Perfect</name><description>MAC performs a perfect destination address filtering for unicast frames</description><value>0</value></enumeratedValue><enumeratedValue><name>Hash</name><description>MAC performs destination address filtering of received unicast frames according to the hash table</description><value>1</value></enumeratedValue></enumeratedValues> 20494 </field> 20495 <field> 20496 <name>HM</name> 20497 <description>Hash multicast</description> 20498 <bitOffset>2</bitOffset> 20499 <bitWidth>1</bitWidth> 20500 <enumeratedValues><name>HM</name><usage>read-write</usage><enumeratedValue><name>Perfect</name><description>MAC performs a perfect destination address filtering for multicast frames</description><value>0</value></enumeratedValue><enumeratedValue><name>Hash</name><description>MAC performs destination address filtering of received multicast frames according to the hash table</description><value>1</value></enumeratedValue></enumeratedValues> 20501 </field> 20502 <field> 20503 <name>DAIF</name> 20504 <description>Destination address unique filtering</description> 20505 <bitOffset>3</bitOffset> 20506 <bitWidth>1</bitWidth> 20507 <enumeratedValues><name>DAIF</name><usage>read-write</usage><enumeratedValue><name>Normal</name><description>Normal filtering of frames</description><value>0</value></enumeratedValue><enumeratedValue><name>Invert</name><description>Address check block operates in inverse filtering mode for the DA address comparison</description><value>1</value></enumeratedValue></enumeratedValues> 20508 </field> 20509 <field> 20510 <name>PAM</name> 20511 <description>Pass all multicast</description> 20512 <bitOffset>4</bitOffset> 20513 <bitWidth>1</bitWidth> 20514 <enumeratedValues><name>PAM</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Filtering of multicast frames depends on HM</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>All received frames with a multicast destination address are passed</description><value>1</value></enumeratedValue></enumeratedValues> 20515 </field> 20516 <field> 20517 <name>BFD</name> 20518 <description>Broadcast frames disable</description> 20519 <bitOffset>5</bitOffset> 20520 <bitWidth>1</bitWidth> 20521 <enumeratedValues><name>BFD</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>Address filters pass all received broadcast frames</description><value>0</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>Address filters filter all incoming broadcast frames</description><value>1</value></enumeratedValue></enumeratedValues> 20522 </field> 20523 <field> 20524 <name>PCF</name> 20525 <description>Pass control frames</description> 20526 <bitOffset>6</bitOffset> 20527 <bitWidth>2</bitWidth> 20528 <enumeratedValues><name>PCF</name><usage>read-write</usage><enumeratedValue><name>PreventAll</name><description>MAC prevents all control frames from reaching the application</description><value>0</value></enumeratedValue><enumeratedValue><name>ForwardAllExceptPause</name><description>MAC forwards all control frames to application except Pause</description><value>1</value></enumeratedValue><enumeratedValue><name>ForwardAll</name><description>MAC forwards all control frames to application even if they fail the address filter</description><value>2</value></enumeratedValue><enumeratedValue><name>ForwardAllFiltered</name><description>MAC forwards control frames that pass the address filter</description><value>3</value></enumeratedValue></enumeratedValues> 20529 </field> 20530 <field> 20531 <name>SAIF</name> 20532 <description>Source address inverse filtering</description> 20533 <bitOffset>7</bitOffset> 20534 <bitWidth>1</bitWidth> 20535 <enumeratedValues><name>SAIF</name><usage>read-write</usage><enumeratedValue><name>Normal</name><description>Source address filter operates normally</description><value>0</value></enumeratedValue><enumeratedValue><name>Invert</name><description>Source address filter operation inverted</description><value>1</value></enumeratedValue></enumeratedValues> 20536 </field> 20537 <field> 20538 <name>SAF</name> 20539 <description>Source address filter</description> 20540 <bitOffset>8</bitOffset> 20541 <bitWidth>1</bitWidth> 20542 <enumeratedValues><name>SAF</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Source address ignored</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>MAC drops frames that fail the source address filter</description><value>1</value></enumeratedValue></enumeratedValues> 20543 </field> 20544 <field> 20545 <name>HPF</name> 20546 <description>Hash or perfect filter</description> 20547 <bitOffset>9</bitOffset> 20548 <bitWidth>1</bitWidth> 20549 <enumeratedValues><name>HPF</name><usage>read-write</usage><enumeratedValue><name>HashOnly</name><description>If HM or HU is set, only frames that match the Hash filter are passed</description><value>0</value></enumeratedValue><enumeratedValue><name>HashOrPerfect</name><description>If HM or HU is set, frames that match either the perfect filter or the hash filter are passed</description><value>1</value></enumeratedValue></enumeratedValues> 20550 </field> 20551 <field> 20552 <name>RA</name> 20553 <description>Receive all</description> 20554 <bitOffset>31</bitOffset> 20555 <bitWidth>1</bitWidth> 20556 <enumeratedValues><name>RA</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>MAC receiver passes on to the application only those frames that have passed the SA/DA address file</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>MAC receiver passes oll received frames on to the application</description><value>1</value></enumeratedValue></enumeratedValues> 20557 </field> 20558 </fields> 20559 </register> 20560 <register> 20561 <name>MACHTHR</name> 20562 <displayName>MACHTHR</displayName> 20563 <description>Ethernet MAC hash table high 20564 register</description> 20565 <addressOffset>0x8</addressOffset> 20566 <size>0x20</size> 20567 <access>read-write</access> 20568 <resetValue>0x00000000</resetValue> 20569 <fields> 20570 <field> 20571 <name>HTH</name> 20572 <description>Upper 32 bits of hash table</description> 20573 <bitOffset>0</bitOffset> 20574 <bitWidth>32</bitWidth> 20575 <writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint> 20576 </field> 20577 </fields> 20578 </register> 20579 <register> 20580 <name>MACHTLR</name> 20581 <displayName>MACHTLR</displayName> 20582 <description>Ethernet MAC hash table low 20583 register</description> 20584 <addressOffset>0xC</addressOffset> 20585 <size>0x20</size> 20586 <access>read-write</access> 20587 <resetValue>0x00000000</resetValue> 20588 <fields> 20589 <field> 20590 <name>HTL</name> 20591 <description>Lower 32 bits of hash table</description> 20592 <bitOffset>0</bitOffset> 20593 <bitWidth>32</bitWidth> 20594 <writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint> 20595 </field> 20596 </fields> 20597 </register> 20598 <register> 20599 <name>MACMIIAR</name> 20600 <displayName>MACMIIAR</displayName> 20601 <description>Ethernet MAC MII address 20602 register</description> 20603 <addressOffset>0x10</addressOffset> 20604 <size>0x20</size> 20605 <access>read-write</access> 20606 <resetValue>0x00000000</resetValue> 20607 <fields> 20608 <field> 20609 <name>MB</name> 20610 <description>MII busy</description> 20611 <bitOffset>0</bitOffset> 20612 <bitWidth>1</bitWidth> 20613 <enumeratedValues><name>MB</name><usage>read-write</usage><enumeratedValue><name>Busy</name><description>This bit is set to 1 by the application to indicate that a read or write access is in progress</description><value>1</value></enumeratedValue></enumeratedValues> 20614 </field> 20615 <field> 20616 <name>MW</name> 20617 <description>MII write</description> 20618 <bitOffset>1</bitOffset> 20619 <bitWidth>1</bitWidth> 20620 <enumeratedValues><name>MW</name><usage>read-write</usage><enumeratedValue><name>Read</name><description>Read operation</description><value>0</value></enumeratedValue><enumeratedValue><name>Write</name><description>Write operation</description><value>1</value></enumeratedValue></enumeratedValues> 20621 </field> 20622 <field> 20623 <name>CR</name> 20624 <description>Clock range</description> 20625 <bitOffset>2</bitOffset> 20626 <bitWidth>3</bitWidth> 20627 <enumeratedValues><name>CR</name><usage>read-write</usage><enumeratedValue><name>CR_60_100</name><description>60-100MHz HCLK/42</description><value>0</value></enumeratedValue><enumeratedValue><name>CR_100_150</name><description>100-150 MHz HCLK/62</description><value>1</value></enumeratedValue><enumeratedValue><name>CR_20_35</name><description>20-35MHz HCLK/16</description><value>2</value></enumeratedValue><enumeratedValue><name>CR_35_60</name><description>35-60MHz HCLK/16</description><value>3</value></enumeratedValue><enumeratedValue><name>CR_150_168</name><description>150-168MHz HCLK/102</description><value>4</value></enumeratedValue></enumeratedValues> 20628 </field> 20629 <field> 20630 <name>MR</name> 20631 <description>MII register - select the desired MII register in the PHY device</description> 20632 <bitOffset>6</bitOffset> 20633 <bitWidth>5</bitWidth> 20634 <writeConstraint><range><minimum>0</minimum><maximum>31</maximum></range></writeConstraint> 20635 </field> 20636 <field> 20637 <name>PA</name> 20638 <description>PHY address - select which of possible 32 PHYs is being accessed</description> 20639 <bitOffset>11</bitOffset> 20640 <bitWidth>5</bitWidth> 20641 <writeConstraint><range><minimum>0</minimum><maximum>31</maximum></range></writeConstraint> 20642 </field> 20643 </fields> 20644 </register> 20645 <register> 20646 <name>MACMIIDR</name> 20647 <displayName>MACMIIDR</displayName> 20648 <description>Ethernet MAC MII data register</description> 20649 <addressOffset>0x14</addressOffset> 20650 <size>0x20</size> 20651 <access>read-write</access> 20652 <resetValue>0x00000000</resetValue> 20653 <fields> 20654 <field> 20655 <name>MD</name> 20656 <description>MII data read from/written to the PHY</description> 20657 <bitOffset>0</bitOffset> 20658 <bitWidth>16</bitWidth> 20659 <writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint> 20660 </field> 20661 </fields> 20662 </register> 20663 <register> 20664 <name>MACFCR</name> 20665 <displayName>MACFCR</displayName> 20666 <description>Ethernet MAC flow control 20667 register</description> 20668 <addressOffset>0x18</addressOffset> 20669 <size>0x20</size> 20670 <access>read-write</access> 20671 <resetValue>0x00000000</resetValue> 20672 <fields> 20673 <field> 20674 <name>FCB</name> 20675 <description>Flow control busy/back pressure activate</description> 20676 <bitOffset>0</bitOffset> 20677 <bitWidth>1</bitWidth> 20678 <enumeratedValues><name>FCB</name><usage>read-write</usage><enumeratedValue><name>PauseOrBackPressure</name><description>In full duplex, initiate a Pause control frame. In half duplex, assert back pressure</description><value>1</value></enumeratedValue><enumeratedValue><name>DisableBackPressure</name><description>In half duplex only, deasserts back pressure</description><value>0</value></enumeratedValue></enumeratedValues> 20679 </field> 20680 <field> 20681 <name>TFCE</name> 20682 <description>Transmit flow control enable</description> 20683 <bitOffset>1</bitOffset> 20684 <bitWidth>1</bitWidth> 20685 <enumeratedValues><name>TFCE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>In full duplex, flow control is disabled. In half duplex, back pressure is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>In full duplex, flow control is enabled. In half duplex, back pressure is enabled</description><value>1</value></enumeratedValue></enumeratedValues> 20686 </field> 20687 <field> 20688 <name>RFCE</name> 20689 <description>Receive flow control enable</description> 20690 <bitOffset>2</bitOffset> 20691 <bitWidth>1</bitWidth> 20692 <enumeratedValues><name>RFCE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Pause frames are not decoded</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>MAC decodes received Pause frames and disables its transmitted for a specified time</description><value>1</value></enumeratedValue></enumeratedValues> 20693 </field> 20694 <field> 20695 <name>UPFD</name> 20696 <description>Unicast pause frame detect</description> 20697 <bitOffset>3</bitOffset> 20698 <bitWidth>1</bitWidth> 20699 <enumeratedValues><name>UPFD</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>MAC detects only a Pause frame with the multicast address specified in the 802.3x standard</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>MAC additionally detects Pause frames with the station's unicast address</description><value>1</value></enumeratedValue></enumeratedValues> 20700 </field> 20701 <field> 20702 <name>PLT</name> 20703 <description>Pause low threshold</description> 20704 <bitOffset>4</bitOffset> 20705 <bitWidth>2</bitWidth> 20706 <enumeratedValues><name>PLT</name><usage>read-write</usage><enumeratedValue><name>PLT4</name><description>Pause time minus 4 slot times</description><value>0</value></enumeratedValue><enumeratedValue><name>PLT28</name><description>Pause time minus 28 slot times</description><value>1</value></enumeratedValue><enumeratedValue><name>PLT144</name><description>Pause time minus 144 slot times</description><value>2</value></enumeratedValue><enumeratedValue><name>PLT256</name><description>Pause time minus 256 slot times</description><value>3</value></enumeratedValue></enumeratedValues> 20707 </field> 20708 <field> 20709 <name>ZQPD</name> 20710 <description>Zero-quanta pause disable</description> 20711 <bitOffset>7</bitOffset> 20712 <bitWidth>1</bitWidth> 20713 <enumeratedValues><name>ZQPD</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>Normal operation with automatic zero-quanta pause control frame generation</description><value>0</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>Automatic generation of zero-quanta pause control frames is disabled</description><value>1</value></enumeratedValue></enumeratedValues> 20714 </field> 20715 <field> 20716 <name>PT</name> 20717 <description>Pause time</description> 20718 <bitOffset>16</bitOffset> 20719 <bitWidth>16</bitWidth> 20720 <writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint> 20721 </field> 20722 </fields> 20723 </register> 20724 <register> 20725 <name>MACVLANTR</name> 20726 <displayName>MACVLANTR</displayName> 20727 <description>Ethernet MAC VLAN tag register</description> 20728 <addressOffset>0x1C</addressOffset> 20729 <size>0x20</size> 20730 <access>read-write</access> 20731 <resetValue>0x00000000</resetValue> 20732 <fields> 20733 <field> 20734 <name>VLANTI</name> 20735 <description>VLAN tag identifier (for receive frames)</description> 20736 <bitOffset>0</bitOffset> 20737 <bitWidth>16</bitWidth> 20738 <writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint> 20739 </field> 20740 <field> 20741 <name>VLANTC</name> 20742 <description>12-bit VLAN tag comparison</description> 20743 <bitOffset>16</bitOffset> 20744 <bitWidth>1</bitWidth> 20745 <enumeratedValues><name>VLANTC</name><usage>read-write</usage><enumeratedValue><name>VLANTC16</name><description>Full 16 bit VLAN identifiers are used for comparison and filtering</description><value>0</value></enumeratedValue><enumeratedValue><name>VLANTC12</name><description>12 bit VLAN identifies are used for comparison and filtering</description><value>1</value></enumeratedValue></enumeratedValues> 20746 </field> 20747 </fields> 20748 </register> 20749 <register> 20750 <name>MACPMTCSR</name> 20751 <displayName>MACPMTCSR</displayName> 20752 <description>Ethernet MAC PMT control and status 20753 register</description> 20754 <addressOffset>0x2C</addressOffset> 20755 <size>0x20</size> 20756 <access>read-write</access> 20757 <resetValue>0x00000000</resetValue> 20758 <fields> 20759 <field> 20760 <name>PD</name> 20761 <description>Power down</description> 20762 <bitOffset>0</bitOffset> 20763 <bitWidth>1</bitWidth> 20764 <enumeratedValues><name>PD</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>All received frames will be dropped. Cleared automatically when a magic packet or wakeup frame is received</description><value>1</value></enumeratedValue></enumeratedValues> 20765 </field> 20766 <field> 20767 <name>MPE</name> 20768 <description>Magic packet enable</description> 20769 <bitOffset>1</bitOffset> 20770 <bitWidth>1</bitWidth> 20771 <enumeratedValues><name>MPE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>No power management event generated due to Magic Packet reception</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Enable generation of a power management event due to Magic Packet reception</description><value>1</value></enumeratedValue></enumeratedValues> 20772 </field> 20773 <field> 20774 <name>WFE</name> 20775 <description>Wakeup frame enable</description> 20776 <bitOffset>2</bitOffset> 20777 <bitWidth>1</bitWidth> 20778 <enumeratedValues><name>WFE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>No power management event generated due to wakeup frame reception</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Enable generation of a power management event due to wakeup frame reception</description><value>1</value></enumeratedValue></enumeratedValues> 20779 </field> 20780 <field> 20781 <name>MPR</name> 20782 <description>Magic packet received</description> 20783 <bitOffset>5</bitOffset> 20784 <bitWidth>1</bitWidth> 20785 </field> 20786 <field> 20787 <name>WFR</name> 20788 <description>Wakeup frame received</description> 20789 <bitOffset>6</bitOffset> 20790 <bitWidth>1</bitWidth> 20791 </field> 20792 <field> 20793 <name>GU</name> 20794 <description>Global unicast</description> 20795 <bitOffset>9</bitOffset> 20796 <bitWidth>1</bitWidth> 20797 <enumeratedValues><name>GU</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Normal operation</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Any unicast packet filtered by the MAC address recognition may be a wakeup frame</description><value>1</value></enumeratedValue></enumeratedValues> 20798 </field> 20799 <field> 20800 <name>WFFRPR</name> 20801 <description>Wakeup frame filter register pointer reset</description> 20802 <bitOffset>31</bitOffset> 20803 <bitWidth>1</bitWidth> 20804 <enumeratedValues><name>WFFRPR</name><usage>read-write</usage><enumeratedValue><name>Reset</name><description>Reset wakeup frame filter register point to 0b000. Automatically cleared</description><value>1</value></enumeratedValue></enumeratedValues> 20805 </field> 20806 </fields> 20807 </register> 20808 <register> 20809 <name>MACDBGR</name> 20810 <displayName>MACDBGR</displayName> 20811 <description>Ethernet MAC debug register</description> 20812 <addressOffset>0x34</addressOffset> 20813 <size>0x20</size> 20814 <access>read-only</access> 20815 <resetValue>0x00000000</resetValue> 20816 <fields> 20817 <field><name>TFF</name><description>Tx FIFO full</description><bitOffset>25</bitOffset><bitWidth>1</bitWidth></field> 20818 <field><name>TFNE</name><description>Tx FIFO not empty</description><bitOffset>24</bitOffset><bitWidth>1</bitWidth></field> 20819 <field><name>TFWA</name><description>Tx FIFO write active</description><bitOffset>22</bitOffset><bitWidth>1</bitWidth></field> 20820 <field><name>TFRS</name><description>Tx FIFO read status</description><bitOffset>20</bitOffset><bitWidth>2</bitWidth></field> 20821 <field><name>MTP</name><description>MAC transmitter in pause</description><bitOffset>19</bitOffset><bitWidth>1</bitWidth></field> 20822 <field><name>MTFCS</name><description>MAC transmit frame controller status</description><bitOffset>17</bitOffset><bitWidth>2</bitWidth></field> 20823 <field><name>MMTEA</name><description>MAC MII transmit engine active</description><bitOffset>16</bitOffset><bitWidth>1</bitWidth></field> 20824 <field><name>RFFL</name><description>Rx FIFO fill level</description><bitOffset>8</bitOffset><bitWidth>2</bitWidth></field> 20825 <field><name>RFRCS</name><description>Rx FIFO read controller status</description><bitOffset>5</bitOffset><bitWidth>2</bitWidth></field> 20826 <field><name>RFWRA</name><description>Rx FIFO write controller active</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field> 20827 <field><name>MSFRWCS</name><description>MAC small FIFO read/write controllers status</description><bitOffset>1</bitOffset><bitWidth>2</bitWidth></field> 20828 <field><name>MMRPEA</name><description>MAC MII receive protocol engine active</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field> 20829 </fields> 20830 </register> 20831 <register> 20832 <name>MACSR</name> 20833 <displayName>MACSR</displayName> 20834 <description>Ethernet MAC interrupt status 20835 register</description> 20836 <addressOffset>0x38</addressOffset> 20837 <size>0x20</size> 20838 <resetValue>0x00000000</resetValue> 20839 <fields> 20840 <field> 20841 <name>PMTS</name> 20842 <description>PMT status</description> 20843 <bitOffset>3</bitOffset> 20844 <bitWidth>1</bitWidth> 20845 <access>read-only</access> 20846 </field> 20847 <field> 20848 <name>MMCS</name> 20849 <description>MMC status</description> 20850 <bitOffset>4</bitOffset> 20851 <bitWidth>1</bitWidth> 20852 <access>read-only</access> 20853 </field> 20854 <field> 20855 <name>MMCRS</name> 20856 <description>MMC receive status</description> 20857 <bitOffset>5</bitOffset> 20858 <bitWidth>1</bitWidth> 20859 <access>read-only</access> 20860 </field> 20861 <field> 20862 <name>MMCTS</name> 20863 <description>MMC transmit status</description> 20864 <bitOffset>6</bitOffset> 20865 <bitWidth>1</bitWidth> 20866 <access>read-only</access> 20867 </field> 20868 <field> 20869 <name>TSTS</name> 20870 <description>Time stamp trigger status</description> 20871 <bitOffset>9</bitOffset> 20872 <bitWidth>1</bitWidth> 20873 <access>read-write</access> 20874 </field> 20875 </fields> 20876 </register> 20877 <register> 20878 <name>MACIMR</name> 20879 <displayName>MACIMR</displayName> 20880 <description>Ethernet MAC interrupt mask 20881 register</description> 20882 <addressOffset>0x3C</addressOffset> 20883 <size>0x20</size> 20884 <access>read-write</access> 20885 <resetValue>0x00000000</resetValue> 20886 <fields> 20887 <field> 20888 <name>PMTIM</name> 20889 <description>PMT interrupt mask</description> 20890 <bitOffset>3</bitOffset> 20891 <bitWidth>1</bitWidth> 20892 <enumeratedValues><name>PMTIM</name><usage>read-write</usage><enumeratedValue><name>Unmasked</name><description>PMT Status interrupt generation enabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Masked</name><description>PMT Status interrupt generation disabled</description><value>1</value></enumeratedValue></enumeratedValues> 20893 </field> 20894 <field> 20895 <name>TSTIM</name> 20896 <description>Time stamp trigger interrupt mask</description> 20897 <bitOffset>9</bitOffset> 20898 <bitWidth>1</bitWidth> 20899 <enumeratedValues><name>TSTIM</name><usage>read-write</usage><enumeratedValue><name>Unmasked</name><description>Time stamp interrupt generation enabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Masked</name><description>Time stamp interrupt generation disabled</description><value>1</value></enumeratedValue></enumeratedValues> 20900 </field> 20901 </fields> 20902 </register> 20903 <register> 20904 <name>MACA0HR</name> 20905 <displayName>MACA0HR</displayName> 20906 <description>Ethernet MAC address 0 high 20907 register</description> 20908 <addressOffset>0x40</addressOffset> 20909 <size>0x20</size> 20910 <resetValue>0x0010FFFF</resetValue> 20911 <fields> 20912 <field> 20913 <name>MACA0H</name> 20914 <description>MAC address0 high</description> 20915 <bitOffset>0</bitOffset> 20916 <bitWidth>16</bitWidth> 20917 <access>read-write</access> 20918 <writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint> 20919 </field> 20920 <field> 20921 <name>MO</name> 20922 <description>Always 1</description> 20923 <bitOffset>31</bitOffset> 20924 <bitWidth>1</bitWidth> 20925 <access>read-only</access> 20926 </field> 20927 </fields> 20928 </register> 20929 <register> 20930 <name>MACA0LR</name> 20931 <displayName>MACA0LR</displayName> 20932 <description>Ethernet MAC address 0 low 20933 register</description> 20934 <addressOffset>0x44</addressOffset> 20935 <size>0x20</size> 20936 <access>read-write</access> 20937 <resetValue>0xFFFFFFFF</resetValue> 20938 <fields> 20939 <field> 20940 <name>MACA0L</name> 20941 <description>0</description> 20942 <bitOffset>0</bitOffset> 20943 <bitWidth>32</bitWidth> 20944 <writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint> 20945 </field> 20946 </fields> 20947 </register> 20948 <register> 20949 <name>MACA1HR</name> 20950 <displayName>MACA1HR</displayName> 20951 <description>Ethernet MAC address 1 high 20952 register</description> 20953 <addressOffset>0x48</addressOffset> 20954 <size>0x20</size> 20955 <access>read-write</access> 20956 <resetValue>0x0000FFFF</resetValue> 20957 <fields> 20958 <field> 20959 <name>MACA1H</name> 20960 <description>MACA1H</description> 20961 <bitOffset>0</bitOffset> 20962 <bitWidth>16</bitWidth> 20963 <writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint> 20964 </field> 20965 <field> 20966 <name>MBC</name> 20967 <description>MBC</description> 20968 <bitOffset>24</bitOffset> 20969 <bitWidth>6</bitWidth> 20970 <writeConstraint><range><minimum>0</minimum><maximum>63</maximum></range></writeConstraint> 20971 </field> 20972 <field> 20973 <name>SA</name> 20974 <description>SA</description> 20975 <bitOffset>30</bitOffset> 20976 <bitWidth>1</bitWidth> 20977 <enumeratedValues><name>SA</name><usage>read-write</usage><enumeratedValue><name>Destination</name><description>This address is used for comparison with DA fields of the received frame</description><value>0</value></enumeratedValue><enumeratedValue><name>Source</name><description>This address is used for comparison with SA fields of received frames</description><value>1</value></enumeratedValue></enumeratedValues> 20978 </field> 20979 <field> 20980 <name>AE</name> 20981 <description>AE</description> 20982 <bitOffset>31</bitOffset> 20983 <bitWidth>1</bitWidth> 20984 <enumeratedValues><name>AE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Address filters ignore this address</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Address filters use this address</description><value>1</value></enumeratedValue></enumeratedValues> 20985 </field> 20986 </fields> 20987 </register> 20988 <register> 20989 <name>MACA1LR</name> 20990 <displayName>MACA1LR</displayName> 20991 <description>Ethernet MAC address1 low 20992 register</description> 20993 <addressOffset>0x4C</addressOffset> 20994 <size>0x20</size> 20995 <access>read-write</access> 20996 <resetValue>0xFFFFFFFF</resetValue> 20997 <fields> 20998 <field> 20999 <name>MACA1L</name> 21000 <description>MACA1LR</description> 21001 <bitOffset>0</bitOffset> 21002 <bitWidth>32</bitWidth> 21003 <writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint> 21004 </field> 21005 </fields> 21006 </register> 21007 <register> 21008 <name>MACA2HR</name> 21009 <displayName>MACA2HR</displayName> 21010 <description>Ethernet MAC address 2 high 21011 register</description> 21012 <addressOffset>0x50</addressOffset> 21013 <size>0x20</size> 21014 <access>read-write</access> 21015 <resetValue>0x0000FFFF</resetValue> 21016 <fields> 21017 <field> 21018 <name>MACA2H</name> 21019 <description>MAC2AH</description> 21020 <bitOffset>0</bitOffset> 21021 <bitWidth>16</bitWidth> 21022 <writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint> 21023 </field> 21024 <field> 21025 <name>MBC</name> 21026 <description>MBC</description> 21027 <bitOffset>24</bitOffset> 21028 <bitWidth>6</bitWidth> 21029 <writeConstraint><range><minimum>0</minimum><maximum>63</maximum></range></writeConstraint> 21030 </field> 21031 <field> 21032 <name>SA</name> 21033 <description>SA</description> 21034 <bitOffset>30</bitOffset> 21035 <bitWidth>1</bitWidth> 21036 <enumeratedValues><name>SA</name><usage>read-write</usage><enumeratedValue><name>Destination</name><description>This address is used for comparison with DA fields of the received frame</description><value>0</value></enumeratedValue><enumeratedValue><name>Source</name><description>This address is used for comparison with SA fields of received frames</description><value>1</value></enumeratedValue></enumeratedValues> 21037 </field> 21038 <field> 21039 <name>AE</name> 21040 <description>AE</description> 21041 <bitOffset>31</bitOffset> 21042 <bitWidth>1</bitWidth> 21043 <enumeratedValues><name>AE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Address filters ignore this address</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Address filters use this address</description><value>1</value></enumeratedValue></enumeratedValues> 21044 </field> 21045 </fields> 21046 </register> 21047 <register> 21048 <name>MACA2LR</name> 21049 <displayName>MACA2LR</displayName> 21050 <description>Ethernet MAC address 2 low 21051 register</description> 21052 <addressOffset>0x54</addressOffset> 21053 <size>0x20</size> 21054 <access>read-write</access> 21055 <resetValue>0xFFFFFFFF</resetValue> 21056 <fields> 21057 <field> 21058 <name>MACA2L</name> 21059 <description>MACA2L</description> 21060 <bitOffset>0</bitOffset> 21061 <bitWidth>32</bitWidth> 21062 <writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint> 21063 </field> 21064 </fields> 21065 </register> 21066 <register> 21067 <name>MACA3HR</name> 21068 <displayName>MACA3HR</displayName> 21069 <description>Ethernet MAC address 3 high 21070 register</description> 21071 <addressOffset>0x58</addressOffset> 21072 <size>0x20</size> 21073 <access>read-write</access> 21074 <resetValue>0x0000FFFF</resetValue> 21075 <fields> 21076 <field> 21077 <name>MACA3H</name> 21078 <description>MACA3H</description> 21079 <bitOffset>0</bitOffset> 21080 <bitWidth>16</bitWidth> 21081 <writeConstraint><range><minimum>0</minimum><maximum>65535</maximum></range></writeConstraint> 21082 </field> 21083 <field> 21084 <name>MBC</name> 21085 <description>MBC</description> 21086 <bitOffset>24</bitOffset> 21087 <bitWidth>6</bitWidth> 21088 <writeConstraint><range><minimum>0</minimum><maximum>63</maximum></range></writeConstraint> 21089 </field> 21090 <field> 21091 <name>SA</name> 21092 <description>SA</description> 21093 <bitOffset>30</bitOffset> 21094 <bitWidth>1</bitWidth> 21095 <enumeratedValues><name>SA</name><usage>read-write</usage><enumeratedValue><name>Destination</name><description>This address is used for comparison with DA fields of the received frame</description><value>0</value></enumeratedValue><enumeratedValue><name>Source</name><description>This address is used for comparison with SA fields of received frames</description><value>1</value></enumeratedValue></enumeratedValues> 21096 </field> 21097 <field> 21098 <name>AE</name> 21099 <description>AE</description> 21100 <bitOffset>31</bitOffset> 21101 <bitWidth>1</bitWidth> 21102 <enumeratedValues><name>AE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Address filters ignore this address</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Address filters use this address</description><value>1</value></enumeratedValue></enumeratedValues> 21103 </field> 21104 </fields> 21105 </register> 21106 <register> 21107 <name>MACA3LR</name> 21108 <displayName>MACA3LR</displayName> 21109 <description>Ethernet MAC address 3 low 21110 register</description> 21111 <addressOffset>0x5C</addressOffset> 21112 <size>0x20</size> 21113 <access>read-write</access> 21114 <resetValue>0xFFFFFFFF</resetValue> 21115 <fields> 21116 <field> 21117 <name>MACA3L</name> 21118 <description>MBCA3L</description> 21119 <bitOffset>0</bitOffset> 21120 <bitWidth>32</bitWidth> 21121 <writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint> 21122 </field> 21123 </fields> 21124 </register> 21125 </registers> 21126 </peripheral> 21127 <peripheral> 21128 <name>Ethernet_MMC</name> 21129 <description>Ethernet: MAC management counters</description> 21130 <groupName>Ethernet</groupName> 21131 <baseAddress>0x40028100</baseAddress> 21132 <addressBlock> 21133 <offset>0x0</offset> 21134 <size>0x400</size> 21135 <usage>registers</usage> 21136 </addressBlock> 21137 <registers> 21138 <register> 21139 <name>MMCCR</name> 21140 <displayName>MMCCR</displayName> 21141 <description>Ethernet MMC control register</description> 21142 <addressOffset>0x0</addressOffset> 21143 <size>0x20</size> 21144 <access>read-write</access> 21145 <resetValue>0x00000000</resetValue> 21146 <fields> 21147 <field> 21148 <name>CR</name> 21149 <description>Counter reset</description> 21150 <bitOffset>0</bitOffset> 21151 <bitWidth>1</bitWidth> 21152 <enumeratedValues><name>CR</name><usage>read-write</usage><enumeratedValue><name>Reset</name><description>Reset all counters. Cleared automatically</description><value>1</value></enumeratedValue></enumeratedValues> 21153 </field> 21154 <field> 21155 <name>CSR</name> 21156 <description>Counter stop rollover</description> 21157 <bitOffset>1</bitOffset> 21158 <bitWidth>1</bitWidth> 21159 <enumeratedValues><name>CSR</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Counters roll over to zero after reaching the maximum value</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Counters do not roll over to zero after reaching the maximum value</description><value>1</value></enumeratedValue></enumeratedValues> 21160 </field> 21161 <field> 21162 <name>ROR</name> 21163 <description>Reset on read</description> 21164 <bitOffset>2</bitOffset> 21165 <bitWidth>1</bitWidth> 21166 <enumeratedValues><name>ROR</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>MMC counters do not reset on read</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>MMC counters reset to zero after read</description><value>1</value></enumeratedValue></enumeratedValues> 21167 </field> 21168 <field> 21169 <name>MCF</name> 21170 <description>MMC counter freeze</description> 21171 <bitOffset>3</bitOffset> 21172 <bitWidth>1</bitWidth> 21173 <enumeratedValues><name>MCF</name><usage>read-write</usage><enumeratedValue><name>Unfrozen</name><description>All MMC counters update normally</description><value>0</value></enumeratedValue><enumeratedValue><name>Frozen</name><description>All MMC counters frozen to their current value</description><value>1</value></enumeratedValue></enumeratedValues> 21174 </field> 21175 <field> 21176 <name>MCP</name> 21177 <description>MMC counter preset</description> 21178 <bitOffset>4</bitOffset> 21179 <bitWidth>1</bitWidth> 21180 <enumeratedValues><name>MCP</name><usage>read-write</usage><enumeratedValue><name>Preset</name><description>MMC counters will be preset to almost full or almost half. Cleared automatically</description><value>1</value></enumeratedValue></enumeratedValues> 21181 </field> 21182 <field> 21183 <name>MCFHP</name> 21184 <description>MMC counter Full-Half preset</description> 21185 <bitOffset>5</bitOffset> 21186 <bitWidth>1</bitWidth> 21187 <enumeratedValues><name>MCFHP</name><usage>read-write</usage><enumeratedValue><name>AlmostHalf</name><description>When MCP is set, MMC counters are preset to almost-half value 0x7FFF_FFF0</description><value>0</value></enumeratedValue><enumeratedValue><name>AlmostFull</name><description>When MCP is set, MMC counters are preset to almost-full value 0xFFFF_FFF0</description><value>1</value></enumeratedValue></enumeratedValues> 21188 </field> 21189 </fields> 21190 </register> 21191 <register> 21192 <name>MMCRIR</name> 21193 <displayName>MMCRIR</displayName> 21194 <description>Ethernet MMC receive interrupt 21195 register</description> 21196 <addressOffset>0x4</addressOffset> 21197 <size>0x20</size> 21198 <access>read-write</access> 21199 <resetValue>0x00000000</resetValue> 21200 <fields> 21201 <field> 21202 <name>RFCES</name> 21203 <description>Received frames CRC error status</description> 21204 <bitOffset>5</bitOffset> 21205 <bitWidth>1</bitWidth> 21206 </field> 21207 <field> 21208 <name>RFAES</name> 21209 <description>Received frames alignment error status</description> 21210 <bitOffset>6</bitOffset> 21211 <bitWidth>1</bitWidth> 21212 </field> 21213 <field> 21214 <name>RGUFS</name> 21215 <description>Received good Unicast frames status</description> 21216 <bitOffset>17</bitOffset> 21217 <bitWidth>1</bitWidth> 21218 </field> 21219 </fields> 21220 </register> 21221 <register> 21222 <name>MMCTIR</name> 21223 <displayName>MMCTIR</displayName> 21224 <description>Ethernet MMC transmit interrupt 21225 register</description> 21226 <addressOffset>0x8</addressOffset> 21227 <size>0x20</size> 21228 <access>read-only</access> 21229 <resetValue>0x00000000</resetValue> 21230 <fields> 21231 <field> 21232 <name>TGFSCS</name> 21233 <description>Transmitted good frames single collision status</description> 21234 <bitOffset>14</bitOffset> 21235 <bitWidth>1</bitWidth> 21236 </field> 21237 <field> 21238 <name>TGFMSCS</name> 21239 <description>Transmitted good frames more than single collision status</description> 21240 <bitOffset>15</bitOffset> 21241 <bitWidth>1</bitWidth> 21242 </field> 21243 <field> 21244 <name>TGFS</name> 21245 <description>Transmitted good frames status</description> 21246 <bitOffset>21</bitOffset> 21247 <bitWidth>1</bitWidth> 21248 </field> 21249 </fields> 21250 </register> 21251 <register> 21252 <name>MMCRIMR</name> 21253 <displayName>MMCRIMR</displayName> 21254 <description>Ethernet MMC receive interrupt mask 21255 register</description> 21256 <addressOffset>0xC</addressOffset> 21257 <size>0x20</size> 21258 <access>read-write</access> 21259 <resetValue>0x00000000</resetValue> 21260 <fields> 21261 <field> 21262 <name>RFCEM</name> 21263 <description>Received frame CRC error mask</description> 21264 <bitOffset>5</bitOffset> 21265 <bitWidth>1</bitWidth> 21266 <enumeratedValues><name>RFCEM</name><usage>read-write</usage><enumeratedValue><name>Unmasked</name><description>Received-crc-error counter half-full interrupt enabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Masked</name><description>Received-crc-error counter half-full interrupt disabled</description><value>1</value></enumeratedValue></enumeratedValues> 21267 </field> 21268 <field> 21269 <name>RFAEM</name> 21270 <description>Received frames alignment error mask</description> 21271 <bitOffset>6</bitOffset> 21272 <bitWidth>1</bitWidth> 21273 <enumeratedValues><name>RFAEM</name><usage>read-write</usage><enumeratedValue><name>Unmasked</name><description>Received-alignment-error counter half-full interrupt enabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Masked</name><description>Received-alignment-error counter half-full interrupt disabled</description><value>1</value></enumeratedValue></enumeratedValues> 21274 </field> 21275 <field> 21276 <name>RGUFM</name> 21277 <description>Received good Unicast frames mask</description> 21278 <bitOffset>17</bitOffset> 21279 <bitWidth>1</bitWidth> 21280 <enumeratedValues><name>RGUFM</name><usage>read-write</usage><enumeratedValue><name>Unmasked</name><description>Received-good-unicast counter half-full interrupt enabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Masked</name><description>Received-good-unicast counter half-full interrupt disabled</description><value>1</value></enumeratedValue></enumeratedValues> 21281 </field> 21282 </fields> 21283 </register> 21284 <register> 21285 <name>MMCTIMR</name> 21286 <displayName>MMCTIMR</displayName> 21287 <description>Ethernet MMC transmit interrupt mask 21288 register</description> 21289 <addressOffset>0x10</addressOffset> 21290 <size>0x20</size> 21291 <access>read-write</access> 21292 <resetValue>0x00000000</resetValue> 21293 <fields> 21294 <field> 21295 <name>TGFSCM</name> 21296 <description>Transmitted good frames single collision mask</description> 21297 <bitOffset>14</bitOffset> 21298 <bitWidth>1</bitWidth> 21299 <enumeratedValues><name>TGFSCM</name><usage>read-write</usage><enumeratedValue><name>Unmasked</name><description>Transmitted-good-single-collision half-full interrupt enabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Masked</name><description>Transmitted-good-single-collision half-full interrupt disabled</description><value>1</value></enumeratedValue></enumeratedValues> 21300 </field> 21301 <field> 21302 <name>TGFMSCM</name> 21303 <description>Transmitted good frames more than single collision mask</description> 21304 <bitOffset>15</bitOffset> 21305 <bitWidth>1</bitWidth> 21306 <enumeratedValues><name>TGFMSCM</name><usage>read-write</usage><enumeratedValue><name>Unmasked</name><description>Transmitted-good-multiple-collision half-full interrupt enabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Masked</name><description>Transmitted-good-multiple-collision half-full interrupt disabled</description><value>1</value></enumeratedValue></enumeratedValues> 21307 </field> 21308 <field> 21309 <name>TGFM</name> 21310 <description>Transmitted good frames mask</description> 21311 <bitOffset>16</bitOffset> 21312 <bitWidth>1</bitWidth> 21313 <enumeratedValues><name>TGFM</name><usage>read-write</usage><enumeratedValue><name>Unmasked</name><description>Transmitted-good counter half-full interrupt enabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Masked</name><description>Transmitted-good counter half-full interrupt disabled</description><value>1</value></enumeratedValue></enumeratedValues> 21314 </field> 21315 </fields> 21316 </register> 21317 <register> 21318 <name>MMCTGFSCCR</name> 21319 <displayName>MMCTGFSCCR</displayName> 21320 <description>Ethernet MMC transmitted good frames after a 21321 single collision counter</description> 21322 <addressOffset>0x4C</addressOffset> 21323 <size>0x20</size> 21324 <access>read-only</access> 21325 <resetValue>0x00000000</resetValue> 21326 <fields> 21327 <field> 21328 <name>TGFSCC</name> 21329 <description>Transmitted good frames single collision counter</description> 21330 <bitOffset>0</bitOffset> 21331 <bitWidth>32</bitWidth> 21332 </field> 21333 </fields> 21334 </register> 21335 <register> 21336 <name>MMCTGFMSCCR</name> 21337 <displayName>MMCTGFMSCCR</displayName> 21338 <description>Ethernet MMC transmitted good frames after 21339 more than a single collision</description> 21340 <addressOffset>0x50</addressOffset> 21341 <size>0x20</size> 21342 <access>read-only</access> 21343 <resetValue>0x00000000</resetValue> 21344 <fields> 21345 <field> 21346 <name>TGFMSCC</name> 21347 <description>TGFMSCC</description> 21348 <bitOffset>0</bitOffset> 21349 <bitWidth>32</bitWidth> 21350 </field> 21351 </fields> 21352 </register> 21353 <register> 21354 <name>MMCTGFCR</name> 21355 <displayName>MMCTGFCR</displayName> 21356 <description>Ethernet MMC transmitted good frames counter 21357 register</description> 21358 <addressOffset>0x68</addressOffset> 21359 <size>0x20</size> 21360 <access>read-only</access> 21361 <resetValue>0x00000000</resetValue> 21362 <fields> 21363 <field> 21364 <name>TGFC</name> 21365 <description>HTL</description> 21366 <bitOffset>0</bitOffset> 21367 <bitWidth>32</bitWidth> 21368 </field> 21369 </fields> 21370 </register> 21371 <register> 21372 <name>MMCRFCECR</name> 21373 <displayName>MMCRFCECR</displayName> 21374 <description>Ethernet MMC received frames with CRC error 21375 counter register</description> 21376 <addressOffset>0x94</addressOffset> 21377 <size>0x20</size> 21378 <access>read-only</access> 21379 <resetValue>0x00000000</resetValue> 21380 <fields> 21381 <field> 21382 <name>RFCFC</name> 21383 <description>RFCFC</description> 21384 <bitOffset>0</bitOffset> 21385 <bitWidth>32</bitWidth> 21386 </field> 21387 </fields> 21388 </register> 21389 <register> 21390 <name>MMCRFAECR</name> 21391 <displayName>MMCRFAECR</displayName> 21392 <description>Ethernet MMC received frames with alignment 21393 error counter register</description> 21394 <addressOffset>0x98</addressOffset> 21395 <size>0x20</size> 21396 <access>read-only</access> 21397 <resetValue>0x00000000</resetValue> 21398 <fields> 21399 <field> 21400 <name>RFAEC</name> 21401 <description>RFAEC</description> 21402 <bitOffset>0</bitOffset> 21403 <bitWidth>32</bitWidth> 21404 </field> 21405 </fields> 21406 </register> 21407 <register> 21408 <name>MMCRGUFCR</name> 21409 <displayName>MMCRGUFCR</displayName> 21410 <description>MMC received good unicast frames counter 21411 register</description> 21412 <addressOffset>0xC4</addressOffset> 21413 <size>0x20</size> 21414 <access>read-only</access> 21415 <resetValue>0x00000000</resetValue> 21416 <fields> 21417 <field> 21418 <name>RGUFC</name> 21419 <description>RGUFC</description> 21420 <bitOffset>0</bitOffset> 21421 <bitWidth>32</bitWidth> 21422 </field> 21423 </fields> 21424 </register> 21425 </registers> 21426 </peripheral> 21427 <peripheral> 21428 <name>Ethernet_PTP</name> 21429 <description>Ethernet: Precision time protocol</description> 21430 <groupName>Ethernet</groupName> 21431 <baseAddress>0x40028700</baseAddress> 21432 <addressBlock> 21433 <offset>0x0</offset> 21434 <size>0x400</size> 21435 <usage>registers</usage> 21436 </addressBlock> 21437 <registers> 21438 <register> 21439 <name>PTPTSCR</name> 21440 <displayName>PTPTSCR</displayName> 21441 <description>Ethernet PTP time stamp control 21442 register</description> 21443 <addressOffset>0x0</addressOffset> 21444 <size>0x20</size> 21445 <access>read-write</access> 21446 <resetValue>0x00002000</resetValue> 21447 <fields> 21448 <field> 21449 <name>TSE</name> 21450 <description>TSE</description> 21451 <bitOffset>0</bitOffset> 21452 <bitWidth>1</bitWidth> 21453 </field> 21454 <field> 21455 <name>TSFCU</name> 21456 <description>TSFCU</description> 21457 <bitOffset>1</bitOffset> 21458 <bitWidth>1</bitWidth> 21459 </field> 21460 <field> 21461 <name>TSPTPPSV2E</name> 21462 <description>TSPTPPSV2E</description> 21463 <bitOffset>10</bitOffset> 21464 <bitWidth>1</bitWidth> 21465 </field> 21466 <field> 21467 <name>TSSPTPOEFE</name> 21468 <description>TSSPTPOEFE</description> 21469 <bitOffset>11</bitOffset> 21470 <bitWidth>1</bitWidth> 21471 </field> 21472 <field> 21473 <name>TSSIPV6FE</name> 21474 <description>TSSIPV6FE</description> 21475 <bitOffset>12</bitOffset> 21476 <bitWidth>1</bitWidth> 21477 </field> 21478 <field> 21479 <name>TSSIPV4FE</name> 21480 <description>TSSIPV4FE</description> 21481 <bitOffset>13</bitOffset> 21482 <bitWidth>1</bitWidth> 21483 </field> 21484 <field> 21485 <name>TSSEME</name> 21486 <description>TSSEME</description> 21487 <bitOffset>14</bitOffset> 21488 <bitWidth>1</bitWidth> 21489 </field> 21490 <field> 21491 <name>TSSMRME</name> 21492 <description>TSSMRME</description> 21493 <bitOffset>15</bitOffset> 21494 <bitWidth>1</bitWidth> 21495 </field> 21496 <field> 21497 <name>TSCNT</name> 21498 <description>TSCNT</description> 21499 <bitOffset>16</bitOffset> 21500 <bitWidth>2</bitWidth> 21501 </field> 21502 <field> 21503 <name>TSPFFMAE</name> 21504 <description>TSPFFMAE</description> 21505 <bitOffset>18</bitOffset> 21506 <bitWidth>1</bitWidth> 21507 </field> 21508 <field> 21509 <name>TSSTI</name> 21510 <description>TSSTI</description> 21511 <bitOffset>2</bitOffset> 21512 <bitWidth>1</bitWidth> 21513 </field> 21514 <field> 21515 <name>TSSTU</name> 21516 <description>TSSTU</description> 21517 <bitOffset>3</bitOffset> 21518 <bitWidth>1</bitWidth> 21519 </field> 21520 <field> 21521 <name>TSITE</name> 21522 <description>TSITE</description> 21523 <bitOffset>4</bitOffset> 21524 <bitWidth>1</bitWidth> 21525 </field> 21526 <field> 21527 <name>TTSARU</name> 21528 <description>TTSARU</description> 21529 <bitOffset>5</bitOffset> 21530 <bitWidth>1</bitWidth> 21531 </field> 21532 <field> 21533 <name>TSSARFE</name> 21534 <description>TSSARFE</description> 21535 <bitOffset>8</bitOffset> 21536 <bitWidth>1</bitWidth> 21537 </field> 21538 <field> 21539 <name>TSSSR</name> 21540 <description>TSSSR</description> 21541 <bitOffset>9</bitOffset> 21542 <bitWidth>1</bitWidth> 21543 </field> 21544 </fields> 21545 </register> 21546 <register> 21547 <name>PTPSSIR</name> 21548 <displayName>PTPSSIR</displayName> 21549 <description>Ethernet PTP subsecond increment 21550 register</description> 21551 <addressOffset>0x4</addressOffset> 21552 <size>0x20</size> 21553 <access>read-write</access> 21554 <resetValue>0x00000000</resetValue> 21555 <fields> 21556 <field> 21557 <name>STSSI</name> 21558 <description>STSSI</description> 21559 <bitOffset>0</bitOffset> 21560 <bitWidth>8</bitWidth> 21561 </field> 21562 </fields> 21563 </register> 21564 <register> 21565 <name>PTPTSHR</name> 21566 <displayName>PTPTSHR</displayName> 21567 <description>Ethernet PTP time stamp high 21568 register</description> 21569 <addressOffset>0x8</addressOffset> 21570 <size>0x20</size> 21571 <access>read-only</access> 21572 <resetValue>0x00000000</resetValue> 21573 <fields> 21574 <field> 21575 <name>STS</name> 21576 <description>STS</description> 21577 <bitOffset>0</bitOffset> 21578 <bitWidth>32</bitWidth> 21579 </field> 21580 </fields> 21581 </register> 21582 <register> 21583 <name>PTPTSLR</name> 21584 <displayName>PTPTSLR</displayName> 21585 <description>Ethernet PTP time stamp low 21586 register</description> 21587 <addressOffset>0xC</addressOffset> 21588 <size>0x20</size> 21589 <access>read-only</access> 21590 <resetValue>0x00000000</resetValue> 21591 <fields> 21592 <field> 21593 <name>STSS</name> 21594 <description>STSS</description> 21595 <bitOffset>0</bitOffset> 21596 <bitWidth>31</bitWidth> 21597 </field> 21598 <field> 21599 <name>STPNS</name> 21600 <description>STPNS</description> 21601 <bitOffset>31</bitOffset> 21602 <bitWidth>1</bitWidth> 21603 </field> 21604 </fields> 21605 </register> 21606 <register> 21607 <name>PTPTSHUR</name> 21608 <displayName>PTPTSHUR</displayName> 21609 <description>Ethernet PTP time stamp high update 21610 register</description> 21611 <addressOffset>0x10</addressOffset> 21612 <size>0x20</size> 21613 <access>read-write</access> 21614 <resetValue>0x00000000</resetValue> 21615 <fields> 21616 <field> 21617 <name>TSUS</name> 21618 <description>TSUS</description> 21619 <bitOffset>0</bitOffset> 21620 <bitWidth>32</bitWidth> 21621 </field> 21622 </fields> 21623 </register> 21624 <register> 21625 <name>PTPTSLUR</name> 21626 <displayName>PTPTSLUR</displayName> 21627 <description>Ethernet PTP time stamp low update 21628 register</description> 21629 <addressOffset>0x14</addressOffset> 21630 <size>0x20</size> 21631 <access>read-write</access> 21632 <resetValue>0x00000000</resetValue> 21633 <fields> 21634 <field> 21635 <name>TSUSS</name> 21636 <description>TSUSS</description> 21637 <bitOffset>0</bitOffset> 21638 <bitWidth>31</bitWidth> 21639 </field> 21640 <field> 21641 <name>TSUPNS</name> 21642 <description>TSUPNS</description> 21643 <bitOffset>31</bitOffset> 21644 <bitWidth>1</bitWidth> 21645 </field> 21646 </fields> 21647 </register> 21648 <register> 21649 <name>PTPTSAR</name> 21650 <displayName>PTPTSAR</displayName> 21651 <description>Ethernet PTP time stamp addend 21652 register</description> 21653 <addressOffset>0x18</addressOffset> 21654 <size>0x20</size> 21655 <access>read-write</access> 21656 <resetValue>0x00000000</resetValue> 21657 <fields> 21658 <field> 21659 <name>TSA</name> 21660 <description>TSA</description> 21661 <bitOffset>0</bitOffset> 21662 <bitWidth>32</bitWidth> 21663 </field> 21664 </fields> 21665 </register> 21666 <register> 21667 <name>PTPTTHR</name> 21668 <displayName>PTPTTHR</displayName> 21669 <description>Ethernet PTP target time high 21670 register</description> 21671 <addressOffset>0x1C</addressOffset> 21672 <size>0x20</size> 21673 <access>read-write</access> 21674 <resetValue>0x00000000</resetValue> 21675 <fields> 21676 <field> 21677 <name>TTSH</name> 21678 <description>0</description> 21679 <bitOffset>0</bitOffset> 21680 <bitWidth>32</bitWidth> 21681 </field> 21682 </fields> 21683 </register> 21684 <register> 21685 <name>PTPTTLR</name> 21686 <displayName>PTPTTLR</displayName> 21687 <description>Ethernet PTP target time low 21688 register</description> 21689 <addressOffset>0x20</addressOffset> 21690 <size>0x20</size> 21691 <access>read-write</access> 21692 <resetValue>0x00000000</resetValue> 21693 <fields> 21694 <field> 21695 <name>TTSL</name> 21696 <description>TTSL</description> 21697 <bitOffset>0</bitOffset> 21698 <bitWidth>32</bitWidth> 21699 </field> 21700 </fields> 21701 </register> 21702 <register> 21703 <name>PTPTSSR</name> 21704 <displayName>PTPTSSR</displayName> 21705 <description>Ethernet PTP time stamp status 21706 register</description> 21707 <addressOffset>0x28</addressOffset> 21708 <size>0x20</size> 21709 <access>read-only</access> 21710 <resetValue>0x00000000</resetValue> 21711 <fields> 21712 <field> 21713 <name>TSSO</name> 21714 <description>TSSO</description> 21715 <bitOffset>0</bitOffset> 21716 <bitWidth>1</bitWidth> 21717 </field> 21718 <field> 21719 <name>TSTTR</name> 21720 <description>TSTTR</description> 21721 <bitOffset>1</bitOffset> 21722 <bitWidth>1</bitWidth> 21723 </field> 21724 </fields> 21725 </register> 21726 <register> 21727 <name>PTPPPSCR</name> 21728 <displayName>PTPPPSCR</displayName> 21729 <description>Ethernet PTP PPS control 21730 register</description> 21731 <addressOffset>0x2C</addressOffset> 21732 <size>0x20</size> 21733 <access>read-only</access> 21734 <resetValue>0x00000000</resetValue> 21735 <fields> 21736 <field> 21737 <name>TSSO</name> 21738 <description>TSSO</description> 21739 <bitOffset>0</bitOffset> 21740 <bitWidth>1</bitWidth> 21741 </field> 21742 <field> 21743 <name>TSTTR</name> 21744 <description>TSTTR</description> 21745 <bitOffset>1</bitOffset> 21746 <bitWidth>1</bitWidth> 21747 </field> 21748 </fields> 21749 </register> 21750 </registers> 21751 </peripheral> 21752 <peripheral> 21753 <name>Ethernet_DMA</name> 21754 <description>Ethernet: DMA controller operation</description> 21755 <groupName>Ethernet</groupName> 21756 <baseAddress>0x40029000</baseAddress> 21757 <addressBlock> 21758 <offset>0x0</offset> 21759 <size>0x400</size> 21760 <usage>registers</usage> 21761 </addressBlock> 21762 <registers> 21763 <register> 21764 <name>DMABMR</name> 21765 <displayName>DMABMR</displayName> 21766 <description>Ethernet DMA bus mode register</description> 21767 <addressOffset>0x0</addressOffset> 21768 <size>0x20</size> 21769 <access>read-write</access> 21770 <resetValue>0x00002101</resetValue> 21771 <fields> 21772 <field> 21773 <name>SR</name> 21774 <description>Software reset</description> 21775 <bitOffset>0</bitOffset> 21776 <bitWidth>1</bitWidth> 21777 <enumeratedValues><name>SR</name><usage>read-write</usage><enumeratedValue><name>Reset</name><description>Reset all MAC subsystem internal registers and logic. Cleared automatically</description><value>1</value></enumeratedValue></enumeratedValues> 21778 </field> 21779 <field> 21780 <name>DA</name> 21781 <description>DMA arbitration</description> 21782 <bitOffset>1</bitOffset> 21783 <bitWidth>1</bitWidth> 21784 <enumeratedValues><name>DA</name><usage>read-write</usage><enumeratedValue><name>RoundRobin</name><description>Round-robin with Rx:Tx priority given by PM</description><value>0</value></enumeratedValue><enumeratedValue><name>RxPriority</name><description>Rx has priority over Tx</description><value>1</value></enumeratedValue></enumeratedValues> 21785 </field> 21786 <field> 21787 <name>DSL</name> 21788 <description>Descriptor skip length</description> 21789 <bitOffset>2</bitOffset> 21790 <bitWidth>5</bitWidth> 21791 <writeConstraint><range><minimum>0</minimum><maximum>31</maximum></range></writeConstraint> 21792 </field> 21793 <field> 21794 <name>EDFE</name> 21795 <description>Enhanced descriptor format enable</description> 21796 <bitOffset>7</bitOffset> 21797 <bitWidth>1</bitWidth> 21798 <enumeratedValues><name>EDFE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Normal descriptor format</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Enhanced 32-byte descriptor format, required for timestamping and IPv4 checksum offload</description><value>1</value></enumeratedValue></enumeratedValues> 21799 </field> 21800 <field> 21801 <name>PBL</name> 21802 <description>Programmable burst length</description> 21803 <bitOffset>8</bitOffset> 21804 <bitWidth>6</bitWidth> 21805 <enumeratedValues><name>PBL</name><usage>read-write</usage><enumeratedValue><name>PBL1</name><description>Maximum of 1 beat per DMA transaction</description><value>1</value></enumeratedValue><enumeratedValue><name>PBL2</name><description>Maximum of 2 beats per DMA transaction</description><value>2</value></enumeratedValue><enumeratedValue><name>PBL4</name><description>Maximum of 4 beats per DMA transaction</description><value>4</value></enumeratedValue><enumeratedValue><name>PBL8</name><description>Maximum of 8 beats per DMA transaction</description><value>8</value></enumeratedValue><enumeratedValue><name>PBL16</name><description>Maximum of 16 beats per DMA transaction</description><value>16</value></enumeratedValue><enumeratedValue><name>PBL32</name><description>Maximum of 32 beats per DMA transaction</description><value>32</value></enumeratedValue></enumeratedValues> 21806 </field> 21807 <field> 21808 <name>PM</name> 21809 <description>Rx-Tx priority ratio</description> 21810 <bitOffset>14</bitOffset> 21811 <bitWidth>2</bitWidth> 21812 <enumeratedValues><name>PM</name><usage>read-write</usage><enumeratedValue><name>OneToOne</name><description>RxDMA priority over TxDMA is 1:1</description><value>0</value></enumeratedValue><enumeratedValue><name>TwoToOne</name><description>RxDMA priority over TxDMA is 2:1</description><value>1</value></enumeratedValue><enumeratedValue><name>ThreeToOne</name><description>RxDMA priority over TxDMA is 3:1</description><value>2</value></enumeratedValue><enumeratedValue><name>FourToOne</name><description>RxDMA priority over TxDMA is 4:1</description><value>3</value></enumeratedValue></enumeratedValues> 21813 </field> 21814 <field> 21815 <name>FB</name> 21816 <description>Fixed burst</description> 21817 <bitOffset>16</bitOffset> 21818 <bitWidth>1</bitWidth> 21819 <enumeratedValues><name>FB</name><usage>read-write</usage><enumeratedValue><name>Variable</name><description>AHB uses SINGLE and INCR burst transfers</description><value>0</value></enumeratedValue><enumeratedValue><name>Fixed</name><description>AHB uses only fixed burst transfers</description><value>1</value></enumeratedValue></enumeratedValues> 21820 </field> 21821 <field> 21822 <name>RDP</name> 21823 <description>Rx DMA PBL</description> 21824 <bitOffset>17</bitOffset> 21825 <bitWidth>6</bitWidth> 21826 <enumeratedValues><name>RDP</name><usage>read-write</usage><enumeratedValue><name>RDP1</name><description>1 beat per RxDMA transaction</description><value>1</value></enumeratedValue><enumeratedValue><name>RDP2</name><description>2 beats per RxDMA transaction</description><value>2</value></enumeratedValue><enumeratedValue><name>RDP4</name><description>4 beats per RxDMA transaction</description><value>4</value></enumeratedValue><enumeratedValue><name>RDP8</name><description>8 beats per RxDMA transaction</description><value>8</value></enumeratedValue><enumeratedValue><name>RDP16</name><description>16 beats per RxDMA transaction</description><value>16</value></enumeratedValue><enumeratedValue><name>RDP32</name><description>32 beats per RxDMA transaction</description><value>32</value></enumeratedValue></enumeratedValues> 21827 </field> 21828 <field> 21829 <name>USP</name> 21830 <description>Use separate PBL</description> 21831 <bitOffset>23</bitOffset> 21832 <bitWidth>1</bitWidth> 21833 <enumeratedValues><name>USP</name><usage>read-write</usage><enumeratedValue><name>Combined</name><description>PBL value used for both Rx and Tx DMA</description><value>0</value></enumeratedValue><enumeratedValue><name>Separate</name><description>RxDMA uses RDP value, TxDMA uses PBL value</description><value>1</value></enumeratedValue></enumeratedValues> 21834 </field> 21835 <field> 21836 <name>FPM</name> 21837 <description>4xPBL mode</description> 21838 <bitOffset>24</bitOffset> 21839 <bitWidth>1</bitWidth> 21840 <enumeratedValues><name>FPM</name><usage>read-write</usage><enumeratedValue><name>x1</name><description>PBL values used as-is</description><value>0</value></enumeratedValue><enumeratedValue><name>x4</name><description>PBL values multiplied by 4</description><value>1</value></enumeratedValue></enumeratedValues> 21841 </field> 21842 <field> 21843 <name>AAB</name> 21844 <description>Address-aligned beats</description> 21845 <bitOffset>25</bitOffset> 21846 <bitWidth>1</bitWidth> 21847 <enumeratedValues><name>AAB</name><usage>read-write</usage><enumeratedValue><name>Unaligned</name><description>Bursts are not aligned</description><value>0</value></enumeratedValue><enumeratedValue><name>Aligned</name><description>Align bursts to start address LS bits. First burst alignment depends on FB bit</description><value>1</value></enumeratedValue></enumeratedValues> 21848 </field> 21849 <field> 21850 <name>MB</name> 21851 <description>Mixed burst</description> 21852 <bitOffset>26</bitOffset> 21853 <bitWidth>1</bitWidth> 21854 <enumeratedValues><name>MB</name><usage>read-write</usage><enumeratedValue><name>Normal</name><description>Fixed burst transfers (INCRx and SINGLE) for burst lengths of 16 and below</description><value>0</value></enumeratedValue><enumeratedValue><name>Mixed</name><description>If FB is low, start all bursts greater than 16 with INCR (undefined burst)</description><value>1</value></enumeratedValue></enumeratedValues> 21855 </field> 21856 </fields> 21857 </register> 21858 <register> 21859 <name>DMATPDR</name> 21860 <displayName>DMATPDR</displayName> 21861 <description>Ethernet DMA transmit poll demand 21862 register</description> 21863 <addressOffset>0x4</addressOffset> 21864 <size>0x20</size> 21865 <access>read-write</access> 21866 <resetValue>0x00000000</resetValue> 21867 <fields> 21868 <field> 21869 <name>TPD</name> 21870 <description>Transmit poll demand</description> 21871 <bitOffset>0</bitOffset> 21872 <bitWidth>32</bitWidth> 21873 <enumeratedValues><name>TPD</name><usage>read-write</usage><enumeratedValue><name>Poll</name><description>Poll the transmit descriptor list</description><value>0</value></enumeratedValue></enumeratedValues> 21874 </field> 21875 </fields> 21876 </register> 21877 <register> 21878 <name>DMARPDR</name> 21879 <displayName>DMARPDR</displayName> 21880 <description>EHERNET DMA receive poll demand 21881 register</description> 21882 <addressOffset>0x8</addressOffset> 21883 <size>0x20</size> 21884 <access>read-write</access> 21885 <resetValue>0x00000000</resetValue> 21886 <fields> 21887 <field> 21888 <name>RPD</name> 21889 <description>Receive poll demand</description> 21890 <bitOffset>0</bitOffset> 21891 <bitWidth>32</bitWidth> 21892 <enumeratedValues><name>RPD</name><usage>read-write</usage><enumeratedValue><name>Poll</name><description>Poll the receive descriptor list</description><value>0</value></enumeratedValue></enumeratedValues> 21893 </field> 21894 </fields> 21895 </register> 21896 <register> 21897 <name>DMARDLAR</name> 21898 <displayName>DMARDLAR</displayName> 21899 <description>Ethernet DMA receive descriptor list address 21900 register</description> 21901 <addressOffset>0xC</addressOffset> 21902 <size>0x20</size> 21903 <access>read-write</access> 21904 <resetValue>0x00000000</resetValue> 21905 <fields> 21906 <field> 21907 <name>SRL</name> 21908 <description>Start of receive list</description> 21909 <bitOffset>0</bitOffset> 21910 <bitWidth>32</bitWidth> 21911 </field> 21912 </fields> 21913 </register> 21914 <register> 21915 <name>DMATDLAR</name> 21916 <displayName>DMATDLAR</displayName> 21917 <description>Ethernet DMA transmit descriptor list 21918 address register</description> 21919 <addressOffset>0x10</addressOffset> 21920 <size>0x20</size> 21921 <access>read-write</access> 21922 <resetValue>0x00000000</resetValue> 21923 <fields> 21924 <field> 21925 <name>STL</name> 21926 <description>Start of transmit list</description> 21927 <bitOffset>0</bitOffset> 21928 <bitWidth>32</bitWidth> 21929 </field> 21930 </fields> 21931 </register> 21932 <register> 21933 <name>DMASR</name> 21934 <displayName>DMASR</displayName> 21935 <description>Ethernet DMA status register</description> 21936 <addressOffset>0x14</addressOffset> 21937 <size>0x20</size> 21938 <resetValue>0x00000000</resetValue> 21939 <fields> 21940 <field> 21941 <name>TS</name> 21942 <description>Transmit status</description> 21943 <bitOffset>0</bitOffset> 21944 <bitWidth>1</bitWidth> 21945 <access>read-write</access> 21946 </field> 21947 <field> 21948 <name>TPSS</name> 21949 <description>Transmit process stopped status</description> 21950 <bitOffset>1</bitOffset> 21951 <bitWidth>1</bitWidth> 21952 <access>read-write</access> 21953 </field> 21954 <field> 21955 <name>TBUS</name> 21956 <description>Transmit buffer unavailable status</description> 21957 <bitOffset>2</bitOffset> 21958 <bitWidth>1</bitWidth> 21959 <access>read-write</access> 21960 </field> 21961 <field> 21962 <name>TJTS</name> 21963 <description>Transmit jabber timeout status</description> 21964 <bitOffset>3</bitOffset> 21965 <bitWidth>1</bitWidth> 21966 <access>read-write</access> 21967 </field> 21968 <field> 21969 <name>ROS</name> 21970 <description>Receive overflow status</description> 21971 <bitOffset>4</bitOffset> 21972 <bitWidth>1</bitWidth> 21973 <access>read-write</access> 21974 </field> 21975 <field> 21976 <name>TUS</name> 21977 <description>Transmit underflow status</description> 21978 <bitOffset>5</bitOffset> 21979 <bitWidth>1</bitWidth> 21980 <access>read-write</access> 21981 </field> 21982 <field> 21983 <name>RS</name> 21984 <description>Receive status</description> 21985 <bitOffset>6</bitOffset> 21986 <bitWidth>1</bitWidth> 21987 <access>read-write</access> 21988 </field> 21989 <field> 21990 <name>RBUS</name> 21991 <description>Receive buffer unavailable status</description> 21992 <bitOffset>7</bitOffset> 21993 <bitWidth>1</bitWidth> 21994 <access>read-write</access> 21995 </field> 21996 <field> 21997 <name>RPSS</name> 21998 <description>Receive process stopped status</description> 21999 <bitOffset>8</bitOffset> 22000 <bitWidth>1</bitWidth> 22001 <access>read-write</access> 22002 </field> 22003 <field> 22004 <name>PWTS</name> 22005 <description>PWTS</description> 22006 <bitOffset>9</bitOffset> 22007 <bitWidth>1</bitWidth> 22008 <access>read-write</access> 22009 </field> 22010 <field> 22011 <name>ETS</name> 22012 <description>Early transmit status</description> 22013 <bitOffset>10</bitOffset> 22014 <bitWidth>1</bitWidth> 22015 <access>read-write</access> 22016 </field> 22017 <field> 22018 <name>FBES</name> 22019 <description>Fatal bus error status</description> 22020 <bitOffset>13</bitOffset> 22021 <bitWidth>1</bitWidth> 22022 <access>read-write</access> 22023 </field> 22024 <field> 22025 <name>ERS</name> 22026 <description>Early receive status</description> 22027 <bitOffset>14</bitOffset> 22028 <bitWidth>1</bitWidth> 22029 <access>read-write</access> 22030 </field> 22031 <field> 22032 <name>AIS</name> 22033 <description>Abnormal interrupt summary</description> 22034 <bitOffset>15</bitOffset> 22035 <bitWidth>1</bitWidth> 22036 <access>read-write</access> 22037 </field> 22038 <field> 22039 <name>NIS</name> 22040 <description>Normal interrupt summary</description> 22041 <bitOffset>16</bitOffset> 22042 <bitWidth>1</bitWidth> 22043 <access>read-write</access> 22044 </field> 22045 <field> 22046 <name>RPS</name> 22047 <description>Receive process state</description> 22048 <bitOffset>17</bitOffset> 22049 <bitWidth>3</bitWidth> 22050 <access>read-only</access> 22051 <enumeratedValues><name>RPS</name><usage>read-write</usage><enumeratedValue><name>Stopped</name><description>Stopped, reset or Stop Receive command issued</description><value>0</value></enumeratedValue><enumeratedValue><name>RunningFetching</name><description>Running, fetching receive transfer descriptor</description><value>1</value></enumeratedValue><enumeratedValue><name>RunningWaiting</name><description>Running, waiting for receive packet</description><value>3</value></enumeratedValue><enumeratedValue><name>Suspended</name><description>Suspended, receive descriptor unavailable</description><value>4</value></enumeratedValue><enumeratedValue><name>RunningWriting</name><description>Running, writing data to host memory buffer</description><value>7</value></enumeratedValue></enumeratedValues> 22052 </field> 22053 <field> 22054 <name>TPS</name> 22055 <description>Transmit process state</description> 22056 <bitOffset>20</bitOffset> 22057 <bitWidth>3</bitWidth> 22058 <access>read-only</access> 22059 <enumeratedValues><name>TPS</name><usage>read-write</usage><enumeratedValue><name>Stopped</name><description>Stopped, Reset or Stop Transmit command issued</description><value>0</value></enumeratedValue><enumeratedValue><name>RunningFetching</name><description>Running, fetching transmit transfer descriptor</description><value>1</value></enumeratedValue><enumeratedValue><name>RunningWaiting</name><description>Running, waiting for status</description><value>2</value></enumeratedValue><enumeratedValue><name>RunningReading</name><description>Running, reading data from host memory buffer</description><value>3</value></enumeratedValue><enumeratedValue><name>Suspended</name><description>Suspended, transmit descriptor unavailable or transmit buffer underflow</description><value>6</value></enumeratedValue><enumeratedValue><name>Running</name><description>Running, closing transmit descriptor</description><value>7</value></enumeratedValue></enumeratedValues> 22060 </field> 22061 <field> 22062 <name>EBS</name> 22063 <description>Error bits status</description> 22064 <bitOffset>23</bitOffset> 22065 <bitWidth>3</bitWidth> 22066 <access>read-only</access> 22067 </field> 22068 <field> 22069 <name>MMCS</name> 22070 <description>MMC status</description> 22071 <bitOffset>27</bitOffset> 22072 <bitWidth>1</bitWidth> 22073 <access>read-only</access> 22074 </field> 22075 <field> 22076 <name>PMTS</name> 22077 <description>PMT status</description> 22078 <bitOffset>28</bitOffset> 22079 <bitWidth>1</bitWidth> 22080 <access>read-only</access> 22081 </field> 22082 <field> 22083 <name>TSTS</name> 22084 <description>Time stamp trigger status</description> 22085 <bitOffset>29</bitOffset> 22086 <bitWidth>1</bitWidth> 22087 <access>read-only</access> 22088 </field> 22089 </fields> 22090 </register> 22091 <register> 22092 <name>DMAOMR</name> 22093 <displayName>DMAOMR</displayName> 22094 <description>Ethernet DMA operation mode 22095 register</description> 22096 <addressOffset>0x18</addressOffset> 22097 <size>0x20</size> 22098 <access>read-write</access> 22099 <resetValue>0x00000000</resetValue> 22100 <fields> 22101 <field> 22102 <name>SR</name> 22103 <description>Start/stop receive</description> 22104 <bitOffset>1</bitOffset> 22105 <bitWidth>1</bitWidth> 22106 <enumeratedValues><name>SR</name><usage>read-write</usage><enumeratedValue><name>Stopped</name><description>Reception is stopped after transfer of the current frame</description><value>0</value></enumeratedValue><enumeratedValue><name>Started</name><description>Reception is placed in the Running state</description><value>1</value></enumeratedValue></enumeratedValues> 22107 </field> 22108 <field> 22109 <name>OSF</name> 22110 <description>Operate on second frame</description> 22111 <bitOffset>2</bitOffset> 22112 <bitWidth>1</bitWidth> 22113 </field> 22114 <field> 22115 <name>RTC</name> 22116 <description>Receive threshold control</description> 22117 <bitOffset>3</bitOffset> 22118 <bitWidth>2</bitWidth> 22119 <enumeratedValues><name>RTC</name><usage>read-write</usage><enumeratedValue><name>RTC64</name><description>64 bytes</description><value>0</value></enumeratedValue><enumeratedValue><name>RTC32</name><description>32 bytes</description><value>1</value></enumeratedValue><enumeratedValue><name>RTC96</name><description>96 bytes</description><value>2</value></enumeratedValue><enumeratedValue><name>RTC128</name><description>128 bytes</description><value>3</value></enumeratedValue></enumeratedValues> 22120 </field> 22121 <field> 22122 <name>FUGF</name> 22123 <description>Forward undersized good frames</description> 22124 <bitOffset>6</bitOffset> 22125 <bitWidth>1</bitWidth> 22126 <enumeratedValues><name>FUGF</name><usage>read-write</usage><enumeratedValue><name>Drop</name><description>Rx FIFO drops all frames of less than 64 bytes</description><value>0</value></enumeratedValue><enumeratedValue><name>Forward</name><description>Rx FIFO forwards undersized frames</description><value>1</value></enumeratedValue></enumeratedValues> 22127 </field> 22128 <field> 22129 <name>FEF</name> 22130 <description>Forward error frames</description> 22131 <bitOffset>7</bitOffset> 22132 <bitWidth>1</bitWidth> 22133 <enumeratedValues><name>FEF</name><usage>read-write</usage><enumeratedValue><name>Drop</name><description>Rx FIFO drops frames with error status</description><value>0</value></enumeratedValue><enumeratedValue><name>Forward</name><description>All frames except runt error frames are forwarded to the DMA</description><value>1</value></enumeratedValue></enumeratedValues> 22134 </field> 22135 <field> 22136 <name>ST</name> 22137 <description>Start/stop transmission</description> 22138 <bitOffset>13</bitOffset> 22139 <bitWidth>1</bitWidth> 22140 <enumeratedValues><name>ST</name><usage>read-write</usage><enumeratedValue><name>Stopped</name><description>Transmission is placed in the Stopped state</description><value>0</value></enumeratedValue><enumeratedValue><name>Started</name><description>Transmission is placed in Running state</description><value>1</value></enumeratedValue></enumeratedValues> 22141 </field> 22142 <field> 22143 <name>TTC</name> 22144 <description>Transmit threshold control</description> 22145 <bitOffset>14</bitOffset> 22146 <bitWidth>3</bitWidth> 22147 <enumeratedValues><name>TTC</name><usage>read-write</usage><enumeratedValue><name>TTC64</name><description>64 bytes</description><value>0</value></enumeratedValue><enumeratedValue><name>TTC128</name><description>128 bytes</description><value>1</value></enumeratedValue><enumeratedValue><name>TTC192</name><description>192 bytes</description><value>2</value></enumeratedValue><enumeratedValue><name>TTC256</name><description>256 bytes</description><value>3</value></enumeratedValue><enumeratedValue><name>TTC40</name><description>40 bytes</description><value>4</value></enumeratedValue><enumeratedValue><name>TTC32</name><description>32 bytes</description><value>5</value></enumeratedValue><enumeratedValue><name>TTC24</name><description>24 bytes</description><value>6</value></enumeratedValue><enumeratedValue><name>TTC16</name><description>16 bytes</description><value>7</value></enumeratedValue></enumeratedValues> 22148 </field> 22149 <field> 22150 <name>FTF</name> 22151 <description>Flush transmit FIFO</description> 22152 <bitOffset>20</bitOffset> 22153 <bitWidth>1</bitWidth> 22154 <enumeratedValues><name>FTF</name><usage>read-write</usage><enumeratedValue><name>Flush</name><description>Transmit FIFO controller logic is reset to its default values. Cleared automatically</description><value>1</value></enumeratedValue></enumeratedValues> 22155 </field> 22156 <field> 22157 <name>TSF</name> 22158 <description>Transmit store and forward</description> 22159 <bitOffset>21</bitOffset> 22160 <bitWidth>1</bitWidth> 22161 <enumeratedValues><name>TSF</name><usage>read-write</usage><enumeratedValue><name>CutThrough</name><description>Transmission starts when the frame size in the Tx FIFO exceeds TTC threshold</description><value>0</value></enumeratedValue><enumeratedValue><name>StoreForward</name><description>Transmission starts when a full frame is in the Tx FIFO</description><value>1</value></enumeratedValue></enumeratedValues> 22162 </field> 22163 <field> 22164 <name>DFRF</name> 22165 <description>Disable flushing of received frames</description> 22166 <bitOffset>24</bitOffset> 22167 <bitWidth>1</bitWidth> 22168 </field> 22169 <field> 22170 <name>RSF</name> 22171 <description>Receive store and forward</description> 22172 <bitOffset>25</bitOffset> 22173 <bitWidth>1</bitWidth> 22174 <enumeratedValues><name>RSF</name><usage>read-write</usage><enumeratedValue><name>CutThrough</name><description>Rx FIFO operates in cut-through mode, subject to RTC bits</description><value>0</value></enumeratedValue><enumeratedValue><name>StoreForward</name><description>Frames are read from Rx FIFO after complete frame has been written</description><value>1</value></enumeratedValue></enumeratedValues> 22175 </field> 22176 <field> 22177 <name>DTCEFD</name> 22178 <description>Dropping of TCP/IP checksum error frames disable</description> 22179 <bitOffset>26</bitOffset> 22180 <bitWidth>1</bitWidth> 22181 <enumeratedValues><name>DTCEFD</name><usage>read-write</usage><enumeratedValue><name>Enabled</name><description>Drop frames with errors only in the receive checksum offload engine</description><value>0</value></enumeratedValue><enumeratedValue><name>Disabled</name><description>Do not drop frames that only have errors in the receive checksum offload engine</description><value>1</value></enumeratedValue></enumeratedValues> 22182 </field> 22183 </fields> 22184 </register> 22185 <register> 22186 <name>DMAIER</name> 22187 <displayName>DMAIER</displayName> 22188 <description>Ethernet DMA interrupt enable 22189 register</description> 22190 <addressOffset>0x1C</addressOffset> 22191 <size>0x20</size> 22192 <access>read-write</access> 22193 <resetValue>0x00000000</resetValue> 22194 <fields> 22195 <field> 22196 <name>TIE</name> 22197 <description>Transmit interrupt enable</description> 22198 <bitOffset>0</bitOffset> 22199 <bitWidth>1</bitWidth> 22200 </field> 22201 <field> 22202 <name>TPSIE</name> 22203 <description>Transmit process stopped interrupt enable</description> 22204 <bitOffset>1</bitOffset> 22205 <bitWidth>1</bitWidth> 22206 </field> 22207 <field> 22208 <name>TBUIE</name> 22209 <description>Transmit buffer unavailable interrupt enable</description> 22210 <bitOffset>2</bitOffset> 22211 <bitWidth>1</bitWidth> 22212 </field> 22213 <field> 22214 <name>TJTIE</name> 22215 <description>Transmit jabber timeout interrupt enable</description> 22216 <bitOffset>3</bitOffset> 22217 <bitWidth>1</bitWidth> 22218 </field> 22219 <field> 22220 <name>ROIE</name> 22221 <description>Receive overflow interrupt enable</description> 22222 <bitOffset>4</bitOffset> 22223 <bitWidth>1</bitWidth> 22224 </field> 22225 <field> 22226 <name>TUIE</name> 22227 <description>Transmit underflow interrupt enable</description> 22228 <bitOffset>5</bitOffset> 22229 <bitWidth>1</bitWidth> 22230 </field> 22231 <field> 22232 <name>RIE</name> 22233 <description>Receive interrupt enable</description> 22234 <bitOffset>6</bitOffset> 22235 <bitWidth>1</bitWidth> 22236 </field> 22237 <field> 22238 <name>RBUIE</name> 22239 <description>Receive buffer unavailable interrupt enable</description> 22240 <bitOffset>7</bitOffset> 22241 <bitWidth>1</bitWidth> 22242 </field> 22243 <field> 22244 <name>RPSIE</name> 22245 <description>Receive process stopped interrupt enable</description> 22246 <bitOffset>8</bitOffset> 22247 <bitWidth>1</bitWidth> 22248 </field> 22249 <field> 22250 <name>RWTIE</name> 22251 <description>Receive watchdog timeout interrupt enable</description> 22252 <bitOffset>9</bitOffset> 22253 <bitWidth>1</bitWidth> 22254 </field> 22255 <field> 22256 <name>ETIE</name> 22257 <description>Early transmit interrupt enable</description> 22258 <bitOffset>10</bitOffset> 22259 <bitWidth>1</bitWidth> 22260 </field> 22261 <field> 22262 <name>FBEIE</name> 22263 <description>Fatal bus error interrupt enable</description> 22264 <bitOffset>13</bitOffset> 22265 <bitWidth>1</bitWidth> 22266 </field> 22267 <field> 22268 <name>ERIE</name> 22269 <description>Early receive interrupt enable</description> 22270 <bitOffset>14</bitOffset> 22271 <bitWidth>1</bitWidth> 22272 </field> 22273 <field> 22274 <name>AISE</name> 22275 <description>Abnormal interrupt summary enable</description> 22276 <bitOffset>15</bitOffset> 22277 <bitWidth>1</bitWidth> 22278 </field> 22279 <field> 22280 <name>NISE</name> 22281 <description>Normal interrupt summary enable</description> 22282 <bitOffset>16</bitOffset> 22283 <bitWidth>1</bitWidth> 22284 </field> 22285 </fields> 22286 </register> 22287 <register> 22288 <name>DMAMFBOCR</name> 22289 <displayName>DMAMFBOCR</displayName> 22290 <description>Ethernet DMA missed frame and buffer 22291 overflow counter register</description> 22292 <addressOffset>0x20</addressOffset> 22293 <size>0x20</size> 22294 <access>read-write</access> 22295 <resetValue>0x00000000</resetValue> 22296 <fields> 22297 <field> 22298 <name>MFC</name> 22299 <description>Missed frames by the controller</description> 22300 <bitOffset>0</bitOffset> 22301 <bitWidth>16</bitWidth> 22302 </field> 22303 <field> 22304 <name>OMFC</name> 22305 <description>Overflow bit for missed frame counter</description> 22306 <bitOffset>16</bitOffset> 22307 <bitWidth>1</bitWidth> 22308 </field> 22309 <field> 22310 <name>MFA</name> 22311 <description>Missed frames by the application</description> 22312 <bitOffset>17</bitOffset> 22313 <bitWidth>11</bitWidth> 22314 </field> 22315 <field> 22316 <name>OFOC</name> 22317 <description>Overflow bit for FIFO overflow counter</description> 22318 <bitOffset>28</bitOffset> 22319 <bitWidth>1</bitWidth> 22320 </field> 22321 </fields> 22322 </register> 22323 <register> 22324 <name>DMARSWTR</name> 22325 <displayName>DMARSWTR</displayName> 22326 <description>Ethernet DMA receive status watchdog timer 22327 register</description> 22328 <addressOffset>0x24</addressOffset> 22329 <size>0x20</size> 22330 <access>read-write</access> 22331 <resetValue>0x00000000</resetValue> 22332 <fields> 22333 <field> 22334 <name>RSWTC</name> 22335 <description>Receive status watchdog timer count</description> 22336 <bitOffset>0</bitOffset> 22337 <bitWidth>8</bitWidth> 22338 <writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint> 22339 </field> 22340 </fields> 22341 </register> 22342 <register> 22343 <name>DMACHTDR</name> 22344 <displayName>DMACHTDR</displayName> 22345 <description>Ethernet DMA current host transmit 22346 descriptor register</description> 22347 <addressOffset>0x48</addressOffset> 22348 <size>0x20</size> 22349 <access>read-only</access> 22350 <resetValue>0x00000000</resetValue> 22351 <fields> 22352 <field> 22353 <name>HTDAP</name> 22354 <description>Host transmit descriptor address pointer</description> 22355 <bitOffset>0</bitOffset> 22356 <bitWidth>32</bitWidth> 22357 </field> 22358 </fields> 22359 </register> 22360 <register> 22361 <name>DMACHRDR</name> 22362 <displayName>DMACHRDR</displayName> 22363 <description>Ethernet DMA current host receive descriptor 22364 register</description> 22365 <addressOffset>0x4C</addressOffset> 22366 <size>0x20</size> 22367 <access>read-only</access> 22368 <resetValue>0x00000000</resetValue> 22369 <fields> 22370 <field> 22371 <name>HRDAP</name> 22372 <description>Host receive descriptor address pointer</description> 22373 <bitOffset>0</bitOffset> 22374 <bitWidth>32</bitWidth> 22375 </field> 22376 </fields> 22377 </register> 22378 <register> 22379 <name>DMACHTBAR</name> 22380 <displayName>DMACHTBAR</displayName> 22381 <description>Ethernet DMA current host transmit buffer 22382 address register</description> 22383 <addressOffset>0x50</addressOffset> 22384 <size>0x20</size> 22385 <access>read-only</access> 22386 <resetValue>0x00000000</resetValue> 22387 <fields> 22388 <field> 22389 <name>HTBAP</name> 22390 <description>Host transmit buffer address pointer</description> 22391 <bitOffset>0</bitOffset> 22392 <bitWidth>32</bitWidth> 22393 </field> 22394 </fields> 22395 </register> 22396 <register> 22397 <name>DMACHRBAR</name> 22398 <displayName>DMACHRBAR</displayName> 22399 <description>Ethernet DMA current host receive buffer 22400 address register</description> 22401 <addressOffset>0x54</addressOffset> 22402 <size>0x20</size> 22403 <access>read-only</access> 22404 <resetValue>0x00000000</resetValue> 22405 <fields> 22406 <field> 22407 <name>HRBAP</name> 22408 <description>Host receive buffer address pointer</description> 22409 <bitOffset>0</bitOffset> 22410 <bitWidth>32</bitWidth> 22411 </field> 22412 </fields> 22413 </register> 22414 </registers> 22415 </peripheral> 22416 <peripheral> 22417 <name>CRC</name> 22418 <description>Cryptographic processor</description> 22419 <groupName>CRC</groupName> 22420 <baseAddress>0x40023000</baseAddress> 22421 <addressBlock> 22422 <offset>0x0</offset> 22423 <size>0x400</size> 22424 <usage>registers</usage> 22425 </addressBlock> 22426 <registers> 22427 <register> 22428 <name>DR</name> 22429 <displayName>DR</displayName> 22430 <description>Data register</description> 22431 <addressOffset>0x0</addressOffset> 22432 <size>0x20</size> 22433 <access>read-write</access> 22434 <resetValue>0xFFFFFFFF</resetValue> 22435 <fields> 22436 <field> 22437 <name>DR</name> 22438 <description>Data Register</description> 22439 <bitOffset>0</bitOffset> 22440 <bitWidth>32</bitWidth> 22441 <writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint> 22442 </field> 22443 </fields> 22444 </register> 22445 <register> 22446 <name>IDR</name> 22447 <displayName>IDR</displayName> 22448 <description>Independent Data register</description> 22449 <addressOffset>0x4</addressOffset> 22450 <size>0x20</size> 22451 <access>read-write</access> 22452 <resetValue>0x00000000</resetValue> 22453 <fields> 22454 <field> 22455 <name>IDR</name> 22456 <description>Independent Data register</description> 22457 <bitOffset>0</bitOffset> 22458 <bitWidth>8</bitWidth> 22459 <writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint> 22460 </field> 22461 </fields> 22462 </register> 22463 <register> 22464 <name>CR</name> 22465 <displayName>CR</displayName> 22466 <description>Control register</description> 22467 <addressOffset>0x8</addressOffset> 22468 <size>0x20</size> 22469 <access>write-only</access> 22470 <resetValue>0x00000000</resetValue> 22471 <fields> 22472 <field> 22473 <name>RESET</name> 22474 <description>Control regidter</description> 22475 <bitOffset>0</bitOffset> 22476 <bitWidth>1</bitWidth> 22477 <enumeratedValues><name>RESETW</name><usage>write</usage><enumeratedValue><name>Reset</name><description>Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF</description><value>1</value></enumeratedValue></enumeratedValues> 22478 </field> 22479 </fields> 22480 </register> 22481 </registers> 22482 </peripheral> 22483 <peripheral> 22484 <name>OTG_FS_GLOBAL</name> 22485 <description>USB on the go full speed</description> 22486 <groupName>USB_OTG_FS</groupName> 22487 <baseAddress>0x50000000</baseAddress> 22488 <addressBlock> 22489 <offset>0x0</offset> 22490 <size>0x400</size> 22491 <usage>registers</usage> 22492 </addressBlock> 22493 <interrupt> 22494 <name>OTG_FS_WKUP</name> 22495 <description>USB On-The-Go FS Wakeup through EXTI line 22496 interrupt</description> 22497 <value>42</value> 22498 </interrupt> 22499 <interrupt> 22500 <name>OTG_FS</name> 22501 <description>USB On The Go FS global 22502 interrupt</description> 22503 <value>67</value> 22504 </interrupt> 22505 <registers> 22506 <register> 22507 <name>GOTGCTL</name> 22508 <displayName>GOTGCTL</displayName> 22509 <description>OTG_FS control and status register 22510 (OTG_FS_GOTGCTL)</description> 22511 <addressOffset>0x0</addressOffset> 22512 <size>0x20</size> 22513 <resetValue>0x00000800</resetValue> 22514 <fields> 22515 <field> 22516 <name>SRQSCS</name> 22517 <description>Session request success</description> 22518 <bitOffset>0</bitOffset> 22519 <bitWidth>1</bitWidth> 22520 <access>read-only</access> 22521 </field> 22522 <field> 22523 <name>SRQ</name> 22524 <description>Session request</description> 22525 <bitOffset>1</bitOffset> 22526 <bitWidth>1</bitWidth> 22527 <access>read-write</access> 22528 </field> 22529 <field> 22530 <name>HNGSCS</name> 22531 <description>Host negotiation success</description> 22532 <bitOffset>8</bitOffset> 22533 <bitWidth>1</bitWidth> 22534 <access>read-only</access> 22535 </field> 22536 <field> 22537 <name>HNPRQ</name> 22538 <description>HNP request</description> 22539 <bitOffset>9</bitOffset> 22540 <bitWidth>1</bitWidth> 22541 <access>read-write</access> 22542 </field> 22543 <field> 22544 <name>HSHNPEN</name> 22545 <description>Host set HNP enable</description> 22546 <bitOffset>10</bitOffset> 22547 <bitWidth>1</bitWidth> 22548 <access>read-write</access> 22549 </field> 22550 <field> 22551 <name>DHNPEN</name> 22552 <description>Device HNP enabled</description> 22553 <bitOffset>11</bitOffset> 22554 <bitWidth>1</bitWidth> 22555 <access>read-write</access> 22556 </field> 22557 <field> 22558 <name>CIDSTS</name> 22559 <description>Connector ID status</description> 22560 <bitOffset>16</bitOffset> 22561 <bitWidth>1</bitWidth> 22562 <access>read-only</access> 22563 </field> 22564 <field> 22565 <name>DBCT</name> 22566 <description>Long/short debounce time</description> 22567 <bitOffset>17</bitOffset> 22568 <bitWidth>1</bitWidth> 22569 <access>read-only</access> 22570 </field> 22571 <field> 22572 <name>ASVLD</name> 22573 <description>A-session valid</description> 22574 <bitOffset>18</bitOffset> 22575 <bitWidth>1</bitWidth> 22576 <access>read-only</access> 22577 </field> 22578 <field> 22579 <name>BSVLD</name> 22580 <description>B-session valid</description> 22581 <bitOffset>19</bitOffset> 22582 <bitWidth>1</bitWidth> 22583 <access>read-only</access> 22584 </field> 22585 </fields> 22586 </register> 22587 <register> 22588 <name>GOTGINT</name> 22589 <displayName>GOTGINT</displayName> 22590 <description>OTG_FS interrupt register 22591 (OTG_FS_GOTGINT)</description> 22592 <addressOffset>0x4</addressOffset> 22593 <size>0x20</size> 22594 <access>read-write</access> 22595 <resetValue>0x00000000</resetValue> 22596 <fields> 22597 <field> 22598 <name>SEDET</name> 22599 <description>Session end detected</description> 22600 <bitOffset>2</bitOffset> 22601 <bitWidth>1</bitWidth> 22602 </field> 22603 <field> 22604 <name>SRSSCHG</name> 22605 <description>Session request success status 22606 change</description> 22607 <bitOffset>8</bitOffset> 22608 <bitWidth>1</bitWidth> 22609 </field> 22610 <field> 22611 <name>HNSSCHG</name> 22612 <description>Host negotiation success status 22613 change</description> 22614 <bitOffset>9</bitOffset> 22615 <bitWidth>1</bitWidth> 22616 </field> 22617 <field> 22618 <name>HNGDET</name> 22619 <description>Host negotiation detected</description> 22620 <bitOffset>17</bitOffset> 22621 <bitWidth>1</bitWidth> 22622 </field> 22623 <field> 22624 <name>ADTOCHG</name> 22625 <description>A-device timeout change</description> 22626 <bitOffset>18</bitOffset> 22627 <bitWidth>1</bitWidth> 22628 </field> 22629 <field> 22630 <name>DBCDNE</name> 22631 <description>Debounce done</description> 22632 <bitOffset>19</bitOffset> 22633 <bitWidth>1</bitWidth> 22634 </field> 22635 </fields> 22636 </register> 22637 <register> 22638 <name>GAHBCFG</name> 22639 <displayName>GAHBCFG</displayName> 22640 <description>OTG_FS AHB configuration register 22641 (OTG_FS_GAHBCFG)</description> 22642 <addressOffset>0x8</addressOffset> 22643 <size>0x20</size> 22644 <access>read-write</access> 22645 <resetValue>0x00000000</resetValue> 22646 <fields> 22647 <field> 22648 <name>GINT</name> 22649 <description>Global interrupt mask</description> 22650 <bitOffset>0</bitOffset> 22651 <bitWidth>1</bitWidth> 22652 </field> 22653 <field> 22654 <name>TXFELVL</name> 22655 <description>TxFIFO empty level</description> 22656 <bitOffset>7</bitOffset> 22657 <bitWidth>1</bitWidth> 22658 </field> 22659 <field> 22660 <name>PTXFELVL</name> 22661 <description>Periodic TxFIFO empty 22662 level</description> 22663 <bitOffset>8</bitOffset> 22664 <bitWidth>1</bitWidth> 22665 </field> 22666 </fields> 22667 </register> 22668 <register> 22669 <name>GUSBCFG</name> 22670 <displayName>GUSBCFG</displayName> 22671 <description>OTG_FS USB configuration register 22672 (OTG_FS_GUSBCFG)</description> 22673 <addressOffset>0xC</addressOffset> 22674 <size>0x20</size> 22675 <resetValue>0x00000A00</resetValue> 22676 <fields> 22677 <field> 22678 <name>TOCAL</name> 22679 <description>FS timeout calibration</description> 22680 <bitOffset>0</bitOffset> 22681 <bitWidth>3</bitWidth> 22682 <access>read-write</access> 22683 </field> 22684 <field> 22685 <name>PHYSEL</name> 22686 <description>Full Speed serial transceiver 22687 select</description> 22688 <bitOffset>6</bitOffset> 22689 <bitWidth>1</bitWidth> 22690 <access>write-only</access> 22691 </field> 22692 <field> 22693 <name>SRPCAP</name> 22694 <description>SRP-capable</description> 22695 <bitOffset>8</bitOffset> 22696 <bitWidth>1</bitWidth> 22697 <access>read-write</access> 22698 </field> 22699 <field> 22700 <name>HNPCAP</name> 22701 <description>HNP-capable</description> 22702 <bitOffset>9</bitOffset> 22703 <bitWidth>1</bitWidth> 22704 <access>read-write</access> 22705 </field> 22706 <field> 22707 <name>TRDT</name> 22708 <description>USB turnaround time</description> 22709 <bitOffset>10</bitOffset> 22710 <bitWidth>4</bitWidth> 22711 <access>read-write</access> 22712 </field> 22713 <field> 22714 <name>FHMOD</name> 22715 <description>Force host mode</description> 22716 <bitOffset>29</bitOffset> 22717 <bitWidth>1</bitWidth> 22718 <access>read-write</access> 22719 </field> 22720 <field> 22721 <name>FDMOD</name> 22722 <description>Force device mode</description> 22723 <bitOffset>30</bitOffset> 22724 <bitWidth>1</bitWidth> 22725 <access>read-write</access> 22726 </field> 22727 <field> 22728 <name>CTXPKT</name> 22729 <description>Corrupt Tx packet</description> 22730 <bitOffset>31</bitOffset> 22731 <bitWidth>1</bitWidth> 22732 <access>read-write</access> 22733 </field> 22734 </fields> 22735 </register> 22736 <register> 22737 <name>GRSTCTL</name> 22738 <displayName>GRSTCTL</displayName> 22739 <description>OTG_FS reset register 22740 (OTG_FS_GRSTCTL)</description> 22741 <addressOffset>0x10</addressOffset> 22742 <size>0x20</size> 22743 <resetValue>0x20000000</resetValue> 22744 <fields> 22745 <field> 22746 <name>CSRST</name> 22747 <description>Core soft reset</description> 22748 <bitOffset>0</bitOffset> 22749 <bitWidth>1</bitWidth> 22750 <access>read-write</access> 22751 </field> 22752 <field> 22753 <name>HSRST</name> 22754 <description>HCLK soft reset</description> 22755 <bitOffset>1</bitOffset> 22756 <bitWidth>1</bitWidth> 22757 <access>read-write</access> 22758 </field> 22759 <field> 22760 <name>FCRST</name> 22761 <description>Host frame counter reset</description> 22762 <bitOffset>2</bitOffset> 22763 <bitWidth>1</bitWidth> 22764 <access>read-write</access> 22765 </field> 22766 <field> 22767 <name>RXFFLSH</name> 22768 <description>RxFIFO flush</description> 22769 <bitOffset>4</bitOffset> 22770 <bitWidth>1</bitWidth> 22771 <access>read-write</access> 22772 </field> 22773 <field> 22774 <name>TXFFLSH</name> 22775 <description>TxFIFO flush</description> 22776 <bitOffset>5</bitOffset> 22777 <bitWidth>1</bitWidth> 22778 <access>read-write</access> 22779 </field> 22780 <field> 22781 <name>TXFNUM</name> 22782 <description>TxFIFO number</description> 22783 <bitOffset>6</bitOffset> 22784 <bitWidth>5</bitWidth> 22785 <access>read-write</access> 22786 </field> 22787 <field> 22788 <name>AHBIDL</name> 22789 <description>AHB master idle</description> 22790 <bitOffset>31</bitOffset> 22791 <bitWidth>1</bitWidth> 22792 <access>read-only</access> 22793 </field> 22794 </fields> 22795 </register> 22796 <register> 22797 <name>GINTSTS</name> 22798 <displayName>GINTSTS</displayName> 22799 <description>OTG_FS core interrupt register 22800 (OTG_FS_GINTSTS)</description> 22801 <addressOffset>0x14</addressOffset> 22802 <size>0x20</size> 22803 <resetValue>0x04000020</resetValue> 22804 <fields> 22805 <field> 22806 <name>CMOD</name> 22807 <description>Current mode of operation</description> 22808 <bitOffset>0</bitOffset> 22809 <bitWidth>1</bitWidth> 22810 <access>read-only</access> 22811 </field> 22812 <field> 22813 <name>MMIS</name> 22814 <description>Mode mismatch interrupt</description> 22815 <bitOffset>1</bitOffset> 22816 <bitWidth>1</bitWidth> 22817 <access>read-write</access> 22818 </field> 22819 <field> 22820 <name>OTGINT</name> 22821 <description>OTG interrupt</description> 22822 <bitOffset>2</bitOffset> 22823 <bitWidth>1</bitWidth> 22824 <access>read-only</access> 22825 </field> 22826 <field> 22827 <name>SOF</name> 22828 <description>Start of frame</description> 22829 <bitOffset>3</bitOffset> 22830 <bitWidth>1</bitWidth> 22831 <access>read-write</access> 22832 </field> 22833 <field> 22834 <name>RXFLVL</name> 22835 <description>RxFIFO non-empty</description> 22836 <bitOffset>4</bitOffset> 22837 <bitWidth>1</bitWidth> 22838 <access>read-only</access> 22839 </field> 22840 <field> 22841 <name>NPTXFE</name> 22842 <description>Non-periodic TxFIFO empty</description> 22843 <bitOffset>5</bitOffset> 22844 <bitWidth>1</bitWidth> 22845 <access>read-only</access> 22846 </field> 22847 <field> 22848 <name>GINAKEFF</name> 22849 <description>Global IN non-periodic NAK 22850 effective</description> 22851 <bitOffset>6</bitOffset> 22852 <bitWidth>1</bitWidth> 22853 <access>read-only</access> 22854 </field> 22855 <field> 22856 <name>GOUTNAKEFF</name> 22857 <description>Global OUT NAK effective</description> 22858 <bitOffset>7</bitOffset> 22859 <bitWidth>1</bitWidth> 22860 <access>read-only</access> 22861 </field> 22862 <field> 22863 <name>ESUSP</name> 22864 <description>Early suspend</description> 22865 <bitOffset>10</bitOffset> 22866 <bitWidth>1</bitWidth> 22867 <access>read-write</access> 22868 </field> 22869 <field> 22870 <name>USBSUSP</name> 22871 <description>USB suspend</description> 22872 <bitOffset>11</bitOffset> 22873 <bitWidth>1</bitWidth> 22874 <access>read-write</access> 22875 </field> 22876 <field> 22877 <name>USBRST</name> 22878 <description>USB reset</description> 22879 <bitOffset>12</bitOffset> 22880 <bitWidth>1</bitWidth> 22881 <access>read-write</access> 22882 </field> 22883 <field> 22884 <name>ENUMDNE</name> 22885 <description>Enumeration done</description> 22886 <bitOffset>13</bitOffset> 22887 <bitWidth>1</bitWidth> 22888 <access>read-write</access> 22889 </field> 22890 <field> 22891 <name>ISOODRP</name> 22892 <description>Isochronous OUT packet dropped 22893 interrupt</description> 22894 <bitOffset>14</bitOffset> 22895 <bitWidth>1</bitWidth> 22896 <access>read-write</access> 22897 </field> 22898 <field> 22899 <name>EOPF</name> 22900 <description>End of periodic frame 22901 interrupt</description> 22902 <bitOffset>15</bitOffset> 22903 <bitWidth>1</bitWidth> 22904 <access>read-write</access> 22905 </field> 22906 <field> 22907 <name>IEPINT</name> 22908 <description>IN endpoint interrupt</description> 22909 <bitOffset>18</bitOffset> 22910 <bitWidth>1</bitWidth> 22911 <access>read-only</access> 22912 </field> 22913 <field> 22914 <name>OEPINT</name> 22915 <description>OUT endpoint interrupt</description> 22916 <bitOffset>19</bitOffset> 22917 <bitWidth>1</bitWidth> 22918 <access>read-only</access> 22919 </field> 22920 <field> 22921 <name>IISOIXFR</name> 22922 <description>Incomplete isochronous IN 22923 transfer</description> 22924 <bitOffset>20</bitOffset> 22925 <bitWidth>1</bitWidth> 22926 <access>read-write</access> 22927 </field> 22928 <field> 22929 <name>IPXFR_INCOMPISOOUT</name> 22930 <description>Incomplete periodic transfer(Host 22931 mode)/Incomplete isochronous OUT transfer(Device 22932 mode)</description> 22933 <bitOffset>21</bitOffset> 22934 <bitWidth>1</bitWidth> 22935 <access>read-write</access> 22936 </field> 22937 <field> 22938 <name>HPRTINT</name> 22939 <description>Host port interrupt</description> 22940 <bitOffset>24</bitOffset> 22941 <bitWidth>1</bitWidth> 22942 <access>read-only</access> 22943 </field> 22944 <field> 22945 <name>HCINT</name> 22946 <description>Host channels interrupt</description> 22947 <bitOffset>25</bitOffset> 22948 <bitWidth>1</bitWidth> 22949 <access>read-only</access> 22950 </field> 22951 <field> 22952 <name>PTXFE</name> 22953 <description>Periodic TxFIFO empty</description> 22954 <bitOffset>26</bitOffset> 22955 <bitWidth>1</bitWidth> 22956 <access>read-only</access> 22957 </field> 22958 <field> 22959 <name>CIDSCHG</name> 22960 <description>Connector ID status change</description> 22961 <bitOffset>28</bitOffset> 22962 <bitWidth>1</bitWidth> 22963 <access>read-write</access> 22964 </field> 22965 <field> 22966 <name>DISCINT</name> 22967 <description>Disconnect detected 22968 interrupt</description> 22969 <bitOffset>29</bitOffset> 22970 <bitWidth>1</bitWidth> 22971 <access>read-write</access> 22972 </field> 22973 <field> 22974 <name>SRQINT</name> 22975 <description>Session request/new session detected 22976 interrupt</description> 22977 <bitOffset>30</bitOffset> 22978 <bitWidth>1</bitWidth> 22979 <access>read-write</access> 22980 </field> 22981 <field> 22982 <name>WKUPINT</name> 22983 <description>Resume/remote wakeup detected 22984 interrupt</description> 22985 <bitOffset>31</bitOffset> 22986 <bitWidth>1</bitWidth> 22987 <access>read-write</access> 22988 </field> 22989 </fields> 22990 </register> 22991 <register> 22992 <name>GINTMSK</name> 22993 <displayName>GINTMSK</displayName> 22994 <description>OTG_FS interrupt mask register 22995 (OTG_FS_GINTMSK)</description> 22996 <addressOffset>0x18</addressOffset> 22997 <size>0x20</size> 22998 <resetValue>0x00000000</resetValue> 22999 <fields> 23000 <field> 23001 <name>MMISM</name> 23002 <description>Mode mismatch interrupt 23003 mask</description> 23004 <bitOffset>1</bitOffset> 23005 <bitWidth>1</bitWidth> 23006 <access>read-write</access> 23007 </field> 23008 <field> 23009 <name>OTGINT</name> 23010 <description>OTG interrupt mask</description> 23011 <bitOffset>2</bitOffset> 23012 <bitWidth>1</bitWidth> 23013 <access>read-write</access> 23014 </field> 23015 <field> 23016 <name>SOFM</name> 23017 <description>Start of frame mask</description> 23018 <bitOffset>3</bitOffset> 23019 <bitWidth>1</bitWidth> 23020 <access>read-write</access> 23021 </field> 23022 <field> 23023 <name>RXFLVLM</name> 23024 <description>Receive FIFO non-empty 23025 mask</description> 23026 <bitOffset>4</bitOffset> 23027 <bitWidth>1</bitWidth> 23028 <access>read-write</access> 23029 </field> 23030 <field> 23031 <name>NPTXFEM</name> 23032 <description>Non-periodic TxFIFO empty 23033 mask</description> 23034 <bitOffset>5</bitOffset> 23035 <bitWidth>1</bitWidth> 23036 <access>read-write</access> 23037 </field> 23038 <field> 23039 <name>GINAKEFFM</name> 23040 <description>Global non-periodic IN NAK effective 23041 mask</description> 23042 <bitOffset>6</bitOffset> 23043 <bitWidth>1</bitWidth> 23044 <access>read-write</access> 23045 </field> 23046 <field> 23047 <name>GONAKEFFM</name> 23048 <description>Global OUT NAK effective 23049 mask</description> 23050 <bitOffset>7</bitOffset> 23051 <bitWidth>1</bitWidth> 23052 <access>read-write</access> 23053 </field> 23054 <field> 23055 <name>ESUSPM</name> 23056 <description>Early suspend mask</description> 23057 <bitOffset>10</bitOffset> 23058 <bitWidth>1</bitWidth> 23059 <access>read-write</access> 23060 </field> 23061 <field> 23062 <name>USBSUSPM</name> 23063 <description>USB suspend mask</description> 23064 <bitOffset>11</bitOffset> 23065 <bitWidth>1</bitWidth> 23066 <access>read-write</access> 23067 </field> 23068 <field> 23069 <name>USBRST</name> 23070 <description>USB reset mask</description> 23071 <bitOffset>12</bitOffset> 23072 <bitWidth>1</bitWidth> 23073 <access>read-write</access> 23074 </field> 23075 <field> 23076 <name>ENUMDNEM</name> 23077 <description>Enumeration done mask</description> 23078 <bitOffset>13</bitOffset> 23079 <bitWidth>1</bitWidth> 23080 <access>read-write</access> 23081 </field> 23082 <field> 23083 <name>ISOODRPM</name> 23084 <description>Isochronous OUT packet dropped interrupt 23085 mask</description> 23086 <bitOffset>14</bitOffset> 23087 <bitWidth>1</bitWidth> 23088 <access>read-write</access> 23089 </field> 23090 <field> 23091 <name>EOPFM</name> 23092 <description>End of periodic frame interrupt 23093 mask</description> 23094 <bitOffset>15</bitOffset> 23095 <bitWidth>1</bitWidth> 23096 <access>read-write</access> 23097 </field> 23098 <field> 23099 <name>EPMISM</name> 23100 <description>Endpoint mismatch interrupt 23101 mask</description> 23102 <bitOffset>17</bitOffset> 23103 <bitWidth>1</bitWidth> 23104 <access>read-write</access> 23105 </field> 23106 <field> 23107 <name>IEPINT</name> 23108 <description>IN endpoints interrupt 23109 mask</description> 23110 <bitOffset>18</bitOffset> 23111 <bitWidth>1</bitWidth> 23112 <access>read-write</access> 23113 </field> 23114 <field> 23115 <name>OEPINT</name> 23116 <description>OUT endpoints interrupt 23117 mask</description> 23118 <bitOffset>19</bitOffset> 23119 <bitWidth>1</bitWidth> 23120 <access>read-write</access> 23121 </field> 23122 <field> 23123 <name>IISOIXFRM</name> 23124 <description>Incomplete isochronous IN transfer 23125 mask</description> 23126 <bitOffset>20</bitOffset> 23127 <bitWidth>1</bitWidth> 23128 <access>read-write</access> 23129 </field> 23130 <field> 23131 <name>IPXFRM_IISOOXFRM</name> 23132 <description>Incomplete periodic transfer mask(Host 23133 mode)/Incomplete isochronous OUT transfer mask(Device 23134 mode)</description> 23135 <bitOffset>21</bitOffset> 23136 <bitWidth>1</bitWidth> 23137 <access>read-write</access> 23138 </field> 23139 <field> 23140 <name>PRTIM</name> 23141 <description>Host port interrupt mask</description> 23142 <bitOffset>24</bitOffset> 23143 <bitWidth>1</bitWidth> 23144 <access>read-only</access> 23145 </field> 23146 <field> 23147 <name>HCIM</name> 23148 <description>Host channels interrupt 23149 mask</description> 23150 <bitOffset>25</bitOffset> 23151 <bitWidth>1</bitWidth> 23152 <access>read-write</access> 23153 </field> 23154 <field> 23155 <name>PTXFEM</name> 23156 <description>Periodic TxFIFO empty mask</description> 23157 <bitOffset>26</bitOffset> 23158 <bitWidth>1</bitWidth> 23159 <access>read-write</access> 23160 </field> 23161 <field> 23162 <name>CIDSCHGM</name> 23163 <description>Connector ID status change 23164 mask</description> 23165 <bitOffset>28</bitOffset> 23166 <bitWidth>1</bitWidth> 23167 <access>read-write</access> 23168 </field> 23169 <field> 23170 <name>DISCINT</name> 23171 <description>Disconnect detected interrupt 23172 mask</description> 23173 <bitOffset>29</bitOffset> 23174 <bitWidth>1</bitWidth> 23175 <access>read-write</access> 23176 </field> 23177 <field> 23178 <name>SRQIM</name> 23179 <description>Session request/new session detected 23180 interrupt mask</description> 23181 <bitOffset>30</bitOffset> 23182 <bitWidth>1</bitWidth> 23183 <access>read-write</access> 23184 </field> 23185 <field> 23186 <name>WUIM</name> 23187 <description>Resume/remote wakeup detected interrupt 23188 mask</description> 23189 <bitOffset>31</bitOffset> 23190 <bitWidth>1</bitWidth> 23191 <access>read-write</access> 23192 </field> 23193 </fields> 23194 </register> 23195 <register> 23196 <name>GRXSTSR_Device</name> 23197 <displayName>GRXSTSR_Device</displayName> 23198 <description>OTG_FS Receive status debug read(Device 23199 mode)</description> 23200 <addressOffset>0x1C</addressOffset> 23201 <size>0x20</size> 23202 <access>read-only</access> 23203 <resetValue>0x00000000</resetValue> 23204 <fields> 23205 <field> 23206 <name>EPNUM</name> 23207 <description>Endpoint number</description> 23208 <bitOffset>0</bitOffset> 23209 <bitWidth>4</bitWidth> 23210 </field> 23211 <field> 23212 <name>BCNT</name> 23213 <description>Byte count</description> 23214 <bitOffset>4</bitOffset> 23215 <bitWidth>11</bitWidth> 23216 </field> 23217 <field> 23218 <name>DPID</name> 23219 <description>Data PID</description> 23220 <bitOffset>15</bitOffset> 23221 <bitWidth>2</bitWidth> 23222 </field> 23223 <field> 23224 <name>PKTSTS</name> 23225 <description>Packet status</description> 23226 <bitOffset>17</bitOffset> 23227 <bitWidth>4</bitWidth> 23228 </field> 23229 <field> 23230 <name>FRMNUM</name> 23231 <description>Frame number</description> 23232 <bitOffset>21</bitOffset> 23233 <bitWidth>4</bitWidth> 23234 </field> 23235 </fields> 23236 </register> 23237 <register> 23238 <name>GRXSTSR_Host</name> 23239 <displayName>GRXSTSR_Host</displayName> 23240 <description>OTG_FS Receive status debug read(Host 23241 mode)</description> 23242 <alternateRegister>FS_GRXSTSR_Device</alternateRegister> 23243 <addressOffset>0x1C</addressOffset> 23244 <size>0x20</size> 23245 <access>read-only</access> 23246 <resetValue>0x00000000</resetValue> 23247 <fields> 23248 <field> 23249 <name>EPNUM</name> 23250 <description>Endpoint number</description> 23251 <bitOffset>0</bitOffset> 23252 <bitWidth>4</bitWidth> 23253 </field> 23254 <field> 23255 <name>BCNT</name> 23256 <description>Byte count</description> 23257 <bitOffset>4</bitOffset> 23258 <bitWidth>11</bitWidth> 23259 </field> 23260 <field> 23261 <name>DPID</name> 23262 <description>Data PID</description> 23263 <bitOffset>15</bitOffset> 23264 <bitWidth>2</bitWidth> 23265 </field> 23266 <field> 23267 <name>PKTSTS</name> 23268 <description>Packet status</description> 23269 <bitOffset>17</bitOffset> 23270 <bitWidth>4</bitWidth> 23271 </field> 23272 <field> 23273 <name>FRMNUM</name> 23274 <description>Frame number</description> 23275 <bitOffset>21</bitOffset> 23276 <bitWidth>4</bitWidth> 23277 </field> 23278 </fields> 23279 </register> 23280 <register> 23281 <name>GRXFSIZ</name> 23282 <displayName>GRXFSIZ</displayName> 23283 <description>OTG_FS Receive FIFO size register 23284 (OTG_FS_GRXFSIZ)</description> 23285 <addressOffset>0x24</addressOffset> 23286 <size>0x20</size> 23287 <access>read-write</access> 23288 <resetValue>0x00000200</resetValue> 23289 <fields> 23290 <field> 23291 <name>RXFD</name> 23292 <description>RxFIFO depth</description> 23293 <bitOffset>0</bitOffset> 23294 <bitWidth>16</bitWidth> 23295 </field> 23296 </fields> 23297 </register> 23298 <register> 23299 <name>DIEPTXF0</name> 23300 <displayName>DIEPTXF0</displayName> 23301 <description>OTG_FS non-periodic transmit FIFO size 23302 register (Device mode)</description> 23303 <addressOffset>0x28</addressOffset> 23304 <size>0x20</size> 23305 <access>read-write</access> 23306 <resetValue>0x00000200</resetValue> 23307 <fields> 23308 <field> 23309 <name>TX0FSA</name> 23310 <description>Endpoint 0 transmit RAM start 23311 address</description> 23312 <bitOffset>0</bitOffset> 23313 <bitWidth>16</bitWidth> 23314 </field> 23315 <field> 23316 <name>TX0FD</name> 23317 <description>Endpoint 0 TxFIFO depth</description> 23318 <bitOffset>16</bitOffset> 23319 <bitWidth>16</bitWidth> 23320 </field> 23321 </fields> 23322 </register> 23323 <register> 23324 <name>HNPTXFSIZ</name> 23325 <displayName>HNPTXFSIZ</displayName> 23326 <description>OTG_FS non-periodic transmit FIFO size 23327 register (Host mode)</description> 23328 <alternateRegister>DIEPTXF0</alternateRegister> 23329 <addressOffset>0x28</addressOffset> 23330 <size>0x20</size> 23331 <access>read-write</access> 23332 <resetValue>0x00000200</resetValue> 23333 <fields> 23334 <field> 23335 <name>NPTXFSA</name> 23336 <description>Non-periodic transmit RAM start 23337 address</description> 23338 <bitOffset>0</bitOffset> 23339 <bitWidth>16</bitWidth> 23340 </field> 23341 <field> 23342 <name>NPTXFD</name> 23343 <description>Non-periodic TxFIFO depth</description> 23344 <bitOffset>16</bitOffset> 23345 <bitWidth>16</bitWidth> 23346 </field> 23347 </fields> 23348 </register> 23349 <register> 23350 <name>GNPTXSTS</name> 23351 <displayName>GNPTXSTS</displayName> 23352 <description>OTG_FS non-periodic transmit FIFO/queue 23353 status register (OTG_FS_GNPTXSTS)</description> 23354 <addressOffset>0x2C</addressOffset> 23355 <size>0x20</size> 23356 <access>read-only</access> 23357 <resetValue>0x00080200</resetValue> 23358 <fields> 23359 <field> 23360 <name>NPTXFSAV</name> 23361 <description>Non-periodic TxFIFO space 23362 available</description> 23363 <bitOffset>0</bitOffset> 23364 <bitWidth>16</bitWidth> 23365 </field> 23366 <field> 23367 <name>NPTQXSAV</name> 23368 <description>Non-periodic transmit request queue 23369 space available</description> 23370 <bitOffset>16</bitOffset> 23371 <bitWidth>8</bitWidth> 23372 </field> 23373 <field> 23374 <name>NPTXQTOP</name> 23375 <description>Top of the non-periodic transmit request 23376 queue</description> 23377 <bitOffset>24</bitOffset> 23378 <bitWidth>7</bitWidth> 23379 </field> 23380 </fields> 23381 </register> 23382 <register> 23383 <name>GCCFG</name> 23384 <displayName>GCCFG</displayName> 23385 <description>OTG_FS general core configuration register 23386 (OTG_FS_GCCFG)</description> 23387 <addressOffset>0x38</addressOffset> 23388 <size>0x20</size> 23389 <access>read-write</access> 23390 <resetValue>0x00000000</resetValue> 23391 <fields> 23392 <field> 23393 <name>PWRDWN</name> 23394 <description>Power down</description> 23395 <bitOffset>16</bitOffset> 23396 <bitWidth>1</bitWidth> 23397 </field> 23398 <field> 23399 <name>VBUSASEN</name> 23400 <description>Enable the VBUS sensing 23401 device</description> 23402 <bitOffset>18</bitOffset> 23403 <bitWidth>1</bitWidth> 23404 </field> 23405 <field> 23406 <name>VBUSBSEN</name> 23407 <description>Enable the VBUS sensing 23408 device</description> 23409 <bitOffset>19</bitOffset> 23410 <bitWidth>1</bitWidth> 23411 </field> 23412 <field> 23413 <name>SOFOUTEN</name> 23414 <description>SOF output enable</description> 23415 <bitOffset>20</bitOffset> 23416 <bitWidth>1</bitWidth> 23417 </field> 23418 </fields> 23419 </register> 23420 <register> 23421 <name>CID</name> 23422 <displayName>CID</displayName> 23423 <description>core ID register</description> 23424 <addressOffset>0x3C</addressOffset> 23425 <size>0x20</size> 23426 <access>read-write</access> 23427 <resetValue>0x00001000</resetValue> 23428 <fields> 23429 <field> 23430 <name>PRODUCT_ID</name> 23431 <description>Product ID field</description> 23432 <bitOffset>0</bitOffset> 23433 <bitWidth>32</bitWidth> 23434 </field> 23435 </fields> 23436 </register> 23437 <register> 23438 <name>HPTXFSIZ</name> 23439 <displayName>HPTXFSIZ</displayName> 23440 <description>OTG_FS Host periodic transmit FIFO size 23441 register (OTG_FS_HPTXFSIZ)</description> 23442 <addressOffset>0x100</addressOffset> 23443 <size>0x20</size> 23444 <access>read-write</access> 23445 <resetValue>0x02000600</resetValue> 23446 <fields> 23447 <field> 23448 <name>PTXSA</name> 23449 <description>Host periodic TxFIFO start 23450 address</description> 23451 <bitOffset>0</bitOffset> 23452 <bitWidth>16</bitWidth> 23453 </field> 23454 <field> 23455 <name>PTXFSIZ</name> 23456 <description>Host periodic TxFIFO depth</description> 23457 <bitOffset>16</bitOffset> 23458 <bitWidth>16</bitWidth> 23459 </field> 23460 </fields> 23461 </register> 23462 <register> 23463 <dim>3</dim><dimIncrement>0x4</dimIncrement><dimIndex>1,2,3</dimIndex><name>DIEPTXF%s</name> 23464 <displayName>DIEPTXF1</displayName> 23465 <description>OTG_FS device IN endpoint transmit FIFO size 23466 register (OTG_FS_DIEPTXF2)</description> 23467 <addressOffset>0x104</addressOffset> 23468 <size>0x20</size> 23469 <access>read-write</access> 23470 <resetValue>0x02000400</resetValue> 23471 <fields> 23472 <field> 23473 <name>INEPTXSA</name> 23474 <description>IN endpoint FIFO2 transmit RAM start 23475 address</description> 23476 <bitOffset>0</bitOffset> 23477 <bitWidth>16</bitWidth> 23478 </field> 23479 <field> 23480 <name>INEPTXFD</name> 23481 <description>IN endpoint TxFIFO depth</description> 23482 <bitOffset>16</bitOffset> 23483 <bitWidth>16</bitWidth> 23484 </field> 23485 </fields> 23486 </register> 23487 <register><name>GRXSTSP_Device</name><description>OTG status read and pop (device mode)</description><addressOffset>32</addressOffset><size>32</size><access>read-only</access><resetValue>0</resetValue><fields><field><name>STSPHST</name><description>Status phase start</description><bitOffset>27</bitOffset><bitWidth>1</bitWidth></field> 23488 <field><name>FRMNUM</name><description>Frame number</description><bitOffset>21</bitOffset><bitWidth>4</bitWidth></field> 23489 <field><name>PKTSTS</name><description>Packet status</description><bitOffset>17</bitOffset><bitWidth>4</bitWidth></field> 23490 <field><name>DPID</name><description>Data PID</description><bitOffset>15</bitOffset><bitWidth>2</bitWidth></field> 23491 <field><name>BCNT</name><description>Byte count</description><bitOffset>4</bitOffset><bitWidth>11</bitWidth></field> 23492 <field><name>EPNUM</name><description>Endpoint number</description><bitOffset>0</bitOffset><bitWidth>4</bitWidth></field> 23493 </fields></register> 23494 <register><name>GRXSTSP_Host</name><description>OTG status read and pop (host mode)</description><alternateRegister>GRXSTSP_Device</alternateRegister><addressOffset>32</addressOffset><size>32</size><access>read-only</access><resetValue>0</resetValue><fields><field><name>PKTSTS</name><description>Packet status</description><bitOffset>17</bitOffset><bitWidth>4</bitWidth></field> 23495 <field><name>DPID</name><description>Data PID</description><bitOffset>15</bitOffset><bitWidth>2</bitWidth></field> 23496 <field><name>BCNT</name><description>Byte count</description><bitOffset>4</bitOffset><bitWidth>11</bitWidth></field> 23497 <field><name>CHNUM</name><description>Channel number</description><bitOffset>0</bitOffset><bitWidth>4</bitWidth></field> 23498 </fields></register> 23499 </registers> 23500 </peripheral> 23501 <peripheral> 23502 <name>OTG_FS_HOST</name> 23503 <description>USB on the go full speed</description> 23504 <groupName>USB_OTG_FS</groupName> 23505 <baseAddress>0x50000400</baseAddress> 23506 <addressBlock> 23507 <offset>0x0</offset> 23508 <size>0x400</size> 23509 <usage>registers</usage> 23510 </addressBlock> 23511 <registers> 23512 <register> 23513 <name>HCFG</name> 23514 <displayName>HCFG</displayName> 23515 <description>OTG_FS host configuration register 23516 (OTG_FS_HCFG)</description> 23517 <addressOffset>0x0</addressOffset> 23518 <size>0x20</size> 23519 <resetValue>0x00000000</resetValue> 23520 <fields> 23521 <field> 23522 <name>FSLSPCS</name> 23523 <description>FS/LS PHY clock select</description> 23524 <bitOffset>0</bitOffset> 23525 <bitWidth>2</bitWidth> 23526 <access>read-write</access> 23527 </field> 23528 <field> 23529 <name>FSLSS</name> 23530 <description>FS- and LS-only support</description> 23531 <bitOffset>2</bitOffset> 23532 <bitWidth>1</bitWidth> 23533 <access>read-only</access> 23534 </field> 23535 </fields> 23536 </register> 23537 <register> 23538 <name>HFIR</name> 23539 <displayName>HFIR</displayName> 23540 <description>OTG_FS Host frame interval 23541 register</description> 23542 <addressOffset>0x4</addressOffset> 23543 <size>0x20</size> 23544 <access>read-write</access> 23545 <resetValue>0x0000EA60</resetValue> 23546 <fields> 23547 <field> 23548 <name>FRIVL</name> 23549 <description>Frame interval</description> 23550 <bitOffset>0</bitOffset> 23551 <bitWidth>16</bitWidth> 23552 </field> 23553 </fields> 23554 </register> 23555 <register> 23556 <name>HFNUM</name> 23557 <displayName>HFNUM</displayName> 23558 <description>OTG_FS host frame number/frame time 23559 remaining register (OTG_FS_HFNUM)</description> 23560 <addressOffset>0x8</addressOffset> 23561 <size>0x20</size> 23562 <access>read-only</access> 23563 <resetValue>0x00003FFF</resetValue> 23564 <fields> 23565 <field> 23566 <name>FRNUM</name> 23567 <description>Frame number</description> 23568 <bitOffset>0</bitOffset> 23569 <bitWidth>16</bitWidth> 23570 </field> 23571 <field> 23572 <name>FTREM</name> 23573 <description>Frame time remaining</description> 23574 <bitOffset>16</bitOffset> 23575 <bitWidth>16</bitWidth> 23576 </field> 23577 </fields> 23578 </register> 23579 <register> 23580 <name>HPTXSTS</name> 23581 <displayName>HPTXSTS</displayName> 23582 <description>OTG_FS_Host periodic transmit FIFO/queue 23583 status register (OTG_FS_HPTXSTS)</description> 23584 <addressOffset>0x10</addressOffset> 23585 <size>0x20</size> 23586 <resetValue>0x00080100</resetValue> 23587 <fields> 23588 <field> 23589 <name>PTXFSAVL</name> 23590 <description>Periodic transmit data FIFO space 23591 available</description> 23592 <bitOffset>0</bitOffset> 23593 <bitWidth>16</bitWidth> 23594 <access>read-write</access> 23595 </field> 23596 <field> 23597 <name>PTXQSAV</name> 23598 <description>Periodic transmit request queue space 23599 available</description> 23600 <bitOffset>16</bitOffset> 23601 <bitWidth>8</bitWidth> 23602 <access>read-only</access> 23603 </field> 23604 <field> 23605 <name>PTXQTOP</name> 23606 <description>Top of the periodic transmit request 23607 queue</description> 23608 <bitOffset>24</bitOffset> 23609 <bitWidth>8</bitWidth> 23610 <access>read-only</access> 23611 </field> 23612 </fields> 23613 </register> 23614 <register> 23615 <name>HAINT</name> 23616 <displayName>HAINT</displayName> 23617 <description>OTG_FS Host all channels interrupt 23618 register</description> 23619 <addressOffset>0x14</addressOffset> 23620 <size>0x20</size> 23621 <access>read-only</access> 23622 <resetValue>0x00000000</resetValue> 23623 <fields> 23624 <field> 23625 <name>HAINT</name> 23626 <description>Channel interrupts</description> 23627 <bitOffset>0</bitOffset> 23628 <bitWidth>16</bitWidth> 23629 </field> 23630 </fields> 23631 </register> 23632 <register> 23633 <name>HAINTMSK</name> 23634 <displayName>HAINTMSK</displayName> 23635 <description>OTG_FS host all channels interrupt mask 23636 register</description> 23637 <addressOffset>0x18</addressOffset> 23638 <size>0x20</size> 23639 <access>read-write</access> 23640 <resetValue>0x00000000</resetValue> 23641 <fields> 23642 <field> 23643 <name>HAINTM</name> 23644 <description>Channel interrupt mask</description> 23645 <bitOffset>0</bitOffset> 23646 <bitWidth>16</bitWidth> 23647 </field> 23648 </fields> 23649 </register> 23650 <register> 23651 <name>HPRT</name> 23652 <displayName>HPRT</displayName> 23653 <description>OTG_FS host port control and status register 23654 (OTG_FS_HPRT)</description> 23655 <addressOffset>0x40</addressOffset> 23656 <size>0x20</size> 23657 <resetValue>0x00000000</resetValue> 23658 <fields> 23659 <field> 23660 <name>PCSTS</name> 23661 <description>Port connect status</description> 23662 <bitOffset>0</bitOffset> 23663 <bitWidth>1</bitWidth> 23664 <access>read-only</access> 23665 </field> 23666 <field> 23667 <name>PCDET</name> 23668 <description>Port connect detected</description> 23669 <bitOffset>1</bitOffset> 23670 <bitWidth>1</bitWidth> 23671 <access>read-write</access> 23672 </field> 23673 <field> 23674 <name>PENA</name> 23675 <description>Port enable</description> 23676 <bitOffset>2</bitOffset> 23677 <bitWidth>1</bitWidth> 23678 <access>read-write</access> 23679 </field> 23680 <field> 23681 <name>PENCHNG</name> 23682 <description>Port enable/disable change</description> 23683 <bitOffset>3</bitOffset> 23684 <bitWidth>1</bitWidth> 23685 <access>read-write</access> 23686 </field> 23687 <field> 23688 <name>POCA</name> 23689 <description>Port overcurrent active</description> 23690 <bitOffset>4</bitOffset> 23691 <bitWidth>1</bitWidth> 23692 <access>read-only</access> 23693 </field> 23694 <field> 23695 <name>POCCHNG</name> 23696 <description>Port overcurrent change</description> 23697 <bitOffset>5</bitOffset> 23698 <bitWidth>1</bitWidth> 23699 <access>read-write</access> 23700 </field> 23701 <field> 23702 <name>PRES</name> 23703 <description>Port resume</description> 23704 <bitOffset>6</bitOffset> 23705 <bitWidth>1</bitWidth> 23706 <access>read-write</access> 23707 </field> 23708 <field> 23709 <name>PSUSP</name> 23710 <description>Port suspend</description> 23711 <bitOffset>7</bitOffset> 23712 <bitWidth>1</bitWidth> 23713 <access>read-write</access> 23714 </field> 23715 <field> 23716 <name>PRST</name> 23717 <description>Port reset</description> 23718 <bitOffset>8</bitOffset> 23719 <bitWidth>1</bitWidth> 23720 <access>read-write</access> 23721 </field> 23722 <field> 23723 <name>PLSTS</name> 23724 <description>Port line status</description> 23725 <bitOffset>10</bitOffset> 23726 <bitWidth>2</bitWidth> 23727 <access>read-only</access> 23728 </field> 23729 <field> 23730 <name>PPWR</name> 23731 <description>Port power</description> 23732 <bitOffset>12</bitOffset> 23733 <bitWidth>1</bitWidth> 23734 <access>read-write</access> 23735 </field> 23736 <field> 23737 <name>PTCTL</name> 23738 <description>Port test control</description> 23739 <bitOffset>13</bitOffset> 23740 <bitWidth>4</bitWidth> 23741 <access>read-write</access> 23742 </field> 23743 <field> 23744 <name>PSPD</name> 23745 <description>Port speed</description> 23746 <bitOffset>17</bitOffset> 23747 <bitWidth>2</bitWidth> 23748 <access>read-only</access> 23749 </field> 23750 </fields> 23751 </register> 23752 <register> 23753 <name>HCCHAR0</name> 23754 <displayName>HCCHAR0</displayName> 23755 <description>OTG_FS host channel-0 characteristics 23756 register (OTG_FS_HCCHAR0)</description> 23757 <addressOffset>0x100</addressOffset> 23758 <size>0x20</size> 23759 <access>read-write</access> 23760 <resetValue>0x00000000</resetValue> 23761 <fields> 23762 <field> 23763 <name>MPSIZ</name> 23764 <description>Maximum packet size</description> 23765 <bitOffset>0</bitOffset> 23766 <bitWidth>11</bitWidth> 23767 </field> 23768 <field> 23769 <name>EPNUM</name> 23770 <description>Endpoint number</description> 23771 <bitOffset>11</bitOffset> 23772 <bitWidth>4</bitWidth> 23773 </field> 23774 <field> 23775 <name>EPDIR</name> 23776 <description>Endpoint direction</description> 23777 <bitOffset>15</bitOffset> 23778 <bitWidth>1</bitWidth> 23779 </field> 23780 <field> 23781 <name>LSDEV</name> 23782 <description>Low-speed device</description> 23783 <bitOffset>17</bitOffset> 23784 <bitWidth>1</bitWidth> 23785 </field> 23786 <field> 23787 <name>EPTYP</name> 23788 <description>Endpoint type</description> 23789 <bitOffset>18</bitOffset> 23790 <bitWidth>2</bitWidth> 23791 </field> 23792 <field> 23793 <name>MCNT</name> 23794 <description>Multicount</description> 23795 <bitOffset>20</bitOffset> 23796 <bitWidth>2</bitWidth> 23797 </field> 23798 <field> 23799 <name>DAD</name> 23800 <description>Device address</description> 23801 <bitOffset>22</bitOffset> 23802 <bitWidth>7</bitWidth> 23803 </field> 23804 <field> 23805 <name>ODDFRM</name> 23806 <description>Odd frame</description> 23807 <bitOffset>29</bitOffset> 23808 <bitWidth>1</bitWidth> 23809 </field> 23810 <field> 23811 <name>CHDIS</name> 23812 <description>Channel disable</description> 23813 <bitOffset>30</bitOffset> 23814 <bitWidth>1</bitWidth> 23815 </field> 23816 <field> 23817 <name>CHENA</name> 23818 <description>Channel enable</description> 23819 <bitOffset>31</bitOffset> 23820 <bitWidth>1</bitWidth> 23821 </field> 23822 </fields> 23823 </register> 23824 <register> 23825 <name>HCCHAR1</name> 23826 <displayName>HCCHAR1</displayName> 23827 <description>OTG_FS host channel-1 characteristics 23828 register (OTG_FS_HCCHAR1)</description> 23829 <addressOffset>0x120</addressOffset> 23830 <size>0x20</size> 23831 <access>read-write</access> 23832 <resetValue>0x00000000</resetValue> 23833 <fields> 23834 <field> 23835 <name>MPSIZ</name> 23836 <description>Maximum packet size</description> 23837 <bitOffset>0</bitOffset> 23838 <bitWidth>11</bitWidth> 23839 </field> 23840 <field> 23841 <name>EPNUM</name> 23842 <description>Endpoint number</description> 23843 <bitOffset>11</bitOffset> 23844 <bitWidth>4</bitWidth> 23845 </field> 23846 <field> 23847 <name>EPDIR</name> 23848 <description>Endpoint direction</description> 23849 <bitOffset>15</bitOffset> 23850 <bitWidth>1</bitWidth> 23851 </field> 23852 <field> 23853 <name>LSDEV</name> 23854 <description>Low-speed device</description> 23855 <bitOffset>17</bitOffset> 23856 <bitWidth>1</bitWidth> 23857 </field> 23858 <field> 23859 <name>EPTYP</name> 23860 <description>Endpoint type</description> 23861 <bitOffset>18</bitOffset> 23862 <bitWidth>2</bitWidth> 23863 </field> 23864 <field> 23865 <name>MCNT</name> 23866 <description>Multicount</description> 23867 <bitOffset>20</bitOffset> 23868 <bitWidth>2</bitWidth> 23869 </field> 23870 <field> 23871 <name>DAD</name> 23872 <description>Device address</description> 23873 <bitOffset>22</bitOffset> 23874 <bitWidth>7</bitWidth> 23875 </field> 23876 <field> 23877 <name>ODDFRM</name> 23878 <description>Odd frame</description> 23879 <bitOffset>29</bitOffset> 23880 <bitWidth>1</bitWidth> 23881 </field> 23882 <field> 23883 <name>CHDIS</name> 23884 <description>Channel disable</description> 23885 <bitOffset>30</bitOffset> 23886 <bitWidth>1</bitWidth> 23887 </field> 23888 <field> 23889 <name>CHENA</name> 23890 <description>Channel enable</description> 23891 <bitOffset>31</bitOffset> 23892 <bitWidth>1</bitWidth> 23893 </field> 23894 </fields> 23895 </register> 23896 <register> 23897 <name>HCCHAR2</name> 23898 <displayName>HCCHAR2</displayName> 23899 <description>OTG_FS host channel-2 characteristics 23900 register (OTG_FS_HCCHAR2)</description> 23901 <addressOffset>0x140</addressOffset> 23902 <size>0x20</size> 23903 <access>read-write</access> 23904 <resetValue>0x00000000</resetValue> 23905 <fields> 23906 <field> 23907 <name>MPSIZ</name> 23908 <description>Maximum packet size</description> 23909 <bitOffset>0</bitOffset> 23910 <bitWidth>11</bitWidth> 23911 </field> 23912 <field> 23913 <name>EPNUM</name> 23914 <description>Endpoint number</description> 23915 <bitOffset>11</bitOffset> 23916 <bitWidth>4</bitWidth> 23917 </field> 23918 <field> 23919 <name>EPDIR</name> 23920 <description>Endpoint direction</description> 23921 <bitOffset>15</bitOffset> 23922 <bitWidth>1</bitWidth> 23923 </field> 23924 <field> 23925 <name>LSDEV</name> 23926 <description>Low-speed device</description> 23927 <bitOffset>17</bitOffset> 23928 <bitWidth>1</bitWidth> 23929 </field> 23930 <field> 23931 <name>EPTYP</name> 23932 <description>Endpoint type</description> 23933 <bitOffset>18</bitOffset> 23934 <bitWidth>2</bitWidth> 23935 </field> 23936 <field> 23937 <name>MCNT</name> 23938 <description>Multicount</description> 23939 <bitOffset>20</bitOffset> 23940 <bitWidth>2</bitWidth> 23941 </field> 23942 <field> 23943 <name>DAD</name> 23944 <description>Device address</description> 23945 <bitOffset>22</bitOffset> 23946 <bitWidth>7</bitWidth> 23947 </field> 23948 <field> 23949 <name>ODDFRM</name> 23950 <description>Odd frame</description> 23951 <bitOffset>29</bitOffset> 23952 <bitWidth>1</bitWidth> 23953 </field> 23954 <field> 23955 <name>CHDIS</name> 23956 <description>Channel disable</description> 23957 <bitOffset>30</bitOffset> 23958 <bitWidth>1</bitWidth> 23959 </field> 23960 <field> 23961 <name>CHENA</name> 23962 <description>Channel enable</description> 23963 <bitOffset>31</bitOffset> 23964 <bitWidth>1</bitWidth> 23965 </field> 23966 </fields> 23967 </register> 23968 <register> 23969 <name>HCCHAR3</name> 23970 <displayName>HCCHAR3</displayName> 23971 <description>OTG_FS host channel-3 characteristics 23972 register (OTG_FS_HCCHAR3)</description> 23973 <addressOffset>0x160</addressOffset> 23974 <size>0x20</size> 23975 <access>read-write</access> 23976 <resetValue>0x00000000</resetValue> 23977 <fields> 23978 <field> 23979 <name>MPSIZ</name> 23980 <description>Maximum packet size</description> 23981 <bitOffset>0</bitOffset> 23982 <bitWidth>11</bitWidth> 23983 </field> 23984 <field> 23985 <name>EPNUM</name> 23986 <description>Endpoint number</description> 23987 <bitOffset>11</bitOffset> 23988 <bitWidth>4</bitWidth> 23989 </field> 23990 <field> 23991 <name>EPDIR</name> 23992 <description>Endpoint direction</description> 23993 <bitOffset>15</bitOffset> 23994 <bitWidth>1</bitWidth> 23995 </field> 23996 <field> 23997 <name>LSDEV</name> 23998 <description>Low-speed device</description> 23999 <bitOffset>17</bitOffset> 24000 <bitWidth>1</bitWidth> 24001 </field> 24002 <field> 24003 <name>EPTYP</name> 24004 <description>Endpoint type</description> 24005 <bitOffset>18</bitOffset> 24006 <bitWidth>2</bitWidth> 24007 </field> 24008 <field> 24009 <name>MCNT</name> 24010 <description>Multicount</description> 24011 <bitOffset>20</bitOffset> 24012 <bitWidth>2</bitWidth> 24013 </field> 24014 <field> 24015 <name>DAD</name> 24016 <description>Device address</description> 24017 <bitOffset>22</bitOffset> 24018 <bitWidth>7</bitWidth> 24019 </field> 24020 <field> 24021 <name>ODDFRM</name> 24022 <description>Odd frame</description> 24023 <bitOffset>29</bitOffset> 24024 <bitWidth>1</bitWidth> 24025 </field> 24026 <field> 24027 <name>CHDIS</name> 24028 <description>Channel disable</description> 24029 <bitOffset>30</bitOffset> 24030 <bitWidth>1</bitWidth> 24031 </field> 24032 <field> 24033 <name>CHENA</name> 24034 <description>Channel enable</description> 24035 <bitOffset>31</bitOffset> 24036 <bitWidth>1</bitWidth> 24037 </field> 24038 </fields> 24039 </register> 24040 <register> 24041 <name>HCCHAR4</name> 24042 <displayName>HCCHAR4</displayName> 24043 <description>OTG_FS host channel-4 characteristics 24044 register (OTG_FS_HCCHAR4)</description> 24045 <addressOffset>0x180</addressOffset> 24046 <size>0x20</size> 24047 <access>read-write</access> 24048 <resetValue>0x00000000</resetValue> 24049 <fields> 24050 <field> 24051 <name>MPSIZ</name> 24052 <description>Maximum packet size</description> 24053 <bitOffset>0</bitOffset> 24054 <bitWidth>11</bitWidth> 24055 </field> 24056 <field> 24057 <name>EPNUM</name> 24058 <description>Endpoint number</description> 24059 <bitOffset>11</bitOffset> 24060 <bitWidth>4</bitWidth> 24061 </field> 24062 <field> 24063 <name>EPDIR</name> 24064 <description>Endpoint direction</description> 24065 <bitOffset>15</bitOffset> 24066 <bitWidth>1</bitWidth> 24067 </field> 24068 <field> 24069 <name>LSDEV</name> 24070 <description>Low-speed device</description> 24071 <bitOffset>17</bitOffset> 24072 <bitWidth>1</bitWidth> 24073 </field> 24074 <field> 24075 <name>EPTYP</name> 24076 <description>Endpoint type</description> 24077 <bitOffset>18</bitOffset> 24078 <bitWidth>2</bitWidth> 24079 </field> 24080 <field> 24081 <name>MCNT</name> 24082 <description>Multicount</description> 24083 <bitOffset>20</bitOffset> 24084 <bitWidth>2</bitWidth> 24085 </field> 24086 <field> 24087 <name>DAD</name> 24088 <description>Device address</description> 24089 <bitOffset>22</bitOffset> 24090 <bitWidth>7</bitWidth> 24091 </field> 24092 <field> 24093 <name>ODDFRM</name> 24094 <description>Odd frame</description> 24095 <bitOffset>29</bitOffset> 24096 <bitWidth>1</bitWidth> 24097 </field> 24098 <field> 24099 <name>CHDIS</name> 24100 <description>Channel disable</description> 24101 <bitOffset>30</bitOffset> 24102 <bitWidth>1</bitWidth> 24103 </field> 24104 <field> 24105 <name>CHENA</name> 24106 <description>Channel enable</description> 24107 <bitOffset>31</bitOffset> 24108 <bitWidth>1</bitWidth> 24109 </field> 24110 </fields> 24111 </register> 24112 <register> 24113 <name>HCCHAR5</name> 24114 <displayName>HCCHAR5</displayName> 24115 <description>OTG_FS host channel-5 characteristics 24116 register (OTG_FS_HCCHAR5)</description> 24117 <addressOffset>0x1A0</addressOffset> 24118 <size>0x20</size> 24119 <access>read-write</access> 24120 <resetValue>0x00000000</resetValue> 24121 <fields> 24122 <field> 24123 <name>MPSIZ</name> 24124 <description>Maximum packet size</description> 24125 <bitOffset>0</bitOffset> 24126 <bitWidth>11</bitWidth> 24127 </field> 24128 <field> 24129 <name>EPNUM</name> 24130 <description>Endpoint number</description> 24131 <bitOffset>11</bitOffset> 24132 <bitWidth>4</bitWidth> 24133 </field> 24134 <field> 24135 <name>EPDIR</name> 24136 <description>Endpoint direction</description> 24137 <bitOffset>15</bitOffset> 24138 <bitWidth>1</bitWidth> 24139 </field> 24140 <field> 24141 <name>LSDEV</name> 24142 <description>Low-speed device</description> 24143 <bitOffset>17</bitOffset> 24144 <bitWidth>1</bitWidth> 24145 </field> 24146 <field> 24147 <name>EPTYP</name> 24148 <description>Endpoint type</description> 24149 <bitOffset>18</bitOffset> 24150 <bitWidth>2</bitWidth> 24151 </field> 24152 <field> 24153 <name>MCNT</name> 24154 <description>Multicount</description> 24155 <bitOffset>20</bitOffset> 24156 <bitWidth>2</bitWidth> 24157 </field> 24158 <field> 24159 <name>DAD</name> 24160 <description>Device address</description> 24161 <bitOffset>22</bitOffset> 24162 <bitWidth>7</bitWidth> 24163 </field> 24164 <field> 24165 <name>ODDFRM</name> 24166 <description>Odd frame</description> 24167 <bitOffset>29</bitOffset> 24168 <bitWidth>1</bitWidth> 24169 </field> 24170 <field> 24171 <name>CHDIS</name> 24172 <description>Channel disable</description> 24173 <bitOffset>30</bitOffset> 24174 <bitWidth>1</bitWidth> 24175 </field> 24176 <field> 24177 <name>CHENA</name> 24178 <description>Channel enable</description> 24179 <bitOffset>31</bitOffset> 24180 <bitWidth>1</bitWidth> 24181 </field> 24182 </fields> 24183 </register> 24184 <register> 24185 <name>HCCHAR6</name> 24186 <displayName>HCCHAR6</displayName> 24187 <description>OTG_FS host channel-6 characteristics 24188 register (OTG_FS_HCCHAR6)</description> 24189 <addressOffset>0x1C0</addressOffset> 24190 <size>0x20</size> 24191 <access>read-write</access> 24192 <resetValue>0x00000000</resetValue> 24193 <fields> 24194 <field> 24195 <name>MPSIZ</name> 24196 <description>Maximum packet size</description> 24197 <bitOffset>0</bitOffset> 24198 <bitWidth>11</bitWidth> 24199 </field> 24200 <field> 24201 <name>EPNUM</name> 24202 <description>Endpoint number</description> 24203 <bitOffset>11</bitOffset> 24204 <bitWidth>4</bitWidth> 24205 </field> 24206 <field> 24207 <name>EPDIR</name> 24208 <description>Endpoint direction</description> 24209 <bitOffset>15</bitOffset> 24210 <bitWidth>1</bitWidth> 24211 </field> 24212 <field> 24213 <name>LSDEV</name> 24214 <description>Low-speed device</description> 24215 <bitOffset>17</bitOffset> 24216 <bitWidth>1</bitWidth> 24217 </field> 24218 <field> 24219 <name>EPTYP</name> 24220 <description>Endpoint type</description> 24221 <bitOffset>18</bitOffset> 24222 <bitWidth>2</bitWidth> 24223 </field> 24224 <field> 24225 <name>MCNT</name> 24226 <description>Multicount</description> 24227 <bitOffset>20</bitOffset> 24228 <bitWidth>2</bitWidth> 24229 </field> 24230 <field> 24231 <name>DAD</name> 24232 <description>Device address</description> 24233 <bitOffset>22</bitOffset> 24234 <bitWidth>7</bitWidth> 24235 </field> 24236 <field> 24237 <name>ODDFRM</name> 24238 <description>Odd frame</description> 24239 <bitOffset>29</bitOffset> 24240 <bitWidth>1</bitWidth> 24241 </field> 24242 <field> 24243 <name>CHDIS</name> 24244 <description>Channel disable</description> 24245 <bitOffset>30</bitOffset> 24246 <bitWidth>1</bitWidth> 24247 </field> 24248 <field> 24249 <name>CHENA</name> 24250 <description>Channel enable</description> 24251 <bitOffset>31</bitOffset> 24252 <bitWidth>1</bitWidth> 24253 </field> 24254 </fields> 24255 </register> 24256 <register> 24257 <name>HCCHAR7</name> 24258 <displayName>HCCHAR7</displayName> 24259 <description>OTG_FS host channel-7 characteristics 24260 register (OTG_FS_HCCHAR7)</description> 24261 <addressOffset>0x1E0</addressOffset> 24262 <size>0x20</size> 24263 <access>read-write</access> 24264 <resetValue>0x00000000</resetValue> 24265 <fields> 24266 <field> 24267 <name>MPSIZ</name> 24268 <description>Maximum packet size</description> 24269 <bitOffset>0</bitOffset> 24270 <bitWidth>11</bitWidth> 24271 </field> 24272 <field> 24273 <name>EPNUM</name> 24274 <description>Endpoint number</description> 24275 <bitOffset>11</bitOffset> 24276 <bitWidth>4</bitWidth> 24277 </field> 24278 <field> 24279 <name>EPDIR</name> 24280 <description>Endpoint direction</description> 24281 <bitOffset>15</bitOffset> 24282 <bitWidth>1</bitWidth> 24283 </field> 24284 <field> 24285 <name>LSDEV</name> 24286 <description>Low-speed device</description> 24287 <bitOffset>17</bitOffset> 24288 <bitWidth>1</bitWidth> 24289 </field> 24290 <field> 24291 <name>EPTYP</name> 24292 <description>Endpoint type</description> 24293 <bitOffset>18</bitOffset> 24294 <bitWidth>2</bitWidth> 24295 </field> 24296 <field> 24297 <name>MCNT</name> 24298 <description>Multicount</description> 24299 <bitOffset>20</bitOffset> 24300 <bitWidth>2</bitWidth> 24301 </field> 24302 <field> 24303 <name>DAD</name> 24304 <description>Device address</description> 24305 <bitOffset>22</bitOffset> 24306 <bitWidth>7</bitWidth> 24307 </field> 24308 <field> 24309 <name>ODDFRM</name> 24310 <description>Odd frame</description> 24311 <bitOffset>29</bitOffset> 24312 <bitWidth>1</bitWidth> 24313 </field> 24314 <field> 24315 <name>CHDIS</name> 24316 <description>Channel disable</description> 24317 <bitOffset>30</bitOffset> 24318 <bitWidth>1</bitWidth> 24319 </field> 24320 <field> 24321 <name>CHENA</name> 24322 <description>Channel enable</description> 24323 <bitOffset>31</bitOffset> 24324 <bitWidth>1</bitWidth> 24325 </field> 24326 </fields> 24327 </register> 24328 <register> 24329 <name>HCINT0</name> 24330 <displayName>HCINT0</displayName> 24331 <description>OTG_FS host channel-0 interrupt register 24332 (OTG_FS_HCINT0)</description> 24333 <addressOffset>0x108</addressOffset> 24334 <size>0x20</size> 24335 <access>read-write</access> 24336 <resetValue>0x00000000</resetValue> 24337 <fields> 24338 <field> 24339 <name>XFRC</name> 24340 <description>Transfer completed</description> 24341 <bitOffset>0</bitOffset> 24342 <bitWidth>1</bitWidth> 24343 </field> 24344 <field> 24345 <name>CHH</name> 24346 <description>Channel halted</description> 24347 <bitOffset>1</bitOffset> 24348 <bitWidth>1</bitWidth> 24349 </field> 24350 <field> 24351 <name>STALL</name> 24352 <description>STALL response received 24353 interrupt</description> 24354 <bitOffset>3</bitOffset> 24355 <bitWidth>1</bitWidth> 24356 </field> 24357 <field> 24358 <name>NAK</name> 24359 <description>NAK response received 24360 interrupt</description> 24361 <bitOffset>4</bitOffset> 24362 <bitWidth>1</bitWidth> 24363 </field> 24364 <field> 24365 <name>ACK</name> 24366 <description>ACK response received/transmitted 24367 interrupt</description> 24368 <bitOffset>5</bitOffset> 24369 <bitWidth>1</bitWidth> 24370 </field> 24371 <field> 24372 <name>TXERR</name> 24373 <description>Transaction error</description> 24374 <bitOffset>7</bitOffset> 24375 <bitWidth>1</bitWidth> 24376 </field> 24377 <field> 24378 <name>BBERR</name> 24379 <description>Babble error</description> 24380 <bitOffset>8</bitOffset> 24381 <bitWidth>1</bitWidth> 24382 </field> 24383 <field> 24384 <name>FRMOR</name> 24385 <description>Frame overrun</description> 24386 <bitOffset>9</bitOffset> 24387 <bitWidth>1</bitWidth> 24388 </field> 24389 <field> 24390 <name>DTERR</name> 24391 <description>Data toggle error</description> 24392 <bitOffset>10</bitOffset> 24393 <bitWidth>1</bitWidth> 24394 </field> 24395 </fields> 24396 </register> 24397 <register> 24398 <name>HCINT1</name> 24399 <displayName>HCINT1</displayName> 24400 <description>OTG_FS host channel-1 interrupt register 24401 (OTG_FS_HCINT1)</description> 24402 <addressOffset>0x128</addressOffset> 24403 <size>0x20</size> 24404 <access>read-write</access> 24405 <resetValue>0x00000000</resetValue> 24406 <fields> 24407 <field> 24408 <name>XFRC</name> 24409 <description>Transfer completed</description> 24410 <bitOffset>0</bitOffset> 24411 <bitWidth>1</bitWidth> 24412 </field> 24413 <field> 24414 <name>CHH</name> 24415 <description>Channel halted</description> 24416 <bitOffset>1</bitOffset> 24417 <bitWidth>1</bitWidth> 24418 </field> 24419 <field> 24420 <name>STALL</name> 24421 <description>STALL response received 24422 interrupt</description> 24423 <bitOffset>3</bitOffset> 24424 <bitWidth>1</bitWidth> 24425 </field> 24426 <field> 24427 <name>NAK</name> 24428 <description>NAK response received 24429 interrupt</description> 24430 <bitOffset>4</bitOffset> 24431 <bitWidth>1</bitWidth> 24432 </field> 24433 <field> 24434 <name>ACK</name> 24435 <description>ACK response received/transmitted 24436 interrupt</description> 24437 <bitOffset>5</bitOffset> 24438 <bitWidth>1</bitWidth> 24439 </field> 24440 <field> 24441 <name>TXERR</name> 24442 <description>Transaction error</description> 24443 <bitOffset>7</bitOffset> 24444 <bitWidth>1</bitWidth> 24445 </field> 24446 <field> 24447 <name>BBERR</name> 24448 <description>Babble error</description> 24449 <bitOffset>8</bitOffset> 24450 <bitWidth>1</bitWidth> 24451 </field> 24452 <field> 24453 <name>FRMOR</name> 24454 <description>Frame overrun</description> 24455 <bitOffset>9</bitOffset> 24456 <bitWidth>1</bitWidth> 24457 </field> 24458 <field> 24459 <name>DTERR</name> 24460 <description>Data toggle error</description> 24461 <bitOffset>10</bitOffset> 24462 <bitWidth>1</bitWidth> 24463 </field> 24464 </fields> 24465 </register> 24466 <register> 24467 <name>HCINT2</name> 24468 <displayName>HCINT2</displayName> 24469 <description>OTG_FS host channel-2 interrupt register 24470 (OTG_FS_HCINT2)</description> 24471 <addressOffset>0x148</addressOffset> 24472 <size>0x20</size> 24473 <access>read-write</access> 24474 <resetValue>0x00000000</resetValue> 24475 <fields> 24476 <field> 24477 <name>XFRC</name> 24478 <description>Transfer completed</description> 24479 <bitOffset>0</bitOffset> 24480 <bitWidth>1</bitWidth> 24481 </field> 24482 <field> 24483 <name>CHH</name> 24484 <description>Channel halted</description> 24485 <bitOffset>1</bitOffset> 24486 <bitWidth>1</bitWidth> 24487 </field> 24488 <field> 24489 <name>STALL</name> 24490 <description>STALL response received 24491 interrupt</description> 24492 <bitOffset>3</bitOffset> 24493 <bitWidth>1</bitWidth> 24494 </field> 24495 <field> 24496 <name>NAK</name> 24497 <description>NAK response received 24498 interrupt</description> 24499 <bitOffset>4</bitOffset> 24500 <bitWidth>1</bitWidth> 24501 </field> 24502 <field> 24503 <name>ACK</name> 24504 <description>ACK response received/transmitted 24505 interrupt</description> 24506 <bitOffset>5</bitOffset> 24507 <bitWidth>1</bitWidth> 24508 </field> 24509 <field> 24510 <name>TXERR</name> 24511 <description>Transaction error</description> 24512 <bitOffset>7</bitOffset> 24513 <bitWidth>1</bitWidth> 24514 </field> 24515 <field> 24516 <name>BBERR</name> 24517 <description>Babble error</description> 24518 <bitOffset>8</bitOffset> 24519 <bitWidth>1</bitWidth> 24520 </field> 24521 <field> 24522 <name>FRMOR</name> 24523 <description>Frame overrun</description> 24524 <bitOffset>9</bitOffset> 24525 <bitWidth>1</bitWidth> 24526 </field> 24527 <field> 24528 <name>DTERR</name> 24529 <description>Data toggle error</description> 24530 <bitOffset>10</bitOffset> 24531 <bitWidth>1</bitWidth> 24532 </field> 24533 </fields> 24534 </register> 24535 <register> 24536 <name>HCINT3</name> 24537 <displayName>HCINT3</displayName> 24538 <description>OTG_FS host channel-3 interrupt register 24539 (OTG_FS_HCINT3)</description> 24540 <addressOffset>0x168</addressOffset> 24541 <size>0x20</size> 24542 <access>read-write</access> 24543 <resetValue>0x00000000</resetValue> 24544 <fields> 24545 <field> 24546 <name>XFRC</name> 24547 <description>Transfer completed</description> 24548 <bitOffset>0</bitOffset> 24549 <bitWidth>1</bitWidth> 24550 </field> 24551 <field> 24552 <name>CHH</name> 24553 <description>Channel halted</description> 24554 <bitOffset>1</bitOffset> 24555 <bitWidth>1</bitWidth> 24556 </field> 24557 <field> 24558 <name>STALL</name> 24559 <description>STALL response received 24560 interrupt</description> 24561 <bitOffset>3</bitOffset> 24562 <bitWidth>1</bitWidth> 24563 </field> 24564 <field> 24565 <name>NAK</name> 24566 <description>NAK response received 24567 interrupt</description> 24568 <bitOffset>4</bitOffset> 24569 <bitWidth>1</bitWidth> 24570 </field> 24571 <field> 24572 <name>ACK</name> 24573 <description>ACK response received/transmitted 24574 interrupt</description> 24575 <bitOffset>5</bitOffset> 24576 <bitWidth>1</bitWidth> 24577 </field> 24578 <field> 24579 <name>TXERR</name> 24580 <description>Transaction error</description> 24581 <bitOffset>7</bitOffset> 24582 <bitWidth>1</bitWidth> 24583 </field> 24584 <field> 24585 <name>BBERR</name> 24586 <description>Babble error</description> 24587 <bitOffset>8</bitOffset> 24588 <bitWidth>1</bitWidth> 24589 </field> 24590 <field> 24591 <name>FRMOR</name> 24592 <description>Frame overrun</description> 24593 <bitOffset>9</bitOffset> 24594 <bitWidth>1</bitWidth> 24595 </field> 24596 <field> 24597 <name>DTERR</name> 24598 <description>Data toggle error</description> 24599 <bitOffset>10</bitOffset> 24600 <bitWidth>1</bitWidth> 24601 </field> 24602 </fields> 24603 </register> 24604 <register> 24605 <name>HCINT4</name> 24606 <displayName>HCINT4</displayName> 24607 <description>OTG_FS host channel-4 interrupt register 24608 (OTG_FS_HCINT4)</description> 24609 <addressOffset>0x188</addressOffset> 24610 <size>0x20</size> 24611 <access>read-write</access> 24612 <resetValue>0x00000000</resetValue> 24613 <fields> 24614 <field> 24615 <name>XFRC</name> 24616 <description>Transfer completed</description> 24617 <bitOffset>0</bitOffset> 24618 <bitWidth>1</bitWidth> 24619 </field> 24620 <field> 24621 <name>CHH</name> 24622 <description>Channel halted</description> 24623 <bitOffset>1</bitOffset> 24624 <bitWidth>1</bitWidth> 24625 </field> 24626 <field> 24627 <name>STALL</name> 24628 <description>STALL response received 24629 interrupt</description> 24630 <bitOffset>3</bitOffset> 24631 <bitWidth>1</bitWidth> 24632 </field> 24633 <field> 24634 <name>NAK</name> 24635 <description>NAK response received 24636 interrupt</description> 24637 <bitOffset>4</bitOffset> 24638 <bitWidth>1</bitWidth> 24639 </field> 24640 <field> 24641 <name>ACK</name> 24642 <description>ACK response received/transmitted 24643 interrupt</description> 24644 <bitOffset>5</bitOffset> 24645 <bitWidth>1</bitWidth> 24646 </field> 24647 <field> 24648 <name>TXERR</name> 24649 <description>Transaction error</description> 24650 <bitOffset>7</bitOffset> 24651 <bitWidth>1</bitWidth> 24652 </field> 24653 <field> 24654 <name>BBERR</name> 24655 <description>Babble error</description> 24656 <bitOffset>8</bitOffset> 24657 <bitWidth>1</bitWidth> 24658 </field> 24659 <field> 24660 <name>FRMOR</name> 24661 <description>Frame overrun</description> 24662 <bitOffset>9</bitOffset> 24663 <bitWidth>1</bitWidth> 24664 </field> 24665 <field> 24666 <name>DTERR</name> 24667 <description>Data toggle error</description> 24668 <bitOffset>10</bitOffset> 24669 <bitWidth>1</bitWidth> 24670 </field> 24671 </fields> 24672 </register> 24673 <register> 24674 <name>HCINT5</name> 24675 <displayName>HCINT5</displayName> 24676 <description>OTG_FS host channel-5 interrupt register 24677 (OTG_FS_HCINT5)</description> 24678 <addressOffset>0x1A8</addressOffset> 24679 <size>0x20</size> 24680 <access>read-write</access> 24681 <resetValue>0x00000000</resetValue> 24682 <fields> 24683 <field> 24684 <name>XFRC</name> 24685 <description>Transfer completed</description> 24686 <bitOffset>0</bitOffset> 24687 <bitWidth>1</bitWidth> 24688 </field> 24689 <field> 24690 <name>CHH</name> 24691 <description>Channel halted</description> 24692 <bitOffset>1</bitOffset> 24693 <bitWidth>1</bitWidth> 24694 </field> 24695 <field> 24696 <name>STALL</name> 24697 <description>STALL response received 24698 interrupt</description> 24699 <bitOffset>3</bitOffset> 24700 <bitWidth>1</bitWidth> 24701 </field> 24702 <field> 24703 <name>NAK</name> 24704 <description>NAK response received 24705 interrupt</description> 24706 <bitOffset>4</bitOffset> 24707 <bitWidth>1</bitWidth> 24708 </field> 24709 <field> 24710 <name>ACK</name> 24711 <description>ACK response received/transmitted 24712 interrupt</description> 24713 <bitOffset>5</bitOffset> 24714 <bitWidth>1</bitWidth> 24715 </field> 24716 <field> 24717 <name>TXERR</name> 24718 <description>Transaction error</description> 24719 <bitOffset>7</bitOffset> 24720 <bitWidth>1</bitWidth> 24721 </field> 24722 <field> 24723 <name>BBERR</name> 24724 <description>Babble error</description> 24725 <bitOffset>8</bitOffset> 24726 <bitWidth>1</bitWidth> 24727 </field> 24728 <field> 24729 <name>FRMOR</name> 24730 <description>Frame overrun</description> 24731 <bitOffset>9</bitOffset> 24732 <bitWidth>1</bitWidth> 24733 </field> 24734 <field> 24735 <name>DTERR</name> 24736 <description>Data toggle error</description> 24737 <bitOffset>10</bitOffset> 24738 <bitWidth>1</bitWidth> 24739 </field> 24740 </fields> 24741 </register> 24742 <register> 24743 <name>HCINT6</name> 24744 <displayName>HCINT6</displayName> 24745 <description>OTG_FS host channel-6 interrupt register 24746 (OTG_FS_HCINT6)</description> 24747 <addressOffset>0x1C8</addressOffset> 24748 <size>0x20</size> 24749 <access>read-write</access> 24750 <resetValue>0x00000000</resetValue> 24751 <fields> 24752 <field> 24753 <name>XFRC</name> 24754 <description>Transfer completed</description> 24755 <bitOffset>0</bitOffset> 24756 <bitWidth>1</bitWidth> 24757 </field> 24758 <field> 24759 <name>CHH</name> 24760 <description>Channel halted</description> 24761 <bitOffset>1</bitOffset> 24762 <bitWidth>1</bitWidth> 24763 </field> 24764 <field> 24765 <name>STALL</name> 24766 <description>STALL response received 24767 interrupt</description> 24768 <bitOffset>3</bitOffset> 24769 <bitWidth>1</bitWidth> 24770 </field> 24771 <field> 24772 <name>NAK</name> 24773 <description>NAK response received 24774 interrupt</description> 24775 <bitOffset>4</bitOffset> 24776 <bitWidth>1</bitWidth> 24777 </field> 24778 <field> 24779 <name>ACK</name> 24780 <description>ACK response received/transmitted 24781 interrupt</description> 24782 <bitOffset>5</bitOffset> 24783 <bitWidth>1</bitWidth> 24784 </field> 24785 <field> 24786 <name>TXERR</name> 24787 <description>Transaction error</description> 24788 <bitOffset>7</bitOffset> 24789 <bitWidth>1</bitWidth> 24790 </field> 24791 <field> 24792 <name>BBERR</name> 24793 <description>Babble error</description> 24794 <bitOffset>8</bitOffset> 24795 <bitWidth>1</bitWidth> 24796 </field> 24797 <field> 24798 <name>FRMOR</name> 24799 <description>Frame overrun</description> 24800 <bitOffset>9</bitOffset> 24801 <bitWidth>1</bitWidth> 24802 </field> 24803 <field> 24804 <name>DTERR</name> 24805 <description>Data toggle error</description> 24806 <bitOffset>10</bitOffset> 24807 <bitWidth>1</bitWidth> 24808 </field> 24809 </fields> 24810 </register> 24811 <register> 24812 <name>HCINT7</name> 24813 <displayName>HCINT7</displayName> 24814 <description>OTG_FS host channel-7 interrupt register 24815 (OTG_FS_HCINT7)</description> 24816 <addressOffset>0x1E8</addressOffset> 24817 <size>0x20</size> 24818 <access>read-write</access> 24819 <resetValue>0x00000000</resetValue> 24820 <fields> 24821 <field> 24822 <name>XFRC</name> 24823 <description>Transfer completed</description> 24824 <bitOffset>0</bitOffset> 24825 <bitWidth>1</bitWidth> 24826 </field> 24827 <field> 24828 <name>CHH</name> 24829 <description>Channel halted</description> 24830 <bitOffset>1</bitOffset> 24831 <bitWidth>1</bitWidth> 24832 </field> 24833 <field> 24834 <name>STALL</name> 24835 <description>STALL response received 24836 interrupt</description> 24837 <bitOffset>3</bitOffset> 24838 <bitWidth>1</bitWidth> 24839 </field> 24840 <field> 24841 <name>NAK</name> 24842 <description>NAK response received 24843 interrupt</description> 24844 <bitOffset>4</bitOffset> 24845 <bitWidth>1</bitWidth> 24846 </field> 24847 <field> 24848 <name>ACK</name> 24849 <description>ACK response received/transmitted 24850 interrupt</description> 24851 <bitOffset>5</bitOffset> 24852 <bitWidth>1</bitWidth> 24853 </field> 24854 <field> 24855 <name>TXERR</name> 24856 <description>Transaction error</description> 24857 <bitOffset>7</bitOffset> 24858 <bitWidth>1</bitWidth> 24859 </field> 24860 <field> 24861 <name>BBERR</name> 24862 <description>Babble error</description> 24863 <bitOffset>8</bitOffset> 24864 <bitWidth>1</bitWidth> 24865 </field> 24866 <field> 24867 <name>FRMOR</name> 24868 <description>Frame overrun</description> 24869 <bitOffset>9</bitOffset> 24870 <bitWidth>1</bitWidth> 24871 </field> 24872 <field> 24873 <name>DTERR</name> 24874 <description>Data toggle error</description> 24875 <bitOffset>10</bitOffset> 24876 <bitWidth>1</bitWidth> 24877 </field> 24878 </fields> 24879 </register> 24880 <register> 24881 <name>HCINTMSK0</name> 24882 <displayName>HCINTMSK0</displayName> 24883 <description>OTG_FS host channel-0 mask register 24884 (OTG_FS_HCINTMSK0)</description> 24885 <addressOffset>0x10C</addressOffset> 24886 <size>0x20</size> 24887 <access>read-write</access> 24888 <resetValue>0x00000000</resetValue> 24889 <fields> 24890 <field> 24891 <name>XFRCM</name> 24892 <description>Transfer completed mask</description> 24893 <bitOffset>0</bitOffset> 24894 <bitWidth>1</bitWidth> 24895 </field> 24896 <field> 24897 <name>CHHM</name> 24898 <description>Channel halted mask</description> 24899 <bitOffset>1</bitOffset> 24900 <bitWidth>1</bitWidth> 24901 </field> 24902 <field> 24903 <name>STALLM</name> 24904 <description>STALL response received interrupt 24905 mask</description> 24906 <bitOffset>3</bitOffset> 24907 <bitWidth>1</bitWidth> 24908 </field> 24909 <field> 24910 <name>NAKM</name> 24911 <description>NAK response received interrupt 24912 mask</description> 24913 <bitOffset>4</bitOffset> 24914 <bitWidth>1</bitWidth> 24915 </field> 24916 <field> 24917 <name>ACKM</name> 24918 <description>ACK response received/transmitted 24919 interrupt mask</description> 24920 <bitOffset>5</bitOffset> 24921 <bitWidth>1</bitWidth> 24922 </field> 24923 <field> 24924 <name>NYET</name> 24925 <description>response received interrupt 24926 mask</description> 24927 <bitOffset>6</bitOffset> 24928 <bitWidth>1</bitWidth> 24929 </field> 24930 <field> 24931 <name>TXERRM</name> 24932 <description>Transaction error mask</description> 24933 <bitOffset>7</bitOffset> 24934 <bitWidth>1</bitWidth> 24935 </field> 24936 <field> 24937 <name>BBERRM</name> 24938 <description>Babble error mask</description> 24939 <bitOffset>8</bitOffset> 24940 <bitWidth>1</bitWidth> 24941 </field> 24942 <field> 24943 <name>FRMORM</name> 24944 <description>Frame overrun mask</description> 24945 <bitOffset>9</bitOffset> 24946 <bitWidth>1</bitWidth> 24947 </field> 24948 <field> 24949 <name>DTERRM</name> 24950 <description>Data toggle error mask</description> 24951 <bitOffset>10</bitOffset> 24952 <bitWidth>1</bitWidth> 24953 </field> 24954 </fields> 24955 </register> 24956 <register> 24957 <name>HCINTMSK1</name> 24958 <displayName>HCINTMSK1</displayName> 24959 <description>OTG_FS host channel-1 mask register 24960 (OTG_FS_HCINTMSK1)</description> 24961 <addressOffset>0x12C</addressOffset> 24962 <size>0x20</size> 24963 <access>read-write</access> 24964 <resetValue>0x00000000</resetValue> 24965 <fields> 24966 <field> 24967 <name>XFRCM</name> 24968 <description>Transfer completed mask</description> 24969 <bitOffset>0</bitOffset> 24970 <bitWidth>1</bitWidth> 24971 </field> 24972 <field> 24973 <name>CHHM</name> 24974 <description>Channel halted mask</description> 24975 <bitOffset>1</bitOffset> 24976 <bitWidth>1</bitWidth> 24977 </field> 24978 <field> 24979 <name>STALLM</name> 24980 <description>STALL response received interrupt 24981 mask</description> 24982 <bitOffset>3</bitOffset> 24983 <bitWidth>1</bitWidth> 24984 </field> 24985 <field> 24986 <name>NAKM</name> 24987 <description>NAK response received interrupt 24988 mask</description> 24989 <bitOffset>4</bitOffset> 24990 <bitWidth>1</bitWidth> 24991 </field> 24992 <field> 24993 <name>ACKM</name> 24994 <description>ACK response received/transmitted 24995 interrupt mask</description> 24996 <bitOffset>5</bitOffset> 24997 <bitWidth>1</bitWidth> 24998 </field> 24999 <field> 25000 <name>NYET</name> 25001 <description>response received interrupt 25002 mask</description> 25003 <bitOffset>6</bitOffset> 25004 <bitWidth>1</bitWidth> 25005 </field> 25006 <field> 25007 <name>TXERRM</name> 25008 <description>Transaction error mask</description> 25009 <bitOffset>7</bitOffset> 25010 <bitWidth>1</bitWidth> 25011 </field> 25012 <field> 25013 <name>BBERRM</name> 25014 <description>Babble error mask</description> 25015 <bitOffset>8</bitOffset> 25016 <bitWidth>1</bitWidth> 25017 </field> 25018 <field> 25019 <name>FRMORM</name> 25020 <description>Frame overrun mask</description> 25021 <bitOffset>9</bitOffset> 25022 <bitWidth>1</bitWidth> 25023 </field> 25024 <field> 25025 <name>DTERRM</name> 25026 <description>Data toggle error mask</description> 25027 <bitOffset>10</bitOffset> 25028 <bitWidth>1</bitWidth> 25029 </field> 25030 </fields> 25031 </register> 25032 <register> 25033 <name>HCINTMSK2</name> 25034 <displayName>HCINTMSK2</displayName> 25035 <description>OTG_FS host channel-2 mask register 25036 (OTG_FS_HCINTMSK2)</description> 25037 <addressOffset>0x14C</addressOffset> 25038 <size>0x20</size> 25039 <access>read-write</access> 25040 <resetValue>0x00000000</resetValue> 25041 <fields> 25042 <field> 25043 <name>XFRCM</name> 25044 <description>Transfer completed mask</description> 25045 <bitOffset>0</bitOffset> 25046 <bitWidth>1</bitWidth> 25047 </field> 25048 <field> 25049 <name>CHHM</name> 25050 <description>Channel halted mask</description> 25051 <bitOffset>1</bitOffset> 25052 <bitWidth>1</bitWidth> 25053 </field> 25054 <field> 25055 <name>STALLM</name> 25056 <description>STALL response received interrupt 25057 mask</description> 25058 <bitOffset>3</bitOffset> 25059 <bitWidth>1</bitWidth> 25060 </field> 25061 <field> 25062 <name>NAKM</name> 25063 <description>NAK response received interrupt 25064 mask</description> 25065 <bitOffset>4</bitOffset> 25066 <bitWidth>1</bitWidth> 25067 </field> 25068 <field> 25069 <name>ACKM</name> 25070 <description>ACK response received/transmitted 25071 interrupt mask</description> 25072 <bitOffset>5</bitOffset> 25073 <bitWidth>1</bitWidth> 25074 </field> 25075 <field> 25076 <name>NYET</name> 25077 <description>response received interrupt 25078 mask</description> 25079 <bitOffset>6</bitOffset> 25080 <bitWidth>1</bitWidth> 25081 </field> 25082 <field> 25083 <name>TXERRM</name> 25084 <description>Transaction error mask</description> 25085 <bitOffset>7</bitOffset> 25086 <bitWidth>1</bitWidth> 25087 </field> 25088 <field> 25089 <name>BBERRM</name> 25090 <description>Babble error mask</description> 25091 <bitOffset>8</bitOffset> 25092 <bitWidth>1</bitWidth> 25093 </field> 25094 <field> 25095 <name>FRMORM</name> 25096 <description>Frame overrun mask</description> 25097 <bitOffset>9</bitOffset> 25098 <bitWidth>1</bitWidth> 25099 </field> 25100 <field> 25101 <name>DTERRM</name> 25102 <description>Data toggle error mask</description> 25103 <bitOffset>10</bitOffset> 25104 <bitWidth>1</bitWidth> 25105 </field> 25106 </fields> 25107 </register> 25108 <register> 25109 <name>HCINTMSK3</name> 25110 <displayName>HCINTMSK3</displayName> 25111 <description>OTG_FS host channel-3 mask register 25112 (OTG_FS_HCINTMSK3)</description> 25113 <addressOffset>0x16C</addressOffset> 25114 <size>0x20</size> 25115 <access>read-write</access> 25116 <resetValue>0x00000000</resetValue> 25117 <fields> 25118 <field> 25119 <name>XFRCM</name> 25120 <description>Transfer completed mask</description> 25121 <bitOffset>0</bitOffset> 25122 <bitWidth>1</bitWidth> 25123 </field> 25124 <field> 25125 <name>CHHM</name> 25126 <description>Channel halted mask</description> 25127 <bitOffset>1</bitOffset> 25128 <bitWidth>1</bitWidth> 25129 </field> 25130 <field> 25131 <name>STALLM</name> 25132 <description>STALL response received interrupt 25133 mask</description> 25134 <bitOffset>3</bitOffset> 25135 <bitWidth>1</bitWidth> 25136 </field> 25137 <field> 25138 <name>NAKM</name> 25139 <description>NAK response received interrupt 25140 mask</description> 25141 <bitOffset>4</bitOffset> 25142 <bitWidth>1</bitWidth> 25143 </field> 25144 <field> 25145 <name>ACKM</name> 25146 <description>ACK response received/transmitted 25147 interrupt mask</description> 25148 <bitOffset>5</bitOffset> 25149 <bitWidth>1</bitWidth> 25150 </field> 25151 <field> 25152 <name>NYET</name> 25153 <description>response received interrupt 25154 mask</description> 25155 <bitOffset>6</bitOffset> 25156 <bitWidth>1</bitWidth> 25157 </field> 25158 <field> 25159 <name>TXERRM</name> 25160 <description>Transaction error mask</description> 25161 <bitOffset>7</bitOffset> 25162 <bitWidth>1</bitWidth> 25163 </field> 25164 <field> 25165 <name>BBERRM</name> 25166 <description>Babble error mask</description> 25167 <bitOffset>8</bitOffset> 25168 <bitWidth>1</bitWidth> 25169 </field> 25170 <field> 25171 <name>FRMORM</name> 25172 <description>Frame overrun mask</description> 25173 <bitOffset>9</bitOffset> 25174 <bitWidth>1</bitWidth> 25175 </field> 25176 <field> 25177 <name>DTERRM</name> 25178 <description>Data toggle error mask</description> 25179 <bitOffset>10</bitOffset> 25180 <bitWidth>1</bitWidth> 25181 </field> 25182 </fields> 25183 </register> 25184 <register> 25185 <name>HCINTMSK4</name> 25186 <displayName>HCINTMSK4</displayName> 25187 <description>OTG_FS host channel-4 mask register 25188 (OTG_FS_HCINTMSK4)</description> 25189 <addressOffset>0x18C</addressOffset> 25190 <size>0x20</size> 25191 <access>read-write</access> 25192 <resetValue>0x00000000</resetValue> 25193 <fields> 25194 <field> 25195 <name>XFRCM</name> 25196 <description>Transfer completed mask</description> 25197 <bitOffset>0</bitOffset> 25198 <bitWidth>1</bitWidth> 25199 </field> 25200 <field> 25201 <name>CHHM</name> 25202 <description>Channel halted mask</description> 25203 <bitOffset>1</bitOffset> 25204 <bitWidth>1</bitWidth> 25205 </field> 25206 <field> 25207 <name>STALLM</name> 25208 <description>STALL response received interrupt 25209 mask</description> 25210 <bitOffset>3</bitOffset> 25211 <bitWidth>1</bitWidth> 25212 </field> 25213 <field> 25214 <name>NAKM</name> 25215 <description>NAK response received interrupt 25216 mask</description> 25217 <bitOffset>4</bitOffset> 25218 <bitWidth>1</bitWidth> 25219 </field> 25220 <field> 25221 <name>ACKM</name> 25222 <description>ACK response received/transmitted 25223 interrupt mask</description> 25224 <bitOffset>5</bitOffset> 25225 <bitWidth>1</bitWidth> 25226 </field> 25227 <field> 25228 <name>NYET</name> 25229 <description>response received interrupt 25230 mask</description> 25231 <bitOffset>6</bitOffset> 25232 <bitWidth>1</bitWidth> 25233 </field> 25234 <field> 25235 <name>TXERRM</name> 25236 <description>Transaction error mask</description> 25237 <bitOffset>7</bitOffset> 25238 <bitWidth>1</bitWidth> 25239 </field> 25240 <field> 25241 <name>BBERRM</name> 25242 <description>Babble error mask</description> 25243 <bitOffset>8</bitOffset> 25244 <bitWidth>1</bitWidth> 25245 </field> 25246 <field> 25247 <name>FRMORM</name> 25248 <description>Frame overrun mask</description> 25249 <bitOffset>9</bitOffset> 25250 <bitWidth>1</bitWidth> 25251 </field> 25252 <field> 25253 <name>DTERRM</name> 25254 <description>Data toggle error mask</description> 25255 <bitOffset>10</bitOffset> 25256 <bitWidth>1</bitWidth> 25257 </field> 25258 </fields> 25259 </register> 25260 <register> 25261 <name>HCINTMSK5</name> 25262 <displayName>HCINTMSK5</displayName> 25263 <description>OTG_FS host channel-5 mask register 25264 (OTG_FS_HCINTMSK5)</description> 25265 <addressOffset>0x1AC</addressOffset> 25266 <size>0x20</size> 25267 <access>read-write</access> 25268 <resetValue>0x00000000</resetValue> 25269 <fields> 25270 <field> 25271 <name>XFRCM</name> 25272 <description>Transfer completed mask</description> 25273 <bitOffset>0</bitOffset> 25274 <bitWidth>1</bitWidth> 25275 </field> 25276 <field> 25277 <name>CHHM</name> 25278 <description>Channel halted mask</description> 25279 <bitOffset>1</bitOffset> 25280 <bitWidth>1</bitWidth> 25281 </field> 25282 <field> 25283 <name>STALLM</name> 25284 <description>STALL response received interrupt 25285 mask</description> 25286 <bitOffset>3</bitOffset> 25287 <bitWidth>1</bitWidth> 25288 </field> 25289 <field> 25290 <name>NAKM</name> 25291 <description>NAK response received interrupt 25292 mask</description> 25293 <bitOffset>4</bitOffset> 25294 <bitWidth>1</bitWidth> 25295 </field> 25296 <field> 25297 <name>ACKM</name> 25298 <description>ACK response received/transmitted 25299 interrupt mask</description> 25300 <bitOffset>5</bitOffset> 25301 <bitWidth>1</bitWidth> 25302 </field> 25303 <field> 25304 <name>NYET</name> 25305 <description>response received interrupt 25306 mask</description> 25307 <bitOffset>6</bitOffset> 25308 <bitWidth>1</bitWidth> 25309 </field> 25310 <field> 25311 <name>TXERRM</name> 25312 <description>Transaction error mask</description> 25313 <bitOffset>7</bitOffset> 25314 <bitWidth>1</bitWidth> 25315 </field> 25316 <field> 25317 <name>BBERRM</name> 25318 <description>Babble error mask</description> 25319 <bitOffset>8</bitOffset> 25320 <bitWidth>1</bitWidth> 25321 </field> 25322 <field> 25323 <name>FRMORM</name> 25324 <description>Frame overrun mask</description> 25325 <bitOffset>9</bitOffset> 25326 <bitWidth>1</bitWidth> 25327 </field> 25328 <field> 25329 <name>DTERRM</name> 25330 <description>Data toggle error mask</description> 25331 <bitOffset>10</bitOffset> 25332 <bitWidth>1</bitWidth> 25333 </field> 25334 </fields> 25335 </register> 25336 <register> 25337 <name>HCINTMSK6</name> 25338 <displayName>HCINTMSK6</displayName> 25339 <description>OTG_FS host channel-6 mask register 25340 (OTG_FS_HCINTMSK6)</description> 25341 <addressOffset>0x1CC</addressOffset> 25342 <size>0x20</size> 25343 <access>read-write</access> 25344 <resetValue>0x00000000</resetValue> 25345 <fields> 25346 <field> 25347 <name>XFRCM</name> 25348 <description>Transfer completed mask</description> 25349 <bitOffset>0</bitOffset> 25350 <bitWidth>1</bitWidth> 25351 </field> 25352 <field> 25353 <name>CHHM</name> 25354 <description>Channel halted mask</description> 25355 <bitOffset>1</bitOffset> 25356 <bitWidth>1</bitWidth> 25357 </field> 25358 <field> 25359 <name>STALLM</name> 25360 <description>STALL response received interrupt 25361 mask</description> 25362 <bitOffset>3</bitOffset> 25363 <bitWidth>1</bitWidth> 25364 </field> 25365 <field> 25366 <name>NAKM</name> 25367 <description>NAK response received interrupt 25368 mask</description> 25369 <bitOffset>4</bitOffset> 25370 <bitWidth>1</bitWidth> 25371 </field> 25372 <field> 25373 <name>ACKM</name> 25374 <description>ACK response received/transmitted 25375 interrupt mask</description> 25376 <bitOffset>5</bitOffset> 25377 <bitWidth>1</bitWidth> 25378 </field> 25379 <field> 25380 <name>NYET</name> 25381 <description>response received interrupt 25382 mask</description> 25383 <bitOffset>6</bitOffset> 25384 <bitWidth>1</bitWidth> 25385 </field> 25386 <field> 25387 <name>TXERRM</name> 25388 <description>Transaction error mask</description> 25389 <bitOffset>7</bitOffset> 25390 <bitWidth>1</bitWidth> 25391 </field> 25392 <field> 25393 <name>BBERRM</name> 25394 <description>Babble error mask</description> 25395 <bitOffset>8</bitOffset> 25396 <bitWidth>1</bitWidth> 25397 </field> 25398 <field> 25399 <name>FRMORM</name> 25400 <description>Frame overrun mask</description> 25401 <bitOffset>9</bitOffset> 25402 <bitWidth>1</bitWidth> 25403 </field> 25404 <field> 25405 <name>DTERRM</name> 25406 <description>Data toggle error mask</description> 25407 <bitOffset>10</bitOffset> 25408 <bitWidth>1</bitWidth> 25409 </field> 25410 </fields> 25411 </register> 25412 <register> 25413 <name>HCINTMSK7</name> 25414 <displayName>HCINTMSK7</displayName> 25415 <description>OTG_FS host channel-7 mask register 25416 (OTG_FS_HCINTMSK7)</description> 25417 <addressOffset>0x1EC</addressOffset> 25418 <size>0x20</size> 25419 <access>read-write</access> 25420 <resetValue>0x00000000</resetValue> 25421 <fields> 25422 <field> 25423 <name>XFRCM</name> 25424 <description>Transfer completed mask</description> 25425 <bitOffset>0</bitOffset> 25426 <bitWidth>1</bitWidth> 25427 </field> 25428 <field> 25429 <name>CHHM</name> 25430 <description>Channel halted mask</description> 25431 <bitOffset>1</bitOffset> 25432 <bitWidth>1</bitWidth> 25433 </field> 25434 <field> 25435 <name>STALLM</name> 25436 <description>STALL response received interrupt 25437 mask</description> 25438 <bitOffset>3</bitOffset> 25439 <bitWidth>1</bitWidth> 25440 </field> 25441 <field> 25442 <name>NAKM</name> 25443 <description>NAK response received interrupt 25444 mask</description> 25445 <bitOffset>4</bitOffset> 25446 <bitWidth>1</bitWidth> 25447 </field> 25448 <field> 25449 <name>ACKM</name> 25450 <description>ACK response received/transmitted 25451 interrupt mask</description> 25452 <bitOffset>5</bitOffset> 25453 <bitWidth>1</bitWidth> 25454 </field> 25455 <field> 25456 <name>NYET</name> 25457 <description>response received interrupt 25458 mask</description> 25459 <bitOffset>6</bitOffset> 25460 <bitWidth>1</bitWidth> 25461 </field> 25462 <field> 25463 <name>TXERRM</name> 25464 <description>Transaction error mask</description> 25465 <bitOffset>7</bitOffset> 25466 <bitWidth>1</bitWidth> 25467 </field> 25468 <field> 25469 <name>BBERRM</name> 25470 <description>Babble error mask</description> 25471 <bitOffset>8</bitOffset> 25472 <bitWidth>1</bitWidth> 25473 </field> 25474 <field> 25475 <name>FRMORM</name> 25476 <description>Frame overrun mask</description> 25477 <bitOffset>9</bitOffset> 25478 <bitWidth>1</bitWidth> 25479 </field> 25480 <field> 25481 <name>DTERRM</name> 25482 <description>Data toggle error mask</description> 25483 <bitOffset>10</bitOffset> 25484 <bitWidth>1</bitWidth> 25485 </field> 25486 </fields> 25487 </register> 25488 <register> 25489 <name>HCTSIZ0</name> 25490 <displayName>HCTSIZ0</displayName> 25491 <description>OTG_FS host channel-0 transfer size 25492 register</description> 25493 <addressOffset>0x110</addressOffset> 25494 <size>0x20</size> 25495 <access>read-write</access> 25496 <resetValue>0x00000000</resetValue> 25497 <fields> 25498 <field> 25499 <name>XFRSIZ</name> 25500 <description>Transfer size</description> 25501 <bitOffset>0</bitOffset> 25502 <bitWidth>19</bitWidth> 25503 </field> 25504 <field> 25505 <name>PKTCNT</name> 25506 <description>Packet count</description> 25507 <bitOffset>19</bitOffset> 25508 <bitWidth>10</bitWidth> 25509 </field> 25510 <field> 25511 <name>DPID</name> 25512 <description>Data PID</description> 25513 <bitOffset>29</bitOffset> 25514 <bitWidth>2</bitWidth> 25515 </field> 25516 </fields> 25517 </register> 25518 <register> 25519 <name>HCTSIZ1</name> 25520 <displayName>HCTSIZ1</displayName> 25521 <description>OTG_FS host channel-1 transfer size 25522 register</description> 25523 <addressOffset>0x130</addressOffset> 25524 <size>0x20</size> 25525 <access>read-write</access> 25526 <resetValue>0x00000000</resetValue> 25527 <fields> 25528 <field> 25529 <name>XFRSIZ</name> 25530 <description>Transfer size</description> 25531 <bitOffset>0</bitOffset> 25532 <bitWidth>19</bitWidth> 25533 </field> 25534 <field> 25535 <name>PKTCNT</name> 25536 <description>Packet count</description> 25537 <bitOffset>19</bitOffset> 25538 <bitWidth>10</bitWidth> 25539 </field> 25540 <field> 25541 <name>DPID</name> 25542 <description>Data PID</description> 25543 <bitOffset>29</bitOffset> 25544 <bitWidth>2</bitWidth> 25545 </field> 25546 </fields> 25547 </register> 25548 <register> 25549 <name>HCTSIZ2</name> 25550 <displayName>HCTSIZ2</displayName> 25551 <description>OTG_FS host channel-2 transfer size 25552 register</description> 25553 <addressOffset>0x150</addressOffset> 25554 <size>0x20</size> 25555 <access>read-write</access> 25556 <resetValue>0x00000000</resetValue> 25557 <fields> 25558 <field> 25559 <name>XFRSIZ</name> 25560 <description>Transfer size</description> 25561 <bitOffset>0</bitOffset> 25562 <bitWidth>19</bitWidth> 25563 </field> 25564 <field> 25565 <name>PKTCNT</name> 25566 <description>Packet count</description> 25567 <bitOffset>19</bitOffset> 25568 <bitWidth>10</bitWidth> 25569 </field> 25570 <field> 25571 <name>DPID</name> 25572 <description>Data PID</description> 25573 <bitOffset>29</bitOffset> 25574 <bitWidth>2</bitWidth> 25575 </field> 25576 </fields> 25577 </register> 25578 <register> 25579 <name>HCTSIZ3</name> 25580 <displayName>HCTSIZ3</displayName> 25581 <description>OTG_FS host channel-3 transfer size 25582 register</description> 25583 <addressOffset>0x170</addressOffset> 25584 <size>0x20</size> 25585 <access>read-write</access> 25586 <resetValue>0x00000000</resetValue> 25587 <fields> 25588 <field> 25589 <name>XFRSIZ</name> 25590 <description>Transfer size</description> 25591 <bitOffset>0</bitOffset> 25592 <bitWidth>19</bitWidth> 25593 </field> 25594 <field> 25595 <name>PKTCNT</name> 25596 <description>Packet count</description> 25597 <bitOffset>19</bitOffset> 25598 <bitWidth>10</bitWidth> 25599 </field> 25600 <field> 25601 <name>DPID</name> 25602 <description>Data PID</description> 25603 <bitOffset>29</bitOffset> 25604 <bitWidth>2</bitWidth> 25605 </field> 25606 </fields> 25607 </register> 25608 <register> 25609 <name>HCTSIZ4</name> 25610 <displayName>HCTSIZ4</displayName> 25611 <description>OTG_FS host channel-x transfer size 25612 register</description> 25613 <addressOffset>0x190</addressOffset> 25614 <size>0x20</size> 25615 <access>read-write</access> 25616 <resetValue>0x00000000</resetValue> 25617 <fields> 25618 <field> 25619 <name>XFRSIZ</name> 25620 <description>Transfer size</description> 25621 <bitOffset>0</bitOffset> 25622 <bitWidth>19</bitWidth> 25623 </field> 25624 <field> 25625 <name>PKTCNT</name> 25626 <description>Packet count</description> 25627 <bitOffset>19</bitOffset> 25628 <bitWidth>10</bitWidth> 25629 </field> 25630 <field> 25631 <name>DPID</name> 25632 <description>Data PID</description> 25633 <bitOffset>29</bitOffset> 25634 <bitWidth>2</bitWidth> 25635 </field> 25636 </fields> 25637 </register> 25638 <register> 25639 <name>HCTSIZ5</name> 25640 <displayName>HCTSIZ5</displayName> 25641 <description>OTG_FS host channel-5 transfer size 25642 register</description> 25643 <addressOffset>0x1B0</addressOffset> 25644 <size>0x20</size> 25645 <access>read-write</access> 25646 <resetValue>0x00000000</resetValue> 25647 <fields> 25648 <field> 25649 <name>XFRSIZ</name> 25650 <description>Transfer size</description> 25651 <bitOffset>0</bitOffset> 25652 <bitWidth>19</bitWidth> 25653 </field> 25654 <field> 25655 <name>PKTCNT</name> 25656 <description>Packet count</description> 25657 <bitOffset>19</bitOffset> 25658 <bitWidth>10</bitWidth> 25659 </field> 25660 <field> 25661 <name>DPID</name> 25662 <description>Data PID</description> 25663 <bitOffset>29</bitOffset> 25664 <bitWidth>2</bitWidth> 25665 </field> 25666 </fields> 25667 </register> 25668 <register> 25669 <name>HCTSIZ6</name> 25670 <displayName>HCTSIZ6</displayName> 25671 <description>OTG_FS host channel-6 transfer size 25672 register</description> 25673 <addressOffset>0x1D0</addressOffset> 25674 <size>0x20</size> 25675 <access>read-write</access> 25676 <resetValue>0x00000000</resetValue> 25677 <fields> 25678 <field> 25679 <name>XFRSIZ</name> 25680 <description>Transfer size</description> 25681 <bitOffset>0</bitOffset> 25682 <bitWidth>19</bitWidth> 25683 </field> 25684 <field> 25685 <name>PKTCNT</name> 25686 <description>Packet count</description> 25687 <bitOffset>19</bitOffset> 25688 <bitWidth>10</bitWidth> 25689 </field> 25690 <field> 25691 <name>DPID</name> 25692 <description>Data PID</description> 25693 <bitOffset>29</bitOffset> 25694 <bitWidth>2</bitWidth> 25695 </field> 25696 </fields> 25697 </register> 25698 <register> 25699 <name>HCTSIZ7</name> 25700 <displayName>HCTSIZ7</displayName> 25701 <description>OTG_FS host channel-7 transfer size 25702 register</description> 25703 <addressOffset>0x1F0</addressOffset> 25704 <size>0x20</size> 25705 <access>read-write</access> 25706 <resetValue>0x00000000</resetValue> 25707 <fields> 25708 <field> 25709 <name>XFRSIZ</name> 25710 <description>Transfer size</description> 25711 <bitOffset>0</bitOffset> 25712 <bitWidth>19</bitWidth> 25713 </field> 25714 <field> 25715 <name>PKTCNT</name> 25716 <description>Packet count</description> 25717 <bitOffset>19</bitOffset> 25718 <bitWidth>10</bitWidth> 25719 </field> 25720 <field> 25721 <name>DPID</name> 25722 <description>Data PID</description> 25723 <bitOffset>29</bitOffset> 25724 <bitWidth>2</bitWidth> 25725 </field> 25726 </fields> 25727 </register> 25728 </registers> 25729 </peripheral> 25730 <peripheral> 25731 <name>OTG_FS_DEVICE</name> 25732 <description>USB on the go full speed</description> 25733 <groupName>USB_OTG_FS</groupName> 25734 <baseAddress>0x50000800</baseAddress> 25735 <addressBlock> 25736 <offset>0x0</offset> 25737 <size>0x400</size> 25738 <usage>registers</usage> 25739 </addressBlock> 25740 <registers> 25741 <register> 25742 <name>DCFG</name> 25743 <displayName>DCFG</displayName> 25744 <description>OTG_FS device configuration register 25745 (OTG_FS_DCFG)</description> 25746 <addressOffset>0x0</addressOffset> 25747 <size>0x20</size> 25748 <access>read-write</access> 25749 <resetValue>0x02200000</resetValue> 25750 <fields> 25751 <field> 25752 <name>DSPD</name> 25753 <description>Device speed</description> 25754 <bitOffset>0</bitOffset> 25755 <bitWidth>2</bitWidth> 25756 </field> 25757 <field> 25758 <name>NZLSOHSK</name> 25759 <description>Non-zero-length status OUT 25760 handshake</description> 25761 <bitOffset>2</bitOffset> 25762 <bitWidth>1</bitWidth> 25763 </field> 25764 <field> 25765 <name>DAD</name> 25766 <description>Device address</description> 25767 <bitOffset>4</bitOffset> 25768 <bitWidth>7</bitWidth> 25769 </field> 25770 <field> 25771 <name>PFIVL</name> 25772 <description>Periodic frame interval</description> 25773 <bitOffset>11</bitOffset> 25774 <bitWidth>2</bitWidth> 25775 </field> 25776 </fields> 25777 </register> 25778 <register> 25779 <name>DCTL</name> 25780 <displayName>DCTL</displayName> 25781 <description>OTG_FS device control register 25782 (OTG_FS_DCTL)</description> 25783 <addressOffset>0x4</addressOffset> 25784 <size>0x20</size> 25785 <resetValue>0x00000000</resetValue> 25786 <fields> 25787 <field> 25788 <name>RWUSIG</name> 25789 <description>Remote wakeup signaling</description> 25790 <bitOffset>0</bitOffset> 25791 <bitWidth>1</bitWidth> 25792 <access>read-write</access> 25793 </field> 25794 <field> 25795 <name>SDIS</name> 25796 <description>Soft disconnect</description> 25797 <bitOffset>1</bitOffset> 25798 <bitWidth>1</bitWidth> 25799 <access>read-write</access> 25800 </field> 25801 <field> 25802 <name>GINSTS</name> 25803 <description>Global IN NAK status</description> 25804 <bitOffset>2</bitOffset> 25805 <bitWidth>1</bitWidth> 25806 <access>read-only</access> 25807 </field> 25808 <field> 25809 <name>GONSTS</name> 25810 <description>Global OUT NAK status</description> 25811 <bitOffset>3</bitOffset> 25812 <bitWidth>1</bitWidth> 25813 <access>read-only</access> 25814 </field> 25815 <field> 25816 <name>TCTL</name> 25817 <description>Test control</description> 25818 <bitOffset>4</bitOffset> 25819 <bitWidth>3</bitWidth> 25820 <access>read-write</access> 25821 </field> 25822 <field> 25823 <name>SGINAK</name> 25824 <description>Set global IN NAK</description> 25825 <bitOffset>7</bitOffset> 25826 <bitWidth>1</bitWidth> 25827 <access>read-write</access> 25828 </field> 25829 <field> 25830 <name>CGINAK</name> 25831 <description>Clear global IN NAK</description> 25832 <bitOffset>8</bitOffset> 25833 <bitWidth>1</bitWidth> 25834 <access>read-write</access> 25835 </field> 25836 <field> 25837 <name>SGONAK</name> 25838 <description>Set global OUT NAK</description> 25839 <bitOffset>9</bitOffset> 25840 <bitWidth>1</bitWidth> 25841 <access>read-write</access> 25842 </field> 25843 <field> 25844 <name>CGONAK</name> 25845 <description>Clear global OUT NAK</description> 25846 <bitOffset>10</bitOffset> 25847 <bitWidth>1</bitWidth> 25848 <access>read-write</access> 25849 </field> 25850 <field> 25851 <name>POPRGDNE</name> 25852 <description>Power-on programming done</description> 25853 <bitOffset>11</bitOffset> 25854 <bitWidth>1</bitWidth> 25855 <access>read-write</access> 25856 </field> 25857 </fields> 25858 </register> 25859 <register> 25860 <name>DSTS</name> 25861 <displayName>DSTS</displayName> 25862 <description>OTG_FS device status register 25863 (OTG_FS_DSTS)</description> 25864 <addressOffset>0x8</addressOffset> 25865 <size>0x20</size> 25866 <access>read-only</access> 25867 <resetValue>0x00000010</resetValue> 25868 <fields> 25869 <field> 25870 <name>SUSPSTS</name> 25871 <description>Suspend status</description> 25872 <bitOffset>0</bitOffset> 25873 <bitWidth>1</bitWidth> 25874 </field> 25875 <field> 25876 <name>ENUMSPD</name> 25877 <description>Enumerated speed</description> 25878 <bitOffset>1</bitOffset> 25879 <bitWidth>2</bitWidth> 25880 </field> 25881 <field> 25882 <name>EERR</name> 25883 <description>Erratic error</description> 25884 <bitOffset>3</bitOffset> 25885 <bitWidth>1</bitWidth> 25886 </field> 25887 <field> 25888 <name>FNSOF</name> 25889 <description>Frame number of the received 25890 SOF</description> 25891 <bitOffset>8</bitOffset> 25892 <bitWidth>14</bitWidth> 25893 </field> 25894 </fields> 25895 </register> 25896 <register> 25897 <name>DIEPMSK</name> 25898 <displayName>DIEPMSK</displayName> 25899 <description>OTG_FS device IN endpoint common interrupt 25900 mask register (OTG_FS_DIEPMSK)</description> 25901 <addressOffset>0x10</addressOffset> 25902 <size>0x20</size> 25903 <access>read-write</access> 25904 <resetValue>0x00000000</resetValue> 25905 <fields> 25906 <field> 25907 <name>XFRCM</name> 25908 <description>Transfer completed interrupt 25909 mask</description> 25910 <bitOffset>0</bitOffset> 25911 <bitWidth>1</bitWidth> 25912 </field> 25913 <field> 25914 <name>EPDM</name> 25915 <description>Endpoint disabled interrupt 25916 mask</description> 25917 <bitOffset>1</bitOffset> 25918 <bitWidth>1</bitWidth> 25919 </field> 25920 <field> 25921 <name>TOM</name> 25922 <description>Timeout condition mask (Non-isochronous 25923 endpoints)</description> 25924 <bitOffset>3</bitOffset> 25925 <bitWidth>1</bitWidth> 25926 </field> 25927 <field> 25928 <name>ITTXFEMSK</name> 25929 <description>IN token received when TxFIFO empty 25930 mask</description> 25931 <bitOffset>4</bitOffset> 25932 <bitWidth>1</bitWidth> 25933 </field> 25934 <field> 25935 <name>INEPNMM</name> 25936 <description>IN token received with EP mismatch 25937 mask</description> 25938 <bitOffset>5</bitOffset> 25939 <bitWidth>1</bitWidth> 25940 </field> 25941 <field> 25942 <name>INEPNEM</name> 25943 <description>IN endpoint NAK effective 25944 mask</description> 25945 <bitOffset>6</bitOffset> 25946 <bitWidth>1</bitWidth> 25947 </field> 25948 </fields> 25949 </register> 25950 <register> 25951 <name>DOEPMSK</name> 25952 <displayName>DOEPMSK</displayName> 25953 <description>OTG_FS device OUT endpoint common interrupt 25954 mask register (OTG_FS_DOEPMSK)</description> 25955 <addressOffset>0x14</addressOffset> 25956 <size>0x20</size> 25957 <access>read-write</access> 25958 <resetValue>0x00000000</resetValue> 25959 <fields> 25960 <field> 25961 <name>XFRCM</name> 25962 <description>Transfer completed interrupt 25963 mask</description> 25964 <bitOffset>0</bitOffset> 25965 <bitWidth>1</bitWidth> 25966 </field> 25967 <field> 25968 <name>EPDM</name> 25969 <description>Endpoint disabled interrupt 25970 mask</description> 25971 <bitOffset>1</bitOffset> 25972 <bitWidth>1</bitWidth> 25973 </field> 25974 <field> 25975 <name>STUPM</name> 25976 <description>SETUP phase done mask</description> 25977 <bitOffset>3</bitOffset> 25978 <bitWidth>1</bitWidth> 25979 </field> 25980 <field> 25981 <name>OTEPDM</name> 25982 <description>OUT token received when endpoint 25983 disabled mask</description> 25984 <bitOffset>4</bitOffset> 25985 <bitWidth>1</bitWidth> 25986 </field> 25987 </fields> 25988 </register> 25989 <register> 25990 <name>DAINT</name> 25991 <displayName>DAINT</displayName> 25992 <description>OTG_FS device all endpoints interrupt 25993 register (OTG_FS_DAINT)</description> 25994 <addressOffset>0x18</addressOffset> 25995 <size>0x20</size> 25996 <access>read-only</access> 25997 <resetValue>0x00000000</resetValue> 25998 <fields> 25999 <field> 26000 <name>IEPINT</name> 26001 <description>IN endpoint interrupt bits</description> 26002 <bitOffset>0</bitOffset> 26003 <bitWidth>16</bitWidth> 26004 </field> 26005 <field> 26006 <name>OEPINT</name> 26007 <description>OUT endpoint interrupt 26008 bits</description> 26009 <bitOffset>16</bitOffset> 26010 <bitWidth>16</bitWidth> 26011 </field> 26012 </fields> 26013 </register> 26014 <register> 26015 <name>DAINTMSK</name> 26016 <displayName>DAINTMSK</displayName> 26017 <description>OTG_FS all endpoints interrupt mask register 26018 (OTG_FS_DAINTMSK)</description> 26019 <addressOffset>0x1C</addressOffset> 26020 <size>0x20</size> 26021 <access>read-write</access> 26022 <resetValue>0x00000000</resetValue> 26023 <fields> 26024 <field> 26025 <name>IEPM</name> 26026 <description>IN EP interrupt mask bits</description> 26027 <bitOffset>0</bitOffset> 26028 <bitWidth>16</bitWidth> 26029 </field> 26030 <field> 26031 <name>OEPM</name> 26032 <description>OUT EP interrupt mask bits</description> 26033 <bitOffset>16</bitOffset> 26034 <bitWidth>16</bitWidth> 26035 </field> 26036 </fields> 26037 </register> 26038 <register> 26039 <name>DVBUSDIS</name> 26040 <displayName>DVBUSDIS</displayName> 26041 <description>OTG_FS device VBUS discharge time 26042 register</description> 26043 <addressOffset>0x28</addressOffset> 26044 <size>0x20</size> 26045 <access>read-write</access> 26046 <resetValue>0x000017D7</resetValue> 26047 <fields> 26048 <field> 26049 <name>VBUSDT</name> 26050 <description>Device VBUS discharge time</description> 26051 <bitOffset>0</bitOffset> 26052 <bitWidth>16</bitWidth> 26053 </field> 26054 </fields> 26055 </register> 26056 <register> 26057 <name>DVBUSPULSE</name> 26058 <displayName>DVBUSPULSE</displayName> 26059 <description>OTG_FS device VBUS pulsing time 26060 register</description> 26061 <addressOffset>0x2C</addressOffset> 26062 <size>0x20</size> 26063 <access>read-write</access> 26064 <resetValue>0x000005B8</resetValue> 26065 <fields> 26066 <field> 26067 <name>DVBUSP</name> 26068 <description>Device VBUS pulsing time</description> 26069 <bitOffset>0</bitOffset> 26070 <bitWidth>12</bitWidth> 26071 </field> 26072 </fields> 26073 </register> 26074 <register> 26075 <name>DIEPEMPMSK</name> 26076 <displayName>DIEPEMPMSK</displayName> 26077 <description>OTG_FS device IN endpoint FIFO empty 26078 interrupt mask register</description> 26079 <addressOffset>0x34</addressOffset> 26080 <size>0x20</size> 26081 <access>read-write</access> 26082 <resetValue>0x00000000</resetValue> 26083 <fields> 26084 <field> 26085 <name>INEPTXFEM</name> 26086 <description>IN EP Tx FIFO empty interrupt mask 26087 bits</description> 26088 <bitOffset>0</bitOffset> 26089 <bitWidth>16</bitWidth> 26090 </field> 26091 </fields> 26092 </register> 26093 <register> 26094 <name>DIEPCTL0</name> 26095 <displayName>DIEPCTL0</displayName> 26096 <description>OTG_FS device control IN endpoint 0 control 26097 register (OTG_FS_DIEPCTL0)</description> 26098 <addressOffset>0x100</addressOffset> 26099 <size>0x20</size> 26100 <resetValue>0x00000000</resetValue> 26101 <fields> 26102 <field> 26103 <name>MPSIZ</name> 26104 <description>Maximum packet size</description> 26105 <bitOffset>0</bitOffset> 26106 <bitWidth>2</bitWidth> 26107 <access>read-write</access> 26108 </field> 26109 <field> 26110 <name>USBAEP</name> 26111 <description>USB active endpoint</description> 26112 <bitOffset>15</bitOffset> 26113 <bitWidth>1</bitWidth> 26114 <access>read-only</access> 26115 </field> 26116 <field> 26117 <name>NAKSTS</name> 26118 <description>NAK status</description> 26119 <bitOffset>17</bitOffset> 26120 <bitWidth>1</bitWidth> 26121 <access>read-only</access> 26122 </field> 26123 <field> 26124 <name>EPTYP</name> 26125 <description>Endpoint type</description> 26126 <bitOffset>18</bitOffset> 26127 <bitWidth>2</bitWidth> 26128 <access>read-only</access> 26129 </field> 26130 <field> 26131 <name>STALL</name> 26132 <description>STALL handshake</description> 26133 <bitOffset>21</bitOffset> 26134 <bitWidth>1</bitWidth> 26135 <access>read-write</access> 26136 </field> 26137 <field> 26138 <name>TXFNUM</name> 26139 <description>TxFIFO number</description> 26140 <bitOffset>22</bitOffset> 26141 <bitWidth>4</bitWidth> 26142 <access>read-write</access> 26143 </field> 26144 <field> 26145 <name>CNAK</name> 26146 <description>Clear NAK</description> 26147 <bitOffset>26</bitOffset> 26148 <bitWidth>1</bitWidth> 26149 <access>write-only</access> 26150 </field> 26151 <field> 26152 <name>SNAK</name> 26153 <description>Set NAK</description> 26154 <bitOffset>27</bitOffset> 26155 <bitWidth>1</bitWidth> 26156 <access>write-only</access> 26157 </field> 26158 <field> 26159 <name>EPDIS</name> 26160 <description>Endpoint disable</description> 26161 <bitOffset>30</bitOffset> 26162 <bitWidth>1</bitWidth> 26163 <access>read-only</access> 26164 </field> 26165 <field> 26166 <name>EPENA</name> 26167 <description>Endpoint enable</description> 26168 <bitOffset>31</bitOffset> 26169 <bitWidth>1</bitWidth> 26170 <access>read-write</access> 26171 </field> 26172 </fields> 26173 </register> 26174 <register> 26175 <dim>3</dim><dimIncrement>0x20</dimIncrement><dimIndex>1,2,3</dimIndex><name>DIEPCTL%s</name> 26176 <displayName>DIEPCTL1</displayName> 26177 <description>OTG device endpoint-1 control 26178 register</description> 26179 <addressOffset>0x120</addressOffset> 26180 <size>0x20</size> 26181 <resetValue>0x00000000</resetValue> 26182 <fields> 26183 <field> 26184 <name>EPENA</name> 26185 <description>EPENA</description> 26186 <bitOffset>31</bitOffset> 26187 <bitWidth>1</bitWidth> 26188 <access>read-write</access> 26189 </field> 26190 <field> 26191 <name>EPDIS</name> 26192 <description>EPDIS</description> 26193 <bitOffset>30</bitOffset> 26194 <bitWidth>1</bitWidth> 26195 <access>read-write</access> 26196 </field> 26197 <field> 26198 <name>SODDFRM_SD1PID</name> 26199 <description>SODDFRM/SD1PID</description> 26200 <bitOffset>29</bitOffset> 26201 <bitWidth>1</bitWidth> 26202 <access>write-only</access> 26203 </field> 26204 <field> 26205 <name>SD0PID_SEVNFRM</name> 26206 <description>SD0PID/SEVNFRM</description> 26207 <bitOffset>28</bitOffset> 26208 <bitWidth>1</bitWidth> 26209 <access>write-only</access> 26210 </field> 26211 <field> 26212 <name>SNAK</name> 26213 <description>SNAK</description> 26214 <bitOffset>27</bitOffset> 26215 <bitWidth>1</bitWidth> 26216 <access>write-only</access> 26217 </field> 26218 <field> 26219 <name>CNAK</name> 26220 <description>CNAK</description> 26221 <bitOffset>26</bitOffset> 26222 <bitWidth>1</bitWidth> 26223 <access>write-only</access> 26224 </field> 26225 <field> 26226 <name>TXFNUM</name> 26227 <description>TXFNUM</description> 26228 <bitOffset>22</bitOffset> 26229 <bitWidth>4</bitWidth> 26230 <access>read-write</access> 26231 </field> 26232 <field> 26233 <name>STALL</name> 26234 <description>STALL</description> 26235 <bitOffset>21</bitOffset> 26236 <bitWidth>1</bitWidth> 26237 <access>read-write</access> 26238 </field> 26239 <field> 26240 <name>EPTYP</name> 26241 <description>EPTYP</description> 26242 <bitOffset>18</bitOffset> 26243 <bitWidth>2</bitWidth> 26244 <access>read-write</access> 26245 </field> 26246 <field> 26247 <name>NAKSTS</name> 26248 <description>NAKSTS</description> 26249 <bitOffset>17</bitOffset> 26250 <bitWidth>1</bitWidth> 26251 <access>read-only</access> 26252 </field> 26253 <field> 26254 <name>EONUM_DPID</name> 26255 <description>EONUM/DPID</description> 26256 <bitOffset>16</bitOffset> 26257 <bitWidth>1</bitWidth> 26258 <access>read-only</access> 26259 </field> 26260 <field> 26261 <name>USBAEP</name> 26262 <description>USBAEP</description> 26263 <bitOffset>15</bitOffset> 26264 <bitWidth>1</bitWidth> 26265 <access>read-write</access> 26266 </field> 26267 <field> 26268 <name>MPSIZ</name> 26269 <description>MPSIZ</description> 26270 <bitOffset>0</bitOffset> 26271 <bitWidth>11</bitWidth> 26272 <access>read-write</access> 26273 </field> 26274 </fields> 26275 </register> 26276 <register> 26277 <name>DOEPCTL0</name> 26278 <displayName>DOEPCTL0</displayName> 26279 <description>device endpoint-0 control 26280 register</description> 26281 <addressOffset>0x300</addressOffset> 26282 <size>0x20</size> 26283 <resetValue>0x00008000</resetValue> 26284 <fields> 26285 <field> 26286 <name>EPENA</name> 26287 <description>EPENA</description> 26288 <bitOffset>31</bitOffset> 26289 <bitWidth>1</bitWidth> 26290 <access>write-only</access> 26291 </field> 26292 <field> 26293 <name>EPDIS</name> 26294 <description>EPDIS</description> 26295 <bitOffset>30</bitOffset> 26296 <bitWidth>1</bitWidth> 26297 <access>read-only</access> 26298 </field> 26299 <field> 26300 <name>SNAK</name> 26301 <description>SNAK</description> 26302 <bitOffset>27</bitOffset> 26303 <bitWidth>1</bitWidth> 26304 <access>write-only</access> 26305 </field> 26306 <field> 26307 <name>CNAK</name> 26308 <description>CNAK</description> 26309 <bitOffset>26</bitOffset> 26310 <bitWidth>1</bitWidth> 26311 <access>write-only</access> 26312 </field> 26313 <field> 26314 <name>STALL</name> 26315 <description>STALL</description> 26316 <bitOffset>21</bitOffset> 26317 <bitWidth>1</bitWidth> 26318 <access>read-write</access> 26319 </field> 26320 <field> 26321 <name>SNPM</name> 26322 <description>SNPM</description> 26323 <bitOffset>20</bitOffset> 26324 <bitWidth>1</bitWidth> 26325 <access>read-write</access> 26326 </field> 26327 <field> 26328 <name>EPTYP</name> 26329 <description>EPTYP</description> 26330 <bitOffset>18</bitOffset> 26331 <bitWidth>2</bitWidth> 26332 <access>read-only</access> 26333 </field> 26334 <field> 26335 <name>NAKSTS</name> 26336 <description>NAKSTS</description> 26337 <bitOffset>17</bitOffset> 26338 <bitWidth>1</bitWidth> 26339 <access>read-only</access> 26340 </field> 26341 <field> 26342 <name>USBAEP</name> 26343 <description>USBAEP</description> 26344 <bitOffset>15</bitOffset> 26345 <bitWidth>1</bitWidth> 26346 <access>read-only</access> 26347 </field> 26348 <field> 26349 <name>MPSIZ</name> 26350 <description>MPSIZ</description> 26351 <bitOffset>0</bitOffset> 26352 <bitWidth>2</bitWidth> 26353 <access>read-only</access> 26354 </field> 26355 </fields> 26356 </register> 26357 <register> 26358 <dim>3</dim><dimIncrement>0x20</dimIncrement><dimIndex>1,2,3</dimIndex><name>DOEPCTL%s</name> 26359 <displayName>DOEPCTL1</displayName> 26360 <description>device endpoint-1 control 26361 register</description> 26362 <addressOffset>0x320</addressOffset> 26363 <size>0x20</size> 26364 <resetValue>0x00000000</resetValue> 26365 <fields> 26366 <field> 26367 <name>EPENA</name> 26368 <description>EPENA</description> 26369 <bitOffset>31</bitOffset> 26370 <bitWidth>1</bitWidth> 26371 <access>read-write</access> 26372 </field> 26373 <field> 26374 <name>EPDIS</name> 26375 <description>EPDIS</description> 26376 <bitOffset>30</bitOffset> 26377 <bitWidth>1</bitWidth> 26378 <access>read-write</access> 26379 </field> 26380 <field> 26381 <name>SODDFRM</name> 26382 <description>SODDFRM</description> 26383 <bitOffset>29</bitOffset> 26384 <bitWidth>1</bitWidth> 26385 <access>write-only</access> 26386 </field> 26387 <field> 26388 <name>SD0PID_SEVNFRM</name> 26389 <description>SD0PID/SEVNFRM</description> 26390 <bitOffset>28</bitOffset> 26391 <bitWidth>1</bitWidth> 26392 <access>write-only</access> 26393 </field> 26394 <field> 26395 <name>SNAK</name> 26396 <description>SNAK</description> 26397 <bitOffset>27</bitOffset> 26398 <bitWidth>1</bitWidth> 26399 <access>write-only</access> 26400 </field> 26401 <field> 26402 <name>CNAK</name> 26403 <description>CNAK</description> 26404 <bitOffset>26</bitOffset> 26405 <bitWidth>1</bitWidth> 26406 <access>write-only</access> 26407 </field> 26408 <field> 26409 <name>STALL</name> 26410 <description>STALL</description> 26411 <bitOffset>21</bitOffset> 26412 <bitWidth>1</bitWidth> 26413 <access>read-write</access> 26414 </field> 26415 <field> 26416 <name>SNPM</name> 26417 <description>SNPM</description> 26418 <bitOffset>20</bitOffset> 26419 <bitWidth>1</bitWidth> 26420 <access>read-write</access> 26421 </field> 26422 <field> 26423 <name>EPTYP</name> 26424 <description>EPTYP</description> 26425 <bitOffset>18</bitOffset> 26426 <bitWidth>2</bitWidth> 26427 <access>read-write</access> 26428 </field> 26429 <field> 26430 <name>NAKSTS</name> 26431 <description>NAKSTS</description> 26432 <bitOffset>17</bitOffset> 26433 <bitWidth>1</bitWidth> 26434 <access>read-only</access> 26435 </field> 26436 <field> 26437 <name>EONUM_DPID</name> 26438 <description>EONUM/DPID</description> 26439 <bitOffset>16</bitOffset> 26440 <bitWidth>1</bitWidth> 26441 <access>read-only</access> 26442 </field> 26443 <field> 26444 <name>USBAEP</name> 26445 <description>USBAEP</description> 26446 <bitOffset>15</bitOffset> 26447 <bitWidth>1</bitWidth> 26448 <access>read-write</access> 26449 </field> 26450 <field> 26451 <name>MPSIZ</name> 26452 <description>MPSIZ</description> 26453 <bitOffset>0</bitOffset> 26454 <bitWidth>11</bitWidth> 26455 <access>read-write</access> 26456 </field> 26457 </fields> 26458 </register> 26459 <register> 26460 <name>DIEPINT0</name> 26461 <displayName>DIEPINT0</displayName> 26462 <description>device endpoint-x interrupt 26463 register</description> 26464 <addressOffset>0x108</addressOffset> 26465 <size>0x20</size> 26466 <resetValue>0x00000080</resetValue> 26467 <fields> 26468 <field> 26469 <name>TXFE</name> 26470 <description>TXFE</description> 26471 <bitOffset>7</bitOffset> 26472 <bitWidth>1</bitWidth> 26473 <access>read-only</access> 26474 </field> 26475 <field> 26476 <name>INEPNE</name> 26477 <description>INEPNE</description> 26478 <bitOffset>6</bitOffset> 26479 <bitWidth>1</bitWidth> 26480 <access>read-write</access> 26481 </field> 26482 <field> 26483 <name>ITTXFE</name> 26484 <description>ITTXFE</description> 26485 <bitOffset>4</bitOffset> 26486 <bitWidth>1</bitWidth> 26487 <access>read-write</access> 26488 </field> 26489 <field> 26490 <name>TOC</name> 26491 <description>TOC</description> 26492 <bitOffset>3</bitOffset> 26493 <bitWidth>1</bitWidth> 26494 <access>read-write</access> 26495 </field> 26496 <field> 26497 <name>EPDISD</name> 26498 <description>EPDISD</description> 26499 <bitOffset>1</bitOffset> 26500 <bitWidth>1</bitWidth> 26501 <access>read-write</access> 26502 </field> 26503 <field> 26504 <name>XFRC</name> 26505 <description>XFRC</description> 26506 <bitOffset>0</bitOffset> 26507 <bitWidth>1</bitWidth> 26508 <access>read-write</access> 26509 </field> 26510 </fields> 26511 </register> 26512 <register> 26513 <name>DIEPINT1</name> 26514 <displayName>DIEPINT1</displayName> 26515 <description>device endpoint-1 interrupt 26516 register</description> 26517 <addressOffset>0x128</addressOffset> 26518 <size>0x20</size> 26519 <resetValue>0x00000080</resetValue> 26520 <fields> 26521 <field> 26522 <name>TXFE</name> 26523 <description>TXFE</description> 26524 <bitOffset>7</bitOffset> 26525 <bitWidth>1</bitWidth> 26526 <access>read-only</access> 26527 </field> 26528 <field> 26529 <name>INEPNE</name> 26530 <description>INEPNE</description> 26531 <bitOffset>6</bitOffset> 26532 <bitWidth>1</bitWidth> 26533 <access>read-write</access> 26534 </field> 26535 <field> 26536 <name>ITTXFE</name> 26537 <description>ITTXFE</description> 26538 <bitOffset>4</bitOffset> 26539 <bitWidth>1</bitWidth> 26540 <access>read-write</access> 26541 </field> 26542 <field> 26543 <name>TOC</name> 26544 <description>TOC</description> 26545 <bitOffset>3</bitOffset> 26546 <bitWidth>1</bitWidth> 26547 <access>read-write</access> 26548 </field> 26549 <field> 26550 <name>EPDISD</name> 26551 <description>EPDISD</description> 26552 <bitOffset>1</bitOffset> 26553 <bitWidth>1</bitWidth> 26554 <access>read-write</access> 26555 </field> 26556 <field> 26557 <name>XFRC</name> 26558 <description>XFRC</description> 26559 <bitOffset>0</bitOffset> 26560 <bitWidth>1</bitWidth> 26561 <access>read-write</access> 26562 </field> 26563 </fields> 26564 </register> 26565 <register> 26566 <name>DIEPINT2</name> 26567 <displayName>DIEPINT2</displayName> 26568 <description>device endpoint-2 interrupt 26569 register</description> 26570 <addressOffset>0x148</addressOffset> 26571 <size>0x20</size> 26572 <resetValue>0x00000080</resetValue> 26573 <fields> 26574 <field> 26575 <name>TXFE</name> 26576 <description>TXFE</description> 26577 <bitOffset>7</bitOffset> 26578 <bitWidth>1</bitWidth> 26579 <access>read-only</access> 26580 </field> 26581 <field> 26582 <name>INEPNE</name> 26583 <description>INEPNE</description> 26584 <bitOffset>6</bitOffset> 26585 <bitWidth>1</bitWidth> 26586 <access>read-write</access> 26587 </field> 26588 <field> 26589 <name>ITTXFE</name> 26590 <description>ITTXFE</description> 26591 <bitOffset>4</bitOffset> 26592 <bitWidth>1</bitWidth> 26593 <access>read-write</access> 26594 </field> 26595 <field> 26596 <name>TOC</name> 26597 <description>TOC</description> 26598 <bitOffset>3</bitOffset> 26599 <bitWidth>1</bitWidth> 26600 <access>read-write</access> 26601 </field> 26602 <field> 26603 <name>EPDISD</name> 26604 <description>EPDISD</description> 26605 <bitOffset>1</bitOffset> 26606 <bitWidth>1</bitWidth> 26607 <access>read-write</access> 26608 </field> 26609 <field> 26610 <name>XFRC</name> 26611 <description>XFRC</description> 26612 <bitOffset>0</bitOffset> 26613 <bitWidth>1</bitWidth> 26614 <access>read-write</access> 26615 </field> 26616 </fields> 26617 </register> 26618 <register> 26619 <name>DIEPINT3</name> 26620 <displayName>DIEPINT3</displayName> 26621 <description>device endpoint-3 interrupt 26622 register</description> 26623 <addressOffset>0x168</addressOffset> 26624 <size>0x20</size> 26625 <resetValue>0x00000080</resetValue> 26626 <fields> 26627 <field> 26628 <name>TXFE</name> 26629 <description>TXFE</description> 26630 <bitOffset>7</bitOffset> 26631 <bitWidth>1</bitWidth> 26632 <access>read-only</access> 26633 </field> 26634 <field> 26635 <name>INEPNE</name> 26636 <description>INEPNE</description> 26637 <bitOffset>6</bitOffset> 26638 <bitWidth>1</bitWidth> 26639 <access>read-write</access> 26640 </field> 26641 <field> 26642 <name>ITTXFE</name> 26643 <description>ITTXFE</description> 26644 <bitOffset>4</bitOffset> 26645 <bitWidth>1</bitWidth> 26646 <access>read-write</access> 26647 </field> 26648 <field> 26649 <name>TOC</name> 26650 <description>TOC</description> 26651 <bitOffset>3</bitOffset> 26652 <bitWidth>1</bitWidth> 26653 <access>read-write</access> 26654 </field> 26655 <field> 26656 <name>EPDISD</name> 26657 <description>EPDISD</description> 26658 <bitOffset>1</bitOffset> 26659 <bitWidth>1</bitWidth> 26660 <access>read-write</access> 26661 </field> 26662 <field> 26663 <name>XFRC</name> 26664 <description>XFRC</description> 26665 <bitOffset>0</bitOffset> 26666 <bitWidth>1</bitWidth> 26667 <access>read-write</access> 26668 </field> 26669 </fields> 26670 </register> 26671 <register> 26672 <name>DOEPINT0</name> 26673 <displayName>DOEPINT0</displayName> 26674 <description>device endpoint-0 interrupt 26675 register</description> 26676 <addressOffset>0x308</addressOffset> 26677 <size>0x20</size> 26678 <access>read-write</access> 26679 <resetValue>0x00000080</resetValue> 26680 <fields> 26681 <field> 26682 <name>B2BSTUP</name> 26683 <description>B2BSTUP</description> 26684 <bitOffset>6</bitOffset> 26685 <bitWidth>1</bitWidth> 26686 </field> 26687 <field> 26688 <name>OTEPDIS</name> 26689 <description>OTEPDIS</description> 26690 <bitOffset>4</bitOffset> 26691 <bitWidth>1</bitWidth> 26692 </field> 26693 <field> 26694 <name>STUP</name> 26695 <description>STUP</description> 26696 <bitOffset>3</bitOffset> 26697 <bitWidth>1</bitWidth> 26698 </field> 26699 <field> 26700 <name>EPDISD</name> 26701 <description>EPDISD</description> 26702 <bitOffset>1</bitOffset> 26703 <bitWidth>1</bitWidth> 26704 </field> 26705 <field> 26706 <name>XFRC</name> 26707 <description>XFRC</description> 26708 <bitOffset>0</bitOffset> 26709 <bitWidth>1</bitWidth> 26710 </field> 26711 </fields> 26712 </register> 26713 <register> 26714 <name>DOEPINT1</name> 26715 <displayName>DOEPINT1</displayName> 26716 <description>device endpoint-1 interrupt 26717 register</description> 26718 <addressOffset>0x328</addressOffset> 26719 <size>0x20</size> 26720 <access>read-write</access> 26721 <resetValue>0x00000080</resetValue> 26722 <fields> 26723 <field> 26724 <name>B2BSTUP</name> 26725 <description>B2BSTUP</description> 26726 <bitOffset>6</bitOffset> 26727 <bitWidth>1</bitWidth> 26728 </field> 26729 <field> 26730 <name>OTEPDIS</name> 26731 <description>OTEPDIS</description> 26732 <bitOffset>4</bitOffset> 26733 <bitWidth>1</bitWidth> 26734 </field> 26735 <field> 26736 <name>STUP</name> 26737 <description>STUP</description> 26738 <bitOffset>3</bitOffset> 26739 <bitWidth>1</bitWidth> 26740 </field> 26741 <field> 26742 <name>EPDISD</name> 26743 <description>EPDISD</description> 26744 <bitOffset>1</bitOffset> 26745 <bitWidth>1</bitWidth> 26746 </field> 26747 <field> 26748 <name>XFRC</name> 26749 <description>XFRC</description> 26750 <bitOffset>0</bitOffset> 26751 <bitWidth>1</bitWidth> 26752 </field> 26753 </fields> 26754 </register> 26755 <register> 26756 <name>DOEPINT2</name> 26757 <displayName>DOEPINT2</displayName> 26758 <description>device endpoint-2 interrupt 26759 register</description> 26760 <addressOffset>0x348</addressOffset> 26761 <size>0x20</size> 26762 <access>read-write</access> 26763 <resetValue>0x00000080</resetValue> 26764 <fields> 26765 <field> 26766 <name>B2BSTUP</name> 26767 <description>B2BSTUP</description> 26768 <bitOffset>6</bitOffset> 26769 <bitWidth>1</bitWidth> 26770 </field> 26771 <field> 26772 <name>OTEPDIS</name> 26773 <description>OTEPDIS</description> 26774 <bitOffset>4</bitOffset> 26775 <bitWidth>1</bitWidth> 26776 </field> 26777 <field> 26778 <name>STUP</name> 26779 <description>STUP</description> 26780 <bitOffset>3</bitOffset> 26781 <bitWidth>1</bitWidth> 26782 </field> 26783 <field> 26784 <name>EPDISD</name> 26785 <description>EPDISD</description> 26786 <bitOffset>1</bitOffset> 26787 <bitWidth>1</bitWidth> 26788 </field> 26789 <field> 26790 <name>XFRC</name> 26791 <description>XFRC</description> 26792 <bitOffset>0</bitOffset> 26793 <bitWidth>1</bitWidth> 26794 </field> 26795 </fields> 26796 </register> 26797 <register> 26798 <name>DOEPINT3</name> 26799 <displayName>DOEPINT3</displayName> 26800 <description>device endpoint-3 interrupt 26801 register</description> 26802 <addressOffset>0x368</addressOffset> 26803 <size>0x20</size> 26804 <access>read-write</access> 26805 <resetValue>0x00000080</resetValue> 26806 <fields> 26807 <field> 26808 <name>B2BSTUP</name> 26809 <description>B2BSTUP</description> 26810 <bitOffset>6</bitOffset> 26811 <bitWidth>1</bitWidth> 26812 </field> 26813 <field> 26814 <name>OTEPDIS</name> 26815 <description>OTEPDIS</description> 26816 <bitOffset>4</bitOffset> 26817 <bitWidth>1</bitWidth> 26818 </field> 26819 <field> 26820 <name>STUP</name> 26821 <description>STUP</description> 26822 <bitOffset>3</bitOffset> 26823 <bitWidth>1</bitWidth> 26824 </field> 26825 <field> 26826 <name>EPDISD</name> 26827 <description>EPDISD</description> 26828 <bitOffset>1</bitOffset> 26829 <bitWidth>1</bitWidth> 26830 </field> 26831 <field> 26832 <name>XFRC</name> 26833 <description>XFRC</description> 26834 <bitOffset>0</bitOffset> 26835 <bitWidth>1</bitWidth> 26836 </field> 26837 </fields> 26838 </register> 26839 <register> 26840 <name>DIEPTSIZ0</name> 26841 <displayName>DIEPTSIZ0</displayName> 26842 <description>device endpoint-0 transfer size 26843 register</description> 26844 <addressOffset>0x110</addressOffset> 26845 <size>0x20</size> 26846 <access>read-write</access> 26847 <resetValue>0x00000000</resetValue> 26848 <fields> 26849 <field> 26850 <name>PKTCNT</name> 26851 <description>Packet count</description> 26852 <bitOffset>19</bitOffset> 26853 <bitWidth>2</bitWidth> 26854 </field> 26855 <field> 26856 <name>XFRSIZ</name> 26857 <description>Transfer size</description> 26858 <bitOffset>0</bitOffset> 26859 <bitWidth>7</bitWidth> 26860 </field> 26861 </fields> 26862 </register> 26863 <register> 26864 <name>DOEPTSIZ0</name> 26865 <displayName>DOEPTSIZ0</displayName> 26866 <description>device OUT endpoint-0 transfer size 26867 register</description> 26868 <addressOffset>0x310</addressOffset> 26869 <size>0x20</size> 26870 <access>read-write</access> 26871 <resetValue>0x00000000</resetValue> 26872 <fields> 26873 <field> 26874 <name>STUPCNT</name> 26875 <description>SETUP packet count</description> 26876 <bitOffset>29</bitOffset> 26877 <bitWidth>2</bitWidth> 26878 </field> 26879 <field> 26880 <name>PKTCNT</name> 26881 <description>Packet count</description> 26882 <bitOffset>19</bitOffset> 26883 <bitWidth>1</bitWidth> 26884 </field> 26885 <field> 26886 <name>XFRSIZ</name> 26887 <description>Transfer size</description> 26888 <bitOffset>0</bitOffset> 26889 <bitWidth>7</bitWidth> 26890 </field> 26891 </fields> 26892 </register> 26893 <register> 26894 <name>DIEPTSIZ1</name> 26895 <displayName>DIEPTSIZ1</displayName> 26896 <description>device endpoint-1 transfer size 26897 register</description> 26898 <addressOffset>0x130</addressOffset> 26899 <size>0x20</size> 26900 <access>read-write</access> 26901 <resetValue>0x00000000</resetValue> 26902 <fields> 26903 <field> 26904 <name>MCNT</name> 26905 <description>Multi count</description> 26906 <bitOffset>29</bitOffset> 26907 <bitWidth>2</bitWidth> 26908 </field> 26909 <field> 26910 <name>PKTCNT</name> 26911 <description>Packet count</description> 26912 <bitOffset>19</bitOffset> 26913 <bitWidth>10</bitWidth> 26914 </field> 26915 <field> 26916 <name>XFRSIZ</name> 26917 <description>Transfer size</description> 26918 <bitOffset>0</bitOffset> 26919 <bitWidth>19</bitWidth> 26920 </field> 26921 </fields> 26922 </register> 26923 <register> 26924 <name>DIEPTSIZ2</name> 26925 <displayName>DIEPTSIZ2</displayName> 26926 <description>device endpoint-2 transfer size 26927 register</description> 26928 <addressOffset>0x150</addressOffset> 26929 <size>0x20</size> 26930 <access>read-write</access> 26931 <resetValue>0x00000000</resetValue> 26932 <fields> 26933 <field> 26934 <name>MCNT</name> 26935 <description>Multi count</description> 26936 <bitOffset>29</bitOffset> 26937 <bitWidth>2</bitWidth> 26938 </field> 26939 <field> 26940 <name>PKTCNT</name> 26941 <description>Packet count</description> 26942 <bitOffset>19</bitOffset> 26943 <bitWidth>10</bitWidth> 26944 </field> 26945 <field> 26946 <name>XFRSIZ</name> 26947 <description>Transfer size</description> 26948 <bitOffset>0</bitOffset> 26949 <bitWidth>19</bitWidth> 26950 </field> 26951 </fields> 26952 </register> 26953 <register> 26954 <name>DIEPTSIZ3</name> 26955 <displayName>DIEPTSIZ3</displayName> 26956 <description>device endpoint-3 transfer size 26957 register</description> 26958 <addressOffset>0x170</addressOffset> 26959 <size>0x20</size> 26960 <access>read-write</access> 26961 <resetValue>0x00000000</resetValue> 26962 <fields> 26963 <field> 26964 <name>MCNT</name> 26965 <description>Multi count</description> 26966 <bitOffset>29</bitOffset> 26967 <bitWidth>2</bitWidth> 26968 </field> 26969 <field> 26970 <name>PKTCNT</name> 26971 <description>Packet count</description> 26972 <bitOffset>19</bitOffset> 26973 <bitWidth>10</bitWidth> 26974 </field> 26975 <field> 26976 <name>XFRSIZ</name> 26977 <description>Transfer size</description> 26978 <bitOffset>0</bitOffset> 26979 <bitWidth>19</bitWidth> 26980 </field> 26981 </fields> 26982 </register> 26983 <register> 26984 <name>DTXFSTS0</name> 26985 <displayName>DTXFSTS0</displayName> 26986 <description>OTG_FS device IN endpoint transmit FIFO 26987 status register</description> 26988 <addressOffset>0x118</addressOffset> 26989 <size>0x20</size> 26990 <access>read-only</access> 26991 <resetValue>0x00000000</resetValue> 26992 <fields> 26993 <field> 26994 <name>INEPTFSAV</name> 26995 <description>IN endpoint TxFIFO space 26996 available</description> 26997 <bitOffset>0</bitOffset> 26998 <bitWidth>16</bitWidth> 26999 </field> 27000 </fields> 27001 </register> 27002 <register> 27003 <name>DTXFSTS1</name> 27004 <displayName>DTXFSTS1</displayName> 27005 <description>OTG_FS device IN endpoint transmit FIFO 27006 status register</description> 27007 <addressOffset>0x138</addressOffset> 27008 <size>0x20</size> 27009 <access>read-only</access> 27010 <resetValue>0x00000000</resetValue> 27011 <fields> 27012 <field> 27013 <name>INEPTFSAV</name> 27014 <description>IN endpoint TxFIFO space 27015 available</description> 27016 <bitOffset>0</bitOffset> 27017 <bitWidth>16</bitWidth> 27018 </field> 27019 </fields> 27020 </register> 27021 <register> 27022 <name>DTXFSTS2</name> 27023 <displayName>DTXFSTS2</displayName> 27024 <description>OTG_FS device IN endpoint transmit FIFO 27025 status register</description> 27026 <addressOffset>0x158</addressOffset> 27027 <size>0x20</size> 27028 <access>read-only</access> 27029 <resetValue>0x00000000</resetValue> 27030 <fields> 27031 <field> 27032 <name>INEPTFSAV</name> 27033 <description>IN endpoint TxFIFO space 27034 available</description> 27035 <bitOffset>0</bitOffset> 27036 <bitWidth>16</bitWidth> 27037 </field> 27038 </fields> 27039 </register> 27040 <register> 27041 <name>DTXFSTS3</name> 27042 <displayName>DTXFSTS3</displayName> 27043 <description>OTG_FS device IN endpoint transmit FIFO 27044 status register</description> 27045 <addressOffset>0x178</addressOffset> 27046 <size>0x20</size> 27047 <access>read-only</access> 27048 <resetValue>0x00000000</resetValue> 27049 <fields> 27050 <field> 27051 <name>INEPTFSAV</name> 27052 <description>IN endpoint TxFIFO space 27053 available</description> 27054 <bitOffset>0</bitOffset> 27055 <bitWidth>16</bitWidth> 27056 </field> 27057 </fields> 27058 </register> 27059 <register> 27060 <name>DOEPTSIZ1</name> 27061 <displayName>DOEPTSIZ1</displayName> 27062 <description>device OUT endpoint-1 transfer size 27063 register</description> 27064 <addressOffset>0x330</addressOffset> 27065 <size>0x20</size> 27066 <access>read-write</access> 27067 <resetValue>0x00000000</resetValue> 27068 <fields> 27069 <field> 27070 <name>RXDPID_STUPCNT</name> 27071 <description>Received data PID/SETUP packet 27072 count</description> 27073 <bitOffset>29</bitOffset> 27074 <bitWidth>2</bitWidth> 27075 </field> 27076 <field> 27077 <name>PKTCNT</name> 27078 <description>Packet count</description> 27079 <bitOffset>19</bitOffset> 27080 <bitWidth>10</bitWidth> 27081 </field> 27082 <field> 27083 <name>XFRSIZ</name> 27084 <description>Transfer size</description> 27085 <bitOffset>0</bitOffset> 27086 <bitWidth>19</bitWidth> 27087 </field> 27088 </fields> 27089 </register> 27090 <register> 27091 <name>DOEPTSIZ2</name> 27092 <displayName>DOEPTSIZ2</displayName> 27093 <description>device OUT endpoint-2 transfer size 27094 register</description> 27095 <addressOffset>0x350</addressOffset> 27096 <size>0x20</size> 27097 <access>read-write</access> 27098 <resetValue>0x00000000</resetValue> 27099 <fields> 27100 <field> 27101 <name>RXDPID_STUPCNT</name> 27102 <description>Received data PID/SETUP packet 27103 count</description> 27104 <bitOffset>29</bitOffset> 27105 <bitWidth>2</bitWidth> 27106 </field> 27107 <field> 27108 <name>PKTCNT</name> 27109 <description>Packet count</description> 27110 <bitOffset>19</bitOffset> 27111 <bitWidth>10</bitWidth> 27112 </field> 27113 <field> 27114 <name>XFRSIZ</name> 27115 <description>Transfer size</description> 27116 <bitOffset>0</bitOffset> 27117 <bitWidth>19</bitWidth> 27118 </field> 27119 </fields> 27120 </register> 27121 <register> 27122 <name>DOEPTSIZ3</name> 27123 <displayName>DOEPTSIZ3</displayName> 27124 <description>device OUT endpoint-3 transfer size 27125 register</description> 27126 <addressOffset>0x370</addressOffset> 27127 <size>0x20</size> 27128 <access>read-write</access> 27129 <resetValue>0x00000000</resetValue> 27130 <fields> 27131 <field> 27132 <name>RXDPID_STUPCNT</name> 27133 <description>Received data PID/SETUP packet 27134 count</description> 27135 <bitOffset>29</bitOffset> 27136 <bitWidth>2</bitWidth> 27137 </field> 27138 <field> 27139 <name>PKTCNT</name> 27140 <description>Packet count</description> 27141 <bitOffset>19</bitOffset> 27142 <bitWidth>10</bitWidth> 27143 </field> 27144 <field> 27145 <name>XFRSIZ</name> 27146 <description>Transfer size</description> 27147 <bitOffset>0</bitOffset> 27148 <bitWidth>19</bitWidth> 27149 </field> 27150 </fields> 27151 </register> 27152 </registers> 27153 </peripheral> 27154 <peripheral> 27155 <name>OTG_FS_PWRCLK</name> 27156 <description>USB on the go full speed</description> 27157 <groupName>USB_OTG_FS</groupName> 27158 <baseAddress>0x50000E00</baseAddress> 27159 <addressBlock> 27160 <offset>0x0</offset> 27161 <size>0x400</size> 27162 <usage>registers</usage> 27163 </addressBlock> 27164 <registers> 27165 <register> 27166 <name>PCGCCTL</name> 27167 <displayName>PCGCCTL</displayName> 27168 <description>OTG_FS power and clock gating control 27169 register</description> 27170 <addressOffset>0x0</addressOffset> 27171 <size>0x20</size> 27172 <access>read-write</access> 27173 <resetValue>0x00000000</resetValue> 27174 <fields> 27175 <field> 27176 <name>STPPCLK</name> 27177 <description>Stop PHY clock</description> 27178 <bitOffset>0</bitOffset> 27179 <bitWidth>1</bitWidth> 27180 </field> 27181 <field> 27182 <name>GATEHCLK</name> 27183 <description>Gate HCLK</description> 27184 <bitOffset>1</bitOffset> 27185 <bitWidth>1</bitWidth> 27186 </field> 27187 <field> 27188 <name>PHYSUSP</name> 27189 <description>PHY Suspended</description> 27190 <bitOffset>4</bitOffset> 27191 <bitWidth>1</bitWidth> 27192 </field> 27193 </fields> 27194 </register> 27195 </registers> 27196 </peripheral> 27197 <peripheral> 27198 <name>CAN1</name> 27199 <description>Controller area network</description> 27200 <groupName>CAN</groupName> 27201 <baseAddress>0x40006400</baseAddress> 27202 <addressBlock> 27203 <offset>0x0</offset> 27204 <size>0x400</size> 27205 <usage>registers</usage> 27206 </addressBlock> 27207 <interrupt> 27208 <name>CAN1_TX</name> 27209 <description>CAN1 TX interrupts</description> 27210 <value>19</value> 27211 </interrupt> 27212 <interrupt> 27213 <name>CAN1_RX0</name> 27214 <description>CAN1 RX0 interrupts</description> 27215 <value>20</value> 27216 </interrupt> 27217 <interrupt> 27218 <name>CAN1_RX1</name> 27219 <description>CAN1 RX1 interrupts</description> 27220 <value>21</value> 27221 </interrupt> 27222 <interrupt> 27223 <name>CAN1_SCE</name> 27224 <description>CAN1 SCE interrupt</description> 27225 <value>22</value> 27226 </interrupt> 27227 <registers> 27228 <cluster><dim>3</dim><dimIncrement>0x10</dimIncrement><dimIndex>0,1,2</dimIndex><name>TX%s</name><description>CAN Transmit cluster</description><addressOffset>0x180</addressOffset><register> 27229 <name>TIR</name> 27230 <displayName>TI0R</displayName> 27231 <description>TX mailbox identifier register</description> 27232 <addressOffset>0x0</addressOffset> 27233 <size>0x20</size> 27234 <access>read-write</access> 27235 <resetValue>0x00000000</resetValue> 27236 <fields> 27237 <field> 27238 <name>STID</name> 27239 <description>STID</description> 27240 <bitOffset>21</bitOffset> 27241 <bitWidth>11</bitWidth> 27242 </field> 27243 <field> 27244 <name>EXID</name> 27245 <description>EXID</description> 27246 <bitOffset>3</bitOffset> 27247 <bitWidth>18</bitWidth> 27248 </field> 27249 <field> 27250 <name>IDE</name> 27251 <description>IDE</description> 27252 <bitOffset>2</bitOffset> 27253 <bitWidth>1</bitWidth> 27254 <enumeratedValues><name>IDE</name><usage>read-write</usage><enumeratedValue><name>Standard</name><description>Standard identifier</description><value>0</value></enumeratedValue><enumeratedValue><name>Extended</name><description>Extended identifier</description><value>1</value></enumeratedValue></enumeratedValues> 27255 </field> 27256 <field> 27257 <name>RTR</name> 27258 <description>RTR</description> 27259 <bitOffset>1</bitOffset> 27260 <bitWidth>1</bitWidth> 27261 <enumeratedValues><name>RTR</name><usage>read-write</usage><enumeratedValue><name>Data</name><description>Data frame</description><value>0</value></enumeratedValue><enumeratedValue><name>Remote</name><description>Remote frame</description><value>1</value></enumeratedValue></enumeratedValues> 27262 </field> 27263 <field> 27264 <name>TXRQ</name> 27265 <description>TXRQ</description> 27266 <bitOffset>0</bitOffset> 27267 <bitWidth>1</bitWidth> 27268 </field> 27269 </fields> 27270 </register> 27271 <register> 27272 <name>TDTR</name> 27273 <displayName>TDT0R</displayName> 27274 <description>mailbox data length control and time stamp 27275 register</description> 27276 <addressOffset>0x4</addressOffset> 27277 <size>0x20</size> 27278 <access>read-write</access> 27279 <resetValue>0x00000000</resetValue> 27280 <fields> 27281 <field> 27282 <name>TIME</name> 27283 <description>TIME</description> 27284 <bitOffset>16</bitOffset> 27285 <bitWidth>16</bitWidth> 27286 </field> 27287 <field> 27288 <name>TGT</name> 27289 <description>TGT</description> 27290 <bitOffset>8</bitOffset> 27291 <bitWidth>1</bitWidth> 27292 </field> 27293 <field> 27294 <name>DLC</name> 27295 <description>DLC</description> 27296 <bitOffset>0</bitOffset> 27297 <bitWidth>4</bitWidth> 27298 <writeConstraint><range><minimum>0</minimum><maximum>8</maximum></range></writeConstraint> 27299 </field> 27300 </fields> 27301 </register> 27302 <register> 27303 <name>TDLR</name> 27304 <displayName>TDL0R</displayName> 27305 <description>mailbox data low register</description> 27306 <addressOffset>0x8</addressOffset> 27307 <size>0x20</size> 27308 <access>read-write</access> 27309 <resetValue>0x00000000</resetValue> 27310 <fields> 27311 <field> 27312 <name>DATA3</name> 27313 <description>DATA3</description> 27314 <bitOffset>24</bitOffset> 27315 <bitWidth>8</bitWidth> 27316 </field> 27317 <field> 27318 <name>DATA2</name> 27319 <description>DATA2</description> 27320 <bitOffset>16</bitOffset> 27321 <bitWidth>8</bitWidth> 27322 </field> 27323 <field> 27324 <name>DATA1</name> 27325 <description>DATA1</description> 27326 <bitOffset>8</bitOffset> 27327 <bitWidth>8</bitWidth> 27328 </field> 27329 <field> 27330 <name>DATA0</name> 27331 <description>DATA0</description> 27332 <bitOffset>0</bitOffset> 27333 <bitWidth>8</bitWidth> 27334 </field> 27335 </fields> 27336 </register> 27337 <register> 27338 <name>TDHR</name> 27339 <displayName>TDH0R</displayName> 27340 <description>mailbox data high register</description> 27341 <addressOffset>0xc</addressOffset> 27342 <size>0x20</size> 27343 <access>read-write</access> 27344 <resetValue>0x00000000</resetValue> 27345 <fields> 27346 <field> 27347 <name>DATA7</name> 27348 <description>DATA7</description> 27349 <bitOffset>24</bitOffset> 27350 <bitWidth>8</bitWidth> 27351 </field> 27352 <field> 27353 <name>DATA6</name> 27354 <description>DATA6</description> 27355 <bitOffset>16</bitOffset> 27356 <bitWidth>8</bitWidth> 27357 </field> 27358 <field> 27359 <name>DATA5</name> 27360 <description>DATA5</description> 27361 <bitOffset>8</bitOffset> 27362 <bitWidth>8</bitWidth> 27363 </field> 27364 <field> 27365 <name>DATA4</name> 27366 <description>DATA4</description> 27367 <bitOffset>0</bitOffset> 27368 <bitWidth>8</bitWidth> 27369 </field> 27370 </fields> 27371 </register> 27372 </cluster><cluster><dim>2</dim><dimIncrement>0x10</dimIncrement><dimIndex>0,1</dimIndex><name>RX%s</name><description>CAN Receive cluster</description><addressOffset>0x1b0</addressOffset><register> 27373 <name>RIR</name> 27374 <displayName>RI0R</displayName> 27375 <description>receive FIFO mailbox identifier 27376 register</description> 27377 <addressOffset>0x0</addressOffset> 27378 <size>0x20</size> 27379 <access>read-only</access> 27380 <resetValue>0x00000000</resetValue> 27381 <fields> 27382 <field> 27383 <name>STID</name> 27384 <description>STID</description> 27385 <bitOffset>21</bitOffset> 27386 <bitWidth>11</bitWidth> 27387 </field> 27388 <field> 27389 <name>EXID</name> 27390 <description>EXID</description> 27391 <bitOffset>3</bitOffset> 27392 <bitWidth>18</bitWidth> 27393 </field> 27394 <field> 27395 <name>IDE</name> 27396 <description>IDE</description> 27397 <bitOffset>2</bitOffset> 27398 <bitWidth>1</bitWidth> 27399 <enumeratedValues><name>IDE</name><usage>read-write</usage><enumeratedValue><name>Standard</name><description>Standard identifier</description><value>0</value></enumeratedValue><enumeratedValue><name>Extended</name><description>Extended identifier</description><value>1</value></enumeratedValue></enumeratedValues> 27400 </field> 27401 <field> 27402 <name>RTR</name> 27403 <description>RTR</description> 27404 <bitOffset>1</bitOffset> 27405 <bitWidth>1</bitWidth> 27406 <enumeratedValues><name>RTR</name><usage>read-write</usage><enumeratedValue><name>Data</name><description>Data frame</description><value>0</value></enumeratedValue><enumeratedValue><name>Remote</name><description>Remote frame</description><value>1</value></enumeratedValue></enumeratedValues> 27407 </field> 27408 </fields> 27409 </register> 27410 <register> 27411 <name>RDTR</name> 27412 <displayName>RDT0R</displayName> 27413 <description>mailbox data high register</description> 27414 <addressOffset>0x4</addressOffset> 27415 <size>0x20</size> 27416 <access>read-only</access> 27417 <resetValue>0x00000000</resetValue> 27418 <fields> 27419 <field> 27420 <name>TIME</name> 27421 <description>TIME</description> 27422 <bitOffset>16</bitOffset> 27423 <bitWidth>16</bitWidth> 27424 </field> 27425 <field> 27426 <name>FMI</name> 27427 <description>FMI</description> 27428 <bitOffset>8</bitOffset> 27429 <bitWidth>8</bitWidth> 27430 </field> 27431 <field> 27432 <name>DLC</name> 27433 <description>DLC</description> 27434 <bitOffset>0</bitOffset> 27435 <bitWidth>4</bitWidth> 27436 <writeConstraint><range><minimum>0</minimum><maximum>8</maximum></range></writeConstraint> 27437 </field> 27438 </fields> 27439 </register> 27440 <register> 27441 <name>RDLR</name> 27442 <displayName>RDL0R</displayName> 27443 <description>mailbox data high register</description> 27444 <addressOffset>0x8</addressOffset> 27445 <size>0x20</size> 27446 <access>read-only</access> 27447 <resetValue>0x00000000</resetValue> 27448 <fields> 27449 <field> 27450 <name>DATA3</name> 27451 <description>DATA3</description> 27452 <bitOffset>24</bitOffset> 27453 <bitWidth>8</bitWidth> 27454 </field> 27455 <field> 27456 <name>DATA2</name> 27457 <description>DATA2</description> 27458 <bitOffset>16</bitOffset> 27459 <bitWidth>8</bitWidth> 27460 </field> 27461 <field> 27462 <name>DATA1</name> 27463 <description>DATA1</description> 27464 <bitOffset>8</bitOffset> 27465 <bitWidth>8</bitWidth> 27466 </field> 27467 <field> 27468 <name>DATA0</name> 27469 <description>DATA0</description> 27470 <bitOffset>0</bitOffset> 27471 <bitWidth>8</bitWidth> 27472 </field> 27473 </fields> 27474 </register> 27475 <register> 27476 <name>RDHR</name> 27477 <displayName>RDH0R</displayName> 27478 <description>receive FIFO mailbox data high 27479 register</description> 27480 <addressOffset>0xc</addressOffset> 27481 <size>0x20</size> 27482 <access>read-only</access> 27483 <resetValue>0x00000000</resetValue> 27484 <fields> 27485 <field> 27486 <name>DATA7</name> 27487 <description>DATA7</description> 27488 <bitOffset>24</bitOffset> 27489 <bitWidth>8</bitWidth> 27490 </field> 27491 <field> 27492 <name>DATA6</name> 27493 <description>DATA6</description> 27494 <bitOffset>16</bitOffset> 27495 <bitWidth>8</bitWidth> 27496 </field> 27497 <field> 27498 <name>DATA5</name> 27499 <description>DATA5</description> 27500 <bitOffset>8</bitOffset> 27501 <bitWidth>8</bitWidth> 27502 </field> 27503 <field> 27504 <name>DATA4</name> 27505 <description>DATA4</description> 27506 <bitOffset>0</bitOffset> 27507 <bitWidth>8</bitWidth> 27508 </field> 27509 </fields> 27510 </register> 27511 </cluster><cluster><dim>28</dim><dimIncrement>0x8</dimIncrement><dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27</dimIndex><name>FB%s</name><description>CAN Filter Bank cluster</description><addressOffset>0x240</addressOffset><register> 27512 <name>FR1</name> 27513 <displayName>F0R1</displayName> 27514 <description>Filter bank 0 register 1</description> 27515 <addressOffset>0x0</addressOffset> 27516 <size>0x20</size> 27517 <access>read-write</access> 27518 <resetValue>0x00000000</resetValue> 27519 <fields> 27520 <field><name>FB</name><description>Filter bits</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields> 27521 </register> 27522 <register> 27523 <name>FR2</name> 27524 <displayName>F0R2</displayName> 27525 <description>Filter bank 0 register 2</description> 27526 <addressOffset>0x4</addressOffset> 27527 <size>0x20</size> 27528 <access>read-write</access> 27529 <resetValue>0x00000000</resetValue> 27530 <fields> 27531 <field><name>FB</name><description>Filter bits</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields> 27532 </register> 27533 </cluster><register> 27534 <name>MCR</name> 27535 <displayName>MCR</displayName> 27536 <description>master control register</description> 27537 <addressOffset>0x0</addressOffset> 27538 <size>0x20</size> 27539 <access>read-write</access> 27540 <resetValue>0x00010002</resetValue> 27541 <fields> 27542 <field> 27543 <name>DBF</name> 27544 <description>DBF</description> 27545 <bitOffset>16</bitOffset> 27546 <bitWidth>1</bitWidth> 27547 </field> 27548 <field> 27549 <name>RESET</name> 27550 <description>RESET</description> 27551 <bitOffset>15</bitOffset> 27552 <bitWidth>1</bitWidth> 27553 </field> 27554 <field> 27555 <name>TTCM</name> 27556 <description>TTCM</description> 27557 <bitOffset>7</bitOffset> 27558 <bitWidth>1</bitWidth> 27559 </field> 27560 <field> 27561 <name>ABOM</name> 27562 <description>ABOM</description> 27563 <bitOffset>6</bitOffset> 27564 <bitWidth>1</bitWidth> 27565 </field> 27566 <field> 27567 <name>AWUM</name> 27568 <description>AWUM</description> 27569 <bitOffset>5</bitOffset> 27570 <bitWidth>1</bitWidth> 27571 </field> 27572 <field> 27573 <name>NART</name> 27574 <description>NART</description> 27575 <bitOffset>4</bitOffset> 27576 <bitWidth>1</bitWidth> 27577 </field> 27578 <field> 27579 <name>RFLM</name> 27580 <description>RFLM</description> 27581 <bitOffset>3</bitOffset> 27582 <bitWidth>1</bitWidth> 27583 </field> 27584 <field> 27585 <name>TXFP</name> 27586 <description>TXFP</description> 27587 <bitOffset>2</bitOffset> 27588 <bitWidth>1</bitWidth> 27589 </field> 27590 <field> 27591 <name>SLEEP</name> 27592 <description>SLEEP</description> 27593 <bitOffset>1</bitOffset> 27594 <bitWidth>1</bitWidth> 27595 </field> 27596 <field> 27597 <name>INRQ</name> 27598 <description>INRQ</description> 27599 <bitOffset>0</bitOffset> 27600 <bitWidth>1</bitWidth> 27601 </field> 27602 </fields> 27603 </register> 27604 <register> 27605 <name>MSR</name> 27606 <displayName>MSR</displayName> 27607 <description>master status register</description> 27608 <addressOffset>0x4</addressOffset> 27609 <size>0x20</size> 27610 <resetValue>0x00000C02</resetValue> 27611 <fields> 27612 <field> 27613 <name>RX</name> 27614 <description>RX</description> 27615 <bitOffset>11</bitOffset> 27616 <bitWidth>1</bitWidth> 27617 <access>read-only</access> 27618 </field> 27619 <field> 27620 <name>SAMP</name> 27621 <description>SAMP</description> 27622 <bitOffset>10</bitOffset> 27623 <bitWidth>1</bitWidth> 27624 <access>read-only</access> 27625 </field> 27626 <field> 27627 <name>RXM</name> 27628 <description>RXM</description> 27629 <bitOffset>9</bitOffset> 27630 <bitWidth>1</bitWidth> 27631 <access>read-only</access> 27632 </field> 27633 <field> 27634 <name>TXM</name> 27635 <description>TXM</description> 27636 <bitOffset>8</bitOffset> 27637 <bitWidth>1</bitWidth> 27638 <access>read-only</access> 27639 </field> 27640 <field> 27641 <name>SLAKI</name> 27642 <description>SLAKI</description> 27643 <bitOffset>4</bitOffset> 27644 <bitWidth>1</bitWidth> 27645 <access>read-write</access> 27646 </field> 27647 <field> 27648 <name>WKUI</name> 27649 <description>WKUI</description> 27650 <bitOffset>3</bitOffset> 27651 <bitWidth>1</bitWidth> 27652 <access>read-write</access> 27653 </field> 27654 <field> 27655 <name>ERRI</name> 27656 <description>ERRI</description> 27657 <bitOffset>2</bitOffset> 27658 <bitWidth>1</bitWidth> 27659 <access>read-write</access> 27660 </field> 27661 <field> 27662 <name>SLAK</name> 27663 <description>SLAK</description> 27664 <bitOffset>1</bitOffset> 27665 <bitWidth>1</bitWidth> 27666 <access>read-only</access> 27667 </field> 27668 <field> 27669 <name>INAK</name> 27670 <description>INAK</description> 27671 <bitOffset>0</bitOffset> 27672 <bitWidth>1</bitWidth> 27673 <access>read-only</access> 27674 </field> 27675 </fields> 27676 </register> 27677 <register> 27678 <name>TSR</name> 27679 <displayName>TSR</displayName> 27680 <description>transmit status register</description> 27681 <addressOffset>0x8</addressOffset> 27682 <size>0x20</size> 27683 <resetValue>0x1C000000</resetValue> 27684 <fields> 27685 <field> 27686 <name>LOW2</name> 27687 <description>Lowest priority flag for mailbox 27688 2</description> 27689 <bitOffset>31</bitOffset> 27690 <bitWidth>1</bitWidth> 27691 <access>read-only</access> 27692 </field> 27693 <field> 27694 <name>LOW1</name> 27695 <description>Lowest priority flag for mailbox 27696 1</description> 27697 <bitOffset>30</bitOffset> 27698 <bitWidth>1</bitWidth> 27699 <access>read-only</access> 27700 </field> 27701 <field> 27702 <name>LOW0</name> 27703 <description>Lowest priority flag for mailbox 27704 0</description> 27705 <bitOffset>29</bitOffset> 27706 <bitWidth>1</bitWidth> 27707 <access>read-only</access> 27708 </field> 27709 <field> 27710 <name>TME2</name> 27711 <description>Lowest priority flag for mailbox 27712 2</description> 27713 <bitOffset>28</bitOffset> 27714 <bitWidth>1</bitWidth> 27715 <access>read-only</access> 27716 </field> 27717 <field> 27718 <name>TME1</name> 27719 <description>Lowest priority flag for mailbox 27720 1</description> 27721 <bitOffset>27</bitOffset> 27722 <bitWidth>1</bitWidth> 27723 <access>read-only</access> 27724 </field> 27725 <field> 27726 <name>TME0</name> 27727 <description>Lowest priority flag for mailbox 27728 0</description> 27729 <bitOffset>26</bitOffset> 27730 <bitWidth>1</bitWidth> 27731 <access>read-only</access> 27732 </field> 27733 <field> 27734 <name>CODE</name> 27735 <description>CODE</description> 27736 <bitOffset>24</bitOffset> 27737 <bitWidth>2</bitWidth> 27738 <access>read-only</access> 27739 </field> 27740 <field> 27741 <name>ABRQ2</name> 27742 <description>ABRQ2</description> 27743 <bitOffset>23</bitOffset> 27744 <bitWidth>1</bitWidth> 27745 <access>read-write</access> 27746 </field> 27747 <field> 27748 <name>TERR2</name> 27749 <description>TERR2</description> 27750 <bitOffset>19</bitOffset> 27751 <bitWidth>1</bitWidth> 27752 <access>read-write</access> 27753 </field> 27754 <field> 27755 <name>ALST2</name> 27756 <description>ALST2</description> 27757 <bitOffset>18</bitOffset> 27758 <bitWidth>1</bitWidth> 27759 <access>read-write</access> 27760 </field> 27761 <field> 27762 <name>TXOK2</name> 27763 <description>TXOK2</description> 27764 <bitOffset>17</bitOffset> 27765 <bitWidth>1</bitWidth> 27766 <access>read-write</access> 27767 </field> 27768 <field> 27769 <name>RQCP2</name> 27770 <description>RQCP2</description> 27771 <bitOffset>16</bitOffset> 27772 <bitWidth>1</bitWidth> 27773 <access>read-write</access> 27774 </field> 27775 <field> 27776 <name>ABRQ1</name> 27777 <description>ABRQ1</description> 27778 <bitOffset>15</bitOffset> 27779 <bitWidth>1</bitWidth> 27780 <access>read-write</access> 27781 </field> 27782 <field> 27783 <name>TERR1</name> 27784 <description>TERR1</description> 27785 <bitOffset>11</bitOffset> 27786 <bitWidth>1</bitWidth> 27787 <access>read-write</access> 27788 </field> 27789 <field> 27790 <name>ALST1</name> 27791 <description>ALST1</description> 27792 <bitOffset>10</bitOffset> 27793 <bitWidth>1</bitWidth> 27794 <access>read-write</access> 27795 </field> 27796 <field> 27797 <name>TXOK1</name> 27798 <description>TXOK1</description> 27799 <bitOffset>9</bitOffset> 27800 <bitWidth>1</bitWidth> 27801 <access>read-write</access> 27802 </field> 27803 <field> 27804 <name>RQCP1</name> 27805 <description>RQCP1</description> 27806 <bitOffset>8</bitOffset> 27807 <bitWidth>1</bitWidth> 27808 <access>read-write</access> 27809 </field> 27810 <field> 27811 <name>ABRQ0</name> 27812 <description>ABRQ0</description> 27813 <bitOffset>7</bitOffset> 27814 <bitWidth>1</bitWidth> 27815 <access>read-write</access> 27816 </field> 27817 <field> 27818 <name>TERR0</name> 27819 <description>TERR0</description> 27820 <bitOffset>3</bitOffset> 27821 <bitWidth>1</bitWidth> 27822 <access>read-write</access> 27823 </field> 27824 <field> 27825 <name>ALST0</name> 27826 <description>ALST0</description> 27827 <bitOffset>2</bitOffset> 27828 <bitWidth>1</bitWidth> 27829 <access>read-write</access> 27830 </field> 27831 <field> 27832 <name>TXOK0</name> 27833 <description>TXOK0</description> 27834 <bitOffset>1</bitOffset> 27835 <bitWidth>1</bitWidth> 27836 <access>read-write</access> 27837 </field> 27838 <field> 27839 <name>RQCP0</name> 27840 <description>RQCP0</description> 27841 <bitOffset>0</bitOffset> 27842 <bitWidth>1</bitWidth> 27843 <access>read-write</access> 27844 </field> 27845 </fields> 27846 </register> 27847 <register> 27848 <dim>2</dim><dimIncrement>0x4</dimIncrement><dimIndex>0,1</dimIndex><name>RF%sR</name> 27849 <displayName>RF0R</displayName> 27850 <description>receive FIFO %s register</description> 27851 <addressOffset>0xC</addressOffset> 27852 <size>0x20</size> 27853 <resetValue>0x00000000</resetValue> 27854 <fields> 27855 <field> 27856 <name>RFOM</name> 27857 <description>RFOM0</description> 27858 <bitOffset>5</bitOffset> 27859 <bitWidth>1</bitWidth> 27860 <access>read-write</access> 27861 <enumeratedValues><name>RFOM0W</name><usage>write</usage><enumeratedValue><name>Release</name><description>Set by software to release the output mailbox of the FIFO</description><value>1</value></enumeratedValue></enumeratedValues> 27862 </field> 27863 <field> 27864 <name>FOVR</name> 27865 <description>FOVR0</description> 27866 <bitOffset>4</bitOffset> 27867 <bitWidth>1</bitWidth> 27868 <access>read-write</access> 27869 <enumeratedValues><name>FOVR0R</name><usage>read</usage><enumeratedValue><name>NoOverrun</name><description>No FIFO x overrun</description><value>0</value></enumeratedValue><enumeratedValue><name>Overrun</name><description>FIFO x overrun</description><value>1</value></enumeratedValue></enumeratedValues> 27870 <enumeratedValues><name>FOVR0W</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clear flag</description><value>1</value></enumeratedValue></enumeratedValues> 27871 </field> 27872 <field> 27873 <name>FULL</name> 27874 <description>FULL0</description> 27875 <bitOffset>3</bitOffset> 27876 <bitWidth>1</bitWidth> 27877 <access>read-write</access> 27878 <enumeratedValues><name>FULL0R</name><usage>read</usage><enumeratedValue><name>NotFull</name><description>FIFO x is not full</description><value>0</value></enumeratedValue><enumeratedValue><name>Full</name><description>FIFO x is full</description><value>1</value></enumeratedValue></enumeratedValues> 27879 <enumeratedValues><name>FULL0W</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clear flag</description><value>1</value></enumeratedValue></enumeratedValues> 27880 </field> 27881 <field> 27882 <name>FMP</name> 27883 <description>FMP0</description> 27884 <bitOffset>0</bitOffset> 27885 <bitWidth>2</bitWidth> 27886 <access>read-only</access> 27887 </field> 27888 </fields> 27889 </register> 27890 <register> 27891 <name>IER</name> 27892 <displayName>IER</displayName> 27893 <description>interrupt enable register</description> 27894 <addressOffset>0x14</addressOffset> 27895 <size>0x20</size> 27896 <access>read-write</access> 27897 <resetValue>0x00000000</resetValue> 27898 <fields> 27899 <field> 27900 <name>SLKIE</name> 27901 <description>SLKIE</description> 27902 <bitOffset>17</bitOffset> 27903 <bitWidth>1</bitWidth> 27904 <enumeratedValues><name>SLKIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>No interrupt when SLAKI bit is set</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt generated when SLAKI bit is set</description><value>1</value></enumeratedValue></enumeratedValues> 27905 </field> 27906 <field> 27907 <name>WKUIE</name> 27908 <description>WKUIE</description> 27909 <bitOffset>16</bitOffset> 27910 <bitWidth>1</bitWidth> 27911 <enumeratedValues><name>WKUIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>No interrupt when WKUI is set</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt generated when WKUI bit is set</description><value>1</value></enumeratedValue></enumeratedValues> 27912 </field> 27913 <field> 27914 <name>ERRIE</name> 27915 <description>ERRIE</description> 27916 <bitOffset>15</bitOffset> 27917 <bitWidth>1</bitWidth> 27918 <enumeratedValues><name>ERRIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>No interrupt will be generated when an error condition is pending in the CAN_ESR</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>An interrupt will be generation when an error condition is pending in the CAN_ESR</description><value>1</value></enumeratedValue></enumeratedValues> 27919 </field> 27920 <field> 27921 <name>LECIE</name> 27922 <description>LECIE</description> 27923 <bitOffset>11</bitOffset> 27924 <bitWidth>1</bitWidth> 27925 <enumeratedValues><name>LECIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>ERRI bit will not be set when the error code in LEC[2:0] is set by hardware on error detection</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>ERRI bit will be set when the error code in LEC[2:0] is set by hardware on error detection</description><value>1</value></enumeratedValue></enumeratedValues> 27926 </field> 27927 <field> 27928 <name>BOFIE</name> 27929 <description>BOFIE</description> 27930 <bitOffset>10</bitOffset> 27931 <bitWidth>1</bitWidth> 27932 <enumeratedValues><name>BOFIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>ERRI bit will not be set when BOFF is set</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>ERRI bit will be set when BOFF is set</description><value>1</value></enumeratedValue></enumeratedValues> 27933 </field> 27934 <field> 27935 <name>EPVIE</name> 27936 <description>EPVIE</description> 27937 <bitOffset>9</bitOffset> 27938 <bitWidth>1</bitWidth> 27939 <enumeratedValues><name>EPVIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>ERRI bit will not be set when EPVF is set</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>ERRI bit will be set when EPVF is set</description><value>1</value></enumeratedValue></enumeratedValues> 27940 </field> 27941 <field> 27942 <name>EWGIE</name> 27943 <description>EWGIE</description> 27944 <bitOffset>8</bitOffset> 27945 <bitWidth>1</bitWidth> 27946 <enumeratedValues><name>EWGIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>ERRI bit will not be set when EWGF is set</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>ERRI bit will be set when EWGF is set</description><value>1</value></enumeratedValue></enumeratedValues> 27947 </field> 27948 <field> 27949 <name>FOVIE1</name> 27950 <description>FOVIE1</description> 27951 <bitOffset>6</bitOffset> 27952 <bitWidth>1</bitWidth> 27953 <enumeratedValues><name>FOVIE1</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>No interrupt when FOVR is set</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt generation when FOVR is set</description><value>1</value></enumeratedValue></enumeratedValues> 27954 </field> 27955 <field> 27956 <name>FFIE1</name> 27957 <description>FFIE1</description> 27958 <bitOffset>5</bitOffset> 27959 <bitWidth>1</bitWidth> 27960 <enumeratedValues><name>FFIE1</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>No interrupt when FULL bit is set</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt generated when FULL bit is set</description><value>1</value></enumeratedValue></enumeratedValues> 27961 </field> 27962 <field> 27963 <name>FMPIE1</name> 27964 <description>FMPIE1</description> 27965 <bitOffset>4</bitOffset> 27966 <bitWidth>1</bitWidth> 27967 <enumeratedValues><name>FMPIE1</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>No interrupt generated when state of FMP[1:0] bits are not 00b</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt generated when state of FMP[1:0] bits are not 00b</description><value>1</value></enumeratedValue></enumeratedValues> 27968 </field> 27969 <field> 27970 <name>FOVIE0</name> 27971 <description>FOVIE0</description> 27972 <bitOffset>3</bitOffset> 27973 <bitWidth>1</bitWidth> 27974 <enumeratedValues><name>FOVIE0</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>No interrupt when FOVR bit is set</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt generated when FOVR bit is set</description><value>1</value></enumeratedValue></enumeratedValues> 27975 </field> 27976 <field> 27977 <name>FFIE0</name> 27978 <description>FFIE0</description> 27979 <bitOffset>2</bitOffset> 27980 <bitWidth>1</bitWidth> 27981 <enumeratedValues><name>FFIE0</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>No interrupt when FULL bit is set</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt generated when FULL bit is set</description><value>1</value></enumeratedValue></enumeratedValues> 27982 </field> 27983 <field> 27984 <name>FMPIE0</name> 27985 <description>FMPIE0</description> 27986 <bitOffset>1</bitOffset> 27987 <bitWidth>1</bitWidth> 27988 <enumeratedValues><name>FMPIE0</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>No interrupt generated when state of FMP[1:0] bits are not 00</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt generated when state of FMP[1:0] bits are not 00b</description><value>1</value></enumeratedValue></enumeratedValues> 27989 </field> 27990 <field> 27991 <name>TMEIE</name> 27992 <description>TMEIE</description> 27993 <bitOffset>0</bitOffset> 27994 <bitWidth>1</bitWidth> 27995 <enumeratedValues><name>TMEIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>No interrupt when RQCPx bit is set</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt generated when RQCPx bit is set</description><value>1</value></enumeratedValue></enumeratedValues> 27996 </field> 27997 </fields> 27998 </register> 27999 <register> 28000 <name>ESR</name> 28001 <displayName>ESR</displayName> 28002 <description>interrupt enable register</description> 28003 <addressOffset>0x18</addressOffset> 28004 <size>0x20</size> 28005 <resetValue>0x00000000</resetValue> 28006 <fields> 28007 <field> 28008 <name>REC</name> 28009 <description>REC</description> 28010 <bitOffset>24</bitOffset> 28011 <bitWidth>8</bitWidth> 28012 <access>read-only</access> 28013 </field> 28014 <field> 28015 <name>TEC</name> 28016 <description>TEC</description> 28017 <bitOffset>16</bitOffset> 28018 <bitWidth>8</bitWidth> 28019 <access>read-only</access> 28020 </field> 28021 <field> 28022 <name>LEC</name> 28023 <description>LEC</description> 28024 <bitOffset>4</bitOffset> 28025 <bitWidth>3</bitWidth> 28026 <access>read-write</access> 28027 <enumeratedValues><name>LEC</name><usage>read-write</usage><enumeratedValue><name>NoError</name><description>No Error</description><value>0</value></enumeratedValue><enumeratedValue><name>Stuff</name><description>Stuff Error</description><value>1</value></enumeratedValue><enumeratedValue><name>Form</name><description>Form Error</description><value>2</value></enumeratedValue><enumeratedValue><name>Ack</name><description>Acknowledgment Error</description><value>3</value></enumeratedValue><enumeratedValue><name>BitRecessive</name><description>Bit recessive Error</description><value>4</value></enumeratedValue><enumeratedValue><name>BitDominant</name><description>Bit dominant Error</description><value>5</value></enumeratedValue><enumeratedValue><name>Crc</name><description>CRC Error</description><value>6</value></enumeratedValue><enumeratedValue><name>Custom</name><description>Set by software</description><value>7</value></enumeratedValue></enumeratedValues> 28028 </field> 28029 <field> 28030 <name>BOFF</name> 28031 <description>BOFF</description> 28032 <bitOffset>2</bitOffset> 28033 <bitWidth>1</bitWidth> 28034 <access>read-only</access> 28035 </field> 28036 <field> 28037 <name>EPVF</name> 28038 <description>EPVF</description> 28039 <bitOffset>1</bitOffset> 28040 <bitWidth>1</bitWidth> 28041 <access>read-only</access> 28042 </field> 28043 <field> 28044 <name>EWGF</name> 28045 <description>EWGF</description> 28046 <bitOffset>0</bitOffset> 28047 <bitWidth>1</bitWidth> 28048 <access>read-only</access> 28049 </field> 28050 </fields> 28051 </register> 28052 <register> 28053 <name>BTR</name> 28054 <displayName>BTR</displayName> 28055 <description>bit timing register</description> 28056 <addressOffset>0x1C</addressOffset> 28057 <size>0x20</size> 28058 <access>read-write</access> 28059 <resetValue>0x00000000</resetValue> 28060 <fields> 28061 <field> 28062 <name>SILM</name> 28063 <description>SILM</description> 28064 <bitOffset>31</bitOffset> 28065 <bitWidth>1</bitWidth> 28066 <enumeratedValues><name>SILM</name><usage>read-write</usage><enumeratedValue><name>Normal</name><description>Normal operation</description><value>0</value></enumeratedValue><enumeratedValue><name>Silent</name><description>Silent Mode</description><value>1</value></enumeratedValue></enumeratedValues> 28067 </field> 28068 <field> 28069 <name>LBKM</name> 28070 <description>LBKM</description> 28071 <bitOffset>30</bitOffset> 28072 <bitWidth>1</bitWidth> 28073 <enumeratedValues><name>LBKM</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Loop Back Mode disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Loop Back Mode enabled</description><value>1</value></enumeratedValue></enumeratedValues> 28074 </field> 28075 <field> 28076 <name>SJW</name> 28077 <description>SJW</description> 28078 <bitOffset>24</bitOffset> 28079 <bitWidth>2</bitWidth> 28080 </field> 28081 <field> 28082 <name>TS2</name> 28083 <description>TS2</description> 28084 <bitOffset>20</bitOffset> 28085 <bitWidth>3</bitWidth> 28086 </field> 28087 <field> 28088 <name>TS1</name> 28089 <description>TS1</description> 28090 <bitOffset>16</bitOffset> 28091 <bitWidth>4</bitWidth> 28092 </field> 28093 <field> 28094 <name>BRP</name> 28095 <description>BRP</description> 28096 <bitOffset>0</bitOffset> 28097 <bitWidth>10</bitWidth> 28098 </field> 28099 </fields> 28100 </register> 28101 <register> 28102 <name>FMR</name> 28103 <displayName>FMR</displayName> 28104 <description>filter master register</description> 28105 <addressOffset>0x200</addressOffset> 28106 <size>0x20</size> 28107 <access>read-write</access> 28108 <resetValue>0x2A1C0E01</resetValue> 28109 <fields> 28110 <field> 28111 <name>CAN2SB</name> 28112 <description>CAN2SB</description> 28113 <bitOffset>8</bitOffset> 28114 <bitWidth>6</bitWidth> 28115 </field> 28116 <field> 28117 <name>FINIT</name> 28118 <description>FINIT</description> 28119 <bitOffset>0</bitOffset> 28120 <bitWidth>1</bitWidth> 28121 </field> 28122 </fields> 28123 </register> 28124 <register> 28125 <name>FM1R</name> 28126 <displayName>FM1R</displayName> 28127 <description>filter mode register</description> 28128 <addressOffset>0x204</addressOffset> 28129 <size>0x20</size> 28130 <access>read-write</access> 28131 <resetValue>0x00000000</resetValue> 28132 <fields> 28133 <field> 28134 <name>FBM0</name> 28135 <description>Filter mode</description> 28136 <bitOffset>0</bitOffset> 28137 <bitWidth>1</bitWidth> 28138 </field> 28139 <field> 28140 <name>FBM1</name> 28141 <description>Filter mode</description> 28142 <bitOffset>1</bitOffset> 28143 <bitWidth>1</bitWidth> 28144 </field> 28145 <field> 28146 <name>FBM2</name> 28147 <description>Filter mode</description> 28148 <bitOffset>2</bitOffset> 28149 <bitWidth>1</bitWidth> 28150 </field> 28151 <field> 28152 <name>FBM3</name> 28153 <description>Filter mode</description> 28154 <bitOffset>3</bitOffset> 28155 <bitWidth>1</bitWidth> 28156 </field> 28157 <field> 28158 <name>FBM4</name> 28159 <description>Filter mode</description> 28160 <bitOffset>4</bitOffset> 28161 <bitWidth>1</bitWidth> 28162 </field> 28163 <field> 28164 <name>FBM5</name> 28165 <description>Filter mode</description> 28166 <bitOffset>5</bitOffset> 28167 <bitWidth>1</bitWidth> 28168 </field> 28169 <field> 28170 <name>FBM6</name> 28171 <description>Filter mode</description> 28172 <bitOffset>6</bitOffset> 28173 <bitWidth>1</bitWidth> 28174 </field> 28175 <field> 28176 <name>FBM7</name> 28177 <description>Filter mode</description> 28178 <bitOffset>7</bitOffset> 28179 <bitWidth>1</bitWidth> 28180 </field> 28181 <field> 28182 <name>FBM8</name> 28183 <description>Filter mode</description> 28184 <bitOffset>8</bitOffset> 28185 <bitWidth>1</bitWidth> 28186 </field> 28187 <field> 28188 <name>FBM9</name> 28189 <description>Filter mode</description> 28190 <bitOffset>9</bitOffset> 28191 <bitWidth>1</bitWidth> 28192 </field> 28193 <field> 28194 <name>FBM10</name> 28195 <description>Filter mode</description> 28196 <bitOffset>10</bitOffset> 28197 <bitWidth>1</bitWidth> 28198 </field> 28199 <field> 28200 <name>FBM11</name> 28201 <description>Filter mode</description> 28202 <bitOffset>11</bitOffset> 28203 <bitWidth>1</bitWidth> 28204 </field> 28205 <field> 28206 <name>FBM12</name> 28207 <description>Filter mode</description> 28208 <bitOffset>12</bitOffset> 28209 <bitWidth>1</bitWidth> 28210 </field> 28211 <field> 28212 <name>FBM13</name> 28213 <description>Filter mode</description> 28214 <bitOffset>13</bitOffset> 28215 <bitWidth>1</bitWidth> 28216 </field> 28217 <field> 28218 <name>FBM14</name> 28219 <description>Filter mode</description> 28220 <bitOffset>14</bitOffset> 28221 <bitWidth>1</bitWidth> 28222 </field> 28223 <field> 28224 <name>FBM15</name> 28225 <description>Filter mode</description> 28226 <bitOffset>15</bitOffset> 28227 <bitWidth>1</bitWidth> 28228 </field> 28229 <field> 28230 <name>FBM16</name> 28231 <description>Filter mode</description> 28232 <bitOffset>16</bitOffset> 28233 <bitWidth>1</bitWidth> 28234 </field> 28235 <field> 28236 <name>FBM17</name> 28237 <description>Filter mode</description> 28238 <bitOffset>17</bitOffset> 28239 <bitWidth>1</bitWidth> 28240 </field> 28241 <field> 28242 <name>FBM18</name> 28243 <description>Filter mode</description> 28244 <bitOffset>18</bitOffset> 28245 <bitWidth>1</bitWidth> 28246 </field> 28247 <field> 28248 <name>FBM19</name> 28249 <description>Filter mode</description> 28250 <bitOffset>19</bitOffset> 28251 <bitWidth>1</bitWidth> 28252 </field> 28253 <field> 28254 <name>FBM20</name> 28255 <description>Filter mode</description> 28256 <bitOffset>20</bitOffset> 28257 <bitWidth>1</bitWidth> 28258 </field> 28259 <field> 28260 <name>FBM21</name> 28261 <description>Filter mode</description> 28262 <bitOffset>21</bitOffset> 28263 <bitWidth>1</bitWidth> 28264 </field> 28265 <field> 28266 <name>FBM22</name> 28267 <description>Filter mode</description> 28268 <bitOffset>22</bitOffset> 28269 <bitWidth>1</bitWidth> 28270 </field> 28271 <field> 28272 <name>FBM23</name> 28273 <description>Filter mode</description> 28274 <bitOffset>23</bitOffset> 28275 <bitWidth>1</bitWidth> 28276 </field> 28277 <field> 28278 <name>FBM24</name> 28279 <description>Filter mode</description> 28280 <bitOffset>24</bitOffset> 28281 <bitWidth>1</bitWidth> 28282 </field> 28283 <field> 28284 <name>FBM25</name> 28285 <description>Filter mode</description> 28286 <bitOffset>25</bitOffset> 28287 <bitWidth>1</bitWidth> 28288 </field> 28289 <field> 28290 <name>FBM26</name> 28291 <description>Filter mode</description> 28292 <bitOffset>26</bitOffset> 28293 <bitWidth>1</bitWidth> 28294 </field> 28295 <field> 28296 <name>FBM27</name> 28297 <description>Filter mode</description> 28298 <bitOffset>27</bitOffset> 28299 <bitWidth>1</bitWidth> 28300 </field> 28301 </fields> 28302 </register> 28303 <register> 28304 <name>FS1R</name> 28305 <displayName>FS1R</displayName> 28306 <description>filter scale register</description> 28307 <addressOffset>0x20C</addressOffset> 28308 <size>0x20</size> 28309 <access>read-write</access> 28310 <resetValue>0x00000000</resetValue> 28311 <fields> 28312 <field> 28313 <name>FSC0</name> 28314 <description>Filter scale configuration</description> 28315 <bitOffset>0</bitOffset> 28316 <bitWidth>1</bitWidth> 28317 </field> 28318 <field> 28319 <name>FSC1</name> 28320 <description>Filter scale configuration</description> 28321 <bitOffset>1</bitOffset> 28322 <bitWidth>1</bitWidth> 28323 </field> 28324 <field> 28325 <name>FSC2</name> 28326 <description>Filter scale configuration</description> 28327 <bitOffset>2</bitOffset> 28328 <bitWidth>1</bitWidth> 28329 </field> 28330 <field> 28331 <name>FSC3</name> 28332 <description>Filter scale configuration</description> 28333 <bitOffset>3</bitOffset> 28334 <bitWidth>1</bitWidth> 28335 </field> 28336 <field> 28337 <name>FSC4</name> 28338 <description>Filter scale configuration</description> 28339 <bitOffset>4</bitOffset> 28340 <bitWidth>1</bitWidth> 28341 </field> 28342 <field> 28343 <name>FSC5</name> 28344 <description>Filter scale configuration</description> 28345 <bitOffset>5</bitOffset> 28346 <bitWidth>1</bitWidth> 28347 </field> 28348 <field> 28349 <name>FSC6</name> 28350 <description>Filter scale configuration</description> 28351 <bitOffset>6</bitOffset> 28352 <bitWidth>1</bitWidth> 28353 </field> 28354 <field> 28355 <name>FSC7</name> 28356 <description>Filter scale configuration</description> 28357 <bitOffset>7</bitOffset> 28358 <bitWidth>1</bitWidth> 28359 </field> 28360 <field> 28361 <name>FSC8</name> 28362 <description>Filter scale configuration</description> 28363 <bitOffset>8</bitOffset> 28364 <bitWidth>1</bitWidth> 28365 </field> 28366 <field> 28367 <name>FSC9</name> 28368 <description>Filter scale configuration</description> 28369 <bitOffset>9</bitOffset> 28370 <bitWidth>1</bitWidth> 28371 </field> 28372 <field> 28373 <name>FSC10</name> 28374 <description>Filter scale configuration</description> 28375 <bitOffset>10</bitOffset> 28376 <bitWidth>1</bitWidth> 28377 </field> 28378 <field> 28379 <name>FSC11</name> 28380 <description>Filter scale configuration</description> 28381 <bitOffset>11</bitOffset> 28382 <bitWidth>1</bitWidth> 28383 </field> 28384 <field> 28385 <name>FSC12</name> 28386 <description>Filter scale configuration</description> 28387 <bitOffset>12</bitOffset> 28388 <bitWidth>1</bitWidth> 28389 </field> 28390 <field> 28391 <name>FSC13</name> 28392 <description>Filter scale configuration</description> 28393 <bitOffset>13</bitOffset> 28394 <bitWidth>1</bitWidth> 28395 </field> 28396 <field> 28397 <name>FSC14</name> 28398 <description>Filter scale configuration</description> 28399 <bitOffset>14</bitOffset> 28400 <bitWidth>1</bitWidth> 28401 </field> 28402 <field> 28403 <name>FSC15</name> 28404 <description>Filter scale configuration</description> 28405 <bitOffset>15</bitOffset> 28406 <bitWidth>1</bitWidth> 28407 </field> 28408 <field> 28409 <name>FSC16</name> 28410 <description>Filter scale configuration</description> 28411 <bitOffset>16</bitOffset> 28412 <bitWidth>1</bitWidth> 28413 </field> 28414 <field> 28415 <name>FSC17</name> 28416 <description>Filter scale configuration</description> 28417 <bitOffset>17</bitOffset> 28418 <bitWidth>1</bitWidth> 28419 </field> 28420 <field> 28421 <name>FSC18</name> 28422 <description>Filter scale configuration</description> 28423 <bitOffset>18</bitOffset> 28424 <bitWidth>1</bitWidth> 28425 </field> 28426 <field> 28427 <name>FSC19</name> 28428 <description>Filter scale configuration</description> 28429 <bitOffset>19</bitOffset> 28430 <bitWidth>1</bitWidth> 28431 </field> 28432 <field> 28433 <name>FSC20</name> 28434 <description>Filter scale configuration</description> 28435 <bitOffset>20</bitOffset> 28436 <bitWidth>1</bitWidth> 28437 </field> 28438 <field> 28439 <name>FSC21</name> 28440 <description>Filter scale configuration</description> 28441 <bitOffset>21</bitOffset> 28442 <bitWidth>1</bitWidth> 28443 </field> 28444 <field> 28445 <name>FSC22</name> 28446 <description>Filter scale configuration</description> 28447 <bitOffset>22</bitOffset> 28448 <bitWidth>1</bitWidth> 28449 </field> 28450 <field> 28451 <name>FSC23</name> 28452 <description>Filter scale configuration</description> 28453 <bitOffset>23</bitOffset> 28454 <bitWidth>1</bitWidth> 28455 </field> 28456 <field> 28457 <name>FSC24</name> 28458 <description>Filter scale configuration</description> 28459 <bitOffset>24</bitOffset> 28460 <bitWidth>1</bitWidth> 28461 </field> 28462 <field> 28463 <name>FSC25</name> 28464 <description>Filter scale configuration</description> 28465 <bitOffset>25</bitOffset> 28466 <bitWidth>1</bitWidth> 28467 </field> 28468 <field> 28469 <name>FSC26</name> 28470 <description>Filter scale configuration</description> 28471 <bitOffset>26</bitOffset> 28472 <bitWidth>1</bitWidth> 28473 </field> 28474 <field> 28475 <name>FSC27</name> 28476 <description>Filter scale configuration</description> 28477 <bitOffset>27</bitOffset> 28478 <bitWidth>1</bitWidth> 28479 </field> 28480 </fields> 28481 </register> 28482 <register> 28483 <name>FFA1R</name> 28484 <displayName>FFA1R</displayName> 28485 <description>filter FIFO assignment 28486 register</description> 28487 <addressOffset>0x214</addressOffset> 28488 <size>0x20</size> 28489 <access>read-write</access> 28490 <resetValue>0x00000000</resetValue> 28491 <fields> 28492 <field> 28493 <name>FFA0</name> 28494 <description>Filter FIFO assignment for filter 28495 0</description> 28496 <bitOffset>0</bitOffset> 28497 <bitWidth>1</bitWidth> 28498 </field> 28499 <field> 28500 <name>FFA1</name> 28501 <description>Filter FIFO assignment for filter 28502 1</description> 28503 <bitOffset>1</bitOffset> 28504 <bitWidth>1</bitWidth> 28505 </field> 28506 <field> 28507 <name>FFA2</name> 28508 <description>Filter FIFO assignment for filter 28509 2</description> 28510 <bitOffset>2</bitOffset> 28511 <bitWidth>1</bitWidth> 28512 </field> 28513 <field> 28514 <name>FFA3</name> 28515 <description>Filter FIFO assignment for filter 28516 3</description> 28517 <bitOffset>3</bitOffset> 28518 <bitWidth>1</bitWidth> 28519 </field> 28520 <field> 28521 <name>FFA4</name> 28522 <description>Filter FIFO assignment for filter 28523 4</description> 28524 <bitOffset>4</bitOffset> 28525 <bitWidth>1</bitWidth> 28526 </field> 28527 <field> 28528 <name>FFA5</name> 28529 <description>Filter FIFO assignment for filter 28530 5</description> 28531 <bitOffset>5</bitOffset> 28532 <bitWidth>1</bitWidth> 28533 </field> 28534 <field> 28535 <name>FFA6</name> 28536 <description>Filter FIFO assignment for filter 28537 6</description> 28538 <bitOffset>6</bitOffset> 28539 <bitWidth>1</bitWidth> 28540 </field> 28541 <field> 28542 <name>FFA7</name> 28543 <description>Filter FIFO assignment for filter 28544 7</description> 28545 <bitOffset>7</bitOffset> 28546 <bitWidth>1</bitWidth> 28547 </field> 28548 <field> 28549 <name>FFA8</name> 28550 <description>Filter FIFO assignment for filter 28551 8</description> 28552 <bitOffset>8</bitOffset> 28553 <bitWidth>1</bitWidth> 28554 </field> 28555 <field> 28556 <name>FFA9</name> 28557 <description>Filter FIFO assignment for filter 28558 9</description> 28559 <bitOffset>9</bitOffset> 28560 <bitWidth>1</bitWidth> 28561 </field> 28562 <field> 28563 <name>FFA10</name> 28564 <description>Filter FIFO assignment for filter 28565 10</description> 28566 <bitOffset>10</bitOffset> 28567 <bitWidth>1</bitWidth> 28568 </field> 28569 <field> 28570 <name>FFA11</name> 28571 <description>Filter FIFO assignment for filter 28572 11</description> 28573 <bitOffset>11</bitOffset> 28574 <bitWidth>1</bitWidth> 28575 </field> 28576 <field> 28577 <name>FFA12</name> 28578 <description>Filter FIFO assignment for filter 28579 12</description> 28580 <bitOffset>12</bitOffset> 28581 <bitWidth>1</bitWidth> 28582 </field> 28583 <field> 28584 <name>FFA13</name> 28585 <description>Filter FIFO assignment for filter 28586 13</description> 28587 <bitOffset>13</bitOffset> 28588 <bitWidth>1</bitWidth> 28589 </field> 28590 <field> 28591 <name>FFA14</name> 28592 <description>Filter FIFO assignment for filter 28593 14</description> 28594 <bitOffset>14</bitOffset> 28595 <bitWidth>1</bitWidth> 28596 </field> 28597 <field> 28598 <name>FFA15</name> 28599 <description>Filter FIFO assignment for filter 28600 15</description> 28601 <bitOffset>15</bitOffset> 28602 <bitWidth>1</bitWidth> 28603 </field> 28604 <field> 28605 <name>FFA16</name> 28606 <description>Filter FIFO assignment for filter 28607 16</description> 28608 <bitOffset>16</bitOffset> 28609 <bitWidth>1</bitWidth> 28610 </field> 28611 <field> 28612 <name>FFA17</name> 28613 <description>Filter FIFO assignment for filter 28614 17</description> 28615 <bitOffset>17</bitOffset> 28616 <bitWidth>1</bitWidth> 28617 </field> 28618 <field> 28619 <name>FFA18</name> 28620 <description>Filter FIFO assignment for filter 28621 18</description> 28622 <bitOffset>18</bitOffset> 28623 <bitWidth>1</bitWidth> 28624 </field> 28625 <field> 28626 <name>FFA19</name> 28627 <description>Filter FIFO assignment for filter 28628 19</description> 28629 <bitOffset>19</bitOffset> 28630 <bitWidth>1</bitWidth> 28631 </field> 28632 <field> 28633 <name>FFA20</name> 28634 <description>Filter FIFO assignment for filter 28635 20</description> 28636 <bitOffset>20</bitOffset> 28637 <bitWidth>1</bitWidth> 28638 </field> 28639 <field> 28640 <name>FFA21</name> 28641 <description>Filter FIFO assignment for filter 28642 21</description> 28643 <bitOffset>21</bitOffset> 28644 <bitWidth>1</bitWidth> 28645 </field> 28646 <field> 28647 <name>FFA22</name> 28648 <description>Filter FIFO assignment for filter 28649 22</description> 28650 <bitOffset>22</bitOffset> 28651 <bitWidth>1</bitWidth> 28652 </field> 28653 <field> 28654 <name>FFA23</name> 28655 <description>Filter FIFO assignment for filter 28656 23</description> 28657 <bitOffset>23</bitOffset> 28658 <bitWidth>1</bitWidth> 28659 </field> 28660 <field> 28661 <name>FFA24</name> 28662 <description>Filter FIFO assignment for filter 28663 24</description> 28664 <bitOffset>24</bitOffset> 28665 <bitWidth>1</bitWidth> 28666 </field> 28667 <field> 28668 <name>FFA25</name> 28669 <description>Filter FIFO assignment for filter 28670 25</description> 28671 <bitOffset>25</bitOffset> 28672 <bitWidth>1</bitWidth> 28673 </field> 28674 <field> 28675 <name>FFA26</name> 28676 <description>Filter FIFO assignment for filter 28677 26</description> 28678 <bitOffset>26</bitOffset> 28679 <bitWidth>1</bitWidth> 28680 </field> 28681 <field> 28682 <name>FFA27</name> 28683 <description>Filter FIFO assignment for filter 28684 27</description> 28685 <bitOffset>27</bitOffset> 28686 <bitWidth>1</bitWidth> 28687 </field> 28688 </fields> 28689 </register> 28690 <register> 28691 <name>FA1R</name> 28692 <displayName>FA1R</displayName> 28693 <description>filter activation register</description> 28694 <addressOffset>0x21C</addressOffset> 28695 <size>0x20</size> 28696 <access>read-write</access> 28697 <resetValue>0x00000000</resetValue> 28698 <fields> 28699 <field> 28700 <name>FACT0</name> 28701 <description>Filter active</description> 28702 <bitOffset>0</bitOffset> 28703 <bitWidth>1</bitWidth> 28704 </field> 28705 <field> 28706 <name>FACT1</name> 28707 <description>Filter active</description> 28708 <bitOffset>1</bitOffset> 28709 <bitWidth>1</bitWidth> 28710 </field> 28711 <field> 28712 <name>FACT2</name> 28713 <description>Filter active</description> 28714 <bitOffset>2</bitOffset> 28715 <bitWidth>1</bitWidth> 28716 </field> 28717 <field> 28718 <name>FACT3</name> 28719 <description>Filter active</description> 28720 <bitOffset>3</bitOffset> 28721 <bitWidth>1</bitWidth> 28722 </field> 28723 <field> 28724 <name>FACT4</name> 28725 <description>Filter active</description> 28726 <bitOffset>4</bitOffset> 28727 <bitWidth>1</bitWidth> 28728 </field> 28729 <field> 28730 <name>FACT5</name> 28731 <description>Filter active</description> 28732 <bitOffset>5</bitOffset> 28733 <bitWidth>1</bitWidth> 28734 </field> 28735 <field> 28736 <name>FACT6</name> 28737 <description>Filter active</description> 28738 <bitOffset>6</bitOffset> 28739 <bitWidth>1</bitWidth> 28740 </field> 28741 <field> 28742 <name>FACT7</name> 28743 <description>Filter active</description> 28744 <bitOffset>7</bitOffset> 28745 <bitWidth>1</bitWidth> 28746 </field> 28747 <field> 28748 <name>FACT8</name> 28749 <description>Filter active</description> 28750 <bitOffset>8</bitOffset> 28751 <bitWidth>1</bitWidth> 28752 </field> 28753 <field> 28754 <name>FACT9</name> 28755 <description>Filter active</description> 28756 <bitOffset>9</bitOffset> 28757 <bitWidth>1</bitWidth> 28758 </field> 28759 <field> 28760 <name>FACT10</name> 28761 <description>Filter active</description> 28762 <bitOffset>10</bitOffset> 28763 <bitWidth>1</bitWidth> 28764 </field> 28765 <field> 28766 <name>FACT11</name> 28767 <description>Filter active</description> 28768 <bitOffset>11</bitOffset> 28769 <bitWidth>1</bitWidth> 28770 </field> 28771 <field> 28772 <name>FACT12</name> 28773 <description>Filter active</description> 28774 <bitOffset>12</bitOffset> 28775 <bitWidth>1</bitWidth> 28776 </field> 28777 <field> 28778 <name>FACT13</name> 28779 <description>Filter active</description> 28780 <bitOffset>13</bitOffset> 28781 <bitWidth>1</bitWidth> 28782 </field> 28783 <field> 28784 <name>FACT14</name> 28785 <description>Filter active</description> 28786 <bitOffset>14</bitOffset> 28787 <bitWidth>1</bitWidth> 28788 </field> 28789 <field> 28790 <name>FACT15</name> 28791 <description>Filter active</description> 28792 <bitOffset>15</bitOffset> 28793 <bitWidth>1</bitWidth> 28794 </field> 28795 <field> 28796 <name>FACT16</name> 28797 <description>Filter active</description> 28798 <bitOffset>16</bitOffset> 28799 <bitWidth>1</bitWidth> 28800 </field> 28801 <field> 28802 <name>FACT17</name> 28803 <description>Filter active</description> 28804 <bitOffset>17</bitOffset> 28805 <bitWidth>1</bitWidth> 28806 </field> 28807 <field> 28808 <name>FACT18</name> 28809 <description>Filter active</description> 28810 <bitOffset>18</bitOffset> 28811 <bitWidth>1</bitWidth> 28812 </field> 28813 <field> 28814 <name>FACT19</name> 28815 <description>Filter active</description> 28816 <bitOffset>19</bitOffset> 28817 <bitWidth>1</bitWidth> 28818 </field> 28819 <field> 28820 <name>FACT20</name> 28821 <description>Filter active</description> 28822 <bitOffset>20</bitOffset> 28823 <bitWidth>1</bitWidth> 28824 </field> 28825 <field> 28826 <name>FACT21</name> 28827 <description>Filter active</description> 28828 <bitOffset>21</bitOffset> 28829 <bitWidth>1</bitWidth> 28830 </field> 28831 <field> 28832 <name>FACT22</name> 28833 <description>Filter active</description> 28834 <bitOffset>22</bitOffset> 28835 <bitWidth>1</bitWidth> 28836 </field> 28837 <field> 28838 <name>FACT23</name> 28839 <description>Filter active</description> 28840 <bitOffset>23</bitOffset> 28841 <bitWidth>1</bitWidth> 28842 </field> 28843 <field> 28844 <name>FACT24</name> 28845 <description>Filter active</description> 28846 <bitOffset>24</bitOffset> 28847 <bitWidth>1</bitWidth> 28848 </field> 28849 <field> 28850 <name>FACT25</name> 28851 <description>Filter active</description> 28852 <bitOffset>25</bitOffset> 28853 <bitWidth>1</bitWidth> 28854 </field> 28855 <field> 28856 <name>FACT26</name> 28857 <description>Filter active</description> 28858 <bitOffset>26</bitOffset> 28859 <bitWidth>1</bitWidth> 28860 </field> 28861 <field> 28862 <name>FACT27</name> 28863 <description>Filter active</description> 28864 <bitOffset>27</bitOffset> 28865 <bitWidth>1</bitWidth> 28866 </field> 28867 </fields> 28868 </register> 28869 </registers> 28870 </peripheral> 28871 <peripheral derivedFrom="CAN1"> 28872 <name>CAN2</name> 28873 <baseAddress>0x40006800</baseAddress> 28874 <interrupt> 28875 <name>CAN2_TX</name> 28876 <description>CAN2 TX interrupts</description> 28877 <value>63</value> 28878 </interrupt> 28879 <interrupt> 28880 <name>CAN2_RX0</name> 28881 <description>CAN2 RX0 interrupts</description> 28882 <value>64</value> 28883 </interrupt> 28884 <interrupt> 28885 <name>CAN2_RX1</name> 28886 <description>CAN2 RX1 interrupts</description> 28887 <value>65</value> 28888 </interrupt> 28889 <interrupt> 28890 <name>CAN2_SCE</name> 28891 <description>CAN2 SCE interrupt</description> 28892 <value>66</value> 28893 </interrupt> 28894 </peripheral> 28895 <peripheral> 28896 <name>FLASH</name> 28897 <description>FLASH</description> 28898 <groupName>FLASH</groupName> 28899 <baseAddress>0x40023C00</baseAddress> 28900 <addressBlock> 28901 <offset>0x0</offset> 28902 <size>0x400</size> 28903 <usage>registers</usage> 28904 </addressBlock> 28905 <registers> 28906 <register> 28907 <name>ACR</name> 28908 <displayName>ACR</displayName> 28909 <description>Flash access control register</description> 28910 <addressOffset>0x0</addressOffset> 28911 <size>0x20</size> 28912 <resetValue>0x00000000</resetValue> 28913 <fields> 28914 <field> 28915 <name>LATENCY</name> 28916 <description>Latency</description> 28917 <bitOffset>0</bitOffset> 28918 <bitWidth>3</bitWidth> 28919 <access>read-write</access> 28920 <enumeratedValues><name>LATENCY</name><usage>read-write</usage><enumeratedValue><name>WS0</name><description>0 wait states</description><value>0</value></enumeratedValue><enumeratedValue><name>WS1</name><description>1 wait states</description><value>1</value></enumeratedValue><enumeratedValue><name>WS2</name><description>2 wait states</description><value>2</value></enumeratedValue><enumeratedValue><name>WS3</name><description>3 wait states</description><value>3</value></enumeratedValue><enumeratedValue><name>WS4</name><description>4 wait states</description><value>4</value></enumeratedValue><enumeratedValue><name>WS5</name><description>5 wait states</description><value>5</value></enumeratedValue><enumeratedValue><name>WS6</name><description>6 wait states</description><value>6</value></enumeratedValue><enumeratedValue><name>WS7</name><description>7 wait states</description><value>7</value></enumeratedValue></enumeratedValues> 28921 </field> 28922 <field> 28923 <name>PRFTEN</name> 28924 <description>Prefetch enable</description> 28925 <bitOffset>8</bitOffset> 28926 <bitWidth>1</bitWidth> 28927 <access>read-write</access> 28928 <enumeratedValues><name>PRFTEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Prefetch is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Prefetch is enabled</description><value>1</value></enumeratedValue></enumeratedValues> 28929 </field> 28930 <field> 28931 <name>ICEN</name> 28932 <description>Instruction cache enable</description> 28933 <bitOffset>9</bitOffset> 28934 <bitWidth>1</bitWidth> 28935 <access>read-write</access> 28936 <enumeratedValues><name>ICEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Instruction cache is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Instruction cache is enabled</description><value>1</value></enumeratedValue></enumeratedValues> 28937 </field> 28938 <field> 28939 <name>DCEN</name> 28940 <description>Data cache enable</description> 28941 <bitOffset>10</bitOffset> 28942 <bitWidth>1</bitWidth> 28943 <access>read-write</access> 28944 <enumeratedValues><name>DCEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Data cache is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Data cache is enabled</description><value>1</value></enumeratedValue></enumeratedValues> 28945 </field> 28946 <field> 28947 <name>ICRST</name> 28948 <description>Instruction cache reset</description> 28949 <bitOffset>11</bitOffset> 28950 <bitWidth>1</bitWidth> 28951 <access>write-only</access> 28952 <enumeratedValues><name>ICRST</name><usage>read-write</usage><enumeratedValue><name>NotReset</name><description>Instruction cache is not reset</description><value>0</value></enumeratedValue><enumeratedValue><name>Reset</name><description>Instruction cache is reset</description><value>1</value></enumeratedValue></enumeratedValues> 28953 </field> 28954 <field> 28955 <name>DCRST</name> 28956 <description>Data cache reset</description> 28957 <bitOffset>12</bitOffset> 28958 <bitWidth>1</bitWidth> 28959 <access>read-write</access> 28960 <enumeratedValues><name>DCRST</name><usage>read-write</usage><enumeratedValue><name>NotReset</name><description>Data cache is not reset</description><value>0</value></enumeratedValue><enumeratedValue><name>Reset</name><description>Data cache is reset</description><value>1</value></enumeratedValue></enumeratedValues> 28961 </field> 28962 </fields> 28963 </register> 28964 <register> 28965 <name>KEYR</name> 28966 <displayName>KEYR</displayName> 28967 <description>Flash key register</description> 28968 <addressOffset>0x4</addressOffset> 28969 <size>0x20</size> 28970 <access>write-only</access> 28971 <resetValue>0x00000000</resetValue> 28972 <fields> 28973 <field> 28974 <name>KEY</name> 28975 <description>FPEC key</description> 28976 <bitOffset>0</bitOffset> 28977 <bitWidth>32</bitWidth> 28978 <writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint> 28979 </field> 28980 </fields> 28981 </register> 28982 <register> 28983 <name>OPTKEYR</name> 28984 <displayName>OPTKEYR</displayName> 28985 <description>Flash option key register</description> 28986 <addressOffset>0x8</addressOffset> 28987 <size>0x20</size> 28988 <access>write-only</access> 28989 <resetValue>0x00000000</resetValue> 28990 <fields> 28991 <field> 28992 <name>OPTKEY</name> 28993 <description>Option byte key</description> 28994 <bitOffset>0</bitOffset> 28995 <bitWidth>32</bitWidth> 28996 <writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint> 28997 </field> 28998 </fields> 28999 </register> 29000 <register> 29001 <name>SR</name> 29002 <displayName>SR</displayName> 29003 <description>Status register</description> 29004 <addressOffset>0xC</addressOffset> 29005 <size>0x20</size> 29006 <resetValue>0x00000000</resetValue> 29007 <fields> 29008 <field> 29009 <name>EOP</name> 29010 <description>End of operation</description> 29011 <bitOffset>0</bitOffset> 29012 <bitWidth>1</bitWidth> 29013 <access>read-write</access> 29014 </field> 29015 <field> 29016 <name>OPERR</name> 29017 <description>Operation error</description> 29018 <bitOffset>1</bitOffset> 29019 <bitWidth>1</bitWidth> 29020 <access>read-write</access> 29021 </field> 29022 <field> 29023 <name>WRPERR</name> 29024 <description>Write protection error</description> 29025 <bitOffset>4</bitOffset> 29026 <bitWidth>1</bitWidth> 29027 <access>read-write</access> 29028 </field> 29029 <field> 29030 <name>PGAERR</name> 29031 <description>Programming alignment 29032 error</description> 29033 <bitOffset>5</bitOffset> 29034 <bitWidth>1</bitWidth> 29035 <access>read-write</access> 29036 </field> 29037 <field> 29038 <name>PGPERR</name> 29039 <description>Programming parallelism 29040 error</description> 29041 <bitOffset>6</bitOffset> 29042 <bitWidth>1</bitWidth> 29043 <access>read-write</access> 29044 </field> 29045 <field> 29046 <name>PGSERR</name> 29047 <description>Programming sequence error</description> 29048 <bitOffset>7</bitOffset> 29049 <bitWidth>1</bitWidth> 29050 <access>read-write</access> 29051 </field> 29052 <field> 29053 <name>BSY</name> 29054 <description>Busy</description> 29055 <bitOffset>16</bitOffset> 29056 <bitWidth>1</bitWidth> 29057 <access>read-only</access> 29058 </field> 29059 </fields> 29060 </register> 29061 <register> 29062 <name>CR</name> 29063 <displayName>CR</displayName> 29064 <description>Control register</description> 29065 <addressOffset>0x10</addressOffset> 29066 <size>0x20</size> 29067 <access>read-write</access> 29068 <resetValue>0x80000000</resetValue> 29069 <fields> 29070 <field> 29071 <name>PG</name> 29072 <description>Programming</description> 29073 <bitOffset>0</bitOffset> 29074 <bitWidth>1</bitWidth> 29075 <enumeratedValues><name>PG</name><usage>read-write</usage><enumeratedValue><name>Program</name><description>Flash programming activated</description><value>1</value></enumeratedValue></enumeratedValues> 29076 </field> 29077 <field> 29078 <name>SER</name> 29079 <description>Sector Erase</description> 29080 <bitOffset>1</bitOffset> 29081 <bitWidth>1</bitWidth> 29082 <enumeratedValues><name>SER</name><usage>read-write</usage><enumeratedValue><name>SectorErase</name><description>Erase activated for selected sector</description><value>1</value></enumeratedValue></enumeratedValues> 29083 </field> 29084 <field> 29085 <name>MER</name> 29086 <description>Mass Erase</description> 29087 <bitOffset>2</bitOffset> 29088 <bitWidth>1</bitWidth> 29089 <enumeratedValues><name>MER</name><usage>read-write</usage><enumeratedValue><name>MassErase</name><description>Erase activated for all user sectors</description><value>1</value></enumeratedValue></enumeratedValues> 29090 </field> 29091 <field> 29092 <name>SNB</name> 29093 <description>Sector number</description> 29094 <bitOffset>3</bitOffset> 29095 <bitWidth>4</bitWidth> 29096 <writeConstraint><range><minimum>0</minimum><maximum>11</maximum></range></writeConstraint> 29097 </field> 29098 <field> 29099 <name>PSIZE</name> 29100 <description>Program size</description> 29101 <bitOffset>8</bitOffset> 29102 <bitWidth>2</bitWidth> 29103 <enumeratedValues><name>PSIZE</name><usage>read-write</usage><enumeratedValue><name>PSIZE8</name><description>Program x8</description><value>0</value></enumeratedValue><enumeratedValue><name>PSIZE16</name><description>Program x16</description><value>1</value></enumeratedValue><enumeratedValue><name>PSIZE32</name><description>Program x32</description><value>2</value></enumeratedValue><enumeratedValue><name>PSIZE64</name><description>Program x64</description><value>3</value></enumeratedValue></enumeratedValues> 29104 </field> 29105 <field> 29106 <name>STRT</name> 29107 <description>Start</description> 29108 <bitOffset>16</bitOffset> 29109 <bitWidth>1</bitWidth> 29110 <enumeratedValues><name>STRT</name><usage>read-write</usage><enumeratedValue><name>Start</name><description>Trigger an erase operation</description><value>1</value></enumeratedValue></enumeratedValues> 29111 </field> 29112 <field> 29113 <name>EOPIE</name> 29114 <description>End of operation interrupt 29115 enable</description> 29116 <bitOffset>24</bitOffset> 29117 <bitWidth>1</bitWidth> 29118 <enumeratedValues><name>EOPIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>End of operation interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>End of operation interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 29119 </field> 29120 <field> 29121 <name>ERRIE</name> 29122 <description>Error interrupt enable</description> 29123 <bitOffset>25</bitOffset> 29124 <bitWidth>1</bitWidth> 29125 <enumeratedValues><name>ERRIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Error interrupt generation disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Error interrupt generation enabled</description><value>1</value></enumeratedValue></enumeratedValues> 29126 </field> 29127 <field> 29128 <name>LOCK</name> 29129 <description>Lock</description> 29130 <bitOffset>31</bitOffset> 29131 <bitWidth>1</bitWidth> 29132 <enumeratedValues><name>LOCK</name><usage>read-write</usage><enumeratedValue><name>Unlocked</name><description>FLASH_CR register is unlocked</description><value>0</value></enumeratedValue><enumeratedValue><name>Locked</name><description>FLASH_CR register is locked</description><value>1</value></enumeratedValue></enumeratedValues> 29133 </field> 29134 </fields> 29135 </register> 29136 <register> 29137 <name>OPTCR</name> 29138 <displayName>OPTCR</displayName> 29139 <description>Flash option control register</description> 29140 <addressOffset>0x14</addressOffset> 29141 <size>0x20</size> 29142 <access>read-write</access> 29143 <resetValue>0x00000014</resetValue> 29144 <fields> 29145 <field> 29146 <name>OPTLOCK</name> 29147 <description>Option lock</description> 29148 <bitOffset>0</bitOffset> 29149 <bitWidth>1</bitWidth> 29150 </field> 29151 <field> 29152 <name>OPTSTRT</name> 29153 <description>Option start</description> 29154 <bitOffset>1</bitOffset> 29155 <bitWidth>1</bitWidth> 29156 </field> 29157 <field> 29158 <name>BOR_LEV</name> 29159 <description>BOR reset Level</description> 29160 <bitOffset>2</bitOffset> 29161 <bitWidth>2</bitWidth> 29162 </field> 29163 <field> 29164 <name>WDG_SW</name> 29165 <description>WDG_SW User option bytes</description> 29166 <bitOffset>5</bitOffset> 29167 <bitWidth>1</bitWidth> 29168 </field> 29169 <field> 29170 <name>nRST_STOP</name> 29171 <description>nRST_STOP User option 29172 bytes</description> 29173 <bitOffset>6</bitOffset> 29174 <bitWidth>1</bitWidth> 29175 </field> 29176 <field> 29177 <name>nRST_STDBY</name> 29178 <description>nRST_STDBY User option 29179 bytes</description> 29180 <bitOffset>7</bitOffset> 29181 <bitWidth>1</bitWidth> 29182 </field> 29183 <field> 29184 <name>RDP</name> 29185 <description>Read protect</description> 29186 <bitOffset>8</bitOffset> 29187 <bitWidth>8</bitWidth> 29188 </field> 29189 <field> 29190 <name>nWRP</name> 29191 <description>Not write protect</description> 29192 <bitOffset>16</bitOffset> 29193 <bitWidth>12</bitWidth> 29194 </field> 29195 </fields> 29196 </register> 29197 </registers> 29198 </peripheral> 29199 <peripheral> 29200 <name>EXTI</name> 29201 <description>External interrupt/event 29202 controller</description> 29203 <groupName>EXTI</groupName> 29204 <baseAddress>0x40013C00</baseAddress> 29205 <addressBlock> 29206 <offset>0x0</offset> 29207 <size>0x400</size> 29208 <usage>registers</usage> 29209 </addressBlock> 29210 <interrupt> 29211 <name>TAMP_STAMP</name> 29212 <description>Tamper and TimeStamp interrupts through the 29213 EXTI line</description> 29214 <value>2</value> 29215 </interrupt> 29216 <interrupt> 29217 <name>EXTI0</name> 29218 <description>EXTI Line0 interrupt</description> 29219 <value>6</value> 29220 </interrupt> 29221 <interrupt> 29222 <name>EXTI1</name> 29223 <description>EXTI Line1 interrupt</description> 29224 <value>7</value> 29225 </interrupt> 29226 <interrupt> 29227 <name>EXTI2</name> 29228 <description>EXTI Line2 interrupt</description> 29229 <value>8</value> 29230 </interrupt> 29231 <interrupt> 29232 <name>EXTI3</name> 29233 <description>EXTI Line3 interrupt</description> 29234 <value>9</value> 29235 </interrupt> 29236 <interrupt> 29237 <name>EXTI4</name> 29238 <description>EXTI Line4 interrupt</description> 29239 <value>10</value> 29240 </interrupt> 29241 <interrupt> 29242 <name>EXTI9_5</name> 29243 <description>EXTI Line[9:5] interrupts</description> 29244 <value>23</value> 29245 </interrupt> 29246 <interrupt> 29247 <name>EXTI9_5</name> 29248 <description>EXTI Line[9:5] interrupts</description> 29249 <value>23</value> 29250 </interrupt> 29251 <interrupt> 29252 <name>EXTI15_10</name> 29253 <description>EXTI Line[15:10] interrupts</description> 29254 <value>40</value> 29255 </interrupt> 29256 <registers> 29257 <register> 29258 <name>IMR</name> 29259 <displayName>IMR</displayName> 29260 <description>Interrupt mask register 29261 (EXTI_IMR)</description> 29262 <addressOffset>0x0</addressOffset> 29263 <size>0x20</size> 29264 <access>read-write</access> 29265 <resetValue>0x00000000</resetValue> 29266 <fields> 29267 <field> 29268 <name>MR0</name> 29269 <description>Interrupt Mask on line 0</description> 29270 <bitOffset>0</bitOffset> 29271 <bitWidth>1</bitWidth> 29272 <enumeratedValues><name>MR0</name><usage>read-write</usage><enumeratedValue><name>Masked</name><description>Interrupt request line is masked</description><value>0</value></enumeratedValue><enumeratedValue><name>Unmasked</name><description>Interrupt request line is unmasked</description><value>1</value></enumeratedValue></enumeratedValues> 29273 </field> 29274 <field> 29275 <name>MR1</name> 29276 <description>Interrupt Mask on line 1</description> 29277 <bitOffset>1</bitOffset> 29278 <bitWidth>1</bitWidth> 29279 <enumeratedValues derivedFrom="MR0"/> 29280 </field> 29281 <field> 29282 <name>MR2</name> 29283 <description>Interrupt Mask on line 2</description> 29284 <bitOffset>2</bitOffset> 29285 <bitWidth>1</bitWidth> 29286 <enumeratedValues derivedFrom="MR0"/> 29287 </field> 29288 <field> 29289 <name>MR3</name> 29290 <description>Interrupt Mask on line 3</description> 29291 <bitOffset>3</bitOffset> 29292 <bitWidth>1</bitWidth> 29293 <enumeratedValues derivedFrom="MR0"/> 29294 </field> 29295 <field> 29296 <name>MR4</name> 29297 <description>Interrupt Mask on line 4</description> 29298 <bitOffset>4</bitOffset> 29299 <bitWidth>1</bitWidth> 29300 <enumeratedValues derivedFrom="MR0"/> 29301 </field> 29302 <field> 29303 <name>MR5</name> 29304 <description>Interrupt Mask on line 5</description> 29305 <bitOffset>5</bitOffset> 29306 <bitWidth>1</bitWidth> 29307 <enumeratedValues derivedFrom="MR0"/> 29308 </field> 29309 <field> 29310 <name>MR6</name> 29311 <description>Interrupt Mask on line 6</description> 29312 <bitOffset>6</bitOffset> 29313 <bitWidth>1</bitWidth> 29314 <enumeratedValues derivedFrom="MR0"/> 29315 </field> 29316 <field> 29317 <name>MR7</name> 29318 <description>Interrupt Mask on line 7</description> 29319 <bitOffset>7</bitOffset> 29320 <bitWidth>1</bitWidth> 29321 <enumeratedValues derivedFrom="MR0"/> 29322 </field> 29323 <field> 29324 <name>MR8</name> 29325 <description>Interrupt Mask on line 8</description> 29326 <bitOffset>8</bitOffset> 29327 <bitWidth>1</bitWidth> 29328 <enumeratedValues derivedFrom="MR0"/> 29329 </field> 29330 <field> 29331 <name>MR9</name> 29332 <description>Interrupt Mask on line 9</description> 29333 <bitOffset>9</bitOffset> 29334 <bitWidth>1</bitWidth> 29335 <enumeratedValues derivedFrom="MR0"/> 29336 </field> 29337 <field> 29338 <name>MR10</name> 29339 <description>Interrupt Mask on line 10</description> 29340 <bitOffset>10</bitOffset> 29341 <bitWidth>1</bitWidth> 29342 <enumeratedValues derivedFrom="MR0"/> 29343 </field> 29344 <field> 29345 <name>MR11</name> 29346 <description>Interrupt Mask on line 11</description> 29347 <bitOffset>11</bitOffset> 29348 <bitWidth>1</bitWidth> 29349 <enumeratedValues derivedFrom="MR0"/> 29350 </field> 29351 <field> 29352 <name>MR12</name> 29353 <description>Interrupt Mask on line 12</description> 29354 <bitOffset>12</bitOffset> 29355 <bitWidth>1</bitWidth> 29356 <enumeratedValues derivedFrom="MR0"/> 29357 </field> 29358 <field> 29359 <name>MR13</name> 29360 <description>Interrupt Mask on line 13</description> 29361 <bitOffset>13</bitOffset> 29362 <bitWidth>1</bitWidth> 29363 <enumeratedValues derivedFrom="MR0"/> 29364 </field> 29365 <field> 29366 <name>MR14</name> 29367 <description>Interrupt Mask on line 14</description> 29368 <bitOffset>14</bitOffset> 29369 <bitWidth>1</bitWidth> 29370 <enumeratedValues derivedFrom="MR0"/> 29371 </field> 29372 <field> 29373 <name>MR15</name> 29374 <description>Interrupt Mask on line 15</description> 29375 <bitOffset>15</bitOffset> 29376 <bitWidth>1</bitWidth> 29377 <enumeratedValues derivedFrom="MR0"/> 29378 </field> 29379 <field> 29380 <name>MR16</name> 29381 <description>Interrupt Mask on line 16</description> 29382 <bitOffset>16</bitOffset> 29383 <bitWidth>1</bitWidth> 29384 <enumeratedValues derivedFrom="MR0"/> 29385 </field> 29386 <field> 29387 <name>MR17</name> 29388 <description>Interrupt Mask on line 17</description> 29389 <bitOffset>17</bitOffset> 29390 <bitWidth>1</bitWidth> 29391 <enumeratedValues derivedFrom="MR0"/> 29392 </field> 29393 <field> 29394 <name>MR18</name> 29395 <description>Interrupt Mask on line 18</description> 29396 <bitOffset>18</bitOffset> 29397 <bitWidth>1</bitWidth> 29398 <enumeratedValues derivedFrom="MR0"/> 29399 </field> 29400 <field> 29401 <name>MR19</name> 29402 <description>Interrupt Mask on line 19</description> 29403 <bitOffset>19</bitOffset> 29404 <bitWidth>1</bitWidth> 29405 <enumeratedValues derivedFrom="MR0"/> 29406 </field> 29407 <field> 29408 <name>MR20</name> 29409 <description>Interrupt Mask on line 20</description> 29410 <bitOffset>20</bitOffset> 29411 <bitWidth>1</bitWidth> 29412 <enumeratedValues derivedFrom="MR0"/> 29413 </field> 29414 <field> 29415 <name>MR21</name> 29416 <description>Interrupt Mask on line 21</description> 29417 <bitOffset>21</bitOffset> 29418 <bitWidth>1</bitWidth> 29419 <enumeratedValues derivedFrom="MR0"/> 29420 </field> 29421 <field> 29422 <name>MR22</name> 29423 <description>Interrupt Mask on line 22</description> 29424 <bitOffset>22</bitOffset> 29425 <bitWidth>1</bitWidth> 29426 <enumeratedValues derivedFrom="MR0"/> 29427 </field> 29428 </fields> 29429 </register> 29430 <register> 29431 <name>EMR</name> 29432 <displayName>EMR</displayName> 29433 <description>Event mask register (EXTI_EMR)</description> 29434 <addressOffset>0x4</addressOffset> 29435 <size>0x20</size> 29436 <access>read-write</access> 29437 <resetValue>0x00000000</resetValue> 29438 <fields> 29439 <field> 29440 <name>MR0</name> 29441 <description>Event Mask on line 0</description> 29442 <bitOffset>0</bitOffset> 29443 <bitWidth>1</bitWidth> 29444 <enumeratedValues><name>MR0</name><usage>read-write</usage><enumeratedValue><name>Masked</name><description>Interrupt request line is masked</description><value>0</value></enumeratedValue><enumeratedValue><name>Unmasked</name><description>Interrupt request line is unmasked</description><value>1</value></enumeratedValue></enumeratedValues> 29445 </field> 29446 <field> 29447 <name>MR1</name> 29448 <description>Event Mask on line 1</description> 29449 <bitOffset>1</bitOffset> 29450 <bitWidth>1</bitWidth> 29451 <enumeratedValues derivedFrom="MR0"/> 29452 </field> 29453 <field> 29454 <name>MR2</name> 29455 <description>Event Mask on line 2</description> 29456 <bitOffset>2</bitOffset> 29457 <bitWidth>1</bitWidth> 29458 <enumeratedValues derivedFrom="MR0"/> 29459 </field> 29460 <field> 29461 <name>MR3</name> 29462 <description>Event Mask on line 3</description> 29463 <bitOffset>3</bitOffset> 29464 <bitWidth>1</bitWidth> 29465 <enumeratedValues derivedFrom="MR0"/> 29466 </field> 29467 <field> 29468 <name>MR4</name> 29469 <description>Event Mask on line 4</description> 29470 <bitOffset>4</bitOffset> 29471 <bitWidth>1</bitWidth> 29472 <enumeratedValues derivedFrom="MR0"/> 29473 </field> 29474 <field> 29475 <name>MR5</name> 29476 <description>Event Mask on line 5</description> 29477 <bitOffset>5</bitOffset> 29478 <bitWidth>1</bitWidth> 29479 <enumeratedValues derivedFrom="MR0"/> 29480 </field> 29481 <field> 29482 <name>MR6</name> 29483 <description>Event Mask on line 6</description> 29484 <bitOffset>6</bitOffset> 29485 <bitWidth>1</bitWidth> 29486 <enumeratedValues derivedFrom="MR0"/> 29487 </field> 29488 <field> 29489 <name>MR7</name> 29490 <description>Event Mask on line 7</description> 29491 <bitOffset>7</bitOffset> 29492 <bitWidth>1</bitWidth> 29493 <enumeratedValues derivedFrom="MR0"/> 29494 </field> 29495 <field> 29496 <name>MR8</name> 29497 <description>Event Mask on line 8</description> 29498 <bitOffset>8</bitOffset> 29499 <bitWidth>1</bitWidth> 29500 <enumeratedValues derivedFrom="MR0"/> 29501 </field> 29502 <field> 29503 <name>MR9</name> 29504 <description>Event Mask on line 9</description> 29505 <bitOffset>9</bitOffset> 29506 <bitWidth>1</bitWidth> 29507 <enumeratedValues derivedFrom="MR0"/> 29508 </field> 29509 <field> 29510 <name>MR10</name> 29511 <description>Event Mask on line 10</description> 29512 <bitOffset>10</bitOffset> 29513 <bitWidth>1</bitWidth> 29514 <enumeratedValues derivedFrom="MR0"/> 29515 </field> 29516 <field> 29517 <name>MR11</name> 29518 <description>Event Mask on line 11</description> 29519 <bitOffset>11</bitOffset> 29520 <bitWidth>1</bitWidth> 29521 <enumeratedValues derivedFrom="MR0"/> 29522 </field> 29523 <field> 29524 <name>MR12</name> 29525 <description>Event Mask on line 12</description> 29526 <bitOffset>12</bitOffset> 29527 <bitWidth>1</bitWidth> 29528 <enumeratedValues derivedFrom="MR0"/> 29529 </field> 29530 <field> 29531 <name>MR13</name> 29532 <description>Event Mask on line 13</description> 29533 <bitOffset>13</bitOffset> 29534 <bitWidth>1</bitWidth> 29535 <enumeratedValues derivedFrom="MR0"/> 29536 </field> 29537 <field> 29538 <name>MR14</name> 29539 <description>Event Mask on line 14</description> 29540 <bitOffset>14</bitOffset> 29541 <bitWidth>1</bitWidth> 29542 <enumeratedValues derivedFrom="MR0"/> 29543 </field> 29544 <field> 29545 <name>MR15</name> 29546 <description>Event Mask on line 15</description> 29547 <bitOffset>15</bitOffset> 29548 <bitWidth>1</bitWidth> 29549 <enumeratedValues derivedFrom="MR0"/> 29550 </field> 29551 <field> 29552 <name>MR16</name> 29553 <description>Event Mask on line 16</description> 29554 <bitOffset>16</bitOffset> 29555 <bitWidth>1</bitWidth> 29556 <enumeratedValues derivedFrom="MR0"/> 29557 </field> 29558 <field> 29559 <name>MR17</name> 29560 <description>Event Mask on line 17</description> 29561 <bitOffset>17</bitOffset> 29562 <bitWidth>1</bitWidth> 29563 <enumeratedValues derivedFrom="MR0"/> 29564 </field> 29565 <field> 29566 <name>MR18</name> 29567 <description>Event Mask on line 18</description> 29568 <bitOffset>18</bitOffset> 29569 <bitWidth>1</bitWidth> 29570 <enumeratedValues derivedFrom="MR0"/> 29571 </field> 29572 <field> 29573 <name>MR19</name> 29574 <description>Event Mask on line 19</description> 29575 <bitOffset>19</bitOffset> 29576 <bitWidth>1</bitWidth> 29577 <enumeratedValues derivedFrom="MR0"/> 29578 </field> 29579 <field> 29580 <name>MR20</name> 29581 <description>Event Mask on line 20</description> 29582 <bitOffset>20</bitOffset> 29583 <bitWidth>1</bitWidth> 29584 <enumeratedValues derivedFrom="MR0"/> 29585 </field> 29586 <field> 29587 <name>MR21</name> 29588 <description>Event Mask on line 21</description> 29589 <bitOffset>21</bitOffset> 29590 <bitWidth>1</bitWidth> 29591 <enumeratedValues derivedFrom="MR0"/> 29592 </field> 29593 <field> 29594 <name>MR22</name> 29595 <description>Event Mask on line 22</description> 29596 <bitOffset>22</bitOffset> 29597 <bitWidth>1</bitWidth> 29598 <enumeratedValues derivedFrom="MR0"/> 29599 </field> 29600 </fields> 29601 </register> 29602 <register> 29603 <name>RTSR</name> 29604 <displayName>RTSR</displayName> 29605 <description>Rising Trigger selection register 29606 (EXTI_RTSR)</description> 29607 <addressOffset>0x8</addressOffset> 29608 <size>0x20</size> 29609 <access>read-write</access> 29610 <resetValue>0x00000000</resetValue> 29611 <fields> 29612 <field> 29613 <name>TR0</name> 29614 <description>Rising trigger event configuration of 29615 line 0</description> 29616 <bitOffset>0</bitOffset> 29617 <bitWidth>1</bitWidth> 29618 <enumeratedValues><name>TR0</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Rising edge trigger is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Rising edge trigger is enabled</description><value>1</value></enumeratedValue></enumeratedValues> 29619 </field> 29620 <field> 29621 <name>TR1</name> 29622 <description>Rising trigger event configuration of 29623 line 1</description> 29624 <bitOffset>1</bitOffset> 29625 <bitWidth>1</bitWidth> 29626 <enumeratedValues derivedFrom="TR0"/> 29627 </field> 29628 <field> 29629 <name>TR2</name> 29630 <description>Rising trigger event configuration of 29631 line 2</description> 29632 <bitOffset>2</bitOffset> 29633 <bitWidth>1</bitWidth> 29634 <enumeratedValues derivedFrom="TR0"/> 29635 </field> 29636 <field> 29637 <name>TR3</name> 29638 <description>Rising trigger event configuration of 29639 line 3</description> 29640 <bitOffset>3</bitOffset> 29641 <bitWidth>1</bitWidth> 29642 <enumeratedValues derivedFrom="TR0"/> 29643 </field> 29644 <field> 29645 <name>TR4</name> 29646 <description>Rising trigger event configuration of 29647 line 4</description> 29648 <bitOffset>4</bitOffset> 29649 <bitWidth>1</bitWidth> 29650 <enumeratedValues derivedFrom="TR0"/> 29651 </field> 29652 <field> 29653 <name>TR5</name> 29654 <description>Rising trigger event configuration of 29655 line 5</description> 29656 <bitOffset>5</bitOffset> 29657 <bitWidth>1</bitWidth> 29658 <enumeratedValues derivedFrom="TR0"/> 29659 </field> 29660 <field> 29661 <name>TR6</name> 29662 <description>Rising trigger event configuration of 29663 line 6</description> 29664 <bitOffset>6</bitOffset> 29665 <bitWidth>1</bitWidth> 29666 <enumeratedValues derivedFrom="TR0"/> 29667 </field> 29668 <field> 29669 <name>TR7</name> 29670 <description>Rising trigger event configuration of 29671 line 7</description> 29672 <bitOffset>7</bitOffset> 29673 <bitWidth>1</bitWidth> 29674 <enumeratedValues derivedFrom="TR0"/> 29675 </field> 29676 <field> 29677 <name>TR8</name> 29678 <description>Rising trigger event configuration of 29679 line 8</description> 29680 <bitOffset>8</bitOffset> 29681 <bitWidth>1</bitWidth> 29682 <enumeratedValues derivedFrom="TR0"/> 29683 </field> 29684 <field> 29685 <name>TR9</name> 29686 <description>Rising trigger event configuration of 29687 line 9</description> 29688 <bitOffset>9</bitOffset> 29689 <bitWidth>1</bitWidth> 29690 <enumeratedValues derivedFrom="TR0"/> 29691 </field> 29692 <field> 29693 <name>TR10</name> 29694 <description>Rising trigger event configuration of 29695 line 10</description> 29696 <bitOffset>10</bitOffset> 29697 <bitWidth>1</bitWidth> 29698 <enumeratedValues derivedFrom="TR0"/> 29699 </field> 29700 <field> 29701 <name>TR11</name> 29702 <description>Rising trigger event configuration of 29703 line 11</description> 29704 <bitOffset>11</bitOffset> 29705 <bitWidth>1</bitWidth> 29706 <enumeratedValues derivedFrom="TR0"/> 29707 </field> 29708 <field> 29709 <name>TR12</name> 29710 <description>Rising trigger event configuration of 29711 line 12</description> 29712 <bitOffset>12</bitOffset> 29713 <bitWidth>1</bitWidth> 29714 <enumeratedValues derivedFrom="TR0"/> 29715 </field> 29716 <field> 29717 <name>TR13</name> 29718 <description>Rising trigger event configuration of 29719 line 13</description> 29720 <bitOffset>13</bitOffset> 29721 <bitWidth>1</bitWidth> 29722 <enumeratedValues derivedFrom="TR0"/> 29723 </field> 29724 <field> 29725 <name>TR14</name> 29726 <description>Rising trigger event configuration of 29727 line 14</description> 29728 <bitOffset>14</bitOffset> 29729 <bitWidth>1</bitWidth> 29730 <enumeratedValues derivedFrom="TR0"/> 29731 </field> 29732 <field> 29733 <name>TR15</name> 29734 <description>Rising trigger event configuration of 29735 line 15</description> 29736 <bitOffset>15</bitOffset> 29737 <bitWidth>1</bitWidth> 29738 <enumeratedValues derivedFrom="TR0"/> 29739 </field> 29740 <field> 29741 <name>TR16</name> 29742 <description>Rising trigger event configuration of 29743 line 16</description> 29744 <bitOffset>16</bitOffset> 29745 <bitWidth>1</bitWidth> 29746 <enumeratedValues derivedFrom="TR0"/> 29747 </field> 29748 <field> 29749 <name>TR17</name> 29750 <description>Rising trigger event configuration of 29751 line 17</description> 29752 <bitOffset>17</bitOffset> 29753 <bitWidth>1</bitWidth> 29754 <enumeratedValues derivedFrom="TR0"/> 29755 </field> 29756 <field> 29757 <name>TR18</name> 29758 <description>Rising trigger event configuration of 29759 line 18</description> 29760 <bitOffset>18</bitOffset> 29761 <bitWidth>1</bitWidth> 29762 <enumeratedValues derivedFrom="TR0"/> 29763 </field> 29764 <field> 29765 <name>TR19</name> 29766 <description>Rising trigger event configuration of 29767 line 19</description> 29768 <bitOffset>19</bitOffset> 29769 <bitWidth>1</bitWidth> 29770 <enumeratedValues derivedFrom="TR0"/> 29771 </field> 29772 <field> 29773 <name>TR20</name> 29774 <description>Rising trigger event configuration of 29775 line 20</description> 29776 <bitOffset>20</bitOffset> 29777 <bitWidth>1</bitWidth> 29778 <enumeratedValues derivedFrom="TR0"/> 29779 </field> 29780 <field> 29781 <name>TR21</name> 29782 <description>Rising trigger event configuration of 29783 line 21</description> 29784 <bitOffset>21</bitOffset> 29785 <bitWidth>1</bitWidth> 29786 <enumeratedValues derivedFrom="TR0"/> 29787 </field> 29788 <field> 29789 <name>TR22</name> 29790 <description>Rising trigger event configuration of 29791 line 22</description> 29792 <bitOffset>22</bitOffset> 29793 <bitWidth>1</bitWidth> 29794 <enumeratedValues derivedFrom="TR0"/> 29795 </field> 29796 </fields> 29797 </register> 29798 <register> 29799 <name>FTSR</name> 29800 <displayName>FTSR</displayName> 29801 <description>Falling Trigger selection register 29802 (EXTI_FTSR)</description> 29803 <addressOffset>0xC</addressOffset> 29804 <size>0x20</size> 29805 <access>read-write</access> 29806 <resetValue>0x00000000</resetValue> 29807 <fields> 29808 <field> 29809 <name>TR0</name> 29810 <description>Falling trigger event configuration of 29811 line 0</description> 29812 <bitOffset>0</bitOffset> 29813 <bitWidth>1</bitWidth> 29814 <enumeratedValues><name>TR0</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Falling edge trigger is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Falling edge trigger is enabled</description><value>1</value></enumeratedValue></enumeratedValues> 29815 </field> 29816 <field> 29817 <name>TR1</name> 29818 <description>Falling trigger event configuration of 29819 line 1</description> 29820 <bitOffset>1</bitOffset> 29821 <bitWidth>1</bitWidth> 29822 <enumeratedValues derivedFrom="TR0"/> 29823 </field> 29824 <field> 29825 <name>TR2</name> 29826 <description>Falling trigger event configuration of 29827 line 2</description> 29828 <bitOffset>2</bitOffset> 29829 <bitWidth>1</bitWidth> 29830 <enumeratedValues derivedFrom="TR0"/> 29831 </field> 29832 <field> 29833 <name>TR3</name> 29834 <description>Falling trigger event configuration of 29835 line 3</description> 29836 <bitOffset>3</bitOffset> 29837 <bitWidth>1</bitWidth> 29838 <enumeratedValues derivedFrom="TR0"/> 29839 </field> 29840 <field> 29841 <name>TR4</name> 29842 <description>Falling trigger event configuration of 29843 line 4</description> 29844 <bitOffset>4</bitOffset> 29845 <bitWidth>1</bitWidth> 29846 <enumeratedValues derivedFrom="TR0"/> 29847 </field> 29848 <field> 29849 <name>TR5</name> 29850 <description>Falling trigger event configuration of 29851 line 5</description> 29852 <bitOffset>5</bitOffset> 29853 <bitWidth>1</bitWidth> 29854 <enumeratedValues derivedFrom="TR0"/> 29855 </field> 29856 <field> 29857 <name>TR6</name> 29858 <description>Falling trigger event configuration of 29859 line 6</description> 29860 <bitOffset>6</bitOffset> 29861 <bitWidth>1</bitWidth> 29862 <enumeratedValues derivedFrom="TR0"/> 29863 </field> 29864 <field> 29865 <name>TR7</name> 29866 <description>Falling trigger event configuration of 29867 line 7</description> 29868 <bitOffset>7</bitOffset> 29869 <bitWidth>1</bitWidth> 29870 <enumeratedValues derivedFrom="TR0"/> 29871 </field> 29872 <field> 29873 <name>TR8</name> 29874 <description>Falling trigger event configuration of 29875 line 8</description> 29876 <bitOffset>8</bitOffset> 29877 <bitWidth>1</bitWidth> 29878 <enumeratedValues derivedFrom="TR0"/> 29879 </field> 29880 <field> 29881 <name>TR9</name> 29882 <description>Falling trigger event configuration of 29883 line 9</description> 29884 <bitOffset>9</bitOffset> 29885 <bitWidth>1</bitWidth> 29886 <enumeratedValues derivedFrom="TR0"/> 29887 </field> 29888 <field> 29889 <name>TR10</name> 29890 <description>Falling trigger event configuration of 29891 line 10</description> 29892 <bitOffset>10</bitOffset> 29893 <bitWidth>1</bitWidth> 29894 <enumeratedValues derivedFrom="TR0"/> 29895 </field> 29896 <field> 29897 <name>TR11</name> 29898 <description>Falling trigger event configuration of 29899 line 11</description> 29900 <bitOffset>11</bitOffset> 29901 <bitWidth>1</bitWidth> 29902 <enumeratedValues derivedFrom="TR0"/> 29903 </field> 29904 <field> 29905 <name>TR12</name> 29906 <description>Falling trigger event configuration of 29907 line 12</description> 29908 <bitOffset>12</bitOffset> 29909 <bitWidth>1</bitWidth> 29910 <enumeratedValues derivedFrom="TR0"/> 29911 </field> 29912 <field> 29913 <name>TR13</name> 29914 <description>Falling trigger event configuration of 29915 line 13</description> 29916 <bitOffset>13</bitOffset> 29917 <bitWidth>1</bitWidth> 29918 <enumeratedValues derivedFrom="TR0"/> 29919 </field> 29920 <field> 29921 <name>TR14</name> 29922 <description>Falling trigger event configuration of 29923 line 14</description> 29924 <bitOffset>14</bitOffset> 29925 <bitWidth>1</bitWidth> 29926 <enumeratedValues derivedFrom="TR0"/> 29927 </field> 29928 <field> 29929 <name>TR15</name> 29930 <description>Falling trigger event configuration of 29931 line 15</description> 29932 <bitOffset>15</bitOffset> 29933 <bitWidth>1</bitWidth> 29934 <enumeratedValues derivedFrom="TR0"/> 29935 </field> 29936 <field> 29937 <name>TR16</name> 29938 <description>Falling trigger event configuration of 29939 line 16</description> 29940 <bitOffset>16</bitOffset> 29941 <bitWidth>1</bitWidth> 29942 <enumeratedValues derivedFrom="TR0"/> 29943 </field> 29944 <field> 29945 <name>TR17</name> 29946 <description>Falling trigger event configuration of 29947 line 17</description> 29948 <bitOffset>17</bitOffset> 29949 <bitWidth>1</bitWidth> 29950 <enumeratedValues derivedFrom="TR0"/> 29951 </field> 29952 <field> 29953 <name>TR18</name> 29954 <description>Falling trigger event configuration of 29955 line 18</description> 29956 <bitOffset>18</bitOffset> 29957 <bitWidth>1</bitWidth> 29958 <enumeratedValues derivedFrom="TR0"/> 29959 </field> 29960 <field> 29961 <name>TR19</name> 29962 <description>Falling trigger event configuration of 29963 line 19</description> 29964 <bitOffset>19</bitOffset> 29965 <bitWidth>1</bitWidth> 29966 <enumeratedValues derivedFrom="TR0"/> 29967 </field> 29968 <field> 29969 <name>TR20</name> 29970 <description>Falling trigger event configuration of 29971 line 20</description> 29972 <bitOffset>20</bitOffset> 29973 <bitWidth>1</bitWidth> 29974 <enumeratedValues derivedFrom="TR0"/> 29975 </field> 29976 <field> 29977 <name>TR21</name> 29978 <description>Falling trigger event configuration of 29979 line 21</description> 29980 <bitOffset>21</bitOffset> 29981 <bitWidth>1</bitWidth> 29982 <enumeratedValues derivedFrom="TR0"/> 29983 </field> 29984 <field> 29985 <name>TR22</name> 29986 <description>Falling trigger event configuration of 29987 line 22</description> 29988 <bitOffset>22</bitOffset> 29989 <bitWidth>1</bitWidth> 29990 <enumeratedValues derivedFrom="TR0"/> 29991 </field> 29992 </fields> 29993 </register> 29994 <register> 29995 <name>SWIER</name> 29996 <displayName>SWIER</displayName> 29997 <description>Software interrupt event register 29998 (EXTI_SWIER)</description> 29999 <addressOffset>0x10</addressOffset> 30000 <size>0x20</size> 30001 <access>read-write</access> 30002 <resetValue>0x00000000</resetValue> 30003 <fields> 30004 <field> 30005 <name>SWIER0</name> 30006 <description>Software Interrupt on line 30007 0</description> 30008 <bitOffset>0</bitOffset> 30009 <bitWidth>1</bitWidth> 30010 <enumeratedValues><name>SWIER0W</name><usage>write</usage><enumeratedValue><name>Pend</name><description>Generates an interrupt request</description><value>1</value></enumeratedValue></enumeratedValues> 30011 </field> 30012 <field> 30013 <name>SWIER1</name> 30014 <description>Software Interrupt on line 30015 1</description> 30016 <bitOffset>1</bitOffset> 30017 <bitWidth>1</bitWidth> 30018 <enumeratedValues derivedFrom="SWIER0W"/> 30019 </field> 30020 <field> 30021 <name>SWIER2</name> 30022 <description>Software Interrupt on line 30023 2</description> 30024 <bitOffset>2</bitOffset> 30025 <bitWidth>1</bitWidth> 30026 <enumeratedValues derivedFrom="SWIER0W"/> 30027 </field> 30028 <field> 30029 <name>SWIER3</name> 30030 <description>Software Interrupt on line 30031 3</description> 30032 <bitOffset>3</bitOffset> 30033 <bitWidth>1</bitWidth> 30034 <enumeratedValues derivedFrom="SWIER0W"/> 30035 </field> 30036 <field> 30037 <name>SWIER4</name> 30038 <description>Software Interrupt on line 30039 4</description> 30040 <bitOffset>4</bitOffset> 30041 <bitWidth>1</bitWidth> 30042 <enumeratedValues derivedFrom="SWIER0W"/> 30043 </field> 30044 <field> 30045 <name>SWIER5</name> 30046 <description>Software Interrupt on line 30047 5</description> 30048 <bitOffset>5</bitOffset> 30049 <bitWidth>1</bitWidth> 30050 <enumeratedValues derivedFrom="SWIER0W"/> 30051 </field> 30052 <field> 30053 <name>SWIER6</name> 30054 <description>Software Interrupt on line 30055 6</description> 30056 <bitOffset>6</bitOffset> 30057 <bitWidth>1</bitWidth> 30058 <enumeratedValues derivedFrom="SWIER0W"/> 30059 </field> 30060 <field> 30061 <name>SWIER7</name> 30062 <description>Software Interrupt on line 30063 7</description> 30064 <bitOffset>7</bitOffset> 30065 <bitWidth>1</bitWidth> 30066 <enumeratedValues derivedFrom="SWIER0W"/> 30067 </field> 30068 <field> 30069 <name>SWIER8</name> 30070 <description>Software Interrupt on line 30071 8</description> 30072 <bitOffset>8</bitOffset> 30073 <bitWidth>1</bitWidth> 30074 <enumeratedValues derivedFrom="SWIER0W"/> 30075 </field> 30076 <field> 30077 <name>SWIER9</name> 30078 <description>Software Interrupt on line 30079 9</description> 30080 <bitOffset>9</bitOffset> 30081 <bitWidth>1</bitWidth> 30082 <enumeratedValues derivedFrom="SWIER0W"/> 30083 </field> 30084 <field> 30085 <name>SWIER10</name> 30086 <description>Software Interrupt on line 30087 10</description> 30088 <bitOffset>10</bitOffset> 30089 <bitWidth>1</bitWidth> 30090 <enumeratedValues derivedFrom="SWIER0W"/> 30091 </field> 30092 <field> 30093 <name>SWIER11</name> 30094 <description>Software Interrupt on line 30095 11</description> 30096 <bitOffset>11</bitOffset> 30097 <bitWidth>1</bitWidth> 30098 <enumeratedValues derivedFrom="SWIER0W"/> 30099 </field> 30100 <field> 30101 <name>SWIER12</name> 30102 <description>Software Interrupt on line 30103 12</description> 30104 <bitOffset>12</bitOffset> 30105 <bitWidth>1</bitWidth> 30106 <enumeratedValues derivedFrom="SWIER0W"/> 30107 </field> 30108 <field> 30109 <name>SWIER13</name> 30110 <description>Software Interrupt on line 30111 13</description> 30112 <bitOffset>13</bitOffset> 30113 <bitWidth>1</bitWidth> 30114 <enumeratedValues derivedFrom="SWIER0W"/> 30115 </field> 30116 <field> 30117 <name>SWIER14</name> 30118 <description>Software Interrupt on line 30119 14</description> 30120 <bitOffset>14</bitOffset> 30121 <bitWidth>1</bitWidth> 30122 <enumeratedValues derivedFrom="SWIER0W"/> 30123 </field> 30124 <field> 30125 <name>SWIER15</name> 30126 <description>Software Interrupt on line 30127 15</description> 30128 <bitOffset>15</bitOffset> 30129 <bitWidth>1</bitWidth> 30130 <enumeratedValues derivedFrom="SWIER0W"/> 30131 </field> 30132 <field> 30133 <name>SWIER16</name> 30134 <description>Software Interrupt on line 30135 16</description> 30136 <bitOffset>16</bitOffset> 30137 <bitWidth>1</bitWidth> 30138 <enumeratedValues derivedFrom="SWIER0W"/> 30139 </field> 30140 <field> 30141 <name>SWIER17</name> 30142 <description>Software Interrupt on line 30143 17</description> 30144 <bitOffset>17</bitOffset> 30145 <bitWidth>1</bitWidth> 30146 <enumeratedValues derivedFrom="SWIER0W"/> 30147 </field> 30148 <field> 30149 <name>SWIER18</name> 30150 <description>Software Interrupt on line 30151 18</description> 30152 <bitOffset>18</bitOffset> 30153 <bitWidth>1</bitWidth> 30154 <enumeratedValues derivedFrom="SWIER0W"/> 30155 </field> 30156 <field> 30157 <name>SWIER19</name> 30158 <description>Software Interrupt on line 30159 19</description> 30160 <bitOffset>19</bitOffset> 30161 <bitWidth>1</bitWidth> 30162 <enumeratedValues derivedFrom="SWIER0W"/> 30163 </field> 30164 <field> 30165 <name>SWIER20</name> 30166 <description>Software Interrupt on line 30167 20</description> 30168 <bitOffset>20</bitOffset> 30169 <bitWidth>1</bitWidth> 30170 <enumeratedValues derivedFrom="SWIER0W"/> 30171 </field> 30172 <field> 30173 <name>SWIER21</name> 30174 <description>Software Interrupt on line 30175 21</description> 30176 <bitOffset>21</bitOffset> 30177 <bitWidth>1</bitWidth> 30178 <enumeratedValues derivedFrom="SWIER0W"/> 30179 </field> 30180 <field> 30181 <name>SWIER22</name> 30182 <description>Software Interrupt on line 30183 22</description> 30184 <bitOffset>22</bitOffset> 30185 <bitWidth>1</bitWidth> 30186 <enumeratedValues derivedFrom="SWIER0W"/> 30187 </field> 30188 </fields> 30189 </register> 30190 <register> 30191 <name>PR</name> 30192 <displayName>PR</displayName> 30193 <description>Pending register (EXTI_PR)</description> 30194 <addressOffset>0x14</addressOffset> 30195 <size>0x20</size> 30196 <access>read-write</access> 30197 <resetValue>0x00000000</resetValue> 30198 <fields> 30199 <field> 30200 <name>PR0</name> 30201 <description>Pending bit 0</description> 30202 <bitOffset>0</bitOffset> 30203 <bitWidth>1</bitWidth> 30204 <enumeratedValues><name>PR0R</name><usage>read</usage><enumeratedValue><name>NotPending</name><description>No trigger request occurred</description><value>0</value></enumeratedValue><enumeratedValue><name>Pending</name><description>Selected trigger request occurred</description><value>1</value></enumeratedValue></enumeratedValues> 30205 <enumeratedValues><name>PR0W</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clears pending bit</description><value>1</value></enumeratedValue></enumeratedValues> 30206 </field> 30207 <field> 30208 <name>PR1</name> 30209 <description>Pending bit 1</description> 30210 <bitOffset>1</bitOffset> 30211 <bitWidth>1</bitWidth> 30212 <enumeratedValues derivedFrom="PR0R"/> 30213 <enumeratedValues derivedFrom="PR0W"/> 30214 </field> 30215 <field> 30216 <name>PR2</name> 30217 <description>Pending bit 2</description> 30218 <bitOffset>2</bitOffset> 30219 <bitWidth>1</bitWidth> 30220 <enumeratedValues derivedFrom="PR0R"/> 30221 <enumeratedValues derivedFrom="PR0W"/> 30222 </field> 30223 <field> 30224 <name>PR3</name> 30225 <description>Pending bit 3</description> 30226 <bitOffset>3</bitOffset> 30227 <bitWidth>1</bitWidth> 30228 <enumeratedValues derivedFrom="PR0R"/> 30229 <enumeratedValues derivedFrom="PR0W"/> 30230 </field> 30231 <field> 30232 <name>PR4</name> 30233 <description>Pending bit 4</description> 30234 <bitOffset>4</bitOffset> 30235 <bitWidth>1</bitWidth> 30236 <enumeratedValues derivedFrom="PR0R"/> 30237 <enumeratedValues derivedFrom="PR0W"/> 30238 </field> 30239 <field> 30240 <name>PR5</name> 30241 <description>Pending bit 5</description> 30242 <bitOffset>5</bitOffset> 30243 <bitWidth>1</bitWidth> 30244 <enumeratedValues derivedFrom="PR0R"/> 30245 <enumeratedValues derivedFrom="PR0W"/> 30246 </field> 30247 <field> 30248 <name>PR6</name> 30249 <description>Pending bit 6</description> 30250 <bitOffset>6</bitOffset> 30251 <bitWidth>1</bitWidth> 30252 <enumeratedValues derivedFrom="PR0R"/> 30253 <enumeratedValues derivedFrom="PR0W"/> 30254 </field> 30255 <field> 30256 <name>PR7</name> 30257 <description>Pending bit 7</description> 30258 <bitOffset>7</bitOffset> 30259 <bitWidth>1</bitWidth> 30260 <enumeratedValues derivedFrom="PR0R"/> 30261 <enumeratedValues derivedFrom="PR0W"/> 30262 </field> 30263 <field> 30264 <name>PR8</name> 30265 <description>Pending bit 8</description> 30266 <bitOffset>8</bitOffset> 30267 <bitWidth>1</bitWidth> 30268 <enumeratedValues derivedFrom="PR0R"/> 30269 <enumeratedValues derivedFrom="PR0W"/> 30270 </field> 30271 <field> 30272 <name>PR9</name> 30273 <description>Pending bit 9</description> 30274 <bitOffset>9</bitOffset> 30275 <bitWidth>1</bitWidth> 30276 <enumeratedValues derivedFrom="PR0R"/> 30277 <enumeratedValues derivedFrom="PR0W"/> 30278 </field> 30279 <field> 30280 <name>PR10</name> 30281 <description>Pending bit 10</description> 30282 <bitOffset>10</bitOffset> 30283 <bitWidth>1</bitWidth> 30284 <enumeratedValues derivedFrom="PR0R"/> 30285 <enumeratedValues derivedFrom="PR0W"/> 30286 </field> 30287 <field> 30288 <name>PR11</name> 30289 <description>Pending bit 11</description> 30290 <bitOffset>11</bitOffset> 30291 <bitWidth>1</bitWidth> 30292 <enumeratedValues derivedFrom="PR0R"/> 30293 <enumeratedValues derivedFrom="PR0W"/> 30294 </field> 30295 <field> 30296 <name>PR12</name> 30297 <description>Pending bit 12</description> 30298 <bitOffset>12</bitOffset> 30299 <bitWidth>1</bitWidth> 30300 <enumeratedValues derivedFrom="PR0R"/> 30301 <enumeratedValues derivedFrom="PR0W"/> 30302 </field> 30303 <field> 30304 <name>PR13</name> 30305 <description>Pending bit 13</description> 30306 <bitOffset>13</bitOffset> 30307 <bitWidth>1</bitWidth> 30308 <enumeratedValues derivedFrom="PR0R"/> 30309 <enumeratedValues derivedFrom="PR0W"/> 30310 </field> 30311 <field> 30312 <name>PR14</name> 30313 <description>Pending bit 14</description> 30314 <bitOffset>14</bitOffset> 30315 <bitWidth>1</bitWidth> 30316 <enumeratedValues derivedFrom="PR0R"/> 30317 <enumeratedValues derivedFrom="PR0W"/> 30318 </field> 30319 <field> 30320 <name>PR15</name> 30321 <description>Pending bit 15</description> 30322 <bitOffset>15</bitOffset> 30323 <bitWidth>1</bitWidth> 30324 <enumeratedValues derivedFrom="PR0R"/> 30325 <enumeratedValues derivedFrom="PR0W"/> 30326 </field> 30327 <field> 30328 <name>PR16</name> 30329 <description>Pending bit 16</description> 30330 <bitOffset>16</bitOffset> 30331 <bitWidth>1</bitWidth> 30332 <enumeratedValues derivedFrom="PR0R"/> 30333 <enumeratedValues derivedFrom="PR0W"/> 30334 </field> 30335 <field> 30336 <name>PR17</name> 30337 <description>Pending bit 17</description> 30338 <bitOffset>17</bitOffset> 30339 <bitWidth>1</bitWidth> 30340 <enumeratedValues derivedFrom="PR0R"/> 30341 <enumeratedValues derivedFrom="PR0W"/> 30342 </field> 30343 <field> 30344 <name>PR18</name> 30345 <description>Pending bit 18</description> 30346 <bitOffset>18</bitOffset> 30347 <bitWidth>1</bitWidth> 30348 <enumeratedValues derivedFrom="PR0R"/> 30349 <enumeratedValues derivedFrom="PR0W"/> 30350 </field> 30351 <field> 30352 <name>PR19</name> 30353 <description>Pending bit 19</description> 30354 <bitOffset>19</bitOffset> 30355 <bitWidth>1</bitWidth> 30356 <enumeratedValues derivedFrom="PR0R"/> 30357 <enumeratedValues derivedFrom="PR0W"/> 30358 </field> 30359 <field> 30360 <name>PR20</name> 30361 <description>Pending bit 20</description> 30362 <bitOffset>20</bitOffset> 30363 <bitWidth>1</bitWidth> 30364 <enumeratedValues derivedFrom="PR0R"/> 30365 <enumeratedValues derivedFrom="PR0W"/> 30366 </field> 30367 <field> 30368 <name>PR21</name> 30369 <description>Pending bit 21</description> 30370 <bitOffset>21</bitOffset> 30371 <bitWidth>1</bitWidth> 30372 <enumeratedValues derivedFrom="PR0R"/> 30373 <enumeratedValues derivedFrom="PR0W"/> 30374 </field> 30375 <field> 30376 <name>PR22</name> 30377 <description>Pending bit 22</description> 30378 <bitOffset>22</bitOffset> 30379 <bitWidth>1</bitWidth> 30380 <enumeratedValues derivedFrom="PR0R"/> 30381 <enumeratedValues derivedFrom="PR0W"/> 30382 </field> 30383 </fields> 30384 </register> 30385 </registers> 30386 </peripheral> 30387 <peripheral> 30388 <name>OTG_HS_GLOBAL</name> 30389 <description>USB on the go high speed</description> 30390 <groupName>USB_OTG_HS</groupName> 30391 <baseAddress>0x40040000</baseAddress> 30392 <addressBlock> 30393 <offset>0x0</offset> 30394 <size>0x131</size> 30395 <usage>registers</usage> 30396 </addressBlock> 30397 <interrupt> 30398 <name>OTG_HS_EP1_OUT</name> 30399 <description>USB On The Go HS End Point 1 Out global 30400 interrupt</description> 30401 <value>74</value> 30402 </interrupt> 30403 <interrupt> 30404 <name>OTG_HS_EP1_IN</name> 30405 <description>USB On The Go HS End Point 1 In global 30406 interrupt</description> 30407 <value>75</value> 30408 </interrupt> 30409 <interrupt> 30410 <name>OTG_HS_WKUP</name> 30411 <description>USB On The Go HS Wakeup through EXTI 30412 interrupt</description> 30413 <value>76</value> 30414 </interrupt> 30415 <interrupt> 30416 <name>OTG_HS</name> 30417 <description>USB On The Go HS global 30418 interrupt</description> 30419 <value>77</value> 30420 </interrupt> 30421 <registers> 30422 <register> 30423 <name>GOTGCTL</name> 30424 <displayName>GOTGCTL</displayName> 30425 <description>OTG_HS control and status 30426 register</description> 30427 <addressOffset>0x0</addressOffset> 30428 <size>32</size> 30429 <resetValue>0x00000800</resetValue> 30430 <fields> 30431 <field> 30432 <name>SRQSCS</name> 30433 <description>Session request success</description> 30434 <bitOffset>0</bitOffset> 30435 <bitWidth>1</bitWidth> 30436 <access>read-only</access> 30437 </field> 30438 <field> 30439 <name>SRQ</name> 30440 <description>Session request</description> 30441 <bitOffset>1</bitOffset> 30442 <bitWidth>1</bitWidth> 30443 <access>read-write</access> 30444 </field> 30445 <field> 30446 <name>HNGSCS</name> 30447 <description>Host negotiation success</description> 30448 <bitOffset>8</bitOffset> 30449 <bitWidth>1</bitWidth> 30450 <access>read-only</access> 30451 </field> 30452 <field> 30453 <name>HNPRQ</name> 30454 <description>HNP request</description> 30455 <bitOffset>9</bitOffset> 30456 <bitWidth>1</bitWidth> 30457 <access>read-write</access> 30458 </field> 30459 <field> 30460 <name>HSHNPEN</name> 30461 <description>Host set HNP enable</description> 30462 <bitOffset>10</bitOffset> 30463 <bitWidth>1</bitWidth> 30464 <access>read-write</access> 30465 </field> 30466 <field> 30467 <name>DHNPEN</name> 30468 <description>Device HNP enabled</description> 30469 <bitOffset>11</bitOffset> 30470 <bitWidth>1</bitWidth> 30471 <access>read-write</access> 30472 </field> 30473 <field> 30474 <name>CIDSTS</name> 30475 <description>Connector ID status</description> 30476 <bitOffset>16</bitOffset> 30477 <bitWidth>1</bitWidth> 30478 <access>read-only</access> 30479 </field> 30480 <field> 30481 <name>DBCT</name> 30482 <description>Long/short debounce time</description> 30483 <bitOffset>17</bitOffset> 30484 <bitWidth>1</bitWidth> 30485 <access>read-only</access> 30486 </field> 30487 <field> 30488 <name>ASVLD</name> 30489 <description>A-session valid</description> 30490 <bitOffset>18</bitOffset> 30491 <bitWidth>1</bitWidth> 30492 <access>read-only</access> 30493 </field> 30494 <field> 30495 <name>BSVLD</name> 30496 <description>B-session valid</description> 30497 <bitOffset>19</bitOffset> 30498 <bitWidth>1</bitWidth> 30499 <access>read-only</access> 30500 </field> 30501 </fields> 30502 </register> 30503 <register> 30504 <name>GOTGINT</name> 30505 <displayName>GOTGINT</displayName> 30506 <description>OTG_HS interrupt register</description> 30507 <addressOffset>0x4</addressOffset> 30508 <size>32</size> 30509 <access>read-write</access> 30510 <resetValue>0x0</resetValue> 30511 <fields> 30512 <field> 30513 <name>SEDET</name> 30514 <description>Session end detected</description> 30515 <bitOffset>2</bitOffset> 30516 <bitWidth>1</bitWidth> 30517 </field> 30518 <field> 30519 <name>SRSSCHG</name> 30520 <description>Session request success status 30521 change</description> 30522 <bitOffset>8</bitOffset> 30523 <bitWidth>1</bitWidth> 30524 </field> 30525 <field> 30526 <name>HNSSCHG</name> 30527 <description>Host negotiation success status 30528 change</description> 30529 <bitOffset>9</bitOffset> 30530 <bitWidth>1</bitWidth> 30531 </field> 30532 <field> 30533 <name>HNGDET</name> 30534 <description>Host negotiation detected</description> 30535 <bitOffset>17</bitOffset> 30536 <bitWidth>1</bitWidth> 30537 </field> 30538 <field> 30539 <name>ADTOCHG</name> 30540 <description>A-device timeout change</description> 30541 <bitOffset>18</bitOffset> 30542 <bitWidth>1</bitWidth> 30543 </field> 30544 <field> 30545 <name>DBCDNE</name> 30546 <description>Debounce done</description> 30547 <bitOffset>19</bitOffset> 30548 <bitWidth>1</bitWidth> 30549 </field> 30550 </fields> 30551 </register> 30552 <register> 30553 <name>GAHBCFG</name> 30554 <displayName>GAHBCFG</displayName> 30555 <description>OTG_HS AHB configuration 30556 register</description> 30557 <addressOffset>0x8</addressOffset> 30558 <size>32</size> 30559 <access>read-write</access> 30560 <resetValue>0x0</resetValue> 30561 <fields> 30562 <field> 30563 <name>GINT</name> 30564 <description>Global interrupt mask</description> 30565 <bitOffset>0</bitOffset> 30566 <bitWidth>1</bitWidth> 30567 </field> 30568 <field> 30569 <name>HBSTLEN</name> 30570 <description>Burst length/type</description> 30571 <bitOffset>1</bitOffset> 30572 <bitWidth>4</bitWidth> 30573 </field> 30574 <field> 30575 <name>DMAEN</name> 30576 <description>DMA enable</description> 30577 <bitOffset>5</bitOffset> 30578 <bitWidth>1</bitWidth> 30579 </field> 30580 <field> 30581 <name>TXFELVL</name> 30582 <description>TxFIFO empty level</description> 30583 <bitOffset>7</bitOffset> 30584 <bitWidth>1</bitWidth> 30585 </field> 30586 <field> 30587 <name>PTXFELVL</name> 30588 <description>Periodic TxFIFO empty 30589 level</description> 30590 <bitOffset>8</bitOffset> 30591 <bitWidth>1</bitWidth> 30592 </field> 30593 </fields> 30594 </register> 30595 <register> 30596 <name>GUSBCFG</name> 30597 <displayName>GUSBCFG</displayName> 30598 <description>OTG_HS USB configuration 30599 register</description> 30600 <addressOffset>0xC</addressOffset> 30601 <size>32</size> 30602 <resetValue>0x00000A00</resetValue> 30603 <fields> 30604 <field> 30605 <name>TOCAL</name> 30606 <description>FS timeout calibration</description> 30607 <bitOffset>0</bitOffset> 30608 <bitWidth>3</bitWidth> 30609 <access>read-write</access> 30610 </field> 30611 <field> 30612 <name>PHYSEL</name> 30613 <description>USB 2.0 high-speed ULPI PHY or USB 1.1 30614 full-speed serial transceiver select</description> 30615 <bitOffset>6</bitOffset> 30616 <bitWidth>1</bitWidth> 30617 <access>write-only</access> 30618 </field> 30619 <field> 30620 <name>SRPCAP</name> 30621 <description>SRP-capable</description> 30622 <bitOffset>8</bitOffset> 30623 <bitWidth>1</bitWidth> 30624 <access>read-write</access> 30625 </field> 30626 <field> 30627 <name>HNPCAP</name> 30628 <description>HNP-capable</description> 30629 <bitOffset>9</bitOffset> 30630 <bitWidth>1</bitWidth> 30631 <access>read-write</access> 30632 </field> 30633 <field> 30634 <name>TRDT</name> 30635 <description>USB turnaround time</description> 30636 <bitOffset>10</bitOffset> 30637 <bitWidth>4</bitWidth> 30638 <access>read-write</access> 30639 </field> 30640 <field> 30641 <name>PHYLPCS</name> 30642 <description>PHY Low-power clock select</description> 30643 <bitOffset>15</bitOffset> 30644 <bitWidth>1</bitWidth> 30645 <access>read-write</access> 30646 </field> 30647 <field> 30648 <name>ULPIFSLS</name> 30649 <description>ULPI FS/LS select</description> 30650 <bitOffset>17</bitOffset> 30651 <bitWidth>1</bitWidth> 30652 <access>read-write</access> 30653 </field> 30654 <field> 30655 <name>ULPIAR</name> 30656 <description>ULPI Auto-resume</description> 30657 <bitOffset>18</bitOffset> 30658 <bitWidth>1</bitWidth> 30659 <access>read-write</access> 30660 </field> 30661 <field> 30662 <name>ULPICSM</name> 30663 <description>ULPI Clock SuspendM</description> 30664 <bitOffset>19</bitOffset> 30665 <bitWidth>1</bitWidth> 30666 <access>read-write</access> 30667 </field> 30668 <field> 30669 <name>ULPIEVBUSD</name> 30670 <description>ULPI External VBUS Drive</description> 30671 <bitOffset>20</bitOffset> 30672 <bitWidth>1</bitWidth> 30673 <access>read-write</access> 30674 </field> 30675 <field> 30676 <name>ULPIEVBUSI</name> 30677 <description>ULPI external VBUS 30678 indicator</description> 30679 <bitOffset>21</bitOffset> 30680 <bitWidth>1</bitWidth> 30681 <access>read-write</access> 30682 </field> 30683 <field> 30684 <name>TSDPS</name> 30685 <description>TermSel DLine pulsing 30686 selection</description> 30687 <bitOffset>22</bitOffset> 30688 <bitWidth>1</bitWidth> 30689 <access>read-write</access> 30690 </field> 30691 <field> 30692 <name>PCCI</name> 30693 <description>Indicator complement</description> 30694 <bitOffset>23</bitOffset> 30695 <bitWidth>1</bitWidth> 30696 <access>read-write</access> 30697 </field> 30698 <field> 30699 <name>PTCI</name> 30700 <description>Indicator pass through</description> 30701 <bitOffset>24</bitOffset> 30702 <bitWidth>1</bitWidth> 30703 <access>read-write</access> 30704 </field> 30705 <field> 30706 <name>ULPIIPD</name> 30707 <description>ULPI interface protect 30708 disable</description> 30709 <bitOffset>25</bitOffset> 30710 <bitWidth>1</bitWidth> 30711 <access>read-write</access> 30712 </field> 30713 <field> 30714 <name>FHMOD</name> 30715 <description>Forced host mode</description> 30716 <bitOffset>29</bitOffset> 30717 <bitWidth>1</bitWidth> 30718 <access>read-write</access> 30719 </field> 30720 <field> 30721 <name>FDMOD</name> 30722 <description>Forced peripheral mode</description> 30723 <bitOffset>30</bitOffset> 30724 <bitWidth>1</bitWidth> 30725 <access>read-write</access> 30726 </field> 30727 <field> 30728 <name>CTXPKT</name> 30729 <description>Corrupt Tx packet</description> 30730 <bitOffset>31</bitOffset> 30731 <bitWidth>1</bitWidth> 30732 <access>read-write</access> 30733 </field> 30734 </fields> 30735 </register> 30736 <register> 30737 <name>GRSTCTL</name> 30738 <displayName>GRSTCTL</displayName> 30739 <description>OTG_HS reset register</description> 30740 <addressOffset>0x10</addressOffset> 30741 <size>32</size> 30742 <resetValue>0x20000000</resetValue> 30743 <fields> 30744 <field> 30745 <name>CSRST</name> 30746 <description>Core soft reset</description> 30747 <bitOffset>0</bitOffset> 30748 <bitWidth>1</bitWidth> 30749 <access>read-write</access> 30750 </field> 30751 <field> 30752 <name>HSRST</name> 30753 <description>HCLK soft reset</description> 30754 <bitOffset>1</bitOffset> 30755 <bitWidth>1</bitWidth> 30756 <access>read-write</access> 30757 </field> 30758 <field> 30759 <name>FCRST</name> 30760 <description>Host frame counter reset</description> 30761 <bitOffset>2</bitOffset> 30762 <bitWidth>1</bitWidth> 30763 <access>read-write</access> 30764 </field> 30765 <field> 30766 <name>RXFFLSH</name> 30767 <description>RxFIFO flush</description> 30768 <bitOffset>4</bitOffset> 30769 <bitWidth>1</bitWidth> 30770 <access>read-write</access> 30771 </field> 30772 <field> 30773 <name>TXFFLSH</name> 30774 <description>TxFIFO flush</description> 30775 <bitOffset>5</bitOffset> 30776 <bitWidth>1</bitWidth> 30777 <access>read-write</access> 30778 </field> 30779 <field> 30780 <name>TXFNUM</name> 30781 <description>TxFIFO number</description> 30782 <bitOffset>6</bitOffset> 30783 <bitWidth>5</bitWidth> 30784 <access>read-write</access> 30785 </field> 30786 <field> 30787 <name>DMAREQ</name> 30788 <description>DMA request signal</description> 30789 <bitOffset>30</bitOffset> 30790 <bitWidth>1</bitWidth> 30791 <access>read-only</access> 30792 </field> 30793 <field> 30794 <name>AHBIDL</name> 30795 <description>AHB master idle</description> 30796 <bitOffset>31</bitOffset> 30797 <bitWidth>1</bitWidth> 30798 <access>read-only</access> 30799 </field> 30800 </fields> 30801 </register> 30802 <register> 30803 <name>GINTSTS</name> 30804 <displayName>GINTSTS</displayName> 30805 <description>OTG_HS core interrupt register</description> 30806 <addressOffset>0x14</addressOffset> 30807 <size>32</size> 30808 <resetValue>0x04000020</resetValue> 30809 <fields> 30810 <field> 30811 <name>CMOD</name> 30812 <description>Current mode of operation</description> 30813 <bitOffset>0</bitOffset> 30814 <bitWidth>1</bitWidth> 30815 <access>read-only</access> 30816 </field> 30817 <field> 30818 <name>MMIS</name> 30819 <description>Mode mismatch interrupt</description> 30820 <bitOffset>1</bitOffset> 30821 <bitWidth>1</bitWidth> 30822 <access>read-write</access> 30823 </field> 30824 <field> 30825 <name>OTGINT</name> 30826 <description>OTG interrupt</description> 30827 <bitOffset>2</bitOffset> 30828 <bitWidth>1</bitWidth> 30829 <access>read-only</access> 30830 </field> 30831 <field> 30832 <name>SOF</name> 30833 <description>Start of frame</description> 30834 <bitOffset>3</bitOffset> 30835 <bitWidth>1</bitWidth> 30836 <access>read-write</access> 30837 </field> 30838 <field> 30839 <name>RXFLVL</name> 30840 <description>RxFIFO nonempty</description> 30841 <bitOffset>4</bitOffset> 30842 <bitWidth>1</bitWidth> 30843 <access>read-only</access> 30844 </field> 30845 <field> 30846 <name>NPTXFE</name> 30847 <description>Nonperiodic TxFIFO empty</description> 30848 <bitOffset>5</bitOffset> 30849 <bitWidth>1</bitWidth> 30850 <access>read-only</access> 30851 </field> 30852 <field> 30853 <name>GINAKEFF</name> 30854 <description>Global IN nonperiodic NAK 30855 effective</description> 30856 <bitOffset>6</bitOffset> 30857 <bitWidth>1</bitWidth> 30858 <access>read-only</access> 30859 </field> 30860 <field> 30861 <name>BOUTNAKEFF</name> 30862 <description>Global OUT NAK effective</description> 30863 <bitOffset>7</bitOffset> 30864 <bitWidth>1</bitWidth> 30865 <access>read-only</access> 30866 </field> 30867 <field> 30868 <name>ESUSP</name> 30869 <description>Early suspend</description> 30870 <bitOffset>10</bitOffset> 30871 <bitWidth>1</bitWidth> 30872 <access>read-write</access> 30873 </field> 30874 <field> 30875 <name>USBSUSP</name> 30876 <description>USB suspend</description> 30877 <bitOffset>11</bitOffset> 30878 <bitWidth>1</bitWidth> 30879 <access>read-write</access> 30880 </field> 30881 <field> 30882 <name>USBRST</name> 30883 <description>USB reset</description> 30884 <bitOffset>12</bitOffset> 30885 <bitWidth>1</bitWidth> 30886 <access>read-write</access> 30887 </field> 30888 <field> 30889 <name>ENUMDNE</name> 30890 <description>Enumeration done</description> 30891 <bitOffset>13</bitOffset> 30892 <bitWidth>1</bitWidth> 30893 <access>read-write</access> 30894 </field> 30895 <field> 30896 <name>ISOODRP</name> 30897 <description>Isochronous OUT packet dropped 30898 interrupt</description> 30899 <bitOffset>14</bitOffset> 30900 <bitWidth>1</bitWidth> 30901 <access>read-write</access> 30902 </field> 30903 <field> 30904 <name>EOPF</name> 30905 <description>End of periodic frame 30906 interrupt</description> 30907 <bitOffset>15</bitOffset> 30908 <bitWidth>1</bitWidth> 30909 <access>read-write</access> 30910 </field> 30911 <field> 30912 <name>IEPINT</name> 30913 <description>IN endpoint interrupt</description> 30914 <bitOffset>18</bitOffset> 30915 <bitWidth>1</bitWidth> 30916 <access>read-only</access> 30917 </field> 30918 <field> 30919 <name>OEPINT</name> 30920 <description>OUT endpoint interrupt</description> 30921 <bitOffset>19</bitOffset> 30922 <bitWidth>1</bitWidth> 30923 <access>read-only</access> 30924 </field> 30925 <field> 30926 <name>IISOIXFR</name> 30927 <description>Incomplete isochronous IN 30928 transfer</description> 30929 <bitOffset>20</bitOffset> 30930 <bitWidth>1</bitWidth> 30931 <access>read-write</access> 30932 </field> 30933 <field> 30934 <name>PXFR_INCOMPISOOUT</name> 30935 <description>Incomplete periodic 30936 transfer</description> 30937 <bitOffset>21</bitOffset> 30938 <bitWidth>1</bitWidth> 30939 <access>read-write</access> 30940 </field> 30941 <field> 30942 <name>DATAFSUSP</name> 30943 <description>Data fetch suspended</description> 30944 <bitOffset>22</bitOffset> 30945 <bitWidth>1</bitWidth> 30946 <access>read-write</access> 30947 </field> 30948 <field> 30949 <name>HPRTINT</name> 30950 <description>Host port interrupt</description> 30951 <bitOffset>24</bitOffset> 30952 <bitWidth>1</bitWidth> 30953 <access>read-only</access> 30954 </field> 30955 <field> 30956 <name>HCINT</name> 30957 <description>Host channels interrupt</description> 30958 <bitOffset>25</bitOffset> 30959 <bitWidth>1</bitWidth> 30960 <access>read-only</access> 30961 </field> 30962 <field> 30963 <name>PTXFE</name> 30964 <description>Periodic TxFIFO empty</description> 30965 <bitOffset>26</bitOffset> 30966 <bitWidth>1</bitWidth> 30967 <access>read-only</access> 30968 </field> 30969 <field> 30970 <name>CIDSCHG</name> 30971 <description>Connector ID status change</description> 30972 <bitOffset>28</bitOffset> 30973 <bitWidth>1</bitWidth> 30974 <access>read-write</access> 30975 </field> 30976 <field> 30977 <name>DISCINT</name> 30978 <description>Disconnect detected 30979 interrupt</description> 30980 <bitOffset>29</bitOffset> 30981 <bitWidth>1</bitWidth> 30982 <access>read-write</access> 30983 </field> 30984 <field> 30985 <name>SRQINT</name> 30986 <description>Session request/new session detected 30987 interrupt</description> 30988 <bitOffset>30</bitOffset> 30989 <bitWidth>1</bitWidth> 30990 <access>read-write</access> 30991 </field> 30992 <field> 30993 <name>WKUPINT</name> 30994 <description>Resume/remote wakeup detected interrupt</description> 30995 <bitOffset>31</bitOffset> 30996 <bitWidth>1</bitWidth> 30997 <access>read-write</access> 30998 </field> 30999 </fields> 31000 </register> 31001 <register> 31002 <name>GINTMSK</name> 31003 <displayName>GINTMSK</displayName> 31004 <description>OTG_HS interrupt mask register</description> 31005 <addressOffset>0x18</addressOffset> 31006 <size>32</size> 31007 <resetValue>0x0</resetValue> 31008 <fields> 31009 <field> 31010 <name>MMISM</name> 31011 <description>Mode mismatch interrupt 31012 mask</description> 31013 <bitOffset>1</bitOffset> 31014 <bitWidth>1</bitWidth> 31015 <access>read-write</access> 31016 </field> 31017 <field> 31018 <name>OTGINT</name> 31019 <description>OTG interrupt mask</description> 31020 <bitOffset>2</bitOffset> 31021 <bitWidth>1</bitWidth> 31022 <access>read-write</access> 31023 </field> 31024 <field> 31025 <name>SOFM</name> 31026 <description>Start of frame mask</description> 31027 <bitOffset>3</bitOffset> 31028 <bitWidth>1</bitWidth> 31029 <access>read-write</access> 31030 </field> 31031 <field> 31032 <name>RXFLVLM</name> 31033 <description>Receive FIFO nonempty mask</description> 31034 <bitOffset>4</bitOffset> 31035 <bitWidth>1</bitWidth> 31036 <access>read-write</access> 31037 </field> 31038 <field> 31039 <name>NPTXFEM</name> 31040 <description>Nonperiodic TxFIFO empty 31041 mask</description> 31042 <bitOffset>5</bitOffset> 31043 <bitWidth>1</bitWidth> 31044 <access>read-write</access> 31045 </field> 31046 <field> 31047 <name>GINAKEFFM</name> 31048 <description>Global nonperiodic IN NAK effective 31049 mask</description> 31050 <bitOffset>6</bitOffset> 31051 <bitWidth>1</bitWidth> 31052 <access>read-write</access> 31053 </field> 31054 <field> 31055 <name>GONAKEFFM</name> 31056 <description>Global OUT NAK effective 31057 mask</description> 31058 <bitOffset>7</bitOffset> 31059 <bitWidth>1</bitWidth> 31060 <access>read-write</access> 31061 </field> 31062 <field> 31063 <name>ESUSPM</name> 31064 <description>Early suspend mask</description> 31065 <bitOffset>10</bitOffset> 31066 <bitWidth>1</bitWidth> 31067 <access>read-write</access> 31068 </field> 31069 <field> 31070 <name>USBSUSPM</name> 31071 <description>USB suspend mask</description> 31072 <bitOffset>11</bitOffset> 31073 <bitWidth>1</bitWidth> 31074 <access>read-write</access> 31075 </field> 31076 <field> 31077 <name>USBRST</name> 31078 <description>USB reset mask</description> 31079 <bitOffset>12</bitOffset> 31080 <bitWidth>1</bitWidth> 31081 <access>read-write</access> 31082 </field> 31083 <field> 31084 <name>ENUMDNEM</name> 31085 <description>Enumeration done mask</description> 31086 <bitOffset>13</bitOffset> 31087 <bitWidth>1</bitWidth> 31088 <access>read-write</access> 31089 </field> 31090 <field> 31091 <name>ISOODRPM</name> 31092 <description>Isochronous OUT packet dropped interrupt 31093 mask</description> 31094 <bitOffset>14</bitOffset> 31095 <bitWidth>1</bitWidth> 31096 <access>read-write</access> 31097 </field> 31098 <field> 31099 <name>EOPFM</name> 31100 <description>End of periodic frame interrupt 31101 mask</description> 31102 <bitOffset>15</bitOffset> 31103 <bitWidth>1</bitWidth> 31104 <access>read-write</access> 31105 </field> 31106 <field> 31107 <name>EPMISM</name> 31108 <description>Endpoint mismatch interrupt 31109 mask</description> 31110 <bitOffset>17</bitOffset> 31111 <bitWidth>1</bitWidth> 31112 <access>read-write</access> 31113 </field> 31114 <field> 31115 <name>IEPINT</name> 31116 <description>IN endpoints interrupt 31117 mask</description> 31118 <bitOffset>18</bitOffset> 31119 <bitWidth>1</bitWidth> 31120 <access>read-write</access> 31121 </field> 31122 <field> 31123 <name>OEPINT</name> 31124 <description>OUT endpoints interrupt 31125 mask</description> 31126 <bitOffset>19</bitOffset> 31127 <bitWidth>1</bitWidth> 31128 <access>read-write</access> 31129 </field> 31130 <field> 31131 <name>IISOIXFRM</name> 31132 <description>Incomplete isochronous IN transfer 31133 mask</description> 31134 <bitOffset>20</bitOffset> 31135 <bitWidth>1</bitWidth> 31136 <access>read-write</access> 31137 </field> 31138 <field> 31139 <name>PXFRM_IISOOXFRM</name> 31140 <description>Incomplete periodic transfer 31141 mask</description> 31142 <bitOffset>21</bitOffset> 31143 <bitWidth>1</bitWidth> 31144 <access>read-write</access> 31145 </field> 31146 <field> 31147 <name>FSUSPM</name> 31148 <description>Data fetch suspended mask</description> 31149 <bitOffset>22</bitOffset> 31150 <bitWidth>1</bitWidth> 31151 <access>read-write</access> 31152 </field> 31153 <field> 31154 <name>PRTIM</name> 31155 <description>Host port interrupt mask</description> 31156 <bitOffset>24</bitOffset> 31157 <bitWidth>1</bitWidth> 31158 <access>read-only</access> 31159 </field> 31160 <field> 31161 <name>HCIM</name> 31162 <description>Host channels interrupt 31163 mask</description> 31164 <bitOffset>25</bitOffset> 31165 <bitWidth>1</bitWidth> 31166 <access>read-write</access> 31167 </field> 31168 <field> 31169 <name>PTXFEM</name> 31170 <description>Periodic TxFIFO empty mask</description> 31171 <bitOffset>26</bitOffset> 31172 <bitWidth>1</bitWidth> 31173 <access>read-write</access> 31174 </field> 31175 <field> 31176 <name>CIDSCHGM</name> 31177 <description>Connector ID status change 31178 mask</description> 31179 <bitOffset>28</bitOffset> 31180 <bitWidth>1</bitWidth> 31181 <access>read-write</access> 31182 </field> 31183 <field> 31184 <name>DISCINT</name> 31185 <description>Disconnect detected interrupt 31186 mask</description> 31187 <bitOffset>29</bitOffset> 31188 <bitWidth>1</bitWidth> 31189 <access>read-write</access> 31190 </field> 31191 <field> 31192 <name>SRQIM</name> 31193 <description>Session request/new session detected 31194 interrupt mask</description> 31195 <bitOffset>30</bitOffset> 31196 <bitWidth>1</bitWidth> 31197 <access>read-write</access> 31198 </field> 31199 <field> 31200 <name>WUIM</name> 31201 <description>Resume/remote wakeup detected interrupt 31202 mask</description> 31203 <bitOffset>31</bitOffset> 31204 <bitWidth>1</bitWidth> 31205 <access>read-write</access> 31206 </field> 31207 </fields> 31208 </register> 31209 <register> 31210 <name>GRXSTSR_Host</name> 31211 <displayName>GRXSTSR_Host</displayName> 31212 <description>OTG_HS Receive status debug read register 31213 (host mode)</description> 31214 <addressOffset>0x1C</addressOffset> 31215 <size>32</size> 31216 <access>read-only</access> 31217 <resetValue>0x0</resetValue> 31218 <fields> 31219 <field> 31220 <name>CHNUM</name> 31221 <description>Channel number</description> 31222 <bitOffset>0</bitOffset> 31223 <bitWidth>4</bitWidth> 31224 </field> 31225 <field> 31226 <name>BCNT</name> 31227 <description>Byte count</description> 31228 <bitOffset>4</bitOffset> 31229 <bitWidth>11</bitWidth> 31230 </field> 31231 <field> 31232 <name>DPID</name> 31233 <description>Data PID</description> 31234 <bitOffset>15</bitOffset> 31235 <bitWidth>2</bitWidth> 31236 </field> 31237 <field> 31238 <name>PKTSTS</name> 31239 <description>Packet status</description> 31240 <bitOffset>17</bitOffset> 31241 <bitWidth>4</bitWidth> 31242 </field> 31243 </fields> 31244 </register> 31245 <register> 31246 <name>GRXSTSP_Host</name> 31247 <displayName>GRXSTSP_Host</displayName> 31248 <description>OTG_HS status read and pop register (host 31249 mode)</description> 31250 <addressOffset>0x20</addressOffset> 31251 <size>32</size> 31252 <access>read-only</access> 31253 <resetValue>0x0</resetValue> 31254 <fields> 31255 <field> 31256 <name>CHNUM</name> 31257 <description>Channel number</description> 31258 <bitOffset>0</bitOffset> 31259 <bitWidth>4</bitWidth> 31260 </field> 31261 <field> 31262 <name>BCNT</name> 31263 <description>Byte count</description> 31264 <bitOffset>4</bitOffset> 31265 <bitWidth>11</bitWidth> 31266 </field> 31267 <field> 31268 <name>DPID</name> 31269 <description>Data PID</description> 31270 <bitOffset>15</bitOffset> 31271 <bitWidth>2</bitWidth> 31272 </field> 31273 <field> 31274 <name>PKTSTS</name> 31275 <description>Packet status</description> 31276 <bitOffset>17</bitOffset> 31277 <bitWidth>4</bitWidth> 31278 </field> 31279 </fields> 31280 </register> 31281 <register> 31282 <name>GRXFSIZ</name> 31283 <displayName>GRXFSIZ</displayName> 31284 <description>OTG_HS Receive FIFO size 31285 register</description> 31286 <addressOffset>0x24</addressOffset> 31287 <size>32</size> 31288 <access>read-write</access> 31289 <resetValue>0x00000200</resetValue> 31290 <fields> 31291 <field> 31292 <name>RXFD</name> 31293 <description>RxFIFO depth</description> 31294 <bitOffset>0</bitOffset> 31295 <bitWidth>16</bitWidth> 31296 </field> 31297 </fields> 31298 </register> 31299 <register> 31300 <name>GNPTXFSIZ</name> 31301 <displayName>GNPTXFSIZ</displayName> 31302 <description>OTG_HS nonperiodic transmit FIFO size 31303 register (host mode)</description> 31304 <addressOffset>0x28</addressOffset> 31305 <size>32</size> 31306 <access>read-write</access> 31307 <resetValue>0x00000200</resetValue> 31308 <fields> 31309 <field> 31310 <name>NPTXFSA</name> 31311 <description>Nonperiodic transmit RAM start 31312 address</description> 31313 <bitOffset>0</bitOffset> 31314 <bitWidth>16</bitWidth> 31315 </field> 31316 <field> 31317 <name>NPTXFD</name> 31318 <description>Nonperiodic TxFIFO depth</description> 31319 <bitOffset>16</bitOffset> 31320 <bitWidth>16</bitWidth> 31321 </field> 31322 </fields> 31323 </register> 31324 <register> 31325 <name>TX0FSIZ</name> 31326 <displayName>TX0FSIZ</displayName> 31327 <description>Endpoint 0 transmit FIFO size (peripheral 31328 mode)</description> 31329 <alternateRegister>GNPTXFSIZ</alternateRegister> 31330 <addressOffset>0x28</addressOffset> 31331 <size>32</size> 31332 <access>read-write</access> 31333 <resetValue>0x00000200</resetValue> 31334 <fields> 31335 <field> 31336 <name>TX0FSA</name> 31337 <description>Endpoint 0 transmit RAM start 31338 address</description> 31339 <bitOffset>0</bitOffset> 31340 <bitWidth>16</bitWidth> 31341 </field> 31342 <field> 31343 <name>TX0FD</name> 31344 <description>Endpoint 0 TxFIFO depth</description> 31345 <bitOffset>16</bitOffset> 31346 <bitWidth>16</bitWidth> 31347 </field> 31348 </fields> 31349 </register> 31350 <register> 31351 <name>GNPTXSTS</name> 31352 <displayName>GNPTXSTS</displayName> 31353 <description>OTG_HS nonperiodic transmit FIFO/queue 31354 status register</description> 31355 <addressOffset>0x2C</addressOffset> 31356 <size>32</size> 31357 <access>read-only</access> 31358 <resetValue>0x00080200</resetValue> 31359 <fields> 31360 <field> 31361 <name>NPTXFSAV</name> 31362 <description>Nonperiodic TxFIFO space 31363 available</description> 31364 <bitOffset>0</bitOffset> 31365 <bitWidth>16</bitWidth> 31366 </field> 31367 <field> 31368 <name>NPTQXSAV</name> 31369 <description>Nonperiodic transmit request queue space 31370 available</description> 31371 <bitOffset>16</bitOffset> 31372 <bitWidth>8</bitWidth> 31373 </field> 31374 <field> 31375 <name>NPTXQTOP</name> 31376 <description>Top of the nonperiodic transmit request 31377 queue</description> 31378 <bitOffset>24</bitOffset> 31379 <bitWidth>7</bitWidth> 31380 </field> 31381 </fields> 31382 </register> 31383 <register> 31384 <name>GCCFG</name> 31385 <displayName>GCCFG</displayName> 31386 <description>OTG_HS general core configuration 31387 register</description> 31388 <addressOffset>0x38</addressOffset> 31389 <size>32</size> 31390 <access>read-write</access> 31391 <resetValue>0x0</resetValue> 31392 <fields> 31393 <field> 31394 <name>PWRDWN</name> 31395 <description>Power down</description> 31396 <bitOffset>16</bitOffset> 31397 <bitWidth>1</bitWidth> 31398 </field> 31399 <field> 31400 <name>I2CPADEN</name> 31401 <description>Enable I2C bus connection for the 31402 external I2C PHY interface</description> 31403 <bitOffset>17</bitOffset> 31404 <bitWidth>1</bitWidth> 31405 </field> 31406 <field> 31407 <name>VBUSASEN</name> 31408 <description>Enable the VBUS sensing 31409 device</description> 31410 <bitOffset>18</bitOffset> 31411 <bitWidth>1</bitWidth> 31412 </field> 31413 <field> 31414 <name>VBUSBSEN</name> 31415 <description>Enable the VBUS sensing 31416 device</description> 31417 <bitOffset>19</bitOffset> 31418 <bitWidth>1</bitWidth> 31419 </field> 31420 <field> 31421 <name>SOFOUTEN</name> 31422 <description>SOF output enable</description> 31423 <bitOffset>20</bitOffset> 31424 <bitWidth>1</bitWidth> 31425 </field> 31426 <field> 31427 <name>NOVBUSSENS</name> 31428 <description>VBUS sensing disable 31429 option</description> 31430 <bitOffset>21</bitOffset> 31431 <bitWidth>1</bitWidth> 31432 </field> 31433 </fields> 31434 </register> 31435 <register> 31436 <name>CID</name> 31437 <displayName>CID</displayName> 31438 <description>OTG_HS core ID register</description> 31439 <addressOffset>0x3C</addressOffset> 31440 <size>32</size> 31441 <access>read-write</access> 31442 <resetValue>0x00001200</resetValue> 31443 <fields> 31444 <field> 31445 <name>PRODUCT_ID</name> 31446 <description>Product ID field</description> 31447 <bitOffset>0</bitOffset> 31448 <bitWidth>32</bitWidth> 31449 </field> 31450 </fields> 31451 </register> 31452 <register> 31453 <name>HPTXFSIZ</name> 31454 <displayName>HPTXFSIZ</displayName> 31455 <description>OTG_HS Host periodic transmit FIFO size 31456 register</description> 31457 <addressOffset>0x100</addressOffset> 31458 <size>32</size> 31459 <access>read-write</access> 31460 <resetValue>0x02000600</resetValue> 31461 <fields> 31462 <field> 31463 <name>PTXSA</name> 31464 <description>Host periodic TxFIFO start 31465 address</description> 31466 <bitOffset>0</bitOffset> 31467 <bitWidth>16</bitWidth> 31468 </field> 31469 <field> 31470 <name>PTXFD</name> 31471 <description>Host periodic TxFIFO depth</description> 31472 <bitOffset>16</bitOffset> 31473 <bitWidth>16</bitWidth> 31474 </field> 31475 </fields> 31476 </register> 31477 <register> 31478 <dim>5</dim><dimIncrement>0x4</dimIncrement><dimIndex>1,2,3,4,5</dimIndex><name>DIEPTXF%s</name> 31479 <displayName>DIEPTXF1</displayName> 31480 <description>OTG_HS device IN endpoint transmit FIFO size 31481 register</description> 31482 <addressOffset>0x104</addressOffset> 31483 <size>32</size> 31484 <access>read-write</access> 31485 <resetValue>0x02000400</resetValue> 31486 <fields> 31487 <field> 31488 <name>INEPTXSA</name> 31489 <description>IN endpoint FIFOx transmit RAM start 31490 address</description> 31491 <bitOffset>0</bitOffset> 31492 <bitWidth>16</bitWidth> 31493 </field> 31494 <field> 31495 <name>INEPTXFD</name> 31496 <description>IN endpoint TxFIFO depth</description> 31497 <bitOffset>16</bitOffset> 31498 <bitWidth>16</bitWidth> 31499 </field> 31500 </fields> 31501 </register> 31502 <register> 31503 <name>GRXSTSR_Peripheral</name> 31504 <displayName>GRXSTSR_Peripheral</displayName> 31505 <description>OTG_HS Receive status debug read register 31506 (peripheral mode mode)</description> 31507 <alternateRegister>OTG_HS_GRXSTSR_Host</alternateRegister> 31508 <addressOffset>0x1C</addressOffset> 31509 <size>32</size> 31510 <access>read-only</access> 31511 <resetValue>0x0</resetValue> 31512 <fields> 31513 <field> 31514 <name>EPNUM</name> 31515 <description>Endpoint number</description> 31516 <bitOffset>0</bitOffset> 31517 <bitWidth>4</bitWidth> 31518 </field> 31519 <field> 31520 <name>BCNT</name> 31521 <description>Byte count</description> 31522 <bitOffset>4</bitOffset> 31523 <bitWidth>11</bitWidth> 31524 </field> 31525 <field> 31526 <name>DPID</name> 31527 <description>Data PID</description> 31528 <bitOffset>15</bitOffset> 31529 <bitWidth>2</bitWidth> 31530 </field> 31531 <field> 31532 <name>PKTSTS</name> 31533 <description>Packet status</description> 31534 <bitOffset>17</bitOffset> 31535 <bitWidth>4</bitWidth> 31536 </field> 31537 <field> 31538 <name>FRMNUM</name> 31539 <description>Frame number</description> 31540 <bitOffset>21</bitOffset> 31541 <bitWidth>4</bitWidth> 31542 </field> 31543 </fields> 31544 </register> 31545 <register> 31546 <name>GRXSTSP_Peripheral</name> 31547 <displayName>GRXSTSP_Peripheral</displayName> 31548 <description>OTG_HS status read and pop register 31549 (peripheral mode)</description> 31550 <alternateRegister>OTG_HS_GRXSTSP_Host</alternateRegister> 31551 <addressOffset>0x20</addressOffset> 31552 <size>32</size> 31553 <access>read-only</access> 31554 <resetValue>0x0</resetValue> 31555 <fields> 31556 <field> 31557 <name>EPNUM</name> 31558 <description>Endpoint number</description> 31559 <bitOffset>0</bitOffset> 31560 <bitWidth>4</bitWidth> 31561 </field> 31562 <field> 31563 <name>BCNT</name> 31564 <description>Byte count</description> 31565 <bitOffset>4</bitOffset> 31566 <bitWidth>11</bitWidth> 31567 </field> 31568 <field> 31569 <name>DPID</name> 31570 <description>Data PID</description> 31571 <bitOffset>15</bitOffset> 31572 <bitWidth>2</bitWidth> 31573 </field> 31574 <field> 31575 <name>PKTSTS</name> 31576 <description>Packet status</description> 31577 <bitOffset>17</bitOffset> 31578 <bitWidth>4</bitWidth> 31579 </field> 31580 <field> 31581 <name>FRMNUM</name> 31582 <description>Frame number</description> 31583 <bitOffset>21</bitOffset> 31584 <bitWidth>4</bitWidth> 31585 </field> 31586 </fields> 31587 </register> 31588 </registers> 31589 </peripheral> 31590 <peripheral> 31591 <name>OTG_HS_HOST</name> 31592 <description>USB on the go high speed</description> 31593 <groupName>USB_OTG_HS</groupName> 31594 <baseAddress>0x40040400</baseAddress> 31595 <addressBlock> 31596 <offset>0x0</offset> 31597 <size>0x400</size> 31598 <usage>registers</usage> 31599 </addressBlock> 31600 <registers> 31601 <register> 31602 <name>HCFG</name> 31603 <displayName>HCFG</displayName> 31604 <description>OTG_HS host configuration 31605 register</description> 31606 <addressOffset>0x0</addressOffset> 31607 <size>32</size> 31608 <resetValue>0x0</resetValue> 31609 <fields> 31610 <field> 31611 <name>FSLSPCS</name> 31612 <description>FS/LS PHY clock select</description> 31613 <bitOffset>0</bitOffset> 31614 <bitWidth>2</bitWidth> 31615 <access>read-write</access> 31616 </field> 31617 <field> 31618 <name>FSLSS</name> 31619 <description>FS- and LS-only support</description> 31620 <bitOffset>2</bitOffset> 31621 <bitWidth>1</bitWidth> 31622 <access>read-only</access> 31623 </field> 31624 </fields> 31625 </register> 31626 <register> 31627 <name>HFIR</name> 31628 <displayName>HFIR</displayName> 31629 <description>OTG_HS Host frame interval 31630 register</description> 31631 <addressOffset>0x4</addressOffset> 31632 <size>32</size> 31633 <access>read-write</access> 31634 <resetValue>0x0000EA60</resetValue> 31635 <fields> 31636 <field> 31637 <name>FRIVL</name> 31638 <description>Frame interval</description> 31639 <bitOffset>0</bitOffset> 31640 <bitWidth>16</bitWidth> 31641 </field> 31642 </fields> 31643 </register> 31644 <register> 31645 <name>HFNUM</name> 31646 <displayName>HFNUM</displayName> 31647 <description>OTG_HS host frame number/frame time 31648 remaining register</description> 31649 <addressOffset>0x8</addressOffset> 31650 <size>32</size> 31651 <access>read-only</access> 31652 <resetValue>0x00003FFF</resetValue> 31653 <fields> 31654 <field> 31655 <name>FRNUM</name> 31656 <description>Frame number</description> 31657 <bitOffset>0</bitOffset> 31658 <bitWidth>16</bitWidth> 31659 </field> 31660 <field> 31661 <name>FTREM</name> 31662 <description>Frame time remaining</description> 31663 <bitOffset>16</bitOffset> 31664 <bitWidth>16</bitWidth> 31665 </field> 31666 </fields> 31667 </register> 31668 <register> 31669 <name>HPTXSTS</name> 31670 <displayName>HPTXSTS</displayName> 31671 <description>OTG_HS_Host periodic transmit FIFO/queue 31672 status register</description> 31673 <addressOffset>0x10</addressOffset> 31674 <size>32</size> 31675 <resetValue>0x00080100</resetValue> 31676 <fields> 31677 <field> 31678 <name>PTXFSAVL</name> 31679 <description>Periodic transmit data FIFO space 31680 available</description> 31681 <bitOffset>0</bitOffset> 31682 <bitWidth>16</bitWidth> 31683 <access>read-write</access> 31684 </field> 31685 <field> 31686 <name>PTXQSAV</name> 31687 <description>Periodic transmit request queue space 31688 available</description> 31689 <bitOffset>16</bitOffset> 31690 <bitWidth>8</bitWidth> 31691 <access>read-only</access> 31692 </field> 31693 <field> 31694 <name>PTXQTOP</name> 31695 <description>Top of the periodic transmit request 31696 queue</description> 31697 <bitOffset>24</bitOffset> 31698 <bitWidth>8</bitWidth> 31699 <access>read-only</access> 31700 </field> 31701 </fields> 31702 </register> 31703 <register> 31704 <name>HAINT</name> 31705 <displayName>HAINT</displayName> 31706 <description>OTG_HS Host all channels interrupt 31707 register</description> 31708 <addressOffset>0x14</addressOffset> 31709 <size>32</size> 31710 <access>read-only</access> 31711 <resetValue>0x0</resetValue> 31712 <fields> 31713 <field> 31714 <name>HAINT</name> 31715 <description>Channel interrupts</description> 31716 <bitOffset>0</bitOffset> 31717 <bitWidth>16</bitWidth> 31718 </field> 31719 </fields> 31720 </register> 31721 <register> 31722 <name>HAINTMSK</name> 31723 <displayName>HAINTMSK</displayName> 31724 <description>OTG_HS host all channels interrupt mask 31725 register</description> 31726 <addressOffset>0x18</addressOffset> 31727 <size>32</size> 31728 <access>read-write</access> 31729 <resetValue>0x0</resetValue> 31730 <fields> 31731 <field> 31732 <name>HAINTM</name> 31733 <description>Channel interrupt mask</description> 31734 <bitOffset>0</bitOffset> 31735 <bitWidth>16</bitWidth> 31736 </field> 31737 </fields> 31738 </register> 31739 <register> 31740 <name>HPRT</name> 31741 <displayName>HPRT</displayName> 31742 <description>OTG_HS host port control and status 31743 register</description> 31744 <addressOffset>0x40</addressOffset> 31745 <size>32</size> 31746 <resetValue>0x0</resetValue> 31747 <fields> 31748 <field> 31749 <name>PCSTS</name> 31750 <description>Port connect status</description> 31751 <bitOffset>0</bitOffset> 31752 <bitWidth>1</bitWidth> 31753 <access>read-only</access> 31754 </field> 31755 <field> 31756 <name>PCDET</name> 31757 <description>Port connect detected</description> 31758 <bitOffset>1</bitOffset> 31759 <bitWidth>1</bitWidth> 31760 <access>read-write</access> 31761 </field> 31762 <field> 31763 <name>PENA</name> 31764 <description>Port enable</description> 31765 <bitOffset>2</bitOffset> 31766 <bitWidth>1</bitWidth> 31767 <access>read-write</access> 31768 </field> 31769 <field> 31770 <name>PENCHNG</name> 31771 <description>Port enable/disable change</description> 31772 <bitOffset>3</bitOffset> 31773 <bitWidth>1</bitWidth> 31774 <access>read-write</access> 31775 </field> 31776 <field> 31777 <name>POCA</name> 31778 <description>Port overcurrent active</description> 31779 <bitOffset>4</bitOffset> 31780 <bitWidth>1</bitWidth> 31781 <access>read-only</access> 31782 </field> 31783 <field> 31784 <name>POCCHNG</name> 31785 <description>Port overcurrent change</description> 31786 <bitOffset>5</bitOffset> 31787 <bitWidth>1</bitWidth> 31788 <access>read-write</access> 31789 </field> 31790 <field> 31791 <name>PRES</name> 31792 <description>Port resume</description> 31793 <bitOffset>6</bitOffset> 31794 <bitWidth>1</bitWidth> 31795 <access>read-write</access> 31796 </field> 31797 <field> 31798 <name>PSUSP</name> 31799 <description>Port suspend</description> 31800 <bitOffset>7</bitOffset> 31801 <bitWidth>1</bitWidth> 31802 <access>read-write</access> 31803 </field> 31804 <field> 31805 <name>PRST</name> 31806 <description>Port reset</description> 31807 <bitOffset>8</bitOffset> 31808 <bitWidth>1</bitWidth> 31809 <access>read-write</access> 31810 </field> 31811 <field> 31812 <name>PLSTS</name> 31813 <description>Port line status</description> 31814 <bitOffset>10</bitOffset> 31815 <bitWidth>2</bitWidth> 31816 <access>read-only</access> 31817 </field> 31818 <field> 31819 <name>PPWR</name> 31820 <description>Port power</description> 31821 <bitOffset>12</bitOffset> 31822 <bitWidth>1</bitWidth> 31823 <access>read-write</access> 31824 </field> 31825 <field> 31826 <name>PTCTL</name> 31827 <description>Port test control</description> 31828 <bitOffset>13</bitOffset> 31829 <bitWidth>4</bitWidth> 31830 <access>read-write</access> 31831 </field> 31832 <field> 31833 <name>PSPD</name> 31834 <description>Port speed</description> 31835 <bitOffset>17</bitOffset> 31836 <bitWidth>2</bitWidth> 31837 <access>read-only</access> 31838 </field> 31839 </fields> 31840 </register> 31841 <register> 31842 <name>HCCHAR0</name> 31843 <displayName>HCCHAR0</displayName> 31844 <description>OTG_HS host channel-0 characteristics 31845 register</description> 31846 <addressOffset>0x100</addressOffset> 31847 <size>32</size> 31848 <access>read-write</access> 31849 <resetValue>0x0</resetValue> 31850 <fields> 31851 <field> 31852 <name>MPSIZ</name> 31853 <description>Maximum packet size</description> 31854 <bitOffset>0</bitOffset> 31855 <bitWidth>11</bitWidth> 31856 </field> 31857 <field> 31858 <name>EPNUM</name> 31859 <description>Endpoint number</description> 31860 <bitOffset>11</bitOffset> 31861 <bitWidth>4</bitWidth> 31862 </field> 31863 <field> 31864 <name>EPDIR</name> 31865 <description>Endpoint direction</description> 31866 <bitOffset>15</bitOffset> 31867 <bitWidth>1</bitWidth> 31868 </field> 31869 <field> 31870 <name>LSDEV</name> 31871 <description>Low-speed device</description> 31872 <bitOffset>17</bitOffset> 31873 <bitWidth>1</bitWidth> 31874 </field> 31875 <field> 31876 <name>EPTYP</name> 31877 <description>Endpoint type</description> 31878 <bitOffset>18</bitOffset> 31879 <bitWidth>2</bitWidth> 31880 </field> 31881 <field> 31882 <name>MC</name> 31883 <description>Multi Count (MC) / Error Count 31884 (EC)</description> 31885 <bitOffset>20</bitOffset> 31886 <bitWidth>2</bitWidth> 31887 </field> 31888 <field> 31889 <name>DAD</name> 31890 <description>Device address</description> 31891 <bitOffset>22</bitOffset> 31892 <bitWidth>7</bitWidth> 31893 </field> 31894 <field> 31895 <name>ODDFRM</name> 31896 <description>Odd frame</description> 31897 <bitOffset>29</bitOffset> 31898 <bitWidth>1</bitWidth> 31899 </field> 31900 <field> 31901 <name>CHDIS</name> 31902 <description>Channel disable</description> 31903 <bitOffset>30</bitOffset> 31904 <bitWidth>1</bitWidth> 31905 </field> 31906 <field> 31907 <name>CHENA</name> 31908 <description>Channel enable</description> 31909 <bitOffset>31</bitOffset> 31910 <bitWidth>1</bitWidth> 31911 </field> 31912 </fields> 31913 </register> 31914 <register> 31915 <name>HCCHAR1</name> 31916 <displayName>HCCHAR1</displayName> 31917 <description>OTG_HS host channel-1 characteristics 31918 register</description> 31919 <addressOffset>0x120</addressOffset> 31920 <size>32</size> 31921 <access>read-write</access> 31922 <resetValue>0x0</resetValue> 31923 <fields> 31924 <field> 31925 <name>MPSIZ</name> 31926 <description>Maximum packet size</description> 31927 <bitOffset>0</bitOffset> 31928 <bitWidth>11</bitWidth> 31929 </field> 31930 <field> 31931 <name>EPNUM</name> 31932 <description>Endpoint number</description> 31933 <bitOffset>11</bitOffset> 31934 <bitWidth>4</bitWidth> 31935 </field> 31936 <field> 31937 <name>EPDIR</name> 31938 <description>Endpoint direction</description> 31939 <bitOffset>15</bitOffset> 31940 <bitWidth>1</bitWidth> 31941 </field> 31942 <field> 31943 <name>LSDEV</name> 31944 <description>Low-speed device</description> 31945 <bitOffset>17</bitOffset> 31946 <bitWidth>1</bitWidth> 31947 </field> 31948 <field> 31949 <name>EPTYP</name> 31950 <description>Endpoint type</description> 31951 <bitOffset>18</bitOffset> 31952 <bitWidth>2</bitWidth> 31953 </field> 31954 <field> 31955 <name>MC</name> 31956 <description>Multi Count (MC) / Error Count 31957 (EC)</description> 31958 <bitOffset>20</bitOffset> 31959 <bitWidth>2</bitWidth> 31960 </field> 31961 <field> 31962 <name>DAD</name> 31963 <description>Device address</description> 31964 <bitOffset>22</bitOffset> 31965 <bitWidth>7</bitWidth> 31966 </field> 31967 <field> 31968 <name>ODDFRM</name> 31969 <description>Odd frame</description> 31970 <bitOffset>29</bitOffset> 31971 <bitWidth>1</bitWidth> 31972 </field> 31973 <field> 31974 <name>CHDIS</name> 31975 <description>Channel disable</description> 31976 <bitOffset>30</bitOffset> 31977 <bitWidth>1</bitWidth> 31978 </field> 31979 <field> 31980 <name>CHENA</name> 31981 <description>Channel enable</description> 31982 <bitOffset>31</bitOffset> 31983 <bitWidth>1</bitWidth> 31984 </field> 31985 </fields> 31986 </register> 31987 <register> 31988 <name>HCCHAR2</name> 31989 <displayName>HCCHAR2</displayName> 31990 <description>OTG_HS host channel-2 characteristics 31991 register</description> 31992 <addressOffset>0x140</addressOffset> 31993 <size>32</size> 31994 <access>read-write</access> 31995 <resetValue>0x0</resetValue> 31996 <fields> 31997 <field> 31998 <name>MPSIZ</name> 31999 <description>Maximum packet size</description> 32000 <bitOffset>0</bitOffset> 32001 <bitWidth>11</bitWidth> 32002 </field> 32003 <field> 32004 <name>EPNUM</name> 32005 <description>Endpoint number</description> 32006 <bitOffset>11</bitOffset> 32007 <bitWidth>4</bitWidth> 32008 </field> 32009 <field> 32010 <name>EPDIR</name> 32011 <description>Endpoint direction</description> 32012 <bitOffset>15</bitOffset> 32013 <bitWidth>1</bitWidth> 32014 </field> 32015 <field> 32016 <name>LSDEV</name> 32017 <description>Low-speed device</description> 32018 <bitOffset>17</bitOffset> 32019 <bitWidth>1</bitWidth> 32020 </field> 32021 <field> 32022 <name>EPTYP</name> 32023 <description>Endpoint type</description> 32024 <bitOffset>18</bitOffset> 32025 <bitWidth>2</bitWidth> 32026 </field> 32027 <field> 32028 <name>MC</name> 32029 <description>Multi Count (MC) / Error Count 32030 (EC)</description> 32031 <bitOffset>20</bitOffset> 32032 <bitWidth>2</bitWidth> 32033 </field> 32034 <field> 32035 <name>DAD</name> 32036 <description>Device address</description> 32037 <bitOffset>22</bitOffset> 32038 <bitWidth>7</bitWidth> 32039 </field> 32040 <field> 32041 <name>ODDFRM</name> 32042 <description>Odd frame</description> 32043 <bitOffset>29</bitOffset> 32044 <bitWidth>1</bitWidth> 32045 </field> 32046 <field> 32047 <name>CHDIS</name> 32048 <description>Channel disable</description> 32049 <bitOffset>30</bitOffset> 32050 <bitWidth>1</bitWidth> 32051 </field> 32052 <field> 32053 <name>CHENA</name> 32054 <description>Channel enable</description> 32055 <bitOffset>31</bitOffset> 32056 <bitWidth>1</bitWidth> 32057 </field> 32058 </fields> 32059 </register> 32060 <register> 32061 <name>HCCHAR3</name> 32062 <displayName>HCCHAR3</displayName> 32063 <description>OTG_HS host channel-3 characteristics 32064 register</description> 32065 <addressOffset>0x160</addressOffset> 32066 <size>32</size> 32067 <access>read-write</access> 32068 <resetValue>0x0</resetValue> 32069 <fields> 32070 <field> 32071 <name>MPSIZ</name> 32072 <description>Maximum packet size</description> 32073 <bitOffset>0</bitOffset> 32074 <bitWidth>11</bitWidth> 32075 </field> 32076 <field> 32077 <name>EPNUM</name> 32078 <description>Endpoint number</description> 32079 <bitOffset>11</bitOffset> 32080 <bitWidth>4</bitWidth> 32081 </field> 32082 <field> 32083 <name>EPDIR</name> 32084 <description>Endpoint direction</description> 32085 <bitOffset>15</bitOffset> 32086 <bitWidth>1</bitWidth> 32087 </field> 32088 <field> 32089 <name>LSDEV</name> 32090 <description>Low-speed device</description> 32091 <bitOffset>17</bitOffset> 32092 <bitWidth>1</bitWidth> 32093 </field> 32094 <field> 32095 <name>EPTYP</name> 32096 <description>Endpoint type</description> 32097 <bitOffset>18</bitOffset> 32098 <bitWidth>2</bitWidth> 32099 </field> 32100 <field> 32101 <name>MC</name> 32102 <description>Multi Count (MC) / Error Count 32103 (EC)</description> 32104 <bitOffset>20</bitOffset> 32105 <bitWidth>2</bitWidth> 32106 </field> 32107 <field> 32108 <name>DAD</name> 32109 <description>Device address</description> 32110 <bitOffset>22</bitOffset> 32111 <bitWidth>7</bitWidth> 32112 </field> 32113 <field> 32114 <name>ODDFRM</name> 32115 <description>Odd frame</description> 32116 <bitOffset>29</bitOffset> 32117 <bitWidth>1</bitWidth> 32118 </field> 32119 <field> 32120 <name>CHDIS</name> 32121 <description>Channel disable</description> 32122 <bitOffset>30</bitOffset> 32123 <bitWidth>1</bitWidth> 32124 </field> 32125 <field> 32126 <name>CHENA</name> 32127 <description>Channel enable</description> 32128 <bitOffset>31</bitOffset> 32129 <bitWidth>1</bitWidth> 32130 </field> 32131 </fields> 32132 </register> 32133 <register> 32134 <name>HCCHAR4</name> 32135 <displayName>HCCHAR4</displayName> 32136 <description>OTG_HS host channel-4 characteristics 32137 register</description> 32138 <addressOffset>0x180</addressOffset> 32139 <size>32</size> 32140 <access>read-write</access> 32141 <resetValue>0x0</resetValue> 32142 <fields> 32143 <field> 32144 <name>MPSIZ</name> 32145 <description>Maximum packet size</description> 32146 <bitOffset>0</bitOffset> 32147 <bitWidth>11</bitWidth> 32148 </field> 32149 <field> 32150 <name>EPNUM</name> 32151 <description>Endpoint number</description> 32152 <bitOffset>11</bitOffset> 32153 <bitWidth>4</bitWidth> 32154 </field> 32155 <field> 32156 <name>EPDIR</name> 32157 <description>Endpoint direction</description> 32158 <bitOffset>15</bitOffset> 32159 <bitWidth>1</bitWidth> 32160 </field> 32161 <field> 32162 <name>LSDEV</name> 32163 <description>Low-speed device</description> 32164 <bitOffset>17</bitOffset> 32165 <bitWidth>1</bitWidth> 32166 </field> 32167 <field> 32168 <name>EPTYP</name> 32169 <description>Endpoint type</description> 32170 <bitOffset>18</bitOffset> 32171 <bitWidth>2</bitWidth> 32172 </field> 32173 <field> 32174 <name>MC</name> 32175 <description>Multi Count (MC) / Error Count 32176 (EC)</description> 32177 <bitOffset>20</bitOffset> 32178 <bitWidth>2</bitWidth> 32179 </field> 32180 <field> 32181 <name>DAD</name> 32182 <description>Device address</description> 32183 <bitOffset>22</bitOffset> 32184 <bitWidth>7</bitWidth> 32185 </field> 32186 <field> 32187 <name>ODDFRM</name> 32188 <description>Odd frame</description> 32189 <bitOffset>29</bitOffset> 32190 <bitWidth>1</bitWidth> 32191 </field> 32192 <field> 32193 <name>CHDIS</name> 32194 <description>Channel disable</description> 32195 <bitOffset>30</bitOffset> 32196 <bitWidth>1</bitWidth> 32197 </field> 32198 <field> 32199 <name>CHENA</name> 32200 <description>Channel enable</description> 32201 <bitOffset>31</bitOffset> 32202 <bitWidth>1</bitWidth> 32203 </field> 32204 </fields> 32205 </register> 32206 <register> 32207 <name>HCCHAR5</name> 32208 <displayName>HCCHAR5</displayName> 32209 <description>OTG_HS host channel-5 characteristics 32210 register</description> 32211 <addressOffset>0x1A0</addressOffset> 32212 <size>32</size> 32213 <access>read-write</access> 32214 <resetValue>0x0</resetValue> 32215 <fields> 32216 <field> 32217 <name>MPSIZ</name> 32218 <description>Maximum packet size</description> 32219 <bitOffset>0</bitOffset> 32220 <bitWidth>11</bitWidth> 32221 </field> 32222 <field> 32223 <name>EPNUM</name> 32224 <description>Endpoint number</description> 32225 <bitOffset>11</bitOffset> 32226 <bitWidth>4</bitWidth> 32227 </field> 32228 <field> 32229 <name>EPDIR</name> 32230 <description>Endpoint direction</description> 32231 <bitOffset>15</bitOffset> 32232 <bitWidth>1</bitWidth> 32233 </field> 32234 <field> 32235 <name>LSDEV</name> 32236 <description>Low-speed device</description> 32237 <bitOffset>17</bitOffset> 32238 <bitWidth>1</bitWidth> 32239 </field> 32240 <field> 32241 <name>EPTYP</name> 32242 <description>Endpoint type</description> 32243 <bitOffset>18</bitOffset> 32244 <bitWidth>2</bitWidth> 32245 </field> 32246 <field> 32247 <name>MC</name> 32248 <description>Multi Count (MC) / Error Count 32249 (EC)</description> 32250 <bitOffset>20</bitOffset> 32251 <bitWidth>2</bitWidth> 32252 </field> 32253 <field> 32254 <name>DAD</name> 32255 <description>Device address</description> 32256 <bitOffset>22</bitOffset> 32257 <bitWidth>7</bitWidth> 32258 </field> 32259 <field> 32260 <name>ODDFRM</name> 32261 <description>Odd frame</description> 32262 <bitOffset>29</bitOffset> 32263 <bitWidth>1</bitWidth> 32264 </field> 32265 <field> 32266 <name>CHDIS</name> 32267 <description>Channel disable</description> 32268 <bitOffset>30</bitOffset> 32269 <bitWidth>1</bitWidth> 32270 </field> 32271 <field> 32272 <name>CHENA</name> 32273 <description>Channel enable</description> 32274 <bitOffset>31</bitOffset> 32275 <bitWidth>1</bitWidth> 32276 </field> 32277 </fields> 32278 </register> 32279 <register> 32280 <name>HCCHAR6</name> 32281 <displayName>HCCHAR6</displayName> 32282 <description>OTG_HS host channel-6 characteristics 32283 register</description> 32284 <addressOffset>0x1C0</addressOffset> 32285 <size>32</size> 32286 <access>read-write</access> 32287 <resetValue>0x0</resetValue> 32288 <fields> 32289 <field> 32290 <name>MPSIZ</name> 32291 <description>Maximum packet size</description> 32292 <bitOffset>0</bitOffset> 32293 <bitWidth>11</bitWidth> 32294 </field> 32295 <field> 32296 <name>EPNUM</name> 32297 <description>Endpoint number</description> 32298 <bitOffset>11</bitOffset> 32299 <bitWidth>4</bitWidth> 32300 </field> 32301 <field> 32302 <name>EPDIR</name> 32303 <description>Endpoint direction</description> 32304 <bitOffset>15</bitOffset> 32305 <bitWidth>1</bitWidth> 32306 </field> 32307 <field> 32308 <name>LSDEV</name> 32309 <description>Low-speed device</description> 32310 <bitOffset>17</bitOffset> 32311 <bitWidth>1</bitWidth> 32312 </field> 32313 <field> 32314 <name>EPTYP</name> 32315 <description>Endpoint type</description> 32316 <bitOffset>18</bitOffset> 32317 <bitWidth>2</bitWidth> 32318 </field> 32319 <field> 32320 <name>MC</name> 32321 <description>Multi Count (MC) / Error Count 32322 (EC)</description> 32323 <bitOffset>20</bitOffset> 32324 <bitWidth>2</bitWidth> 32325 </field> 32326 <field> 32327 <name>DAD</name> 32328 <description>Device address</description> 32329 <bitOffset>22</bitOffset> 32330 <bitWidth>7</bitWidth> 32331 </field> 32332 <field> 32333 <name>ODDFRM</name> 32334 <description>Odd frame</description> 32335 <bitOffset>29</bitOffset> 32336 <bitWidth>1</bitWidth> 32337 </field> 32338 <field> 32339 <name>CHDIS</name> 32340 <description>Channel disable</description> 32341 <bitOffset>30</bitOffset> 32342 <bitWidth>1</bitWidth> 32343 </field> 32344 <field> 32345 <name>CHENA</name> 32346 <description>Channel enable</description> 32347 <bitOffset>31</bitOffset> 32348 <bitWidth>1</bitWidth> 32349 </field> 32350 </fields> 32351 </register> 32352 <register> 32353 <name>HCCHAR7</name> 32354 <displayName>HCCHAR7</displayName> 32355 <description>OTG_HS host channel-7 characteristics 32356 register</description> 32357 <addressOffset>0x1E0</addressOffset> 32358 <size>32</size> 32359 <access>read-write</access> 32360 <resetValue>0x0</resetValue> 32361 <fields> 32362 <field> 32363 <name>MPSIZ</name> 32364 <description>Maximum packet size</description> 32365 <bitOffset>0</bitOffset> 32366 <bitWidth>11</bitWidth> 32367 </field> 32368 <field> 32369 <name>EPNUM</name> 32370 <description>Endpoint number</description> 32371 <bitOffset>11</bitOffset> 32372 <bitWidth>4</bitWidth> 32373 </field> 32374 <field> 32375 <name>EPDIR</name> 32376 <description>Endpoint direction</description> 32377 <bitOffset>15</bitOffset> 32378 <bitWidth>1</bitWidth> 32379 </field> 32380 <field> 32381 <name>LSDEV</name> 32382 <description>Low-speed device</description> 32383 <bitOffset>17</bitOffset> 32384 <bitWidth>1</bitWidth> 32385 </field> 32386 <field> 32387 <name>EPTYP</name> 32388 <description>Endpoint type</description> 32389 <bitOffset>18</bitOffset> 32390 <bitWidth>2</bitWidth> 32391 </field> 32392 <field> 32393 <name>MC</name> 32394 <description>Multi Count (MC) / Error Count 32395 (EC)</description> 32396 <bitOffset>20</bitOffset> 32397 <bitWidth>2</bitWidth> 32398 </field> 32399 <field> 32400 <name>DAD</name> 32401 <description>Device address</description> 32402 <bitOffset>22</bitOffset> 32403 <bitWidth>7</bitWidth> 32404 </field> 32405 <field> 32406 <name>ODDFRM</name> 32407 <description>Odd frame</description> 32408 <bitOffset>29</bitOffset> 32409 <bitWidth>1</bitWidth> 32410 </field> 32411 <field> 32412 <name>CHDIS</name> 32413 <description>Channel disable</description> 32414 <bitOffset>30</bitOffset> 32415 <bitWidth>1</bitWidth> 32416 </field> 32417 <field> 32418 <name>CHENA</name> 32419 <description>Channel enable</description> 32420 <bitOffset>31</bitOffset> 32421 <bitWidth>1</bitWidth> 32422 </field> 32423 </fields> 32424 </register> 32425 <register> 32426 <name>HCCHAR8</name> 32427 <displayName>HCCHAR8</displayName> 32428 <description>OTG_HS host channel-8 characteristics 32429 register</description> 32430 <addressOffset>0x200</addressOffset> 32431 <size>32</size> 32432 <access>read-write</access> 32433 <resetValue>0x0</resetValue> 32434 <fields> 32435 <field> 32436 <name>MPSIZ</name> 32437 <description>Maximum packet size</description> 32438 <bitOffset>0</bitOffset> 32439 <bitWidth>11</bitWidth> 32440 </field> 32441 <field> 32442 <name>EPNUM</name> 32443 <description>Endpoint number</description> 32444 <bitOffset>11</bitOffset> 32445 <bitWidth>4</bitWidth> 32446 </field> 32447 <field> 32448 <name>EPDIR</name> 32449 <description>Endpoint direction</description> 32450 <bitOffset>15</bitOffset> 32451 <bitWidth>1</bitWidth> 32452 </field> 32453 <field> 32454 <name>LSDEV</name> 32455 <description>Low-speed device</description> 32456 <bitOffset>17</bitOffset> 32457 <bitWidth>1</bitWidth> 32458 </field> 32459 <field> 32460 <name>EPTYP</name> 32461 <description>Endpoint type</description> 32462 <bitOffset>18</bitOffset> 32463 <bitWidth>2</bitWidth> 32464 </field> 32465 <field> 32466 <name>MC</name> 32467 <description>Multi Count (MC) / Error Count 32468 (EC)</description> 32469 <bitOffset>20</bitOffset> 32470 <bitWidth>2</bitWidth> 32471 </field> 32472 <field> 32473 <name>DAD</name> 32474 <description>Device address</description> 32475 <bitOffset>22</bitOffset> 32476 <bitWidth>7</bitWidth> 32477 </field> 32478 <field> 32479 <name>ODDFRM</name> 32480 <description>Odd frame</description> 32481 <bitOffset>29</bitOffset> 32482 <bitWidth>1</bitWidth> 32483 </field> 32484 <field> 32485 <name>CHDIS</name> 32486 <description>Channel disable</description> 32487 <bitOffset>30</bitOffset> 32488 <bitWidth>1</bitWidth> 32489 </field> 32490 <field> 32491 <name>CHENA</name> 32492 <description>Channel enable</description> 32493 <bitOffset>31</bitOffset> 32494 <bitWidth>1</bitWidth> 32495 </field> 32496 </fields> 32497 </register> 32498 <register> 32499 <name>HCCHAR9</name> 32500 <displayName>HCCHAR9</displayName> 32501 <description>OTG_HS host channel-9 characteristics 32502 register</description> 32503 <addressOffset>0x220</addressOffset> 32504 <size>32</size> 32505 <access>read-write</access> 32506 <resetValue>0x0</resetValue> 32507 <fields> 32508 <field> 32509 <name>MPSIZ</name> 32510 <description>Maximum packet size</description> 32511 <bitOffset>0</bitOffset> 32512 <bitWidth>11</bitWidth> 32513 </field> 32514 <field> 32515 <name>EPNUM</name> 32516 <description>Endpoint number</description> 32517 <bitOffset>11</bitOffset> 32518 <bitWidth>4</bitWidth> 32519 </field> 32520 <field> 32521 <name>EPDIR</name> 32522 <description>Endpoint direction</description> 32523 <bitOffset>15</bitOffset> 32524 <bitWidth>1</bitWidth> 32525 </field> 32526 <field> 32527 <name>LSDEV</name> 32528 <description>Low-speed device</description> 32529 <bitOffset>17</bitOffset> 32530 <bitWidth>1</bitWidth> 32531 </field> 32532 <field> 32533 <name>EPTYP</name> 32534 <description>Endpoint type</description> 32535 <bitOffset>18</bitOffset> 32536 <bitWidth>2</bitWidth> 32537 </field> 32538 <field> 32539 <name>MC</name> 32540 <description>Multi Count (MC) / Error Count 32541 (EC)</description> 32542 <bitOffset>20</bitOffset> 32543 <bitWidth>2</bitWidth> 32544 </field> 32545 <field> 32546 <name>DAD</name> 32547 <description>Device address</description> 32548 <bitOffset>22</bitOffset> 32549 <bitWidth>7</bitWidth> 32550 </field> 32551 <field> 32552 <name>ODDFRM</name> 32553 <description>Odd frame</description> 32554 <bitOffset>29</bitOffset> 32555 <bitWidth>1</bitWidth> 32556 </field> 32557 <field> 32558 <name>CHDIS</name> 32559 <description>Channel disable</description> 32560 <bitOffset>30</bitOffset> 32561 <bitWidth>1</bitWidth> 32562 </field> 32563 <field> 32564 <name>CHENA</name> 32565 <description>Channel enable</description> 32566 <bitOffset>31</bitOffset> 32567 <bitWidth>1</bitWidth> 32568 </field> 32569 </fields> 32570 </register> 32571 <register> 32572 <name>HCCHAR10</name> 32573 <displayName>HCCHAR10</displayName> 32574 <description>OTG_HS host channel-10 characteristics 32575 register</description> 32576 <addressOffset>0x240</addressOffset> 32577 <size>32</size> 32578 <access>read-write</access> 32579 <resetValue>0x0</resetValue> 32580 <fields> 32581 <field> 32582 <name>MPSIZ</name> 32583 <description>Maximum packet size</description> 32584 <bitOffset>0</bitOffset> 32585 <bitWidth>11</bitWidth> 32586 </field> 32587 <field> 32588 <name>EPNUM</name> 32589 <description>Endpoint number</description> 32590 <bitOffset>11</bitOffset> 32591 <bitWidth>4</bitWidth> 32592 </field> 32593 <field> 32594 <name>EPDIR</name> 32595 <description>Endpoint direction</description> 32596 <bitOffset>15</bitOffset> 32597 <bitWidth>1</bitWidth> 32598 </field> 32599 <field> 32600 <name>LSDEV</name> 32601 <description>Low-speed device</description> 32602 <bitOffset>17</bitOffset> 32603 <bitWidth>1</bitWidth> 32604 </field> 32605 <field> 32606 <name>EPTYP</name> 32607 <description>Endpoint type</description> 32608 <bitOffset>18</bitOffset> 32609 <bitWidth>2</bitWidth> 32610 </field> 32611 <field> 32612 <name>MC</name> 32613 <description>Multi Count (MC) / Error Count 32614 (EC)</description> 32615 <bitOffset>20</bitOffset> 32616 <bitWidth>2</bitWidth> 32617 </field> 32618 <field> 32619 <name>DAD</name> 32620 <description>Device address</description> 32621 <bitOffset>22</bitOffset> 32622 <bitWidth>7</bitWidth> 32623 </field> 32624 <field> 32625 <name>ODDFRM</name> 32626 <description>Odd frame</description> 32627 <bitOffset>29</bitOffset> 32628 <bitWidth>1</bitWidth> 32629 </field> 32630 <field> 32631 <name>CHDIS</name> 32632 <description>Channel disable</description> 32633 <bitOffset>30</bitOffset> 32634 <bitWidth>1</bitWidth> 32635 </field> 32636 <field> 32637 <name>CHENA</name> 32638 <description>Channel enable</description> 32639 <bitOffset>31</bitOffset> 32640 <bitWidth>1</bitWidth> 32641 </field> 32642 </fields> 32643 </register> 32644 <register> 32645 <name>HCCHAR11</name> 32646 <displayName>HCCHAR11</displayName> 32647 <description>OTG_HS host channel-11 characteristics 32648 register</description> 32649 <addressOffset>0x260</addressOffset> 32650 <size>32</size> 32651 <access>read-write</access> 32652 <resetValue>0x0</resetValue> 32653 <fields> 32654 <field> 32655 <name>MPSIZ</name> 32656 <description>Maximum packet size</description> 32657 <bitOffset>0</bitOffset> 32658 <bitWidth>11</bitWidth> 32659 </field> 32660 <field> 32661 <name>EPNUM</name> 32662 <description>Endpoint number</description> 32663 <bitOffset>11</bitOffset> 32664 <bitWidth>4</bitWidth> 32665 </field> 32666 <field> 32667 <name>EPDIR</name> 32668 <description>Endpoint direction</description> 32669 <bitOffset>15</bitOffset> 32670 <bitWidth>1</bitWidth> 32671 </field> 32672 <field> 32673 <name>LSDEV</name> 32674 <description>Low-speed device</description> 32675 <bitOffset>17</bitOffset> 32676 <bitWidth>1</bitWidth> 32677 </field> 32678 <field> 32679 <name>EPTYP</name> 32680 <description>Endpoint type</description> 32681 <bitOffset>18</bitOffset> 32682 <bitWidth>2</bitWidth> 32683 </field> 32684 <field> 32685 <name>MC</name> 32686 <description>Multi Count (MC) / Error Count 32687 (EC)</description> 32688 <bitOffset>20</bitOffset> 32689 <bitWidth>2</bitWidth> 32690 </field> 32691 <field> 32692 <name>DAD</name> 32693 <description>Device address</description> 32694 <bitOffset>22</bitOffset> 32695 <bitWidth>7</bitWidth> 32696 </field> 32697 <field> 32698 <name>ODDFRM</name> 32699 <description>Odd frame</description> 32700 <bitOffset>29</bitOffset> 32701 <bitWidth>1</bitWidth> 32702 </field> 32703 <field> 32704 <name>CHDIS</name> 32705 <description>Channel disable</description> 32706 <bitOffset>30</bitOffset> 32707 <bitWidth>1</bitWidth> 32708 </field> 32709 <field> 32710 <name>CHENA</name> 32711 <description>Channel enable</description> 32712 <bitOffset>31</bitOffset> 32713 <bitWidth>1</bitWidth> 32714 </field> 32715 </fields> 32716 </register> 32717 <register> 32718 <name>HCSPLT0</name> 32719 <displayName>HCSPLT0</displayName> 32720 <description>OTG_HS host channel-0 split control 32721 register</description> 32722 <addressOffset>0x104</addressOffset> 32723 <size>32</size> 32724 <access>read-write</access> 32725 <resetValue>0x0</resetValue> 32726 <fields> 32727 <field> 32728 <name>PRTADDR</name> 32729 <description>Port address</description> 32730 <bitOffset>0</bitOffset> 32731 <bitWidth>7</bitWidth> 32732 </field> 32733 <field> 32734 <name>HUBADDR</name> 32735 <description>Hub address</description> 32736 <bitOffset>7</bitOffset> 32737 <bitWidth>7</bitWidth> 32738 </field> 32739 <field> 32740 <name>XACTPOS</name> 32741 <description>XACTPOS</description> 32742 <bitOffset>14</bitOffset> 32743 <bitWidth>2</bitWidth> 32744 </field> 32745 <field> 32746 <name>COMPLSPLT</name> 32747 <description>Do complete split</description> 32748 <bitOffset>16</bitOffset> 32749 <bitWidth>1</bitWidth> 32750 </field> 32751 <field> 32752 <name>SPLITEN</name> 32753 <description>Split enable</description> 32754 <bitOffset>31</bitOffset> 32755 <bitWidth>1</bitWidth> 32756 </field> 32757 </fields> 32758 </register> 32759 <register> 32760 <name>HCSPLT1</name> 32761 <displayName>HCSPLT1</displayName> 32762 <description>OTG_HS host channel-1 split control 32763 register</description> 32764 <addressOffset>0x124</addressOffset> 32765 <size>32</size> 32766 <access>read-write</access> 32767 <resetValue>0x0</resetValue> 32768 <fields> 32769 <field> 32770 <name>PRTADDR</name> 32771 <description>Port address</description> 32772 <bitOffset>0</bitOffset> 32773 <bitWidth>7</bitWidth> 32774 </field> 32775 <field> 32776 <name>HUBADDR</name> 32777 <description>Hub address</description> 32778 <bitOffset>7</bitOffset> 32779 <bitWidth>7</bitWidth> 32780 </field> 32781 <field> 32782 <name>XACTPOS</name> 32783 <description>XACTPOS</description> 32784 <bitOffset>14</bitOffset> 32785 <bitWidth>2</bitWidth> 32786 </field> 32787 <field> 32788 <name>COMPLSPLT</name> 32789 <description>Do complete split</description> 32790 <bitOffset>16</bitOffset> 32791 <bitWidth>1</bitWidth> 32792 </field> 32793 <field> 32794 <name>SPLITEN</name> 32795 <description>Split enable</description> 32796 <bitOffset>31</bitOffset> 32797 <bitWidth>1</bitWidth> 32798 </field> 32799 </fields> 32800 </register> 32801 <register> 32802 <name>HCSPLT2</name> 32803 <displayName>HCSPLT2</displayName> 32804 <description>OTG_HS host channel-2 split control 32805 register</description> 32806 <addressOffset>0x144</addressOffset> 32807 <size>32</size> 32808 <access>read-write</access> 32809 <resetValue>0x0</resetValue> 32810 <fields> 32811 <field> 32812 <name>PRTADDR</name> 32813 <description>Port address</description> 32814 <bitOffset>0</bitOffset> 32815 <bitWidth>7</bitWidth> 32816 </field> 32817 <field> 32818 <name>HUBADDR</name> 32819 <description>Hub address</description> 32820 <bitOffset>7</bitOffset> 32821 <bitWidth>7</bitWidth> 32822 </field> 32823 <field> 32824 <name>XACTPOS</name> 32825 <description>XACTPOS</description> 32826 <bitOffset>14</bitOffset> 32827 <bitWidth>2</bitWidth> 32828 </field> 32829 <field> 32830 <name>COMPLSPLT</name> 32831 <description>Do complete split</description> 32832 <bitOffset>16</bitOffset> 32833 <bitWidth>1</bitWidth> 32834 </field> 32835 <field> 32836 <name>SPLITEN</name> 32837 <description>Split enable</description> 32838 <bitOffset>31</bitOffset> 32839 <bitWidth>1</bitWidth> 32840 </field> 32841 </fields> 32842 </register> 32843 <register> 32844 <name>HCSPLT3</name> 32845 <displayName>HCSPLT3</displayName> 32846 <description>OTG_HS host channel-3 split control 32847 register</description> 32848 <addressOffset>0x164</addressOffset> 32849 <size>32</size> 32850 <access>read-write</access> 32851 <resetValue>0x0</resetValue> 32852 <fields> 32853 <field> 32854 <name>PRTADDR</name> 32855 <description>Port address</description> 32856 <bitOffset>0</bitOffset> 32857 <bitWidth>7</bitWidth> 32858 </field> 32859 <field> 32860 <name>HUBADDR</name> 32861 <description>Hub address</description> 32862 <bitOffset>7</bitOffset> 32863 <bitWidth>7</bitWidth> 32864 </field> 32865 <field> 32866 <name>XACTPOS</name> 32867 <description>XACTPOS</description> 32868 <bitOffset>14</bitOffset> 32869 <bitWidth>2</bitWidth> 32870 </field> 32871 <field> 32872 <name>COMPLSPLT</name> 32873 <description>Do complete split</description> 32874 <bitOffset>16</bitOffset> 32875 <bitWidth>1</bitWidth> 32876 </field> 32877 <field> 32878 <name>SPLITEN</name> 32879 <description>Split enable</description> 32880 <bitOffset>31</bitOffset> 32881 <bitWidth>1</bitWidth> 32882 </field> 32883 </fields> 32884 </register> 32885 <register> 32886 <name>HCSPLT4</name> 32887 <displayName>HCSPLT4</displayName> 32888 <description>OTG_HS host channel-4 split control 32889 register</description> 32890 <addressOffset>0x184</addressOffset> 32891 <size>32</size> 32892 <access>read-write</access> 32893 <resetValue>0x0</resetValue> 32894 <fields> 32895 <field> 32896 <name>PRTADDR</name> 32897 <description>Port address</description> 32898 <bitOffset>0</bitOffset> 32899 <bitWidth>7</bitWidth> 32900 </field> 32901 <field> 32902 <name>HUBADDR</name> 32903 <description>Hub address</description> 32904 <bitOffset>7</bitOffset> 32905 <bitWidth>7</bitWidth> 32906 </field> 32907 <field> 32908 <name>XACTPOS</name> 32909 <description>XACTPOS</description> 32910 <bitOffset>14</bitOffset> 32911 <bitWidth>2</bitWidth> 32912 </field> 32913 <field> 32914 <name>COMPLSPLT</name> 32915 <description>Do complete split</description> 32916 <bitOffset>16</bitOffset> 32917 <bitWidth>1</bitWidth> 32918 </field> 32919 <field> 32920 <name>SPLITEN</name> 32921 <description>Split enable</description> 32922 <bitOffset>31</bitOffset> 32923 <bitWidth>1</bitWidth> 32924 </field> 32925 </fields> 32926 </register> 32927 <register> 32928 <name>HCSPLT5</name> 32929 <displayName>HCSPLT5</displayName> 32930 <description>OTG_HS host channel-5 split control 32931 register</description> 32932 <addressOffset>0x1A4</addressOffset> 32933 <size>32</size> 32934 <access>read-write</access> 32935 <resetValue>0x0</resetValue> 32936 <fields> 32937 <field> 32938 <name>PRTADDR</name> 32939 <description>Port address</description> 32940 <bitOffset>0</bitOffset> 32941 <bitWidth>7</bitWidth> 32942 </field> 32943 <field> 32944 <name>HUBADDR</name> 32945 <description>Hub address</description> 32946 <bitOffset>7</bitOffset> 32947 <bitWidth>7</bitWidth> 32948 </field> 32949 <field> 32950 <name>XACTPOS</name> 32951 <description>XACTPOS</description> 32952 <bitOffset>14</bitOffset> 32953 <bitWidth>2</bitWidth> 32954 </field> 32955 <field> 32956 <name>COMPLSPLT</name> 32957 <description>Do complete split</description> 32958 <bitOffset>16</bitOffset> 32959 <bitWidth>1</bitWidth> 32960 </field> 32961 <field> 32962 <name>SPLITEN</name> 32963 <description>Split enable</description> 32964 <bitOffset>31</bitOffset> 32965 <bitWidth>1</bitWidth> 32966 </field> 32967 </fields> 32968 </register> 32969 <register> 32970 <name>HCSPLT6</name> 32971 <displayName>HCSPLT6</displayName> 32972 <description>OTG_HS host channel-6 split control 32973 register</description> 32974 <addressOffset>0x1C4</addressOffset> 32975 <size>32</size> 32976 <access>read-write</access> 32977 <resetValue>0x0</resetValue> 32978 <fields> 32979 <field> 32980 <name>PRTADDR</name> 32981 <description>Port address</description> 32982 <bitOffset>0</bitOffset> 32983 <bitWidth>7</bitWidth> 32984 </field> 32985 <field> 32986 <name>HUBADDR</name> 32987 <description>Hub address</description> 32988 <bitOffset>7</bitOffset> 32989 <bitWidth>7</bitWidth> 32990 </field> 32991 <field> 32992 <name>XACTPOS</name> 32993 <description>XACTPOS</description> 32994 <bitOffset>14</bitOffset> 32995 <bitWidth>2</bitWidth> 32996 </field> 32997 <field> 32998 <name>COMPLSPLT</name> 32999 <description>Do complete split</description> 33000 <bitOffset>16</bitOffset> 33001 <bitWidth>1</bitWidth> 33002 </field> 33003 <field> 33004 <name>SPLITEN</name> 33005 <description>Split enable</description> 33006 <bitOffset>31</bitOffset> 33007 <bitWidth>1</bitWidth> 33008 </field> 33009 </fields> 33010 </register> 33011 <register> 33012 <name>HCSPLT7</name> 33013 <displayName>HCSPLT7</displayName> 33014 <description>OTG_HS host channel-7 split control 33015 register</description> 33016 <addressOffset>0x1E4</addressOffset> 33017 <size>32</size> 33018 <access>read-write</access> 33019 <resetValue>0x0</resetValue> 33020 <fields> 33021 <field> 33022 <name>PRTADDR</name> 33023 <description>Port address</description> 33024 <bitOffset>0</bitOffset> 33025 <bitWidth>7</bitWidth> 33026 </field> 33027 <field> 33028 <name>HUBADDR</name> 33029 <description>Hub address</description> 33030 <bitOffset>7</bitOffset> 33031 <bitWidth>7</bitWidth> 33032 </field> 33033 <field> 33034 <name>XACTPOS</name> 33035 <description>XACTPOS</description> 33036 <bitOffset>14</bitOffset> 33037 <bitWidth>2</bitWidth> 33038 </field> 33039 <field> 33040 <name>COMPLSPLT</name> 33041 <description>Do complete split</description> 33042 <bitOffset>16</bitOffset> 33043 <bitWidth>1</bitWidth> 33044 </field> 33045 <field> 33046 <name>SPLITEN</name> 33047 <description>Split enable</description> 33048 <bitOffset>31</bitOffset> 33049 <bitWidth>1</bitWidth> 33050 </field> 33051 </fields> 33052 </register> 33053 <register> 33054 <name>HCSPLT8</name> 33055 <displayName>HCSPLT8</displayName> 33056 <description>OTG_HS host channel-8 split control 33057 register</description> 33058 <addressOffset>0x204</addressOffset> 33059 <size>32</size> 33060 <access>read-write</access> 33061 <resetValue>0x0</resetValue> 33062 <fields> 33063 <field> 33064 <name>PRTADDR</name> 33065 <description>Port address</description> 33066 <bitOffset>0</bitOffset> 33067 <bitWidth>7</bitWidth> 33068 </field> 33069 <field> 33070 <name>HUBADDR</name> 33071 <description>Hub address</description> 33072 <bitOffset>7</bitOffset> 33073 <bitWidth>7</bitWidth> 33074 </field> 33075 <field> 33076 <name>XACTPOS</name> 33077 <description>XACTPOS</description> 33078 <bitOffset>14</bitOffset> 33079 <bitWidth>2</bitWidth> 33080 </field> 33081 <field> 33082 <name>COMPLSPLT</name> 33083 <description>Do complete split</description> 33084 <bitOffset>16</bitOffset> 33085 <bitWidth>1</bitWidth> 33086 </field> 33087 <field> 33088 <name>SPLITEN</name> 33089 <description>Split enable</description> 33090 <bitOffset>31</bitOffset> 33091 <bitWidth>1</bitWidth> 33092 </field> 33093 </fields> 33094 </register> 33095 <register> 33096 <name>HCSPLT9</name> 33097 <displayName>HCSPLT9</displayName> 33098 <description>OTG_HS host channel-9 split control 33099 register</description> 33100 <addressOffset>0x224</addressOffset> 33101 <size>32</size> 33102 <access>read-write</access> 33103 <resetValue>0x0</resetValue> 33104 <fields> 33105 <field> 33106 <name>PRTADDR</name> 33107 <description>Port address</description> 33108 <bitOffset>0</bitOffset> 33109 <bitWidth>7</bitWidth> 33110 </field> 33111 <field> 33112 <name>HUBADDR</name> 33113 <description>Hub address</description> 33114 <bitOffset>7</bitOffset> 33115 <bitWidth>7</bitWidth> 33116 </field> 33117 <field> 33118 <name>XACTPOS</name> 33119 <description>XACTPOS</description> 33120 <bitOffset>14</bitOffset> 33121 <bitWidth>2</bitWidth> 33122 </field> 33123 <field> 33124 <name>COMPLSPLT</name> 33125 <description>Do complete split</description> 33126 <bitOffset>16</bitOffset> 33127 <bitWidth>1</bitWidth> 33128 </field> 33129 <field> 33130 <name>SPLITEN</name> 33131 <description>Split enable</description> 33132 <bitOffset>31</bitOffset> 33133 <bitWidth>1</bitWidth> 33134 </field> 33135 </fields> 33136 </register> 33137 <register> 33138 <name>HCSPLT10</name> 33139 <displayName>HCSPLT10</displayName> 33140 <description>OTG_HS host channel-10 split control 33141 register</description> 33142 <addressOffset>0x244</addressOffset> 33143 <size>32</size> 33144 <access>read-write</access> 33145 <resetValue>0x0</resetValue> 33146 <fields> 33147 <field> 33148 <name>PRTADDR</name> 33149 <description>Port address</description> 33150 <bitOffset>0</bitOffset> 33151 <bitWidth>7</bitWidth> 33152 </field> 33153 <field> 33154 <name>HUBADDR</name> 33155 <description>Hub address</description> 33156 <bitOffset>7</bitOffset> 33157 <bitWidth>7</bitWidth> 33158 </field> 33159 <field> 33160 <name>XACTPOS</name> 33161 <description>XACTPOS</description> 33162 <bitOffset>14</bitOffset> 33163 <bitWidth>2</bitWidth> 33164 </field> 33165 <field> 33166 <name>COMPLSPLT</name> 33167 <description>Do complete split</description> 33168 <bitOffset>16</bitOffset> 33169 <bitWidth>1</bitWidth> 33170 </field> 33171 <field> 33172 <name>SPLITEN</name> 33173 <description>Split enable</description> 33174 <bitOffset>31</bitOffset> 33175 <bitWidth>1</bitWidth> 33176 </field> 33177 </fields> 33178 </register> 33179 <register> 33180 <name>HCSPLT11</name> 33181 <displayName>HCSPLT11</displayName> 33182 <description>OTG_HS host channel-11 split control 33183 register</description> 33184 <addressOffset>0x264</addressOffset> 33185 <size>32</size> 33186 <access>read-write</access> 33187 <resetValue>0x0</resetValue> 33188 <fields> 33189 <field> 33190 <name>PRTADDR</name> 33191 <description>Port address</description> 33192 <bitOffset>0</bitOffset> 33193 <bitWidth>7</bitWidth> 33194 </field> 33195 <field> 33196 <name>HUBADDR</name> 33197 <description>Hub address</description> 33198 <bitOffset>7</bitOffset> 33199 <bitWidth>7</bitWidth> 33200 </field> 33201 <field> 33202 <name>XACTPOS</name> 33203 <description>XACTPOS</description> 33204 <bitOffset>14</bitOffset> 33205 <bitWidth>2</bitWidth> 33206 </field> 33207 <field> 33208 <name>COMPLSPLT</name> 33209 <description>Do complete split</description> 33210 <bitOffset>16</bitOffset> 33211 <bitWidth>1</bitWidth> 33212 </field> 33213 <field> 33214 <name>SPLITEN</name> 33215 <description>Split enable</description> 33216 <bitOffset>31</bitOffset> 33217 <bitWidth>1</bitWidth> 33218 </field> 33219 </fields> 33220 </register> 33221 <register> 33222 <name>HCINT0</name> 33223 <displayName>HCINT0</displayName> 33224 <description>OTG_HS host channel-11 interrupt 33225 register</description> 33226 <addressOffset>0x108</addressOffset> 33227 <size>32</size> 33228 <access>read-write</access> 33229 <resetValue>0x0</resetValue> 33230 <fields> 33231 <field> 33232 <name>XFRC</name> 33233 <description>Transfer completed</description> 33234 <bitOffset>0</bitOffset> 33235 <bitWidth>1</bitWidth> 33236 </field> 33237 <field> 33238 <name>CHH</name> 33239 <description>Channel halted</description> 33240 <bitOffset>1</bitOffset> 33241 <bitWidth>1</bitWidth> 33242 </field> 33243 <field> 33244 <name>AHBERR</name> 33245 <description>AHB error</description> 33246 <bitOffset>2</bitOffset> 33247 <bitWidth>1</bitWidth> 33248 </field> 33249 <field> 33250 <name>STALL</name> 33251 <description>STALL response received 33252 interrupt</description> 33253 <bitOffset>3</bitOffset> 33254 <bitWidth>1</bitWidth> 33255 </field> 33256 <field> 33257 <name>NAK</name> 33258 <description>NAK response received 33259 interrupt</description> 33260 <bitOffset>4</bitOffset> 33261 <bitWidth>1</bitWidth> 33262 </field> 33263 <field> 33264 <name>ACK</name> 33265 <description>ACK response received/transmitted 33266 interrupt</description> 33267 <bitOffset>5</bitOffset> 33268 <bitWidth>1</bitWidth> 33269 </field> 33270 <field> 33271 <name>NYET</name> 33272 <description>Response received 33273 interrupt</description> 33274 <bitOffset>6</bitOffset> 33275 <bitWidth>1</bitWidth> 33276 </field> 33277 <field> 33278 <name>TXERR</name> 33279 <description>Transaction error</description> 33280 <bitOffset>7</bitOffset> 33281 <bitWidth>1</bitWidth> 33282 </field> 33283 <field> 33284 <name>BBERR</name> 33285 <description>Babble error</description> 33286 <bitOffset>8</bitOffset> 33287 <bitWidth>1</bitWidth> 33288 </field> 33289 <field> 33290 <name>FRMOR</name> 33291 <description>Frame overrun</description> 33292 <bitOffset>9</bitOffset> 33293 <bitWidth>1</bitWidth> 33294 </field> 33295 <field> 33296 <name>DTERR</name> 33297 <description>Data toggle error</description> 33298 <bitOffset>10</bitOffset> 33299 <bitWidth>1</bitWidth> 33300 </field> 33301 </fields> 33302 </register> 33303 <register> 33304 <name>HCINT1</name> 33305 <displayName>HCINT1</displayName> 33306 <description>OTG_HS host channel-1 interrupt 33307 register</description> 33308 <addressOffset>0x128</addressOffset> 33309 <size>32</size> 33310 <access>read-write</access> 33311 <resetValue>0x0</resetValue> 33312 <fields> 33313 <field> 33314 <name>XFRC</name> 33315 <description>Transfer completed</description> 33316 <bitOffset>0</bitOffset> 33317 <bitWidth>1</bitWidth> 33318 </field> 33319 <field> 33320 <name>CHH</name> 33321 <description>Channel halted</description> 33322 <bitOffset>1</bitOffset> 33323 <bitWidth>1</bitWidth> 33324 </field> 33325 <field> 33326 <name>AHBERR</name> 33327 <description>AHB error</description> 33328 <bitOffset>2</bitOffset> 33329 <bitWidth>1</bitWidth> 33330 </field> 33331 <field> 33332 <name>STALL</name> 33333 <description>STALL response received 33334 interrupt</description> 33335 <bitOffset>3</bitOffset> 33336 <bitWidth>1</bitWidth> 33337 </field> 33338 <field> 33339 <name>NAK</name> 33340 <description>NAK response received 33341 interrupt</description> 33342 <bitOffset>4</bitOffset> 33343 <bitWidth>1</bitWidth> 33344 </field> 33345 <field> 33346 <name>ACK</name> 33347 <description>ACK response received/transmitted 33348 interrupt</description> 33349 <bitOffset>5</bitOffset> 33350 <bitWidth>1</bitWidth> 33351 </field> 33352 <field> 33353 <name>NYET</name> 33354 <description>Response received 33355 interrupt</description> 33356 <bitOffset>6</bitOffset> 33357 <bitWidth>1</bitWidth> 33358 </field> 33359 <field> 33360 <name>TXERR</name> 33361 <description>Transaction error</description> 33362 <bitOffset>7</bitOffset> 33363 <bitWidth>1</bitWidth> 33364 </field> 33365 <field> 33366 <name>BBERR</name> 33367 <description>Babble error</description> 33368 <bitOffset>8</bitOffset> 33369 <bitWidth>1</bitWidth> 33370 </field> 33371 <field> 33372 <name>FRMOR</name> 33373 <description>Frame overrun</description> 33374 <bitOffset>9</bitOffset> 33375 <bitWidth>1</bitWidth> 33376 </field> 33377 <field> 33378 <name>DTERR</name> 33379 <description>Data toggle error</description> 33380 <bitOffset>10</bitOffset> 33381 <bitWidth>1</bitWidth> 33382 </field> 33383 </fields> 33384 </register> 33385 <register> 33386 <name>HCINT2</name> 33387 <displayName>HCINT2</displayName> 33388 <description>OTG_HS host channel-2 interrupt 33389 register</description> 33390 <addressOffset>0x148</addressOffset> 33391 <size>32</size> 33392 <access>read-write</access> 33393 <resetValue>0x0</resetValue> 33394 <fields> 33395 <field> 33396 <name>XFRC</name> 33397 <description>Transfer completed</description> 33398 <bitOffset>0</bitOffset> 33399 <bitWidth>1</bitWidth> 33400 </field> 33401 <field> 33402 <name>CHH</name> 33403 <description>Channel halted</description> 33404 <bitOffset>1</bitOffset> 33405 <bitWidth>1</bitWidth> 33406 </field> 33407 <field> 33408 <name>AHBERR</name> 33409 <description>AHB error</description> 33410 <bitOffset>2</bitOffset> 33411 <bitWidth>1</bitWidth> 33412 </field> 33413 <field> 33414 <name>STALL</name> 33415 <description>STALL response received 33416 interrupt</description> 33417 <bitOffset>3</bitOffset> 33418 <bitWidth>1</bitWidth> 33419 </field> 33420 <field> 33421 <name>NAK</name> 33422 <description>NAK response received 33423 interrupt</description> 33424 <bitOffset>4</bitOffset> 33425 <bitWidth>1</bitWidth> 33426 </field> 33427 <field> 33428 <name>ACK</name> 33429 <description>ACK response received/transmitted 33430 interrupt</description> 33431 <bitOffset>5</bitOffset> 33432 <bitWidth>1</bitWidth> 33433 </field> 33434 <field> 33435 <name>NYET</name> 33436 <description>Response received 33437 interrupt</description> 33438 <bitOffset>6</bitOffset> 33439 <bitWidth>1</bitWidth> 33440 </field> 33441 <field> 33442 <name>TXERR</name> 33443 <description>Transaction error</description> 33444 <bitOffset>7</bitOffset> 33445 <bitWidth>1</bitWidth> 33446 </field> 33447 <field> 33448 <name>BBERR</name> 33449 <description>Babble error</description> 33450 <bitOffset>8</bitOffset> 33451 <bitWidth>1</bitWidth> 33452 </field> 33453 <field> 33454 <name>FRMOR</name> 33455 <description>Frame overrun</description> 33456 <bitOffset>9</bitOffset> 33457 <bitWidth>1</bitWidth> 33458 </field> 33459 <field> 33460 <name>DTERR</name> 33461 <description>Data toggle error</description> 33462 <bitOffset>10</bitOffset> 33463 <bitWidth>1</bitWidth> 33464 </field> 33465 </fields> 33466 </register> 33467 <register> 33468 <name>HCINT3</name> 33469 <displayName>HCINT3</displayName> 33470 <description>OTG_HS host channel-3 interrupt 33471 register</description> 33472 <addressOffset>0x168</addressOffset> 33473 <size>32</size> 33474 <access>read-write</access> 33475 <resetValue>0x0</resetValue> 33476 <fields> 33477 <field> 33478 <name>XFRC</name> 33479 <description>Transfer completed</description> 33480 <bitOffset>0</bitOffset> 33481 <bitWidth>1</bitWidth> 33482 </field> 33483 <field> 33484 <name>CHH</name> 33485 <description>Channel halted</description> 33486 <bitOffset>1</bitOffset> 33487 <bitWidth>1</bitWidth> 33488 </field> 33489 <field> 33490 <name>AHBERR</name> 33491 <description>AHB error</description> 33492 <bitOffset>2</bitOffset> 33493 <bitWidth>1</bitWidth> 33494 </field> 33495 <field> 33496 <name>STALL</name> 33497 <description>STALL response received 33498 interrupt</description> 33499 <bitOffset>3</bitOffset> 33500 <bitWidth>1</bitWidth> 33501 </field> 33502 <field> 33503 <name>NAK</name> 33504 <description>NAK response received 33505 interrupt</description> 33506 <bitOffset>4</bitOffset> 33507 <bitWidth>1</bitWidth> 33508 </field> 33509 <field> 33510 <name>ACK</name> 33511 <description>ACK response received/transmitted 33512 interrupt</description> 33513 <bitOffset>5</bitOffset> 33514 <bitWidth>1</bitWidth> 33515 </field> 33516 <field> 33517 <name>NYET</name> 33518 <description>Response received 33519 interrupt</description> 33520 <bitOffset>6</bitOffset> 33521 <bitWidth>1</bitWidth> 33522 </field> 33523 <field> 33524 <name>TXERR</name> 33525 <description>Transaction error</description> 33526 <bitOffset>7</bitOffset> 33527 <bitWidth>1</bitWidth> 33528 </field> 33529 <field> 33530 <name>BBERR</name> 33531 <description>Babble error</description> 33532 <bitOffset>8</bitOffset> 33533 <bitWidth>1</bitWidth> 33534 </field> 33535 <field> 33536 <name>FRMOR</name> 33537 <description>Frame overrun</description> 33538 <bitOffset>9</bitOffset> 33539 <bitWidth>1</bitWidth> 33540 </field> 33541 <field> 33542 <name>DTERR</name> 33543 <description>Data toggle error</description> 33544 <bitOffset>10</bitOffset> 33545 <bitWidth>1</bitWidth> 33546 </field> 33547 </fields> 33548 </register> 33549 <register> 33550 <name>HCINT4</name> 33551 <displayName>HCINT4</displayName> 33552 <description>OTG_HS host channel-4 interrupt 33553 register</description> 33554 <addressOffset>0x188</addressOffset> 33555 <size>32</size> 33556 <access>read-write</access> 33557 <resetValue>0x0</resetValue> 33558 <fields> 33559 <field> 33560 <name>XFRC</name> 33561 <description>Transfer completed</description> 33562 <bitOffset>0</bitOffset> 33563 <bitWidth>1</bitWidth> 33564 </field> 33565 <field> 33566 <name>CHH</name> 33567 <description>Channel halted</description> 33568 <bitOffset>1</bitOffset> 33569 <bitWidth>1</bitWidth> 33570 </field> 33571 <field> 33572 <name>AHBERR</name> 33573 <description>AHB error</description> 33574 <bitOffset>2</bitOffset> 33575 <bitWidth>1</bitWidth> 33576 </field> 33577 <field> 33578 <name>STALL</name> 33579 <description>STALL response received 33580 interrupt</description> 33581 <bitOffset>3</bitOffset> 33582 <bitWidth>1</bitWidth> 33583 </field> 33584 <field> 33585 <name>NAK</name> 33586 <description>NAK response received 33587 interrupt</description> 33588 <bitOffset>4</bitOffset> 33589 <bitWidth>1</bitWidth> 33590 </field> 33591 <field> 33592 <name>ACK</name> 33593 <description>ACK response received/transmitted 33594 interrupt</description> 33595 <bitOffset>5</bitOffset> 33596 <bitWidth>1</bitWidth> 33597 </field> 33598 <field> 33599 <name>NYET</name> 33600 <description>Response received 33601 interrupt</description> 33602 <bitOffset>6</bitOffset> 33603 <bitWidth>1</bitWidth> 33604 </field> 33605 <field> 33606 <name>TXERR</name> 33607 <description>Transaction error</description> 33608 <bitOffset>7</bitOffset> 33609 <bitWidth>1</bitWidth> 33610 </field> 33611 <field> 33612 <name>BBERR</name> 33613 <description>Babble error</description> 33614 <bitOffset>8</bitOffset> 33615 <bitWidth>1</bitWidth> 33616 </field> 33617 <field> 33618 <name>FRMOR</name> 33619 <description>Frame overrun</description> 33620 <bitOffset>9</bitOffset> 33621 <bitWidth>1</bitWidth> 33622 </field> 33623 <field> 33624 <name>DTERR</name> 33625 <description>Data toggle error</description> 33626 <bitOffset>10</bitOffset> 33627 <bitWidth>1</bitWidth> 33628 </field> 33629 </fields> 33630 </register> 33631 <register> 33632 <name>HCINT5</name> 33633 <displayName>HCINT5</displayName> 33634 <description>OTG_HS host channel-5 interrupt 33635 register</description> 33636 <addressOffset>0x1A8</addressOffset> 33637 <size>32</size> 33638 <access>read-write</access> 33639 <resetValue>0x0</resetValue> 33640 <fields> 33641 <field> 33642 <name>XFRC</name> 33643 <description>Transfer completed</description> 33644 <bitOffset>0</bitOffset> 33645 <bitWidth>1</bitWidth> 33646 </field> 33647 <field> 33648 <name>CHH</name> 33649 <description>Channel halted</description> 33650 <bitOffset>1</bitOffset> 33651 <bitWidth>1</bitWidth> 33652 </field> 33653 <field> 33654 <name>AHBERR</name> 33655 <description>AHB error</description> 33656 <bitOffset>2</bitOffset> 33657 <bitWidth>1</bitWidth> 33658 </field> 33659 <field> 33660 <name>STALL</name> 33661 <description>STALL response received 33662 interrupt</description> 33663 <bitOffset>3</bitOffset> 33664 <bitWidth>1</bitWidth> 33665 </field> 33666 <field> 33667 <name>NAK</name> 33668 <description>NAK response received 33669 interrupt</description> 33670 <bitOffset>4</bitOffset> 33671 <bitWidth>1</bitWidth> 33672 </field> 33673 <field> 33674 <name>ACK</name> 33675 <description>ACK response received/transmitted 33676 interrupt</description> 33677 <bitOffset>5</bitOffset> 33678 <bitWidth>1</bitWidth> 33679 </field> 33680 <field> 33681 <name>NYET</name> 33682 <description>Response received 33683 interrupt</description> 33684 <bitOffset>6</bitOffset> 33685 <bitWidth>1</bitWidth> 33686 </field> 33687 <field> 33688 <name>TXERR</name> 33689 <description>Transaction error</description> 33690 <bitOffset>7</bitOffset> 33691 <bitWidth>1</bitWidth> 33692 </field> 33693 <field> 33694 <name>BBERR</name> 33695 <description>Babble error</description> 33696 <bitOffset>8</bitOffset> 33697 <bitWidth>1</bitWidth> 33698 </field> 33699 <field> 33700 <name>FRMOR</name> 33701 <description>Frame overrun</description> 33702 <bitOffset>9</bitOffset> 33703 <bitWidth>1</bitWidth> 33704 </field> 33705 <field> 33706 <name>DTERR</name> 33707 <description>Data toggle error</description> 33708 <bitOffset>10</bitOffset> 33709 <bitWidth>1</bitWidth> 33710 </field> 33711 </fields> 33712 </register> 33713 <register> 33714 <name>HCINT6</name> 33715 <displayName>HCINT6</displayName> 33716 <description>OTG_HS host channel-6 interrupt 33717 register</description> 33718 <addressOffset>0x1C8</addressOffset> 33719 <size>32</size> 33720 <access>read-write</access> 33721 <resetValue>0x0</resetValue> 33722 <fields> 33723 <field> 33724 <name>XFRC</name> 33725 <description>Transfer completed</description> 33726 <bitOffset>0</bitOffset> 33727 <bitWidth>1</bitWidth> 33728 </field> 33729 <field> 33730 <name>CHH</name> 33731 <description>Channel halted</description> 33732 <bitOffset>1</bitOffset> 33733 <bitWidth>1</bitWidth> 33734 </field> 33735 <field> 33736 <name>AHBERR</name> 33737 <description>AHB error</description> 33738 <bitOffset>2</bitOffset> 33739 <bitWidth>1</bitWidth> 33740 </field> 33741 <field> 33742 <name>STALL</name> 33743 <description>STALL response received 33744 interrupt</description> 33745 <bitOffset>3</bitOffset> 33746 <bitWidth>1</bitWidth> 33747 </field> 33748 <field> 33749 <name>NAK</name> 33750 <description>NAK response received 33751 interrupt</description> 33752 <bitOffset>4</bitOffset> 33753 <bitWidth>1</bitWidth> 33754 </field> 33755 <field> 33756 <name>ACK</name> 33757 <description>ACK response received/transmitted 33758 interrupt</description> 33759 <bitOffset>5</bitOffset> 33760 <bitWidth>1</bitWidth> 33761 </field> 33762 <field> 33763 <name>NYET</name> 33764 <description>Response received 33765 interrupt</description> 33766 <bitOffset>6</bitOffset> 33767 <bitWidth>1</bitWidth> 33768 </field> 33769 <field> 33770 <name>TXERR</name> 33771 <description>Transaction error</description> 33772 <bitOffset>7</bitOffset> 33773 <bitWidth>1</bitWidth> 33774 </field> 33775 <field> 33776 <name>BBERR</name> 33777 <description>Babble error</description> 33778 <bitOffset>8</bitOffset> 33779 <bitWidth>1</bitWidth> 33780 </field> 33781 <field> 33782 <name>FRMOR</name> 33783 <description>Frame overrun</description> 33784 <bitOffset>9</bitOffset> 33785 <bitWidth>1</bitWidth> 33786 </field> 33787 <field> 33788 <name>DTERR</name> 33789 <description>Data toggle error</description> 33790 <bitOffset>10</bitOffset> 33791 <bitWidth>1</bitWidth> 33792 </field> 33793 </fields> 33794 </register> 33795 <register> 33796 <name>HCINT7</name> 33797 <displayName>HCINT7</displayName> 33798 <description>OTG_HS host channel-7 interrupt 33799 register</description> 33800 <addressOffset>0x1E8</addressOffset> 33801 <size>32</size> 33802 <access>read-write</access> 33803 <resetValue>0x0</resetValue> 33804 <fields> 33805 <field> 33806 <name>XFRC</name> 33807 <description>Transfer completed</description> 33808 <bitOffset>0</bitOffset> 33809 <bitWidth>1</bitWidth> 33810 </field> 33811 <field> 33812 <name>CHH</name> 33813 <description>Channel halted</description> 33814 <bitOffset>1</bitOffset> 33815 <bitWidth>1</bitWidth> 33816 </field> 33817 <field> 33818 <name>AHBERR</name> 33819 <description>AHB error</description> 33820 <bitOffset>2</bitOffset> 33821 <bitWidth>1</bitWidth> 33822 </field> 33823 <field> 33824 <name>STALL</name> 33825 <description>STALL response received 33826 interrupt</description> 33827 <bitOffset>3</bitOffset> 33828 <bitWidth>1</bitWidth> 33829 </field> 33830 <field> 33831 <name>NAK</name> 33832 <description>NAK response received 33833 interrupt</description> 33834 <bitOffset>4</bitOffset> 33835 <bitWidth>1</bitWidth> 33836 </field> 33837 <field> 33838 <name>ACK</name> 33839 <description>ACK response received/transmitted 33840 interrupt</description> 33841 <bitOffset>5</bitOffset> 33842 <bitWidth>1</bitWidth> 33843 </field> 33844 <field> 33845 <name>NYET</name> 33846 <description>Response received 33847 interrupt</description> 33848 <bitOffset>6</bitOffset> 33849 <bitWidth>1</bitWidth> 33850 </field> 33851 <field> 33852 <name>TXERR</name> 33853 <description>Transaction error</description> 33854 <bitOffset>7</bitOffset> 33855 <bitWidth>1</bitWidth> 33856 </field> 33857 <field> 33858 <name>BBERR</name> 33859 <description>Babble error</description> 33860 <bitOffset>8</bitOffset> 33861 <bitWidth>1</bitWidth> 33862 </field> 33863 <field> 33864 <name>FRMOR</name> 33865 <description>Frame overrun</description> 33866 <bitOffset>9</bitOffset> 33867 <bitWidth>1</bitWidth> 33868 </field> 33869 <field> 33870 <name>DTERR</name> 33871 <description>Data toggle error</description> 33872 <bitOffset>10</bitOffset> 33873 <bitWidth>1</bitWidth> 33874 </field> 33875 </fields> 33876 </register> 33877 <register> 33878 <name>HCINT8</name> 33879 <displayName>HCINT8</displayName> 33880 <description>OTG_HS host channel-8 interrupt 33881 register</description> 33882 <addressOffset>0x208</addressOffset> 33883 <size>32</size> 33884 <access>read-write</access> 33885 <resetValue>0x0</resetValue> 33886 <fields> 33887 <field> 33888 <name>XFRC</name> 33889 <description>Transfer completed</description> 33890 <bitOffset>0</bitOffset> 33891 <bitWidth>1</bitWidth> 33892 </field> 33893 <field> 33894 <name>CHH</name> 33895 <description>Channel halted</description> 33896 <bitOffset>1</bitOffset> 33897 <bitWidth>1</bitWidth> 33898 </field> 33899 <field> 33900 <name>AHBERR</name> 33901 <description>AHB error</description> 33902 <bitOffset>2</bitOffset> 33903 <bitWidth>1</bitWidth> 33904 </field> 33905 <field> 33906 <name>STALL</name> 33907 <description>STALL response received 33908 interrupt</description> 33909 <bitOffset>3</bitOffset> 33910 <bitWidth>1</bitWidth> 33911 </field> 33912 <field> 33913 <name>NAK</name> 33914 <description>NAK response received 33915 interrupt</description> 33916 <bitOffset>4</bitOffset> 33917 <bitWidth>1</bitWidth> 33918 </field> 33919 <field> 33920 <name>ACK</name> 33921 <description>ACK response received/transmitted 33922 interrupt</description> 33923 <bitOffset>5</bitOffset> 33924 <bitWidth>1</bitWidth> 33925 </field> 33926 <field> 33927 <name>NYET</name> 33928 <description>Response received 33929 interrupt</description> 33930 <bitOffset>6</bitOffset> 33931 <bitWidth>1</bitWidth> 33932 </field> 33933 <field> 33934 <name>TXERR</name> 33935 <description>Transaction error</description> 33936 <bitOffset>7</bitOffset> 33937 <bitWidth>1</bitWidth> 33938 </field> 33939 <field> 33940 <name>BBERR</name> 33941 <description>Babble error</description> 33942 <bitOffset>8</bitOffset> 33943 <bitWidth>1</bitWidth> 33944 </field> 33945 <field> 33946 <name>FRMOR</name> 33947 <description>Frame overrun</description> 33948 <bitOffset>9</bitOffset> 33949 <bitWidth>1</bitWidth> 33950 </field> 33951 <field> 33952 <name>DTERR</name> 33953 <description>Data toggle error</description> 33954 <bitOffset>10</bitOffset> 33955 <bitWidth>1</bitWidth> 33956 </field> 33957 </fields> 33958 </register> 33959 <register> 33960 <name>HCINT9</name> 33961 <displayName>HCINT9</displayName> 33962 <description>OTG_HS host channel-9 interrupt 33963 register</description> 33964 <addressOffset>0x228</addressOffset> 33965 <size>32</size> 33966 <access>read-write</access> 33967 <resetValue>0x0</resetValue> 33968 <fields> 33969 <field> 33970 <name>XFRC</name> 33971 <description>Transfer completed</description> 33972 <bitOffset>0</bitOffset> 33973 <bitWidth>1</bitWidth> 33974 </field> 33975 <field> 33976 <name>CHH</name> 33977 <description>Channel halted</description> 33978 <bitOffset>1</bitOffset> 33979 <bitWidth>1</bitWidth> 33980 </field> 33981 <field> 33982 <name>AHBERR</name> 33983 <description>AHB error</description> 33984 <bitOffset>2</bitOffset> 33985 <bitWidth>1</bitWidth> 33986 </field> 33987 <field> 33988 <name>STALL</name> 33989 <description>STALL response received 33990 interrupt</description> 33991 <bitOffset>3</bitOffset> 33992 <bitWidth>1</bitWidth> 33993 </field> 33994 <field> 33995 <name>NAK</name> 33996 <description>NAK response received 33997 interrupt</description> 33998 <bitOffset>4</bitOffset> 33999 <bitWidth>1</bitWidth> 34000 </field> 34001 <field> 34002 <name>ACK</name> 34003 <description>ACK response received/transmitted 34004 interrupt</description> 34005 <bitOffset>5</bitOffset> 34006 <bitWidth>1</bitWidth> 34007 </field> 34008 <field> 34009 <name>NYET</name> 34010 <description>Response received 34011 interrupt</description> 34012 <bitOffset>6</bitOffset> 34013 <bitWidth>1</bitWidth> 34014 </field> 34015 <field> 34016 <name>TXERR</name> 34017 <description>Transaction error</description> 34018 <bitOffset>7</bitOffset> 34019 <bitWidth>1</bitWidth> 34020 </field> 34021 <field> 34022 <name>BBERR</name> 34023 <description>Babble error</description> 34024 <bitOffset>8</bitOffset> 34025 <bitWidth>1</bitWidth> 34026 </field> 34027 <field> 34028 <name>FRMOR</name> 34029 <description>Frame overrun</description> 34030 <bitOffset>9</bitOffset> 34031 <bitWidth>1</bitWidth> 34032 </field> 34033 <field> 34034 <name>DTERR</name> 34035 <description>Data toggle error</description> 34036 <bitOffset>10</bitOffset> 34037 <bitWidth>1</bitWidth> 34038 </field> 34039 </fields> 34040 </register> 34041 <register> 34042 <name>HCINT10</name> 34043 <displayName>HCINT10</displayName> 34044 <description>OTG_HS host channel-10 interrupt 34045 register</description> 34046 <addressOffset>0x248</addressOffset> 34047 <size>32</size> 34048 <access>read-write</access> 34049 <resetValue>0x0</resetValue> 34050 <fields> 34051 <field> 34052 <name>XFRC</name> 34053 <description>Transfer completed</description> 34054 <bitOffset>0</bitOffset> 34055 <bitWidth>1</bitWidth> 34056 </field> 34057 <field> 34058 <name>CHH</name> 34059 <description>Channel halted</description> 34060 <bitOffset>1</bitOffset> 34061 <bitWidth>1</bitWidth> 34062 </field> 34063 <field> 34064 <name>AHBERR</name> 34065 <description>AHB error</description> 34066 <bitOffset>2</bitOffset> 34067 <bitWidth>1</bitWidth> 34068 </field> 34069 <field> 34070 <name>STALL</name> 34071 <description>STALL response received 34072 interrupt</description> 34073 <bitOffset>3</bitOffset> 34074 <bitWidth>1</bitWidth> 34075 </field> 34076 <field> 34077 <name>NAK</name> 34078 <description>NAK response received 34079 interrupt</description> 34080 <bitOffset>4</bitOffset> 34081 <bitWidth>1</bitWidth> 34082 </field> 34083 <field> 34084 <name>ACK</name> 34085 <description>ACK response received/transmitted 34086 interrupt</description> 34087 <bitOffset>5</bitOffset> 34088 <bitWidth>1</bitWidth> 34089 </field> 34090 <field> 34091 <name>NYET</name> 34092 <description>Response received 34093 interrupt</description> 34094 <bitOffset>6</bitOffset> 34095 <bitWidth>1</bitWidth> 34096 </field> 34097 <field> 34098 <name>TXERR</name> 34099 <description>Transaction error</description> 34100 <bitOffset>7</bitOffset> 34101 <bitWidth>1</bitWidth> 34102 </field> 34103 <field> 34104 <name>BBERR</name> 34105 <description>Babble error</description> 34106 <bitOffset>8</bitOffset> 34107 <bitWidth>1</bitWidth> 34108 </field> 34109 <field> 34110 <name>FRMOR</name> 34111 <description>Frame overrun</description> 34112 <bitOffset>9</bitOffset> 34113 <bitWidth>1</bitWidth> 34114 </field> 34115 <field> 34116 <name>DTERR</name> 34117 <description>Data toggle error</description> 34118 <bitOffset>10</bitOffset> 34119 <bitWidth>1</bitWidth> 34120 </field> 34121 </fields> 34122 </register> 34123 <register> 34124 <name>HCINT11</name> 34125 <displayName>HCINT11</displayName> 34126 <description>OTG_HS host channel-11 interrupt 34127 register</description> 34128 <addressOffset>0x268</addressOffset> 34129 <size>32</size> 34130 <access>read-write</access> 34131 <resetValue>0x0</resetValue> 34132 <fields> 34133 <field> 34134 <name>XFRC</name> 34135 <description>Transfer completed</description> 34136 <bitOffset>0</bitOffset> 34137 <bitWidth>1</bitWidth> 34138 </field> 34139 <field> 34140 <name>CHH</name> 34141 <description>Channel halted</description> 34142 <bitOffset>1</bitOffset> 34143 <bitWidth>1</bitWidth> 34144 </field> 34145 <field> 34146 <name>AHBERR</name> 34147 <description>AHB error</description> 34148 <bitOffset>2</bitOffset> 34149 <bitWidth>1</bitWidth> 34150 </field> 34151 <field> 34152 <name>STALL</name> 34153 <description>STALL response received 34154 interrupt</description> 34155 <bitOffset>3</bitOffset> 34156 <bitWidth>1</bitWidth> 34157 </field> 34158 <field> 34159 <name>NAK</name> 34160 <description>NAK response received 34161 interrupt</description> 34162 <bitOffset>4</bitOffset> 34163 <bitWidth>1</bitWidth> 34164 </field> 34165 <field> 34166 <name>ACK</name> 34167 <description>ACK response received/transmitted 34168 interrupt</description> 34169 <bitOffset>5</bitOffset> 34170 <bitWidth>1</bitWidth> 34171 </field> 34172 <field> 34173 <name>NYET</name> 34174 <description>Response received 34175 interrupt</description> 34176 <bitOffset>6</bitOffset> 34177 <bitWidth>1</bitWidth> 34178 </field> 34179 <field> 34180 <name>TXERR</name> 34181 <description>Transaction error</description> 34182 <bitOffset>7</bitOffset> 34183 <bitWidth>1</bitWidth> 34184 </field> 34185 <field> 34186 <name>BBERR</name> 34187 <description>Babble error</description> 34188 <bitOffset>8</bitOffset> 34189 <bitWidth>1</bitWidth> 34190 </field> 34191 <field> 34192 <name>FRMOR</name> 34193 <description>Frame overrun</description> 34194 <bitOffset>9</bitOffset> 34195 <bitWidth>1</bitWidth> 34196 </field> 34197 <field> 34198 <name>DTERR</name> 34199 <description>Data toggle error</description> 34200 <bitOffset>10</bitOffset> 34201 <bitWidth>1</bitWidth> 34202 </field> 34203 </fields> 34204 </register> 34205 <register> 34206 <name>HCINTMSK0</name> 34207 <displayName>HCINTMSK0</displayName> 34208 <description>OTG_HS host channel-11 interrupt mask 34209 register</description> 34210 <addressOffset>0x10C</addressOffset> 34211 <size>32</size> 34212 <access>read-write</access> 34213 <resetValue>0x0</resetValue> 34214 <fields> 34215 <field> 34216 <name>XFRCM</name> 34217 <description>Transfer completed mask</description> 34218 <bitOffset>0</bitOffset> 34219 <bitWidth>1</bitWidth> 34220 </field> 34221 <field> 34222 <name>CHHM</name> 34223 <description>Channel halted mask</description> 34224 <bitOffset>1</bitOffset> 34225 <bitWidth>1</bitWidth> 34226 </field> 34227 <field> 34228 <name>AHBERR</name> 34229 <description>AHB error</description> 34230 <bitOffset>2</bitOffset> 34231 <bitWidth>1</bitWidth> 34232 </field> 34233 <field> 34234 <name>STALLM</name> 34235 <description>STALL response received interrupt 34236 mask</description> 34237 <bitOffset>3</bitOffset> 34238 <bitWidth>1</bitWidth> 34239 </field> 34240 <field> 34241 <name>NAKM</name> 34242 <description>NAK response received interrupt 34243 mask</description> 34244 <bitOffset>4</bitOffset> 34245 <bitWidth>1</bitWidth> 34246 </field> 34247 <field> 34248 <name>ACKM</name> 34249 <description>ACK response received/transmitted 34250 interrupt mask</description> 34251 <bitOffset>5</bitOffset> 34252 <bitWidth>1</bitWidth> 34253 </field> 34254 <field> 34255 <name>NYET</name> 34256 <description>response received interrupt 34257 mask</description> 34258 <bitOffset>6</bitOffset> 34259 <bitWidth>1</bitWidth> 34260 </field> 34261 <field> 34262 <name>TXERRM</name> 34263 <description>Transaction error mask</description> 34264 <bitOffset>7</bitOffset> 34265 <bitWidth>1</bitWidth> 34266 </field> 34267 <field> 34268 <name>BBERRM</name> 34269 <description>Babble error mask</description> 34270 <bitOffset>8</bitOffset> 34271 <bitWidth>1</bitWidth> 34272 </field> 34273 <field> 34274 <name>FRMORM</name> 34275 <description>Frame overrun mask</description> 34276 <bitOffset>9</bitOffset> 34277 <bitWidth>1</bitWidth> 34278 </field> 34279 <field> 34280 <name>DTERRM</name> 34281 <description>Data toggle error mask</description> 34282 <bitOffset>10</bitOffset> 34283 <bitWidth>1</bitWidth> 34284 </field> 34285 </fields> 34286 </register> 34287 <register> 34288 <name>HCINTMSK1</name> 34289 <displayName>HCINTMSK1</displayName> 34290 <description>OTG_HS host channel-1 interrupt mask 34291 register</description> 34292 <addressOffset>0x12C</addressOffset> 34293 <size>32</size> 34294 <access>read-write</access> 34295 <resetValue>0x0</resetValue> 34296 <fields> 34297 <field> 34298 <name>XFRCM</name> 34299 <description>Transfer completed mask</description> 34300 <bitOffset>0</bitOffset> 34301 <bitWidth>1</bitWidth> 34302 </field> 34303 <field> 34304 <name>CHHM</name> 34305 <description>Channel halted mask</description> 34306 <bitOffset>1</bitOffset> 34307 <bitWidth>1</bitWidth> 34308 </field> 34309 <field> 34310 <name>AHBERR</name> 34311 <description>AHB error</description> 34312 <bitOffset>2</bitOffset> 34313 <bitWidth>1</bitWidth> 34314 </field> 34315 <field> 34316 <name>STALLM</name> 34317 <description>STALL response received interrupt 34318 mask</description> 34319 <bitOffset>3</bitOffset> 34320 <bitWidth>1</bitWidth> 34321 </field> 34322 <field> 34323 <name>NAKM</name> 34324 <description>NAK response received interrupt 34325 mask</description> 34326 <bitOffset>4</bitOffset> 34327 <bitWidth>1</bitWidth> 34328 </field> 34329 <field> 34330 <name>ACKM</name> 34331 <description>ACK response received/transmitted 34332 interrupt mask</description> 34333 <bitOffset>5</bitOffset> 34334 <bitWidth>1</bitWidth> 34335 </field> 34336 <field> 34337 <name>NYET</name> 34338 <description>response received interrupt 34339 mask</description> 34340 <bitOffset>6</bitOffset> 34341 <bitWidth>1</bitWidth> 34342 </field> 34343 <field> 34344 <name>TXERRM</name> 34345 <description>Transaction error mask</description> 34346 <bitOffset>7</bitOffset> 34347 <bitWidth>1</bitWidth> 34348 </field> 34349 <field> 34350 <name>BBERRM</name> 34351 <description>Babble error mask</description> 34352 <bitOffset>8</bitOffset> 34353 <bitWidth>1</bitWidth> 34354 </field> 34355 <field> 34356 <name>FRMORM</name> 34357 <description>Frame overrun mask</description> 34358 <bitOffset>9</bitOffset> 34359 <bitWidth>1</bitWidth> 34360 </field> 34361 <field> 34362 <name>DTERRM</name> 34363 <description>Data toggle error mask</description> 34364 <bitOffset>10</bitOffset> 34365 <bitWidth>1</bitWidth> 34366 </field> 34367 </fields> 34368 </register> 34369 <register> 34370 <name>HCINTMSK2</name> 34371 <displayName>HCINTMSK2</displayName> 34372 <description>OTG_HS host channel-2 interrupt mask 34373 register</description> 34374 <addressOffset>0x14C</addressOffset> 34375 <size>32</size> 34376 <access>read-write</access> 34377 <resetValue>0x0</resetValue> 34378 <fields> 34379 <field> 34380 <name>XFRCM</name> 34381 <description>Transfer completed mask</description> 34382 <bitOffset>0</bitOffset> 34383 <bitWidth>1</bitWidth> 34384 </field> 34385 <field> 34386 <name>CHHM</name> 34387 <description>Channel halted mask</description> 34388 <bitOffset>1</bitOffset> 34389 <bitWidth>1</bitWidth> 34390 </field> 34391 <field> 34392 <name>AHBERR</name> 34393 <description>AHB error</description> 34394 <bitOffset>2</bitOffset> 34395 <bitWidth>1</bitWidth> 34396 </field> 34397 <field> 34398 <name>STALLM</name> 34399 <description>STALL response received interrupt 34400 mask</description> 34401 <bitOffset>3</bitOffset> 34402 <bitWidth>1</bitWidth> 34403 </field> 34404 <field> 34405 <name>NAKM</name> 34406 <description>NAK response received interrupt 34407 mask</description> 34408 <bitOffset>4</bitOffset> 34409 <bitWidth>1</bitWidth> 34410 </field> 34411 <field> 34412 <name>ACKM</name> 34413 <description>ACK response received/transmitted 34414 interrupt mask</description> 34415 <bitOffset>5</bitOffset> 34416 <bitWidth>1</bitWidth> 34417 </field> 34418 <field> 34419 <name>NYET</name> 34420 <description>response received interrupt 34421 mask</description> 34422 <bitOffset>6</bitOffset> 34423 <bitWidth>1</bitWidth> 34424 </field> 34425 <field> 34426 <name>TXERRM</name> 34427 <description>Transaction error mask</description> 34428 <bitOffset>7</bitOffset> 34429 <bitWidth>1</bitWidth> 34430 </field> 34431 <field> 34432 <name>BBERRM</name> 34433 <description>Babble error mask</description> 34434 <bitOffset>8</bitOffset> 34435 <bitWidth>1</bitWidth> 34436 </field> 34437 <field> 34438 <name>FRMORM</name> 34439 <description>Frame overrun mask</description> 34440 <bitOffset>9</bitOffset> 34441 <bitWidth>1</bitWidth> 34442 </field> 34443 <field> 34444 <name>DTERRM</name> 34445 <description>Data toggle error mask</description> 34446 <bitOffset>10</bitOffset> 34447 <bitWidth>1</bitWidth> 34448 </field> 34449 </fields> 34450 </register> 34451 <register> 34452 <name>HCINTMSK3</name> 34453 <displayName>HCINTMSK3</displayName> 34454 <description>OTG_HS host channel-3 interrupt mask 34455 register</description> 34456 <addressOffset>0x16C</addressOffset> 34457 <size>32</size> 34458 <access>read-write</access> 34459 <resetValue>0x0</resetValue> 34460 <fields> 34461 <field> 34462 <name>XFRCM</name> 34463 <description>Transfer completed mask</description> 34464 <bitOffset>0</bitOffset> 34465 <bitWidth>1</bitWidth> 34466 </field> 34467 <field> 34468 <name>CHHM</name> 34469 <description>Channel halted mask</description> 34470 <bitOffset>1</bitOffset> 34471 <bitWidth>1</bitWidth> 34472 </field> 34473 <field> 34474 <name>AHBERR</name> 34475 <description>AHB error</description> 34476 <bitOffset>2</bitOffset> 34477 <bitWidth>1</bitWidth> 34478 </field> 34479 <field> 34480 <name>STALLM</name> 34481 <description>STALL response received interrupt 34482 mask</description> 34483 <bitOffset>3</bitOffset> 34484 <bitWidth>1</bitWidth> 34485 </field> 34486 <field> 34487 <name>NAKM</name> 34488 <description>NAK response received interrupt 34489 mask</description> 34490 <bitOffset>4</bitOffset> 34491 <bitWidth>1</bitWidth> 34492 </field> 34493 <field> 34494 <name>ACKM</name> 34495 <description>ACK response received/transmitted 34496 interrupt mask</description> 34497 <bitOffset>5</bitOffset> 34498 <bitWidth>1</bitWidth> 34499 </field> 34500 <field> 34501 <name>NYET</name> 34502 <description>response received interrupt 34503 mask</description> 34504 <bitOffset>6</bitOffset> 34505 <bitWidth>1</bitWidth> 34506 </field> 34507 <field> 34508 <name>TXERRM</name> 34509 <description>Transaction error mask</description> 34510 <bitOffset>7</bitOffset> 34511 <bitWidth>1</bitWidth> 34512 </field> 34513 <field> 34514 <name>BBERRM</name> 34515 <description>Babble error mask</description> 34516 <bitOffset>8</bitOffset> 34517 <bitWidth>1</bitWidth> 34518 </field> 34519 <field> 34520 <name>FRMORM</name> 34521 <description>Frame overrun mask</description> 34522 <bitOffset>9</bitOffset> 34523 <bitWidth>1</bitWidth> 34524 </field> 34525 <field> 34526 <name>DTERRM</name> 34527 <description>Data toggle error mask</description> 34528 <bitOffset>10</bitOffset> 34529 <bitWidth>1</bitWidth> 34530 </field> 34531 </fields> 34532 </register> 34533 <register> 34534 <name>HCINTMSK4</name> 34535 <displayName>HCINTMSK4</displayName> 34536 <description>OTG_HS host channel-4 interrupt mask 34537 register</description> 34538 <addressOffset>0x18C</addressOffset> 34539 <size>32</size> 34540 <access>read-write</access> 34541 <resetValue>0x0</resetValue> 34542 <fields> 34543 <field> 34544 <name>XFRCM</name> 34545 <description>Transfer completed mask</description> 34546 <bitOffset>0</bitOffset> 34547 <bitWidth>1</bitWidth> 34548 </field> 34549 <field> 34550 <name>CHHM</name> 34551 <description>Channel halted mask</description> 34552 <bitOffset>1</bitOffset> 34553 <bitWidth>1</bitWidth> 34554 </field> 34555 <field> 34556 <name>AHBERR</name> 34557 <description>AHB error</description> 34558 <bitOffset>2</bitOffset> 34559 <bitWidth>1</bitWidth> 34560 </field> 34561 <field> 34562 <name>STALLM</name> 34563 <description>STALL response received interrupt 34564 mask</description> 34565 <bitOffset>3</bitOffset> 34566 <bitWidth>1</bitWidth> 34567 </field> 34568 <field> 34569 <name>NAKM</name> 34570 <description>NAK response received interrupt 34571 mask</description> 34572 <bitOffset>4</bitOffset> 34573 <bitWidth>1</bitWidth> 34574 </field> 34575 <field> 34576 <name>ACKM</name> 34577 <description>ACK response received/transmitted 34578 interrupt mask</description> 34579 <bitOffset>5</bitOffset> 34580 <bitWidth>1</bitWidth> 34581 </field> 34582 <field> 34583 <name>NYET</name> 34584 <description>response received interrupt 34585 mask</description> 34586 <bitOffset>6</bitOffset> 34587 <bitWidth>1</bitWidth> 34588 </field> 34589 <field> 34590 <name>TXERRM</name> 34591 <description>Transaction error mask</description> 34592 <bitOffset>7</bitOffset> 34593 <bitWidth>1</bitWidth> 34594 </field> 34595 <field> 34596 <name>BBERRM</name> 34597 <description>Babble error mask</description> 34598 <bitOffset>8</bitOffset> 34599 <bitWidth>1</bitWidth> 34600 </field> 34601 <field> 34602 <name>FRMORM</name> 34603 <description>Frame overrun mask</description> 34604 <bitOffset>9</bitOffset> 34605 <bitWidth>1</bitWidth> 34606 </field> 34607 <field> 34608 <name>DTERRM</name> 34609 <description>Data toggle error mask</description> 34610 <bitOffset>10</bitOffset> 34611 <bitWidth>1</bitWidth> 34612 </field> 34613 </fields> 34614 </register> 34615 <register> 34616 <name>HCINTMSK5</name> 34617 <displayName>HCINTMSK5</displayName> 34618 <description>OTG_HS host channel-5 interrupt mask 34619 register</description> 34620 <addressOffset>0x1AC</addressOffset> 34621 <size>32</size> 34622 <access>read-write</access> 34623 <resetValue>0x0</resetValue> 34624 <fields> 34625 <field> 34626 <name>XFRCM</name> 34627 <description>Transfer completed mask</description> 34628 <bitOffset>0</bitOffset> 34629 <bitWidth>1</bitWidth> 34630 </field> 34631 <field> 34632 <name>CHHM</name> 34633 <description>Channel halted mask</description> 34634 <bitOffset>1</bitOffset> 34635 <bitWidth>1</bitWidth> 34636 </field> 34637 <field> 34638 <name>AHBERR</name> 34639 <description>AHB error</description> 34640 <bitOffset>2</bitOffset> 34641 <bitWidth>1</bitWidth> 34642 </field> 34643 <field> 34644 <name>STALLM</name> 34645 <description>STALL response received interrupt 34646 mask</description> 34647 <bitOffset>3</bitOffset> 34648 <bitWidth>1</bitWidth> 34649 </field> 34650 <field> 34651 <name>NAKM</name> 34652 <description>NAK response received interrupt 34653 mask</description> 34654 <bitOffset>4</bitOffset> 34655 <bitWidth>1</bitWidth> 34656 </field> 34657 <field> 34658 <name>ACKM</name> 34659 <description>ACK response received/transmitted 34660 interrupt mask</description> 34661 <bitOffset>5</bitOffset> 34662 <bitWidth>1</bitWidth> 34663 </field> 34664 <field> 34665 <name>NYET</name> 34666 <description>response received interrupt 34667 mask</description> 34668 <bitOffset>6</bitOffset> 34669 <bitWidth>1</bitWidth> 34670 </field> 34671 <field> 34672 <name>TXERRM</name> 34673 <description>Transaction error mask</description> 34674 <bitOffset>7</bitOffset> 34675 <bitWidth>1</bitWidth> 34676 </field> 34677 <field> 34678 <name>BBERRM</name> 34679 <description>Babble error mask</description> 34680 <bitOffset>8</bitOffset> 34681 <bitWidth>1</bitWidth> 34682 </field> 34683 <field> 34684 <name>FRMORM</name> 34685 <description>Frame overrun mask</description> 34686 <bitOffset>9</bitOffset> 34687 <bitWidth>1</bitWidth> 34688 </field> 34689 <field> 34690 <name>DTERRM</name> 34691 <description>Data toggle error mask</description> 34692 <bitOffset>10</bitOffset> 34693 <bitWidth>1</bitWidth> 34694 </field> 34695 </fields> 34696 </register> 34697 <register> 34698 <name>HCINTMSK6</name> 34699 <displayName>HCINTMSK6</displayName> 34700 <description>OTG_HS host channel-6 interrupt mask 34701 register</description> 34702 <addressOffset>0x1CC</addressOffset> 34703 <size>32</size> 34704 <access>read-write</access> 34705 <resetValue>0x0</resetValue> 34706 <fields> 34707 <field> 34708 <name>XFRCM</name> 34709 <description>Transfer completed mask</description> 34710 <bitOffset>0</bitOffset> 34711 <bitWidth>1</bitWidth> 34712 </field> 34713 <field> 34714 <name>CHHM</name> 34715 <description>Channel halted mask</description> 34716 <bitOffset>1</bitOffset> 34717 <bitWidth>1</bitWidth> 34718 </field> 34719 <field> 34720 <name>AHBERR</name> 34721 <description>AHB error</description> 34722 <bitOffset>2</bitOffset> 34723 <bitWidth>1</bitWidth> 34724 </field> 34725 <field> 34726 <name>STALLM</name> 34727 <description>STALL response received interrupt 34728 mask</description> 34729 <bitOffset>3</bitOffset> 34730 <bitWidth>1</bitWidth> 34731 </field> 34732 <field> 34733 <name>NAKM</name> 34734 <description>NAK response received interrupt 34735 mask</description> 34736 <bitOffset>4</bitOffset> 34737 <bitWidth>1</bitWidth> 34738 </field> 34739 <field> 34740 <name>ACKM</name> 34741 <description>ACK response received/transmitted 34742 interrupt mask</description> 34743 <bitOffset>5</bitOffset> 34744 <bitWidth>1</bitWidth> 34745 </field> 34746 <field> 34747 <name>NYET</name> 34748 <description>response received interrupt 34749 mask</description> 34750 <bitOffset>6</bitOffset> 34751 <bitWidth>1</bitWidth> 34752 </field> 34753 <field> 34754 <name>TXERRM</name> 34755 <description>Transaction error mask</description> 34756 <bitOffset>7</bitOffset> 34757 <bitWidth>1</bitWidth> 34758 </field> 34759 <field> 34760 <name>BBERRM</name> 34761 <description>Babble error mask</description> 34762 <bitOffset>8</bitOffset> 34763 <bitWidth>1</bitWidth> 34764 </field> 34765 <field> 34766 <name>FRMORM</name> 34767 <description>Frame overrun mask</description> 34768 <bitOffset>9</bitOffset> 34769 <bitWidth>1</bitWidth> 34770 </field> 34771 <field> 34772 <name>DTERRM</name> 34773 <description>Data toggle error mask</description> 34774 <bitOffset>10</bitOffset> 34775 <bitWidth>1</bitWidth> 34776 </field> 34777 </fields> 34778 </register> 34779 <register> 34780 <name>HCINTMSK7</name> 34781 <displayName>HCINTMSK7</displayName> 34782 <description>OTG_HS host channel-7 interrupt mask 34783 register</description> 34784 <addressOffset>0x1EC</addressOffset> 34785 <size>32</size> 34786 <access>read-write</access> 34787 <resetValue>0x0</resetValue> 34788 <fields> 34789 <field> 34790 <name>XFRCM</name> 34791 <description>Transfer completed mask</description> 34792 <bitOffset>0</bitOffset> 34793 <bitWidth>1</bitWidth> 34794 </field> 34795 <field> 34796 <name>CHHM</name> 34797 <description>Channel halted mask</description> 34798 <bitOffset>1</bitOffset> 34799 <bitWidth>1</bitWidth> 34800 </field> 34801 <field> 34802 <name>AHBERR</name> 34803 <description>AHB error</description> 34804 <bitOffset>2</bitOffset> 34805 <bitWidth>1</bitWidth> 34806 </field> 34807 <field> 34808 <name>STALLM</name> 34809 <description>STALL response received interrupt 34810 mask</description> 34811 <bitOffset>3</bitOffset> 34812 <bitWidth>1</bitWidth> 34813 </field> 34814 <field> 34815 <name>NAKM</name> 34816 <description>NAK response received interrupt 34817 mask</description> 34818 <bitOffset>4</bitOffset> 34819 <bitWidth>1</bitWidth> 34820 </field> 34821 <field> 34822 <name>ACKM</name> 34823 <description>ACK response received/transmitted 34824 interrupt mask</description> 34825 <bitOffset>5</bitOffset> 34826 <bitWidth>1</bitWidth> 34827 </field> 34828 <field> 34829 <name>NYET</name> 34830 <description>response received interrupt 34831 mask</description> 34832 <bitOffset>6</bitOffset> 34833 <bitWidth>1</bitWidth> 34834 </field> 34835 <field> 34836 <name>TXERRM</name> 34837 <description>Transaction error mask</description> 34838 <bitOffset>7</bitOffset> 34839 <bitWidth>1</bitWidth> 34840 </field> 34841 <field> 34842 <name>BBERRM</name> 34843 <description>Babble error mask</description> 34844 <bitOffset>8</bitOffset> 34845 <bitWidth>1</bitWidth> 34846 </field> 34847 <field> 34848 <name>FRMORM</name> 34849 <description>Frame overrun mask</description> 34850 <bitOffset>9</bitOffset> 34851 <bitWidth>1</bitWidth> 34852 </field> 34853 <field> 34854 <name>DTERRM</name> 34855 <description>Data toggle error mask</description> 34856 <bitOffset>10</bitOffset> 34857 <bitWidth>1</bitWidth> 34858 </field> 34859 </fields> 34860 </register> 34861 <register> 34862 <name>HCINTMSK8</name> 34863 <displayName>HCINTMSK8</displayName> 34864 <description>OTG_HS host channel-8 interrupt mask 34865 register</description> 34866 <addressOffset>0x20C</addressOffset> 34867 <size>32</size> 34868 <access>read-write</access> 34869 <resetValue>0x0</resetValue> 34870 <fields> 34871 <field> 34872 <name>XFRCM</name> 34873 <description>Transfer completed mask</description> 34874 <bitOffset>0</bitOffset> 34875 <bitWidth>1</bitWidth> 34876 </field> 34877 <field> 34878 <name>CHHM</name> 34879 <description>Channel halted mask</description> 34880 <bitOffset>1</bitOffset> 34881 <bitWidth>1</bitWidth> 34882 </field> 34883 <field> 34884 <name>AHBERR</name> 34885 <description>AHB error</description> 34886 <bitOffset>2</bitOffset> 34887 <bitWidth>1</bitWidth> 34888 </field> 34889 <field> 34890 <name>STALLM</name> 34891 <description>STALL response received interrupt 34892 mask</description> 34893 <bitOffset>3</bitOffset> 34894 <bitWidth>1</bitWidth> 34895 </field> 34896 <field> 34897 <name>NAKM</name> 34898 <description>NAK response received interrupt 34899 mask</description> 34900 <bitOffset>4</bitOffset> 34901 <bitWidth>1</bitWidth> 34902 </field> 34903 <field> 34904 <name>ACKM</name> 34905 <description>ACK response received/transmitted 34906 interrupt mask</description> 34907 <bitOffset>5</bitOffset> 34908 <bitWidth>1</bitWidth> 34909 </field> 34910 <field> 34911 <name>NYET</name> 34912 <description>response received interrupt 34913 mask</description> 34914 <bitOffset>6</bitOffset> 34915 <bitWidth>1</bitWidth> 34916 </field> 34917 <field> 34918 <name>TXERRM</name> 34919 <description>Transaction error mask</description> 34920 <bitOffset>7</bitOffset> 34921 <bitWidth>1</bitWidth> 34922 </field> 34923 <field> 34924 <name>BBERRM</name> 34925 <description>Babble error mask</description> 34926 <bitOffset>8</bitOffset> 34927 <bitWidth>1</bitWidth> 34928 </field> 34929 <field> 34930 <name>FRMORM</name> 34931 <description>Frame overrun mask</description> 34932 <bitOffset>9</bitOffset> 34933 <bitWidth>1</bitWidth> 34934 </field> 34935 <field> 34936 <name>DTERRM</name> 34937 <description>Data toggle error mask</description> 34938 <bitOffset>10</bitOffset> 34939 <bitWidth>1</bitWidth> 34940 </field> 34941 </fields> 34942 </register> 34943 <register> 34944 <name>HCINTMSK9</name> 34945 <displayName>HCINTMSK9</displayName> 34946 <description>OTG_HS host channel-9 interrupt mask 34947 register</description> 34948 <addressOffset>0x22C</addressOffset> 34949 <size>32</size> 34950 <access>read-write</access> 34951 <resetValue>0x0</resetValue> 34952 <fields> 34953 <field> 34954 <name>XFRCM</name> 34955 <description>Transfer completed mask</description> 34956 <bitOffset>0</bitOffset> 34957 <bitWidth>1</bitWidth> 34958 </field> 34959 <field> 34960 <name>CHHM</name> 34961 <description>Channel halted mask</description> 34962 <bitOffset>1</bitOffset> 34963 <bitWidth>1</bitWidth> 34964 </field> 34965 <field> 34966 <name>AHBERR</name> 34967 <description>AHB error</description> 34968 <bitOffset>2</bitOffset> 34969 <bitWidth>1</bitWidth> 34970 </field> 34971 <field> 34972 <name>STALLM</name> 34973 <description>STALL response received interrupt 34974 mask</description> 34975 <bitOffset>3</bitOffset> 34976 <bitWidth>1</bitWidth> 34977 </field> 34978 <field> 34979 <name>NAKM</name> 34980 <description>NAK response received interrupt 34981 mask</description> 34982 <bitOffset>4</bitOffset> 34983 <bitWidth>1</bitWidth> 34984 </field> 34985 <field> 34986 <name>ACKM</name> 34987 <description>ACK response received/transmitted 34988 interrupt mask</description> 34989 <bitOffset>5</bitOffset> 34990 <bitWidth>1</bitWidth> 34991 </field> 34992 <field> 34993 <name>NYET</name> 34994 <description>response received interrupt 34995 mask</description> 34996 <bitOffset>6</bitOffset> 34997 <bitWidth>1</bitWidth> 34998 </field> 34999 <field> 35000 <name>TXERRM</name> 35001 <description>Transaction error mask</description> 35002 <bitOffset>7</bitOffset> 35003 <bitWidth>1</bitWidth> 35004 </field> 35005 <field> 35006 <name>BBERRM</name> 35007 <description>Babble error mask</description> 35008 <bitOffset>8</bitOffset> 35009 <bitWidth>1</bitWidth> 35010 </field> 35011 <field> 35012 <name>FRMORM</name> 35013 <description>Frame overrun mask</description> 35014 <bitOffset>9</bitOffset> 35015 <bitWidth>1</bitWidth> 35016 </field> 35017 <field> 35018 <name>DTERRM</name> 35019 <description>Data toggle error mask</description> 35020 <bitOffset>10</bitOffset> 35021 <bitWidth>1</bitWidth> 35022 </field> 35023 </fields> 35024 </register> 35025 <register> 35026 <name>HCINTMSK10</name> 35027 <displayName>HCINTMSK10</displayName> 35028 <description>OTG_HS host channel-10 interrupt mask 35029 register</description> 35030 <addressOffset>0x24C</addressOffset> 35031 <size>32</size> 35032 <access>read-write</access> 35033 <resetValue>0x0</resetValue> 35034 <fields> 35035 <field> 35036 <name>XFRCM</name> 35037 <description>Transfer completed mask</description> 35038 <bitOffset>0</bitOffset> 35039 <bitWidth>1</bitWidth> 35040 </field> 35041 <field> 35042 <name>CHHM</name> 35043 <description>Channel halted mask</description> 35044 <bitOffset>1</bitOffset> 35045 <bitWidth>1</bitWidth> 35046 </field> 35047 <field> 35048 <name>AHBERR</name> 35049 <description>AHB error</description> 35050 <bitOffset>2</bitOffset> 35051 <bitWidth>1</bitWidth> 35052 </field> 35053 <field> 35054 <name>STALLM</name> 35055 <description>STALL response received interrupt 35056 mask</description> 35057 <bitOffset>3</bitOffset> 35058 <bitWidth>1</bitWidth> 35059 </field> 35060 <field> 35061 <name>NAKM</name> 35062 <description>NAK response received interrupt 35063 mask</description> 35064 <bitOffset>4</bitOffset> 35065 <bitWidth>1</bitWidth> 35066 </field> 35067 <field> 35068 <name>ACKM</name> 35069 <description>ACK response received/transmitted 35070 interrupt mask</description> 35071 <bitOffset>5</bitOffset> 35072 <bitWidth>1</bitWidth> 35073 </field> 35074 <field> 35075 <name>NYET</name> 35076 <description>response received interrupt 35077 mask</description> 35078 <bitOffset>6</bitOffset> 35079 <bitWidth>1</bitWidth> 35080 </field> 35081 <field> 35082 <name>TXERRM</name> 35083 <description>Transaction error mask</description> 35084 <bitOffset>7</bitOffset> 35085 <bitWidth>1</bitWidth> 35086 </field> 35087 <field> 35088 <name>BBERRM</name> 35089 <description>Babble error mask</description> 35090 <bitOffset>8</bitOffset> 35091 <bitWidth>1</bitWidth> 35092 </field> 35093 <field> 35094 <name>FRMORM</name> 35095 <description>Frame overrun mask</description> 35096 <bitOffset>9</bitOffset> 35097 <bitWidth>1</bitWidth> 35098 </field> 35099 <field> 35100 <name>DTERRM</name> 35101 <description>Data toggle error mask</description> 35102 <bitOffset>10</bitOffset> 35103 <bitWidth>1</bitWidth> 35104 </field> 35105 </fields> 35106 </register> 35107 <register> 35108 <name>HCINTMSK11</name> 35109 <displayName>HCINTMSK11</displayName> 35110 <description>OTG_HS host channel-11 interrupt mask 35111 register</description> 35112 <addressOffset>0x26C</addressOffset> 35113 <size>32</size> 35114 <access>read-write</access> 35115 <resetValue>0x0</resetValue> 35116 <fields> 35117 <field> 35118 <name>XFRCM</name> 35119 <description>Transfer completed mask</description> 35120 <bitOffset>0</bitOffset> 35121 <bitWidth>1</bitWidth> 35122 </field> 35123 <field> 35124 <name>CHHM</name> 35125 <description>Channel halted mask</description> 35126 <bitOffset>1</bitOffset> 35127 <bitWidth>1</bitWidth> 35128 </field> 35129 <field> 35130 <name>AHBERR</name> 35131 <description>AHB error</description> 35132 <bitOffset>2</bitOffset> 35133 <bitWidth>1</bitWidth> 35134 </field> 35135 <field> 35136 <name>STALLM</name> 35137 <description>STALL response received interrupt 35138 mask</description> 35139 <bitOffset>3</bitOffset> 35140 <bitWidth>1</bitWidth> 35141 </field> 35142 <field> 35143 <name>NAKM</name> 35144 <description>NAK response received interrupt 35145 mask</description> 35146 <bitOffset>4</bitOffset> 35147 <bitWidth>1</bitWidth> 35148 </field> 35149 <field> 35150 <name>ACKM</name> 35151 <description>ACK response received/transmitted 35152 interrupt mask</description> 35153 <bitOffset>5</bitOffset> 35154 <bitWidth>1</bitWidth> 35155 </field> 35156 <field> 35157 <name>NYET</name> 35158 <description>response received interrupt 35159 mask</description> 35160 <bitOffset>6</bitOffset> 35161 <bitWidth>1</bitWidth> 35162 </field> 35163 <field> 35164 <name>TXERRM</name> 35165 <description>Transaction error mask</description> 35166 <bitOffset>7</bitOffset> 35167 <bitWidth>1</bitWidth> 35168 </field> 35169 <field> 35170 <name>BBERRM</name> 35171 <description>Babble error mask</description> 35172 <bitOffset>8</bitOffset> 35173 <bitWidth>1</bitWidth> 35174 </field> 35175 <field> 35176 <name>FRMORM</name> 35177 <description>Frame overrun mask</description> 35178 <bitOffset>9</bitOffset> 35179 <bitWidth>1</bitWidth> 35180 </field> 35181 <field> 35182 <name>DTERRM</name> 35183 <description>Data toggle error mask</description> 35184 <bitOffset>10</bitOffset> 35185 <bitWidth>1</bitWidth> 35186 </field> 35187 </fields> 35188 </register> 35189 <register> 35190 <name>HCTSIZ0</name> 35191 <displayName>HCTSIZ0</displayName> 35192 <description>OTG_HS host channel-11 transfer size 35193 register</description> 35194 <addressOffset>0x110</addressOffset> 35195 <size>32</size> 35196 <access>read-write</access> 35197 <resetValue>0x0</resetValue> 35198 <fields> 35199 <field> 35200 <name>XFRSIZ</name> 35201 <description>Transfer size</description> 35202 <bitOffset>0</bitOffset> 35203 <bitWidth>19</bitWidth> 35204 </field> 35205 <field> 35206 <name>PKTCNT</name> 35207 <description>Packet count</description> 35208 <bitOffset>19</bitOffset> 35209 <bitWidth>10</bitWidth> 35210 </field> 35211 <field> 35212 <name>DPID</name> 35213 <description>Data PID</description> 35214 <bitOffset>29</bitOffset> 35215 <bitWidth>2</bitWidth> 35216 </field> 35217 </fields> 35218 </register> 35219 <register> 35220 <name>HCTSIZ1</name> 35221 <displayName>HCTSIZ1</displayName> 35222 <description>OTG_HS host channel-1 transfer size 35223 register</description> 35224 <addressOffset>0x130</addressOffset> 35225 <size>32</size> 35226 <access>read-write</access> 35227 <resetValue>0x0</resetValue> 35228 <fields> 35229 <field> 35230 <name>XFRSIZ</name> 35231 <description>Transfer size</description> 35232 <bitOffset>0</bitOffset> 35233 <bitWidth>19</bitWidth> 35234 </field> 35235 <field> 35236 <name>PKTCNT</name> 35237 <description>Packet count</description> 35238 <bitOffset>19</bitOffset> 35239 <bitWidth>10</bitWidth> 35240 </field> 35241 <field> 35242 <name>DPID</name> 35243 <description>Data PID</description> 35244 <bitOffset>29</bitOffset> 35245 <bitWidth>2</bitWidth> 35246 </field> 35247 </fields> 35248 </register> 35249 <register> 35250 <name>HCTSIZ2</name> 35251 <displayName>HCTSIZ2</displayName> 35252 <description>OTG_HS host channel-2 transfer size 35253 register</description> 35254 <addressOffset>0x150</addressOffset> 35255 <size>32</size> 35256 <access>read-write</access> 35257 <resetValue>0x0</resetValue> 35258 <fields> 35259 <field> 35260 <name>XFRSIZ</name> 35261 <description>Transfer size</description> 35262 <bitOffset>0</bitOffset> 35263 <bitWidth>19</bitWidth> 35264 </field> 35265 <field> 35266 <name>PKTCNT</name> 35267 <description>Packet count</description> 35268 <bitOffset>19</bitOffset> 35269 <bitWidth>10</bitWidth> 35270 </field> 35271 <field> 35272 <name>DPID</name> 35273 <description>Data PID</description> 35274 <bitOffset>29</bitOffset> 35275 <bitWidth>2</bitWidth> 35276 </field> 35277 </fields> 35278 </register> 35279 <register> 35280 <name>HCTSIZ3</name> 35281 <displayName>HCTSIZ3</displayName> 35282 <description>OTG_HS host channel-3 transfer size 35283 register</description> 35284 <addressOffset>0x170</addressOffset> 35285 <size>32</size> 35286 <access>read-write</access> 35287 <resetValue>0x0</resetValue> 35288 <fields> 35289 <field> 35290 <name>XFRSIZ</name> 35291 <description>Transfer size</description> 35292 <bitOffset>0</bitOffset> 35293 <bitWidth>19</bitWidth> 35294 </field> 35295 <field> 35296 <name>PKTCNT</name> 35297 <description>Packet count</description> 35298 <bitOffset>19</bitOffset> 35299 <bitWidth>10</bitWidth> 35300 </field> 35301 <field> 35302 <name>DPID</name> 35303 <description>Data PID</description> 35304 <bitOffset>29</bitOffset> 35305 <bitWidth>2</bitWidth> 35306 </field> 35307 </fields> 35308 </register> 35309 <register> 35310 <name>HCTSIZ4</name> 35311 <displayName>HCTSIZ4</displayName> 35312 <description>OTG_HS host channel-4 transfer size 35313 register</description> 35314 <addressOffset>0x190</addressOffset> 35315 <size>32</size> 35316 <access>read-write</access> 35317 <resetValue>0x0</resetValue> 35318 <fields> 35319 <field> 35320 <name>XFRSIZ</name> 35321 <description>Transfer size</description> 35322 <bitOffset>0</bitOffset> 35323 <bitWidth>19</bitWidth> 35324 </field> 35325 <field> 35326 <name>PKTCNT</name> 35327 <description>Packet count</description> 35328 <bitOffset>19</bitOffset> 35329 <bitWidth>10</bitWidth> 35330 </field> 35331 <field> 35332 <name>DPID</name> 35333 <description>Data PID</description> 35334 <bitOffset>29</bitOffset> 35335 <bitWidth>2</bitWidth> 35336 </field> 35337 </fields> 35338 </register> 35339 <register> 35340 <name>HCTSIZ5</name> 35341 <displayName>HCTSIZ5</displayName> 35342 <description>OTG_HS host channel-5 transfer size 35343 register</description> 35344 <addressOffset>0x1B0</addressOffset> 35345 <size>32</size> 35346 <access>read-write</access> 35347 <resetValue>0x0</resetValue> 35348 <fields> 35349 <field> 35350 <name>XFRSIZ</name> 35351 <description>Transfer size</description> 35352 <bitOffset>0</bitOffset> 35353 <bitWidth>19</bitWidth> 35354 </field> 35355 <field> 35356 <name>PKTCNT</name> 35357 <description>Packet count</description> 35358 <bitOffset>19</bitOffset> 35359 <bitWidth>10</bitWidth> 35360 </field> 35361 <field> 35362 <name>DPID</name> 35363 <description>Data PID</description> 35364 <bitOffset>29</bitOffset> 35365 <bitWidth>2</bitWidth> 35366 </field> 35367 </fields> 35368 </register> 35369 <register> 35370 <name>HCTSIZ6</name> 35371 <displayName>HCTSIZ6</displayName> 35372 <description>OTG_HS host channel-6 transfer size 35373 register</description> 35374 <addressOffset>0x1D0</addressOffset> 35375 <size>32</size> 35376 <access>read-write</access> 35377 <resetValue>0x0</resetValue> 35378 <fields> 35379 <field> 35380 <name>XFRSIZ</name> 35381 <description>Transfer size</description> 35382 <bitOffset>0</bitOffset> 35383 <bitWidth>19</bitWidth> 35384 </field> 35385 <field> 35386 <name>PKTCNT</name> 35387 <description>Packet count</description> 35388 <bitOffset>19</bitOffset> 35389 <bitWidth>10</bitWidth> 35390 </field> 35391 <field> 35392 <name>DPID</name> 35393 <description>Data PID</description> 35394 <bitOffset>29</bitOffset> 35395 <bitWidth>2</bitWidth> 35396 </field> 35397 </fields> 35398 </register> 35399 <register> 35400 <name>HCTSIZ7</name> 35401 <displayName>HCTSIZ7</displayName> 35402 <description>OTG_HS host channel-7 transfer size 35403 register</description> 35404 <addressOffset>0x1F0</addressOffset> 35405 <size>32</size> 35406 <access>read-write</access> 35407 <resetValue>0x0</resetValue> 35408 <fields> 35409 <field> 35410 <name>XFRSIZ</name> 35411 <description>Transfer size</description> 35412 <bitOffset>0</bitOffset> 35413 <bitWidth>19</bitWidth> 35414 </field> 35415 <field> 35416 <name>PKTCNT</name> 35417 <description>Packet count</description> 35418 <bitOffset>19</bitOffset> 35419 <bitWidth>10</bitWidth> 35420 </field> 35421 <field> 35422 <name>DPID</name> 35423 <description>Data PID</description> 35424 <bitOffset>29</bitOffset> 35425 <bitWidth>2</bitWidth> 35426 </field> 35427 </fields> 35428 </register> 35429 <register> 35430 <name>HCTSIZ8</name> 35431 <displayName>HCTSIZ8</displayName> 35432 <description>OTG_HS host channel-8 transfer size 35433 register</description> 35434 <addressOffset>0x210</addressOffset> 35435 <size>32</size> 35436 <access>read-write</access> 35437 <resetValue>0x0</resetValue> 35438 <fields> 35439 <field> 35440 <name>XFRSIZ</name> 35441 <description>Transfer size</description> 35442 <bitOffset>0</bitOffset> 35443 <bitWidth>19</bitWidth> 35444 </field> 35445 <field> 35446 <name>PKTCNT</name> 35447 <description>Packet count</description> 35448 <bitOffset>19</bitOffset> 35449 <bitWidth>10</bitWidth> 35450 </field> 35451 <field> 35452 <name>DPID</name> 35453 <description>Data PID</description> 35454 <bitOffset>29</bitOffset> 35455 <bitWidth>2</bitWidth> 35456 </field> 35457 </fields> 35458 </register> 35459 <register> 35460 <name>HCTSIZ9</name> 35461 <displayName>HCTSIZ9</displayName> 35462 <description>OTG_HS host channel-9 transfer size 35463 register</description> 35464 <addressOffset>0x230</addressOffset> 35465 <size>32</size> 35466 <access>read-write</access> 35467 <resetValue>0x0</resetValue> 35468 <fields> 35469 <field> 35470 <name>XFRSIZ</name> 35471 <description>Transfer size</description> 35472 <bitOffset>0</bitOffset> 35473 <bitWidth>19</bitWidth> 35474 </field> 35475 <field> 35476 <name>PKTCNT</name> 35477 <description>Packet count</description> 35478 <bitOffset>19</bitOffset> 35479 <bitWidth>10</bitWidth> 35480 </field> 35481 <field> 35482 <name>DPID</name> 35483 <description>Data PID</description> 35484 <bitOffset>29</bitOffset> 35485 <bitWidth>2</bitWidth> 35486 </field> 35487 </fields> 35488 </register> 35489 <register> 35490 <name>HCTSIZ10</name> 35491 <displayName>HCTSIZ10</displayName> 35492 <description>OTG_HS host channel-10 transfer size 35493 register</description> 35494 <addressOffset>0x250</addressOffset> 35495 <size>32</size> 35496 <access>read-write</access> 35497 <resetValue>0x0</resetValue> 35498 <fields> 35499 <field> 35500 <name>XFRSIZ</name> 35501 <description>Transfer size</description> 35502 <bitOffset>0</bitOffset> 35503 <bitWidth>19</bitWidth> 35504 </field> 35505 <field> 35506 <name>PKTCNT</name> 35507 <description>Packet count</description> 35508 <bitOffset>19</bitOffset> 35509 <bitWidth>10</bitWidth> 35510 </field> 35511 <field> 35512 <name>DPID</name> 35513 <description>Data PID</description> 35514 <bitOffset>29</bitOffset> 35515 <bitWidth>2</bitWidth> 35516 </field> 35517 </fields> 35518 </register> 35519 <register> 35520 <name>HCTSIZ11</name> 35521 <displayName>HCTSIZ11</displayName> 35522 <description>OTG_HS host channel-11 transfer size 35523 register</description> 35524 <addressOffset>0x270</addressOffset> 35525 <size>32</size> 35526 <access>read-write</access> 35527 <resetValue>0x0</resetValue> 35528 <fields> 35529 <field> 35530 <name>XFRSIZ</name> 35531 <description>Transfer size</description> 35532 <bitOffset>0</bitOffset> 35533 <bitWidth>19</bitWidth> 35534 </field> 35535 <field> 35536 <name>PKTCNT</name> 35537 <description>Packet count</description> 35538 <bitOffset>19</bitOffset> 35539 <bitWidth>10</bitWidth> 35540 </field> 35541 <field> 35542 <name>DPID</name> 35543 <description>Data PID</description> 35544 <bitOffset>29</bitOffset> 35545 <bitWidth>2</bitWidth> 35546 </field> 35547 </fields> 35548 </register> 35549 <register> 35550 <name>HCDMA0</name> 35551 <displayName>HCDMA0</displayName> 35552 <description>OTG_HS host channel-0 DMA address 35553 register</description> 35554 <addressOffset>0x114</addressOffset> 35555 <size>32</size> 35556 <access>read-write</access> 35557 <resetValue>0x0</resetValue> 35558 <fields> 35559 <field> 35560 <name>DMAADDR</name> 35561 <description>DMA address</description> 35562 <bitOffset>0</bitOffset> 35563 <bitWidth>32</bitWidth> 35564 </field> 35565 </fields> 35566 </register> 35567 <register> 35568 <name>HCDMA1</name> 35569 <displayName>HCDMA1</displayName> 35570 <description>OTG_HS host channel-1 DMA address 35571 register</description> 35572 <addressOffset>0x134</addressOffset> 35573 <size>32</size> 35574 <access>read-write</access> 35575 <resetValue>0x0</resetValue> 35576 <fields> 35577 <field> 35578 <name>DMAADDR</name> 35579 <description>DMA address</description> 35580 <bitOffset>0</bitOffset> 35581 <bitWidth>32</bitWidth> 35582 </field> 35583 </fields> 35584 </register> 35585 <register> 35586 <name>HCDMA2</name> 35587 <displayName>HCDMA2</displayName> 35588 <description>OTG_HS host channel-2 DMA address 35589 register</description> 35590 <addressOffset>0x154</addressOffset> 35591 <size>32</size> 35592 <access>read-write</access> 35593 <resetValue>0x0</resetValue> 35594 <fields> 35595 <field> 35596 <name>DMAADDR</name> 35597 <description>DMA address</description> 35598 <bitOffset>0</bitOffset> 35599 <bitWidth>32</bitWidth> 35600 </field> 35601 </fields> 35602 </register> 35603 <register> 35604 <name>HCDMA3</name> 35605 <displayName>HCDMA3</displayName> 35606 <description>OTG_HS host channel-3 DMA address 35607 register</description> 35608 <addressOffset>0x174</addressOffset> 35609 <size>32</size> 35610 <access>read-write</access> 35611 <resetValue>0x0</resetValue> 35612 <fields> 35613 <field> 35614 <name>DMAADDR</name> 35615 <description>DMA address</description> 35616 <bitOffset>0</bitOffset> 35617 <bitWidth>32</bitWidth> 35618 </field> 35619 </fields> 35620 </register> 35621 <register> 35622 <name>HCDMA4</name> 35623 <displayName>HCDMA4</displayName> 35624 <description>OTG_HS host channel-4 DMA address 35625 register</description> 35626 <addressOffset>0x194</addressOffset> 35627 <size>32</size> 35628 <access>read-write</access> 35629 <resetValue>0x0</resetValue> 35630 <fields> 35631 <field> 35632 <name>DMAADDR</name> 35633 <description>DMA address</description> 35634 <bitOffset>0</bitOffset> 35635 <bitWidth>32</bitWidth> 35636 </field> 35637 </fields> 35638 </register> 35639 <register> 35640 <name>HCDMA5</name> 35641 <displayName>HCDMA5</displayName> 35642 <description>OTG_HS host channel-5 DMA address 35643 register</description> 35644 <addressOffset>0x1B4</addressOffset> 35645 <size>32</size> 35646 <access>read-write</access> 35647 <resetValue>0x0</resetValue> 35648 <fields> 35649 <field> 35650 <name>DMAADDR</name> 35651 <description>DMA address</description> 35652 <bitOffset>0</bitOffset> 35653 <bitWidth>32</bitWidth> 35654 </field> 35655 </fields> 35656 </register> 35657 <register> 35658 <name>HCDMA6</name> 35659 <displayName>HCDMA6</displayName> 35660 <description>OTG_HS host channel-6 DMA address 35661 register</description> 35662 <addressOffset>0x1D4</addressOffset> 35663 <size>32</size> 35664 <access>read-write</access> 35665 <resetValue>0x0</resetValue> 35666 <fields> 35667 <field> 35668 <name>DMAADDR</name> 35669 <description>DMA address</description> 35670 <bitOffset>0</bitOffset> 35671 <bitWidth>32</bitWidth> 35672 </field> 35673 </fields> 35674 </register> 35675 <register> 35676 <name>HCDMA7</name> 35677 <displayName>HCDMA7</displayName> 35678 <description>OTG_HS host channel-7 DMA address 35679 register</description> 35680 <addressOffset>0x1F4</addressOffset> 35681 <size>32</size> 35682 <access>read-write</access> 35683 <resetValue>0x0</resetValue> 35684 <fields> 35685 <field> 35686 <name>DMAADDR</name> 35687 <description>DMA address</description> 35688 <bitOffset>0</bitOffset> 35689 <bitWidth>32</bitWidth> 35690 </field> 35691 </fields> 35692 </register> 35693 <register> 35694 <name>HCDMA8</name> 35695 <displayName>HCDMA8</displayName> 35696 <description>OTG_HS host channel-8 DMA address 35697 register</description> 35698 <addressOffset>0x214</addressOffset> 35699 <size>32</size> 35700 <access>read-write</access> 35701 <resetValue>0x0</resetValue> 35702 <fields> 35703 <field> 35704 <name>DMAADDR</name> 35705 <description>DMA address</description> 35706 <bitOffset>0</bitOffset> 35707 <bitWidth>32</bitWidth> 35708 </field> 35709 </fields> 35710 </register> 35711 <register> 35712 <name>HCDMA9</name> 35713 <displayName>HCDMA9</displayName> 35714 <description>OTG_HS host channel-9 DMA address 35715 register</description> 35716 <addressOffset>0x234</addressOffset> 35717 <size>32</size> 35718 <access>read-write</access> 35719 <resetValue>0x0</resetValue> 35720 <fields> 35721 <field> 35722 <name>DMAADDR</name> 35723 <description>DMA address</description> 35724 <bitOffset>0</bitOffset> 35725 <bitWidth>32</bitWidth> 35726 </field> 35727 </fields> 35728 </register> 35729 <register> 35730 <name>HCDMA10</name> 35731 <displayName>HCDMA10</displayName> 35732 <description>OTG_HS host channel-10 DMA address 35733 register</description> 35734 <addressOffset>0x254</addressOffset> 35735 <size>32</size> 35736 <access>read-write</access> 35737 <resetValue>0x0</resetValue> 35738 <fields> 35739 <field> 35740 <name>DMAADDR</name> 35741 <description>DMA address</description> 35742 <bitOffset>0</bitOffset> 35743 <bitWidth>32</bitWidth> 35744 </field> 35745 </fields> 35746 </register> 35747 <register> 35748 <name>HCDMA11</name> 35749 <displayName>HCDMA11</displayName> 35750 <description>OTG_HS host channel-11 DMA address 35751 register</description> 35752 <addressOffset>0x274</addressOffset> 35753 <size>32</size> 35754 <access>read-write</access> 35755 <resetValue>0x0</resetValue> 35756 <fields> 35757 <field> 35758 <name>DMAADDR</name> 35759 <description>DMA address</description> 35760 <bitOffset>0</bitOffset> 35761 <bitWidth>32</bitWidth> 35762 </field> 35763 </fields> 35764 </register> 35765 </registers> 35766 </peripheral> 35767 <peripheral> 35768 <name>OTG_HS_DEVICE</name> 35769 <description>USB on the go high speed</description> 35770 <groupName>USB_OTG_HS</groupName> 35771 <baseAddress>0x40040800</baseAddress> 35772 <addressBlock> 35773 <offset>0x0</offset> 35774 <size>0x400</size> 35775 <usage>registers</usage> 35776 </addressBlock> 35777 <registers> 35778 <register> 35779 <name>DCFG</name> 35780 <displayName>DCFG</displayName> 35781 <description>OTG_HS device configuration 35782 register</description> 35783 <addressOffset>0x0</addressOffset> 35784 <size>32</size> 35785 <access>read-write</access> 35786 <resetValue>0x02200000</resetValue> 35787 <fields> 35788 <field> 35789 <name>DSPD</name> 35790 <description>Device speed</description> 35791 <bitOffset>0</bitOffset> 35792 <bitWidth>2</bitWidth> 35793 </field> 35794 <field> 35795 <name>NZLSOHSK</name> 35796 <description>Nonzero-length status OUT 35797 handshake</description> 35798 <bitOffset>2</bitOffset> 35799 <bitWidth>1</bitWidth> 35800 </field> 35801 <field> 35802 <name>DAD</name> 35803 <description>Device address</description> 35804 <bitOffset>4</bitOffset> 35805 <bitWidth>7</bitWidth> 35806 </field> 35807 <field> 35808 <name>PFIVL</name> 35809 <description>Periodic (micro)frame 35810 interval</description> 35811 <bitOffset>11</bitOffset> 35812 <bitWidth>2</bitWidth> 35813 </field> 35814 <field> 35815 <name>PERSCHIVL</name> 35816 <description>Periodic scheduling 35817 interval</description> 35818 <bitOffset>24</bitOffset> 35819 <bitWidth>2</bitWidth> 35820 </field> 35821 </fields> 35822 </register> 35823 <register> 35824 <name>DCTL</name> 35825 <displayName>DCTL</displayName> 35826 <description>OTG_HS device control register</description> 35827 <addressOffset>0x4</addressOffset> 35828 <size>32</size> 35829 <resetValue>0x0</resetValue> 35830 <fields> 35831 <field> 35832 <name>RWUSIG</name> 35833 <description>Remote wakeup signaling</description> 35834 <bitOffset>0</bitOffset> 35835 <bitWidth>1</bitWidth> 35836 <access>read-write</access> 35837 </field> 35838 <field> 35839 <name>SDIS</name> 35840 <description>Soft disconnect</description> 35841 <bitOffset>1</bitOffset> 35842 <bitWidth>1</bitWidth> 35843 <access>read-write</access> 35844 </field> 35845 <field> 35846 <name>GINSTS</name> 35847 <description>Global IN NAK status</description> 35848 <bitOffset>2</bitOffset> 35849 <bitWidth>1</bitWidth> 35850 <access>read-only</access> 35851 </field> 35852 <field> 35853 <name>GONSTS</name> 35854 <description>Global OUT NAK status</description> 35855 <bitOffset>3</bitOffset> 35856 <bitWidth>1</bitWidth> 35857 <access>read-only</access> 35858 </field> 35859 <field> 35860 <name>TCTL</name> 35861 <description>Test control</description> 35862 <bitOffset>4</bitOffset> 35863 <bitWidth>3</bitWidth> 35864 <access>read-write</access> 35865 </field> 35866 <field> 35867 <name>SGINAK</name> 35868 <description>Set global IN NAK</description> 35869 <bitOffset>7</bitOffset> 35870 <bitWidth>1</bitWidth> 35871 <access>write-only</access> 35872 </field> 35873 <field> 35874 <name>CGINAK</name> 35875 <description>Clear global IN NAK</description> 35876 <bitOffset>8</bitOffset> 35877 <bitWidth>1</bitWidth> 35878 <access>write-only</access> 35879 </field> 35880 <field> 35881 <name>SGONAK</name> 35882 <description>Set global OUT NAK</description> 35883 <bitOffset>9</bitOffset> 35884 <bitWidth>1</bitWidth> 35885 <access>write-only</access> 35886 </field> 35887 <field> 35888 <name>CGONAK</name> 35889 <description>Clear global OUT NAK</description> 35890 <bitOffset>10</bitOffset> 35891 <bitWidth>1</bitWidth> 35892 <access>write-only</access> 35893 </field> 35894 <field> 35895 <name>POPRGDNE</name> 35896 <description>Power-on programming done</description> 35897 <bitOffset>11</bitOffset> 35898 <bitWidth>1</bitWidth> 35899 <access>read-write</access> 35900 </field> 35901 </fields> 35902 </register> 35903 <register> 35904 <name>DSTS</name> 35905 <displayName>DSTS</displayName> 35906 <description>OTG_HS device status register</description> 35907 <addressOffset>0x8</addressOffset> 35908 <size>32</size> 35909 <access>read-only</access> 35910 <resetValue>0x00000010</resetValue> 35911 <fields> 35912 <field> 35913 <name>SUSPSTS</name> 35914 <description>Suspend status</description> 35915 <bitOffset>0</bitOffset> 35916 <bitWidth>1</bitWidth> 35917 </field> 35918 <field> 35919 <name>ENUMSPD</name> 35920 <description>Enumerated speed</description> 35921 <bitOffset>1</bitOffset> 35922 <bitWidth>2</bitWidth> 35923 </field> 35924 <field> 35925 <name>EERR</name> 35926 <description>Erratic error</description> 35927 <bitOffset>3</bitOffset> 35928 <bitWidth>1</bitWidth> 35929 </field> 35930 <field> 35931 <name>FNSOF</name> 35932 <description>Frame number of the received 35933 SOF</description> 35934 <bitOffset>8</bitOffset> 35935 <bitWidth>14</bitWidth> 35936 </field> 35937 </fields> 35938 </register> 35939 <register> 35940 <name>DIEPMSK</name> 35941 <displayName>DIEPMSK</displayName> 35942 <description>OTG_HS device IN endpoint common interrupt 35943 mask register</description> 35944 <addressOffset>0x10</addressOffset> 35945 <size>32</size> 35946 <access>read-write</access> 35947 <resetValue>0x0</resetValue> 35948 <fields> 35949 <field> 35950 <name>XFRCM</name> 35951 <description>Transfer completed interrupt 35952 mask</description> 35953 <bitOffset>0</bitOffset> 35954 <bitWidth>1</bitWidth> 35955 </field> 35956 <field> 35957 <name>EPDM</name> 35958 <description>Endpoint disabled interrupt 35959 mask</description> 35960 <bitOffset>1</bitOffset> 35961 <bitWidth>1</bitWidth> 35962 </field> 35963 <field> 35964 <name>TOM</name> 35965 <description>Timeout condition mask (nonisochronous 35966 endpoints)</description> 35967 <bitOffset>3</bitOffset> 35968 <bitWidth>1</bitWidth> 35969 </field> 35970 <field> 35971 <name>ITTXFEMSK</name> 35972 <description>IN token received when TxFIFO empty 35973 mask</description> 35974 <bitOffset>4</bitOffset> 35975 <bitWidth>1</bitWidth> 35976 </field> 35977 <field> 35978 <name>INEPNMM</name> 35979 <description>IN token received with EP mismatch 35980 mask</description> 35981 <bitOffset>5</bitOffset> 35982 <bitWidth>1</bitWidth> 35983 </field> 35984 <field> 35985 <name>INEPNEM</name> 35986 <description>IN endpoint NAK effective 35987 mask</description> 35988 <bitOffset>6</bitOffset> 35989 <bitWidth>1</bitWidth> 35990 </field> 35991 <field> 35992 <name>TXFURM</name> 35993 <description>FIFO underrun mask</description> 35994 <bitOffset>8</bitOffset> 35995 <bitWidth>1</bitWidth> 35996 </field> 35997 <field> 35998 <name>BIM</name> 35999 <description>BNA interrupt mask</description> 36000 <bitOffset>9</bitOffset> 36001 <bitWidth>1</bitWidth> 36002 </field> 36003 </fields> 36004 </register> 36005 <register> 36006 <name>DOEPMSK</name> 36007 <displayName>DOEPMSK</displayName> 36008 <description>OTG_HS device OUT endpoint common interrupt 36009 mask register</description> 36010 <addressOffset>0x14</addressOffset> 36011 <size>32</size> 36012 <access>read-write</access> 36013 <resetValue>0x0</resetValue> 36014 <fields> 36015 <field> 36016 <name>XFRCM</name> 36017 <description>Transfer completed interrupt 36018 mask</description> 36019 <bitOffset>0</bitOffset> 36020 <bitWidth>1</bitWidth> 36021 </field> 36022 <field> 36023 <name>EPDM</name> 36024 <description>Endpoint disabled interrupt 36025 mask</description> 36026 <bitOffset>1</bitOffset> 36027 <bitWidth>1</bitWidth> 36028 </field> 36029 <field> 36030 <name>STUPM</name> 36031 <description>SETUP phase done mask</description> 36032 <bitOffset>3</bitOffset> 36033 <bitWidth>1</bitWidth> 36034 </field> 36035 <field> 36036 <name>OTEPDM</name> 36037 <description>OUT token received when endpoint 36038 disabled mask</description> 36039 <bitOffset>4</bitOffset> 36040 <bitWidth>1</bitWidth> 36041 </field> 36042 <field> 36043 <name>B2BSTUP</name> 36044 <description>Back-to-back SETUP packets received 36045 mask</description> 36046 <bitOffset>6</bitOffset> 36047 <bitWidth>1</bitWidth> 36048 </field> 36049 <field> 36050 <name>OPEM</name> 36051 <description>OUT packet error mask</description> 36052 <bitOffset>8</bitOffset> 36053 <bitWidth>1</bitWidth> 36054 </field> 36055 <field> 36056 <name>BOIM</name> 36057 <description>BNA interrupt mask</description> 36058 <bitOffset>9</bitOffset> 36059 <bitWidth>1</bitWidth> 36060 </field> 36061 </fields> 36062 </register> 36063 <register> 36064 <name>DAINT</name> 36065 <displayName>DAINT</displayName> 36066 <description>OTG_HS device all endpoints interrupt 36067 register</description> 36068 <addressOffset>0x18</addressOffset> 36069 <size>32</size> 36070 <access>read-only</access> 36071 <resetValue>0x0</resetValue> 36072 <fields> 36073 <field> 36074 <name>IEPINT</name> 36075 <description>IN endpoint interrupt bits</description> 36076 <bitOffset>0</bitOffset> 36077 <bitWidth>16</bitWidth> 36078 </field> 36079 <field> 36080 <name>OEPINT</name> 36081 <description>OUT endpoint interrupt 36082 bits</description> 36083 <bitOffset>16</bitOffset> 36084 <bitWidth>16</bitWidth> 36085 </field> 36086 </fields> 36087 </register> 36088 <register> 36089 <name>DAINTMSK</name> 36090 <displayName>DAINTMSK</displayName> 36091 <description>OTG_HS all endpoints interrupt mask 36092 register</description> 36093 <addressOffset>0x1C</addressOffset> 36094 <size>32</size> 36095 <access>read-write</access> 36096 <resetValue>0x0</resetValue> 36097 <fields> 36098 <field> 36099 <name>IEPM</name> 36100 <description>IN EP interrupt mask bits</description> 36101 <bitOffset>0</bitOffset> 36102 <bitWidth>16</bitWidth> 36103 </field> 36104 <field> 36105 <name>OEPM</name> 36106 <description>OUT EP interrupt mask bits</description> 36107 <bitOffset>16</bitOffset> 36108 <bitWidth>16</bitWidth> 36109 </field> 36110 </fields> 36111 </register> 36112 <register> 36113 <name>DVBUSDIS</name> 36114 <displayName>DVBUSDIS</displayName> 36115 <description>OTG_HS device VBUS discharge time 36116 register</description> 36117 <addressOffset>0x28</addressOffset> 36118 <size>32</size> 36119 <access>read-write</access> 36120 <resetValue>0x000017D7</resetValue> 36121 <fields> 36122 <field> 36123 <name>VBUSDT</name> 36124 <description>Device VBUS discharge time</description> 36125 <bitOffset>0</bitOffset> 36126 <bitWidth>16</bitWidth> 36127 </field> 36128 </fields> 36129 </register> 36130 <register> 36131 <name>DVBUSPULSE</name> 36132 <displayName>DVBUSPULSE</displayName> 36133 <description>OTG_HS device VBUS pulsing time 36134 register</description> 36135 <addressOffset>0x2C</addressOffset> 36136 <size>32</size> 36137 <access>read-write</access> 36138 <resetValue>0x000005B8</resetValue> 36139 <fields> 36140 <field> 36141 <name>DVBUSP</name> 36142 <description>Device VBUS pulsing time</description> 36143 <bitOffset>0</bitOffset> 36144 <bitWidth>12</bitWidth> 36145 </field> 36146 </fields> 36147 </register> 36148 <register> 36149 <name>DTHRCTL</name> 36150 <displayName>DTHRCTL</displayName> 36151 <description>OTG_HS Device threshold control 36152 register</description> 36153 <addressOffset>0x30</addressOffset> 36154 <size>32</size> 36155 <access>read-write</access> 36156 <resetValue>0x0</resetValue> 36157 <fields> 36158 <field> 36159 <name>NONISOTHREN</name> 36160 <description>Nonisochronous IN endpoints threshold 36161 enable</description> 36162 <bitOffset>0</bitOffset> 36163 <bitWidth>1</bitWidth> 36164 </field> 36165 <field> 36166 <name>ISOTHREN</name> 36167 <description>ISO IN endpoint threshold 36168 enable</description> 36169 <bitOffset>1</bitOffset> 36170 <bitWidth>1</bitWidth> 36171 </field> 36172 <field> 36173 <name>TXTHRLEN</name> 36174 <description>Transmit threshold length</description> 36175 <bitOffset>2</bitOffset> 36176 <bitWidth>9</bitWidth> 36177 </field> 36178 <field> 36179 <name>RXTHREN</name> 36180 <description>Receive threshold enable</description> 36181 <bitOffset>16</bitOffset> 36182 <bitWidth>1</bitWidth> 36183 </field> 36184 <field> 36185 <name>RXTHRLEN</name> 36186 <description>Receive threshold length</description> 36187 <bitOffset>17</bitOffset> 36188 <bitWidth>9</bitWidth> 36189 </field> 36190 <field> 36191 <name>ARPEN</name> 36192 <description>Arbiter parking enable</description> 36193 <bitOffset>27</bitOffset> 36194 <bitWidth>1</bitWidth> 36195 </field> 36196 </fields> 36197 </register> 36198 <register> 36199 <name>DIEPEMPMSK</name> 36200 <displayName>DIEPEMPMSK</displayName> 36201 <description>OTG_HS device IN endpoint FIFO empty 36202 interrupt mask register</description> 36203 <addressOffset>0x34</addressOffset> 36204 <size>32</size> 36205 <access>read-write</access> 36206 <resetValue>0x0</resetValue> 36207 <fields> 36208 <field> 36209 <name>INEPTXFEM</name> 36210 <description>IN EP Tx FIFO empty interrupt mask 36211 bits</description> 36212 <bitOffset>0</bitOffset> 36213 <bitWidth>16</bitWidth> 36214 </field> 36215 </fields> 36216 </register> 36217 <register> 36218 <name>DEACHINT</name> 36219 <displayName>DEACHINT</displayName> 36220 <description>OTG_HS device each endpoint interrupt 36221 register</description> 36222 <addressOffset>0x38</addressOffset> 36223 <size>32</size> 36224 <access>read-write</access> 36225 <resetValue>0x0</resetValue> 36226 <fields> 36227 <field> 36228 <name>IEP1INT</name> 36229 <description>IN endpoint 1interrupt bit</description> 36230 <bitOffset>1</bitOffset> 36231 <bitWidth>1</bitWidth> 36232 </field> 36233 <field> 36234 <name>OEP1INT</name> 36235 <description>OUT endpoint 1 interrupt 36236 bit</description> 36237 <bitOffset>17</bitOffset> 36238 <bitWidth>1</bitWidth> 36239 </field> 36240 </fields> 36241 </register> 36242 <register> 36243 <name>DEACHINTMSK</name> 36244 <displayName>DEACHINTMSK</displayName> 36245 <description>OTG_HS device each endpoint interrupt 36246 register mask</description> 36247 <addressOffset>0x3C</addressOffset> 36248 <size>32</size> 36249 <access>read-write</access> 36250 <resetValue>0x0</resetValue> 36251 <fields> 36252 <field> 36253 <name>IEP1INTM</name> 36254 <description>IN Endpoint 1 interrupt mask 36255 bit</description> 36256 <bitOffset>1</bitOffset> 36257 <bitWidth>1</bitWidth> 36258 </field> 36259 <field> 36260 <name>OEP1INTM</name> 36261 <description>OUT Endpoint 1 interrupt mask 36262 bit</description> 36263 <bitOffset>17</bitOffset> 36264 <bitWidth>1</bitWidth> 36265 </field> 36266 </fields> 36267 </register> 36268 <register> 36269 <name>DIEPEACHMSK1</name> 36270 <displayName>DIEPEACHMSK1</displayName> 36271 <description>OTG_HS device each in endpoint-1 interrupt 36272 register</description> 36273 <addressOffset>0x40</addressOffset> 36274 <size>32</size> 36275 <access>read-write</access> 36276 <resetValue>0x0</resetValue> 36277 <fields> 36278 <field> 36279 <name>XFRCM</name> 36280 <description>Transfer completed interrupt 36281 mask</description> 36282 <bitOffset>0</bitOffset> 36283 <bitWidth>1</bitWidth> 36284 </field> 36285 <field> 36286 <name>EPDM</name> 36287 <description>Endpoint disabled interrupt 36288 mask</description> 36289 <bitOffset>1</bitOffset> 36290 <bitWidth>1</bitWidth> 36291 </field> 36292 <field> 36293 <name>TOM</name> 36294 <description>Timeout condition mask (nonisochronous 36295 endpoints)</description> 36296 <bitOffset>3</bitOffset> 36297 <bitWidth>1</bitWidth> 36298 </field> 36299 <field> 36300 <name>ITTXFEMSK</name> 36301 <description>IN token received when TxFIFO empty 36302 mask</description> 36303 <bitOffset>4</bitOffset> 36304 <bitWidth>1</bitWidth> 36305 </field> 36306 <field> 36307 <name>INEPNMM</name> 36308 <description>IN token received with EP mismatch 36309 mask</description> 36310 <bitOffset>5</bitOffset> 36311 <bitWidth>1</bitWidth> 36312 </field> 36313 <field> 36314 <name>INEPNEM</name> 36315 <description>IN endpoint NAK effective 36316 mask</description> 36317 <bitOffset>6</bitOffset> 36318 <bitWidth>1</bitWidth> 36319 </field> 36320 <field> 36321 <name>TXFURM</name> 36322 <description>FIFO underrun mask</description> 36323 <bitOffset>8</bitOffset> 36324 <bitWidth>1</bitWidth> 36325 </field> 36326 <field> 36327 <name>BIM</name> 36328 <description>BNA interrupt mask</description> 36329 <bitOffset>9</bitOffset> 36330 <bitWidth>1</bitWidth> 36331 </field> 36332 <field> 36333 <name>NAKM</name> 36334 <description>NAK interrupt mask</description> 36335 <bitOffset>13</bitOffset> 36336 <bitWidth>1</bitWidth> 36337 </field> 36338 </fields> 36339 </register> 36340 <register> 36341 <name>DOEPEACHMSK1</name> 36342 <displayName>DOEPEACHMSK1</displayName> 36343 <description>OTG_HS device each OUT endpoint-1 interrupt 36344 register</description> 36345 <addressOffset>0x80</addressOffset> 36346 <size>32</size> 36347 <access>read-write</access> 36348 <resetValue>0x0</resetValue> 36349 <fields> 36350 <field> 36351 <name>XFRCM</name> 36352 <description>Transfer completed interrupt 36353 mask</description> 36354 <bitOffset>0</bitOffset> 36355 <bitWidth>1</bitWidth> 36356 </field> 36357 <field> 36358 <name>EPDM</name> 36359 <description>Endpoint disabled interrupt 36360 mask</description> 36361 <bitOffset>1</bitOffset> 36362 <bitWidth>1</bitWidth> 36363 </field> 36364 <field> 36365 <name>TOM</name> 36366 <description>Timeout condition mask</description> 36367 <bitOffset>3</bitOffset> 36368 <bitWidth>1</bitWidth> 36369 </field> 36370 <field> 36371 <name>ITTXFEMSK</name> 36372 <description>IN token received when TxFIFO empty 36373 mask</description> 36374 <bitOffset>4</bitOffset> 36375 <bitWidth>1</bitWidth> 36376 </field> 36377 <field> 36378 <name>INEPNMM</name> 36379 <description>IN token received with EP mismatch 36380 mask</description> 36381 <bitOffset>5</bitOffset> 36382 <bitWidth>1</bitWidth> 36383 </field> 36384 <field> 36385 <name>INEPNEM</name> 36386 <description>IN endpoint NAK effective 36387 mask</description> 36388 <bitOffset>6</bitOffset> 36389 <bitWidth>1</bitWidth> 36390 </field> 36391 <field> 36392 <name>TXFURM</name> 36393 <description>OUT packet error mask</description> 36394 <bitOffset>8</bitOffset> 36395 <bitWidth>1</bitWidth> 36396 </field> 36397 <field> 36398 <name>BIM</name> 36399 <description>BNA interrupt mask</description> 36400 <bitOffset>9</bitOffset> 36401 <bitWidth>1</bitWidth> 36402 </field> 36403 <field> 36404 <name>BERRM</name> 36405 <description>Bubble error interrupt 36406 mask</description> 36407 <bitOffset>12</bitOffset> 36408 <bitWidth>1</bitWidth> 36409 </field> 36410 <field> 36411 <name>NAKM</name> 36412 <description>NAK interrupt mask</description> 36413 <bitOffset>13</bitOffset> 36414 <bitWidth>1</bitWidth> 36415 </field> 36416 <field> 36417 <name>NYETM</name> 36418 <description>NYET interrupt mask</description> 36419 <bitOffset>14</bitOffset> 36420 <bitWidth>1</bitWidth> 36421 </field> 36422 </fields> 36423 </register> 36424 <register> 36425 <name>DIEPCTL0</name> 36426 <displayName>DIEPCTL0</displayName> 36427 <description>OTG device endpoint-0 control 36428 register</description> 36429 <addressOffset>0x100</addressOffset> 36430 <size>32</size> 36431 <resetValue>0x0</resetValue> 36432 <fields> 36433 <field> 36434 <name>MPSIZ</name> 36435 <description>Maximum packet size</description> 36436 <bitOffset>0</bitOffset> 36437 <bitWidth>11</bitWidth> 36438 <access>read-write</access> 36439 </field> 36440 <field> 36441 <name>USBAEP</name> 36442 <description>USB active endpoint</description> 36443 <bitOffset>15</bitOffset> 36444 <bitWidth>1</bitWidth> 36445 <access>read-write</access> 36446 </field> 36447 <field> 36448 <name>EONUM_DPID</name> 36449 <description>Even/odd frame</description> 36450 <bitOffset>16</bitOffset> 36451 <bitWidth>1</bitWidth> 36452 <access>read-only</access> 36453 </field> 36454 <field> 36455 <name>NAKSTS</name> 36456 <description>NAK status</description> 36457 <bitOffset>17</bitOffset> 36458 <bitWidth>1</bitWidth> 36459 <access>read-only</access> 36460 </field> 36461 <field> 36462 <name>EPTYP</name> 36463 <description>Endpoint type</description> 36464 <bitOffset>18</bitOffset> 36465 <bitWidth>2</bitWidth> 36466 <access>read-write</access> 36467 </field> 36468 <field> 36469 <name>STALL</name> 36470 <description>STALL handshake</description> 36471 <bitOffset>21</bitOffset> 36472 <bitWidth>1</bitWidth> 36473 <access>read-write</access> 36474 </field> 36475 <field> 36476 <name>TXFNUM</name> 36477 <description>TxFIFO number</description> 36478 <bitOffset>22</bitOffset> 36479 <bitWidth>4</bitWidth> 36480 <access>read-write</access> 36481 </field> 36482 <field> 36483 <name>CNAK</name> 36484 <description>Clear NAK</description> 36485 <bitOffset>26</bitOffset> 36486 <bitWidth>1</bitWidth> 36487 <access>write-only</access> 36488 </field> 36489 <field> 36490 <name>SNAK</name> 36491 <description>Set NAK</description> 36492 <bitOffset>27</bitOffset> 36493 <bitWidth>1</bitWidth> 36494 <access>write-only</access> 36495 </field> 36496 <field> 36497 <name>SD0PID_SEVNFRM</name> 36498 <description>Set DATA0 PID</description> 36499 <bitOffset>28</bitOffset> 36500 <bitWidth>1</bitWidth> 36501 <access>write-only</access> 36502 </field> 36503 <field> 36504 <name>SODDFRM</name> 36505 <description>Set odd frame</description> 36506 <bitOffset>29</bitOffset> 36507 <bitWidth>1</bitWidth> 36508 <access>write-only</access> 36509 </field> 36510 <field> 36511 <name>EPDIS</name> 36512 <description>Endpoint disable</description> 36513 <bitOffset>30</bitOffset> 36514 <bitWidth>1</bitWidth> 36515 <access>read-write</access> 36516 </field> 36517 <field> 36518 <name>EPENA</name> 36519 <description>Endpoint enable</description> 36520 <bitOffset>31</bitOffset> 36521 <bitWidth>1</bitWidth> 36522 <access>read-write</access> 36523 </field> 36524 </fields> 36525 </register> 36526 <register> 36527 <dim>5</dim><dimIncrement>0x20</dimIncrement><dimIndex>1,2,3,4,5</dimIndex><name>DIEPCTL%s</name> 36528 <displayName>DIEPCTL1</displayName> 36529 <description>OTG device endpoint-1 control 36530 register</description> 36531 <addressOffset>0x120</addressOffset> 36532 <size>32</size> 36533 <resetValue>0x0</resetValue> 36534 <fields> 36535 <field> 36536 <name>MPSIZ</name> 36537 <description>Maximum packet size</description> 36538 <bitOffset>0</bitOffset> 36539 <bitWidth>11</bitWidth> 36540 <access>read-write</access> 36541 </field> 36542 <field> 36543 <name>USBAEP</name> 36544 <description>USB active endpoint</description> 36545 <bitOffset>15</bitOffset> 36546 <bitWidth>1</bitWidth> 36547 <access>read-write</access> 36548 </field> 36549 <field> 36550 <name>EONUM_DPID</name> 36551 <description>Even/odd frame</description> 36552 <bitOffset>16</bitOffset> 36553 <bitWidth>1</bitWidth> 36554 <access>read-only</access> 36555 </field> 36556 <field> 36557 <name>NAKSTS</name> 36558 <description>NAK status</description> 36559 <bitOffset>17</bitOffset> 36560 <bitWidth>1</bitWidth> 36561 <access>read-only</access> 36562 </field> 36563 <field> 36564 <name>EPTYP</name> 36565 <description>Endpoint type</description> 36566 <bitOffset>18</bitOffset> 36567 <bitWidth>2</bitWidth> 36568 <access>read-write</access> 36569 </field> 36570 <field> 36571 <name>STALL</name> 36572 <description>STALL handshake</description> 36573 <bitOffset>21</bitOffset> 36574 <bitWidth>1</bitWidth> 36575 <access>read-write</access> 36576 </field> 36577 <field> 36578 <name>TXFNUM</name> 36579 <description>TxFIFO number</description> 36580 <bitOffset>22</bitOffset> 36581 <bitWidth>4</bitWidth> 36582 <access>read-write</access> 36583 </field> 36584 <field> 36585 <name>CNAK</name> 36586 <description>Clear NAK</description> 36587 <bitOffset>26</bitOffset> 36588 <bitWidth>1</bitWidth> 36589 <access>write-only</access> 36590 </field> 36591 <field> 36592 <name>SNAK</name> 36593 <description>Set NAK</description> 36594 <bitOffset>27</bitOffset> 36595 <bitWidth>1</bitWidth> 36596 <access>write-only</access> 36597 </field> 36598 <field> 36599 <name>SD0PID_SEVNFRM</name> 36600 <description>Set DATA0 PID</description> 36601 <bitOffset>28</bitOffset> 36602 <bitWidth>1</bitWidth> 36603 <access>write-only</access> 36604 </field> 36605 <field> 36606 <name>SODDFRM</name> 36607 <description>Set odd frame</description> 36608 <bitOffset>29</bitOffset> 36609 <bitWidth>1</bitWidth> 36610 <access>write-only</access> 36611 </field> 36612 <field> 36613 <name>EPDIS</name> 36614 <description>Endpoint disable</description> 36615 <bitOffset>30</bitOffset> 36616 <bitWidth>1</bitWidth> 36617 <access>read-write</access> 36618 </field> 36619 <field> 36620 <name>EPENA</name> 36621 <description>Endpoint enable</description> 36622 <bitOffset>31</bitOffset> 36623 <bitWidth>1</bitWidth> 36624 <access>read-write</access> 36625 </field> 36626 </fields> 36627 </register> 36628 <register> 36629 <dim>6</dim><dimIncrement>0x20</dimIncrement><dimIndex>0,1,2,3,4,5</dimIndex><name>DIEPINT%s</name> 36630 <displayName>DIEPINT0</displayName> 36631 <description>OTG device endpoint-%s interrupt 36632 register</description> 36633 <addressOffset>0x108</addressOffset> 36634 <size>32</size> 36635 <resetValue>0x00000080</resetValue> 36636 <fields> 36637 <field> 36638 <name>XFRC</name> 36639 <description>Transfer completed 36640 interrupt</description> 36641 <bitOffset>0</bitOffset> 36642 <bitWidth>1</bitWidth> 36643 <access>read-write</access> 36644 </field> 36645 <field> 36646 <name>EPDISD</name> 36647 <description>Endpoint disabled 36648 interrupt</description> 36649 <bitOffset>1</bitOffset> 36650 <bitWidth>1</bitWidth> 36651 <access>read-write</access> 36652 </field> 36653 <field> 36654 <name>TOC</name> 36655 <description>Timeout condition</description> 36656 <bitOffset>3</bitOffset> 36657 <bitWidth>1</bitWidth> 36658 <access>read-write</access> 36659 </field> 36660 <field> 36661 <name>ITTXFE</name> 36662 <description>IN token received when TxFIFO is 36663 empty</description> 36664 <bitOffset>4</bitOffset> 36665 <bitWidth>1</bitWidth> 36666 <access>read-write</access> 36667 </field> 36668 <field> 36669 <name>INEPNE</name> 36670 <description>IN endpoint NAK effective</description> 36671 <bitOffset>6</bitOffset> 36672 <bitWidth>1</bitWidth> 36673 <access>read-write</access> 36674 </field> 36675 <field> 36676 <name>TXFE</name> 36677 <description>Transmit FIFO empty</description> 36678 <bitOffset>7</bitOffset> 36679 <bitWidth>1</bitWidth> 36680 <access>read-only</access> 36681 </field> 36682 <field> 36683 <name>TXFIFOUDRN</name> 36684 <description>Transmit Fifo Underrun</description> 36685 <bitOffset>8</bitOffset> 36686 <bitWidth>1</bitWidth> 36687 <access>read-write</access> 36688 </field> 36689 <field> 36690 <name>BNA</name> 36691 <description>Buffer not available 36692 interrupt</description> 36693 <bitOffset>9</bitOffset> 36694 <bitWidth>1</bitWidth> 36695 <access>read-write</access> 36696 </field> 36697 <field> 36698 <name>PKTDRPSTS</name> 36699 <description>Packet dropped status</description> 36700 <bitOffset>11</bitOffset> 36701 <bitWidth>1</bitWidth> 36702 <access>read-write</access> 36703 </field> 36704 <field> 36705 <name>BERR</name> 36706 <description>Babble error interrupt</description> 36707 <bitOffset>12</bitOffset> 36708 <bitWidth>1</bitWidth> 36709 <access>read-write</access> 36710 </field> 36711 <field> 36712 <name>NAK</name> 36713 <description>NAK interrupt</description> 36714 <bitOffset>13</bitOffset> 36715 <bitWidth>1</bitWidth> 36716 <access>read-write</access> 36717 </field> 36718 </fields> 36719 </register> 36720 <register> 36721 <name>DIEPTSIZ0</name> 36722 <displayName>DIEPTSIZ0</displayName> 36723 <description>OTG_HS device IN endpoint 0 transfer size 36724 register</description> 36725 <addressOffset>0x110</addressOffset> 36726 <size>32</size> 36727 <access>read-write</access> 36728 <resetValue>0x0</resetValue> 36729 <fields> 36730 <field> 36731 <name>XFRSIZ</name> 36732 <description>Transfer size</description> 36733 <bitOffset>0</bitOffset> 36734 <bitWidth>7</bitWidth> 36735 </field> 36736 <field> 36737 <name>PKTCNT</name> 36738 <description>Packet count</description> 36739 <bitOffset>19</bitOffset> 36740 <bitWidth>2</bitWidth> 36741 </field> 36742 </fields> 36743 </register> 36744 <register> 36745 <name>DIEPDMA1</name> 36746 <displayName>DIEPDMA1</displayName> 36747 <description>OTG_HS device endpoint-1 DMA address 36748 register</description> 36749 <addressOffset>0x114</addressOffset> 36750 <size>32</size> 36751 <access>read-write</access> 36752 <resetValue>0x0</resetValue> 36753 <fields> 36754 <field> 36755 <name>DMAADDR</name> 36756 <description>DMA address</description> 36757 <bitOffset>0</bitOffset> 36758 <bitWidth>32</bitWidth> 36759 </field> 36760 </fields> 36761 </register> 36762 <register> 36763 <name>DIEPDMA2</name> 36764 <displayName>DIEPDMA2</displayName> 36765 <description>OTG_HS device endpoint-2 DMA address 36766 register</description> 36767 <addressOffset>0x134</addressOffset> 36768 <size>32</size> 36769 <access>read-write</access> 36770 <resetValue>0x0</resetValue> 36771 <fields> 36772 <field> 36773 <name>DMAADDR</name> 36774 <description>DMA address</description> 36775 <bitOffset>0</bitOffset> 36776 <bitWidth>32</bitWidth> 36777 </field> 36778 </fields> 36779 </register> 36780 <register> 36781 <name>DIEPDMA3</name> 36782 <displayName>DIEPDMA3</displayName> 36783 <description>OTG_HS device endpoint-3 DMA address 36784 register</description> 36785 <addressOffset>0x154</addressOffset> 36786 <size>32</size> 36787 <access>read-write</access> 36788 <resetValue>0x0</resetValue> 36789 <fields> 36790 <field> 36791 <name>DMAADDR</name> 36792 <description>DMA address</description> 36793 <bitOffset>0</bitOffset> 36794 <bitWidth>32</bitWidth> 36795 </field> 36796 </fields> 36797 </register> 36798 <register> 36799 <name>DIEPDMA4</name> 36800 <displayName>DIEPDMA4</displayName> 36801 <description>OTG_HS device endpoint-4 DMA address 36802 register</description> 36803 <addressOffset>0x174</addressOffset> 36804 <size>32</size> 36805 <access>read-write</access> 36806 <resetValue>0x0</resetValue> 36807 <fields> 36808 <field> 36809 <name>DMAADDR</name> 36810 <description>DMA address</description> 36811 <bitOffset>0</bitOffset> 36812 <bitWidth>32</bitWidth> 36813 </field> 36814 </fields> 36815 </register> 36816 <register> 36817 <name>DIEPDMA5</name> 36818 <displayName>DIEPDMA5</displayName> 36819 <description>OTG_HS device endpoint-5 DMA address 36820 register</description> 36821 <addressOffset>0x194</addressOffset> 36822 <size>32</size> 36823 <access>read-write</access> 36824 <resetValue>0x0</resetValue> 36825 <fields> 36826 <field> 36827 <name>DMAADDR</name> 36828 <description>DMA address</description> 36829 <bitOffset>0</bitOffset> 36830 <bitWidth>32</bitWidth> 36831 </field> 36832 </fields> 36833 </register> 36834 <register> 36835 <dim>6</dim><dimIncrement>0x20</dimIncrement><dimIndex>0,1,2,3,4,5</dimIndex><name>DTXFSTS%s</name> 36836 <displayName>DTXFSTS0</displayName> 36837 <description>OTG_HS device IN endpoint transmit FIFO 36838 status register</description> 36839 <addressOffset>0x118</addressOffset> 36840 <size>32</size> 36841 <access>read-only</access> 36842 <resetValue>0x0</resetValue> 36843 <fields> 36844 <field> 36845 <name>INEPTFSAV</name> 36846 <description>IN endpoint TxFIFO space 36847 avail</description> 36848 <bitOffset>0</bitOffset> 36849 <bitWidth>16</bitWidth> 36850 </field> 36851 </fields> 36852 </register> 36853 <register> 36854 <dim>5</dim><dimIncrement>0x20</dimIncrement><dimIndex>1,2,3,4,5</dimIndex><name>DIEPTSIZ%s</name> 36855 <displayName>DIEPTSIZ1</displayName> 36856 <description>OTG_HS device endpoint transfer size 36857 register</description> 36858 <addressOffset>0x130</addressOffset> 36859 <size>32</size> 36860 <access>read-write</access> 36861 <resetValue>0x0</resetValue> 36862 <fields> 36863 <field> 36864 <name>XFRSIZ</name> 36865 <description>Transfer size</description> 36866 <bitOffset>0</bitOffset> 36867 <bitWidth>19</bitWidth> 36868 </field> 36869 <field> 36870 <name>PKTCNT</name> 36871 <description>Packet count</description> 36872 <bitOffset>19</bitOffset> 36873 <bitWidth>10</bitWidth> 36874 </field> 36875 <field> 36876 <name>MCNT</name> 36877 <description>Multi count</description> 36878 <bitOffset>29</bitOffset> 36879 <bitWidth>2</bitWidth> 36880 </field> 36881 </fields> 36882 </register> 36883 <register> 36884 <name>DOEPCTL0</name> 36885 <displayName>DOEPCTL0</displayName> 36886 <description>OTG_HS device control OUT endpoint 0 control 36887 register</description> 36888 <addressOffset>0x300</addressOffset> 36889 <size>32</size> 36890 <resetValue>0x00008000</resetValue> 36891 <fields> 36892 <field> 36893 <name>MPSIZ</name> 36894 <description>Maximum packet size</description> 36895 <bitOffset>0</bitOffset> 36896 <bitWidth>2</bitWidth> 36897 <access>read-only</access> 36898 </field> 36899 <field> 36900 <name>USBAEP</name> 36901 <description>USB active endpoint</description> 36902 <bitOffset>15</bitOffset> 36903 <bitWidth>1</bitWidth> 36904 <access>read-only</access> 36905 </field> 36906 <field> 36907 <name>NAKSTS</name> 36908 <description>NAK status</description> 36909 <bitOffset>17</bitOffset> 36910 <bitWidth>1</bitWidth> 36911 <access>read-only</access> 36912 </field> 36913 <field> 36914 <name>EPTYP</name> 36915 <description>Endpoint type</description> 36916 <bitOffset>18</bitOffset> 36917 <bitWidth>2</bitWidth> 36918 <access>read-only</access> 36919 </field> 36920 <field> 36921 <name>SNPM</name> 36922 <description>Snoop mode</description> 36923 <bitOffset>20</bitOffset> 36924 <bitWidth>1</bitWidth> 36925 <access>read-write</access> 36926 </field> 36927 <field> 36928 <name>STALL</name> 36929 <description>STALL handshake</description> 36930 <bitOffset>21</bitOffset> 36931 <bitWidth>1</bitWidth> 36932 <access>read-write</access> 36933 </field> 36934 <field> 36935 <name>CNAK</name> 36936 <description>Clear NAK</description> 36937 <bitOffset>26</bitOffset> 36938 <bitWidth>1</bitWidth> 36939 <access>write-only</access> 36940 </field> 36941 <field> 36942 <name>SNAK</name> 36943 <description>Set NAK</description> 36944 <bitOffset>27</bitOffset> 36945 <bitWidth>1</bitWidth> 36946 <access>write-only</access> 36947 </field> 36948 <field> 36949 <name>EPDIS</name> 36950 <description>Endpoint disable</description> 36951 <bitOffset>30</bitOffset> 36952 <bitWidth>1</bitWidth> 36953 <access>read-only</access> 36954 </field> 36955 <field> 36956 <name>EPENA</name> 36957 <description>Endpoint enable</description> 36958 <bitOffset>31</bitOffset> 36959 <bitWidth>1</bitWidth> 36960 <access>write-only</access> 36961 </field> 36962 </fields> 36963 </register> 36964 <register> 36965 <dim>5</dim><dimIncrement>0x20</dimIncrement><dimIndex>1,2,3,4,5</dimIndex><name>DOEPCTL%s</name> 36966 <displayName>DOEPCTL1</displayName> 36967 <description>OTG device endpoint-1 control 36968 register</description> 36969 <addressOffset>0x320</addressOffset> 36970 <size>32</size> 36971 <resetValue>0x0</resetValue> 36972 <fields> 36973 <field> 36974 <name>MPSIZ</name> 36975 <description>Maximum packet size</description> 36976 <bitOffset>0</bitOffset> 36977 <bitWidth>11</bitWidth> 36978 <access>read-write</access> 36979 </field> 36980 <field> 36981 <name>USBAEP</name> 36982 <description>USB active endpoint</description> 36983 <bitOffset>15</bitOffset> 36984 <bitWidth>1</bitWidth> 36985 <access>read-write</access> 36986 </field> 36987 <field> 36988 <name>EONUM_DPID</name> 36989 <description>Even odd frame/Endpoint data 36990 PID</description> 36991 <bitOffset>16</bitOffset> 36992 <bitWidth>1</bitWidth> 36993 <access>read-only</access> 36994 </field> 36995 <field> 36996 <name>NAKSTS</name> 36997 <description>NAK status</description> 36998 <bitOffset>17</bitOffset> 36999 <bitWidth>1</bitWidth> 37000 <access>read-only</access> 37001 </field> 37002 <field> 37003 <name>EPTYP</name> 37004 <description>Endpoint type</description> 37005 <bitOffset>18</bitOffset> 37006 <bitWidth>2</bitWidth> 37007 <access>read-write</access> 37008 </field> 37009 <field> 37010 <name>SNPM</name> 37011 <description>Snoop mode</description> 37012 <bitOffset>20</bitOffset> 37013 <bitWidth>1</bitWidth> 37014 <access>read-write</access> 37015 </field> 37016 <field> 37017 <name>STALL</name> 37018 <description>STALL handshake</description> 37019 <bitOffset>21</bitOffset> 37020 <bitWidth>1</bitWidth> 37021 <access>read-write</access> 37022 </field> 37023 <field> 37024 <name>CNAK</name> 37025 <description>Clear NAK</description> 37026 <bitOffset>26</bitOffset> 37027 <bitWidth>1</bitWidth> 37028 <access>write-only</access> 37029 </field> 37030 <field> 37031 <name>SNAK</name> 37032 <description>Set NAK</description> 37033 <bitOffset>27</bitOffset> 37034 <bitWidth>1</bitWidth> 37035 <access>write-only</access> 37036 </field> 37037 <field> 37038 <name>SD0PID_SEVNFRM</name> 37039 <description>Set DATA0 PID/Set even 37040 frame</description> 37041 <bitOffset>28</bitOffset> 37042 <bitWidth>1</bitWidth> 37043 <access>write-only</access> 37044 </field> 37045 <field> 37046 <name>SODDFRM</name> 37047 <description>Set odd frame</description> 37048 <bitOffset>29</bitOffset> 37049 <bitWidth>1</bitWidth> 37050 <access>write-only</access> 37051 </field> 37052 <field> 37053 <name>EPDIS</name> 37054 <description>Endpoint disable</description> 37055 <bitOffset>30</bitOffset> 37056 <bitWidth>1</bitWidth> 37057 <access>read-write</access> 37058 </field> 37059 <field> 37060 <name>EPENA</name> 37061 <description>Endpoint enable</description> 37062 <bitOffset>31</bitOffset> 37063 <bitWidth>1</bitWidth> 37064 <access>read-write</access> 37065 </field> 37066 </fields> 37067 </register> 37068 <register> 37069 <dim>6</dim><dimIncrement>0x20</dimIncrement><dimIndex>0,1,2,3,4,5</dimIndex><name>DOEPINT%s</name> 37070 <displayName>DOEPINT0</displayName> 37071 <description>OTG_HS device endpoint-%s interrupt 37072 register</description> 37073 <addressOffset>0x308</addressOffset> 37074 <size>32</size> 37075 <access>read-write</access> 37076 <resetValue>0x00000080</resetValue> 37077 <fields> 37078 <field> 37079 <name>XFRC</name> 37080 <description>Transfer completed 37081 interrupt</description> 37082 <bitOffset>0</bitOffset> 37083 <bitWidth>1</bitWidth> 37084 </field> 37085 <field> 37086 <name>EPDISD</name> 37087 <description>Endpoint disabled 37088 interrupt</description> 37089 <bitOffset>1</bitOffset> 37090 <bitWidth>1</bitWidth> 37091 </field> 37092 <field> 37093 <name>STUP</name> 37094 <description>SETUP phase done</description> 37095 <bitOffset>3</bitOffset> 37096 <bitWidth>1</bitWidth> 37097 </field> 37098 <field> 37099 <name>OTEPDIS</name> 37100 <description>OUT token received when endpoint 37101 disabled</description> 37102 <bitOffset>4</bitOffset> 37103 <bitWidth>1</bitWidth> 37104 </field> 37105 <field> 37106 <name>B2BSTUP</name> 37107 <description>Back-to-back SETUP packets 37108 received</description> 37109 <bitOffset>6</bitOffset> 37110 <bitWidth>1</bitWidth> 37111 </field> 37112 <field> 37113 <name>NYET</name> 37114 <description>NYET interrupt</description> 37115 <bitOffset>14</bitOffset> 37116 <bitWidth>1</bitWidth> 37117 </field> 37118 </fields> 37119 </register> 37120 <register> 37121 <name>DOEPTSIZ0</name> 37122 <displayName>DOEPTSIZ0</displayName> 37123 <description>OTG_HS device endpoint-1 transfer size 37124 register</description> 37125 <addressOffset>0x310</addressOffset> 37126 <size>32</size> 37127 <access>read-write</access> 37128 <resetValue>0x0</resetValue> 37129 <fields> 37130 <field> 37131 <name>XFRSIZ</name> 37132 <description>Transfer size</description> 37133 <bitOffset>0</bitOffset> 37134 <bitWidth>7</bitWidth> 37135 </field> 37136 <field> 37137 <name>PKTCNT</name> 37138 <description>Packet count</description> 37139 <bitOffset>19</bitOffset> 37140 <bitWidth>1</bitWidth> 37141 </field> 37142 <field> 37143 <name>STUPCNT</name> 37144 <description>SETUP packet count</description> 37145 <bitOffset>29</bitOffset> 37146 <bitWidth>2</bitWidth> 37147 </field> 37148 </fields> 37149 </register> 37150 <register> 37151 <dim>5</dim><dimIncrement>0x20</dimIncrement><dimIndex>1,2,3,4,5</dimIndex><name>DOEPTSIZ%s</name> 37152 <displayName>DOEPTSIZ1</displayName> 37153 <description>OTG_HS device endpoint-2 transfer size 37154 register</description> 37155 <addressOffset>0x330</addressOffset> 37156 <size>32</size> 37157 <access>read-write</access> 37158 <resetValue>0x0</resetValue> 37159 <fields> 37160 <field> 37161 <name>XFRSIZ</name> 37162 <description>Transfer size</description> 37163 <bitOffset>0</bitOffset> 37164 <bitWidth>19</bitWidth> 37165 </field> 37166 <field> 37167 <name>PKTCNT</name> 37168 <description>Packet count</description> 37169 <bitOffset>19</bitOffset> 37170 <bitWidth>10</bitWidth> 37171 </field> 37172 <field> 37173 <name>RXDPID_STUPCNT</name> 37174 <description>Received data PID/SETUP packet 37175 count</description> 37176 <bitOffset>29</bitOffset> 37177 <bitWidth>2</bitWidth> 37178 </field> 37179 </fields> 37180 </register> 37181 </registers> 37182 </peripheral> 37183 <peripheral> 37184 <name>OTG_HS_PWRCLK</name> 37185 <description>USB on the go high speed</description> 37186 <groupName>USB_OTG_HS</groupName> 37187 <baseAddress>0x40040E00</baseAddress> 37188 <addressBlock> 37189 <offset>0x0</offset> 37190 <size>0x3F200</size> 37191 <usage>registers</usage> 37192 </addressBlock> 37193 <registers> 37194 <register> 37195 <name>PCGCCTL</name> 37196 <displayName>PCGCCTL</displayName> 37197 <description>Power and clock gating control 37198 register</description> 37199 <addressOffset>0x0</addressOffset> 37200 <size>32</size> 37201 <access>read-write</access> 37202 <resetValue>0x0</resetValue> 37203 <fields> 37204 <field> 37205 <name>STPPCLK</name> 37206 <description>Stop PHY clock</description> 37207 <bitOffset>0</bitOffset> 37208 <bitWidth>1</bitWidth> 37209 </field> 37210 <field> 37211 <name>GATEHCLK</name> 37212 <description>Gate HCLK</description> 37213 <bitOffset>1</bitOffset> 37214 <bitWidth>1</bitWidth> 37215 </field> 37216 <field> 37217 <name>PHYSUSP</name> 37218 <description>PHY suspended</description> 37219 <bitOffset>4</bitOffset> 37220 <bitWidth>1</bitWidth> 37221 </field> 37222 </fields> 37223 </register> 37224 </registers> 37225 </peripheral> 37226 <peripheral> 37227 <name>NVIC</name> 37228 <description>Nested Vectored Interrupt 37229 Controller</description> 37230 <groupName>NVIC</groupName> 37231 <baseAddress>0xE000E100</baseAddress> 37232 <addressBlock> 37233 <offset>0x0</offset> 37234 <size>0x351</size> 37235 <usage>registers</usage> 37236 </addressBlock> 37237 <registers> 37238 <register> 37239 <name>ISER0</name> 37240 <displayName>ISER0</displayName> 37241 <description>Interrupt Set-Enable Register</description> 37242 <addressOffset>0x0</addressOffset> 37243 <size>0x20</size> 37244 <access>read-write</access> 37245 <resetValue>0x00000000</resetValue> 37246 <fields> 37247 <field> 37248 <name>SETENA</name> 37249 <description>SETENA</description> 37250 <bitOffset>0</bitOffset> 37251 <bitWidth>32</bitWidth> 37252 </field> 37253 </fields> 37254 </register> 37255 <register> 37256 <name>ISER1</name> 37257 <displayName>ISER1</displayName> 37258 <description>Interrupt Set-Enable Register</description> 37259 <addressOffset>0x4</addressOffset> 37260 <size>0x20</size> 37261 <access>read-write</access> 37262 <resetValue>0x00000000</resetValue> 37263 <fields> 37264 <field> 37265 <name>SETENA</name> 37266 <description>SETENA</description> 37267 <bitOffset>0</bitOffset> 37268 <bitWidth>32</bitWidth> 37269 </field> 37270 </fields> 37271 </register> 37272 <register> 37273 <name>ISER2</name> 37274 <displayName>ISER2</displayName> 37275 <description>Interrupt Set-Enable Register</description> 37276 <addressOffset>0x8</addressOffset> 37277 <size>0x20</size> 37278 <access>read-write</access> 37279 <resetValue>0x00000000</resetValue> 37280 <fields> 37281 <field> 37282 <name>SETENA</name> 37283 <description>SETENA</description> 37284 <bitOffset>0</bitOffset> 37285 <bitWidth>32</bitWidth> 37286 </field> 37287 </fields> 37288 </register> 37289 <register> 37290 <name>ICER0</name> 37291 <displayName>ICER0</displayName> 37292 <description>Interrupt Clear-Enable 37293 Register</description> 37294 <addressOffset>0x80</addressOffset> 37295 <size>0x20</size> 37296 <access>read-write</access> 37297 <resetValue>0x00000000</resetValue> 37298 <fields> 37299 <field> 37300 <name>CLRENA</name> 37301 <description>CLRENA</description> 37302 <bitOffset>0</bitOffset> 37303 <bitWidth>32</bitWidth> 37304 </field> 37305 </fields> 37306 </register> 37307 <register> 37308 <name>ICER1</name> 37309 <displayName>ICER1</displayName> 37310 <description>Interrupt Clear-Enable 37311 Register</description> 37312 <addressOffset>0x84</addressOffset> 37313 <size>0x20</size> 37314 <access>read-write</access> 37315 <resetValue>0x00000000</resetValue> 37316 <fields> 37317 <field> 37318 <name>CLRENA</name> 37319 <description>CLRENA</description> 37320 <bitOffset>0</bitOffset> 37321 <bitWidth>32</bitWidth> 37322 </field> 37323 </fields> 37324 </register> 37325 <register> 37326 <name>ICER2</name> 37327 <displayName>ICER2</displayName> 37328 <description>Interrupt Clear-Enable 37329 Register</description> 37330 <addressOffset>0x88</addressOffset> 37331 <size>0x20</size> 37332 <access>read-write</access> 37333 <resetValue>0x00000000</resetValue> 37334 <fields> 37335 <field> 37336 <name>CLRENA</name> 37337 <description>CLRENA</description> 37338 <bitOffset>0</bitOffset> 37339 <bitWidth>32</bitWidth> 37340 </field> 37341 </fields> 37342 </register> 37343 <register> 37344 <name>ISPR0</name> 37345 <displayName>ISPR0</displayName> 37346 <description>Interrupt Set-Pending Register</description> 37347 <addressOffset>0x100</addressOffset> 37348 <size>0x20</size> 37349 <access>read-write</access> 37350 <resetValue>0x00000000</resetValue> 37351 <fields> 37352 <field> 37353 <name>SETPEND</name> 37354 <description>SETPEND</description> 37355 <bitOffset>0</bitOffset> 37356 <bitWidth>32</bitWidth> 37357 </field> 37358 </fields> 37359 </register> 37360 <register> 37361 <name>ISPR1</name> 37362 <displayName>ISPR1</displayName> 37363 <description>Interrupt Set-Pending Register</description> 37364 <addressOffset>0x104</addressOffset> 37365 <size>0x20</size> 37366 <access>read-write</access> 37367 <resetValue>0x00000000</resetValue> 37368 <fields> 37369 <field> 37370 <name>SETPEND</name> 37371 <description>SETPEND</description> 37372 <bitOffset>0</bitOffset> 37373 <bitWidth>32</bitWidth> 37374 </field> 37375 </fields> 37376 </register> 37377 <register> 37378 <name>ISPR2</name> 37379 <displayName>ISPR2</displayName> 37380 <description>Interrupt Set-Pending Register</description> 37381 <addressOffset>0x108</addressOffset> 37382 <size>0x20</size> 37383 <access>read-write</access> 37384 <resetValue>0x00000000</resetValue> 37385 <fields> 37386 <field> 37387 <name>SETPEND</name> 37388 <description>SETPEND</description> 37389 <bitOffset>0</bitOffset> 37390 <bitWidth>32</bitWidth> 37391 </field> 37392 </fields> 37393 </register> 37394 <register> 37395 <name>ICPR0</name> 37396 <displayName>ICPR0</displayName> 37397 <description>Interrupt Clear-Pending 37398 Register</description> 37399 <addressOffset>0x180</addressOffset> 37400 <size>0x20</size> 37401 <access>read-write</access> 37402 <resetValue>0x00000000</resetValue> 37403 <fields> 37404 <field> 37405 <name>CLRPEND</name> 37406 <description>CLRPEND</description> 37407 <bitOffset>0</bitOffset> 37408 <bitWidth>32</bitWidth> 37409 </field> 37410 </fields> 37411 </register> 37412 <register> 37413 <name>ICPR1</name> 37414 <displayName>ICPR1</displayName> 37415 <description>Interrupt Clear-Pending 37416 Register</description> 37417 <addressOffset>0x184</addressOffset> 37418 <size>0x20</size> 37419 <access>read-write</access> 37420 <resetValue>0x00000000</resetValue> 37421 <fields> 37422 <field> 37423 <name>CLRPEND</name> 37424 <description>CLRPEND</description> 37425 <bitOffset>0</bitOffset> 37426 <bitWidth>32</bitWidth> 37427 </field> 37428 </fields> 37429 </register> 37430 <register> 37431 <name>ICPR2</name> 37432 <displayName>ICPR2</displayName> 37433 <description>Interrupt Clear-Pending 37434 Register</description> 37435 <addressOffset>0x188</addressOffset> 37436 <size>0x20</size> 37437 <access>read-write</access> 37438 <resetValue>0x00000000</resetValue> 37439 <fields> 37440 <field> 37441 <name>CLRPEND</name> 37442 <description>CLRPEND</description> 37443 <bitOffset>0</bitOffset> 37444 <bitWidth>32</bitWidth> 37445 </field> 37446 </fields> 37447 </register> 37448 <register> 37449 <name>IABR0</name> 37450 <displayName>IABR0</displayName> 37451 <description>Interrupt Active Bit Register</description> 37452 <addressOffset>0x200</addressOffset> 37453 <size>0x20</size> 37454 <access>read-only</access> 37455 <resetValue>0x00000000</resetValue> 37456 <fields> 37457 <field> 37458 <name>ACTIVE</name> 37459 <description>ACTIVE</description> 37460 <bitOffset>0</bitOffset> 37461 <bitWidth>32</bitWidth> 37462 </field> 37463 </fields> 37464 </register> 37465 <register> 37466 <name>IABR1</name> 37467 <displayName>IABR1</displayName> 37468 <description>Interrupt Active Bit Register</description> 37469 <addressOffset>0x204</addressOffset> 37470 <size>0x20</size> 37471 <access>read-only</access> 37472 <resetValue>0x00000000</resetValue> 37473 <fields> 37474 <field> 37475 <name>ACTIVE</name> 37476 <description>ACTIVE</description> 37477 <bitOffset>0</bitOffset> 37478 <bitWidth>32</bitWidth> 37479 </field> 37480 </fields> 37481 </register> 37482 <register> 37483 <name>IABR2</name> 37484 <displayName>IABR2</displayName> 37485 <description>Interrupt Active Bit Register</description> 37486 <addressOffset>0x208</addressOffset> 37487 <size>0x20</size> 37488 <access>read-only</access> 37489 <resetValue>0x00000000</resetValue> 37490 <fields> 37491 <field> 37492 <name>ACTIVE</name> 37493 <description>ACTIVE</description> 37494 <bitOffset>0</bitOffset> 37495 <bitWidth>32</bitWidth> 37496 </field> 37497 </fields> 37498 </register> 37499 <register> 37500 <name>IPR0</name> 37501 <displayName>IPR0</displayName> 37502 <description>Interrupt Priority Register</description> 37503 <addressOffset>0x300</addressOffset> 37504 <size>0x20</size> 37505 <access>read-write</access> 37506 <resetValue>0x00000000</resetValue> 37507 <fields> 37508 <field> 37509 <name>IPR_N0</name> 37510 <description>IPR_N0</description> 37511 <bitOffset>0</bitOffset> 37512 <bitWidth>8</bitWidth> 37513 </field> 37514 <field> 37515 <name>IPR_N1</name> 37516 <description>IPR_N1</description> 37517 <bitOffset>8</bitOffset> 37518 <bitWidth>8</bitWidth> 37519 </field> 37520 <field> 37521 <name>IPR_N2</name> 37522 <description>IPR_N2</description> 37523 <bitOffset>16</bitOffset> 37524 <bitWidth>8</bitWidth> 37525 </field> 37526 <field> 37527 <name>IPR_N3</name> 37528 <description>IPR_N3</description> 37529 <bitOffset>24</bitOffset> 37530 <bitWidth>8</bitWidth> 37531 </field> 37532 </fields> 37533 </register> 37534 <register> 37535 <name>IPR1</name> 37536 <displayName>IPR1</displayName> 37537 <description>Interrupt Priority Register</description> 37538 <addressOffset>0x304</addressOffset> 37539 <size>0x20</size> 37540 <access>read-write</access> 37541 <resetValue>0x00000000</resetValue> 37542 <fields> 37543 <field> 37544 <name>IPR_N0</name> 37545 <description>IPR_N0</description> 37546 <bitOffset>0</bitOffset> 37547 <bitWidth>8</bitWidth> 37548 </field> 37549 <field> 37550 <name>IPR_N1</name> 37551 <description>IPR_N1</description> 37552 <bitOffset>8</bitOffset> 37553 <bitWidth>8</bitWidth> 37554 </field> 37555 <field> 37556 <name>IPR_N2</name> 37557 <description>IPR_N2</description> 37558 <bitOffset>16</bitOffset> 37559 <bitWidth>8</bitWidth> 37560 </field> 37561 <field> 37562 <name>IPR_N3</name> 37563 <description>IPR_N3</description> 37564 <bitOffset>24</bitOffset> 37565 <bitWidth>8</bitWidth> 37566 </field> 37567 </fields> 37568 </register> 37569 <register> 37570 <name>IPR2</name> 37571 <displayName>IPR2</displayName> 37572 <description>Interrupt Priority Register</description> 37573 <addressOffset>0x308</addressOffset> 37574 <size>0x20</size> 37575 <access>read-write</access> 37576 <resetValue>0x00000000</resetValue> 37577 <fields> 37578 <field> 37579 <name>IPR_N0</name> 37580 <description>IPR_N0</description> 37581 <bitOffset>0</bitOffset> 37582 <bitWidth>8</bitWidth> 37583 </field> 37584 <field> 37585 <name>IPR_N1</name> 37586 <description>IPR_N1</description> 37587 <bitOffset>8</bitOffset> 37588 <bitWidth>8</bitWidth> 37589 </field> 37590 <field> 37591 <name>IPR_N2</name> 37592 <description>IPR_N2</description> 37593 <bitOffset>16</bitOffset> 37594 <bitWidth>8</bitWidth> 37595 </field> 37596 <field> 37597 <name>IPR_N3</name> 37598 <description>IPR_N3</description> 37599 <bitOffset>24</bitOffset> 37600 <bitWidth>8</bitWidth> 37601 </field> 37602 </fields> 37603 </register> 37604 <register> 37605 <name>IPR3</name> 37606 <displayName>IPR3</displayName> 37607 <description>Interrupt Priority Register</description> 37608 <addressOffset>0x30C</addressOffset> 37609 <size>0x20</size> 37610 <access>read-write</access> 37611 <resetValue>0x00000000</resetValue> 37612 <fields> 37613 <field> 37614 <name>IPR_N0</name> 37615 <description>IPR_N0</description> 37616 <bitOffset>0</bitOffset> 37617 <bitWidth>8</bitWidth> 37618 </field> 37619 <field> 37620 <name>IPR_N1</name> 37621 <description>IPR_N1</description> 37622 <bitOffset>8</bitOffset> 37623 <bitWidth>8</bitWidth> 37624 </field> 37625 <field> 37626 <name>IPR_N2</name> 37627 <description>IPR_N2</description> 37628 <bitOffset>16</bitOffset> 37629 <bitWidth>8</bitWidth> 37630 </field> 37631 <field> 37632 <name>IPR_N3</name> 37633 <description>IPR_N3</description> 37634 <bitOffset>24</bitOffset> 37635 <bitWidth>8</bitWidth> 37636 </field> 37637 </fields> 37638 </register> 37639 <register> 37640 <name>IPR4</name> 37641 <displayName>IPR4</displayName> 37642 <description>Interrupt Priority Register</description> 37643 <addressOffset>0x310</addressOffset> 37644 <size>0x20</size> 37645 <access>read-write</access> 37646 <resetValue>0x00000000</resetValue> 37647 <fields> 37648 <field> 37649 <name>IPR_N0</name> 37650 <description>IPR_N0</description> 37651 <bitOffset>0</bitOffset> 37652 <bitWidth>8</bitWidth> 37653 </field> 37654 <field> 37655 <name>IPR_N1</name> 37656 <description>IPR_N1</description> 37657 <bitOffset>8</bitOffset> 37658 <bitWidth>8</bitWidth> 37659 </field> 37660 <field> 37661 <name>IPR_N2</name> 37662 <description>IPR_N2</description> 37663 <bitOffset>16</bitOffset> 37664 <bitWidth>8</bitWidth> 37665 </field> 37666 <field> 37667 <name>IPR_N3</name> 37668 <description>IPR_N3</description> 37669 <bitOffset>24</bitOffset> 37670 <bitWidth>8</bitWidth> 37671 </field> 37672 </fields> 37673 </register> 37674 <register> 37675 <name>IPR5</name> 37676 <displayName>IPR5</displayName> 37677 <description>Interrupt Priority Register</description> 37678 <addressOffset>0x314</addressOffset> 37679 <size>0x20</size> 37680 <access>read-write</access> 37681 <resetValue>0x00000000</resetValue> 37682 <fields> 37683 <field> 37684 <name>IPR_N0</name> 37685 <description>IPR_N0</description> 37686 <bitOffset>0</bitOffset> 37687 <bitWidth>8</bitWidth> 37688 </field> 37689 <field> 37690 <name>IPR_N1</name> 37691 <description>IPR_N1</description> 37692 <bitOffset>8</bitOffset> 37693 <bitWidth>8</bitWidth> 37694 </field> 37695 <field> 37696 <name>IPR_N2</name> 37697 <description>IPR_N2</description> 37698 <bitOffset>16</bitOffset> 37699 <bitWidth>8</bitWidth> 37700 </field> 37701 <field> 37702 <name>IPR_N3</name> 37703 <description>IPR_N3</description> 37704 <bitOffset>24</bitOffset> 37705 <bitWidth>8</bitWidth> 37706 </field> 37707 </fields> 37708 </register> 37709 <register> 37710 <name>IPR6</name> 37711 <displayName>IPR6</displayName> 37712 <description>Interrupt Priority Register</description> 37713 <addressOffset>0x318</addressOffset> 37714 <size>0x20</size> 37715 <access>read-write</access> 37716 <resetValue>0x00000000</resetValue> 37717 <fields> 37718 <field> 37719 <name>IPR_N0</name> 37720 <description>IPR_N0</description> 37721 <bitOffset>0</bitOffset> 37722 <bitWidth>8</bitWidth> 37723 </field> 37724 <field> 37725 <name>IPR_N1</name> 37726 <description>IPR_N1</description> 37727 <bitOffset>8</bitOffset> 37728 <bitWidth>8</bitWidth> 37729 </field> 37730 <field> 37731 <name>IPR_N2</name> 37732 <description>IPR_N2</description> 37733 <bitOffset>16</bitOffset> 37734 <bitWidth>8</bitWidth> 37735 </field> 37736 <field> 37737 <name>IPR_N3</name> 37738 <description>IPR_N3</description> 37739 <bitOffset>24</bitOffset> 37740 <bitWidth>8</bitWidth> 37741 </field> 37742 </fields> 37743 </register> 37744 <register> 37745 <name>IPR7</name> 37746 <displayName>IPR7</displayName> 37747 <description>Interrupt Priority Register</description> 37748 <addressOffset>0x31C</addressOffset> 37749 <size>0x20</size> 37750 <access>read-write</access> 37751 <resetValue>0x00000000</resetValue> 37752 <fields> 37753 <field> 37754 <name>IPR_N0</name> 37755 <description>IPR_N0</description> 37756 <bitOffset>0</bitOffset> 37757 <bitWidth>8</bitWidth> 37758 </field> 37759 <field> 37760 <name>IPR_N1</name> 37761 <description>IPR_N1</description> 37762 <bitOffset>8</bitOffset> 37763 <bitWidth>8</bitWidth> 37764 </field> 37765 <field> 37766 <name>IPR_N2</name> 37767 <description>IPR_N2</description> 37768 <bitOffset>16</bitOffset> 37769 <bitWidth>8</bitWidth> 37770 </field> 37771 <field> 37772 <name>IPR_N3</name> 37773 <description>IPR_N3</description> 37774 <bitOffset>24</bitOffset> 37775 <bitWidth>8</bitWidth> 37776 </field> 37777 </fields> 37778 </register> 37779 <register> 37780 <name>IPR8</name> 37781 <displayName>IPR8</displayName> 37782 <description>Interrupt Priority Register</description> 37783 <addressOffset>0x320</addressOffset> 37784 <size>0x20</size> 37785 <access>read-write</access> 37786 <resetValue>0x00000000</resetValue> 37787 <fields> 37788 <field> 37789 <name>IPR_N0</name> 37790 <description>IPR_N0</description> 37791 <bitOffset>0</bitOffset> 37792 <bitWidth>8</bitWidth> 37793 </field> 37794 <field> 37795 <name>IPR_N1</name> 37796 <description>IPR_N1</description> 37797 <bitOffset>8</bitOffset> 37798 <bitWidth>8</bitWidth> 37799 </field> 37800 <field> 37801 <name>IPR_N2</name> 37802 <description>IPR_N2</description> 37803 <bitOffset>16</bitOffset> 37804 <bitWidth>8</bitWidth> 37805 </field> 37806 <field> 37807 <name>IPR_N3</name> 37808 <description>IPR_N3</description> 37809 <bitOffset>24</bitOffset> 37810 <bitWidth>8</bitWidth> 37811 </field> 37812 </fields> 37813 </register> 37814 <register> 37815 <name>IPR9</name> 37816 <displayName>IPR9</displayName> 37817 <description>Interrupt Priority Register</description> 37818 <addressOffset>0x324</addressOffset> 37819 <size>0x20</size> 37820 <access>read-write</access> 37821 <resetValue>0x00000000</resetValue> 37822 <fields> 37823 <field> 37824 <name>IPR_N0</name> 37825 <description>IPR_N0</description> 37826 <bitOffset>0</bitOffset> 37827 <bitWidth>8</bitWidth> 37828 </field> 37829 <field> 37830 <name>IPR_N1</name> 37831 <description>IPR_N1</description> 37832 <bitOffset>8</bitOffset> 37833 <bitWidth>8</bitWidth> 37834 </field> 37835 <field> 37836 <name>IPR_N2</name> 37837 <description>IPR_N2</description> 37838 <bitOffset>16</bitOffset> 37839 <bitWidth>8</bitWidth> 37840 </field> 37841 <field> 37842 <name>IPR_N3</name> 37843 <description>IPR_N3</description> 37844 <bitOffset>24</bitOffset> 37845 <bitWidth>8</bitWidth> 37846 </field> 37847 </fields> 37848 </register> 37849 <register> 37850 <name>IPR10</name> 37851 <displayName>IPR10</displayName> 37852 <description>Interrupt Priority Register</description> 37853 <addressOffset>0x328</addressOffset> 37854 <size>0x20</size> 37855 <access>read-write</access> 37856 <resetValue>0x00000000</resetValue> 37857 <fields> 37858 <field> 37859 <name>IPR_N0</name> 37860 <description>IPR_N0</description> 37861 <bitOffset>0</bitOffset> 37862 <bitWidth>8</bitWidth> 37863 </field> 37864 <field> 37865 <name>IPR_N1</name> 37866 <description>IPR_N1</description> 37867 <bitOffset>8</bitOffset> 37868 <bitWidth>8</bitWidth> 37869 </field> 37870 <field> 37871 <name>IPR_N2</name> 37872 <description>IPR_N2</description> 37873 <bitOffset>16</bitOffset> 37874 <bitWidth>8</bitWidth> 37875 </field> 37876 <field> 37877 <name>IPR_N3</name> 37878 <description>IPR_N3</description> 37879 <bitOffset>24</bitOffset> 37880 <bitWidth>8</bitWidth> 37881 </field> 37882 </fields> 37883 </register> 37884 <register> 37885 <name>IPR11</name> 37886 <displayName>IPR11</displayName> 37887 <description>Interrupt Priority Register</description> 37888 <addressOffset>0x32C</addressOffset> 37889 <size>0x20</size> 37890 <access>read-write</access> 37891 <resetValue>0x00000000</resetValue> 37892 <fields> 37893 <field> 37894 <name>IPR_N0</name> 37895 <description>IPR_N0</description> 37896 <bitOffset>0</bitOffset> 37897 <bitWidth>8</bitWidth> 37898 </field> 37899 <field> 37900 <name>IPR_N1</name> 37901 <description>IPR_N1</description> 37902 <bitOffset>8</bitOffset> 37903 <bitWidth>8</bitWidth> 37904 </field> 37905 <field> 37906 <name>IPR_N2</name> 37907 <description>IPR_N2</description> 37908 <bitOffset>16</bitOffset> 37909 <bitWidth>8</bitWidth> 37910 </field> 37911 <field> 37912 <name>IPR_N3</name> 37913 <description>IPR_N3</description> 37914 <bitOffset>24</bitOffset> 37915 <bitWidth>8</bitWidth> 37916 </field> 37917 </fields> 37918 </register> 37919 <register> 37920 <name>IPR12</name> 37921 <displayName>IPR12</displayName> 37922 <description>Interrupt Priority Register</description> 37923 <addressOffset>0x330</addressOffset> 37924 <size>0x20</size> 37925 <access>read-write</access> 37926 <resetValue>0x00000000</resetValue> 37927 <fields> 37928 <field> 37929 <name>IPR_N0</name> 37930 <description>IPR_N0</description> 37931 <bitOffset>0</bitOffset> 37932 <bitWidth>8</bitWidth> 37933 </field> 37934 <field> 37935 <name>IPR_N1</name> 37936 <description>IPR_N1</description> 37937 <bitOffset>8</bitOffset> 37938 <bitWidth>8</bitWidth> 37939 </field> 37940 <field> 37941 <name>IPR_N2</name> 37942 <description>IPR_N2</description> 37943 <bitOffset>16</bitOffset> 37944 <bitWidth>8</bitWidth> 37945 </field> 37946 <field> 37947 <name>IPR_N3</name> 37948 <description>IPR_N3</description> 37949 <bitOffset>24</bitOffset> 37950 <bitWidth>8</bitWidth> 37951 </field> 37952 </fields> 37953 </register> 37954 <register> 37955 <name>IPR13</name> 37956 <displayName>IPR13</displayName> 37957 <description>Interrupt Priority Register</description> 37958 <addressOffset>0x334</addressOffset> 37959 <size>0x20</size> 37960 <access>read-write</access> 37961 <resetValue>0x00000000</resetValue> 37962 <fields> 37963 <field> 37964 <name>IPR_N0</name> 37965 <description>IPR_N0</description> 37966 <bitOffset>0</bitOffset> 37967 <bitWidth>8</bitWidth> 37968 </field> 37969 <field> 37970 <name>IPR_N1</name> 37971 <description>IPR_N1</description> 37972 <bitOffset>8</bitOffset> 37973 <bitWidth>8</bitWidth> 37974 </field> 37975 <field> 37976 <name>IPR_N2</name> 37977 <description>IPR_N2</description> 37978 <bitOffset>16</bitOffset> 37979 <bitWidth>8</bitWidth> 37980 </field> 37981 <field> 37982 <name>IPR_N3</name> 37983 <description>IPR_N3</description> 37984 <bitOffset>24</bitOffset> 37985 <bitWidth>8</bitWidth> 37986 </field> 37987 </fields> 37988 </register> 37989 <register> 37990 <name>IPR14</name> 37991 <displayName>IPR14</displayName> 37992 <description>Interrupt Priority Register</description> 37993 <addressOffset>0x338</addressOffset> 37994 <size>0x20</size> 37995 <access>read-write</access> 37996 <resetValue>0x00000000</resetValue> 37997 <fields> 37998 <field> 37999 <name>IPR_N0</name> 38000 <description>IPR_N0</description> 38001 <bitOffset>0</bitOffset> 38002 <bitWidth>8</bitWidth> 38003 </field> 38004 <field> 38005 <name>IPR_N1</name> 38006 <description>IPR_N1</description> 38007 <bitOffset>8</bitOffset> 38008 <bitWidth>8</bitWidth> 38009 </field> 38010 <field> 38011 <name>IPR_N2</name> 38012 <description>IPR_N2</description> 38013 <bitOffset>16</bitOffset> 38014 <bitWidth>8</bitWidth> 38015 </field> 38016 <field> 38017 <name>IPR_N3</name> 38018 <description>IPR_N3</description> 38019 <bitOffset>24</bitOffset> 38020 <bitWidth>8</bitWidth> 38021 </field> 38022 </fields> 38023 </register> 38024 <register> 38025 <name>IPR15</name> 38026 <displayName>IPR15</displayName> 38027 <description>Interrupt Priority Register</description> 38028 <addressOffset>0x33C</addressOffset> 38029 <size>0x20</size> 38030 <access>read-write</access> 38031 <resetValue>0x00000000</resetValue> 38032 <fields> 38033 <field> 38034 <name>IPR_N0</name> 38035 <description>IPR_N0</description> 38036 <bitOffset>0</bitOffset> 38037 <bitWidth>8</bitWidth> 38038 </field> 38039 <field> 38040 <name>IPR_N1</name> 38041 <description>IPR_N1</description> 38042 <bitOffset>8</bitOffset> 38043 <bitWidth>8</bitWidth> 38044 </field> 38045 <field> 38046 <name>IPR_N2</name> 38047 <description>IPR_N2</description> 38048 <bitOffset>16</bitOffset> 38049 <bitWidth>8</bitWidth> 38050 </field> 38051 <field> 38052 <name>IPR_N3</name> 38053 <description>IPR_N3</description> 38054 <bitOffset>24</bitOffset> 38055 <bitWidth>8</bitWidth> 38056 </field> 38057 </fields> 38058 </register> 38059 <register> 38060 <name>IPR16</name> 38061 <displayName>IPR16</displayName> 38062 <description>Interrupt Priority Register</description> 38063 <addressOffset>0x340</addressOffset> 38064 <size>0x20</size> 38065 <access>read-write</access> 38066 <resetValue>0x00000000</resetValue> 38067 <fields> 38068 <field> 38069 <name>IPR_N0</name> 38070 <description>IPR_N0</description> 38071 <bitOffset>0</bitOffset> 38072 <bitWidth>8</bitWidth> 38073 </field> 38074 <field> 38075 <name>IPR_N1</name> 38076 <description>IPR_N1</description> 38077 <bitOffset>8</bitOffset> 38078 <bitWidth>8</bitWidth> 38079 </field> 38080 <field> 38081 <name>IPR_N2</name> 38082 <description>IPR_N2</description> 38083 <bitOffset>16</bitOffset> 38084 <bitWidth>8</bitWidth> 38085 </field> 38086 <field> 38087 <name>IPR_N3</name> 38088 <description>IPR_N3</description> 38089 <bitOffset>24</bitOffset> 38090 <bitWidth>8</bitWidth> 38091 </field> 38092 </fields> 38093 </register> 38094 <register> 38095 <name>IPR17</name> 38096 <displayName>IPR17</displayName> 38097 <description>Interrupt Priority Register</description> 38098 <addressOffset>0x344</addressOffset> 38099 <size>0x20</size> 38100 <access>read-write</access> 38101 <resetValue>0x00000000</resetValue> 38102 <fields> 38103 <field> 38104 <name>IPR_N0</name> 38105 <description>IPR_N0</description> 38106 <bitOffset>0</bitOffset> 38107 <bitWidth>8</bitWidth> 38108 </field> 38109 <field> 38110 <name>IPR_N1</name> 38111 <description>IPR_N1</description> 38112 <bitOffset>8</bitOffset> 38113 <bitWidth>8</bitWidth> 38114 </field> 38115 <field> 38116 <name>IPR_N2</name> 38117 <description>IPR_N2</description> 38118 <bitOffset>16</bitOffset> 38119 <bitWidth>8</bitWidth> 38120 </field> 38121 <field> 38122 <name>IPR_N3</name> 38123 <description>IPR_N3</description> 38124 <bitOffset>24</bitOffset> 38125 <bitWidth>8</bitWidth> 38126 </field> 38127 </fields> 38128 </register> 38129 <register> 38130 <name>IPR18</name> 38131 <displayName>IPR18</displayName> 38132 <description>Interrupt Priority Register</description> 38133 <addressOffset>0x348</addressOffset> 38134 <size>0x20</size> 38135 <access>read-write</access> 38136 <resetValue>0x00000000</resetValue> 38137 <fields> 38138 <field> 38139 <name>IPR_N0</name> 38140 <description>IPR_N0</description> 38141 <bitOffset>0</bitOffset> 38142 <bitWidth>8</bitWidth> 38143 </field> 38144 <field> 38145 <name>IPR_N1</name> 38146 <description>IPR_N1</description> 38147 <bitOffset>8</bitOffset> 38148 <bitWidth>8</bitWidth> 38149 </field> 38150 <field> 38151 <name>IPR_N2</name> 38152 <description>IPR_N2</description> 38153 <bitOffset>16</bitOffset> 38154 <bitWidth>8</bitWidth> 38155 </field> 38156 <field> 38157 <name>IPR_N3</name> 38158 <description>IPR_N3</description> 38159 <bitOffset>24</bitOffset> 38160 <bitWidth>8</bitWidth> 38161 </field> 38162 </fields> 38163 </register> 38164 <register> 38165 <name>IPR19</name> 38166 <displayName>IPR19</displayName> 38167 <description>Interrupt Priority Register</description> 38168 <addressOffset>0x34C</addressOffset> 38169 <size>0x20</size> 38170 <access>read-write</access> 38171 <resetValue>0x00000000</resetValue> 38172 <fields> 38173 <field> 38174 <name>IPR_N0</name> 38175 <description>IPR_N0</description> 38176 <bitOffset>0</bitOffset> 38177 <bitWidth>8</bitWidth> 38178 </field> 38179 <field> 38180 <name>IPR_N1</name> 38181 <description>IPR_N1</description> 38182 <bitOffset>8</bitOffset> 38183 <bitWidth>8</bitWidth> 38184 </field> 38185 <field> 38186 <name>IPR_N2</name> 38187 <description>IPR_N2</description> 38188 <bitOffset>16</bitOffset> 38189 <bitWidth>8</bitWidth> 38190 </field> 38191 <field> 38192 <name>IPR_N3</name> 38193 <description>IPR_N3</description> 38194 <bitOffset>24</bitOffset> 38195 <bitWidth>8</bitWidth> 38196 </field> 38197 </fields> 38198 </register> 38199 </registers> 38200 </peripheral> 38201 <peripheral> 38202 <name>SAI1</name> 38203 <description>Serial audio interface</description> 38204 <groupName>SAI1</groupName> 38205 <baseAddress>0x40015800</baseAddress> 38206 <addressBlock> 38207 <offset>0x0</offset> 38208 <size>0x400</size> 38209 <usage>registers</usage> 38210 </addressBlock> 38211 <registers> 38212 <cluster><dim>2</dim><dimIncrement>0x20</dimIncrement><dimIndex>A,B</dimIndex><name>CH%s</name><description>Cluster CH%s, containing ?CR1, ?CR2, ?FRCR, ?SLOTR, ?IM, ?SR, ?CLRFR, ?DR</description><addressOffset>0x4</addressOffset><register> 38213 <name>CR1</name> 38214 <displayName>ACR1</displayName> 38215 <description>SAI AConfiguration register 1</description> 38216 <addressOffset>0x0</addressOffset> 38217 <size>0x20</size> 38218 <access>read-write</access> 38219 <resetValue>0x00000040</resetValue> 38220 <fields> 38221 <field> 38222 <name>MCKDIV</name> 38223 <description>Master clock divider</description> 38224 <bitOffset>20</bitOffset> 38225 <bitWidth>4</bitWidth> 38226 </field> 38227 <field> 38228 <name>MODE</name> 38229 <description>Audio block mode</description> 38230 <bitOffset>0</bitOffset> 38231 <bitWidth>2</bitWidth> 38232 <enumeratedValues><name>MODE</name><usage>read-write</usage><enumeratedValue><name>MasterTx</name><description>Master transmitter</description><value>0</value></enumeratedValue><enumeratedValue><name>MasterRx</name><description>Master receiver</description><value>1</value></enumeratedValue><enumeratedValue><name>SlaveTx</name><description>Slave transmitter</description><value>2</value></enumeratedValue><enumeratedValue><name>SlaveRx</name><description>Slave receiver</description><value>3</value></enumeratedValue></enumeratedValues> 38233 </field> 38234 <field> 38235 <name>PRTCFG</name> 38236 <description>Protocol configuration</description> 38237 <bitOffset>2</bitOffset> 38238 <bitWidth>2</bitWidth> 38239 <enumeratedValues><name>PRTCFG</name><usage>read-write</usage><enumeratedValue><name>Free</name><description>Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol</description><value>0</value></enumeratedValue><enumeratedValue><name>Spdif</name><description>SPDIF protocol</description><value>1</value></enumeratedValue><enumeratedValue><name>Ac97</name><description>AC’97 protocol</description><value>2</value></enumeratedValue></enumeratedValues> 38240 </field> 38241 <field> 38242 <name>DS</name> 38243 <description>Data size</description> 38244 <bitOffset>5</bitOffset> 38245 <bitWidth>3</bitWidth> 38246 <enumeratedValues><name>DS</name><usage>read-write</usage><enumeratedValue><name>Bit8</name><description>8 bits</description><value>2</value></enumeratedValue><enumeratedValue><name>Bit10</name><description>10 bits</description><value>3</value></enumeratedValue><enumeratedValue><name>Bit16</name><description>16 bits</description><value>4</value></enumeratedValue><enumeratedValue><name>Bit20</name><description>20 bits</description><value>5</value></enumeratedValue><enumeratedValue><name>Bit24</name><description>24 bits</description><value>6</value></enumeratedValue><enumeratedValue><name>Bit32</name><description>32 bits</description><value>7</value></enumeratedValue></enumeratedValues> 38247 </field> 38248 <field> 38249 <name>LSBFIRST</name> 38250 <description>Least significant bit 38251 first</description> 38252 <bitOffset>8</bitOffset> 38253 <bitWidth>1</bitWidth> 38254 <enumeratedValues><name>LSBFIRST</name><usage>read-write</usage><enumeratedValue><name>MsbFirst</name><description>Data are transferred with MSB first</description><value>0</value></enumeratedValue><enumeratedValue><name>LsbFirst</name><description>Data are transferred with LSB first</description><value>1</value></enumeratedValue></enumeratedValues> 38255 </field> 38256 <field> 38257 <name>CKSTR</name> 38258 <description>Clock strobing edge</description> 38259 <bitOffset>9</bitOffset> 38260 <bitWidth>1</bitWidth> 38261 <enumeratedValues><name>CKSTR</name><usage>read-write</usage><enumeratedValue><name>FallingEdge</name><description>Data strobing edge is falling edge of SCK</description><value>0</value></enumeratedValue><enumeratedValue><name>RisingEdge</name><description>Data strobing edge is rising edge of SCK</description><value>1</value></enumeratedValue></enumeratedValues> 38262 </field> 38263 <field> 38264 <name>SYNCEN</name> 38265 <description>Synchronization enable</description> 38266 <bitOffset>10</bitOffset> 38267 <bitWidth>2</bitWidth> 38268 <enumeratedValues><name>SYNCEN</name><usage>read-write</usage><enumeratedValue><name>Asynchronous</name><description>audio sub-block in asynchronous mode</description><value>0</value></enumeratedValue><enumeratedValue><name>Internal</name><description>audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode</description><value>1</value></enumeratedValue><enumeratedValue><name>External</name><description>audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode</description><value>2</value></enumeratedValue></enumeratedValues> 38269 </field> 38270 <field> 38271 <name>MONO</name> 38272 <description>Mono mode</description> 38273 <bitOffset>12</bitOffset> 38274 <bitWidth>1</bitWidth> 38275 <enumeratedValues><name>MONO</name><usage>read-write</usage><enumeratedValue><name>Stereo</name><description>Stereo mode</description><value>0</value></enumeratedValue><enumeratedValue><name>Mono</name><description>Mono mode</description><value>1</value></enumeratedValue></enumeratedValues> 38276 </field> 38277 <field> 38278 <name>OUTDRIV</name> 38279 <description>Output drive</description> 38280 <bitOffset>13</bitOffset> 38281 <bitWidth>1</bitWidth> 38282 <enumeratedValues><name>OUTDRIV</name><usage>read-write</usage><enumeratedValue><name>OnStart</name><description>Audio block output driven when SAIEN is set</description><value>0</value></enumeratedValue><enumeratedValue><name>Immediately</name><description>Audio block output driven immediately after the setting of this bit</description><value>1</value></enumeratedValue></enumeratedValues> 38283 </field> 38284 <field> 38285 <name>SAIEN</name> 38286 <description>Audio block enable</description> 38287 <bitOffset>16</bitOffset> 38288 <bitWidth>1</bitWidth> 38289 <enumeratedValues><name>SAIEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>SAI audio block disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>SAI audio block enabled</description><value>1</value></enumeratedValue></enumeratedValues> 38290 </field> 38291 <field> 38292 <name>DMAEN</name> 38293 <description>DMA enable</description> 38294 <bitOffset>17</bitOffset> 38295 <bitWidth>1</bitWidth> 38296 <enumeratedValues><name>DMAEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>DMA disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>DMA enabled</description><value>1</value></enumeratedValue></enumeratedValues> 38297 </field> 38298 <field> 38299 <name>NODIV</name> 38300 <description>No divider</description> 38301 <bitOffset>19</bitOffset> 38302 <bitWidth>1</bitWidth> 38303 <enumeratedValues><name>NODIV</name><usage>read-write</usage><enumeratedValue><name>MasterClock</name><description>MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value</description><value>0</value></enumeratedValue><enumeratedValue><name>NoDiv</name><description>MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL.</description><value>1</value></enumeratedValue></enumeratedValues> 38304 </field> 38305 </fields> 38306 </register> 38307 <register> 38308 <name>CR2</name> 38309 <displayName>ACR2</displayName> 38310 <description>SAI AConfiguration register 2</description> 38311 <addressOffset>0x4</addressOffset> 38312 <size>0x20</size> 38313 <access>read-write</access> 38314 <resetValue>0x00000040</resetValue> 38315 <fields> 38316 <field> 38317 <name>FTH</name> 38318 <description>FIFO threshold</description> 38319 <bitOffset>0</bitOffset> 38320 <bitWidth>3</bitWidth> 38321 <enumeratedValues><name>FTH</name><usage>read-write</usage><enumeratedValue><name>Empty</name><description>FIFO empty</description><value>0</value></enumeratedValue><enumeratedValue><name>Quarter1</name><description>1⁄4 FIFO</description><value>1</value></enumeratedValue><enumeratedValue><name>Quarter2</name><description>1⁄2 FIFO</description><value>2</value></enumeratedValue><enumeratedValue><name>Quarter3</name><description>3⁄4 FIFO</description><value>3</value></enumeratedValue><enumeratedValue><name>Full</name><description>FIFO full</description><value>4</value></enumeratedValue></enumeratedValues> 38322 </field> 38323 <field> 38324 <name>FFLUSH</name> 38325 <description>FIFO flush</description> 38326 <bitOffset>3</bitOffset> 38327 <bitWidth>1</bitWidth> 38328 <enumeratedValues><name>FFLUSH</name><usage>read-write</usage><enumeratedValue><name>NoFlush</name><description>No FIFO flush</description><value>0</value></enumeratedValue><enumeratedValue><name>Flush</name><description>FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared</description><value>1</value></enumeratedValue></enumeratedValues> 38329 </field> 38330 <field> 38331 <name>TRIS</name> 38332 <description>Tristate management on data 38333 line</description> 38334 <bitOffset>4</bitOffset> 38335 <bitWidth>1</bitWidth> 38336 </field> 38337 <field> 38338 <name>MUTE</name> 38339 <description>Mute</description> 38340 <bitOffset>5</bitOffset> 38341 <bitWidth>1</bitWidth> 38342 <enumeratedValues><name>MUTE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>No mute mode</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Mute mode enabled</description><value>1</value></enumeratedValue></enumeratedValues> 38343 </field> 38344 <field> 38345 <name>MUTEVAL</name> 38346 <description>Mute value</description> 38347 <bitOffset>6</bitOffset> 38348 <bitWidth>1</bitWidth> 38349 <enumeratedValues><name>MUTEVAL</name><usage>read-write</usage><enumeratedValue><name>SendZero</name><description>Bit value 0 is sent during the mute mode</description><value>0</value></enumeratedValue><enumeratedValue><name>SendLast</name><description>Last values are sent during the mute mode</description><value>1</value></enumeratedValue></enumeratedValues> 38350 </field> 38351 <field> 38352 <name>MUTECNT</name> 38353 <description>Mute counter</description> 38354 <bitOffset>7</bitOffset> 38355 <bitWidth>6</bitWidth> 38356 </field> 38357 <field> 38358 <name>CPL</name> 38359 <description>Complement bit</description> 38360 <bitOffset>13</bitOffset> 38361 <bitWidth>1</bitWidth> 38362 <enumeratedValues><name>CPL</name><usage>read-write</usage><enumeratedValue><name>OnesComplement</name><description>1’s complement representation</description><value>0</value></enumeratedValue><enumeratedValue><name>TwosComplement</name><description>2’s complement representation</description><value>1</value></enumeratedValue></enumeratedValues> 38363 </field> 38364 <field> 38365 <name>COMP</name> 38366 <description>Companding mode</description> 38367 <bitOffset>14</bitOffset> 38368 <bitWidth>2</bitWidth> 38369 <enumeratedValues><name>COMP</name><usage>read-write</usage><enumeratedValue><name>NoCompanding</name><description>No companding algorithm</description><value>0</value></enumeratedValue><enumeratedValue><name>MuLaw</name><description>μ-Law algorithm</description><value>2</value></enumeratedValue><enumeratedValue><name>ALaw</name><description>A-Law algorithm</description><value>3</value></enumeratedValue></enumeratedValues> 38370 </field> 38371 </fields> 38372 </register> 38373 <register> 38374 <name>FRCR</name> 38375 <displayName>AFRCR</displayName> 38376 <description>SAI AFrame configuration 38377 register</description> 38378 <addressOffset>0x8</addressOffset> 38379 <size>0x20</size> 38380 <resetValue>0x00000007</resetValue> 38381 <fields> 38382 <field> 38383 <name>FRL</name> 38384 <description>Frame length</description> 38385 <bitOffset>0</bitOffset> 38386 <bitWidth>8</bitWidth> 38387 <access>read-write</access> 38388 </field> 38389 <field> 38390 <name>FSALL</name> 38391 <description>Frame synchronization active level 38392 length</description> 38393 <bitOffset>8</bitOffset> 38394 <bitWidth>7</bitWidth> 38395 <access>read-write</access> 38396 </field> 38397 <field> 38398 <name>FSDEF</name> 38399 <description>Frame synchronization 38400 definition</description> 38401 <bitOffset>16</bitOffset> 38402 <bitWidth>1</bitWidth> 38403 <access>read-only</access> 38404 </field> 38405 <field> 38406 <name>FSPOL</name> 38407 <description>Frame synchronization 38408 polarity</description> 38409 <bitOffset>17</bitOffset> 38410 <bitWidth>1</bitWidth> 38411 <access>read-write</access> 38412 <enumeratedValues><name>FSPOL</name><usage>read-write</usage><enumeratedValue><name>FallingEdge</name><description>FS is active low (falling edge)</description><value>0</value></enumeratedValue><enumeratedValue><name>RisingEdge</name><description>FS is active high (rising edge)</description><value>1</value></enumeratedValue></enumeratedValues> 38413 </field> 38414 <field> 38415 <name>FSOFF</name> 38416 <description>Frame synchronization 38417 offset</description> 38418 <bitOffset>18</bitOffset> 38419 <bitWidth>1</bitWidth> 38420 <access>read-write</access> 38421 <enumeratedValues><name>FSOFF</name><usage>read-write</usage><enumeratedValue><name>OnFirst</name><description>FS is asserted on the first bit of the slot 0</description><value>0</value></enumeratedValue><enumeratedValue><name>BeforeFirst</name><description>FS is asserted one bit before the first bit of the slot 0</description><value>1</value></enumeratedValue></enumeratedValues> 38422 </field> 38423 </fields> 38424 </register> 38425 <register> 38426 <name>SLOTR</name> 38427 <displayName>ASLOTR</displayName> 38428 <description>SAI ASlot register</description> 38429 <addressOffset>0xc</addressOffset> 38430 <size>0x20</size> 38431 <access>read-write</access> 38432 <resetValue>0x00000000</resetValue> 38433 <fields> 38434 <field> 38435 <name>FBOFF</name> 38436 <description>First bit offset</description> 38437 <bitOffset>0</bitOffset> 38438 <bitWidth>5</bitWidth> 38439 </field> 38440 <field> 38441 <name>SLOTSZ</name> 38442 <description>Slot size</description> 38443 <bitOffset>6</bitOffset> 38444 <bitWidth>2</bitWidth> 38445 <enumeratedValues><name>SLOTSZ</name><usage>read-write</usage><enumeratedValue><name>DataSize</name><description>The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)</description><value>0</value></enumeratedValue><enumeratedValue><name>Bit16</name><description>16-bit</description><value>1</value></enumeratedValue><enumeratedValue><name>Bit32</name><description>32-bit</description><value>2</value></enumeratedValue></enumeratedValues> 38446 </field> 38447 <field> 38448 <name>NBSLOT</name> 38449 <description>Number of slots in an audio 38450 frame</description> 38451 <bitOffset>8</bitOffset> 38452 <bitWidth>4</bitWidth> 38453 </field> 38454 <field> 38455 <name>SLOTEN</name> 38456 <description>Slot enable</description> 38457 <bitOffset>16</bitOffset> 38458 <bitWidth>16</bitWidth> 38459 <enumeratedValues><name>SLOTEN</name><usage>read-write</usage><enumeratedValue><name>Inactive</name><description>Inactive slot</description><value>0</value></enumeratedValue><enumeratedValue><name>Active</name><description>Active slot</description><value>1</value></enumeratedValue></enumeratedValues> 38460 </field> 38461 </fields> 38462 </register> 38463 <register> 38464 <name>IM</name> 38465 <displayName>AIM</displayName> 38466 <description>SAI AInterrupt mask register2</description> 38467 <addressOffset>0x10</addressOffset> 38468 <size>0x20</size> 38469 <access>read-write</access> 38470 <resetValue>0x00000000</resetValue> 38471 <fields> 38472 <field> 38473 <name>OVRUDRIE</name> 38474 <description>Overrun/underrun interrupt 38475 enable</description> 38476 <bitOffset>0</bitOffset> 38477 <bitWidth>1</bitWidth> 38478 <enumeratedValues><name>OVRUDRIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Interrupt is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt is enabled</description><value>1</value></enumeratedValue></enumeratedValues> 38479 </field> 38480 <field> 38481 <name>MUTEDETIE</name> 38482 <description>Mute detection interrupt 38483 enable</description> 38484 <bitOffset>1</bitOffset> 38485 <bitWidth>1</bitWidth> 38486 <enumeratedValues><name>MUTEDETIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Interrupt is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt is enabled</description><value>1</value></enumeratedValue></enumeratedValues> 38487 </field> 38488 <field> 38489 <name>WCKCFGIE</name> 38490 <description>Wrong clock configuration interrupt 38491 enable</description> 38492 <bitOffset>2</bitOffset> 38493 <bitWidth>1</bitWidth> 38494 <enumeratedValues><name>WCKCFGIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Interrupt is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt is enabled</description><value>1</value></enumeratedValue></enumeratedValues> 38495 </field> 38496 <field> 38497 <name>FREQIE</name> 38498 <description>FIFO request interrupt 38499 enable</description> 38500 <bitOffset>3</bitOffset> 38501 <bitWidth>1</bitWidth> 38502 <enumeratedValues><name>FREQIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Interrupt is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt is enabled</description><value>1</value></enumeratedValue></enumeratedValues> 38503 </field> 38504 <field> 38505 <name>CNRDYIE</name> 38506 <description>Codec not ready interrupt 38507 enable</description> 38508 <bitOffset>4</bitOffset> 38509 <bitWidth>1</bitWidth> 38510 <enumeratedValues><name>CNRDYIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Interrupt is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt is enabled</description><value>1</value></enumeratedValue></enumeratedValues> 38511 </field> 38512 <field> 38513 <name>AFSDETIE</name> 38514 <description>Anticipated frame synchronization 38515 detection interrupt enable</description> 38516 <bitOffset>5</bitOffset> 38517 <bitWidth>1</bitWidth> 38518 <enumeratedValues><name>AFSDETIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Interrupt is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt is enabled</description><value>1</value></enumeratedValue></enumeratedValues> 38519 </field> 38520 <field> 38521 <name>LFSDETIE</name> 38522 <description>Late frame synchronization detection 38523 interrupt enable</description> 38524 <bitOffset>6</bitOffset> 38525 <bitWidth>1</bitWidth> 38526 <enumeratedValues><name>LFSDETIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Interrupt is disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Interrupt is enabled</description><value>1</value></enumeratedValue></enumeratedValues> 38527 </field> 38528 </fields> 38529 </register> 38530 <register> 38531 <name>SR</name> 38532 <displayName>ASR</displayName> 38533 <description>SAI AStatus register</description> 38534 <addressOffset>0x14</addressOffset> 38535 <size>0x20</size> 38536 <access>read-only</access> 38537 <resetValue>0x00000008</resetValue> 38538 <fields> 38539 <field> 38540 <name>OVRUDR</name> 38541 <description>Overrun / underrun</description> 38542 <bitOffset>0</bitOffset> 38543 <bitWidth>1</bitWidth> 38544 <enumeratedValues><name>OVRUDRR</name><usage>read</usage><enumeratedValue><name>NoError</name><description>No overrun/underrun error</description><value>0</value></enumeratedValue><enumeratedValue><name>Overrun</name><description>Overrun/underrun error detection</description><value>1</value></enumeratedValue></enumeratedValues> 38545 </field> 38546 <field> 38547 <name>MUTEDET</name> 38548 <description>Mute detection</description> 38549 <bitOffset>1</bitOffset> 38550 <bitWidth>1</bitWidth> 38551 <enumeratedValues><name>MUTEDETR</name><usage>read</usage><enumeratedValue><name>NoMute</name><description>No MUTE detection on the SD input line</description><value>0</value></enumeratedValue><enumeratedValue><name>Mute</name><description>MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame</description><value>1</value></enumeratedValue></enumeratedValues> 38552 </field> 38553 <field> 38554 <name>WCKCFG</name> 38555 <description>Wrong clock configuration 38556 flag</description> 38557 <bitOffset>2</bitOffset> 38558 <bitWidth>1</bitWidth> 38559 <enumeratedValues><name>WCKCFGR</name><usage>read</usage><enumeratedValue><name>Correct</name><description>Clock configuration is correct</description><value>0</value></enumeratedValue><enumeratedValue><name>Wrong</name><description>Clock configuration does not respect the rule concerning the frame length specification</description><value>1</value></enumeratedValue></enumeratedValues> 38560 </field> 38561 <field> 38562 <name>FREQ</name> 38563 <description>FIFO request</description> 38564 <bitOffset>3</bitOffset> 38565 <bitWidth>1</bitWidth> 38566 <enumeratedValues><name>FREQR</name><usage>read</usage><enumeratedValue><name>NoRequest</name><description>No FIFO request</description><value>0</value></enumeratedValue><enumeratedValue><name>Request</name><description>FIFO request to read or to write the SAI_xDR</description><value>1</value></enumeratedValue></enumeratedValues> 38567 </field> 38568 <field> 38569 <name>CNRDY</name> 38570 <description>Codec not ready</description> 38571 <bitOffset>4</bitOffset> 38572 <bitWidth>1</bitWidth> 38573 <enumeratedValues><name>CNRDYR</name><usage>read</usage><enumeratedValue><name>Ready</name><description>External AC’97 Codec is ready</description><value>0</value></enumeratedValue><enumeratedValue><name>NotReady</name><description>External AC’97 Codec is not ready</description><value>1</value></enumeratedValue></enumeratedValues> 38574 </field> 38575 <field> 38576 <name>AFSDET</name> 38577 <description>Anticipated frame synchronization 38578 detection</description> 38579 <bitOffset>5</bitOffset> 38580 <bitWidth>1</bitWidth> 38581 <enumeratedValues><name>AFSDETR</name><usage>read</usage><enumeratedValue><name>NoError</name><description>No error</description><value>0</value></enumeratedValue><enumeratedValue><name>EarlySync</name><description>Frame synchronization signal is detected earlier than expected</description><value>1</value></enumeratedValue></enumeratedValues> 38582 </field> 38583 <field> 38584 <name>LFSDET</name> 38585 <description>Late frame synchronization 38586 detection</description> 38587 <bitOffset>6</bitOffset> 38588 <bitWidth>1</bitWidth> 38589 <enumeratedValues><name>LFSDETR</name><usage>read</usage><enumeratedValue><name>NoError</name><description>No error</description><value>0</value></enumeratedValue><enumeratedValue><name>NoSync</name><description>Frame synchronization signal is not present at the right time</description><value>1</value></enumeratedValue></enumeratedValues> 38590 </field> 38591 <field> 38592 <name>FLVL</name> 38593 <description>FIFO level threshold</description> 38594 <bitOffset>16</bitOffset> 38595 <bitWidth>3</bitWidth> 38596 <enumeratedValues><name>FLVLR</name><usage>read</usage><enumeratedValue><name>Empty</name><description>FIFO empty</description><value>0</value></enumeratedValue><enumeratedValue><name>Quarter1</name><description>FIFO <= 1⁄4 but not empty</description><value>1</value></enumeratedValue><enumeratedValue><name>Quarter2</name><description>1⁄4 < FIFO <= 1⁄2</description><value>2</value></enumeratedValue><enumeratedValue><name>Quarter3</name><description>1⁄2 < FIFO <= 3⁄4</description><value>3</value></enumeratedValue><enumeratedValue><name>Quarter4</name><description>3⁄4 < FIFO but not full</description><value>4</value></enumeratedValue><enumeratedValue><name>Full</name><description>FIFO full</description><value>5</value></enumeratedValue></enumeratedValues> 38597 </field> 38598 </fields> 38599 </register> 38600 <register> 38601 <name>CLRFR</name> 38602 <displayName>ACLRFR</displayName> 38603 <description>SAI AClear flag register</description> 38604 <addressOffset>0x18</addressOffset> 38605 <size>0x20</size> 38606 <access>read-write</access> 38607 <resetValue>0x00000000</resetValue> 38608 <fields> 38609 <field> 38610 <name>COVRUDR</name> 38611 <description>Clear overrun / underrun</description> 38612 <bitOffset>0</bitOffset> 38613 <bitWidth>1</bitWidth> 38614 <enumeratedValues><name>COVRUDRW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clears the OVRUDR flag</description><value>1</value></enumeratedValue></enumeratedValues> 38615 </field> 38616 <field> 38617 <name>CMUTEDET</name> 38618 <description>Mute detection flag</description> 38619 <bitOffset>1</bitOffset> 38620 <bitWidth>1</bitWidth> 38621 <enumeratedValues><name>CMUTEDETW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clears the MUTEDET flag</description><value>1</value></enumeratedValue></enumeratedValues> 38622 </field> 38623 <field> 38624 <name>CWCKCFG</name> 38625 <description>Clear wrong clock configuration 38626 flag</description> 38627 <bitOffset>2</bitOffset> 38628 <bitWidth>1</bitWidth> 38629 <enumeratedValues><name>CWCKCFGW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clears the WCKCFG flag</description><value>1</value></enumeratedValue></enumeratedValues> 38630 </field> 38631 <field> 38632 <name>CCNRDY</name> 38633 <description>Clear codec not ready flag</description> 38634 <bitOffset>4</bitOffset> 38635 <bitWidth>1</bitWidth> 38636 <enumeratedValues><name>CCNRDYW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clears the CNRDY flag</description><value>1</value></enumeratedValue></enumeratedValues> 38637 </field> 38638 <field> 38639 <name>CAFSDET</name> 38640 <description>Clear anticipated frame synchronization 38641 detection flag</description> 38642 <bitOffset>5</bitOffset> 38643 <bitWidth>1</bitWidth> 38644 <enumeratedValues><name>CAFSDETW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clears the AFSDET flag</description><value>1</value></enumeratedValue></enumeratedValues> 38645 </field> 38646 <field> 38647 <name>CLFSDET</name> 38648 <description>Clear late frame synchronization 38649 detection flag</description> 38650 <bitOffset>6</bitOffset> 38651 <bitWidth>1</bitWidth> 38652 <enumeratedValues><name>CLFSDETW</name><usage>write</usage><enumeratedValue><name>Clear</name><description>Clears the LFSDET flag</description><value>1</value></enumeratedValue></enumeratedValues> 38653 </field> 38654 </fields> 38655 </register> 38656 <register> 38657 <name>DR</name> 38658 <displayName>ADR</displayName> 38659 <description>SAI AData register</description> 38660 <addressOffset>0x1c</addressOffset> 38661 <size>0x20</size> 38662 <access>read-write</access> 38663 <resetValue>0x00000000</resetValue> 38664 <fields> 38665 <field> 38666 <name>DATA</name> 38667 <description>Data</description> 38668 <bitOffset>0</bitOffset> 38669 <bitWidth>32</bitWidth> 38670 </field> 38671 </fields> 38672 </register> 38673 </cluster></registers> 38674 </peripheral> 38675 <peripheral> 38676 <name>LTDC</name> 38677 <description>LCD-TFT Controller</description> 38678 <groupName>LTDC</groupName> 38679 <baseAddress>0x40016800</baseAddress> 38680 <addressBlock> 38681 <offset>0x0</offset> 38682 <size>0x400</size> 38683 <usage>registers</usage> 38684 </addressBlock> 38685 <interrupt> 38686 <name>LCD_TFT</name> 38687 <description>LTDC global interrupt</description> 38688 <value>88</value> 38689 </interrupt> 38690 <interrupt> 38691 <name>LCD_TFT_1</name> 38692 <description>LTDC global error interrupt</description> 38693 <value>89</value> 38694 </interrupt> 38695 <registers> 38696 <cluster><dim>2</dim><dimIncrement>0x80</dimIncrement><dimIndex>1,2</dimIndex><name>LAYER%s</name><description>Cluster LAYER%s, containing L?CR, L?WHPCR, L?WVPCR, L?CKCR, L?PFCR, L?CACR, L?DCCR, L?BFCR, L?CFBAR, L?CFBLR, L?CFBLNR, L?CLUTWR</description><addressOffset>0x84</addressOffset><register> 38697 <name>CR</name> 38698 <displayName>L1CR</displayName> 38699 <description>Layerx Control Register</description> 38700 <addressOffset>0x0</addressOffset> 38701 <size>0x20</size> 38702 <access>read-write</access> 38703 <resetValue>0x00000000</resetValue> 38704 <fields> 38705 <field> 38706 <name>CLUTEN</name> 38707 <description>Color Look-Up Table Enable</description> 38708 <bitOffset>4</bitOffset> 38709 <bitWidth>1</bitWidth> 38710 <enumeratedValues><name>CLUTEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Color look-up table disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Color look-up table enabled</description><value>1</value></enumeratedValue></enumeratedValues> 38711 </field> 38712 <field> 38713 <name>COLKEN</name> 38714 <description>Color Keying Enable</description> 38715 <bitOffset>1</bitOffset> 38716 <bitWidth>1</bitWidth> 38717 <enumeratedValues><name>COLKEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Color keying disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Color keying enabled</description><value>1</value></enumeratedValue></enumeratedValues> 38718 </field> 38719 <field> 38720 <name>LEN</name> 38721 <description>Layer Enable</description> 38722 <bitOffset>0</bitOffset> 38723 <bitWidth>1</bitWidth> 38724 <enumeratedValues><name>LEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Layer disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Layer enabled</description><value>1</value></enumeratedValue></enumeratedValues> 38725 </field> 38726 </fields> 38727 </register> 38728 <register> 38729 <name>WHPCR</name> 38730 <displayName>L1WHPCR</displayName> 38731 <description>Layerx Window Horizontal Position 38732 Configuration Register</description> 38733 <addressOffset>0x4</addressOffset> 38734 <size>0x20</size> 38735 <access>read-write</access> 38736 <resetValue>0x00000000</resetValue> 38737 <fields> 38738 <field> 38739 <name>WHSPPOS</name> 38740 <description>Window Horizontal Stop 38741 Position</description> 38742 <bitOffset>16</bitOffset> 38743 <bitWidth>12</bitWidth> 38744 <writeConstraint><range><minimum>0</minimum><maximum>4095</maximum></range></writeConstraint> 38745 </field> 38746 <field> 38747 <name>WHSTPOS</name> 38748 <description>Window Horizontal Start 38749 Position</description> 38750 <bitOffset>0</bitOffset> 38751 <bitWidth>12</bitWidth> 38752 <writeConstraint><range><minimum>0</minimum><maximum>4095</maximum></range></writeConstraint> 38753 </field> 38754 </fields> 38755 </register> 38756 <register> 38757 <name>WVPCR</name> 38758 <displayName>L1WVPCR</displayName> 38759 <description>Layerx Window Vertical Position 38760 Configuration Register</description> 38761 <addressOffset>0x8</addressOffset> 38762 <size>0x20</size> 38763 <access>read-write</access> 38764 <resetValue>0x00000000</resetValue> 38765 <fields> 38766 <field> 38767 <name>WVSPPOS</name> 38768 <description>Window Vertical Stop 38769 Position</description> 38770 <bitOffset>16</bitOffset> 38771 <bitWidth>11</bitWidth> 38772 <writeConstraint><range><minimum>0</minimum><maximum>2047</maximum></range></writeConstraint> 38773 </field> 38774 <field> 38775 <name>WVSTPOS</name> 38776 <description>Window Vertical Start 38777 Position</description> 38778 <bitOffset>0</bitOffset> 38779 <bitWidth>11</bitWidth> 38780 <writeConstraint><range><minimum>0</minimum><maximum>2047</maximum></range></writeConstraint> 38781 </field> 38782 </fields> 38783 </register> 38784 <register> 38785 <name>CKCR</name> 38786 <displayName>L1CKCR</displayName> 38787 <description>Layerx Color Keying Configuration 38788 Register</description> 38789 <addressOffset>0xc</addressOffset> 38790 <size>0x20</size> 38791 <access>read-write</access> 38792 <resetValue>0x00000000</resetValue> 38793 <fields> 38794 <field> 38795 <name>CKRED</name> 38796 <description>Color Key Red value</description> 38797 <bitOffset>16</bitOffset> 38798 <bitWidth>8</bitWidth> 38799 <writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint> 38800 </field> 38801 <field> 38802 <name>CKGREEN</name> 38803 <description>Color Key Green value</description> 38804 <bitOffset>8</bitOffset> 38805 <bitWidth>8</bitWidth> 38806 <writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint> 38807 </field> 38808 <field> 38809 <name>CKBLUE</name> 38810 <description>Color Key Blue value</description> 38811 <bitOffset>0</bitOffset> 38812 <bitWidth>8</bitWidth> 38813 <writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint> 38814 </field> 38815 </fields> 38816 </register> 38817 <register> 38818 <name>PFCR</name> 38819 <displayName>L1PFCR</displayName> 38820 <description>Layerx Pixel Format Configuration 38821 Register</description> 38822 <addressOffset>0x10</addressOffset> 38823 <size>0x20</size> 38824 <access>read-write</access> 38825 <resetValue>0x00000000</resetValue> 38826 <fields> 38827 <field> 38828 <name>PF</name> 38829 <description>Pixel Format</description> 38830 <bitOffset>0</bitOffset> 38831 <bitWidth>3</bitWidth> 38832 <enumeratedValues><name>PF</name><usage>read-write</usage><enumeratedValue><name>ARGB8888</name><description>ARGB8888</description><value>0</value></enumeratedValue><enumeratedValue><name>RGB888</name><description>RGB888</description><value>1</value></enumeratedValue><enumeratedValue><name>RGB565</name><description>RGB565</description><value>2</value></enumeratedValue><enumeratedValue><name>ARGB1555</name><description>ARGB1555</description><value>3</value></enumeratedValue><enumeratedValue><name>ARGB4444</name><description>ARGB4444</description><value>4</value></enumeratedValue><enumeratedValue><name>L8</name><description>L8 (8-bit luminance)</description><value>5</value></enumeratedValue><enumeratedValue><name>AL44</name><description>AL44 (4-bit alpha, 4-bit luminance)</description><value>6</value></enumeratedValue><enumeratedValue><name>AL88</name><description>AL88 (8-bit alpha, 8-bit luminance)</description><value>7</value></enumeratedValue></enumeratedValues> 38833 </field> 38834 </fields> 38835 </register> 38836 <register> 38837 <name>CACR</name> 38838 <displayName>L1CACR</displayName> 38839 <description>Layerx Constant Alpha Configuration 38840 Register</description> 38841 <addressOffset>0x14</addressOffset> 38842 <size>0x20</size> 38843 <access>read-write</access> 38844 <resetValue>0x00000000</resetValue> 38845 <fields> 38846 <field> 38847 <name>CONSTA</name> 38848 <description>Constant Alpha</description> 38849 <bitOffset>0</bitOffset> 38850 <bitWidth>8</bitWidth> 38851 <writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint> 38852 </field> 38853 </fields> 38854 </register> 38855 <register> 38856 <name>DCCR</name> 38857 <displayName>L1DCCR</displayName> 38858 <description>Layerx Default Color Configuration 38859 Register</description> 38860 <addressOffset>0x18</addressOffset> 38861 <size>0x20</size> 38862 <access>read-write</access> 38863 <resetValue>0x00000000</resetValue> 38864 <fields> 38865 <field> 38866 <name>DCALPHA</name> 38867 <description>Default Color Alpha</description> 38868 <bitOffset>24</bitOffset> 38869 <bitWidth>8</bitWidth> 38870 <writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint> 38871 </field> 38872 <field> 38873 <name>DCRED</name> 38874 <description>Default Color Red</description> 38875 <bitOffset>16</bitOffset> 38876 <bitWidth>8</bitWidth> 38877 <writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint> 38878 </field> 38879 <field> 38880 <name>DCGREEN</name> 38881 <description>Default Color Green</description> 38882 <bitOffset>8</bitOffset> 38883 <bitWidth>8</bitWidth> 38884 <writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint> 38885 </field> 38886 <field> 38887 <name>DCBLUE</name> 38888 <description>Default Color Blue</description> 38889 <bitOffset>0</bitOffset> 38890 <bitWidth>8</bitWidth> 38891 <writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint> 38892 </field> 38893 </fields> 38894 </register> 38895 <register> 38896 <name>BFCR</name> 38897 <displayName>L1BFCR</displayName> 38898 <description>Layerx Blending Factors Configuration 38899 Register</description> 38900 <addressOffset>0x1c</addressOffset> 38901 <size>0x20</size> 38902 <access>read-write</access> 38903 <resetValue>0x00000607</resetValue> 38904 <fields> 38905 <field> 38906 <name>BF1</name> 38907 <description>Blending Factor 1</description> 38908 <bitOffset>8</bitOffset> 38909 <bitWidth>3</bitWidth> 38910 <enumeratedValues><name>BF1</name><usage>read-write</usage><enumeratedValue><name>Constant</name><description>BF1 = constant alpha</description><value>4</value></enumeratedValue><enumeratedValue><name>Pixel</name><description>BF1 = pixel alpha * constant alpha</description><value>6</value></enumeratedValue></enumeratedValues> 38911 </field> 38912 <field> 38913 <name>BF2</name> 38914 <description>Blending Factor 2</description> 38915 <bitOffset>0</bitOffset> 38916 <bitWidth>3</bitWidth> 38917 <enumeratedValues><name>BF2</name><usage>read-write</usage><enumeratedValue><name>Constant</name><description>BF2 = 1 - constant alpha</description><value>5</value></enumeratedValue><enumeratedValue><name>Pixel</name><description>BF2 = 1 - pixel alpha * constant alpha</description><value>7</value></enumeratedValue></enumeratedValues> 38918 </field> 38919 </fields> 38920 </register> 38921 <register> 38922 <name>CFBAR</name> 38923 <displayName>L1CFBAR</displayName> 38924 <description>Layerx Color Frame Buffer Address 38925 Register</description> 38926 <addressOffset>0x28</addressOffset> 38927 <size>0x20</size> 38928 <access>read-write</access> 38929 <resetValue>0x00000000</resetValue> 38930 <fields> 38931 <field> 38932 <name>CFBADD</name> 38933 <description>Color Frame Buffer Start 38934 Address</description> 38935 <bitOffset>0</bitOffset> 38936 <bitWidth>32</bitWidth> 38937 <writeConstraint><range><minimum>0</minimum><maximum>4294967295</maximum></range></writeConstraint> 38938 </field> 38939 </fields> 38940 </register> 38941 <register> 38942 <name>CFBLR</name> 38943 <displayName>L1CFBLR</displayName> 38944 <description>Layerx Color Frame Buffer Length 38945 Register</description> 38946 <addressOffset>0x2c</addressOffset> 38947 <size>0x20</size> 38948 <access>read-write</access> 38949 <resetValue>0x00000000</resetValue> 38950 <fields> 38951 <field> 38952 <name>CFBP</name> 38953 <description>Color Frame Buffer Pitch in 38954 bytes</description> 38955 <bitOffset>16</bitOffset> 38956 <bitWidth>13</bitWidth> 38957 <writeConstraint><range><minimum>0</minimum><maximum>8191</maximum></range></writeConstraint> 38958 </field> 38959 <field> 38960 <name>CFBLL</name> 38961 <description>Color Frame Buffer Line 38962 Length</description> 38963 <bitOffset>0</bitOffset> 38964 <bitWidth>13</bitWidth> 38965 <writeConstraint><range><minimum>0</minimum><maximum>8191</maximum></range></writeConstraint> 38966 </field> 38967 </fields> 38968 </register> 38969 <register> 38970 <name>CFBLNR</name> 38971 <displayName>L1CFBLNR</displayName> 38972 <description>Layerx ColorFrame Buffer Line Number 38973 Register</description> 38974 <addressOffset>0x30</addressOffset> 38975 <size>0x20</size> 38976 <access>read-write</access> 38977 <resetValue>0x00000000</resetValue> 38978 <fields> 38979 <field> 38980 <name>CFBLNBR</name> 38981 <description>Frame Buffer Line Number</description> 38982 <bitOffset>0</bitOffset> 38983 <bitWidth>11</bitWidth> 38984 <writeConstraint><range><minimum>0</minimum><maximum>2047</maximum></range></writeConstraint> 38985 </field> 38986 </fields> 38987 </register> 38988 <register> 38989 <name>CLUTWR</name> 38990 <displayName>L1CLUTWR</displayName> 38991 <description>Layerx CLUT Write Register</description> 38992 <addressOffset>0x40</addressOffset> 38993 <size>0x20</size> 38994 <access>write-only</access> 38995 <resetValue>0x00000000</resetValue> 38996 <fields> 38997 <field> 38998 <name>CLUTADD</name> 38999 <description>CLUT Address</description> 39000 <bitOffset>24</bitOffset> 39001 <bitWidth>8</bitWidth> 39002 <writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint> 39003 </field> 39004 <field> 39005 <name>RED</name> 39006 <description>Red value</description> 39007 <bitOffset>16</bitOffset> 39008 <bitWidth>8</bitWidth> 39009 <writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint> 39010 </field> 39011 <field> 39012 <name>GREEN</name> 39013 <description>Green value</description> 39014 <bitOffset>8</bitOffset> 39015 <bitWidth>8</bitWidth> 39016 <writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint> 39017 </field> 39018 <field> 39019 <name>BLUE</name> 39020 <description>Blue value</description> 39021 <bitOffset>0</bitOffset> 39022 <bitWidth>8</bitWidth> 39023 <writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint> 39024 </field> 39025 </fields> 39026 </register> 39027 </cluster><register> 39028 <name>SSCR</name> 39029 <displayName>SSCR</displayName> 39030 <description>Synchronization Size Configuration 39031 Register</description> 39032 <addressOffset>0x8</addressOffset> 39033 <size>0x20</size> 39034 <access>read-write</access> 39035 <resetValue>0x00000000</resetValue> 39036 <fields> 39037 <field> 39038 <name>HSW</name> 39039 <description>Horizontal Synchronization Width (in 39040 units of pixel clock period)</description> 39041 <bitOffset>16</bitOffset> 39042 <bitWidth>12</bitWidth> 39043 <writeConstraint><range><minimum>0</minimum><maximum>4095</maximum></range></writeConstraint> 39044 </field> 39045 <field> 39046 <name>VSH</name> 39047 <description>Vertical Synchronization Height (in 39048 units of horizontal scan line)</description> 39049 <bitOffset>0</bitOffset> 39050 <bitWidth>11</bitWidth> 39051 <writeConstraint><range><minimum>0</minimum><maximum>2047</maximum></range></writeConstraint> 39052 </field> 39053 </fields> 39054 </register> 39055 <register> 39056 <name>BPCR</name> 39057 <displayName>BPCR</displayName> 39058 <description>Back Porch Configuration 39059 Register</description> 39060 <addressOffset>0xC</addressOffset> 39061 <size>0x20</size> 39062 <access>read-write</access> 39063 <resetValue>0x00000000</resetValue> 39064 <fields> 39065 <field> 39066 <name>AHBP</name> 39067 <description>Accumulated Horizontal back porch (in 39068 units of pixel clock period)</description> 39069 <bitOffset>16</bitOffset> 39070 <bitWidth>12</bitWidth> 39071 <writeConstraint><range><minimum>0</minimum><maximum>4095</maximum></range></writeConstraint> 39072 </field> 39073 <field> 39074 <name>AVBP</name> 39075 <description>Accumulated Vertical back porch (in 39076 units of horizontal scan line)</description> 39077 <bitOffset>0</bitOffset> 39078 <bitWidth>11</bitWidth> 39079 <writeConstraint><range><minimum>0</minimum><maximum>2047</maximum></range></writeConstraint> 39080 </field> 39081 </fields> 39082 </register> 39083 <register> 39084 <name>AWCR</name> 39085 <displayName>AWCR</displayName> 39086 <description>Active Width Configuration 39087 Register</description> 39088 <addressOffset>0x10</addressOffset> 39089 <size>0x20</size> 39090 <access>read-write</access> 39091 <resetValue>0x00000000</resetValue> 39092 <fields> 39093 <field> 39094 <name>AAW</name> 39095 <description>Accumulated Active Width (in units of pixel clock period)</description> 39096 <bitOffset>16</bitOffset> 39097 <bitWidth>12</bitWidth> 39098 <writeConstraint><range><minimum>0</minimum><maximum>4095</maximum></range></writeConstraint> 39099 </field> 39100 <field> 39101 <name>AAH</name> 39102 <description>Accumulated Active Height (in units of 39103 horizontal scan line)</description> 39104 <bitOffset>0</bitOffset> 39105 <bitWidth>11</bitWidth> 39106 <writeConstraint><range><minimum>0</minimum><maximum>2047</maximum></range></writeConstraint> 39107 </field> 39108 </fields> 39109 </register> 39110 <register> 39111 <name>TWCR</name> 39112 <displayName>TWCR</displayName> 39113 <description>Total Width Configuration 39114 Register</description> 39115 <addressOffset>0x14</addressOffset> 39116 <size>0x20</size> 39117 <access>read-write</access> 39118 <resetValue>0x00000000</resetValue> 39119 <fields> 39120 <field> 39121 <name>TOTALW</name> 39122 <description>Total Width (in units of pixel clock 39123 period)</description> 39124 <bitOffset>16</bitOffset> 39125 <bitWidth>12</bitWidth> 39126 <writeConstraint><range><minimum>0</minimum><maximum>4095</maximum></range></writeConstraint> 39127 </field> 39128 <field> 39129 <name>TOTALH</name> 39130 <description>Total Height (in units of horizontal 39131 scan line)</description> 39132 <bitOffset>0</bitOffset> 39133 <bitWidth>11</bitWidth> 39134 <writeConstraint><range><minimum>0</minimum><maximum>2047</maximum></range></writeConstraint> 39135 </field> 39136 </fields> 39137 </register> 39138 <register> 39139 <name>GCR</name> 39140 <displayName>GCR</displayName> 39141 <description>Global Control Register</description> 39142 <addressOffset>0x18</addressOffset> 39143 <size>0x20</size> 39144 <resetValue>0x00002220</resetValue> 39145 <fields> 39146 <field> 39147 <name>HSPOL</name> 39148 <description>Horizontal Synchronization 39149 Polarity</description> 39150 <bitOffset>31</bitOffset> 39151 <bitWidth>1</bitWidth> 39152 <access>read-write</access> 39153 <enumeratedValues><name>HSPOL</name><usage>read-write</usage><enumeratedValue><name>ActiveLow</name><description>Horizontal synchronization polarity is active low</description><value>0</value></enumeratedValue><enumeratedValue><name>ActiveHigh</name><description>Horizontal synchronization polarity is active high</description><value>1</value></enumeratedValue></enumeratedValues> 39154 </field> 39155 <field> 39156 <name>VSPOL</name> 39157 <description>Vertical Synchronization 39158 Polarity</description> 39159 <bitOffset>30</bitOffset> 39160 <bitWidth>1</bitWidth> 39161 <access>read-write</access> 39162 <enumeratedValues><name>VSPOL</name><usage>read-write</usage><enumeratedValue><name>ActiveLow</name><description>Vertical synchronization polarity is active low</description><value>0</value></enumeratedValue><enumeratedValue><name>ActiveHigh</name><description>Vertical synchronization polarity is active high</description><value>1</value></enumeratedValue></enumeratedValues> 39163 </field> 39164 <field> 39165 <name>DEPOL</name> 39166 <description>Data Enable Polarity</description> 39167 <bitOffset>29</bitOffset> 39168 <bitWidth>1</bitWidth> 39169 <access>read-write</access> 39170 <enumeratedValues><name>DEPOL</name><usage>read-write</usage><enumeratedValue><name>ActiveLow</name><description>Data enable polarity is active low</description><value>0</value></enumeratedValue><enumeratedValue><name>ActiveHigh</name><description>Data enable polarity is active high</description><value>1</value></enumeratedValue></enumeratedValues> 39171 </field> 39172 <field> 39173 <name>PCPOL</name> 39174 <description>Pixel Clock Polarity</description> 39175 <bitOffset>28</bitOffset> 39176 <bitWidth>1</bitWidth> 39177 <access>read-write</access> 39178 <enumeratedValues><name>PCPOL</name><usage>read-write</usage><enumeratedValue><name>RisingEdge</name><description>Pixel clock on rising edge</description><value>0</value></enumeratedValue><enumeratedValue><name>FallingEdge</name><description>Pixel clock on falling edge</description><value>1</value></enumeratedValue></enumeratedValues> 39179 </field> 39180 <field> 39181 <name>DEN</name> 39182 <description>Dither Enable</description> 39183 <bitOffset>16</bitOffset> 39184 <bitWidth>1</bitWidth> 39185 <access>read-write</access> 39186 <enumeratedValues><name>DEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Dither disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Dither enabled</description><value>1</value></enumeratedValue></enumeratedValues> 39187 </field> 39188 <field> 39189 <name>DRW</name> 39190 <description>Dither Red Width</description> 39191 <bitOffset>12</bitOffset> 39192 <bitWidth>3</bitWidth> 39193 <access>read-only</access> 39194 </field> 39195 <field> 39196 <name>DGW</name> 39197 <description>Dither Green Width</description> 39198 <bitOffset>8</bitOffset> 39199 <bitWidth>3</bitWidth> 39200 <access>read-only</access> 39201 </field> 39202 <field> 39203 <name>DBW</name> 39204 <description>Dither Blue Width</description> 39205 <bitOffset>4</bitOffset> 39206 <bitWidth>3</bitWidth> 39207 <access>read-only</access> 39208 </field> 39209 <field> 39210 <name>LTDCEN</name> 39211 <description>LCD-TFT controller enable 39212 bit</description> 39213 <bitOffset>0</bitOffset> 39214 <bitWidth>1</bitWidth> 39215 <access>read-write</access> 39216 <enumeratedValues><name>LTDCEN</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>LCD-TFT controller disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>LCD-TFT controller enabled</description><value>1</value></enumeratedValue></enumeratedValues> 39217 </field> 39218 </fields> 39219 </register> 39220 <register> 39221 <name>SRCR</name> 39222 <displayName>SRCR</displayName> 39223 <description>Shadow Reload Configuration 39224 Register</description> 39225 <addressOffset>0x24</addressOffset> 39226 <size>0x20</size> 39227 <access>read-write</access> 39228 <resetValue>0x00000000</resetValue> 39229 <fields> 39230 <field> 39231 <name>VBR</name> 39232 <description>Vertical Blanking Reload</description> 39233 <bitOffset>1</bitOffset> 39234 <bitWidth>1</bitWidth> 39235 <enumeratedValues><name>VBR</name><usage>read-write</usage><enumeratedValue><name>Reload</name><description>The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area).</description><value>1</value></enumeratedValue><enumeratedValue><name>NoEffect</name><description>This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set)</description><value>0</value></enumeratedValue></enumeratedValues> 39236 </field> 39237 <field> 39238 <name>IMR</name> 39239 <description>Immediate Reload</description> 39240 <bitOffset>0</bitOffset> 39241 <bitWidth>1</bitWidth> 39242 <enumeratedValues><name>IMR</name><usage>read-write</usage><enumeratedValue><name>Reload</name><description>The shadow registers are reloaded immediately. This bit is set by software and cleared only by hardware after reload</description><value>1</value></enumeratedValue><enumeratedValue><name>NoEffect</name><description>This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set)</description><value>0</value></enumeratedValue></enumeratedValues> 39243 </field> 39244 </fields> 39245 </register> 39246 <register> 39247 <name>BCCR</name> 39248 <displayName>BCCR</displayName> 39249 <description>Background Color Configuration 39250 Register</description> 39251 <addressOffset>0x2C</addressOffset> 39252 <size>0x20</size> 39253 <access>read-write</access> 39254 <resetValue>0x00000000</resetValue> 39255 <fields> 39256 <field><name>BCBLUE</name><description>Background color blue value</description><bitOffset>0</bitOffset><bitWidth>8</bitWidth><writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint> 39257 </field> 39258 <field><name>BCGREEN</name><description>Background color green value</description><bitOffset>8</bitOffset><bitWidth>8</bitWidth><writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint> 39259 </field> 39260 <field><name>BCRED</name><description>Background color red value</description><bitOffset>16</bitOffset><bitWidth>8</bitWidth><writeConstraint><range><minimum>0</minimum><maximum>255</maximum></range></writeConstraint> 39261 </field> 39262 </fields> 39263 </register> 39264 <register> 39265 <name>IER</name> 39266 <displayName>IER</displayName> 39267 <description>Interrupt Enable Register</description> 39268 <addressOffset>0x34</addressOffset> 39269 <size>0x20</size> 39270 <access>read-write</access> 39271 <resetValue>0x00000000</resetValue> 39272 <fields> 39273 <field> 39274 <name>RRIE</name> 39275 <description>Register Reload interrupt 39276 enable</description> 39277 <bitOffset>3</bitOffset> 39278 <bitWidth>1</bitWidth> 39279 <enumeratedValues><name>RRIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Register reload interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Register reload interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 39280 </field> 39281 <field> 39282 <name>TERRIE</name> 39283 <description>Transfer Error Interrupt 39284 Enable</description> 39285 <bitOffset>2</bitOffset> 39286 <bitWidth>1</bitWidth> 39287 <enumeratedValues><name>TERRIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Transfer error interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Transfer error interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 39288 </field> 39289 <field> 39290 <name>FUIE</name> 39291 <description>FIFO Underrun Interrupt 39292 Enable</description> 39293 <bitOffset>1</bitOffset> 39294 <bitWidth>1</bitWidth> 39295 <enumeratedValues><name>FUIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>FIFO underrun interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>FIFO underrun interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 39296 </field> 39297 <field> 39298 <name>LIE</name> 39299 <description>Line Interrupt Enable</description> 39300 <bitOffset>0</bitOffset> 39301 <bitWidth>1</bitWidth> 39302 <enumeratedValues><name>LIE</name><usage>read-write</usage><enumeratedValue><name>Disabled</name><description>Line interrupt disabled</description><value>0</value></enumeratedValue><enumeratedValue><name>Enabled</name><description>Line interrupt enabled</description><value>1</value></enumeratedValue></enumeratedValues> 39303 </field> 39304 </fields> 39305 </register> 39306 <register> 39307 <name>ISR</name> 39308 <displayName>ISR</displayName> 39309 <description>Interrupt Status Register</description> 39310 <addressOffset>0x38</addressOffset> 39311 <size>0x20</size> 39312 <access>read-only</access> 39313 <resetValue>0x00000000</resetValue> 39314 <fields> 39315 <field> 39316 <name>RRIF</name> 39317 <description>Register Reload Interrupt 39318 Flag</description> 39319 <bitOffset>3</bitOffset> 39320 <bitWidth>1</bitWidth> 39321 <enumeratedValues><name>RRIF</name><usage>read-write</usage><enumeratedValue><name>NoReload</name><description>No register reload</description><value>0</value></enumeratedValue><enumeratedValue><name>Reload</name><description>Register reload interrupt generated when a vertical blanking reload occurs (and the first line after the active area is reached)</description><value>1</value></enumeratedValue></enumeratedValues> 39322 </field> 39323 <field> 39324 <name>TERRIF</name> 39325 <description>Transfer Error interrupt 39326 flag</description> 39327 <bitOffset>2</bitOffset> 39328 <bitWidth>1</bitWidth> 39329 <enumeratedValues><name>TERRIF</name><usage>read-write</usage><enumeratedValue><name>NoError</name><description>No transfer error</description><value>0</value></enumeratedValue><enumeratedValue><name>Error</name><description>Transfer error interrupt generated when a bus error occurs</description><value>1</value></enumeratedValue></enumeratedValues> 39330 </field> 39331 <field> 39332 <name>FUIF</name> 39333 <description>FIFO Underrun Interrupt 39334 flag</description> 39335 <bitOffset>1</bitOffset> 39336 <bitWidth>1</bitWidth> 39337 <enumeratedValues><name>FUIF</name><usage>read-write</usage><enumeratedValue><name>NoUnderrun</name><description>No FIFO underrun</description><value>0</value></enumeratedValue><enumeratedValue><name>Underrun</name><description>FIFO underrun interrupt generated, if one of the layer FIFOs is empty and pixel data is read from the FIFO</description><value>1</value></enumeratedValue></enumeratedValues> 39338 </field> 39339 <field> 39340 <name>LIF</name> 39341 <description>Line Interrupt flag</description> 39342 <bitOffset>0</bitOffset> 39343 <bitWidth>1</bitWidth> 39344 <enumeratedValues><name>LIF</name><usage>read-write</usage><enumeratedValue><name>NotReached</name><description>Programmed line not reached</description><value>0</value></enumeratedValue><enumeratedValue><name>Reached</name><description>Line interrupt generated when a programmed line is reached</description><value>1</value></enumeratedValue></enumeratedValues> 39345 </field> 39346 </fields> 39347 </register> 39348 <register> 39349 <name>ICR</name> 39350 <displayName>ICR</displayName> 39351 <description>Interrupt Clear Register</description> 39352 <addressOffset>0x3C</addressOffset> 39353 <size>0x20</size> 39354 <access>write-only</access> 39355 <resetValue>0x00000000</resetValue> 39356 <fields> 39357 <field> 39358 <name>CRRIF</name> 39359 <description>Clears Register Reload Interrupt 39360 Flag</description> 39361 <bitOffset>3</bitOffset> 39362 <bitWidth>1</bitWidth> 39363 <enumeratedValues><name>CRRIF</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>Clears the RRIF flag in the ISR register</description><value>1</value></enumeratedValue></enumeratedValues> 39364 </field> 39365 <field> 39366 <name>CTERRIF</name> 39367 <description>Clears the Transfer Error Interrupt 39368 Flag</description> 39369 <bitOffset>2</bitOffset> 39370 <bitWidth>1</bitWidth> 39371 <enumeratedValues><name>CTERRIF</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>Clears the TERRIF flag in the ISR register</description><value>1</value></enumeratedValue></enumeratedValues> 39372 </field> 39373 <field> 39374 <name>CFUIF</name> 39375 <description>Clears the FIFO Underrun Interrupt 39376 flag</description> 39377 <bitOffset>1</bitOffset> 39378 <bitWidth>1</bitWidth> 39379 <enumeratedValues><name>CFUIF</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>Clears the FUIF flag in the ISR register</description><value>1</value></enumeratedValue></enumeratedValues> 39380 </field> 39381 <field> 39382 <name>CLIF</name> 39383 <description>Clears the Line Interrupt 39384 Flag</description> 39385 <bitOffset>0</bitOffset> 39386 <bitWidth>1</bitWidth> 39387 <enumeratedValues><name>CLIF</name><usage>read-write</usage><enumeratedValue><name>Clear</name><description>Clears the LIF flag in the ISR register</description><value>1</value></enumeratedValue></enumeratedValues> 39388 </field> 39389 </fields> 39390 </register> 39391 <register> 39392 <name>LIPCR</name> 39393 <displayName>LIPCR</displayName> 39394 <description>Line Interrupt Position Configuration 39395 Register</description> 39396 <addressOffset>0x40</addressOffset> 39397 <size>0x20</size> 39398 <access>read-write</access> 39399 <resetValue>0x00000000</resetValue> 39400 <fields> 39401 <field> 39402 <name>LIPOS</name> 39403 <description>Line Interrupt Position</description> 39404 <bitOffset>0</bitOffset> 39405 <bitWidth>11</bitWidth> 39406 <writeConstraint><range><minimum>0</minimum><maximum>2047</maximum></range></writeConstraint> 39407 </field> 39408 </fields> 39409 </register> 39410 <register> 39411 <name>CPSR</name> 39412 <displayName>CPSR</displayName> 39413 <description>Current Position Status 39414 Register</description> 39415 <addressOffset>0x44</addressOffset> 39416 <size>0x20</size> 39417 <access>read-only</access> 39418 <resetValue>0x00000000</resetValue> 39419 <fields> 39420 <field> 39421 <name>CXPOS</name> 39422 <description>Current X Position</description> 39423 <bitOffset>16</bitOffset> 39424 <bitWidth>16</bitWidth> 39425 </field> 39426 <field> 39427 <name>CYPOS</name> 39428 <description>Current Y Position</description> 39429 <bitOffset>0</bitOffset> 39430 <bitWidth>16</bitWidth> 39431 </field> 39432 </fields> 39433 </register> 39434 <register> 39435 <name>CDSR</name> 39436 <displayName>CDSR</displayName> 39437 <description>Current Display Status 39438 Register</description> 39439 <addressOffset>0x48</addressOffset> 39440 <size>0x20</size> 39441 <access>read-only</access> 39442 <resetValue>0x0000000F</resetValue> 39443 <fields> 39444 <field> 39445 <name>HSYNCS</name> 39446 <description>Horizontal Synchronization display 39447 Status</description> 39448 <bitOffset>3</bitOffset> 39449 <bitWidth>1</bitWidth> 39450 <enumeratedValues><name>HSYNCS</name><usage>read-write</usage><enumeratedValue><name>NotActive</name><description>Currently not in HSYNC phase</description><value>0</value></enumeratedValue><enumeratedValue><name>Active</name><description>Currently in HSYNC phase</description><value>1</value></enumeratedValue></enumeratedValues> 39451 </field> 39452 <field> 39453 <name>VSYNCS</name> 39454 <description>Vertical Synchronization display 39455 Status</description> 39456 <bitOffset>2</bitOffset> 39457 <bitWidth>1</bitWidth> 39458 <enumeratedValues><name>VSYNCS</name><usage>read-write</usage><enumeratedValue><name>NotActive</name><description>Currently not in VSYNC phase</description><value>0</value></enumeratedValue><enumeratedValue><name>Active</name><description>Currently in VSYNC phase</description><value>1</value></enumeratedValue></enumeratedValues> 39459 </field> 39460 <field> 39461 <name>HDES</name> 39462 <description>Horizontal Data Enable display 39463 Status</description> 39464 <bitOffset>1</bitOffset> 39465 <bitWidth>1</bitWidth> 39466 <enumeratedValues><name>HDES</name><usage>read-write</usage><enumeratedValue><name>NotActive</name><description>Currently not in horizontal Data Enable phase</description><value>0</value></enumeratedValue><enumeratedValue><name>Active</name><description>Currently in horizontal Data Enable phase</description><value>1</value></enumeratedValue></enumeratedValues> 39467 </field> 39468 <field> 39469 <name>VDES</name> 39470 <description>Vertical Data Enable display 39471 Status</description> 39472 <bitOffset>0</bitOffset> 39473 <bitWidth>1</bitWidth> 39474 <enumeratedValues><name>VDES</name><usage>read-write</usage><enumeratedValue><name>NotActive</name><description>Currently not in vertical Data Enable phase</description><value>0</value></enumeratedValue><enumeratedValue><name>Active</name><description>Currently in vertical Data Enable phase</description><value>1</value></enumeratedValue></enumeratedValues> 39475 </field> 39476 </fields> 39477 </register> 39478 </registers> 39479 </peripheral> 39480 <peripheral> 39481 <name>HASH</name> 39482 <description>Hash processor</description> 39483 <groupName>HASH</groupName> 39484 <baseAddress>0x50060400</baseAddress> 39485 <addressBlock> 39486 <offset>0x0</offset> 39487 <size>0x400</size> 39488 <usage>registers</usage> 39489 </addressBlock> 39490 <interrupt> 39491 <name>HASH_RNG</name> 39492 <description>Hash and Rng global interrupt</description> 39493 <value>80</value> 39494 </interrupt> 39495 <registers> 39496 <register> 39497 <name>CR</name> 39498 <displayName>CR</displayName> 39499 <description>control register</description> 39500 <addressOffset>0x0</addressOffset> 39501 <size>0x20</size> 39502 <resetValue>0x00000000</resetValue> 39503 <fields> 39504 <field> 39505 <name>INIT</name> 39506 <description>Initialize message digest 39507 calculation</description> 39508 <bitOffset>2</bitOffset> 39509 <bitWidth>1</bitWidth> 39510 <access>write-only</access> 39511 </field> 39512 <field> 39513 <name>DMAE</name> 39514 <description>DMA enable</description> 39515 <bitOffset>3</bitOffset> 39516 <bitWidth>1</bitWidth> 39517 <access>read-write</access> 39518 </field> 39519 <field> 39520 <name>DATATYPE</name> 39521 <description>Data type selection</description> 39522 <bitOffset>4</bitOffset> 39523 <bitWidth>2</bitWidth> 39524 <access>read-write</access> 39525 </field> 39526 <field> 39527 <name>MODE</name> 39528 <description>Mode selection</description> 39529 <bitOffset>6</bitOffset> 39530 <bitWidth>1</bitWidth> 39531 <access>read-write</access> 39532 </field> 39533 <field> 39534 <name>ALGO0</name> 39535 <description>Algorithm selection</description> 39536 <bitOffset>7</bitOffset> 39537 <bitWidth>1</bitWidth> 39538 <access>read-write</access> 39539 </field> 39540 <field> 39541 <name>NBW</name> 39542 <description>Number of words already 39543 pushed</description> 39544 <bitOffset>8</bitOffset> 39545 <bitWidth>4</bitWidth> 39546 <access>read-only</access> 39547 </field> 39548 <field> 39549 <name>DINNE</name> 39550 <description>DIN not empty</description> 39551 <bitOffset>12</bitOffset> 39552 <bitWidth>1</bitWidth> 39553 <access>read-only</access> 39554 </field> 39555 <field> 39556 <name>MDMAT</name> 39557 <description>Multiple DMA Transfers</description> 39558 <bitOffset>13</bitOffset> 39559 <bitWidth>1</bitWidth> 39560 <access>read-write</access> 39561 </field> 39562 <field> 39563 <name>LKEY</name> 39564 <description>Long key selection</description> 39565 <bitOffset>16</bitOffset> 39566 <bitWidth>1</bitWidth> 39567 <access>read-write</access> 39568 </field> 39569 <field> 39570 <name>ALGO1</name> 39571 <description>ALGO</description> 39572 <bitOffset>18</bitOffset> 39573 <bitWidth>1</bitWidth> 39574 <access>read-write</access> 39575 </field> 39576 </fields> 39577 </register> 39578 <register> 39579 <name>DIN</name> 39580 <displayName>DIN</displayName> 39581 <description>data input register</description> 39582 <addressOffset>0x4</addressOffset> 39583 <size>0x20</size> 39584 <access>read-write</access> 39585 <resetValue>0x00000000</resetValue> 39586 <fields> 39587 <field> 39588 <name>DATAIN</name> 39589 <description>Data input</description> 39590 <bitOffset>0</bitOffset> 39591 <bitWidth>32</bitWidth> 39592 </field> 39593 </fields> 39594 </register> 39595 <register> 39596 <name>STR</name> 39597 <displayName>STR</displayName> 39598 <description>start register</description> 39599 <addressOffset>0x8</addressOffset> 39600 <size>0x20</size> 39601 <resetValue>0x00000000</resetValue> 39602 <fields> 39603 <field> 39604 <name>DCAL</name> 39605 <description>Digest calculation</description> 39606 <bitOffset>8</bitOffset> 39607 <bitWidth>1</bitWidth> 39608 <access>write-only</access> 39609 </field> 39610 <field> 39611 <name>NBLW</name> 39612 <description>Number of valid bits in the last word of 39613 the message</description> 39614 <bitOffset>0</bitOffset> 39615 <bitWidth>5</bitWidth> 39616 <access>read-write</access> 39617 </field> 39618 </fields> 39619 </register> 39620 <register> 39621 <dim>5</dim><dimIncrement>0x4</dimIncrement><dimIndex>0,1,2,3,4</dimIndex><name>HR%s</name> 39622 <displayName>HR0</displayName> 39623 <description>digest registers</description> 39624 <addressOffset>0xC</addressOffset> 39625 <size>0x20</size> 39626 <access>read-only</access> 39627 <resetValue>0x00000000</resetValue> 39628 <fields> 39629 <field> 39630 <name>H</name> 39631 <description>H0</description> 39632 <bitOffset>0</bitOffset> 39633 <bitWidth>32</bitWidth> 39634 </field> 39635 </fields> 39636 </register> 39637 <register> 39638 <name>IMR</name> 39639 <displayName>IMR</displayName> 39640 <description>interrupt enable register</description> 39641 <addressOffset>0x20</addressOffset> 39642 <size>0x20</size> 39643 <access>read-write</access> 39644 <resetValue>0x00000000</resetValue> 39645 <fields> 39646 <field> 39647 <name>DCIE</name> 39648 <description>Digest calculation completion interrupt 39649 enable</description> 39650 <bitOffset>1</bitOffset> 39651 <bitWidth>1</bitWidth> 39652 </field> 39653 <field> 39654 <name>DINIE</name> 39655 <description>Data input interrupt 39656 enable</description> 39657 <bitOffset>0</bitOffset> 39658 <bitWidth>1</bitWidth> 39659 </field> 39660 </fields> 39661 </register> 39662 <register> 39663 <name>SR</name> 39664 <displayName>SR</displayName> 39665 <description>status register</description> 39666 <addressOffset>0x24</addressOffset> 39667 <size>0x20</size> 39668 <resetValue>0x00000001</resetValue> 39669 <fields> 39670 <field> 39671 <name>BUSY</name> 39672 <description>Busy bit</description> 39673 <bitOffset>3</bitOffset> 39674 <bitWidth>1</bitWidth> 39675 <access>read-only</access> 39676 </field> 39677 <field> 39678 <name>DMAS</name> 39679 <description>DMA Status</description> 39680 <bitOffset>2</bitOffset> 39681 <bitWidth>1</bitWidth> 39682 <access>read-only</access> 39683 </field> 39684 <field> 39685 <name>DCIS</name> 39686 <description>Digest calculation completion interrupt 39687 status</description> 39688 <bitOffset>1</bitOffset> 39689 <bitWidth>1</bitWidth> 39690 <access>read-write</access> 39691 </field> 39692 <field> 39693 <name>DINIS</name> 39694 <description>Data input interrupt 39695 status</description> 39696 <bitOffset>0</bitOffset> 39697 <bitWidth>1</bitWidth> 39698 <access>read-write</access> 39699 </field> 39700 </fields> 39701 </register> 39702 <register> 39703 <dim>54</dim><dimIncrement>0x4</dimIncrement><dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53</dimIndex><name>CSR%s</name> 39704 <displayName>CSR0</displayName> 39705 <description>context swap registers</description> 39706 <addressOffset>0xF8</addressOffset> 39707 <size>0x20</size> 39708 <access>read-write</access> 39709 <resetValue>0x00000000</resetValue> 39710 <fields> 39711 <field> 39712 <name>CSR</name> 39713 <description>CSR0</description> 39714 <bitOffset>0</bitOffset> 39715 <bitWidth>32</bitWidth> 39716 </field> 39717 </fields> 39718 </register> 39719 <register> 39720 <dim>8</dim><dimIncrement>0x4</dimIncrement><dimIndex>0,1,2,3,4,5,6,7</dimIndex><name>HASH_HR%s</name> 39721 <displayName>HASH_HR0</displayName> 39722 <description>HASH digest register</description> 39723 <addressOffset>0x310</addressOffset> 39724 <size>0x20</size> 39725 <access>read-only</access> 39726 <resetValue>0x00000000</resetValue> 39727 <fields> 39728 <field> 39729 <name>H</name> 39730 <description>H0</description> 39731 <bitOffset>0</bitOffset> 39732 <bitWidth>32</bitWidth> 39733 </field> 39734 </fields> 39735 </register> 39736 </registers> 39737 </peripheral> 39738 <peripheral> 39739 <name>CRYP</name> 39740 <description>Cryptographic processor</description> 39741 <groupName>CRYP</groupName> 39742 <baseAddress>0x50060000</baseAddress> 39743 <addressBlock> 39744 <offset>0x0</offset> 39745 <size>0x400</size> 39746 <usage>registers</usage> 39747 </addressBlock> 39748 <interrupt> 39749 <name>CRYP</name> 39750 <description>CRYP crypto global interrupt</description> 39751 <value>79</value> 39752 </interrupt> 39753 <registers> 39754 <cluster><dim>4</dim><dimIncrement>0x8</dimIncrement><dimIndex>0,1,2,3</dimIndex><name>KEY%s</name><description>Cluster KEY%s, containing K?LR, K?RR</description><addressOffset>0x20</addressOffset><register> 39755 <name>KLR</name> 39756 <displayName>K0LR</displayName> 39757 <description>key registers</description> 39758 <addressOffset>0x0</addressOffset> 39759 <size>0x20</size> 39760 <access>write-only</access> 39761 <resetValue>0x00000000</resetValue> 39762 <fields> 39763 <field><name>b2</name><description>b224</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields> 39764 </register> 39765 <register> 39766 <name>KRR</name> 39767 <displayName>K0RR</displayName> 39768 <description>key registers</description> 39769 <addressOffset>0x4</addressOffset> 39770 <size>0x20</size> 39771 <access>write-only</access> 39772 <resetValue>0x00000000</resetValue> 39773 <fields> 39774 <field><name>b</name><description>b192</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields> 39775 </register> 39776 </cluster><cluster><dim>2</dim><dimIncrement>0x8</dimIncrement><dimIndex>0,1</dimIndex><name>INIT%s</name><description>Cluster INIT%s, containing IV?LR, IV?RR</description><addressOffset>0x40</addressOffset><register> 39777 <name>IVLR</name> 39778 <displayName>IV0LR</displayName> 39779 <description>initialization vector 39780 registers</description> 39781 <addressOffset>0x0</addressOffset> 39782 <size>0x20</size> 39783 <access>read-write</access> 39784 <resetValue>0x00000000</resetValue> 39785 <fields> 39786 <field><name>IV</name><description>IV31</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields> 39787 </register> 39788 <register> 39789 <name>IVRR</name> 39790 <displayName>IV0RR</displayName> 39791 <description>initialization vector 39792 registers</description> 39793 <addressOffset>0x4</addressOffset> 39794 <size>0x20</size> 39795 <access>read-write</access> 39796 <resetValue>0x00000000</resetValue> 39797 <fields> 39798 <field><name>IV</name><description>IV63</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields> 39799 </register> 39800 </cluster><register> 39801 <name>CR</name> 39802 <displayName>CR</displayName> 39803 <description>control register</description> 39804 <addressOffset>0x0</addressOffset> 39805 <size>0x20</size> 39806 <resetValue>0x00000000</resetValue> 39807 <fields> 39808 <field> 39809 <name>ALGODIR</name> 39810 <description>Algorithm direction</description> 39811 <bitOffset>2</bitOffset> 39812 <bitWidth>1</bitWidth> 39813 <access>read-write</access> 39814 </field> 39815 <field> 39816 <name>ALGOMODE0</name> 39817 <description>Algorithm mode</description> 39818 <bitOffset>3</bitOffset> 39819 <bitWidth>3</bitWidth> 39820 <access>read-write</access> 39821 </field> 39822 <field> 39823 <name>DATATYPE</name> 39824 <description>Data type selection</description> 39825 <bitOffset>6</bitOffset> 39826 <bitWidth>2</bitWidth> 39827 <access>read-write</access> 39828 </field> 39829 <field> 39830 <name>KEYSIZE</name> 39831 <description>Key size selection (AES mode 39832 only)</description> 39833 <bitOffset>8</bitOffset> 39834 <bitWidth>2</bitWidth> 39835 <access>read-write</access> 39836 </field> 39837 <field> 39838 <name>FFLUSH</name> 39839 <description>FIFO flush</description> 39840 <bitOffset>14</bitOffset> 39841 <bitWidth>1</bitWidth> 39842 <access>write-only</access> 39843 </field> 39844 <field> 39845 <name>CRYPEN</name> 39846 <description>Cryptographic processor 39847 enable</description> 39848 <bitOffset>15</bitOffset> 39849 <bitWidth>1</bitWidth> 39850 <access>read-write</access> 39851 </field> 39852 <field> 39853 <name>GCM_CCMPH</name> 39854 <description>GCM_CCMPH</description> 39855 <bitOffset>16</bitOffset> 39856 <bitWidth>2</bitWidth> 39857 <access>read-write</access> 39858 </field> 39859 <field> 39860 <name>ALGOMODE3</name> 39861 <description>ALGOMODE</description> 39862 <bitOffset>19</bitOffset> 39863 <bitWidth>1</bitWidth> 39864 <access>read-write</access> 39865 </field> 39866 </fields> 39867 </register> 39868 <register> 39869 <name>SR</name> 39870 <displayName>SR</displayName> 39871 <description>status register</description> 39872 <addressOffset>0x4</addressOffset> 39873 <size>0x20</size> 39874 <access>read-only</access> 39875 <resetValue>0x00000003</resetValue> 39876 <fields> 39877 <field> 39878 <name>BUSY</name> 39879 <description>Busy bit</description> 39880 <bitOffset>4</bitOffset> 39881 <bitWidth>1</bitWidth> 39882 </field> 39883 <field> 39884 <name>OFFU</name> 39885 <description>Output FIFO full</description> 39886 <bitOffset>3</bitOffset> 39887 <bitWidth>1</bitWidth> 39888 </field> 39889 <field> 39890 <name>OFNE</name> 39891 <description>Output FIFO not empty</description> 39892 <bitOffset>2</bitOffset> 39893 <bitWidth>1</bitWidth> 39894 </field> 39895 <field> 39896 <name>IFNF</name> 39897 <description>Input FIFO not full</description> 39898 <bitOffset>1</bitOffset> 39899 <bitWidth>1</bitWidth> 39900 </field> 39901 <field> 39902 <name>IFEM</name> 39903 <description>Input FIFO empty</description> 39904 <bitOffset>0</bitOffset> 39905 <bitWidth>1</bitWidth> 39906 </field> 39907 </fields> 39908 </register> 39909 <register> 39910 <name>DIN</name> 39911 <displayName>DIN</displayName> 39912 <description>data input register</description> 39913 <addressOffset>0x8</addressOffset> 39914 <size>0x20</size> 39915 <access>read-write</access> 39916 <resetValue>0x00000000</resetValue> 39917 <fields> 39918 <field> 39919 <name>DATAIN</name> 39920 <description>Data input</description> 39921 <bitOffset>0</bitOffset> 39922 <bitWidth>32</bitWidth> 39923 </field> 39924 </fields> 39925 </register> 39926 <register> 39927 <name>DOUT</name> 39928 <displayName>DOUT</displayName> 39929 <description>data output register</description> 39930 <addressOffset>0xC</addressOffset> 39931 <size>0x20</size> 39932 <access>read-only</access> 39933 <resetValue>0x00000000</resetValue> 39934 <fields> 39935 <field> 39936 <name>DATAOUT</name> 39937 <description>Data output</description> 39938 <bitOffset>0</bitOffset> 39939 <bitWidth>32</bitWidth> 39940 </field> 39941 </fields> 39942 </register> 39943 <register> 39944 <name>DMACR</name> 39945 <displayName>DMACR</displayName> 39946 <description>DMA control register</description> 39947 <addressOffset>0x10</addressOffset> 39948 <size>0x20</size> 39949 <access>read-write</access> 39950 <resetValue>0x00000000</resetValue> 39951 <fields> 39952 <field> 39953 <name>DOEN</name> 39954 <description>DMA output enable</description> 39955 <bitOffset>1</bitOffset> 39956 <bitWidth>1</bitWidth> 39957 </field> 39958 <field> 39959 <name>DIEN</name> 39960 <description>DMA input enable</description> 39961 <bitOffset>0</bitOffset> 39962 <bitWidth>1</bitWidth> 39963 </field> 39964 </fields> 39965 </register> 39966 <register> 39967 <name>IMSCR</name> 39968 <displayName>IMSCR</displayName> 39969 <description>interrupt mask set/clear 39970 register</description> 39971 <addressOffset>0x14</addressOffset> 39972 <size>0x20</size> 39973 <access>read-write</access> 39974 <resetValue>0x00000000</resetValue> 39975 <fields> 39976 <field> 39977 <name>OUTIM</name> 39978 <description>Output FIFO service interrupt 39979 mask</description> 39980 <bitOffset>1</bitOffset> 39981 <bitWidth>1</bitWidth> 39982 </field> 39983 <field> 39984 <name>INIM</name> 39985 <description>Input FIFO service interrupt 39986 mask</description> 39987 <bitOffset>0</bitOffset> 39988 <bitWidth>1</bitWidth> 39989 </field> 39990 </fields> 39991 </register> 39992 <register> 39993 <name>RISR</name> 39994 <displayName>RISR</displayName> 39995 <description>raw interrupt status register</description> 39996 <addressOffset>0x18</addressOffset> 39997 <size>0x20</size> 39998 <access>read-only</access> 39999 <resetValue>0x00000001</resetValue> 40000 <fields> 40001 <field> 40002 <name>OUTRIS</name> 40003 <description>Output FIFO service raw interrupt 40004 status</description> 40005 <bitOffset>1</bitOffset> 40006 <bitWidth>1</bitWidth> 40007 </field> 40008 <field> 40009 <name>INRIS</name> 40010 <description>Input FIFO service raw interrupt 40011 status</description> 40012 <bitOffset>0</bitOffset> 40013 <bitWidth>1</bitWidth> 40014 </field> 40015 </fields> 40016 </register> 40017 <register> 40018 <name>MISR</name> 40019 <displayName>MISR</displayName> 40020 <description>masked interrupt status 40021 register</description> 40022 <addressOffset>0x1C</addressOffset> 40023 <size>0x20</size> 40024 <access>read-only</access> 40025 <resetValue>0x00000000</resetValue> 40026 <fields> 40027 <field> 40028 <name>OUTMIS</name> 40029 <description>Output FIFO service masked interrupt 40030 status</description> 40031 <bitOffset>1</bitOffset> 40032 <bitWidth>1</bitWidth> 40033 </field> 40034 <field> 40035 <name>INMIS</name> 40036 <description>Input FIFO service masked interrupt 40037 status</description> 40038 <bitOffset>0</bitOffset> 40039 <bitWidth>1</bitWidth> 40040 </field> 40041 </fields> 40042 </register> 40043 <register> 40044 <dim>8</dim><dimIncrement>0x4</dimIncrement><dimIndex>0,1,2,3,4,5,6,7</dimIndex><name>CSGCMCCM%sR</name> 40045 <displayName>CSGCMCCM0R</displayName> 40046 <description>context swap register</description> 40047 <addressOffset>0x50</addressOffset> 40048 <size>0x20</size> 40049 <access>read-write</access> 40050 <resetValue>0x00000000</resetValue> 40051 <fields> 40052 <field> 40053 <name>CSGCMCCM0R</name> 40054 <description>CSGCMCCM0R</description> 40055 <bitOffset>0</bitOffset> 40056 <bitWidth>32</bitWidth> 40057 </field> 40058 </fields> 40059 </register> 40060 <register> 40061 <dim>8</dim><dimIncrement>0x4</dimIncrement><dimIndex>0,1,2,3,4,5,6,7</dimIndex><name>CSGCM%sR</name> 40062 <displayName>CSGCM0R</displayName> 40063 <description>context swap register</description> 40064 <addressOffset>0x70</addressOffset> 40065 <size>0x20</size> 40066 <access>read-write</access> 40067 <resetValue>0x00000000</resetValue> 40068 <fields> 40069 <field> 40070 <name>CSGCMR</name> 40071 <description>CSGCM0R</description> 40072 <bitOffset>0</bitOffset> 40073 <bitWidth>32</bitWidth> 40074 </field> 40075 </fields> 40076 </register> 40077 </registers> 40078 </peripheral> 40079 <peripheral> 40080 <name>FPU</name> 40081 <description>Floting point unit</description> 40082 <groupName>FPU</groupName> 40083 <baseAddress>0xE000EF34</baseAddress> 40084 <addressBlock> 40085 <offset>0x0</offset> 40086 <size>0xD</size> 40087 <usage>registers</usage> 40088 </addressBlock> 40089 <interrupt><name>FPU</name><description>Floating point unit</description><value>81</value></interrupt> 40090 <registers> 40091 <register> 40092 <name>FPCCR</name> 40093 <displayName>FPCCR</displayName> 40094 <description>Floating-point context control 40095 register</description> 40096 <addressOffset>0x0</addressOffset> 40097 <size>0x20</size> 40098 <access>read-write</access> 40099 <resetValue>0x00000000</resetValue> 40100 <fields> 40101 <field> 40102 <name>LSPACT</name> 40103 <description>LSPACT</description> 40104 <bitOffset>0</bitOffset> 40105 <bitWidth>1</bitWidth> 40106 </field> 40107 <field> 40108 <name>USER</name> 40109 <description>USER</description> 40110 <bitOffset>1</bitOffset> 40111 <bitWidth>1</bitWidth> 40112 </field> 40113 <field> 40114 <name>THREAD</name> 40115 <description>THREAD</description> 40116 <bitOffset>3</bitOffset> 40117 <bitWidth>1</bitWidth> 40118 </field> 40119 <field> 40120 <name>HFRDY</name> 40121 <description>HFRDY</description> 40122 <bitOffset>4</bitOffset> 40123 <bitWidth>1</bitWidth> 40124 </field> 40125 <field> 40126 <name>MMRDY</name> 40127 <description>MMRDY</description> 40128 <bitOffset>5</bitOffset> 40129 <bitWidth>1</bitWidth> 40130 </field> 40131 <field> 40132 <name>BFRDY</name> 40133 <description>BFRDY</description> 40134 <bitOffset>6</bitOffset> 40135 <bitWidth>1</bitWidth> 40136 </field> 40137 <field> 40138 <name>MONRDY</name> 40139 <description>MONRDY</description> 40140 <bitOffset>8</bitOffset> 40141 <bitWidth>1</bitWidth> 40142 </field> 40143 <field> 40144 <name>LSPEN</name> 40145 <description>LSPEN</description> 40146 <bitOffset>30</bitOffset> 40147 <bitWidth>1</bitWidth> 40148 </field> 40149 <field> 40150 <name>ASPEN</name> 40151 <description>ASPEN</description> 40152 <bitOffset>31</bitOffset> 40153 <bitWidth>1</bitWidth> 40154 </field> 40155 </fields> 40156 </register> 40157 <register> 40158 <name>FPCAR</name> 40159 <displayName>FPCAR</displayName> 40160 <description>Floating-point context address 40161 register</description> 40162 <addressOffset>0x4</addressOffset> 40163 <size>0x20</size> 40164 <access>read-write</access> 40165 <resetValue>0x00000000</resetValue> 40166 <fields> 40167 <field> 40168 <name>ADDRESS</name> 40169 <description>Location of unpopulated 40170 floating-point</description> 40171 <bitOffset>3</bitOffset> 40172 <bitWidth>29</bitWidth> 40173 </field> 40174 </fields> 40175 </register> 40176 <register> 40177 <name>FPSCR</name> 40178 <displayName>FPSCR</displayName> 40179 <description>Floating-point status control 40180 register</description> 40181 <addressOffset>0x8</addressOffset> 40182 <size>0x20</size> 40183 <access>read-write</access> 40184 <resetValue>0x00000000</resetValue> 40185 <fields> 40186 <field> 40187 <name>IOC</name> 40188 <description>Invalid operation cumulative exception 40189 bit</description> 40190 <bitOffset>0</bitOffset> 40191 <bitWidth>1</bitWidth> 40192 </field> 40193 <field> 40194 <name>DZC</name> 40195 <description>Division by zero cumulative exception 40196 bit.</description> 40197 <bitOffset>1</bitOffset> 40198 <bitWidth>1</bitWidth> 40199 </field> 40200 <field> 40201 <name>OFC</name> 40202 <description>Overflow cumulative exception 40203 bit</description> 40204 <bitOffset>2</bitOffset> 40205 <bitWidth>1</bitWidth> 40206 </field> 40207 <field> 40208 <name>UFC</name> 40209 <description>Underflow cumulative exception 40210 bit</description> 40211 <bitOffset>3</bitOffset> 40212 <bitWidth>1</bitWidth> 40213 </field> 40214 <field> 40215 <name>IXC</name> 40216 <description>Inexact cumulative exception 40217 bit</description> 40218 <bitOffset>4</bitOffset> 40219 <bitWidth>1</bitWidth> 40220 </field> 40221 <field> 40222 <name>IDC</name> 40223 <description>Input denormal cumulative exception 40224 bit.</description> 40225 <bitOffset>7</bitOffset> 40226 <bitWidth>1</bitWidth> 40227 </field> 40228 <field> 40229 <name>RMode</name> 40230 <description>Rounding Mode control 40231 field</description> 40232 <bitOffset>22</bitOffset> 40233 <bitWidth>2</bitWidth> 40234 </field> 40235 <field> 40236 <name>FZ</name> 40237 <description>Flush-to-zero mode control 40238 bit:</description> 40239 <bitOffset>24</bitOffset> 40240 <bitWidth>1</bitWidth> 40241 </field> 40242 <field> 40243 <name>DN</name> 40244 <description>Default NaN mode control 40245 bit</description> 40246 <bitOffset>25</bitOffset> 40247 <bitWidth>1</bitWidth> 40248 </field> 40249 <field> 40250 <name>AHP</name> 40251 <description>Alternative half-precision control 40252 bit</description> 40253 <bitOffset>26</bitOffset> 40254 <bitWidth>1</bitWidth> 40255 </field> 40256 <field> 40257 <name>V</name> 40258 <description>Overflow condition code 40259 flag</description> 40260 <bitOffset>28</bitOffset> 40261 <bitWidth>1</bitWidth> 40262 </field> 40263 <field> 40264 <name>C</name> 40265 <description>Carry condition code flag</description> 40266 <bitOffset>29</bitOffset> 40267 <bitWidth>1</bitWidth> 40268 </field> 40269 <field> 40270 <name>Z</name> 40271 <description>Zero condition code flag</description> 40272 <bitOffset>30</bitOffset> 40273 <bitWidth>1</bitWidth> 40274 </field> 40275 <field> 40276 <name>N</name> 40277 <description>Negative condition code 40278 flag</description> 40279 <bitOffset>31</bitOffset> 40280 <bitWidth>1</bitWidth> 40281 </field> 40282 </fields> 40283 </register> 40284 </registers> 40285 </peripheral> 40286 <peripheral> 40287 <name>MPU</name> 40288 <description>Memory protection unit</description> 40289 <groupName>MPU</groupName> 40290 <baseAddress>0xE000ED90</baseAddress> 40291 <addressBlock> 40292 <offset>0x0</offset> 40293 <size>0x15</size> 40294 <usage>registers</usage> 40295 </addressBlock> 40296 <registers> 40297 <register> 40298 <name>TYPER</name> 40299 <displayName>TYPER</displayName> 40300 <description>MPU type register</description> 40301 <addressOffset>0x0</addressOffset> 40302 <size>0x20</size> 40303 <access>read-only</access> 40304 <resetValue>0X00000800</resetValue> 40305 <fields> 40306 <field> 40307 <name>SEPARATE</name> 40308 <description>Separate flag</description> 40309 <bitOffset>0</bitOffset> 40310 <bitWidth>1</bitWidth> 40311 </field> 40312 <field> 40313 <name>DREGION</name> 40314 <description>Number of MPU data regions</description> 40315 <bitOffset>8</bitOffset> 40316 <bitWidth>8</bitWidth> 40317 </field> 40318 <field> 40319 <name>IREGION</name> 40320 <description>Number of MPU instruction 40321 regions</description> 40322 <bitOffset>16</bitOffset> 40323 <bitWidth>8</bitWidth> 40324 </field> 40325 </fields> 40326 </register> 40327 <register> 40328 <name>CTRL</name> 40329 <displayName>CTRL</displayName> 40330 <description>MPU control register</description> 40331 <addressOffset>0x4</addressOffset> 40332 <size>0x20</size> 40333 <access>read-only</access> 40334 <resetValue>0X00000000</resetValue> 40335 <fields> 40336 <field> 40337 <name>ENABLE</name> 40338 <description>Enables the MPU</description> 40339 <bitOffset>0</bitOffset> 40340 <bitWidth>1</bitWidth> 40341 </field> 40342 <field> 40343 <name>HFNMIENA</name> 40344 <description>Enables the operation of MPU during hard 40345 fault</description> 40346 <bitOffset>1</bitOffset> 40347 <bitWidth>1</bitWidth> 40348 </field> 40349 <field> 40350 <name>PRIVDEFENA</name> 40351 <description>Enable priviliged software access to 40352 default memory map</description> 40353 <bitOffset>2</bitOffset> 40354 <bitWidth>1</bitWidth> 40355 </field> 40356 </fields> 40357 </register> 40358 <register> 40359 <name>RNR</name> 40360 <displayName>RNR</displayName> 40361 <description>MPU region number register</description> 40362 <addressOffset>0x8</addressOffset> 40363 <size>0x20</size> 40364 <access>read-write</access> 40365 <resetValue>0X00000000</resetValue> 40366 <fields> 40367 <field> 40368 <name>REGION</name> 40369 <description>MPU region</description> 40370 <bitOffset>0</bitOffset> 40371 <bitWidth>8</bitWidth> 40372 </field> 40373 </fields> 40374 </register> 40375 <register> 40376 <name>RBAR</name> 40377 <displayName>RBAR</displayName> 40378 <description>MPU region base address 40379 register</description> 40380 <addressOffset>0xC</addressOffset> 40381 <size>0x20</size> 40382 <access>read-write</access> 40383 <resetValue>0X00000000</resetValue> 40384 <fields> 40385 <field> 40386 <name>REGION</name> 40387 <description>MPU region field</description> 40388 <bitOffset>0</bitOffset> 40389 <bitWidth>4</bitWidth> 40390 </field> 40391 <field> 40392 <name>VALID</name> 40393 <description>MPU region number valid</description> 40394 <bitOffset>4</bitOffset> 40395 <bitWidth>1</bitWidth> 40396 </field> 40397 <field> 40398 <name>ADDR</name> 40399 <description>Region base address field</description> 40400 <bitOffset>5</bitOffset> 40401 <bitWidth>27</bitWidth> 40402 </field> 40403 </fields> 40404 </register> 40405 <register> 40406 <name>RASR</name> 40407 <displayName>RASR</displayName> 40408 <description>MPU region attribute and size 40409 register</description> 40410 <addressOffset>0x10</addressOffset> 40411 <size>0x20</size> 40412 <access>read-write</access> 40413 <resetValue>0X00000000</resetValue> 40414 <fields> 40415 <field> 40416 <name>ENABLE</name> 40417 <description>Region enable bit.</description> 40418 <bitOffset>0</bitOffset> 40419 <bitWidth>1</bitWidth> 40420 </field> 40421 <field> 40422 <name>SIZE</name> 40423 <description>Size of the MPU protection 40424 region</description> 40425 <bitOffset>1</bitOffset> 40426 <bitWidth>5</bitWidth> 40427 </field> 40428 <field> 40429 <name>SRD</name> 40430 <description>Subregion disable bits</description> 40431 <bitOffset>8</bitOffset> 40432 <bitWidth>8</bitWidth> 40433 </field> 40434 <field> 40435 <name>B</name> 40436 <description>memory attribute</description> 40437 <bitOffset>16</bitOffset> 40438 <bitWidth>1</bitWidth> 40439 </field> 40440 <field> 40441 <name>C</name> 40442 <description>memory attribute</description> 40443 <bitOffset>17</bitOffset> 40444 <bitWidth>1</bitWidth> 40445 </field> 40446 <field> 40447 <name>S</name> 40448 <description>Shareable memory attribute</description> 40449 <bitOffset>18</bitOffset> 40450 <bitWidth>1</bitWidth> 40451 </field> 40452 <field> 40453 <name>TEX</name> 40454 <description>memory attribute</description> 40455 <bitOffset>19</bitOffset> 40456 <bitWidth>3</bitWidth> 40457 </field> 40458 <field> 40459 <name>AP</name> 40460 <description>Access permission</description> 40461 <bitOffset>24</bitOffset> 40462 <bitWidth>3</bitWidth> 40463 </field> 40464 <field> 40465 <name>XN</name> 40466 <description>Instruction access disable 40467 bit</description> 40468 <bitOffset>28</bitOffset> 40469 <bitWidth>1</bitWidth> 40470 </field> 40471 </fields> 40472 </register> 40473 </registers> 40474 </peripheral> 40475 <peripheral> 40476 <name>STK</name> 40477 <description>SysTick timer</description> 40478 <groupName>STK</groupName> 40479 <baseAddress>0xE000E010</baseAddress> 40480 <addressBlock> 40481 <offset>0x0</offset> 40482 <size>0x11</size> 40483 <usage>registers</usage> 40484 </addressBlock> 40485 <registers> 40486 <register> 40487 <name>CTRL</name> 40488 <displayName>CTRL</displayName> 40489 <description>SysTick control and status 40490 register</description> 40491 <addressOffset>0x0</addressOffset> 40492 <size>0x20</size> 40493 <access>read-write</access> 40494 <resetValue>0X00000000</resetValue> 40495 <fields> 40496 <field> 40497 <name>ENABLE</name> 40498 <description>Counter enable</description> 40499 <bitOffset>0</bitOffset> 40500 <bitWidth>1</bitWidth> 40501 </field> 40502 <field> 40503 <name>TICKINT</name> 40504 <description>SysTick exception request 40505 enable</description> 40506 <bitOffset>1</bitOffset> 40507 <bitWidth>1</bitWidth> 40508 </field> 40509 <field> 40510 <name>CLKSOURCE</name> 40511 <description>Clock source selection</description> 40512 <bitOffset>2</bitOffset> 40513 <bitWidth>1</bitWidth> 40514 </field> 40515 <field> 40516 <name>COUNTFLAG</name> 40517 <description>COUNTFLAG</description> 40518 <bitOffset>16</bitOffset> 40519 <bitWidth>1</bitWidth> 40520 </field> 40521 </fields> 40522 </register> 40523 <register> 40524 <name>LOAD</name> 40525 <displayName>LOAD</displayName> 40526 <description>SysTick reload value register</description> 40527 <addressOffset>0x4</addressOffset> 40528 <size>0x20</size> 40529 <access>read-write</access> 40530 <resetValue>0X00000000</resetValue> 40531 <fields> 40532 <field> 40533 <name>RELOAD</name> 40534 <description>RELOAD value</description> 40535 <bitOffset>0</bitOffset> 40536 <bitWidth>24</bitWidth> 40537 </field> 40538 </fields> 40539 </register> 40540 <register> 40541 <name>VAL</name> 40542 <displayName>VAL</displayName> 40543 <description>SysTick current value register</description> 40544 <addressOffset>0x8</addressOffset> 40545 <size>0x20</size> 40546 <access>read-write</access> 40547 <resetValue>0X00000000</resetValue> 40548 <fields> 40549 <field> 40550 <name>CURRENT</name> 40551 <description>Current counter value</description> 40552 <bitOffset>0</bitOffset> 40553 <bitWidth>24</bitWidth> 40554 </field> 40555 </fields> 40556 </register> 40557 <register> 40558 <name>CALIB</name> 40559 <displayName>CALIB</displayName> 40560 <description>SysTick calibration value 40561 register</description> 40562 <addressOffset>0xC</addressOffset> 40563 <size>0x20</size> 40564 <access>read-write</access> 40565 <resetValue>0X00000000</resetValue> 40566 <fields> 40567 <field> 40568 <name>TENMS</name> 40569 <description>Calibration value</description> 40570 <bitOffset>0</bitOffset> 40571 <bitWidth>24</bitWidth> 40572 </field> 40573 <field> 40574 <name>SKEW</name> 40575 <description>SKEW flag: Indicates whether the TENMS 40576 value is exact</description> 40577 <bitOffset>30</bitOffset> 40578 <bitWidth>1</bitWidth> 40579 </field> 40580 <field> 40581 <name>NOREF</name> 40582 <description>NOREF flag. Reads as zero</description> 40583 <bitOffset>31</bitOffset> 40584 <bitWidth>1</bitWidth> 40585 </field> 40586 </fields> 40587 </register> 40588 </registers> 40589 </peripheral> 40590 <peripheral> 40591 <name>SCB</name> 40592 <description>System control block</description> 40593 <groupName>SCB</groupName> 40594 <baseAddress>0xE000ED00</baseAddress> 40595 <addressBlock> 40596 <offset>0x0</offset> 40597 <size>0x41</size> 40598 <usage>registers</usage> 40599 </addressBlock> 40600 <registers> 40601 <register> 40602 <name>CPUID</name> 40603 <displayName>CPUID</displayName> 40604 <description>CPUID base register</description> 40605 <addressOffset>0x0</addressOffset> 40606 <size>0x20</size> 40607 <access>read-only</access> 40608 <resetValue>0x410FC241</resetValue> 40609 <fields> 40610 <field> 40611 <name>Revision</name> 40612 <description>Revision number</description> 40613 <bitOffset>0</bitOffset> 40614 <bitWidth>4</bitWidth> 40615 </field> 40616 <field> 40617 <name>PartNo</name> 40618 <description>Part number of the 40619 processor</description> 40620 <bitOffset>4</bitOffset> 40621 <bitWidth>12</bitWidth> 40622 </field> 40623 <field> 40624 <name>Constant</name> 40625 <description>Reads as 0xF</description> 40626 <bitOffset>16</bitOffset> 40627 <bitWidth>4</bitWidth> 40628 </field> 40629 <field> 40630 <name>Variant</name> 40631 <description>Variant number</description> 40632 <bitOffset>20</bitOffset> 40633 <bitWidth>4</bitWidth> 40634 </field> 40635 <field> 40636 <name>Implementer</name> 40637 <description>Implementer code</description> 40638 <bitOffset>24</bitOffset> 40639 <bitWidth>8</bitWidth> 40640 </field> 40641 </fields> 40642 </register> 40643 <register> 40644 <name>ICSR</name> 40645 <displayName>ICSR</displayName> 40646 <description>Interrupt control and state 40647 register</description> 40648 <addressOffset>0x4</addressOffset> 40649 <size>0x20</size> 40650 <access>read-write</access> 40651 <resetValue>0x00000000</resetValue> 40652 <fields> 40653 <field> 40654 <name>VECTACTIVE</name> 40655 <description>Active vector</description> 40656 <bitOffset>0</bitOffset> 40657 <bitWidth>9</bitWidth> 40658 </field> 40659 <field> 40660 <name>RETTOBASE</name> 40661 <description>Return to base level</description> 40662 <bitOffset>11</bitOffset> 40663 <bitWidth>1</bitWidth> 40664 </field> 40665 <field> 40666 <name>VECTPENDING</name> 40667 <description>Pending vector</description> 40668 <bitOffset>12</bitOffset> 40669 <bitWidth>7</bitWidth> 40670 </field> 40671 <field> 40672 <name>ISRPENDING</name> 40673 <description>Interrupt pending flag</description> 40674 <bitOffset>22</bitOffset> 40675 <bitWidth>1</bitWidth> 40676 </field> 40677 <field> 40678 <name>PENDSTCLR</name> 40679 <description>SysTick exception clear-pending 40680 bit</description> 40681 <bitOffset>25</bitOffset> 40682 <bitWidth>1</bitWidth> 40683 </field> 40684 <field> 40685 <name>PENDSTSET</name> 40686 <description>SysTick exception set-pending 40687 bit</description> 40688 <bitOffset>26</bitOffset> 40689 <bitWidth>1</bitWidth> 40690 </field> 40691 <field> 40692 <name>PENDSVCLR</name> 40693 <description>PendSV clear-pending bit</description> 40694 <bitOffset>27</bitOffset> 40695 <bitWidth>1</bitWidth> 40696 </field> 40697 <field> 40698 <name>PENDSVSET</name> 40699 <description>PendSV set-pending bit</description> 40700 <bitOffset>28</bitOffset> 40701 <bitWidth>1</bitWidth> 40702 </field> 40703 <field> 40704 <name>NMIPENDSET</name> 40705 <description>NMI set-pending bit.</description> 40706 <bitOffset>31</bitOffset> 40707 <bitWidth>1</bitWidth> 40708 </field> 40709 </fields> 40710 </register> 40711 <register> 40712 <name>VTOR</name> 40713 <displayName>VTOR</displayName> 40714 <description>Vector table offset register</description> 40715 <addressOffset>0x8</addressOffset> 40716 <size>0x20</size> 40717 <access>read-write</access> 40718 <resetValue>0x00000000</resetValue> 40719 <fields> 40720 <field> 40721 <name>TBLOFF</name> 40722 <description>Vector table base offset 40723 field</description> 40724 <bitOffset>9</bitOffset> 40725 <bitWidth>21</bitWidth> 40726 </field> 40727 </fields> 40728 </register> 40729 <register> 40730 <name>AIRCR</name> 40731 <displayName>AIRCR</displayName> 40732 <description>Application interrupt and reset control 40733 register</description> 40734 <addressOffset>0xC</addressOffset> 40735 <size>0x20</size> 40736 <access>read-write</access> 40737 <resetValue>0x00000000</resetValue> 40738 <fields> 40739 <field> 40740 <name>VECTRESET</name> 40741 <description>VECTRESET</description> 40742 <bitOffset>0</bitOffset> 40743 <bitWidth>1</bitWidth> 40744 </field> 40745 <field> 40746 <name>VECTCLRACTIVE</name> 40747 <description>VECTCLRACTIVE</description> 40748 <bitOffset>1</bitOffset> 40749 <bitWidth>1</bitWidth> 40750 </field> 40751 <field> 40752 <name>SYSRESETREQ</name> 40753 <description>SYSRESETREQ</description> 40754 <bitOffset>2</bitOffset> 40755 <bitWidth>1</bitWidth> 40756 </field> 40757 <field> 40758 <name>PRIGROUP</name> 40759 <description>PRIGROUP</description> 40760 <bitOffset>8</bitOffset> 40761 <bitWidth>3</bitWidth> 40762 </field> 40763 <field> 40764 <name>ENDIANESS</name> 40765 <description>ENDIANESS</description> 40766 <bitOffset>15</bitOffset> 40767 <bitWidth>1</bitWidth> 40768 </field> 40769 <field> 40770 <name>VECTKEYSTAT</name> 40771 <description>Register key</description> 40772 <bitOffset>16</bitOffset> 40773 <bitWidth>16</bitWidth> 40774 </field> 40775 </fields> 40776 </register> 40777 <register> 40778 <name>SCR</name> 40779 <displayName>SCR</displayName> 40780 <description>System control register</description> 40781 <addressOffset>0x10</addressOffset> 40782 <size>0x20</size> 40783 <access>read-write</access> 40784 <resetValue>0x00000000</resetValue> 40785 <fields> 40786 <field> 40787 <name>SLEEPONEXIT</name> 40788 <description>SLEEPONEXIT</description> 40789 <bitOffset>1</bitOffset> 40790 <bitWidth>1</bitWidth> 40791 </field> 40792 <field> 40793 <name>SLEEPDEEP</name> 40794 <description>SLEEPDEEP</description> 40795 <bitOffset>2</bitOffset> 40796 <bitWidth>1</bitWidth> 40797 </field> 40798 <field> 40799 <name>SEVEONPEND</name> 40800 <description>Send Event on Pending bit</description> 40801 <bitOffset>4</bitOffset> 40802 <bitWidth>1</bitWidth> 40803 </field> 40804 </fields> 40805 </register> 40806 <register> 40807 <name>CCR</name> 40808 <displayName>CCR</displayName> 40809 <description>Configuration and control 40810 register</description> 40811 <addressOffset>0x14</addressOffset> 40812 <size>0x20</size> 40813 <access>read-write</access> 40814 <resetValue>0x00000000</resetValue> 40815 <fields> 40816 <field> 40817 <name>NONBASETHRDENA</name> 40818 <description>Configures how the processor enters 40819 Thread mode</description> 40820 <bitOffset>0</bitOffset> 40821 <bitWidth>1</bitWidth> 40822 </field> 40823 <field> 40824 <name>USERSETMPEND</name> 40825 <description>USERSETMPEND</description> 40826 <bitOffset>1</bitOffset> 40827 <bitWidth>1</bitWidth> 40828 </field> 40829 <field> 40830 <name>UNALIGN__TRP</name> 40831 <description>UNALIGN_ TRP</description> 40832 <bitOffset>3</bitOffset> 40833 <bitWidth>1</bitWidth> 40834 </field> 40835 <field> 40836 <name>DIV_0_TRP</name> 40837 <description>DIV_0_TRP</description> 40838 <bitOffset>4</bitOffset> 40839 <bitWidth>1</bitWidth> 40840 </field> 40841 <field> 40842 <name>BFHFNMIGN</name> 40843 <description>BFHFNMIGN</description> 40844 <bitOffset>8</bitOffset> 40845 <bitWidth>1</bitWidth> 40846 </field> 40847 <field> 40848 <name>STKALIGN</name> 40849 <description>STKALIGN</description> 40850 <bitOffset>9</bitOffset> 40851 <bitWidth>1</bitWidth> 40852 </field> 40853 </fields> 40854 </register> 40855 <register> 40856 <name>SHPR1</name> 40857 <displayName>SHPR1</displayName> 40858 <description>System handler priority 40859 registers</description> 40860 <addressOffset>0x18</addressOffset> 40861 <size>0x20</size> 40862 <access>read-write</access> 40863 <resetValue>0x00000000</resetValue> 40864 <fields> 40865 <field> 40866 <name>PRI_4</name> 40867 <description>Priority of system handler 40868 4</description> 40869 <bitOffset>0</bitOffset> 40870 <bitWidth>8</bitWidth> 40871 </field> 40872 <field> 40873 <name>PRI_5</name> 40874 <description>Priority of system handler 40875 5</description> 40876 <bitOffset>8</bitOffset> 40877 <bitWidth>8</bitWidth> 40878 </field> 40879 <field> 40880 <name>PRI_6</name> 40881 <description>Priority of system handler 40882 6</description> 40883 <bitOffset>16</bitOffset> 40884 <bitWidth>8</bitWidth> 40885 </field> 40886 </fields> 40887 </register> 40888 <register> 40889 <name>SHPR2</name> 40890 <displayName>SHPR2</displayName> 40891 <description>System handler priority 40892 registers</description> 40893 <addressOffset>0x1C</addressOffset> 40894 <size>0x20</size> 40895 <access>read-write</access> 40896 <resetValue>0x00000000</resetValue> 40897 <fields> 40898 <field> 40899 <name>PRI_11</name> 40900 <description>Priority of system handler 40901 11</description> 40902 <bitOffset>24</bitOffset> 40903 <bitWidth>8</bitWidth> 40904 </field> 40905 </fields> 40906 </register> 40907 <register> 40908 <name>SHPR3</name> 40909 <displayName>SHPR3</displayName> 40910 <description>System handler priority 40911 registers</description> 40912 <addressOffset>0x20</addressOffset> 40913 <size>0x20</size> 40914 <access>read-write</access> 40915 <resetValue>0x00000000</resetValue> 40916 <fields> 40917 <field> 40918 <name>PRI_14</name> 40919 <description>Priority of system handler 40920 14</description> 40921 <bitOffset>16</bitOffset> 40922 <bitWidth>8</bitWidth> 40923 </field> 40924 <field> 40925 <name>PRI_15</name> 40926 <description>Priority of system handler 40927 15</description> 40928 <bitOffset>24</bitOffset> 40929 <bitWidth>8</bitWidth> 40930 </field> 40931 </fields> 40932 </register> 40933 <register> 40934 <name>SHCRS</name> 40935 <displayName>SHCRS</displayName> 40936 <description>System handler control and state 40937 register</description> 40938 <addressOffset>0x24</addressOffset> 40939 <size>0x20</size> 40940 <access>read-write</access> 40941 <resetValue>0x00000000</resetValue> 40942 <fields> 40943 <field> 40944 <name>MEMFAULTACT</name> 40945 <description>Memory management fault exception active 40946 bit</description> 40947 <bitOffset>0</bitOffset> 40948 <bitWidth>1</bitWidth> 40949 </field> 40950 <field> 40951 <name>BUSFAULTACT</name> 40952 <description>Bus fault exception active 40953 bit</description> 40954 <bitOffset>1</bitOffset> 40955 <bitWidth>1</bitWidth> 40956 </field> 40957 <field> 40958 <name>USGFAULTACT</name> 40959 <description>Usage fault exception active 40960 bit</description> 40961 <bitOffset>3</bitOffset> 40962 <bitWidth>1</bitWidth> 40963 </field> 40964 <field> 40965 <name>SVCALLACT</name> 40966 <description>SVC call active bit</description> 40967 <bitOffset>7</bitOffset> 40968 <bitWidth>1</bitWidth> 40969 </field> 40970 <field> 40971 <name>MONITORACT</name> 40972 <description>Debug monitor active bit</description> 40973 <bitOffset>8</bitOffset> 40974 <bitWidth>1</bitWidth> 40975 </field> 40976 <field> 40977 <name>PENDSVACT</name> 40978 <description>PendSV exception active 40979 bit</description> 40980 <bitOffset>10</bitOffset> 40981 <bitWidth>1</bitWidth> 40982 </field> 40983 <field> 40984 <name>SYSTICKACT</name> 40985 <description>SysTick exception active 40986 bit</description> 40987 <bitOffset>11</bitOffset> 40988 <bitWidth>1</bitWidth> 40989 </field> 40990 <field> 40991 <name>USGFAULTPENDED</name> 40992 <description>Usage fault exception pending 40993 bit</description> 40994 <bitOffset>12</bitOffset> 40995 <bitWidth>1</bitWidth> 40996 </field> 40997 <field> 40998 <name>MEMFAULTPENDED</name> 40999 <description>Memory management fault exception 41000 pending bit</description> 41001 <bitOffset>13</bitOffset> 41002 <bitWidth>1</bitWidth> 41003 </field> 41004 <field> 41005 <name>BUSFAULTPENDED</name> 41006 <description>Bus fault exception pending 41007 bit</description> 41008 <bitOffset>14</bitOffset> 41009 <bitWidth>1</bitWidth> 41010 </field> 41011 <field> 41012 <name>SVCALLPENDED</name> 41013 <description>SVC call pending bit</description> 41014 <bitOffset>15</bitOffset> 41015 <bitWidth>1</bitWidth> 41016 </field> 41017 <field> 41018 <name>MEMFAULTENA</name> 41019 <description>Memory management fault enable 41020 bit</description> 41021 <bitOffset>16</bitOffset> 41022 <bitWidth>1</bitWidth> 41023 </field> 41024 <field> 41025 <name>BUSFAULTENA</name> 41026 <description>Bus fault enable bit</description> 41027 <bitOffset>17</bitOffset> 41028 <bitWidth>1</bitWidth> 41029 </field> 41030 <field> 41031 <name>USGFAULTENA</name> 41032 <description>Usage fault enable bit</description> 41033 <bitOffset>18</bitOffset> 41034 <bitWidth>1</bitWidth> 41035 </field> 41036 </fields> 41037 </register> 41038 <register> 41039 <name>CFSR_UFSR_BFSR_MMFSR</name> 41040 <displayName>CFSR_UFSR_BFSR_MMFSR</displayName> 41041 <description>Configurable fault status 41042 register</description> 41043 <addressOffset>0x28</addressOffset> 41044 <size>0x20</size> 41045 <access>read-write</access> 41046 <resetValue>0x00000000</resetValue> 41047 <fields> 41048 <field> 41049 <name>IACCVIOL</name> 41050 <description>Instruction access violation 41051 flag</description> 41052 <bitOffset>1</bitOffset> 41053 <bitWidth>1</bitWidth> 41054 </field> 41055 <field> 41056 <name>MUNSTKERR</name> 41057 <description>Memory manager fault on unstacking for a 41058 return from exception</description> 41059 <bitOffset>3</bitOffset> 41060 <bitWidth>1</bitWidth> 41061 </field> 41062 <field> 41063 <name>MSTKERR</name> 41064 <description>Memory manager fault on stacking for 41065 exception entry.</description> 41066 <bitOffset>4</bitOffset> 41067 <bitWidth>1</bitWidth> 41068 </field> 41069 <field> 41070 <name>MLSPERR</name> 41071 <description>MLSPERR</description> 41072 <bitOffset>5</bitOffset> 41073 <bitWidth>1</bitWidth> 41074 </field> 41075 <field> 41076 <name>MMARVALID</name> 41077 <description>Memory Management Fault Address Register 41078 (MMAR) valid flag</description> 41079 <bitOffset>7</bitOffset> 41080 <bitWidth>1</bitWidth> 41081 </field> 41082 <field> 41083 <name>IBUSERR</name> 41084 <description>Instruction bus error</description> 41085 <bitOffset>8</bitOffset> 41086 <bitWidth>1</bitWidth> 41087 </field> 41088 <field> 41089 <name>PRECISERR</name> 41090 <description>Precise data bus error</description> 41091 <bitOffset>9</bitOffset> 41092 <bitWidth>1</bitWidth> 41093 </field> 41094 <field> 41095 <name>IMPRECISERR</name> 41096 <description>Imprecise data bus error</description> 41097 <bitOffset>10</bitOffset> 41098 <bitWidth>1</bitWidth> 41099 </field> 41100 <field> 41101 <name>UNSTKERR</name> 41102 <description>Bus fault on unstacking for a return 41103 from exception</description> 41104 <bitOffset>11</bitOffset> 41105 <bitWidth>1</bitWidth> 41106 </field> 41107 <field> 41108 <name>STKERR</name> 41109 <description>Bus fault on stacking for exception 41110 entry</description> 41111 <bitOffset>12</bitOffset> 41112 <bitWidth>1</bitWidth> 41113 </field> 41114 <field> 41115 <name>LSPERR</name> 41116 <description>Bus fault on floating-point lazy state 41117 preservation</description> 41118 <bitOffset>13</bitOffset> 41119 <bitWidth>1</bitWidth> 41120 </field> 41121 <field> 41122 <name>BFARVALID</name> 41123 <description>Bus Fault Address Register (BFAR) valid 41124 flag</description> 41125 <bitOffset>15</bitOffset> 41126 <bitWidth>1</bitWidth> 41127 </field> 41128 <field> 41129 <name>UNDEFINSTR</name> 41130 <description>Undefined instruction usage 41131 fault</description> 41132 <bitOffset>16</bitOffset> 41133 <bitWidth>1</bitWidth> 41134 </field> 41135 <field> 41136 <name>INVSTATE</name> 41137 <description>Invalid state usage fault</description> 41138 <bitOffset>17</bitOffset> 41139 <bitWidth>1</bitWidth> 41140 </field> 41141 <field> 41142 <name>INVPC</name> 41143 <description>Invalid PC load usage 41144 fault</description> 41145 <bitOffset>18</bitOffset> 41146 <bitWidth>1</bitWidth> 41147 </field> 41148 <field> 41149 <name>NOCP</name> 41150 <description>No coprocessor usage 41151 fault.</description> 41152 <bitOffset>19</bitOffset> 41153 <bitWidth>1</bitWidth> 41154 </field> 41155 <field> 41156 <name>UNALIGNED</name> 41157 <description>Unaligned access usage 41158 fault</description> 41159 <bitOffset>24</bitOffset> 41160 <bitWidth>1</bitWidth> 41161 </field> 41162 <field> 41163 <name>DIVBYZERO</name> 41164 <description>Divide by zero usage fault</description> 41165 <bitOffset>25</bitOffset> 41166 <bitWidth>1</bitWidth> 41167 </field> 41168 </fields> 41169 </register> 41170 <register> 41171 <name>HFSR</name> 41172 <displayName>HFSR</displayName> 41173 <description>Hard fault status register</description> 41174 <addressOffset>0x2C</addressOffset> 41175 <size>0x20</size> 41176 <access>read-write</access> 41177 <resetValue>0x00000000</resetValue> 41178 <fields> 41179 <field> 41180 <name>VECTTBL</name> 41181 <description>Vector table hard fault</description> 41182 <bitOffset>1</bitOffset> 41183 <bitWidth>1</bitWidth> 41184 </field> 41185 <field> 41186 <name>FORCED</name> 41187 <description>Forced hard fault</description> 41188 <bitOffset>30</bitOffset> 41189 <bitWidth>1</bitWidth> 41190 </field> 41191 <field> 41192 <name>DEBUG_VT</name> 41193 <description>Reserved for Debug use</description> 41194 <bitOffset>31</bitOffset> 41195 <bitWidth>1</bitWidth> 41196 </field> 41197 </fields> 41198 </register> 41199 <register> 41200 <name>MMFAR</name> 41201 <displayName>MMFAR</displayName> 41202 <description>Memory management fault address 41203 register</description> 41204 <addressOffset>0x34</addressOffset> 41205 <size>0x20</size> 41206 <access>read-write</access> 41207 <resetValue>0x00000000</resetValue> 41208 <fields> 41209 <field> 41210 <name>MMFAR</name> 41211 <description>Memory management fault 41212 address</description> 41213 <bitOffset>0</bitOffset> 41214 <bitWidth>32</bitWidth> 41215 </field> 41216 </fields> 41217 </register> 41218 <register> 41219 <name>BFAR</name> 41220 <displayName>BFAR</displayName> 41221 <description>Bus fault address register</description> 41222 <addressOffset>0x38</addressOffset> 41223 <size>0x20</size> 41224 <access>read-write</access> 41225 <resetValue>0x00000000</resetValue> 41226 <fields> 41227 <field> 41228 <name>BFAR</name> 41229 <description>Bus fault address</description> 41230 <bitOffset>0</bitOffset> 41231 <bitWidth>32</bitWidth> 41232 </field> 41233 </fields> 41234 </register> 41235 <register> 41236 <name>AFSR</name> 41237 <displayName>AFSR</displayName> 41238 <description>Auxiliary fault status 41239 register</description> 41240 <addressOffset>0x3C</addressOffset> 41241 <size>0x20</size> 41242 <access>read-write</access> 41243 <resetValue>0x00000000</resetValue> 41244 <fields> 41245 <field> 41246 <name>IMPDEF</name> 41247 <description>Implementation defined</description> 41248 <bitOffset>0</bitOffset> 41249 <bitWidth>32</bitWidth> 41250 </field> 41251 </fields> 41252 </register> 41253 </registers> 41254 </peripheral> 41255 <peripheral> 41256 <name>NVIC_STIR</name> 41257 <description>Nested vectored interrupt 41258 controller</description> 41259 <groupName>NVIC</groupName> 41260 <baseAddress>0xE000EF00</baseAddress> 41261 <addressBlock> 41262 <offset>0x0</offset> 41263 <size>0x5</size> 41264 <usage>registers</usage> 41265 </addressBlock> 41266 <registers> 41267 <register> 41268 <name>STIR</name> 41269 <displayName>STIR</displayName> 41270 <description>Software trigger interrupt 41271 register</description> 41272 <addressOffset>0x0</addressOffset> 41273 <size>0x20</size> 41274 <access>read-write</access> 41275 <resetValue>0x00000000</resetValue> 41276 <fields> 41277 <field> 41278 <name>INTID</name> 41279 <description>Software generated interrupt 41280 ID</description> 41281 <bitOffset>0</bitOffset> 41282 <bitWidth>9</bitWidth> 41283 </field> 41284 </fields> 41285 </register> 41286 </registers> 41287 </peripheral> 41288 <peripheral> 41289 <name>FPU_CPACR</name> 41290 <description>Floating point unit CPACR</description> 41291 <groupName>FPU</groupName> 41292 <baseAddress>0xE000ED88</baseAddress> 41293 <addressBlock> 41294 <offset>0x0</offset> 41295 <size>0x5</size> 41296 <usage>registers</usage> 41297 </addressBlock> 41298 <registers> 41299 <register> 41300 <name>CPACR</name> 41301 <displayName>CPACR</displayName> 41302 <description>Coprocessor access control 41303 register</description> 41304 <addressOffset>0x0</addressOffset> 41305 <size>0x20</size> 41306 <access>read-write</access> 41307 <resetValue>0x0000000</resetValue> 41308 <fields> 41309 <field> 41310 <name>CP</name> 41311 <description>CP</description> 41312 <bitOffset>20</bitOffset> 41313 <bitWidth>4</bitWidth> 41314 </field> 41315 </fields> 41316 </register> 41317 </registers> 41318 </peripheral> 41319 <peripheral> 41320 <name>SCB_ACTRL</name> 41321 <description>System control block ACTLR</description> 41322 <groupName>SCB</groupName> 41323 <baseAddress>0xE000E008</baseAddress> 41324 <addressBlock> 41325 <offset>0x0</offset> 41326 <size>0x5</size> 41327 <usage>registers</usage> 41328 </addressBlock> 41329 <registers> 41330 <register> 41331 <name>ACTRL</name> 41332 <displayName>ACTRL</displayName> 41333 <description>Auxiliary control register</description> 41334 <addressOffset>0x0</addressOffset> 41335 <size>0x20</size> 41336 <access>read-write</access> 41337 <resetValue>0x00000000</resetValue> 41338 <fields> 41339 <field> 41340 <name>DISMCYCINT</name> 41341 <description>DISMCYCINT</description> 41342 <bitOffset>0</bitOffset> 41343 <bitWidth>1</bitWidth> 41344 </field> 41345 <field> 41346 <name>DISDEFWBUF</name> 41347 <description>DISDEFWBUF</description> 41348 <bitOffset>1</bitOffset> 41349 <bitWidth>1</bitWidth> 41350 </field> 41351 <field> 41352 <name>DISFOLD</name> 41353 <description>DISFOLD</description> 41354 <bitOffset>2</bitOffset> 41355 <bitWidth>1</bitWidth> 41356 </field> 41357 <field> 41358 <name>DISFPCA</name> 41359 <description>DISFPCA</description> 41360 <bitOffset>8</bitOffset> 41361 <bitWidth>1</bitWidth> 41362 </field> 41363 <field> 41364 <name>DISOOFP</name> 41365 <description>DISOOFP</description> 41366 <bitOffset>9</bitOffset> 41367 <bitWidth>1</bitWidth> 41368 </field> 41369 </fields> 41370 </register> 41371 </registers> 41372 </peripheral> 41373 </peripherals> 41374 </device>