commit 11f0a1cfe3bfc4ffec5371f1515c614495e8ec5c
Author: mehdi-norouzi <mehdeenoroozi@gmail.com>
Date: Sat, 8 Feb 2025 11:30:51 +0330
initial commit
Diffstat:
77 files changed, 67173 insertions(+), 0 deletions(-)
diff --git a/.gdbinit b/.gdbinit
@@ -0,0 +1,7 @@
+target extended-remote localhost:3333
+source /home/mehdi/extra/gits/svd-tools/gdb-svd.py
+svd LPC176x5x.svd
+monitor reset halt
+monitor flash write_image erase build/fw.elf
+start
+lay src
diff --git a/.gitignore b/.gitignore
@@ -0,0 +1,12 @@
+bin/
+*.elf
+*.bin
+*.o
+*.d
+*.map
+generated.*.ld
+build/*
+.cache/*
+globals/version.c
+tags
+compile_commands.json
diff --git a/LICENSE b/LICENSE
@@ -0,0 +1,19 @@
+Copyright 2025 Mehdi Noroozi <mehdeenoroozi@gmail.com>
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
diff --git a/LPC176x5x.svd b/LPC176x5x.svd
@@ -0,0 +1,32121 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
+ <name>LPC176x5x</name>
+ <version>0.2</version>
+ <description>LPC176x/LPC175x M3</description>
+ <cpu>
+ <name>CM3</name>
+ <revision>r0p0</revision>
+ <endian>little</endian>
+ <mpuPresent>1</mpuPresent>
+ <fpuPresent>0</fpuPresent>
+ <nvicPrioBits>5</nvicPrioBits>
+ <vendorSystickConfig>0</vendorSystickConfig>
+ </cpu>
+
+ <headerDefinitionsPrefix>LPC_</headerDefinitionsPrefix>
+ <addressUnitBits>8</addressUnitBits>
+ <width>32</width>
+ <size>32</size>
+
+ <!--
+ Software that is described herein is for illustrative purposes only
+ which provides customers with programming information regarding the
+ products. This software is supplied "AS IS" without any warranties.
+ NXP Semiconductors assumes no responsibility or liability for the
+ use of the software, conveys no license or title under any patent,
+ copyright, or mask work right to the product. NXP Semiconductors
+ reserves the right to make changes in the software without
+ notification. NXP Semiconductors also make no representation or
+ warranty that such application will be suitable for the specified
+ use without further testing or modification.
+
+ -->
+
+
+
+
+
+
+
+ <peripherals>
+ <peripheral>
+ <name>WDT</name>
+ <description>Watchdog Timer (WDT) </description>
+ <groupName>WDT</groupName>
+ <baseAddress>0x40000000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0xFFF</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>WDT</name>
+ <value>0</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>MOD</name>
+ <description>Watchdog mode register. This register determines the basic mode and status of the Watchdog Timer.</description>
+ <addressOffset>0x000</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>WDEN</name>
+ <description>Watchdog enable bit. This bit is Set Only.</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>STOP</name>
+ <description>The watchdog timer is stopped.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RUN</name>
+ <description>The watchdog timer is running.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>WDRESET</name>
+ <description>Watchdog reset enable bit. This bit is Set Only. See Table 652.</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>NORESET</name>
+ <description>A watchdog timeout will not cause a chip reset.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESET</name>
+ <description>A watchdog timeout will cause a chip reset.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>WDTOF</name>
+ <description>Watchdog time-out flag. Set when the watchdog timer times out, cleared by software.</description>
+ <bitRange>[2:2]</bitRange>
+
+ </field>
+ <field>
+ <name>WDINT</name>
+ <description>Watchdog interrupt flag. Cleared by software.</description>
+ <bitRange>[3:3]</bitRange>
+
+ </field>
+
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:4]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TC</name>
+ <description>Watchdog timer constant register. The value in this register determines the time-out value.</description>
+ <addressOffset>0x004</addressOffset>
+ <access>read-write</access>
+ <resetValue>0xFF</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>Count</name>
+ <description>Watchdog time-out interval.</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+
+ </fields>
+ </register>
+ <register>
+ <name>FEED</name>
+ <description>Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC.</description>
+ <addressOffset>0x008</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>Feed</name>
+ <description>Feed value should be 0xAA followed by 0x55.</description>
+ <bitRange>[7:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TV</name>
+ <description>Watchdog timer value register. This register reads out the current value of the Watchdog timer.</description>
+ <addressOffset>0x00C</addressOffset>
+ <access>read-only</access>
+ <resetValue>0xFF</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>Count</name>
+ <description>Counter timer value.</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+
+ </fields>
+ </register>
+ <register>
+ <name>CLKSEL</name>
+ <description>Watchdog clock select register.</description>
+ <addressOffset>0x010</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>CLKSEL</name>
+ <description>Selects source of WDT clock</description>
+ <bitRange>[1:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>IRC</name>
+ <description>IRC</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PCLK</name>
+ <description>Peripheral clock</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RTCOSC</name>
+ <description>RTC oscillator</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <isDefault>true</isDefault>
+
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[30:1]</bitRange>
+
+ </field>
+ <field>
+ <name>LOCK</name>
+ <description>If this bit is set to one writing to this register does not affect bit 0. The clock source can only be changed by first clearing this bit, then writing the new value of bit 0.</description>
+ <bitRange>[31:31]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>UNLOCKED</name>
+ <description>This bit is set to 0 on any reset. It cannot be cleared by software.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>LOCKED</name>
+ <description>Software can set this bit to 1 at any time. Once WDLOCK is set, the bits of this register
+ cannot be modified.</description>
+ <value>1</value>
+ </enumeratedValue>
+
+ </enumeratedValues>
+
+ </field>
+ </fields>
+ </register>
+
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>TIMER0</name>
+ <description>Timer0/1/2/3 </description>
+ <groupName>TIMER0</groupName>
+ <baseAddress>0x40004000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0xFFF</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>TIMER0</name>
+ <value>1</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>IR</name>
+ <description>Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending.</description>
+ <addressOffset>0x000</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>MR0INT</name>
+ <description>Interrupt flag for match channel 0.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>MR1INT</name>
+ <description>Interrupt flag for match channel 1.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>MR2INT</name>
+ <description>Interrupt flag for match channel 2.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>MR3INT</name>
+ <description>Interrupt flag for match channel 3.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>CR0INT</name>
+ <description>Interrupt flag for capture channel 0 event.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>CR1INT</name>
+ <description>Interrupt flag for capture channel 1 event.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:6]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TCR</name>
+ <description>Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.</description>
+ <addressOffset>0x004</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>CEN</name>
+ <description>When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>CRST</name>
+ <description>When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:2]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TC</name>
+ <description>Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.</description>
+ <addressOffset>0x008</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>TC</name>
+ <description>Timer counter value.</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PR</name>
+ <description>Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC.</description>
+ <addressOffset>0x00C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>PM</name>
+ <description>Prescale counter maximum value.</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PC</name>
+ <description>Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.</description>
+ <addressOffset>0x010</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>PC</name>
+ <description>Prescale counter value.</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>MCR</name>
+ <description>Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.</description>
+ <addressOffset>0x014</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>MR0I</name>
+ <description>Interrupt on MR0</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>INTERRUPT_IS_GENERAT</name>
+ <description>Interrupt is generated when MR0 matches the value in the TC.</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>INTERRUPT_IS_DISABLE</name>
+ <description>Interrupt is disabled</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>MR0R</name>
+ <description>Reset on MR0</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>TC_WILL_BE_RESET_IF_</name>
+ <description>TC will be reset if MR0 matches it.</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>FEATURE_DISABLED_</name>
+ <description>Feature disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>MR0S</name>
+ <description>Stop on MR0</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>TC_AND_PC_WILL_BE_ST</name>
+ <description>TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>FEATURE_DISABLED_</name>
+ <description>Feature disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>MR1I</name>
+ <description>Interrupt on MR1</description>
+ <bitRange>[3:3]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>INTERRUPT_IS_GENERAT</name>
+ <description>Interrupt is generated when MR1 matches the value in the TC.</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>INTERRUPT_IS_DISABLE</name>
+ <description>Interrupt is disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>MR1R</name>
+ <description>Reset on MR1</description>
+ <bitRange>[4:4]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>TC_WILL_BE_RESET_IF_</name>
+ <description>TC will be reset if MR1 matches it.</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>FEATURE_DISABLED_</name>
+ <description>Feature disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>MR1S</name>
+ <description>Stop on MR1</description>
+ <bitRange>[5:5]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>TC_AND_PC_WILL_BE_ST</name>
+ <description>TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>FEATURE_DISABLED_</name>
+ <description>Feature disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>MR2I</name>
+ <description>Interrupt on MR2</description>
+ <bitRange>[6:6]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>INTERRUPT_IS_GENERAT</name>
+ <description>Interrupt is generated when MR2 matches the value in the TC.</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>INTERRUPT_IS_DISABLE</name>
+ <description>Interrupt is disabled</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>MR2R</name>
+ <description>Reset on MR2</description>
+ <bitRange>[7:7]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>TC_WILL_BE_RESET_IF_</name>
+ <description>TC will be reset if MR2 matches it.</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>FEATURE_DISABLED_</name>
+ <description>Feature disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>MR2S</name>
+ <description>Stop on MR2.</description>
+ <bitRange>[8:8]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>TC_AND_PC_WILL_BE_ST</name>
+ <description>TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>FEATURE_DISABLED_</name>
+ <description>Feature disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>MR3I</name>
+ <description>Interrupt on MR3</description>
+ <bitRange>[9:9]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>INTERRUPT_IS_GENERAT</name>
+ <description>Interrupt is generated when MR3 matches the value in the TC.</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>THIS_INTERRUPT_IS_DI</name>
+ <description>This interrupt is disabled</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>MR3R</name>
+ <description>Reset on MR3</description>
+ <bitRange>[10:10]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>TC_WILL_BE_RESET_IF_</name>
+ <description>TC will be reset if MR3 matches it.</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>FEATURE_DISABLED_</name>
+ <description>Feature disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>MR3S</name>
+ <description>Stop on MR3</description>
+ <bitRange>[11:11]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>TC_AND_PC_WILL_BE_ST</name>
+ <description>TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>FEATURE_DISABLED_</name>
+ <description>Feature disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:12]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <dim>4</dim>
+ <dimIncrement>0x4</dimIncrement>
+ <dimIndex>0-3</dimIndex>
+ <name>MR[%s]</name>
+ <displayName>MR[%s]</displayName>
+ <description>Match Register 0. MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC.</description>
+ <addressOffset>0x018</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>MATCH</name>
+ <description>Timer counter match value.</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCR</name>
+ <description>Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.</description>
+ <addressOffset>0x028</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>CAP0RE</name>
+ <description>Capture on CAPn.0 rising edge</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>ENABLE</name>
+ <description>A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC.</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLE</name>
+ <description>This feature is disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CAP0FE</name>
+ <description>Capture on CAPn.0 falling edge</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>ENABLE</name>
+ <description>A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC.</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLE</name>
+ <description>This feature is disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CAP0I</name>
+ <description>Interrupt on CAPn.0 event</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>ENABLE</name>
+ <description>A CR0 load due to a CAPn.0 event will generate an interrupt.</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLE</name>
+ <description>This feature is disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CAP1RE</name>
+ <description>Capture on CAPn.1 rising edge</description>
+ <bitRange>[3:3]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>ENABLE</name>
+ <description>A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC.</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLE</name>
+ <description>This feature is disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CAP1FE</name>
+ <description>Capture on CAPn.1 falling edge</description>
+ <bitRange>[4:4]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>ENABLE</name>
+ <description>A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC.</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLE</name>
+ <description>This feature is disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CAP1I</name>
+ <description>Interrupt on CAPn.1 event</description>
+ <bitRange>[5:5]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>ENABLE</name>
+ <description>A CR1 load due to a CAPn.1 event will generate an interrupt.</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLE</name>
+ <description>This feature is disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:6]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <dim>2</dim>
+ <dimIncrement>0x4</dimIncrement>
+ <dimIndex>0-1</dimIndex>
+ <name>CR[%s]</name>
+ <displayName>CR[%s]</displayName>
+ <description>Capture Register 0. CR0 is loaded with the value of TC when there is an event on the CAPn.0 input.</description>
+ <addressOffset>0x02C</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>CAP</name>
+ <description>Timer counter capture value.</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>EMR</name>
+ <description>External Match Register. The EMR controls the external match pins.</description>
+ <addressOffset>0x03C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>EM0</name>
+ <description>External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high).</description>
+ <bitRange>[0:0]</bitRange>
+
+ </field>
+ <field>
+ <name>EM1</name>
+ <description>External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high).</description>
+ <bitRange>[1:1]</bitRange>
+
+ </field>
+ <field>
+ <name>EM2</name>
+ <description>External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high).</description>
+ <bitRange>[2:2]</bitRange>
+
+ </field>
+ <field>
+ <name>EM3</name>
+ <description>External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high).</description>
+ <bitRange>[3:3]</bitRange>
+
+ </field>
+ <field>
+ <name>EMC0</name>
+ <description>External Match Control 0. Determines the functionality of External Match 0.</description>
+ <bitRange>[5:4]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DO_NOTHING_</name>
+ <description>Do Nothing.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CLEAR_THE_CORRESPOND</name>
+ <description>Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out).</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SET_THE_CORRESPONDIN</name>
+ <description>Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out).</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>TOGGLE_THE_CORRESPON</name>
+ <description>Toggle the corresponding External Match bit/output.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>EMC1</name>
+ <description>External Match Control 1. Determines the functionality of External Match 1.</description>
+ <bitRange>[7:6]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DO_NOTHING_</name>
+ <description>Do Nothing.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CLEAR_THE_CORRESPOND</name>
+ <description>Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out).</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SET_THE_CORRESPONDIN</name>
+ <description>Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out).</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>TOGGLE_THE_CORRESPON</name>
+ <description>Toggle the corresponding External Match bit/output.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>EMC2</name>
+ <description>External Match Control 2. Determines the functionality of External Match 2.</description>
+ <bitRange>[9:8]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DO_NOTHING_</name>
+ <description>Do Nothing.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CLEAR_THE_CORRESPOND</name>
+ <description>Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out).</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SET_THE_CORRESPONDIN</name>
+ <description>Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out).</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>TOGGLE_THE_CORRESPON</name>
+ <description>Toggle the corresponding External Match bit/output.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>EMC3</name>
+ <description>External Match Control 3. Determines the functionality of External Match 3.</description>
+ <bitRange>[11:10]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DO_NOTHING_</name>
+ <description>Do Nothing.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CLEAR_THE_CORRESPOND</name>
+ <description>Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out).</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SET_THE_CORRESPONDIN</name>
+ <description>Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out).</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>TOGGLE_THE_CORRESPON</name>
+ <description>Toggle the corresponding External Match bit/output.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:12]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CTCR</name>
+ <description>Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.</description>
+ <addressOffset>0x070</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>CTMODE</name>
+ <description>Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.</description>
+ <bitRange>[1:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>TIMER_MODE_EVERY_RI</name>
+ <description>Timer Mode: every rising PCLK edge</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RISING</name>
+ <description>Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>FALLING</name>
+ <description>Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DUALEDGE</name>
+ <description>Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CINSEL</name>
+ <description>Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.</description>
+ <bitRange>[3:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>CAPN_0_FOR_TIMERN</name>
+ <description>CAPn.0 for TIMERn</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CAPN_1_FOR_TIMERN</name>
+ <description>CAPn.1 for TIMERn</description>
+ <value>0x1</value>
+ </enumeratedValue>
+
+
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:4]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ </registers>
+</peripheral>
+ <peripheral derivedFrom="TIMER0">
+ <name>TIMER1</name>
+ <baseAddress>0x40008000</baseAddress>
+ <addressBlock>
+ <offset>0</offset>
+ <size>0xFFF</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>TIMER1</name>
+ <value>2</value>
+ </interrupt>
+ </peripheral>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ <peripheral>
+ <name>UART0</name>
+ <description>UART0/2/3 </description>
+ <groupName>UART0</groupName>
+ <baseAddress>0x4000C000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0xFFF</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>UART0</name>
+ <value>5</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>RBR</name>
+ <description>Receiver Buffer Register. Contains the next received character to be read (DLAB =0).</description>
+ <addressOffset>0x000</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <readAction>modify</readAction>
+ <fields>
+ <field>
+ <name>RBR</name>
+ <description>The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO.</description>
+ <bitRange>[7:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, the value read from a reserved bit is not defined.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>THR</name>
+ <description>Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0).</description>
+ <alternateRegister>RBR</alternateRegister>
+ <addressOffset>0x000</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>THR</name>
+ <description>Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available.</description>
+ <bitRange>[7:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DLL</name>
+ <description>Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1).</description>
+ <alternateRegister>RBR</alternateRegister>
+ <addressOffset>0x000</addressOffset>
+ <access>read-write</access>
+ <resetValue>0x01</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>DLLSB</name>
+ <description>The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn.</description>
+ <bitRange>[7:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DLM</name>
+ <description>Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1).</description>
+ <addressOffset>0x004</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>DLMSB</name>
+ <description>The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn.</description>
+ <bitRange>[7:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IER</name>
+ <description>Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0).</description>
+ <alternateRegister>DLM</alternateRegister>
+ <addressOffset>0x004</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RBRIE</name>
+ <description>RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt.</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE_THE_RDA_INTE</name>
+ <description>Disable the RDA interrupts.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE_THE_RDA_INTER</name>
+ <description>Enable the RDA interrupts.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>THREIE</name>
+ <description>THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5].</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE_THE_THRE_INT</name>
+ <description>Disable the THRE interrupts.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE_THE_THRE_INTE</name>
+ <description>Enable the THRE interrupts.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RXIE</name>
+ <description>RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1].</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE_THE_RX_LINE_</name>
+ <description>Disable the RX line status interrupts.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE_THE_RX_LINE_S</name>
+ <description>Enable the RX line status interrupts.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[7:3]</bitRange>
+
+ </field>
+ <field>
+ <name>ABEOINTEN</name>
+ <description>Enables the end of auto-baud interrupt.</description>
+ <bitRange>[8:8]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE_END_OF_AUTO_</name>
+ <description>Disable end of auto-baud Interrupt.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE_END_OF_AUTO_B</name>
+ <description>Enable end of auto-baud Interrupt.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>ABTOINTEN</name>
+ <description>Enables the auto-baud time-out interrupt.</description>
+ <bitRange>[9:9]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE_AUTO_BAUD_TI</name>
+ <description>Disable auto-baud time-out Interrupt.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE_AUTO_BAUD_TIM</name>
+ <description>Enable auto-baud time-out Interrupt.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:10]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IIR</name>
+ <description>Interrupt ID Register. Identifies which interrupt(s) are pending.</description>
+ <addressOffset>0x008</addressOffset>
+ <access>read-only</access>
+ <resetValue>0x01</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>INTSTATUS</name>
+ <description>Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1].</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>AT_LEAST_ONE_INTERRU</name>
+ <description>At least one interrupt is pending.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>NO_INTERRUPT_IS_PEND</name>
+ <description>No interrupt is pending.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>INTID</name>
+ <description>Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111).</description>
+ <bitRange>[3:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>1_RECEIVE_LINE_S</name>
+ <description>1 - Receive Line Status (RLS).</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>2A__RECEIVE_DATA_AV</name>
+ <description>2a - Receive Data Available (RDA).</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>2B__CHARACTER_TIME_</name>
+ <description>2b - Character Time-out Indicator (CTI).</description>
+ <value>0x6</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>3_THRE_INTERRUPT</name>
+ <description>3 - THRE Interrupt</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[5:4]</bitRange>
+
+ </field>
+ <field>
+ <name>FIFOENABLE</name>
+ <description>Copies of UnFCR[0].</description>
+ <bitRange>[7:6]</bitRange>
+
+ </field>
+ <field>
+ <name>ABEOINT</name>
+ <description>End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled.</description>
+ <bitRange>[8:8]</bitRange>
+
+ </field>
+ <field>
+ <name>ABTOINT</name>
+ <description>Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled.</description>
+ <bitRange>[9:9]</bitRange>
+
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:10]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FCR</name>
+ <description>FIFO Control Register. Controls UART FIFO usage and modes.</description>
+ <alternateRegister>IIR</alternateRegister>
+ <addressOffset>0x008</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>FIFOEN</name>
+ <description>FIFO Enable.</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>UARTN_FIFOS_ARE_DISA</name>
+ <description>UARTn FIFOs are disabled. Must not be used in the application.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ACTIVE_HIGH_ENABLE_F</name>
+ <description>Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RXFIFORES</name>
+ <description>RX FIFO Reset.</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>NO_IMPACT_ON_EITHER_</name>
+ <description>No impact on either of UARTn FIFOs.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>WRITING_A_LOGIC_1_TO</name>
+ <description>Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TXFIFORES</name>
+ <description>TX FIFO Reset.</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>NO_IMPACT_ON_EITHER_</name>
+ <description>No impact on either of UARTn FIFOs.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>WRITING_A_LOGIC_1_TO</name>
+ <description>Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>DMAMODE</name>
+ <description>DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1.</description>
+ <bitRange>[3:3]</bitRange>
+
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[5:4]</bitRange>
+
+ </field>
+ <field>
+ <name>RXTRIGLVL</name>
+ <description>RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated.</description>
+ <bitRange>[7:6]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>TRIGGER_LEVEL_0_1_C</name>
+ <description>Trigger level 0 (1 character or 0x01).</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>TRIGGER_LEVEL_1_4_C</name>
+ <description>Trigger level 1 (4 characters or 0x04).</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>TRIGGER_LEVEL_2_8_C</name>
+ <description>Trigger level 2 (8 characters or 0x08).</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>TRIGGER_LEVEL_3_14_</name>
+ <description>Trigger level 3 (14 characters or 0x0E).</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:8]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>LCR</name>
+ <description>Line Control Register. Contains controls for frame formatting and break generation.</description>
+ <addressOffset>0x00C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>WLS</name>
+ <description>Word Length Select.</description>
+ <bitRange>[1:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>5_BIT_CHARACTER_LENG</name>
+ <description>5-bit character length</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>6_BIT_CHARACTER_LENG</name>
+ <description>6-bit character length</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>7_BIT_CHARACTER_LENG</name>
+ <description>7-bit character length</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>8_BIT_CHARACTER_LENG</name>
+ <description>8-bit character length</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>SBS</name>
+ <description>Stop Bit Select</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>1_STOP_BIT_</name>
+ <description>1 stop bit.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>2_STOP_BITS_1_5_IF_</name>
+ <description>2 stop bits (1.5 if UnLCR[1:0]=00).</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PE</name>
+ <description>Parity Enable.</description>
+ <bitRange>[3:3]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE_PARITY_GENER</name>
+ <description>Disable parity generation and checking.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE_PARITY_GENERA</name>
+ <description>Enable parity generation and checking.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PS</name>
+ <description>Parity Select</description>
+ <bitRange>[5:4]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>ODD_PARITY_NUMBER_O</name>
+ <description>Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>EVEN_PARITY_NUMBER_</name>
+ <description>Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>FORCED_1_STICK_PARIT</name>
+ <description>Forced 1 stick parity.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>FORCED_0_STICK_PARIT</name>
+ <description>Forced 0 stick parity.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>BC</name>
+ <description>Break Control</description>
+ <bitRange>[6:6]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE_BREAK_TRANSM</name>
+ <description>Disable break transmission.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE_BREAK_TRANSMI</name>
+ <description>Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>DLAB</name>
+ <description>Divisor Latch Access Bit</description>
+ <bitRange>[7:7]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE_ACCESS_TO_DI</name>
+ <description>Disable access to Divisor Latches.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE_ACCESS_TO_DIV</name>
+ <description>Enable access to Divisor Latches.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:8]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>LSR</name>
+ <description>Line Status Register. Contains flags for transmit and receive status, including line errors.</description>
+ <addressOffset>0x014</addressOffset>
+ <access>read-only</access>
+ <resetValue>0x60</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <readAction>modify</readAction>
+ <fields>
+ <field>
+ <name>RDR</name>
+ <description>Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty.</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>EMPTY</name>
+ <description>The UARTn receiver FIFO is empty.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>NOTEMPTY</name>
+ <description>The UARTn receiver FIFO is not empty.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>OE</name>
+ <description>Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost.</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>INACTIVE</name>
+ <description>Overrun error status is inactive.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ACTIVE</name>
+ <description>Overrun error status is active.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PE</name>
+ <description>Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO.</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>INACTIVE</name>
+ <description>Parity error status is inactive.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ACTIVE</name>
+ <description>Parity error status is active.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>FE</name>
+ <description>Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO.</description>
+ <bitRange>[3:3]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>INACTIVE</name>
+ <description>Framing error status is inactive.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ACTIVE</name>
+ <description>Framing error status is active.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>BI</name>
+ <description>Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO.</description>
+ <bitRange>[4:4]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>INACTIVE</name>
+ <description>Break interrupt status is inactive.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ACTIVE</name>
+ <description>Break interrupt status is active.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>THRE</name>
+ <description>Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write.</description>
+ <bitRange>[5:5]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>VALIDDATA</name>
+ <description>UnTHR contains valid data.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>EMPTY</name>
+ <description>UnTHR is empty.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TEMT</name>
+ <description>Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data.</description>
+ <bitRange>[6:6]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>VALIDDATA</name>
+ <description>UnTHR and/or the UnTSR contains valid data.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>EMPTY</name>
+ <description>UnTHR and the UnTSR are empty.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RXFE</name>
+ <description>Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO.</description>
+ <bitRange>[7:7]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>NOERROR</name>
+ <description>UnRBR contains no UARTn RX errors or UnFCR[0]=0.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ERRORS</name>
+ <description>UARTn RBR contains at least one UARTn RX error.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:8]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SCR</name>
+ <description>Scratch Pad Register. 8-bit temporary storage for software.</description>
+ <addressOffset>0x01C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>PAD</name>
+ <description>A readable, writable byte.</description>
+ <bitRange>[7:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ACR</name>
+ <description>Auto-baud Control Register. Contains controls for the auto-baud feature.</description>
+ <addressOffset>0x020</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>START</name>
+ <description>Start bit. This bit is automatically cleared after auto-baud completion.</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>AUTO_BAUD_STOP_AUTO</name>
+ <description>Auto-baud stop (auto-baud is not running).</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>AUTO_BAUD_START_AUT</name>
+ <description>Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>MODE</name>
+ <description>Auto-baud mode select bit.</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>MODE_0_</name>
+ <description>Mode 0.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MODE_1_</name>
+ <description>Mode 1.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>AUTORESTART</name>
+ <description>Restart bit.</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>NO_RESTART_</name>
+ <description>No restart.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESTART_IN_CASE_OF_T</name>
+ <description>Restart in case of time-out (counter restarts at next UARTn Rx falling edge)</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[7:3]</bitRange>
+
+ </field>
+ <field>
+ <name>ABEOINTCLR</name>
+ <description>End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.</description>
+ <bitRange>[8:8]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>NO_IMPACT_</name>
+ <description>No impact.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CLEAR_THE_CORRESPOND</name>
+ <description>Clear the corresponding interrupt in the IIR.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>ABTOINTCLR</name>
+ <description>Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.</description>
+ <bitRange>[9:9]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>NO_IMPACT_</name>
+ <description>No impact.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CLEAR_THE_CORRESPOND</name>
+ <description>Clear the corresponding interrupt in the IIR.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:10]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FDR</name>
+ <description>Fractional Divider Register. Generates a clock input for the baud rate divider.</description>
+ <addressOffset>0x028</addressOffset>
+ <access>read-write</access>
+ <resetValue>0x10</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>DIVADDVAL</name>
+ <description>Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate.</description>
+ <bitRange>[3:0]</bitRange>
+
+ </field>
+ <field>
+ <name>MULVAL</name>
+ <description>Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not.</description>
+ <bitRange>[7:4]</bitRange>
+
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:8]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TER</name>
+ <description>Transmit Enable Register. Turns off UART transmitter for use with software flow control.</description>
+ <addressOffset>0x030</addressOffset>
+ <access>read-write</access>
+ <resetValue>0x80</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[6:0]</bitRange>
+ </field>
+ <field>
+ <name>TXEN</name>
+ <description>When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RS485CTRL</name>
+ <description>RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes.</description>
+ <addressOffset>0x04C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>NMMEN</name>
+ <description>NMM enable.</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLED</name>
+ <description>RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RXDIS</name>
+ <description>Receiver enable.</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>ENABLED</name>
+ <description>The receiver is enabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>The receiver is disabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>AADEN</name>
+ <description>AAD enable.</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Auto Address Detect (AAD) is disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLED</name>
+ <description>Auto Address Detect (AAD) is enabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[3:3]</bitRange>
+
+ </field>
+ <field>
+ <name>DCTRL</name>
+ <description>Direction control enable.</description>
+ <bitRange>[4:4]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE_AUTO_DIRECTI</name>
+ <description>Disable Auto Direction Control.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE_AUTO_DIRECTIO</name>
+ <description>Enable Auto Direction Control.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>OINV</name>
+ <description>Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin.</description>
+ <bitRange>[5:5]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DIRLOW</name>
+ <description>The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DIRHIGH</name>
+ <description>The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:6]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RS485ADRMATCH</name>
+ <description>RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode.</description>
+ <addressOffset>0x050</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>ADRMATCH</name>
+ <description>Contains the address match value.</description>
+ <bitRange>[7:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RS485DLY</name>
+ <description>RS-485/EIA-485 direction control delay.</description>
+ <addressOffset>0x054</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>DLY</name>
+ <description>Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter.</description>
+ <bitRange>[7:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+ </registers>
+
+ </peripheral>
+
+
+ <peripheral>
+ <name>UART1</name>
+ <description>UART1 </description>
+ <groupName>UART1</groupName>
+ <baseAddress>0x40010000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0xFFF</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>UART1</name>
+ <value>6</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>RBR</name>
+ <description>DLAB =0 Receiver Buffer Register. Contains the next received character to be read.</description>
+ <addressOffset>0x000</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <readAction>modify</readAction>
+ <fields>
+ <field>
+ <name>RBR</name>
+ <description>The UART1 Receiver Buffer Register contains the oldest received byte in the UART1 RX FIFO.</description>
+ <bitRange>[7:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, the value read from a reserved bit is not defined.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>THR</name>
+ <description>DLAB =0. Transmit Holding Register. The next character to be transmitted is written here.</description>
+ <alternateRegister>RBR</alternateRegister>
+ <addressOffset>0x000</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>THR</name>
+ <description>Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1 transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available.</description>
+ <bitRange>[7:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DLL</name>
+ <description>DLAB =1. Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.</description>
+ <alternateRegister>RBR</alternateRegister>
+ <addressOffset>0x000</addressOffset>
+ <access>read-write</access>
+ <resetValue>0x01</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>DLLSB</name>
+ <description>The UART1 Divisor Latch LSB Register, along with the U1DLM register, determines the baud rate of the UART1.</description>
+ <bitRange>[7:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DLM</name>
+ <description>DLAB =1. Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.</description>
+ <addressOffset>0x004</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>DLMSB</name>
+ <description>The UART1 Divisor Latch MSB Register, along with the U1DLL register, determines the baud rate of the UART1.</description>
+ <bitRange>[7:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IER</name>
+ <description>DLAB =0. Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts.</description>
+ <alternateRegister>DLM</alternateRegister>
+ <addressOffset>0x004</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RBRIE</name>
+ <description>RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It also controls the Character Receive Time-out interrupt.</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE_THE_RDA_INTE</name>
+ <description>Disable the RDA interrupts.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE_THE_RDA_INTER</name>
+ <description>Enable the RDA interrupts.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>THREIE</name>
+ <description>THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this interrupt can be read from LSR[5].</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE_THE_THRE_INT</name>
+ <description>Disable the THRE interrupts.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE_THE_THRE_INTE</name>
+ <description>Enable the THRE interrupts.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RXIE</name>
+ <description>RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The status of this interrupt can be read from LSR[4:1].</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE_THE_RX_LINE_</name>
+ <description>Disable the RX line status interrupts.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE_THE_RX_LINE_S</name>
+ <description>Enable the RX line status interrupts.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>MSIE</name>
+ <description>Modem Status Interrupt Enable. Enables the modem interrupt. The status of this interrupt can be read from MSR[3:0].</description>
+ <bitRange>[3:3]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE_THE_MODEM_IN</name>
+ <description>Disable the modem interrupt.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE_THE_MODEM_INT</name>
+ <description>Enable the modem interrupt.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[6:4]</bitRange>
+
+ </field>
+ <field>
+ <name>CTSIE</name>
+ <description>CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the modem status interrupt generation on a CTS1 signal transition. If auto-cts mode is disabled a CTS1 transition will generate an interrupt if Modem Status Interrupt Enable (IER[3]) is set. In normal operation a CTS1 signal transition will generate a Modem Status Interrupt unless the interrupt has been disabled by clearing the IER[3] bit in the IER register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both the IER[3] and IER[7] bits are set.</description>
+ <bitRange>[7:7]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE_THE_CTS_INTE</name>
+ <description>Disable the CTS interrupt.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE_THE_CTS_INTER</name>
+ <description>Enable the CTS interrupt.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>ABEOIE</name>
+ <description>Enables the end of auto-baud interrupt.</description>
+ <bitRange>[8:8]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE_END_OF_AUTO_</name>
+ <description>Disable end of auto-baud Interrupt.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE_END_OF_AUTO_B</name>
+ <description>Enable end of auto-baud Interrupt.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>ABTOIE</name>
+ <description>Enables the auto-baud time-out interrupt.</description>
+ <bitRange>[9:9]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE_AUTO_BAUD_TI</name>
+ <description>Disable auto-baud time-out Interrupt.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE_AUTO_BAUD_TIM</name>
+ <description>Enable auto-baud time-out Interrupt.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:10]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IIR</name>
+ <description>Interrupt ID Register. Identifies which interrupt(s) are pending.</description>
+ <addressOffset>0x008</addressOffset>
+ <access>read-only</access>
+ <resetValue>0x01</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>INTSTATUS</name>
+ <description>Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>AT_LEAST_ONE_INTERRU</name>
+ <description>At least one interrupt is pending.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>NO_INTERRUPT_IS_PEND</name>
+ <description>No interrupt is pending.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>INTID</name>
+ <description>Interrupt identification. IER[3:1] identifies an interrupt corresponding to the UART1 Rx or TX FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).</description>
+ <bitRange>[3:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>RLS</name>
+ <description>1 - Receive Line Status (RLS).</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RDA</name>
+ <description>2a - Receive Data Available (RDA).</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CTI</name>
+ <description>2b - Character Time-out Indicator (CTI).</description>
+ <value>0x6</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>THRE</name>
+ <description>3 - THRE Interrupt.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MODEM</name>
+ <description>4 - Modem Interrupt.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[5:4]</bitRange>
+
+ </field>
+ <field>
+ <name>FIFOENABLE</name>
+ <description>Copies of FCR[0].</description>
+ <bitRange>[7:6]</bitRange>
+
+ </field>
+ <field>
+ <name>ABEOINT</name>
+ <description>End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled.</description>
+ <bitRange>[8:8]</bitRange>
+
+ </field>
+ <field>
+ <name>ABTOINT</name>
+ <description>Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled.</description>
+ <bitRange>[9:9]</bitRange>
+
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, the value read from a reserved bit is not defined.</description>
+ <bitRange>[31:10]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FCR</name>
+ <description>FIFO Control Register. Controls UART1 FIFO usage and modes.</description>
+ <alternateRegister>IIR</alternateRegister>
+ <addressOffset>0x008</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>FIFOEN</name>
+ <description>FIFO enable.</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>MUST_NOT_BE_USED_IN_</name>
+ <description>Must not be used in the application.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ACTIVE_HIGH_ENABLE_F</name>
+ <description>Active high enable for both UART1 Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper UART1 operation. Any transition on this bit will automatically clear the UART1 FIFOs.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RXFIFORES</name>
+ <description>RX FIFO Reset.</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>NO_IMPACT_ON_EITHER_</name>
+ <description>No impact on either of UART1 FIFOs.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>WRITING_A_LOGIC_1_TO</name>
+ <description>Writing a logic 1 to FCR[1] will clear all bytes in UART1 Rx FIFO, reset the pointer logic. This bit is self-clearing.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TXFIFORES</name>
+ <description>TX FIFO Reset.</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>NO_IMPACT_ON_EITHER_</name>
+ <description>No impact on either of UART1 FIFOs.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>WRITING_A_LOGIC_1_TO</name>
+ <description>Writing a logic 1 to FCR[2] will clear all bytes in UART1 TX FIFO, reset the pointer logic. This bit is self-clearing.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>DMAMODE</name>
+ <description>DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode. See Section 36.6.6.1.</description>
+ <bitRange>[3:3]</bitRange>
+
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[5:4]</bitRange>
+
+ </field>
+ <field>
+ <name>RXTRIGLVL</name>
+ <description>RX Trigger Level. These two bits determine how many receiver UART1 FIFO characters must be written before an interrupt is activated.</description>
+ <bitRange>[7:6]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>TRIGGER_LEVEL_0_1_C</name>
+ <description>Trigger level 0 (1 character or 0x01).</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>TRIGGER_LEVEL_1_4_C</name>
+ <description>Trigger level 1 (4 characters or 0x04).</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>TRIGGER_LEVEL_2_8_C</name>
+ <description>Trigger level 2 (8 characters or 0x08).</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>TRIGGER_LEVEL_3_14_</name>
+ <description>Trigger level 3 (14 characters or 0x0E).</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits.</description>
+ <bitRange>[31:8]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>LCR</name>
+ <description>Line Control Register. Contains controls for frame formatting and break generation.</description>
+ <addressOffset>0x00C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>WLS</name>
+ <description>Word Length Select.</description>
+ <bitRange>[1:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>5_BIT_CHARACTER_LENG</name>
+ <description>5-bit character length.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>6_BIT_CHARACTER_LENG</name>
+ <description>6-bit character length.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>7_BIT_CHARACTER_LENG</name>
+ <description>7-bit character length.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>8_BIT_CHARACTER_LENG</name>
+ <description>8-bit character length.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>SBS</name>
+ <description>Stop Bit Select.</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>1_STOP_BIT_</name>
+ <description>1 stop bit.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>2_STOP_BITS_1_5_IF_</name>
+ <description>2 stop bits (1.5 if LCR[1:0]=00).</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PE</name>
+ <description>Parity Enable.</description>
+ <bitRange>[3:3]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE_PARITY_GENER</name>
+ <description>Disable parity generation and checking.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE_PARITY_GENERA</name>
+ <description>Enable parity generation and checking.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PS</name>
+ <description>Parity Select.</description>
+ <bitRange>[5:4]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>ODD_PARITY_NUMBER_O</name>
+ <description>Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>EVEN_PARITY_NUMBER_</name>
+ <description>Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>FORCED1STICK_PAR</name>
+ <description>Forced 1 stick parity.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>FORCED0STICK_PAR</name>
+ <description>Forced 0 stick parity.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>BC</name>
+ <description>Break Control.</description>
+ <bitRange>[6:6]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE_BREAK_TRANSM</name>
+ <description>Disable break transmission.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE_BREAK_TRANSMI</name>
+ <description>Enable break transmission. Output pin UART1 TXD is forced to logic 0 when LCR[6] is active high.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>DLAB</name>
+ <description>Divisor Latch Access Bit (DLAB)</description>
+ <bitRange>[7:7]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE_ACCESS_TO_DI</name>
+ <description>Disable access to Divisor Latches.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE_ACCESS_TO_DIV</name>
+ <description>Enable access to Divisor Latches.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:8]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>MCR</name>
+ <description>Modem Control Register. Contains controls for flow control handshaking and loopback mode.</description>
+ <addressOffset>0x010</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>DTRCTRL</name>
+ <description>DTR Control. Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active.</description>
+ <bitRange>[0:0]</bitRange>
+
+ </field>
+ <field>
+ <name>RTSCTRL</name>
+ <description>RTS Control. Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active.</description>
+ <bitRange>[1:1]</bitRange>
+
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[3:2]</bitRange>
+
+ </field>
+ <field>
+ <name>LMS</name>
+ <description>Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to the 4 modem inputs. As a result of these connections, the upper 4 bits of the MSR will be driven by the lower 4 bits of the MCR rather than the 4 modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower 4 bits of MCR.</description>
+ <bitRange>[4:4]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE_MODEM_LOOPBA</name>
+ <description>Disable modem loopback mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE_MODEM_LOOPBAC</name>
+ <description>Enable modem loopback mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[5:5]</bitRange>
+
+ </field>
+ <field>
+ <name>RTSEN</name>
+ <description>RTS enable.</description>
+ <bitRange>[6:6]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE_AUTO_RTS_FLO</name>
+ <description>Disable auto-rts flow control.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE_AUTO_RTS_FLOW</name>
+ <description>Enable auto-rts flow control.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CTSEN</name>
+ <description>CTS enable.</description>
+ <bitRange>[7:7]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE_AUTO_CTS_FLO</name>
+ <description>Disable auto-cts flow control.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE_AUTO_CTS_FLOW</name>
+ <description>Enable auto-cts flow control.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:8]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>LSR</name>
+ <description>Line Status Register. Contains flags for transmit and receive status, including line errors.</description>
+ <addressOffset>0x014</addressOffset>
+ <access>read-only</access>
+ <resetValue>0x60</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <readAction>modify</readAction>
+ <fields>
+ <field>
+ <name>RDR</name>
+ <description>Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the UART1 RBR FIFO is empty.</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>EMPTY</name>
+ <description>The UART1 receiver FIFO is empty.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>NOTEMPTY</name>
+ <description>The UART1 receiver FIFO is not empty.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>OE</name>
+ <description>Overrun Error. The overrun error condition is set as soon as it occurs. An LSR read clears LSR[1]. LSR[1] is set when UART1 RSR has a new character assembled and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be overwritten and the character in the UART1 RSR will be lost.</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>INACTIVE</name>
+ <description>Overrun error status is inactive.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ACTIVE</name>
+ <description>Overrun error status is active.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PE</name>
+ <description>Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART1 RBR FIFO.</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>INACTIVE</name>
+ <description>Parity error status is inactive.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ACTIVE</name>
+ <description>Parity error status is active.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>FE</name>
+ <description>Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART1 RBR FIFO.</description>
+ <bitRange>[3:3]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>INACTIVE</name>
+ <description>Framing error status is inactive.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ACTIVE</name>
+ <description>Framing error status is active.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>BI</name>
+ <description>Break Interrupt. When RXD1 is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). An LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART1 RBR FIFO.</description>
+ <bitRange>[4:4]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>INACTIVE</name>
+ <description>Break interrupt status is inactive.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ACTIVE</name>
+ <description>Break interrupt status is active.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>THRE</name>
+ <description>Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UART1 THR and is cleared on a THR write.</description>
+ <bitRange>[5:5]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>VALID</name>
+ <description>THR contains valid data.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>THR_IS_EMPTY_</name>
+ <description>THR is empty.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TEMT</name>
+ <description>Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.</description>
+ <bitRange>[6:6]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>VALID</name>
+ <description>THR and/or the TSR contains valid data.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>EMPTY</name>
+ <description>THR and the TSR are empty.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RXFE</name>
+ <description>Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART1 FIFO.</description>
+ <bitRange>[7:7]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>NOERROR</name>
+ <description>RBR contains no UART1 RX errors or FCR[0]=0.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ERRORS</name>
+ <description>UART1 RBR contains at least one UART1 RX error.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, the value read from a reserved bit is not defined.</description>
+ <bitRange>[31:8]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>MSR</name>
+ <description>Modem Status Register. Contains handshake signal status flags.</description>
+ <addressOffset>0x018</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <readAction>modify</readAction>
+ <fields>
+ <field>
+ <name>DCTS</name>
+ <description>Delta CTS. Set upon state change of input CTS. Cleared on an MSR read.</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>NO_CHANGE_DETECTED_O</name>
+ <description>No change detected on modem input, CTS.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>STATE_CHANGE_DETECTE</name>
+ <description>State change detected on modem input, CTS.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>DDSR</name>
+ <description>Delta DSR. Set upon state change of input DSR. Cleared on an MSR read.</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>NO_CHANGE_DETECTED_O</name>
+ <description>No change detected on modem input, DSR.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>STATE_CHANGE_DETECTE</name>
+ <description>State change detected on modem input, DSR.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TERI</name>
+ <description>Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read.</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>NO_CHANGE_DETECTED_O</name>
+ <description>No change detected on modem input, RI.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>LOW_TO_HIGH_TRANSITI</name>
+ <description>Low-to-high transition detected on RI.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>DDCD</name>
+ <description>Delta DCD. Set upon state change of input DCD. Cleared on an MSR read.</description>
+ <bitRange>[3:3]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>NO_CHANGE_DETECTED_O</name>
+ <description>No change detected on modem input, DCD.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>STATE_CHANGE_DETECTE</name>
+ <description>State change detected on modem input, DCD.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CTS</name>
+ <description>Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode.</description>
+ <bitRange>[4:4]</bitRange>
+
+ </field>
+ <field>
+ <name>DSR</name>
+ <description>Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode.</description>
+ <bitRange>[5:5]</bitRange>
+
+ </field>
+ <field>
+ <name>RI</name>
+ <description>Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode.</description>
+ <bitRange>[6:6]</bitRange>
+
+ </field>
+ <field>
+ <name>DCD</name>
+ <description>Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode.</description>
+ <bitRange>[7:7]</bitRange>
+
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, the value read from a reserved bit is not defined.</description>
+ <bitRange>[31:8]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SCR</name>
+ <description>Scratch Pad Register. 8-bit temporary storage for software.</description>
+ <addressOffset>0x01C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>Pad</name>
+ <description>A readable, writable byte.</description>
+ <bitRange>[7:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ACR</name>
+ <description>Auto-baud Control Register. Contains controls for the auto-baud feature.</description>
+ <addressOffset>0x020</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>START</name>
+ <description>Auto-baud start bit. This bit is automatically cleared after auto-baud completion.</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>STOP</name>
+ <description>Auto-baud stop (auto-baud is not running).</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>START</name>
+ <description>Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>MODE</name>
+ <description>Auto-baud mode select bit.</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>MODE_0_</name>
+ <description>Mode 0.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MODE_1_</name>
+ <description>Mode 1.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>AUTORESTART</name>
+ <description>Auto-baud restart bit.</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>NO_RESTART</name>
+ <description>No restart</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESTART_IN_CASE_OF_T</name>
+ <description>Restart in case of time-out (counter restarts at next UART1 Rx falling edge)</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[7:3]</bitRange>
+
+ </field>
+ <field>
+ <name>ABEOINTCLR</name>
+ <description>End of auto-baud interrupt clear bit (write-only).</description>
+ <bitRange>[8:8]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>WRITING_A_0_HAS_NO_I</name>
+ <description>Writing a 0 has no impact.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>WRITING_A_1_WILL_CLE</name>
+ <description>Writing a 1 will clear the corresponding interrupt in the IIR.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>ABTOINTCLR</name>
+ <description>Auto-baud time-out interrupt clear bit (write-only).</description>
+ <bitRange>[9:9]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>WRITING_A_0_HAS_NO_I</name>
+ <description>Writing a 0 has no impact.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>WRITING_A_1_WILL_CLE</name>
+ <description>Writing a 1 will clear the corresponding interrupt in the IIR.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:10]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FDR</name>
+ <description>Fractional Divider Register. Generates a clock input for the baud rate divider.</description>
+ <addressOffset>0x028</addressOffset>
+ <access>read-write</access>
+ <resetValue>0x10</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>DIVADDVAL</name>
+ <description>Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the UART1 baud rate.</description>
+ <bitRange>[3:0]</bitRange>
+
+ </field>
+ <field>
+ <name>MULVAL</name>
+ <description>Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for UART1 to operate properly, regardless of whether the fractional baud rate generator is used or not.</description>
+ <bitRange>[7:4]</bitRange>
+
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:8]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TER</name>
+ <description>Transmit Enable Register. Turns off UART transmitter for use with software flow control.</description>
+ <addressOffset>0x030</addressOffset>
+ <access>read-write</access>
+ <resetValue>0x80</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[6:0]</bitRange>
+ </field>
+ <field>
+ <name>TXEN</name>
+ <description>When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RS485CTRL</name>
+ <description>RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes.</description>
+ <addressOffset>0x04C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>NMMEN</name>
+ <description>RS-485/EIA-485 Normal Multidrop Mode (NMM) mode select.</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLED_</name>
+ <description>Disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLED_IN_THIS_MOD</name>
+ <description>Enabled. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RXDIS</name>
+ <description>Receive enable.</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>ENABLED_</name>
+ <description>Enabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED_</name>
+ <description>Disabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>AADEN</name>
+ <description>Auto Address Detect (AAD) enable.</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLED_</name>
+ <description>Disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLED_</name>
+ <description>Enabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>SEL</name>
+ <description>Direction control.</description>
+ <bitRange>[3:3]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>RTS_IF_DIRECTION_CO</name>
+ <description>RTS. If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DTR_IF_DIRECTION_CO</name>
+ <description>DTR. If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>DCTRL</name>
+ <description>Direction control enable.</description>
+ <bitRange>[4:4]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE_AUTO_DIRECTI</name>
+ <description>Disable Auto Direction Control.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE_AUTO_DIRECTIO</name>
+ <description>Enable Auto Direction Control.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>OINV</name>
+ <description>Polarity. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.</description>
+ <bitRange>[5:5]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>LOW_THE_DIRECTION_C</name>
+ <description>LOW. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>HIGH_THE_DIRECTION_</name>
+ <description>HIGH. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:6]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RS485ADRMATCH</name>
+ <description>RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode.</description>
+ <addressOffset>0x050</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>ADRMATCH</name>
+ <description>Contains the address match value.</description>
+ <bitRange>[7:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RS485DLY</name>
+ <description>RS-485/EIA-485 direction control delay.</description>
+ <addressOffset>0x054</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>DLY</name>
+ <description>Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter.</description>
+ <bitRange>[7:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+ </registers>
+</peripheral>
+
+ <peripheral>
+ <name>PWM1</name>
+ <description>Pulse Width Modulators (PWM1) </description>
+ <groupName>PWM</groupName>
+ <baseAddress>0x40018000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0xFFF</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>PWM1</name>
+ <value>9</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>IR</name>
+ <description>Interrupt Register. The IR can be written to clear interrupts, or read to identify which PWM interrupt sources are pending.</description>
+ <addressOffset>0x000</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>PWMMR0INT</name>
+ <description>Interrupt flag for PWM match channel 0.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>PWMMR1INT</name>
+ <description>Interrupt flag for PWM match channel 1.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>PWMMR2INT</name>
+ <description>Interrupt flag for PWM match channel 2.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>PWMMR3INT</name>
+ <description>Interrupt flag for PWM match channel 3.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>PWMCAP0INT</name>
+ <description>Interrupt flag for capture input 0</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>PWMCAP1INT</name>
+ <description>Interrupt flag for capture input 1 (available in PWM1IR only; this bit is reserved in PWM0IR).</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[7:6]</bitRange>
+ </field>
+ <field>
+ <name>PWMMR4INT</name>
+ <description>Interrupt flag for PWM match channel 4.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>PWMMR5INT</name>
+ <description>Interrupt flag for PWM match channel 5.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>PWMMR6INT</name>
+ <description>Interrupt flag for PWM match channel 6.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:11]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TCR</name>
+ <description>Timer Control Register. The TCR is used to control the Timer Counter functions.</description>
+ <addressOffset>0x004</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>CE</name>
+ <description>Counter Enable</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>THE_PWM_TIMER_COUNTE</name>
+ <description>The PWM Timer Counter and PWM Prescale Counter are enabled for counting.</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>THE_COUNTERS_ARE_DIS</name>
+ <description>The counters are disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CR</name>
+ <description>Counter Reset</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>THE_PWM_TIMER_COUNTE</name>
+ <description>The PWM Timer Counter and the PWM Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until this bit is returned to zero.</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CLEAR_RESET_</name>
+ <description>Clear reset.</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[2:2]</bitRange>
+
+ </field>
+ <field>
+ <name>PWMEN</name>
+ <description>PWM Enable</description>
+ <bitRange>[3:3]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>PWM_MODE_IS_ENABLED_</name>
+ <description>PWM mode is enabled (counter resets to 1). PWM mode causes the shadow registers to operate in connection with the Match registers. A program write to a Match register will not have an effect on the Match result until the corresponding bit in PWMLER has been set, followed by the occurrence of a PWM Match 0 event. Note that the PWM Match register that determines the PWM rate (PWM Match Register 0 - MR0) must be set up prior to the PWM being enabled. Otherwise a Match event will not occur to cause shadow register contents to become effective.</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>TIMER_MODE_IS_ENABLE</name>
+ <description>Timer mode is enabled (counter resets to 0).</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>MDIS</name>
+ <description>Master Disable (PWM0 only). The two PWMs may be synchronized using the Master Disable control bit. The Master disable bit of the Master PWM (PWM0 module) controls a secondary enable input to both PWMs, as shown in Figure 141. This bit has no function in the Slave PWM (PWM1).</description>
+ <bitRange>[4:4]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>MASTER_USE_PWM0_IS_</name>
+ <description>Master use. PWM0 is the master, and both PWMs are enabled for counting.</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>INDIVIDUAL_USE_THE_</name>
+ <description>Individual use. The PWMs are used independently, and the individual Counter Enable bits are used to control the PWMs.</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:5]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TC</name>
+ <description>Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.</description>
+ <addressOffset>0x008</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>TC</name>
+ <description>Timer counter value.</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PR</name>
+ <description>Prescale Register. Determines how often the PWM counter is incremented.</description>
+ <addressOffset>0x00C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>PM</name>
+ <description>Prescale counter maximum value.</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PC</name>
+ <description>Prescale Counter. Prescaler for the main PWM counter.</description>
+ <addressOffset>0x010</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>PC</name>
+ <description>Prescale counter value.</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>MCR</name>
+ <description>Match Control Register. The MCR is used to control whether an interrupt is generated and if the PWM counter is reset when a Match occurs.</description>
+ <addressOffset>0x014</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>PWMMR0I</name>
+ <description>Interrupt PWM0</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLED_</name>
+ <description>Disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>INTERRUPT_ON_PWMMR0</name>
+ <description>Interrupt on PWMMR0: an interrupt is generated when PWMMR0 matches the value in the PWMTC.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PWMMR0R</name>
+ <description>Reset PWM0</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLED_</name>
+ <description>Disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESET_ON_PWMMR0_THE</name>
+ <description>Reset on PWMMR0: the PWMTC will be reset if PWMMR0 matches it.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PWMMR0S</name>
+ <description>Stop PWM0</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>STOP_ON_PWMMR0_THE_</name>
+ <description>Stop on PWMMR0: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PWMMR1I</name>
+ <description>Interrupt PWM1</description>
+ <bitRange>[3:3]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLED_</name>
+ <description>Disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>INTERRUPT_ON_PWMMR1</name>
+ <description>Interrupt on PWMMR1: an interrupt is generated when PWMMR1 matches the value in the PWMTC.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PWMMR1R</name>
+ <description>Reset PWM1</description>
+ <bitRange>[4:4]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLED_</name>
+ <description>Disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESET_ON_PWMMR1_THE</name>
+ <description>Reset on PWMMR1: the PWMTC will be reset if PWMMR1 matches it.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PWMMR1S</name>
+ <description>Stop PWM1</description>
+ <bitRange>[5:5]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>STOP_ON_PWMMR1_THE_</name>
+ <description>Stop on PWMMR1: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR1 matches the PWMTC.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PWMMR2I</name>
+ <description>Interrupt PWM0</description>
+ <bitRange>[6:6]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLED_</name>
+ <description>Disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>INTERRUPT_ON_PWMMR2</name>
+ <description>Interrupt on PWMMR2: an interrupt is generated when PWMMR2 matches the value in the PWMTC.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PWMMR2R</name>
+ <description>Reset PWM0</description>
+ <bitRange>[7:7]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLED_</name>
+ <description>Disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESET_ON_PWMMR2_THE</name>
+ <description>Reset on PWMMR2: the PWMTC will be reset if PWMMR2 matches it.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PWMMR2S</name>
+ <description>Stop PWM0</description>
+ <bitRange>[8:8]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>STOP_ON_PWMMR2_THE_</name>
+ <description>Stop on PWMMR2: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PWMMR3I</name>
+ <description>Interrupt PWM3</description>
+ <bitRange>[9:9]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLED_</name>
+ <description>Disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>INTERRUPT_ON_PWMMR3</name>
+ <description>Interrupt on PWMMR3: an interrupt is generated when PWMMR3 matches the value in the PWMTC.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PWMMR3R</name>
+ <description>Reset PWM3</description>
+ <bitRange>[10:10]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLED_</name>
+ <description>Disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESET_ON_PWMMR3_THE</name>
+ <description>Reset on PWMMR3: the PWMTC will be reset if PWMMR3 matches it.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PWMMR3S</name>
+ <description>Stop PWM0</description>
+ <bitRange>[11:11]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>STOP_ON_PWMMR3_THE_</name>
+ <description>Stop on PWMMR3: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PWMMR4I</name>
+ <description>Interrupt PWM4</description>
+ <bitRange>[12:12]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLED_</name>
+ <description>Disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>INTERRUPT_ON_PWMMR4</name>
+ <description>Interrupt on PWMMR4: an interrupt is generated when PWMMR4 matches the value in the PWMTC.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PWMMR4R</name>
+ <description>Reset PWM4</description>
+ <bitRange>[13:13]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLED_</name>
+ <description>Disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESET_ON_PWMMR4_THE</name>
+ <description>Reset on PWMMR4: the PWMTC will be reset if PWMMR4 matches it.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PWMMR4S</name>
+ <description>Stop PWM4</description>
+ <bitRange>[14:14]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>STOP_ON_PWMMR4_THE_</name>
+ <description>Stop on PWMMR4: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR4 matches the PWMTC.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PWMMR5I</name>
+ <description>Interrupt PWM5</description>
+ <bitRange>[15:15]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLED_</name>
+ <description>Disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>INTERRUPT_ON_PWMMR5</name>
+ <description>Interrupt on PWMMR5: an interrupt is generated when PWMMR5 matches the value in the PWMTC.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PWMMR5R</name>
+ <description>Reset PWM5</description>
+ <bitRange>[16:16]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLED_</name>
+ <description>Disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESET_ON_PWMMR5_THE</name>
+ <description>Reset on PWMMR5: the PWMTC will be reset if PWMMR5 matches it.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PWMMR5S</name>
+ <description>Stop PWM5</description>
+ <bitRange>[17:17]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>STOP_ON_PWMMR5_THE_</name>
+ <description>Stop on PWMMR5: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR5 matches the PWMTC.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PWMMR6I</name>
+ <description>Interrupt PWM6</description>
+ <bitRange>[18:18]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLED_</name>
+ <description>Disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>INTERRUPT_ON_PWMMR6</name>
+ <description>Interrupt on PWMMR6: an interrupt is generated when PWMMR6 matches the value in the PWMTC.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PWMMR6R</name>
+ <description>Reset PWM6</description>
+ <bitRange>[19:19]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLED_</name>
+ <description>Disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESET_ON_PWMMR6_THE</name>
+ <description>Reset on PWMMR6: the PWMTC will be reset if PWMMR6 matches it.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PWMMR6S</name>
+ <description>Stop PWM6</description>
+ <bitRange>[20:20]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>STOP_ON_PWMMR6_THE_</name>
+ <description>Stop on PWMMR6: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR6 matches the PWMTC.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:21]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <dim>4</dim>
+ <dimIncrement>0x4</dimIncrement>
+ <dimIndex>0-3</dimIndex>
+ <name>MR%s</name>
+
+ <description>Match Register. Match registers
+are continuously compared to the PWM counter in order to control PWM
+output edges.</description>
+ <addressOffset>0x018</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>MATCH</name>
+ <description>Timer counter match value.</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCR</name>
+ <description>Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated for a capture event.</description>
+ <addressOffset>0x028</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>CAP0_R</name>
+ <description>Capture on PWMn_CAP0 rising edge</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLED_THIS_FEATU</name>
+ <description>Disabled. This feature is disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RISING_EDGE_A_SYNCH</name>
+ <description>Rising edge. A synchronously sampled rising edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of the TC.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CAP0_F</name>
+ <description>Capture on PWMn_CAP0 falling edge</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLED_THIS_FEATU</name>
+ <description>Disabled. This feature is disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>FALLING_EDGE_A_SYNC</name>
+ <description>Falling edge. A synchronously sampled falling edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of TC.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CAP0_I</name>
+ <description>Interrupt on PWMn_CAP0 event</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLED_THIS_FEATU</name>
+ <description>Disabled. This feature is disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>INTERRUPT_A_CR0_LOA</name>
+ <description>Interrupt. A CR0 load due to a PWMn_CAP0 event will generate an interrupt.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CAP1_R</name>
+ <description>Capture on PWMn_CAP1 rising edge. Reserved for PWM0.</description>
+ <bitRange>[3:3]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLED_THIS_FEATU</name>
+ <description>Disabled. This feature is disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RISING_EDGE_A_SYNCH</name>
+ <description>Rising edge. A synchronously sampled rising edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of the TC.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CAP1_F</name>
+ <description>Capture on PWMn_CAP1 falling edge. Reserved for PWM0.</description>
+ <bitRange>[4:4]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLED_THIS_FEATU</name>
+ <description>Disabled. This feature is disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>FALLING_EDGE_A_SYNC</name>
+ <description>Falling edge. A synchronously sampled falling edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of TC.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CAP1_I</name>
+ <description>Interrupt on PWMn_CAP1 event. Reserved for PWM0.</description>
+ <bitRange>[5:5]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLED_THIS_FEATU</name>
+ <description>Disabled. This feature is disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>INTERRUPT_A_CR1_LOA</name>
+ <description>Interrupt. A CR1 load due to a PWMn_CAP1 event will generate an interrupt.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:6]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <dim>2</dim>
+ <dimIncrement>0x4</dimIncrement>
+ <dimIndex>0-1</dimIndex>
+ <name>CR[%s]</name>
+ <displayName>CR[%s]</displayName>
+ <description>PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs.</description>
+ <addressOffset>0x02C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[1:0]</bitRange>
+
+ </field>
+ <field>
+ <name>PWMSEL2</name>
+ <description>PWM[2] output single/double edge mode control.</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>SINGLE_EDGE_CONTROLL</name>
+ <description>Single edge controlled mode is selected.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DOUBLE_EDGE_CONTROLL</name>
+ <description>Double edge controlled mode is selected.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PWMSEL3</name>
+ <description>PWM[3] output edge control.</description>
+ <bitRange>[3:3]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>SINGLE_EDGE_CONTROLL</name>
+ <description>Single edge controlled mode is selected.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DOUBLE_EDGE_CONTROLL</name>
+ <description>Double edge controlled mode is selected.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PWMSEL4</name>
+ <description>PWM[4] output edge control.</description>
+ <bitRange>[4:4]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>SINGLE_EDGE_CONTROLL</name>
+ <description>Single edge controlled mode is selected.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DOUBLE_EDGE_CONTROLL</name>
+ <description>Double edge controlled mode is selected.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PWMSEL5</name>
+ <description>PWM[5] output edge control.</description>
+ <bitRange>[5:5]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>SINGLE_EDGE_CONTROLL</name>
+ <description>Single edge controlled mode is selected.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DOUBLE_EDGE_CONTROLL</name>
+ <description>Double edge controlled mode is selected.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PWMSEL6</name>
+ <description>PWM[6] output edge control.</description>
+ <bitRange>[6:6]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>SINGLE_EDGE_CONTROLL</name>
+ <description>Single edge controlled mode is selected.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DOUBLE_EDGE_CONTROLL</name>
+ <description>Double edge controlled mode is selected.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[8:7]</bitRange>
+
+ </field>
+ <field>
+ <name>PWMENA1</name>
+ <description>PWM[1] output enable control.</description>
+ <bitRange>[9:9]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>THE_PWM_OUTPUT_IS_DI</name>
+ <description>The PWM output is disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>THE_PWM_OUTPUT_IS_EN</name>
+ <description>The PWM output is enabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PWMENA2</name>
+ <description>PWM[2] output enable control.</description>
+ <bitRange>[10:10]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>THE_PWM_OUTPUT_IS_DI</name>
+ <description>The PWM output is disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>THE_PWM_OUTPUT_IS_EN</name>
+ <description>The PWM output is enabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PWMENA3</name>
+ <description>PWM[3] output enable control.</description>
+ <bitRange>[11:11]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>THE_PWM_OUTPUT_IS_DI</name>
+ <description>The PWM output is disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>THE_PWM_OUTPUT_IS_EN</name>
+ <description>The PWM output is enabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PWMENA4</name>
+ <description>PWM[4] output enable control.</description>
+ <bitRange>[12:12]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>THE_PWM_OUTPUT_IS_DI</name>
+ <description>The PWM output is disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>THE_PWM_OUTPUT_IS_EN</name>
+ <description>The PWM output is enabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PWMENA5</name>
+ <description>PWM[5] output enable control.</description>
+ <bitRange>[13:13]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>THE_PWM_OUTPUT_IS_DI</name>
+ <description>The PWM output is disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>THE_PWM_OUTPUT_IS_EN</name>
+ <description>The PWM output is enabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PWMENA6</name>
+ <description>PWM[6] output enable control. See PWMENA1 for details.</description>
+ <bitRange>[14:14]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>THE_PWM_OUTPUT_IS_DI</name>
+ <description>The PWM output is disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>THE_PWM_OUTPUT_IS_EN</name>
+ <description>The PWM output is enabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused, always zero.</description>
+ <bitRange>[31:15]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <dim>3</dim>
+ <dimIncrement>0x4</dimIncrement>
+ <dimIndex>4-6</dimIndex>
+ <name>MR%s</name>
+
+ <description>Match Register. Match registers
+are continuously compared to the PWM counter in order to control PWM
+output edges.</description>
+ <addressOffset>0x040</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>MATCH</name>
+ <description>Timer counter match value.</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PCR</name>
+ <description>PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs.</description>
+ <addressOffset>0x04C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[1:0]</bitRange>
+
+ </field>
+ <field>
+ <name>PWMSEL2</name>
+ <description>PWM[2] output single/double edge mode control.</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>SINGLE_EDGE_CONTROLL</name>
+ <description>Single edge controlled mode is selected.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DOUBLE_EDGE_CONTROLL</name>
+ <description>Double edge controlled mode is selected.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PWMSEL3</name>
+ <description>PWM[3] output edge control.</description>
+ <bitRange>[3:3]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>SINGLE_EDGE_CONTROLL</name>
+ <description>Single edge controlled mode is selected.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DOUBLE_EDGE_CONTROLL</name>
+ <description>Double edge controlled mode is selected.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PWMSEL4</name>
+ <description>PWM[4] output edge control.</description>
+ <bitRange>[4:4]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>SINGLE_EDGE_CONTROLL</name>
+ <description>Single edge controlled mode is selected.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DOUBLE_EDGE_CONTROLL</name>
+ <description>Double edge controlled mode is selected.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PWMSEL5</name>
+ <description>PWM[5] output edge control.</description>
+ <bitRange>[5:5]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>SINGLE_EDGE_CONTROLL</name>
+ <description>Single edge controlled mode is selected.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DOUBLE_EDGE_CONTROLL</name>
+ <description>Double edge controlled mode is selected.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PWMSEL6</name>
+ <description>PWM[6] output edge control.</description>
+ <bitRange>[6:6]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>SINGLE_EDGE_CONTROLL</name>
+ <description>Single edge controlled mode is selected.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DOUBLE_EDGE_CONTROLL</name>
+ <description>Double edge controlled mode is selected.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[8:7]</bitRange>
+
+ </field>
+ <field>
+ <name>PWMENA1</name>
+ <description>PWM[1] output enable control.</description>
+ <bitRange>[9:9]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>THE_PWM_OUTPUT_IS_DI</name>
+ <description>The PWM output is disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>THE_PWM_OUTPUT_IS_EN</name>
+ <description>The PWM output is enabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PWMENA2</name>
+ <description>PWM[2] output enable control.</description>
+ <bitRange>[10:10]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>THE_PWM_OUTPUT_IS_DI</name>
+ <description>The PWM output is disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>THE_PWM_OUTPUT_IS_EN</name>
+ <description>The PWM output is enabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PWMENA3</name>
+ <description>PWM[3] output enable control.</description>
+ <bitRange>[11:11]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>THE_PWM_OUTPUT_IS_DI</name>
+ <description>The PWM output is disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>THE_PWM_OUTPUT_IS_EN</name>
+ <description>The PWM output is enabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PWMENA4</name>
+ <description>PWM[4] output enable control.</description>
+ <bitRange>[12:12]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>THE_PWM_OUTPUT_IS_DI</name>
+ <description>The PWM output is disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>THE_PWM_OUTPUT_IS_EN</name>
+ <description>The PWM output is enabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PWMENA5</name>
+ <description>PWM[5] output enable control.</description>
+ <bitRange>[13:13]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>THE_PWM_OUTPUT_IS_DI</name>
+ <description>The PWM output is disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>THE_PWM_OUTPUT_IS_EN</name>
+ <description>The PWM output is enabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PWMENA6</name>
+ <description>PWM[6] output enable control. See PWMENA1 for details.</description>
+ <bitRange>[14:14]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>THE_PWM_OUTPUT_IS_DI</name>
+ <description>The PWM output is disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>THE_PWM_OUTPUT_IS_EN</name>
+ <description>The PWM output is enabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused, always zero.</description>
+ <bitRange>[31:15]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+
+
+
+ <register>
+ <name>LER</name>
+ <description>Load Enable Register. Enables use of updated PWM match values.</description>
+ <addressOffset>0x050</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>MAT0LATCHEN</name>
+ <description>Enable PWM Match 0 Latch. PWM MR0 register update control. Writing a one to this bit allows the last value written to the PWM Match Register 0 to be become effective when the timer is next reset by a PWM Match event. See Section 27.6.7.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>MAT1LATCHEN</name>
+ <description>Enable PWM Match 1 Latch. PWM MR1 register update control. See bit 0 for details.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>MAT2LATCHEN</name>
+ <description>Enable PWM Match 2 Latch. PWM MR2 register update control. See bit 0 for details.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>MAT3LATCHEN</name>
+ <description>Enable PWM Match 3 Latch. PWM MR3 register update control. See bit 0 for details.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>MAT4LATCHEN</name>
+ <description>Enable PWM Match 4 Latch. PWM MR4 register update control. See bit 0 for details.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>MAT5LATCHEN</name>
+ <description>Enable PWM Match 5 Latch. PWM MR5 register update control. See bit 0 for details.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>MAT6LATCHEN</name>
+ <description>Enable PWM Match 6 Latch. PWM MR6 register update control. See bit 0 for details.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:7]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CTCR</name>
+ <description>Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.</description>
+ <addressOffset>0x070</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>MOD</name>
+ <description>Counter/ Timer Mode</description>
+ <bitRange>[1:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>TIMER_MODE_THE_TC_I</name>
+ <description>Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale register.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RISING_EDGE_COUNTER_</name>
+ <description>Rising edge counter Mode: the TC is incremented on rising edges of the PWM_CAP input selected by bits 3:2.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>FALLING_EDGE_COUNTER</name>
+ <description>Falling edge counter Mode: the TC is incremented on falling edges of the PWM_CAP input selected by bits 3:2.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DUAL_EDGE_COUNTER_MO</name>
+ <description>Dual edge counter Mode: the TC is incremented on both edges of the PWM_CAP input selected by bits 3:2.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CIS</name>
+ <description>Count Input Select. When bits 1:0 are not 00, these bits select which PWM_CAP pin carries the signal used to increment the TC. Other combinations are reserved.</description>
+ <bitRange>[3:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>FOR_PWM0_00_EQ_PWM0_</name>
+ <description>For PWM0: 00 = PWM0_CAP0 (Other combinations are reserved) For PWM1: 00 = PWM1_CAP0, 01 = PWM1_CAP1 (Other combinations are reserved)</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:4]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ </registers>
+</peripheral>
+
+
+ <peripheral>
+ <name>I2C0</name>
+ <description>I2C bus interface</description>
+ <groupName>I2C</groupName>
+ <baseAddress>0x4001C000</baseAddress>
+ <addressBlock>
+ <offset>0</offset>
+ <size>0xFFF</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>I2C0</name>
+ <value>10</value>
+
+ </interrupt>
+ <registers>
+ <register>
+ <name>CONSET</name>
+ <description>I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register.</description>
+ <addressOffset>0x000</addressOffset>
+ <access>read-write</access>
+ <resetValue>0x00</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[1:0]</bitRange>
+ </field>
+ <field>
+ <name>AA</name>
+ <description>Assert acknowledge flag.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>SI</name>
+ <description>I2C interrupt flag.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>STO</name>
+ <description>STOP flag.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>STA</name>
+ <description>START flag.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>I2EN</name>
+ <description>I2C interface enable.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:7]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>STAT</name>
+ <description>I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed.</description>
+ <addressOffset>0x004</addressOffset>
+ <access>read-only</access>
+ <resetValue>0xF8</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>These bits are unused and are always 0.</description>
+ <bitRange>[2:0]</bitRange>
+ </field>
+ <field>
+ <name>Status</name>
+ <description>These bits give the actual status information about the I 2C interface.</description>
+ <bitRange>[7:3]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DAT</name>
+ <description>I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register.</description>
+ <addressOffset>0x008</addressOffset>
+ <access>read-write</access>
+ <resetValue>0x00</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>Data</name>
+ <description>This register holds data values that have been received or are to be transmitted.</description>
+ <bitRange>[7:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ADR0</name>
+ <description>I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.</description>
+ <addressOffset>0x00C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0x00</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>GC</name>
+ <description>General Call enable bit.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>Address</name>
+ <description>The I2C device address for slave mode.</description>
+ <bitRange>[7:1]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SCLH</name>
+ <description>SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock.</description>
+ <addressOffset>0x010</addressOffset>
+ <access>read-write</access>
+ <resetValue>0x04</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>SCLH</name>
+ <description>Count for SCL HIGH time period selection.</description>
+ <bitRange>[15:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:16]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SCLL</name>
+ <description>SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode.</description>
+ <addressOffset>0x014</addressOffset>
+ <access>read-write</access>
+ <resetValue>0x04</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>SCLL</name>
+ <description>Count for SCL low time period selection.</description>
+ <bitRange>[15:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:16]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CONCLR</name>
+ <description>I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register.</description>
+ <addressOffset>0x018</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[1:0]</bitRange>
+ </field>
+ <field>
+ <name>AAC</name>
+ <description>Assert acknowledge Clear bit.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>SIC</name>
+ <description>I2C interrupt Clear bit.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>STAC</name>
+ <description>START flag Clear bit.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>I2ENC</name>
+ <description>I2C interface Disable bit.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>MMCTRL</name>
+ <description>Monitor mode control register.</description>
+ <addressOffset>0x01C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0x00</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>MM_ENA</name>
+ <description>Monitor mode enable.</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>MONITOR_MODE_DISABLE</name>
+ <description>Monitor mode disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>THE_I_2C_MODULE_WILL</name>
+ <description>The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>ENA_SCL</name>
+ <description>SCL output enable.</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>WHEN_THIS_BIT_IS_CLE</name>
+ <description>When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>WHEN_THIS_BIT_IS_SET</name>
+ <description>When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>MATCH_ALL</name>
+ <description>Select interrupt register match.</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>WHEN_THIS_BIT_IS_CLE</name>
+ <description>When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>WHEN_THIS_BIT_IS_SET</name>
+ <description>When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. The value read from reserved bits is not defined.</description>
+ <bitRange>[31:3]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <dim>3</dim>
+ <dimIncrement>0x4</dimIncrement>
+ <dimIndex>1-3</dimIndex>
+ <name>ADR%s</name>
+ <description>I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.</description>
+ <addressOffset>0x020</addressOffset>
+ <access>read-write</access>
+ <resetValue>0x00</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>GC</name>
+ <description>General Call enable bit.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>Address</name>
+ <description>The I2C device address for slave mode.</description>
+ <bitRange>[7:1]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DATA_BUFFER</name>
+ <description>Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus.</description>
+ <addressOffset>0x02C</addressOffset>
+ <access>read-only</access>
+ <resetValue>0x00</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>Data</name>
+ <description>This register holds contents of the 8 MSBs of the DAT shift register.</description>
+ <bitRange>[7:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <dim>4</dim>
+ <dimIncrement>0x4</dimIncrement>
+ <dimIndex>0-3</dimIndex>
+ <name>MASK[%s]</name>
+ <displayName>MASK[%s]</displayName>
+ <description>I2C Slave address mask register</description>
+ <addressOffset>0x030</addressOffset>
+ <access>read-write</access>
+ <resetValue>0x00</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. User software should not write ones to reserved bits. This bit reads always back as 0.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>MASK</name>
+ <description>Mask bits.</description>
+ <bitRange>[7:1]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>SPI</name>
+ <description>SPI </description>
+ <groupName>SPI</groupName>
+ <baseAddress>0x40020000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0xFFF</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>SPI</name>
+ <value>13</value>
+ </interrupt>
+
+ <registers>
+ <register>
+ <name>CR</name>
+ <description>SPI Control Register. This register controls the operation of the SPI.</description>
+ <addressOffset>0x000</addressOffset>
+ <access>read-write</access>
+ <resetValue>0x00</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[1:0]</bitRange>
+
+ </field>
+ <field>
+ <name>BITENABLE</name>
+ <description>The SPI controller sends and receives 8 bits of data per transfer.</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>THE_SPI_CONTROLLER_S</name>
+ <description>The SPI controller sends and receives the number of bits selected by bits 11:8.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CPHA</name>
+ <description>Clock phase control determines the relationship between the data and the clock on SPI transfers, and controls when a slave transfer is defined as starting and ending.</description>
+ <bitRange>[3:3]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>FIRST_EDGE</name>
+ <description>Data is sampled on the first clock edge of SCK. A transfer starts and ends with activation and deactivation of the SSEL signal.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SECOND_EDGE</name>
+ <description>Data is sampled on the second clock edge of the SCK. A transfer starts with the first clock edge, and ends with the last sampling edge when the SSEL signal is active.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CPOL</name>
+ <description>Clock polarity control.</description>
+ <bitRange>[4:4]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>SCK_IS_ACTIVE_HIGH_</name>
+ <description>SCK is active high.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SCK_IS_ACTIVE_LOW_</name>
+ <description>SCK is active low.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>MSTR</name>
+ <description>Master mode select.</description>
+ <bitRange>[5:5]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>SLAVE</name>
+ <description>The SPI operates in Slave mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MASTER</name>
+ <description>The SPI operates in Master mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>LSBF</name>
+ <description>LSB First controls which direction each byte is shifted when transferred.</description>
+ <bitRange>[6:6]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>MSB</name>
+ <description>SPI data is transferred MSB (bit 7) first.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>LSB</name>
+ <description>SPI data is transferred LSB (bit 0) first.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>SPIE</name>
+ <description>Serial peripheral interrupt enable.</description>
+ <bitRange>[7:7]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>INTBLOCK</name>
+ <description>SPI interrupts are inhibited.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>HWINT</name>
+ <description>A hardware interrupt is generated each time the SPIF or MODF bits are activated.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>BITS</name>
+ <description>When bit 2 of this register is 1, this field controls the number of bits per transfer:</description>
+ <bitRange>[11:8]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>8_BITS_PER_TRANSFER</name>
+ <description>8 bits per transfer</description>
+ <value>0x8</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>9_BITS_PER_TRANSFER</name>
+ <description>9 bits per transfer</description>
+ <value>0x9</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>10_BITS_PER_TRANSFER</name>
+ <description>10 bits per transfer</description>
+ <value>0xA</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>11_BITS_PER_TRANSFER</name>
+ <description>11 bits per transfer</description>
+ <value>0xB</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>12_BITS_PER_TRANSFER</name>
+ <description>12 bits per transfer</description>
+ <value>0xC</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>13_BITS_PER_TRANSFER</name>
+ <description>13 bits per transfer</description>
+ <value>0xD</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>14_BITS_PER_TRANSFER</name>
+ <description>14 bits per transfer</description>
+ <value>0xE</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>15_BITS_PER_TRANSFER</name>
+ <description>15 bits per transfer</description>
+ <value>0xF</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>16_BITS_PER_TRANSFER</name>
+ <description>16 bits per transfer</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:12]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SR</name>
+ <description>SPI Status Register. This register shows the status of the SPI.</description>
+ <addressOffset>0x004</addressOffset>
+ <access>read-only</access>
+ <resetValue>0x00</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[2:0]</bitRange>
+ </field>
+ <field>
+ <name>ABRT</name>
+ <description>Slave abort. When 1, this bit indicates that a slave abort has occurred. This bit is cleared by reading this register.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>MODF</name>
+ <description>Mode fault. when 1, this bit indicates that a Mode fault error has occurred. This bit is cleared by reading this register, then writing the SPI0 control register.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>ROVR</name>
+ <description>Read overrun. When 1, this bit indicates that a read overrun has occurred. This bit is cleared by reading this register.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>WCOL</name>
+ <description>Write collision. When 1, this bit indicates that a write collision has occurred. This bit is cleared by reading this register, then accessing the SPI Data Register.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>SPIF</name>
+ <description>SPI transfer complete flag. When 1, this bit indicates when a SPI data transfer is complete. When a master, this bit is set at the end of the last cycle of the transfer. When a slave, this bit is set on the last data sampling edge of the SCK. This bit is cleared by first reading this register, then accessing the SPI Data Register. Note: this is not the SPI interrupt flag. This flag is found in the SPINT register.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DR</name>
+ <description>SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register.</description>
+ <addressOffset>0x008</addressOffset>
+ <access>read-write</access>
+ <resetValue>0x00</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <readAction>modify</readAction>
+ <fields>
+ <field>
+ <name>DATALOW</name>
+ <description>SPI Bi-directional data port.</description>
+ <bitRange>[7:0]</bitRange>
+ </field>
+ <field>
+ <name>DATAHIGH</name>
+ <description>If bit 2 of the SPCR is 1 and bits 11:8 are other than 1000, some or all of these bits contain the additional transmit and receive bits. When less than 16 bits are selected, the more significant among these bits read as zeroes.</description>
+ <bitRange>[15:8]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:16]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCR</name>
+ <description>SPI Clock Counter Register. This register controls the frequency of a master's SCK0.</description>
+ <addressOffset>0x00C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0x00</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>COUNTER</name>
+ <description>SPI0 Clock counter setting.</description>
+ <bitRange>[7:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+
+
+ <register>
+ <name>INT</name>
+ <description>SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface.</description>
+ <addressOffset>0x01C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0x00</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>SPIF</name>
+ <description>SPI interrupt flag. Set by the SPI interface to generate an interrupt. Cleared by writing a 1 to this bit. Note: this bit will be set once when SPIE = 1 and at least one of SPIF and WCOL bits is 1. However, only when the SPI Interrupt bit is set and SPI0 Interrupt is enabled in the NVIC, SPI based interrupt can be processed by interrupt handling software.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[7:1]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+ </registers>
+</peripheral>
+ <peripheral>
+ <name>RTC</name>
+ <description> Real Time Clock (RTC) </description>
+ <groupName>RTC</groupName>
+ <baseAddress>0x40024000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0xFFF</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>RTC</name>
+ <value>17</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>ILR</name>
+ <description>Interrupt Location Register</description>
+ <addressOffset>0x000</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RTCCIF</name>
+ <description>When one, the Counter Increment Interrupt block generated an interrupt. Writing a one to this bit location clears the counter increment interrupt.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>RTCALF</name>
+ <description>When one, the alarm registers generated an interrupt. Writing a one to this bit location clears the alarm interrupt.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:21]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCR</name>
+ <description>Clock Control Register</description>
+ <addressOffset>0x008</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>CLKEN</name>
+ <description>Clock Enable.</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>THE_TIME_COUNTERS_AR</name>
+ <description>The time counters are enabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>THE_TIME_COUNTERS_AR</name>
+ <description>The time counters are disabled so that they may be initialized.</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CTCRST</name>
+ <description>CTC Reset.</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>RESET</name>
+ <description>When one, the elements in the internal oscillator divider are reset, and remain reset until CCR[1] is changed to zero. This is the divider that generates the 1 Hz clock from the 32.768 kHz crystal. The state of the divider is not visible to software.</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>NO_EFFECT_</name>
+ <description>No effect.</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Internal test mode controls. These bits must be 0 for normal RTC operation.</description>
+ <bitRange>[3:2]</bitRange>
+
+ </field>
+ <field>
+ <name>CCALEN</name>
+ <description>Calibration counter enable.</description>
+ <bitRange>[4:4]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>THE_CALIBRATION_COUN</name>
+ <description>The calibration counter is disabled and reset to zero.</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>THE_CALIBRATION_COUN</name>
+ <description>The calibration counter is enabled and counting, using the 1 Hz clock. When the calibration counter is equal to the value of the CALIBRATION register, the counter resets and repeats counting up to the value of the CALIBRATION register. See Section 30.6.4.2 and Section 30.6.5.</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:5]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CIIR</name>
+ <description>Counter Increment Interrupt Register</description>
+ <addressOffset>0x00C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>IMSEC</name>
+ <description>When 1, an increment of the Second value generates an interrupt.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>IMMIN</name>
+ <description>When 1, an increment of the Minute value generates an interrupt.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>IMHOUR</name>
+ <description>When 1, an increment of the Hour value generates an interrupt.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>IMDOM</name>
+ <description>When 1, an increment of the Day of Month value generates an interrupt.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>IMDOW</name>
+ <description>When 1, an increment of the Day of Week value generates an interrupt.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>IMDOY</name>
+ <description>When 1, an increment of the Day of Year value generates an interrupt.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>IMMON</name>
+ <description>When 1, an increment of the Month value generates an interrupt.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>IMYEAR</name>
+ <description>When 1, an increment of the Year value generates an interrupt.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>AMR</name>
+ <description>Alarm Mask Register</description>
+ <addressOffset>0x010</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>AMRSEC</name>
+ <description>When 1, the Second value is not compared for the alarm.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>AMRMIN</name>
+ <description>When 1, the Minutes value is not compared for the alarm.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>AMRHOUR</name>
+ <description>When 1, the Hour value is not compared for the alarm.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>AMRDOM</name>
+ <description>When 1, the Day of Month value is not compared for the alarm.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>AMRDOW</name>
+ <description>When 1, the Day of Week value is not compared for the alarm.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>AMRDOY</name>
+ <description>When 1, the Day of Year value is not compared for the alarm.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>AMRMON</name>
+ <description>When 1, the Month value is not compared for the alarm.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>AMRYEAR</name>
+ <description>When 1, the Year value is not compared for the alarm.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+
+
+ <register>
+ <name>CTIME0</name>
+ <description>Consolidated Time Register 0</description>
+ <addressOffset>0x014</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>SECONDS</name>
+ <description>Seconds value in the range of 0 to 59</description>
+ <bitRange>[5:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. The value read from a reserved bit is not defined.</description>
+ <bitRange>[7:6]</bitRange>
+ </field>
+ <field>
+ <name>MINUTES</name>
+ <description>Minutes value in the range of 0 to 59</description>
+ <bitRange>[13:8]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. The value read from a reserved bit is not defined.</description>
+ <bitRange>[15:14]</bitRange>
+ </field>
+ <field>
+ <name>HOURS</name>
+ <description>Hours value in the range of 0 to 23</description>
+ <bitRange>[20:16]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. The value read from a reserved bit is not defined.</description>
+ <bitRange>[23:21]</bitRange>
+ </field>
+ <field>
+ <name>DOW</name>
+ <description>Day of week value in the range of 0 to 6</description>
+ <bitRange>[26:24]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:27]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CTIME1</name>
+ <description>Consolidated Time Register 1</description>
+ <addressOffset>0x018</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>DOM</name>
+ <description>Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year).</description>
+ <bitRange>[4:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. The value read from a reserved bit is not defined.</description>
+ <bitRange>[7:5]</bitRange>
+ </field>
+ <field>
+ <name>MONTH</name>
+ <description>Month value in the range of 1 to 12.</description>
+ <bitRange>[11:8]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. The value read from a reserved bit is not defined.</description>
+ <bitRange>[15:12]</bitRange>
+ </field>
+ <field>
+ <name>YEAR</name>
+ <description>Year value in the range of 0 to 4095.</description>
+ <bitRange>[27:16]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:28]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CTIME2</name>
+ <description>Consolidated Time Register 2</description>
+ <addressOffset>0x01C</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>DOY</name>
+ <description>Day of year value in the range of 1 to 365 (366 for leap years).</description>
+ <bitRange>[11:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:12]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SEC</name>
+ <description>Seconds Counter</description>
+ <addressOffset>0x020</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>SECONDS</name>
+ <description>Seconds value in the range of 0 to 59</description>
+ <bitRange>[5:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:6]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>MIN</name>
+ <description>Minutes Register</description>
+ <addressOffset>0x024</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>MINUTES</name>
+ <description>Minutes value in the range of 0 to 59</description>
+ <bitRange>[5:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:6]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HRS</name>
+ <description>Hours Register</description>
+ <addressOffset>0x028</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>HOURS</name>
+ <description>Hours value in the range of 0 to 23</description>
+ <bitRange>[4:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:5]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DOM</name>
+ <description>Day of Month Register</description>
+ <addressOffset>0x02C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>DOM</name>
+ <description>Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year).</description>
+ <bitRange>[4:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:5]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DOW</name>
+ <description>Day of Week Register</description>
+ <addressOffset>0x030</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>DOW</name>
+ <description>Day of week value in the range of 0 to 6.</description>
+ <bitRange>[2:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:3]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DOY</name>
+ <description>Day of Year Register</description>
+ <addressOffset>0x034</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>DOY</name>
+ <description>Day of year value in the range of 1 to 365 (366 for leap years).</description>
+ <bitRange>[8:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:9]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>MONTH</name>
+ <description>Months Register</description>
+ <addressOffset>0x038</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>MONTH</name>
+ <description>Month value in the range of 1 to 12.</description>
+ <bitRange>[3:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:4]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>YEAR</name>
+ <description>Years Register</description>
+ <addressOffset>0x03C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>YEAR</name>
+ <description>Year value in the range of 0 to 4095.</description>
+ <bitRange>[11:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:12]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CALIBRATION</name>
+ <description>Calibration Value Register</description>
+ <addressOffset>0x040</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>CALVAL</name>
+ <description>If enabled, the calibration counter counts up to this value. The maximum value is 131, 072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL = 0.</description>
+ <bitRange>[16:0]</bitRange>
+
+ </field>
+ <field>
+ <name>CALDIR</name>
+ <description>Calibration direction</description>
+ <bitRange>[17:17]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>BACKWARD_CALIBRATION</name>
+ <description>Backward calibration. When CALVAL is equal to the calibration counter, the RTC timers will stop incrementing for 1 second.</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>FORWARD_CALIBRATION_</name>
+ <description>Forward calibration. When CALVAL is equal to the calibration counter, the RTC timers will jump by 2 seconds.</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <dim>5</dim>
+ <dimIncrement>0x4</dimIncrement>
+ <dimIndex>0-4</dimIndex>
+ <name>GPREG%s</name>
+ <description>General Purpose Register 0</description>
+ <addressOffset>0x044</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>GP</name>
+ <description>General purpose storage.</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RTC_AUX</name>
+ <description>RTC Auxiliary control register</description>
+ <addressOffset>0x05C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0x10</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[3:0]</bitRange>
+ </field>
+ <field>
+ <name>RTC_OSCF</name>
+ <description>RTC Oscillator Fail detect flag. Read: this bit is set if the RTC oscillator stops, and when RTC power is first turned on. An interrupt will occur when this bit is set, the RTC_OSCFEN bit in RTC_AUXEN is a 1, and the RTC interrupt is enabled in the NVIC. Write: writing a 1 to this bit clears the flag.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>RTC_PDOUT</name>
+ <description>When 0: the RTC_ALARM pin reflects the RTC alarm status. When 1: the RTC_ALARM pin indicates Deep Power-down mode.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:7]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RTC_AUXEN</name>
+ <description>RTC Auxiliary Enable register</description>
+ <addressOffset>0x058</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[3:0]</bitRange>
+ </field>
+ <field>
+ <name>RTC_OSCFEN</name>
+ <description>Oscillator Fail Detect interrupt enable. When 0: the RTC Oscillator Fail detect interrupt is disabled. When 1: the RTC Oscillator Fail detect interrupt is enabled. See Section 30.6.2.5.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:5]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ASEC</name>
+ <description>Alarm value for Seconds</description>
+ <addressOffset>0x060</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>SECONDS</name>
+ <description>Seconds value in the range of 0 to 59</description>
+ <bitRange>[5:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:6]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>AMIN</name>
+ <description>Alarm value for Minutes</description>
+ <addressOffset>0x64</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>MINUTES</name>
+ <description>Minutes value in the range of 0 to 59</description>
+ <bitRange>[5:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:6]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>AHRS</name>
+ <description>Alarm value for Hours</description>
+ <addressOffset>0x068</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>HOURS</name>
+ <description>Hours value in the range of 0 to 23</description>
+ <bitRange>[4:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:5]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ADOM</name>
+ <description>Alarm value for Day of Month</description>
+ <addressOffset>0x06C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>DOM</name>
+ <description>Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year).</description>
+ <bitRange>[4:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:5]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ADOW</name>
+ <description>Alarm value for Day of Week</description>
+ <addressOffset>0x070</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>DOW</name>
+ <description>Day of week value in the range of 0 to 6.</description>
+ <bitRange>[2:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:3]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ADOY</name>
+ <description>Alarm value for Day of Year</description>
+ <addressOffset>0x074</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>DOY</name>
+ <description>Day of year value in the range of 1 to 365 (366 for leap years).</description>
+ <bitRange>[8:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:9]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>AMON</name>
+ <description>Alarm value for Months</description>
+ <addressOffset>0x078</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>MONTH</name>
+ <description>Month value in the range of 1 to 12.</description>
+ <bitRange>[3:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:4]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>AYRS</name>
+ <description>Alarm value for Year</description>
+ <addressOffset>0x07C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>YEAR</name>
+ <description>Year value in the range of 0 to 4095.</description>
+ <bitRange>[11:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:12]</bitRange>
+ </field>
+ </fields>
+ </register>
+
+
+
+
+
+
+ </registers>
+</peripheral>
+<peripheral>
+ <name>GPIOINT</name>
+ <description>GPIO</description>
+ <groupName>GPIOINT</groupName>
+ <!-- change this to base address 0x40028080 to be backwards compatible WHY???? -->
+ <baseAddress>0x40028080</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0xFFF</size>
+ <usage>registers</usage>
+ </addressBlock>
+
+ <registers>
+ <register>
+ <name>STATUS</name>
+ <description>GPIO overall Interrupt Status.</description>
+ <addressOffset>0x000</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>P0INT</name>
+ <description>Port 0 GPIO interrupt pending.</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>NO_PENDING_INTERRUPT</name>
+ <description>No pending interrupts on Port 0.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>AT_LEAST_ONE_PENDING</name>
+ <description>At least one pending interrupt on Port 0.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. The value read from a reserved bit is not defined.</description>
+ <bitRange>[1:1]</bitRange>
+
+ </field>
+ <field>
+ <name>P2INT</name>
+ <description>Port 2 GPIO interrupt pending.</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>NO_PENDING_INTERRUPT</name>
+ <description>No pending interrupts on Port 2.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>AT_LEAST_ONE_PENDING</name>
+ <description>At least one pending interrupt on Port 2.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:2]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>STATR0</name>
+ <description>GPIO Interrupt Status for Rising edge for Port 0.</description>
+ <addressOffset>0x004</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>P0_0REI</name>
+ <description>Status of Rising Edge Interrupt for P0[0]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>P0_1REI</name>
+ <description>Status of Rising Edge Interrupt for P0[1]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>P0_2REI</name>
+ <description>Status of Rising Edge Interrupt for P0[2]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>P0_3REI</name>
+ <description>Status of Rising Edge Interrupt for P0[3]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>P0_4REI</name>
+ <description>Status of Rising Edge Interrupt for P0[4]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>P0_5REI</name>
+ <description>Status of Rising Edge Interrupt for P0[5]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>P0_6REI</name>
+ <description>Status of Rising Edge Interrupt for P0[6]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>P0_7REI</name>
+ <description>Status of Rising Edge Interrupt for P0[7]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>P0_8REI</name>
+ <description>Status of Rising Edge Interrupt for P0[8]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>P0_9REI</name>
+ <description>Status of Rising Edge Interrupt for P0[9]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>P0_10REI</name>
+ <description>Status of Rising Edge Interrupt for P0[10]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>P0_11REI</name>
+ <description>Status of Rising Edge Interrupt for P0[11]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>P0_12REI</name>
+ <description>Status of Rising Edge Interrupt for P0[12]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>P0_13REI</name>
+ <description>Status of Rising Edge Interrupt for P0[13]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>P0_14REI</name>
+ <description>Status of Rising Edge Interrupt for P0[14]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>P0_15REI</name>
+ <description>Status of Rising Edge Interrupt for P0[15]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>P0_16REI</name>
+ <description>Status of Rising Edge Interrupt for P0[16]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[16:16]</bitRange>
+ </field>
+ <field>
+ <name>P0_17REI</name>
+ <description>Status of Rising Edge Interrupt for P0[17]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[17:17]</bitRange>
+ </field>
+ <field>
+ <name>P0_18REI</name>
+ <description>Status of Rising Edge Interrupt for P0[18]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[18:18]</bitRange>
+ </field>
+ <field>
+ <name>P0_19REI</name>
+ <description>Status of Rising Edge Interrupt for P0[19]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[19:19]</bitRange>
+ </field>
+ <field>
+ <name>P0_20REI</name>
+ <description>Status of Rising Edge Interrupt for P0[20]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[20:20]</bitRange>
+ </field>
+ <field>
+ <name>P0_21REI</name>
+ <description>Status of Rising Edge Interrupt for P0[21]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[21:21]</bitRange>
+ </field>
+ <field>
+ <name>P0_22REI</name>
+ <description>Status of Rising Edge Interrupt for P0[22]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[22:22]</bitRange>
+ </field>
+ <field>
+ <name>P0_23REI</name>
+ <description>Status of Rising Edge Interrupt for P0[23]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[23:23]</bitRange>
+ </field>
+ <field>
+ <name>P0_24REI</name>
+ <description>Status of Rising Edge Interrupt for P0[24]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[24:24]</bitRange>
+ </field>
+ <field>
+ <name>P0_25REI</name>
+ <description>Status of Rising Edge Interrupt for P0[25]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[25:25]</bitRange>
+ </field>
+ <field>
+ <name>P0_26REI</name>
+ <description>Status of Rising Edge Interrupt for P0[26]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[26:26]</bitRange>
+ </field>
+ <field>
+ <name>P0_27REI</name>
+ <description>Status of Rising Edge Interrupt for P0[27]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[27:27]</bitRange>
+ </field>
+ <field>
+ <name>P0_28REI</name>
+ <description>Status of Rising Edge Interrupt for P0[28]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[28:28]</bitRange>
+ </field>
+ <field>
+ <name>P0_29REI</name>
+ <description>Status of Rising Edge Interrupt for P0[29]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[29:29]</bitRange>
+ </field>
+ <field>
+ <name>P0_30REI</name>
+ <description>Status of Rising Edge Interrupt for P0[30]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[30:30]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[31:31]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>STATF0</name>
+ <description>GPIO Interrupt Status for Falling edge for Port 0.</description>
+ <addressOffset>0x008</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>P0_0FEI</name>
+ <description>Status of Falling Edge Interrupt for P0[0]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>P0_1FEI</name>
+ <description>Status of Falling Edge Interrupt for P0[1]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>P0_2FEI</name>
+ <description>Status of Falling Edge Interrupt for P0[2]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>P0_3FEI</name>
+ <description>Status of Falling Edge Interrupt for P0[3]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>P0_4FEI</name>
+ <description>Status of Falling Edge Interrupt for P0[4]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>P0_5FEI</name>
+ <description>Status of Falling Edge Interrupt for P0[5]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>P0_6FEI</name>
+ <description>Status of Falling Edge Interrupt for P0[6]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>P0_7FEI</name>
+ <description>Status of Falling Edge Interrupt for P0[7]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>P0_8FEI</name>
+ <description>Status of Falling Edge Interrupt for P0[8]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>P0_9FEI</name>
+ <description>Status of Falling Edge Interrupt for P0[9]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>P0_10FEI</name>
+ <description>Status of Falling Edge Interrupt for P0[10]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>P0_11FEI</name>
+ <description>Status of Falling Edge Interrupt for P0[11]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>P0_12FEI</name>
+ <description>Status of Falling Edge Interrupt for P0[12]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>P0_13FEI</name>
+ <description>Status of Falling Edge Interrupt for P0[13]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>P0_14FEI</name>
+ <description>Status of Falling Edge Interrupt for P0[14]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>P0_15FEI</name>
+ <description>Status of Falling Edge Interrupt for P0[15]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>P0_16FEI</name>
+ <description>Status of Falling Edge Interrupt for P0[16]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[16:16]</bitRange>
+ </field>
+ <field>
+ <name>P0_17FEI</name>
+ <description>Status of Falling Edge Interrupt for P0[17]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[17:17]</bitRange>
+ </field>
+ <field>
+ <name>P0_18FEI</name>
+ <description>Status of Falling Edge Interrupt for P0[18]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[18:18]</bitRange>
+ </field>
+ <field>
+ <name>P0_19FEI</name>
+ <description>Status of Falling Edge Interrupt for P0[19]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[19:19]</bitRange>
+ </field>
+ <field>
+ <name>P0_20FEI</name>
+ <description>Status of Falling Edge Interrupt for P0[20]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[20:20]</bitRange>
+ </field>
+ <field>
+ <name>P0_21FEI</name>
+ <description>Status of Falling Edge Interrupt for P0[21]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[21:21]</bitRange>
+ </field>
+ <field>
+ <name>P0_22FEI</name>
+ <description>Status of Falling Edge Interrupt for P0[22]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[22:22]</bitRange>
+ </field>
+ <field>
+ <name>P0_23FEI</name>
+ <description>Status of Falling Edge Interrupt for P0[23]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[23:23]</bitRange>
+ </field>
+ <field>
+ <name>P0_24FEI</name>
+ <description>Status of Falling Edge Interrupt for P0[24]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[24:24]</bitRange>
+ </field>
+ <field>
+ <name>P0_25FEI</name>
+ <description>Status of Falling Edge Interrupt for P0[25]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[25:25]</bitRange>
+ </field>
+ <field>
+ <name>P0_26FEI</name>
+ <description>Status of Falling Edge Interrupt for P0[26]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[26:26]</bitRange>
+ </field>
+ <field>
+ <name>P0_27FEI</name>
+ <description>Status of Falling Edge Interrupt for P0[27]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[27:27]</bitRange>
+ </field>
+ <field>
+ <name>P0_28FEI</name>
+ <description>Status of Falling Edge Interrupt for P0[28]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[28:28]</bitRange>
+ </field>
+ <field>
+ <name>P0_29FEI</name>
+ <description>Status of Falling Edge Interrupt for P0[29]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[29:29]</bitRange>
+ </field>
+ <field>
+ <name>P0_30FEI</name>
+ <description>Status of Falling Edge Interrupt for P0[30]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[30:30]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[31:31]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CLR0</name>
+ <description>GPIO Interrupt Clear.</description>
+ <addressOffset>0x00C</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>P0_0CI</name>
+ <description>Clear GPIO port Interrupts for P0[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>P0_1CI</name>
+ <description>Clear GPIO port Interrupts for P0[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>P0_2CI</name>
+ <description>Clear GPIO port Interrupts for P0[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>P0_3CI</name>
+ <description>Clear GPIO port Interrupts for P0[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>P0_4CI</name>
+ <description>Clear GPIO port Interrupts for P0[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>P0_5CI</name>
+ <description>Clear GPIO port Interrupts for P0[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>P0_6CI</name>
+ <description>Clear GPIO port Interrupts for P0[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>P0_7CI</name>
+ <description>Clear GPIO port Interrupts for P0[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>P0_8CI</name>
+ <description>Clear GPIO port Interrupts for P0[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>P0_9CI</name>
+ <description>Clear GPIO port Interrupts for P0[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>P0_10CI</name>
+ <description>Clear GPIO port Interrupts for P0[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>P0_11CI</name>
+ <description>Clear GPIO port Interrupts for P0[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>P0_12CI</name>
+ <description>Clear GPIO port Interrupts for P0[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>P0_13CI</name>
+ <description>Clear GPIO port Interrupts for P0[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>P0_14CI</name>
+ <description>Clear GPIO port Interrupts for P0[14]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>P0_15CI</name>
+ <description>Clear GPIO port Interrupts for P0[15]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>P0_16CI</name>
+ <description>Clear GPIO port Interrupts for P0[16]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[16:16]</bitRange>
+ </field>
+ <field>
+ <name>P0_17CI</name>
+ <description>Clear GPIO port Interrupts for P0[17]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[17:17]</bitRange>
+ </field>
+ <field>
+ <name>P0_18CI</name>
+ <description>Clear GPIO port Interrupts for P0[18]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[18:18]</bitRange>
+ </field>
+ <field>
+ <name>P0_19CI</name>
+ <description>Clear GPIO port Interrupts for P0[19]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[19:19]</bitRange>
+ </field>
+ <field>
+ <name>P0_20CI</name>
+ <description>Clear GPIO port Interrupts for P0[20]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[20:20]</bitRange>
+ </field>
+ <field>
+ <name>P0_21CI</name>
+ <description>Clear GPIO port Interrupts for P0[21]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[21:21]</bitRange>
+ </field>
+ <field>
+ <name>P0_22CI</name>
+ <description>Clear GPIO port Interrupts for P0[22]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[22:22]</bitRange>
+ </field>
+ <field>
+ <name>P0_23CI</name>
+ <description>Clear GPIO port Interrupts for P0[23]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[23:23]</bitRange>
+ </field>
+ <field>
+ <name>P0_24CI</name>
+ <description>Clear GPIO port Interrupts for P0[24]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[24:24]</bitRange>
+ </field>
+ <field>
+ <name>P0_25CI</name>
+ <description>Clear GPIO port Interrupts for P0[25]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[25:25]</bitRange>
+ </field>
+ <field>
+ <name>P0_26CI</name>
+ <description>Clear GPIO port Interrupts for P0[26]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[26:26]</bitRange>
+ </field>
+ <field>
+ <name>P0_27CI</name>
+ <description>Clear GPIO port Interrupts for P0[27]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[27:27]</bitRange>
+ </field>
+ <field>
+ <name>P0_28CI</name>
+ <description>Clear GPIO port Interrupts for P0[28]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[28:28]</bitRange>
+ </field>
+ <field>
+ <name>P0_29CI</name>
+ <description>Clear GPIO port Interrupts for P0[29]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[29:29]</bitRange>
+ </field>
+ <field>
+ <name>P0_30CI</name>
+ <description>Clear GPIO port Interrupts for P0[30]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[30:30]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[31:31]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ENR0</name>
+ <description>GPIO Interrupt Enable for Rising edge for Port 0.</description>
+ <addressOffset>0x010</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>P0_0ER</name>
+ <description>Enable rising edge interrupt for P0[0]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>P0_1ER</name>
+ <description>Enable rising edge interrupt for P0[1]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>P0_2ER</name>
+ <description>Enable rising edge interrupt for P0[2]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>P0_3ER</name>
+ <description>Enable rising edge interrupt for P0[3]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>P0_4ER</name>
+ <description>Enable rising edge interrupt for P0[4]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>P0_5ER</name>
+ <description>Enable rising edge interrupt for P0[5]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>P0_6ER</name>
+ <description>Enable rising edge interrupt for P0[6]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>P0_7ER</name>
+ <description>Enable rising edge interrupt for P0[7]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>P0_8ER</name>
+ <description>Enable rising edge interrupt for P0[8]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>P0_9ER</name>
+ <description>Enable rising edge interrupt for P0[9]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>P0_10ER</name>
+ <description>Enable rising edge interrupt for P0[10]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>P0_11ER</name>
+ <description>Enable rising edge interrupt for P0[11]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>P0_12ER</name>
+ <description>Enable rising edge interrupt for P0[12]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>P0_13ER</name>
+ <description>Enable rising edge interrupt for P0[13]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>P0_14ER</name>
+ <description>Enable rising edge interrupt for P0[14]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>P0_15ER</name>
+ <description>Enable rising edge interrupt for P0[15]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>P0_16ER</name>
+ <description>Enable rising edge interrupt for P0[16]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[16:16]</bitRange>
+ </field>
+ <field>
+ <name>P0_17ER</name>
+ <description>Enable rising edge interrupt for P0[17]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[17:17]</bitRange>
+ </field>
+ <field>
+ <name>P0_18ER</name>
+ <description>Enable rising edge interrupt for P0[18]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[18:18]</bitRange>
+ </field>
+ <field>
+ <name>P0_19ER</name>
+ <description>Enable rising edge interrupt for P0[19]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[19:19]</bitRange>
+ </field>
+ <field>
+ <name>P0_20ER</name>
+ <description>Enable rising edge interrupt for P0[20]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[20:20]</bitRange>
+ </field>
+ <field>
+ <name>P0_21ER</name>
+ <description>Enable rising edge interrupt for P0[21]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[21:21]</bitRange>
+ </field>
+ <field>
+ <name>P0_22ER</name>
+ <description>Enable rising edge interrupt for P0[22]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[22:22]</bitRange>
+ </field>
+ <field>
+ <name>P0_23ER</name>
+ <description>Enable rising edge interrupt for P0[23]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[23:23]</bitRange>
+ </field>
+ <field>
+ <name>P0_24ER</name>
+ <description>Enable rising edge interrupt for P0[24]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[24:24]</bitRange>
+ </field>
+ <field>
+ <name>P0_25ER</name>
+ <description>Enable rising edge interrupt for P0[25]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[25:25]</bitRange>
+ </field>
+ <field>
+ <name>P0_26ER</name>
+ <description>Enable rising edge interrupt for P0[26]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[26:26]</bitRange>
+ </field>
+ <field>
+ <name>P0_27ER</name>
+ <description>Enable rising edge interrupt for P0[27]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[27:27]</bitRange>
+ </field>
+ <field>
+ <name>P0_28ER</name>
+ <description>Enable rising edge interrupt for P0[28]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[28:28]</bitRange>
+ </field>
+ <field>
+ <name>P0_29ER</name>
+ <description>Enable rising edge interrupt for P0[29]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[29:29]</bitRange>
+ </field>
+ <field>
+ <name>P0_30ER</name>
+ <description>Enable rising edge interrupt for P0[30]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[30:30]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[31:31]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ENF0</name>
+ <description>GPIO Interrupt Enable for Falling edge for Port 0.</description>
+ <addressOffset>0x014</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>P0_0EF</name>
+ <description>Enable falling edge interrupt for P0[0]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>P0_1EF</name>
+ <description>Enable falling edge interrupt for P0[1]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>P0_2EF</name>
+ <description>Enable falling edge interrupt for P0[2]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>P0_3EF</name>
+ <description>Enable falling edge interrupt for P0[3]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>P0_4EF</name>
+ <description>Enable falling edge interrupt for P0[4]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>P0_5EF</name>
+ <description>Enable falling edge interrupt for P0[5]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>P0_6EF</name>
+ <description>Enable falling edge interrupt for P0[6]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>P0_7EF</name>
+ <description>Enable falling edge interrupt for P0[7]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>P0_8EF</name>
+ <description>Enable falling edge interrupt for P0[8]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>P0_9EF</name>
+ <description>Enable falling edge interrupt for P0[9]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>P0_10EF</name>
+ <description>Enable falling edge interrupt for P0[10]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>P0_11EF</name>
+ <description>Enable falling edge interrupt for P0[11]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>P0_12EF</name>
+ <description>Enable falling edge interrupt for P0[12]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>P0_13EF</name>
+ <description>Enable falling edge interrupt for P0[13]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>P0_14EF</name>
+ <description>Enable falling edge interrupt for P0[14]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>P0_15EF</name>
+ <description>Enable falling edge interrupt for P0[15]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>P0_16EF</name>
+ <description>Enable falling edge interrupt for P0[16]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[16:16]</bitRange>
+ </field>
+ <field>
+ <name>P0_17EF</name>
+ <description>Enable falling edge interrupt for P0[17]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[17:17]</bitRange>
+ </field>
+ <field>
+ <name>P0_18EF</name>
+ <description>Enable falling edge interrupt for P0[18]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[18:18]</bitRange>
+ </field>
+ <field>
+ <name>P0_19EF</name>
+ <description>Enable falling edge interrupt for P0[19]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[19:19]</bitRange>
+ </field>
+ <field>
+ <name>P0_20EF</name>
+ <description>Enable falling edge interrupt for P0[20]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[20:20]</bitRange>
+ </field>
+ <field>
+ <name>P0_21EF</name>
+ <description>Enable falling edge interrupt for P0[21]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[21:21]</bitRange>
+ </field>
+ <field>
+ <name>P0_22EF</name>
+ <description>Enable falling edge interrupt for P0[22]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[22:22]</bitRange>
+ </field>
+ <field>
+ <name>P0_23EF</name>
+ <description>Enable falling edge interrupt for P0[23]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[23:23]</bitRange>
+ </field>
+ <field>
+ <name>P0_24EF</name>
+ <description>Enable falling edge interrupt for P0[24]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[24:24]</bitRange>
+ </field>
+ <field>
+ <name>P0_25EF</name>
+ <description>Enable falling edge interrupt for P0[25]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[25:25]</bitRange>
+ </field>
+ <field>
+ <name>P0_26EF</name>
+ <description>Enable falling edge interrupt for P0[26]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[26:26]</bitRange>
+ </field>
+ <field>
+ <name>P0_27EF</name>
+ <description>Enable falling edge interrupt for P0[27]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[27:27]</bitRange>
+ </field>
+ <field>
+ <name>P0_28EF</name>
+ <description>Enable falling edge interrupt for P0[28]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[28:28]</bitRange>
+ </field>
+ <field>
+ <name>P0_29EF</name>
+ <description>Enable falling edge interrupt for P0[29]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[29:29]</bitRange>
+ </field>
+ <field>
+ <name>P0_30EF</name>
+ <description>Enable falling edge interrupt for P0[30]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[30:30]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[31:31]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>STATR2</name>
+ <description>GPIO Interrupt Status for Rising edge for Port 0.</description>
+ <addressOffset>0x024</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>P2_0REI</name>
+ <description>Status of Rising Edge Interrupt for P2[0]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>P2_1REI</name>
+ <description>Status of Rising Edge Interrupt for P2[1]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>P2_2REI</name>
+ <description>Status of Rising Edge Interrupt for P2[2]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>P2_3REI</name>
+ <description>Status of Rising Edge Interrupt for P2[3]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>P2_4REI</name>
+ <description>Status of Rising Edge Interrupt for P2[4]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>P2_5REI</name>
+ <description>Status of Rising Edge Interrupt for P2[5]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>P2_6REI</name>
+ <description>Status of Rising Edge Interrupt for P2[6]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>P2_7REI</name>
+ <description>Status of Rising Edge Interrupt for P2[7]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>P2_8REI</name>
+ <description>Status of Rising Edge Interrupt for P2[8]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>P2_9REI</name>
+ <description>Status of Rising Edge Interrupt for P2[9]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>P2_10REI</name>
+ <description>Status of Rising Edge Interrupt for P2[10]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>P2_11REI</name>
+ <description>Status of Rising Edge Interrupt for P2[11]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>P2_12REI</name>
+ <description>Status of Rising Edge Interrupt for P2[12]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>P2_13REI</name>
+ <description>Status of Rising Edge Interrupt for P2[13]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[31:14]</bitRange>
+ </field>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ </fields>
+ </register>
+ <register>
+ <name>STATF2</name>
+ <description>GPIO Interrupt Status for Falling edge for Port 0.</description>
+ <addressOffset>0x028</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>P2_0FEI</name>
+ <description>Status of Falling Edge Interrupt for P2[0]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>P2_1FEI</name>
+ <description>Status of Falling Edge Interrupt for P2[1]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>P2_2FEI</name>
+ <description>Status of Falling Edge Interrupt for P2[2]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>P2_3FEI</name>
+ <description>Status of Falling Edge Interrupt for P2[3]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>P2_4FEI</name>
+ <description>Status of Falling Edge Interrupt for P2[4]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>P2_5FEI</name>
+ <description>Status of Falling Edge Interrupt for P2[5]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>P2_6FEI</name>
+ <description>Status of Falling Edge Interrupt for P2[6]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>P2_7FEI</name>
+ <description>Status of Falling Edge Interrupt for P2[7]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>P2_8FEI</name>
+ <description>Status of Falling Edge Interrupt for P2[8]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>P2_9FEI</name>
+ <description>Status of Falling Edge Interrupt for P2[9]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>P2_10FEI</name>
+ <description>Status of Falling Edge Interrupt for P2[10]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>P2_11FEI</name>
+ <description>Status of Falling Edge Interrupt for P2[11]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>P2_12FEI</name>
+ <description>Status of Falling Edge Interrupt for P2[12]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>P2_13FEI</name>
+ <description>Status of Falling Edge Interrupt for P2[13]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[31:14]</bitRange>
+ </field>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ </fields>
+ </register>
+ <register>
+ <name>CLR2</name>
+ <description>GPIO Interrupt Clear.</description>
+ <addressOffset>0x02C</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>P2_0CI</name>
+ <description>Clear GPIO port Interrupts for P2[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>P2_1CI</name>
+ <description>Clear GPIO port Interrupts for P2[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>P2_2CI</name>
+ <description>Clear GPIO port Interrupts for P2[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>P2_3CI</name>
+ <description>Clear GPIO port Interrupts for P2[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>P2_4CI</name>
+ <description>Clear GPIO port Interrupts for P2[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>P2_5CI</name>
+ <description>Clear GPIO port Interrupts for P2[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>P2_6CI</name>
+ <description>Clear GPIO port Interrupts for P2[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>P2_7CI</name>
+ <description>Clear GPIO port Interrupts for P2[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>P2_8CI</name>
+ <description>Clear GPIO port Interrupts for P2[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>P2_9CI</name>
+ <description>Clear GPIO port Interrupts for P2[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>P2_10CI</name>
+ <description>Clear GPIO port Interrupts for P2[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>P2_11CI</name>
+ <description>Clear GPIO port Interrupts for P2[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>P2_12CI</name>
+ <description>Clear GPIO port Interrupts for P2[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>P2_13CI</name>
+ <description>Clear GPIO port Interrupts for P2[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[31:14]</bitRange>
+ </field>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ </fields>
+ </register>
+ <register>
+ <name>ENR2</name>
+ <description>GPIO Interrupt Enable for Rising edge for Port 0.</description>
+ <addressOffset>0x030</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>P2_0ER</name>
+ <description>Enable rising edge interrupt for P2[0]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>P2_1ER</name>
+ <description>Enable rising edge interrupt for P2[1]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>P2_2ER</name>
+ <description>Enable rising edge interrupt for P2[2]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>P2_3ER</name>
+ <description>Enable rising edge interrupt for P2[3]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>P2_4ER</name>
+ <description>Enable rising edge interrupt for P2[4]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>P2_5ER</name>
+ <description>Enable rising edge interrupt for P2[5]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>P2_6ER</name>
+ <description>Enable rising edge interrupt for P2[6]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>P2_7ER</name>
+ <description>Enable rising edge interrupt for P2[7]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>P2_8ER</name>
+ <description>Enable rising edge interrupt for P2[8]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>P2_9ER</name>
+ <description>Enable rising edge interrupt for P2[9]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>P2_10ER</name>
+ <description>Enable rising edge interrupt for P2[10]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>P2_11ER</name>
+ <description>Enable rising edge interrupt for P2[11]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>P2_12ER</name>
+ <description>Enable rising edge interrupt for P2[12]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>P2_13ER</name>
+ <description>Enable rising edge interrupt for P2[13]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[31:14]</bitRange>
+ </field>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ </fields>
+ </register>
+ <register>
+ <name>ENF2</name>
+ <description>GPIO Interrupt Enable for Falling edge for Port 0.</description>
+ <addressOffset>0x034</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>P2_0EF</name>
+ <description>Enable falling edge interrupt for P2[0]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>P2_1EF</name>
+ <description>Enable falling edge interrupt for P2[1]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>P2_2EF</name>
+ <description>Enable falling edge interrupt for P2[2]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>P2_3EF</name>
+ <description>Enable falling edge interrupt for P2[3]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>P2_4EF</name>
+ <description>Enable falling edge interrupt for P2[4]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>P2_5EF</name>
+ <description>Enable falling edge interrupt for P2[5]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>P2_6EF</name>
+ <description>Enable falling edge interrupt for P2[6]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>P2_7EF</name>
+ <description>Enable falling edge interrupt for P2[7]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>P2_8EF</name>
+ <description>Enable falling edge interrupt for P2[8]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>P2_9EF</name>
+ <description>Enable falling edge interrupt for P2[9]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>P2_10EF</name>
+ <description>Enable falling edge interrupt for P2[10]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>P2_11EF</name>
+ <description>Enable falling edge interrupt for P2[11]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>P2_12EF</name>
+ <description>Enable falling edge interrupt for P2[12]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>P2_13EF</name>
+ <description>Enable falling edge interrupt for P2[13]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[31:14]</bitRange>
+ </field>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+
+
+ <peripheral>
+ <name>PINCONNECT</name>
+ <description>Pin connect block</description>
+ <baseAddress>0x4002C000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0xFFF</size>
+ <usage>registers</usage>
+ </addressBlock>
+
+ <registers>
+ <register>
+ <name>PINSEL0</name>
+ <description>Pin function select register 0.</description>
+ <addressOffset>0x000</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>P0_0</name>
+ <description>Pin function select P0.0.</description>
+ <bitRange>[1:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P0</name>
+ <description>GPIO P0.0</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RD1</name>
+ <description>RD1</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>TXD3</name>
+ <description>TXD3</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SDA1</name>
+ <description>SDA1</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_1</name>
+ <description>Pin function select P0.1.</description>
+ <bitRange>[3:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P0</name>
+ <description>GPIO P0.1</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>TD1</name>
+ <description>TD1</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RXD3</name>
+ <description>RXD3</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SCL1</name>
+ <description>SCL1</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_2</name>
+ <description>Pin function select P0.2.</description>
+ <bitRange>[5:4]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P0</name>
+ <description>GPIO P0.2</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>TXD0</name>
+ <description>TXD0</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>AD0</name>
+ <description>AD0.7</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_3</name>
+ <description>Pin function select P0.3.</description>
+ <bitRange>[7:6]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P0</name>
+ <description>GPIO P0.3.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RXD0</name>
+ <description>RXD0</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>AD0</name>
+ <description>AD0.6</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_4</name>
+ <description>Pin function select P0.4.</description>
+ <bitRange>[9:8]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P0</name>
+ <description>GPIO P0.4.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>I2SRX_CLK</name>
+ <description>I2SRX_CLK</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RD2</name>
+ <description>RD2</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CAP2</name>
+ <description>CAP2.0</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_5</name>
+ <description>Pin function select P0.5.</description>
+ <bitRange>[11:10]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P0</name>
+ <description>GPIO P0.5.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>I2SRX_WS</name>
+ <description>I2SRX_WS</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>TD2</name>
+ <description>TD2</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CAP2</name>
+ <description>CAP2.1</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_6</name>
+ <description>Pin function select P0.6.</description>
+ <bitRange>[13:12]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P0</name>
+ <description>GPIO P0.6.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>I2SRX_SDA</name>
+ <description>I2SRX_SDA</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SSEL1</name>
+ <description>SSEL1</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MAT2</name>
+ <description>MAT2.0</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_7</name>
+ <description>Pin function select P0.7.</description>
+ <bitRange>[15:14]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P0</name>
+ <description>GPIO P0.7.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>I2STX_CLK</name>
+ <description>I2STX_CLK</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SCK1</name>
+ <description>SCK1</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MAT2</name>
+ <description>MAT2.1</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_8</name>
+ <description>Pin function select P0.8.</description>
+ <bitRange>[17:16]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P0</name>
+ <description>GPIO P0.8.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>I2STX_WS</name>
+ <description>I2STX_WS</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MISO1</name>
+ <description>MISO1</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MAT2</name>
+ <description>MAT2.2</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_9</name>
+ <description>Pin function select P0.9.</description>
+ <bitRange>[19:18]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P0</name>
+ <description>GPIO P0.9</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>I2STX_SDA</name>
+ <description>I2STX_SDA</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MOSI1</name>
+ <description>MOSI1</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MAT2</name>
+ <description>MAT2.3</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_10</name>
+ <description>Pin function select P0.10.</description>
+ <bitRange>[21:20]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P0</name>
+ <description>GPIO P0.10</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>TXD2</name>
+ <description>TXD2</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SDA2</name>
+ <description>SDA2</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MAT3</name>
+ <description>MAT3.0</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_11</name>
+ <description>Pin function select P0.11.</description>
+ <bitRange>[23:22]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P0</name>
+ <description>GPIO P0.11</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RXD2</name>
+ <description>RXD2</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SCL2</name>
+ <description>SCL2</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MAT3</name>
+ <description>MAT3.1</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[29:24]</bitRange>
+
+ </field>
+ <field>
+ <name>P0_15</name>
+ <description>Pin function select P0.15.</description>
+ <bitRange>[31:30]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P0</name>
+ <description>GPIO P0.15</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>TXD1</name>
+ <description>TXD1</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SCK0</name>
+ <description>SCK0</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SCK</name>
+ <description>SCK</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PINSEL1</name>
+ <description>Pin function select register 1.</description>
+ <addressOffset>0x004</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>P0_16</name>
+ <description>Pin function select P0.16.</description>
+ <bitRange>[1:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P0</name>
+ <description>GPIO P0.16</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RXD1</name>
+ <description>RXD1</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SSEL0</name>
+ <description>SSEL0</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SSEL</name>
+ <description>SSEL</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_17</name>
+ <description>Pin function select P0.17.</description>
+ <bitRange>[3:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P0</name>
+ <description>GPIO P0.17</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CTS1</name>
+ <description>CTS1</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MISO0</name>
+ <description>MISO0</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MISO</name>
+ <description>MISO</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_18</name>
+ <description>Pin function select P0.18.</description>
+ <bitRange>[5:4]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P0</name>
+ <description>GPIO P0.18</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DCD1</name>
+ <description>DCD1</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MOSI0</name>
+ <description>MOSI0</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MOSI</name>
+ <description>MOSI</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_19</name>
+ <description>Pin function select P019.</description>
+ <bitRange>[7:6]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P0</name>
+ <description>GPIO P0.19.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DSR1</name>
+ <description>DSR1</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SDA1</name>
+ <description>SDA1</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_20</name>
+ <description>Pin function select P0.20.</description>
+ <bitRange>[9:8]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P0</name>
+ <description>GPIO P0.20.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DTR1</name>
+ <description>DTR1</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SCL1</name>
+ <description>SCL1</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_21</name>
+ <description>Pin function select P0.21.</description>
+ <bitRange>[11:10]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_PORT_0</name>
+ <description>GPIO Port 0.21.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RI1</name>
+ <description>RI1</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RD1</name>
+ <description>RD1</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_22</name>
+ <description>Pin function select P022</description>
+ <bitRange>[13:12]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P0</name>
+ <description>GPIO P0.22.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RTS1</name>
+ <description>RTS1</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>TD1</name>
+ <description>TD1</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_23</name>
+ <description>Pin function select P023.</description>
+ <bitRange>[15:14]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P0</name>
+ <description>GPIO P0.23.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>AD0</name>
+ <description>AD0.0</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>I2SRX_CLK</name>
+ <description>I2SRX_CLK</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CAP3</name>
+ <description>CAP3.0</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_24</name>
+ <description>Pin function select P0.24.</description>
+ <bitRange>[17:16]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P0</name>
+ <description>GPIO P0.24.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>AD0</name>
+ <description>AD0.1</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>I2SRX_WS</name>
+ <description>I2SRX_WS</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CAP3</name>
+ <description>CAP3.1</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_25</name>
+ <description>Pin function select P0.25.</description>
+ <bitRange>[19:18]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P0</name>
+ <description>GPIO P0.25</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>AD0</name>
+ <description>AD0.2</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>I2SRX_SDA</name>
+ <description>I2SRX_SDA</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>TXD3</name>
+ <description>TXD3</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_26</name>
+ <description>Pin function select P0.26.</description>
+ <bitRange>[21:20]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P0</name>
+ <description>GPIO P0.26</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>AD0</name>
+ <description>AD0.3</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>AOUT</name>
+ <description>AOUT</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RXD3</name>
+ <description>RXD3</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_27</name>
+ <description>Pin function select P0.27.</description>
+ <bitRange>[23:22]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P0</name>
+ <description>GPIO P0.27</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SDA0</name>
+ <description>SDA0</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>USB_SDA</name>
+ <description>USB_SDA</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_28</name>
+ <description>Pin function select P0.28.</description>
+ <bitRange>[25:24]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P0</name>
+ <description>GPIO P0.28</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SCL0</name>
+ <description>SCL0</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>USB_SCL</name>
+ <description>USB_SCL</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_29</name>
+ <description>Pin function select P0.29</description>
+ <bitRange>[27:26]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P0</name>
+ <description>GPIO P0.29</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>USB_DP</name>
+ <description>USB_D+</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_30</name>
+ <description>Pin function select P0.30.</description>
+ <bitRange>[29:28]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P0</name>
+ <description>GPIO P0.30</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>USB_DM</name>
+ <description>USB_D-</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <bitRange>[31:30]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PINSEL2</name>
+ <description>Pin function select register 2.</description>
+ <addressOffset>0x008</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>P1_0</name>
+ <description>Pin function select P1.0.</description>
+ <bitRange>[1:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P1</name>
+ <description>GPIO P1.0</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENET_TXD0</name>
+ <description>ENET_TXD0</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_1</name>
+ <description>Pin function select P1.1.</description>
+ <bitRange>[3:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P1</name>
+ <description>GPIO P1.1</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENET_TXD1</name>
+ <description>ENET_TXD1</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[7:4]</bitRange>
+
+ </field>
+ <field>
+ <name>P1_4</name>
+ <description>Pin function select P1.4.</description>
+ <bitRange>[9:8]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P1</name>
+ <description>GPIO P1.4.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENET_TX_EN</name>
+ <description>ENET_TX_EN</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[15:10]</bitRange>
+
+ </field>
+ <field>
+ <name>P1_8</name>
+ <description>Pin function select P1.8.</description>
+ <bitRange>[17:16]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P1</name>
+ <description>GPIO P1.8.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENET_CRS</name>
+ <description>ENET_CRS</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_9</name>
+ <description>Pin function select P1.9.</description>
+ <bitRange>[19:18]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_PORT_1</name>
+ <description>GPIO Port 1.9</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENET_RXD0</name>
+ <description>ENET_RXD0</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_10</name>
+ <description>Pin function select P1.10.</description>
+ <bitRange>[21:20]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P1</name>
+ <description>GPIO P1.10</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENET_RXD1</name>
+ <description>ENET_RXD1</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[29:24]</bitRange>
+
+ </field>
+ <field>
+ <name>P1_14</name>
+ <description>Pin function select P1.14.</description>
+ <bitRange>[23:22]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P1</name>
+ <description>GPIO P1.14</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENET_RX_ER</name>
+ <description>ENET_RX_ER</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[29:24]</bitRange>
+
+ </field>
+ <field>
+ <name>P1_15</name>
+ <description>Pin function select P1.15.</description>
+ <bitRange>[31:30]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P1</name>
+ <description>GPIO P1.15</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENET_REF_CLK</name>
+ <description>ENET_REF_CLK</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PINSEL3</name>
+ <description>Pin function select register 3.</description>
+ <addressOffset>0x00C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>P1_16</name>
+ <description>Pin function select P1.16.</description>
+ <bitRange>[1:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P1</name>
+ <description>GPIO P1.16</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENET_MDC</name>
+ <description>ENET_MDC</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_17</name>
+ <description>Pin function select P1.17.</description>
+ <bitRange>[3:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P1</name>
+ <description>GPIO P1.17</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENET_MDIO</name>
+ <description>ENET_MDIO</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_18</name>
+ <description>Pin function select P1.18.</description>
+ <bitRange>[5:4]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P1</name>
+ <description>GPIO P1.18</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>USB_UP_LED</name>
+ <description>USB_UP_LED</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PWM1</name>
+ <description>PWM1.1</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CAP1</name>
+ <description>CAP1.0</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_19</name>
+ <description>Pin function select P1.19.</description>
+ <bitRange>[7:6]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P1</name>
+ <description>GPIO P1.19.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MCOA0</name>
+ <description>MCOA0</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>USB_PPWR</name>
+ <description>USB_PPWR</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CAP1</name>
+ <description>CAP1.1</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_20</name>
+ <description>Pin function select P1.20.</description>
+ <bitRange>[9:8]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P1</name>
+ <description>GPIO P1.20.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MCI0</name>
+ <description>MCI0</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PWM1</name>
+ <description>PWM1.2</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SCK0</name>
+ <description>SCK0</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_21</name>
+ <description>Pin function select P1.21.</description>
+ <bitRange>[11:10]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P1</name>
+ <description>GPIO P1.21.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MCABORT</name>
+ <description>MCABORT</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PWM1</name>
+ <description>PWM1.3</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SSEL0</name>
+ <description>SSEL0</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_22</name>
+ <description>Pin function select P1.22</description>
+ <bitRange>[13:12]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P1</name>
+ <description>GPIO P1.22.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MCOB0</name>
+ <description>MCOB0</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>USB_PWRD</name>
+ <description>USB_PWRD</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MAT1</name>
+ <description>MAT1.0</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_23</name>
+ <description>Pin function select P1.23.</description>
+ <bitRange>[15:14]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P1</name>
+ <description>GPIO P1.23.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MCI1</name>
+ <description>MCI1</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PWM1</name>
+ <description>PWM1.4</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MISO0</name>
+ <description>MISO0</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_24</name>
+ <description>Pin function select P1.24.</description>
+ <bitRange>[17:16]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P1</name>
+ <description>GPIO P1.24.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MCI2</name>
+ <description>MCI2</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PWM1</name>
+ <description>PWM1.5</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MOSI0</name>
+ <description>MOSI0</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_25</name>
+ <description>Pin function select P1.25.</description>
+ <bitRange>[19:18]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P1</name>
+ <description>GPIO P1.25</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MCOA1</name>
+ <description>MCOA1</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MAT1</name>
+ <description>MAT1.1</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_26</name>
+ <description>Pin function select P1.26.</description>
+ <bitRange>[21:20]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P1</name>
+ <description>GPIO P1.26</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MCOB1</name>
+ <description>MCOB1</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PWM1</name>
+ <description>PWM1.6</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CAP0</name>
+ <description>CAP0.0</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_27</name>
+ <description>Pin function select P1.27.</description>
+ <bitRange>[23:22]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P1</name>
+ <description>GPIO P1.27</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CLKOUT</name>
+ <description>CLKOUT</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>USB_OVRCR</name>
+ <description>USB_OVRCR</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CAP0</name>
+ <description>CAP0.1</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_28</name>
+ <description>Pin function select P1.28.</description>
+ <bitRange>[25:24]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P1</name>
+ <description>GPIO P1.28</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MCOA2</name>
+ <description>MCOA2</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PCAP1</name>
+ <description>PCAP1.0</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MAT0</name>
+ <description>MAT0.0</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_29</name>
+ <description>Pin function select P1.29</description>
+ <bitRange>[27:26]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P1</name>
+ <description>GPIO P1.29</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MCOB2</name>
+ <description>MCOB2</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PCAP1</name>
+ <description>PCAP1.1</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MAT0</name>
+ <description>MAT0.1</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_30</name>
+ <description>Pin function select P1.30.</description>
+ <bitRange>[29:28]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P1</name>
+ <description>GPIO P1.30</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>VBUS</name>
+ <description>VBUS</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>AD0</name>
+ <description>AD0.4</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_31</name>
+ <description>Pin function select P1.31.</description>
+ <bitRange>[31:30]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_PORT_1</name>
+ <description>GPIO Port 1.31</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SCK1</name>
+ <description>SCK1</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>AD0</name>
+ <description>AD0.5</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PINSEL4</name>
+ <description>Pin function select register 4</description>
+ <addressOffset>0x010</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>P2_0</name>
+ <description>Pin function select P2.0.</description>
+ <bitRange>[1:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P2</name>
+ <description>GPIO P2.0</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PWM1</name>
+ <description>PWM1.1</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>TXD1</name>
+ <description>TXD1</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P2_1</name>
+ <description>Pin function select P2.1.</description>
+ <bitRange>[3:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P2</name>
+ <description>GPIO P2.1</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PWM1</name>
+ <description>PWM1.2</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RXD1</name>
+ <description>RXD1</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P2_2</name>
+ <description>Pin function select P2.2.</description>
+ <bitRange>[5:4]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P2</name>
+ <description>GPIO P2.2</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PWM1</name>
+ <description>PWM1.3</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CTS1</name>
+ <description>CTS1</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P2_3</name>
+ <description>Pin function select P2.3.</description>
+ <bitRange>[7:6]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P2</name>
+ <description>GPIO P2.3.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PWM1</name>
+ <description>PWM1.4</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DCD1</name>
+ <description>DCD1</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P2_4</name>
+ <description>Pin function select P2.4.</description>
+ <bitRange>[9:8]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P2</name>
+ <description>GPIO P2.4.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PWM1</name>
+ <description>PWM1.5</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DSR1</name>
+ <description>DSR1</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P2_5</name>
+ <description>Pin function select P2.5.</description>
+ <bitRange>[11:10]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P2</name>
+ <description>GPIO P2.5.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PWM1</name>
+ <description>PWM1.6</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DTR1</name>
+ <description>DTR1</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P2_6</name>
+ <description>Pin function select P2.6.</description>
+ <bitRange>[13:12]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P2</name>
+ <description>GPIO P2.6.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PCAP1</name>
+ <description>PCAP1.0</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RI1</name>
+ <description>RI1</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P2_7</name>
+ <description>Pin function select P2.7.</description>
+ <bitRange>[15:14]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P2</name>
+ <description>GPIO P2.7.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RD2</name>
+ <description>RD2</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RTS1</name>
+ <description>RTS1</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P2_8</name>
+ <description>Pin function select P2.8.</description>
+ <bitRange>[17:16]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P2</name>
+ <description>GPIO P2.8.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>TD2</name>
+ <description>TD2</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>TXD2</name>
+ <description>TXD2</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENET_MDC</name>
+ <description>ENET_MDC</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P2_9</name>
+ <description>Pin function select P2.9.</description>
+ <bitRange>[19:18]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P2</name>
+ <description>GPIO P2.9</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>USB_CONNECT</name>
+ <description>USB_CONNECT</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RXD2</name>
+ <description>RXD2</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENET_MDIO</name>
+ <description>ENET_MDIO</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P2_10</name>
+ <description>Pin function select P2.10.</description>
+ <bitRange>[21:20]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P2</name>
+ <description>GPIO P2.10</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>EINT0</name>
+ <description>EINT0</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>NMI</name>
+ <description>NMI</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P2_11</name>
+ <description>Pin function select P2.11.</description>
+ <bitRange>[23:22]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P2</name>
+ <description>GPIO P2.11</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>EINT1</name>
+ <description>EINT1</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>I2STX_CLK</name>
+ <description>I2STX_CLK</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P2_12</name>
+ <description>Pin function select P2.12.</description>
+ <bitRange>[25:24]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P2</name>
+ <description>GPIO P2.12</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>EINT2</name>
+ <description>EINT2</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>I2STX_WS</name>
+ <description>I2STX_WS</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P2_13</name>
+ <description>Pin function select P2.13.</description>
+ <bitRange>[27:26]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P2</name>
+ <description>GPIO P2.13</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>EINT3</name>
+ <description>EINT3</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>I2STX_SDA</name>
+ <description>I2STX_SDA</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[31:28]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PINSEL7</name>
+ <description>Pin function select register 7</description>
+ <addressOffset>0x01C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[17:0]</bitRange>
+
+ </field>
+ <field>
+ <name>P3_25</name>
+ <description>Pin function select P3.25.</description>
+ <bitRange>[19:18]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P3</name>
+ <description>GPIO P3.25</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MAT0</name>
+ <description>MAT0.0</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PWM1</name>
+ <description>PWM1.2</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P3_26</name>
+ <description>Pin function select P3.26.</description>
+ <bitRange>[21:20]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P3</name>
+ <description>GPIO P3.26</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>STCLK</name>
+ <description>STCLK</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MAT0</name>
+ <description>MAT0.1</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PWM1</name>
+ <description>PWM1.3</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[31:22]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PINSEL9</name>
+ <description>Pin function select register 9</description>
+ <addressOffset>0x024</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[23:0]</bitRange>
+
+ </field>
+ <field>
+ <name>P4_28</name>
+ <description>Pin function select P4.28.</description>
+ <bitRange>[25:24]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P4</name>
+ <description>GPIO P4.28</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RX_MCLK</name>
+ <description>RX_MCLK</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MAT2</name>
+ <description>MAT2.0</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>TXD3</name>
+ <description>TXD3</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P4_29</name>
+ <description>Pin function select P4.29.</description>
+ <bitRange>[27:26]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>GPIO_P4</name>
+ <description>GPIO P4.29</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>TX_MCLK</name>
+ <description>TX_MCLK</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MAT2</name>
+ <description>MAT2.1</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RXD3</name>
+ <description>RXD3</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[31:28]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PINSEL10</name>
+ <description>Pin function select register 10</description>
+ <addressOffset>0x028</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Software should not write 1 to these bits.</description>
+ <bitRange>[2:0]</bitRange>
+
+ </field>
+ <field>
+ <name>TPIUCTRL</name>
+ <description>TPIU interface pins control.</description>
+ <bitRange>[3:3]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. TPIU interface is disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLED</name>
+ <description>Enabled. TPIU interface is enabled. TPIU signals are available on the pins hosting them regardless of the PINSEL4 content.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Software should not write 1 to these bits.</description>
+ <bitRange>[31:4]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PINMODE0</name>
+ <description>Pin mode select register 0</description>
+ <addressOffset>0x040</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>P0_00MODE</name>
+ <description>Port 0 pin 0 on-chip pull-up/down resistor control.</description>
+ <bitRange>[1:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P0.0 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P0.0 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P0.0 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P0.0 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_01MODE</name>
+ <description>Port 0 pin 1 control.</description>
+ <bitRange>[3:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P0.1 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P0.1 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P0.1 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P0.1 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_02MODE</name>
+ <description>Port 0 pin 2 control.</description>
+ <bitRange>[5:4]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P0.2 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P0.2 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P0.2 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P0.2 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_03MODE</name>
+ <description>Port 0 pin 3 control.</description>
+ <bitRange>[7:6]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P0.3 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P0.3 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P0.3 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P0.3 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_04MODE</name>
+ <description>Port 0 pin 4 control.</description>
+ <bitRange>[9:8]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P0.4 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P0.4 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P0.4 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P0.4 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_05MODE</name>
+ <description>Port 0 pin 5 control.</description>
+ <bitRange>[11:10]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P0.5 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P0.5 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P0.5 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P0.5 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_06MODE</name>
+ <description>Port 0 pin 6 control.</description>
+ <bitRange>[13:12]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P0.6 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. Repeater. P0.6 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P0.6 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P0.6 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_07MODE</name>
+ <description>Port 0 pin 7 control.</description>
+ <bitRange>[15:14]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P0.7 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P0.7 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P0.7 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P0.7 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_08MODE</name>
+ <description>Port 0 pin 8 control.</description>
+ <bitRange>[17:16]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P0.8 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P0.8 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P0.8 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P0.8 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_09MODE</name>
+ <description>Port 0 pin 9 control.</description>
+ <bitRange>[19:18]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P0.9 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P0.9 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P0.9 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P0.9 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_10MODE</name>
+ <description>Port 0 pin 10 control.</description>
+ <bitRange>[21:20]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P0.10 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P0.10 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P0.10 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P0.10 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_11MODE</name>
+ <description>Port 0 pin 11 control.</description>
+ <bitRange>[23:22]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P0.11 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P0.11 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P0.11 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P0.11 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[29:24]</bitRange>
+
+ </field>
+ <field>
+ <name>P0_15MODE</name>
+ <description>Port 0 pin 15 control.</description>
+ <bitRange>[31:30]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P0.15 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P0.15 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P0.15 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P0.15 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PINMODE1</name>
+ <description>Pin mode select register 1</description>
+ <addressOffset>0x044</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>P0_16MODE</name>
+ <description>Port 1 pin 16 control.</description>
+ <bitRange>[1:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P0.16 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P0.16 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P0.16 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P0.16 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_17MODE</name>
+ <description>Port 1 pin 17 control.</description>
+ <bitRange>[3:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P0.17 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P0.17 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P0.17 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P0.17 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_18MODE</name>
+ <description>Port 1 pin 18 control.</description>
+ <bitRange>[5:4]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P0.18 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P0.18 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P0.18 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P0.18 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_19MODE</name>
+ <description>Port 1 pin 19 control.</description>
+ <bitRange>[7:6]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P0.19 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P0.19 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P0.19 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P0.19 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_20MODE</name>
+ <description>Port 1 pin 20 control.</description>
+ <bitRange>[9:8]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P0.20 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P0.20 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P0.20 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P0.20 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_21MODE</name>
+ <description>Port 1 pin 21 control.</description>
+ <bitRange>[11:10]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P0.21 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P0.21 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P0.21 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P0.21 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_22MODE</name>
+ <description>Port 1 pin 22 control.</description>
+ <bitRange>[13:12]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P0.22 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P0.22 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P0.22 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P0.22 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_23MODE</name>
+ <description>Port 1 pin 23 control.</description>
+ <bitRange>[15:14]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P0.23 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P0.23 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P0.23 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P0.23 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_24MODE</name>
+ <description>Port 1 pin 24 control.</description>
+ <bitRange>[17:16]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P0.24 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P0.24 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P0.24 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P0.24 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_25MODE</name>
+ <description>Port 1 pin 25 control.</description>
+ <bitRange>[19:18]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P0.25 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P0.25 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P0.25 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P0.25 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_26MODE</name>
+ <description>Port 1 pin 26 control.</description>
+ <bitRange>[21:20]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P0.26 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P0.26 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P0.26 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P0.26 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[29:22]</bitRange>
+
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[31:30]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PINMODE2</name>
+ <description>Pin mode select register 2</description>
+ <addressOffset>0x048</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>P1_00MODE</name>
+ <description>Port 1 pin 0 control.</description>
+ <bitRange>[1:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P1.0 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P1.0 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P1.0 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P1.0 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_01MODE</name>
+ <description>Port 1 pin 1 control.</description>
+ <bitRange>[3:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P1.1 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P1.1 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P1.1 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P1.1 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[7:4]</bitRange>
+
+ </field>
+ <field>
+ <name>P1_04MODE</name>
+ <description>Port 1 pin 4 control.</description>
+ <bitRange>[9:8]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P1.4 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P1.4 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P1.4 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P1.4 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[15:10]</bitRange>
+
+ </field>
+ <field>
+ <name>P1_08MODE</name>
+ <description>Port 1 pin 8 control.</description>
+ <bitRange>[17:16]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P1.8 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P1.8 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P1.8 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P1.8 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_09MODE</name>
+ <description>Port 1 pin 9 control.</description>
+ <bitRange>[19:18]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P1.9 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P1.9 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P1.9 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P1.9 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_10MODE</name>
+ <description>Port 1 pin 10 control.</description>
+ <bitRange>[21:20]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P1.10 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P1.10 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P1.10 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P1.10 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[27:22]</bitRange>
+
+
+ </field>
+ <field>
+ <name>P1_14MODE</name>
+ <description>Port 1 pin 14 control.</description>
+ <bitRange>[29:28]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P1.14 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P1.14 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P1.14 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P1.14 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_15MODE</name>
+ <description>Port 1 pin 15 control.</description>
+ <bitRange>[31:30]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P1.15 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P1.15 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P1.15 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P1.15 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PINMODE3</name>
+ <description>Pin mode select register 3.</description>
+ <addressOffset>0x04C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>P1_16MODE</name>
+ <description>Port 1 pin 16 control.</description>
+ <bitRange>[1:0]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P1.16 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P1.16 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P1.16 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P1.16 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_17MODE</name>
+ <description>Port 1 pin 17 control.</description>
+ <bitRange>[3:2]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P1.17 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P1.17 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P1.17 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P1.17 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_18MODE</name>
+ <description>Port 1 pin 18 control.</description>
+ <bitRange>[5:4]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P1.18 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P1.18 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P1.18 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P1.18 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_19MODE</name>
+ <description>Port 1 pin 19 control.</description>
+ <bitRange>[7:6]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P1.19 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P1.19 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P1.19 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P1.19 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_20MODE</name>
+ <description>Port 1 pin 20 control.</description>
+ <bitRange>[9:8]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P1.20 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P1.20 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P1.20 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P1.20 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_21MODE</name>
+ <description>Port 1 pin 21 control.</description>
+ <bitRange>[11:10]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P1.21 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P1.21 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P1.21 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P1.21 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_22MODE</name>
+ <description>Port 1 pin 22 control.</description>
+ <bitRange>[13:12]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P1.22 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P1.22 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P1.22 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P1.22 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_23MODE</name>
+ <description>Port 1 pin 23 control.</description>
+ <bitRange>[15:14]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P1.23 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P1.23 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P1.23 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P1.23 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_24MODE</name>
+ <description>Port 1 pin 24 control.</description>
+ <bitRange>[17:16]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P1.24 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P1.24 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P1.24 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P1.24 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_25MODE</name>
+ <description>Port 1 pin 25 control.</description>
+ <bitRange>[19:18]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P1.25 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P1.25 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P1.25 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P1.25 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_26MODE</name>
+ <description>Port 1 pin 26 control.</description>
+ <bitRange>[21:20]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P1.26 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P1.26 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P1.26 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P1.26 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_27MODE</name>
+ <description>Port 1 pin 27 control.</description>
+ <bitRange>[23:22]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P1.27 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P1.27 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P1.27 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P1.27 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_28MODE</name>
+ <description>Port 1 pin 28 control.</description>
+ <bitRange>[25:24]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P1.28 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P1.28 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P1.28 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P1.28 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_29MODE</name>
+ <description>Port 1 pin 29 control.</description>
+ <bitRange>[27:26]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P1.29 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P1.29 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P1.29 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P1.29 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_30MODE</name>
+ <description>Port 1 pin 30 control.</description>
+ <bitRange>[29:28]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P1.30 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P1.30 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P1.30 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P1.30 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_31MODE</name>
+ <description>Port 1 pin 31 control.</description>
+ <bitRange>[31:30]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P1.31 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P1.31 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P1.31 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P1.31 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PINMODE4</name>
+ <description>Pin mode select register 4</description>
+ <addressOffset>0x050</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>P2_00MODE</name>
+ <description>Port 2 pin 0 control.</description>
+ <bitRange>[1:0]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P2.0 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P2.0 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P2.0 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P2.0 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P2_01MODE</name>
+ <description>Port 2 pin 1 control.</description>
+ <bitRange>[3:2]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P2.1 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P2.1 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P2.1 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P2.1 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P2_02MODE</name>
+ <description>Port 2 pin 2 control.</description>
+ <bitRange>[5:4]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P2.2 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P2.2 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P2.2 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P2.2 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P2_03MODE</name>
+ <description>Port 2 pin 3 control.</description>
+ <bitRange>[7:6]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P2.3 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P2.3 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P2.3 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P2.3 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P2_04MODE</name>
+ <description>Port 2 pin 4 control.</description>
+ <bitRange>[9:8]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P2.4 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P2.4 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P2.4 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P2.4 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P2_05MODE</name>
+ <description>Port 2 pin 5 control.</description>
+ <bitRange>[11:10]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P2.5 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P2.5 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P2.5 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P2.5 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P2_06MODE</name>
+ <description>Port 2 pin 6 control.</description>
+ <bitRange>[13:12]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P2.6 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P2.6 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P2.6 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P2.6 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P2_07MODE</name>
+ <description>Port 2 pin 7 control.</description>
+ <bitRange>[15:14]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P2.7 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P2.7 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P2.7 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P2.7 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P2_08MODE</name>
+ <description>Port 2 pin 8 control.</description>
+ <bitRange>[17:16]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P2.8 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P2.8 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P2.8 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P2.8 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P2_09MODE</name>
+ <description>Port 2 pin 9 control.</description>
+ <bitRange>[19:18]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P2.9 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P2.9 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P2.9 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P2.9 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P2_10MODE</name>
+ <description>Port 2 pin 10 control.</description>
+ <bitRange>[21:20]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P2.10 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P2.10 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P2.10 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P2.10 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P2_11MODE</name>
+ <description>Port 2 pin 11 control.</description>
+ <bitRange>[23:22]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P2.11 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P2.11 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P2.11 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P2.11 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P2_12MODE</name>
+ <description>Port 2 pin 12 control.</description>
+ <bitRange>[25:24]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P2.12 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P2.12 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P2.12 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P2.12 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P2_13MODE</name>
+ <description>Port 2 pin 13 control.</description>
+ <bitRange>[27:26]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P2.13 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P2.13 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P2.13 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P2.13 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[31:28]</bitRange>
+
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PINMODE7</name>
+ <description>Pin mode select register 7</description>
+ <addressOffset>0x05C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <bitRange>[17:0]</bitRange>
+
+
+ </field>
+ <field>
+ <name>P3_25MODE</name>
+ <description>Port 3 pin 25 control.</description>
+ <bitRange>[19:18]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P3.25 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P3.25 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P3.25 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P3.25 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P3_26MODE</name>
+ <description>Port 3 pin 26 control.</description>
+ <bitRange>[21:20]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P3.26 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P3.26 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P3.26 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P3.26 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[31:22]</bitRange>
+
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PINMODE9</name>
+ <description>Pin mode select register 9</description>
+ <addressOffset>0x064</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[23:0]</bitRange>
+
+
+ </field>
+ <field>
+ <name>P4_28MODE</name>
+ <description>Port 4 pin 28 control.</description>
+ <bitRange>[25:24]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P4.28 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P4.28 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P4.28 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P4.28 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P4_29MODE</name>
+ <description>Port 4 pin 29 control.</description>
+ <bitRange>[27:26]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>PULL_UP</name>
+ <description>Pull-up. P4.29 pin has a pull-up resistor enabled.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>REPEATER</name>
+ <description>Repeater. P4.29 pin has repeater mode enabled.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. P4.29 pin has neither pull-up nor pull-down.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PULL_DOWN</name>
+ <description>Pull-down. P4.29 has a pull-down resistor enabled.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[31:28]</bitRange>
+
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PINMODE_OD0</name>
+ <description>Open drain mode control register 0</description>
+ <addressOffset>0x068</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>P0_00OD</name>
+ <description>Port 0 pin 0 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.</description>
+ <bitRange>[0:0]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P0.0 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P0.0 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_01OD</name>
+ <description>Port 0 pin 1 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.</description>
+ <bitRange>[1:1]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P0.1 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P0.1 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_02OD</name>
+ <description>Port 0 pin 2 open drain mode control</description>
+ <bitRange>[2:2]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P0.2 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P0.2 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_03OD</name>
+ <description>Port 0 pin 3 open drain mode control</description>
+ <bitRange>[3:3]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P0.3 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P0.3 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_04OD</name>
+ <description>Port 0 pin 4 open drain mode control</description>
+ <bitRange>[4:4]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P0.4 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P0.4 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_05OD</name>
+ <description>Port 0 pin 5 open drain mode control</description>
+ <bitRange>[5:5]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P0.5 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P0.5 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_06OD</name>
+ <description>Port 0 pin 6 open drain mode control</description>
+ <bitRange>[6:6]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P0.6 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P0.6 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_07OD</name>
+ <description>Port 0 pin 7 open drain mode control</description>
+ <bitRange>[7:7]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P0.7 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P0.7 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_08OD</name>
+ <description>Port 0 pin 8 open drain mode control</description>
+ <bitRange>[8:8]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P0.8 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P0.8 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_09OD</name>
+ <description>Port 0 pin 9 open drain mode control</description>
+ <bitRange>[9:9]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P0.9 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P0.9 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_10OD</name>
+ <description>Port 0 pin 10 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.</description>
+ <bitRange>[10:10]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P0.10 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P0.10 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_11OD</name>
+ <description>Port 0 pin 11 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.</description>
+ <bitRange>[11:11]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P0.11 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P0.11 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[14:12]</bitRange>
+
+
+ </field>
+ <field>
+ <name>P0_15OD</name>
+ <description>Port 0 pin 15 open drain mode control</description>
+ <bitRange>[15:15]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P0.15 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P0.15 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_16OD</name>
+ <description>Port 0 pin 16 open drain mode control</description>
+ <bitRange>[16:16]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P0.16 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P0.16 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_17OD</name>
+ <description>Port 0 pin 17 open drain mode control</description>
+ <bitRange>[17:17]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P0.17 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P0.17 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_18OD</name>
+ <description>Port 0 pin 18 open drain mode control</description>
+ <bitRange>[18:18]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P0.18 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P0.18 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_19OD</name>
+ <description>Port 0 pin 19 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.</description>
+ <bitRange>[19:19]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P0.19 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P0.19 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_20OD</name>
+ <description>Port 0 pin 20open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.</description>
+ <bitRange>[20:20]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P0.20 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P0.20 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_21OD</name>
+ <description>Port 0 pin 21 open drain mode control</description>
+ <bitRange>[21:21]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P0.21 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P0.21 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_22OD</name>
+ <description>Port 0 pin 22 open drain mode control</description>
+ <bitRange>[22:22]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P0.22 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P0.22 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_23OD</name>
+ <description>Port 0 pin 23 open drain mode control</description>
+ <bitRange>[23:23]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P0.23 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P0.23 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_24OD</name>
+ <description>Port 0 pin 24open drain mode control</description>
+ <bitRange>[24:24]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P0.23 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P0.23 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_25OD</name>
+ <description>Port 0 pin 25 open drain mode control</description>
+ <bitRange>[25:25]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P0.25 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P0.25 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_26OD</name>
+ <description>Port 0 pin 26 open drain mode control</description>
+ <bitRange>[26:26]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P0.26 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P0.26 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[28:27]</bitRange>
+
+
+ </field>
+ <field>
+ <name>P0_29OD</name>
+ <description>Port 0 pin 29 open drain mode control</description>
+ <bitRange>[29:29]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P0.29 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P0.29 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P0_30OD</name>
+ <description>Port 0 pin 30 open drain mode control</description>
+ <bitRange>[30:30]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P0.30 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P0.30 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[31:31]</bitRange>
+
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PINMODE_OD1</name>
+ <description>Open drain mode control register 1</description>
+ <addressOffset>0x06C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>P1_00OD</name>
+ <description>Port 1 pin 0 open drain mode control.</description>
+ <bitRange>[0:0]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P1.0 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P1.0 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_01OD</name>
+ <description>Port 1 pin 1 open drain mode control, see P1.00OD</description>
+ <bitRange>[1:1]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P1.1 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P1.1 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[3:2]</bitRange>
+
+
+ </field>
+ <field>
+ <name>P1_04OD</name>
+ <description>Port 1 pin 4 open drain mode control, see P1.00OD</description>
+ <bitRange>[4:4]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P1.4 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P1.4 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[7:5]</bitRange>
+
+
+ </field>
+ <field>
+ <name>P1_08OD</name>
+ <description>Port 1 pin 8 open drain mode control, see P1.00OD</description>
+ <bitRange>[8:8]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P1.8 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P1.8 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_09OD</name>
+ <description>Port 1 pin 9 open drain mode control, see P1.00OD</description>
+ <bitRange>[9:9]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P1.9 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P1.9 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_10OD</name>
+ <description>Port 1 pin 10 open drain mode control, see P1.00OD</description>
+ <bitRange>[10:10]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P1.10 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P1.10 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[13:11]</bitRange>
+
+
+ </field>
+ <field>
+ <name>P1_14OD</name>
+ <description>Port 1 pin 14 open drain mode control, see P1.00OD</description>
+ <bitRange>[14:14]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P1.14 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P1.14 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_15OD</name>
+ <description>Port 1 pin 15 open drain mode control, see P1.00OD</description>
+ <bitRange>[15:15]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P1.15 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P1.15 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_16OD</name>
+ <description>Port 1 pin 16 open drain mode control, see P1.00OD</description>
+ <bitRange>[16:16]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P1.16 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P1.16 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_17OD</name>
+ <description>Port 1 pin 17 open drain mode control, see P1.00OD</description>
+ <bitRange>[17:17]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P1.17 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P1.17 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_18OD</name>
+ <description>Port 1 pin 18 open drain mode control, see P1.00OD</description>
+ <bitRange>[18:18]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P1.18 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P1.18 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_19OD</name>
+ <description>Port 1 pin 19 open drain mode control, see P1.00OD</description>
+ <bitRange>[19:19]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P1.19 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P1.19 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_20OD</name>
+ <description>Port 1 pin 20open drain mode control, see P1.00OD</description>
+ <bitRange>[20:20]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P1.20 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P1.20 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_21OD</name>
+ <description>Port 1 pin 21 open drain mode control, see P1.00OD</description>
+ <bitRange>[21:21]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P1.21 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P1.21 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_22OD</name>
+ <description>Port 1 pin 22 open drain mode control, see P1.00OD</description>
+ <bitRange>[22:22]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P1.22 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P1.22 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_23OD</name>
+ <description>Port 1 pin 23 open drain mode control, see P1.00OD</description>
+ <bitRange>[23:23]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P1.23 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P1.23 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_24OD</name>
+ <description>Port 1 pin 24open drain mode control, see P1.00OD</description>
+ <bitRange>[24:24]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P1.24 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P1.24 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_25OD</name>
+ <description>Port 1 pin 25 open drain mode control, see P1.00OD</description>
+ <bitRange>[25:25]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P1.25 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P1.25 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_26OD</name>
+ <description>Port 1 pin 26 open drain mode control, see P1.00OD</description>
+ <bitRange>[26:26]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P1.26 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P1.26 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_27OD</name>
+ <description>Port 1 pin 27 open drain mode control, see P1.00OD</description>
+ <bitRange>[27:27]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P1.27 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P1.27 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_28OD</name>
+ <description>Port 1 pin 28 open drain mode control, see P1.00OD</description>
+ <bitRange>[28:28]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P1.28 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P1.28 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_29OD</name>
+ <description>Port 1 pin 29 open drain mode control, see P1.00OD</description>
+ <bitRange>[29:29]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P1.29 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P1.29 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_30OD</name>
+ <description>Port 1 pin 30 open drain mode control, see P1.00OD</description>
+ <bitRange>[30:30]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P1.30 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P1.30 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P1_31OD</name>
+ <description>Port 1 pin 31 open drain mode control.</description>
+ <bitRange>[31:31]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P1.31 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P1.31 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PINMODE_OD2</name>
+ <description>Open drain mode control register 2</description>
+ <addressOffset>0x070</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>P2_00OD</name>
+ <description>Port 2 pin 0 open drain mode control.</description>
+ <bitRange>[0:0]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P2.0 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P2.0 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P2_01OD</name>
+ <description>Port 2 pin 1 open drain mode control, see P2.00OD</description>
+ <bitRange>[1:1]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P2.1 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P2.1p in is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P2_02OD</name>
+ <description>Port 2 pin 2 open drain mode control, see P2.00OD</description>
+ <bitRange>[2:2]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P2.2 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P2.2 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P2_03OD</name>
+ <description>Port 2 pin 3 open drain mode control, see P2.00OD</description>
+ <bitRange>[3:3]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P2.3 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P2.3 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P2_04OD</name>
+ <description>Port 2 pin 4 open drain mode control, see P2.00OD</description>
+ <bitRange>[4:4]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P2.4 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P2.4 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P2_05OD</name>
+ <description>Port 2 pin 5 open drain mode control, see P2.00OD</description>
+ <bitRange>[5:5]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P2.5 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P2.5 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P2_06OD</name>
+ <description>Port 2 pin 6 open drain mode control, see P2.00OD</description>
+ <bitRange>[6:6]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P2.6 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P2.6 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P2_07OD</name>
+ <description>Port 2 pin 7 open drain mode control, see P2.00OD</description>
+ <bitRange>[7:7]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P2.7 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P2.7 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P2_08OD</name>
+ <description>Port 2 pin 8 open drain mode control, see P2.00OD</description>
+ <bitRange>[8:8]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P2.8 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P2.8 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P2_09OD</name>
+ <description>Port 2 pin 9 open drain mode control, see P2.00OD</description>
+ <bitRange>[9:9]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P2.9 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P2.9 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P2_10OD</name>
+ <description>Port 2 pin 10 open drain mode control, see P2.00OD</description>
+ <bitRange>[10:10]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P2.10 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P2.10 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P2_11OD</name>
+ <description>Port 2 pin 11 open drain mode control, see P2.00OD</description>
+ <bitRange>[11:11]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P2.11 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P2.11 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P2_12OD</name>
+ <description>Port 2 pin 12 open drain mode control, see P2.00OD</description>
+ <bitRange>[12:12]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P2.12 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P2.12 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P2_13OD</name>
+ <description>Port 2 pin 13 open drain mode control, see P2.00OD</description>
+ <bitRange>[13:13]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P2.13 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P2.13 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[31:14]</bitRange>
+
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PINMODE_OD3</name>
+ <description>Open drain mode control register 3</description>
+ <addressOffset>0x074</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[24:0]</bitRange>
+
+
+ </field>
+ <field>
+ <name>P3_25OD</name>
+ <description>Port 3 pin 25 open drain mode control.</description>
+ <bitRange>[25:25]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P3.25 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P3.25 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P3_26OD</name>
+ <description>Port 3 pin 26 open drain mode control, see P3.25OD</description>
+ <bitRange>[26:26]</bitRange>
+
+
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[31:27]</bitRange>
+
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PINMODE_OD4</name>
+ <description>Open drain mode control register 4</description>
+ <addressOffset>0x078</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[27:0]</bitRange>
+
+
+ </field>
+ <field>
+ <name>P4_28OD</name>
+ <description>Port 4 pin 28 open drain mode control.</description>
+ <bitRange>[28:28]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>Normal. P4.28 pin is in the normal (not open drain) mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OPEN_DRAIN</name>
+ <description>Open-drain. P4.28 pin is in the open drain mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>P4_29OD</name>
+ <description>Port 4 pin 29 open drain mode control, see P4.28OD</description>
+ <bitRange>[29:29]</bitRange>
+
+
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[31:30]</bitRange>
+
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>I2CPADCFG</name>
+ <description>I2C Pin Configuration register</description>
+ <addressOffset>0x07C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>SDADRV0</name>
+ <description>Drive mode control for the SDA0 pin, P0.27.</description>
+ <bitRange>[0:0]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>STANDARD</name>
+ <description>Standard. The SDA0 pin is in the standard drive mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>FAST_MODE_PLUS</name>
+ <description>Fast-mode plus. The SDA0 pin is in Fast Mode Plus drive mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>SDAI2C0</name>
+ <description>I 2C filter mode control for the SDA0 pin, P0.27.</description>
+ <bitRange>[1:1]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>ENABLED</name>
+ <description>Enabled. The SDA0 pin has I2C glitch filtering and slew rate control enabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. The SDA0 pin has I2C glitch filtering and slew rate control disabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>SCLDRV0</name>
+ <description>Drive mode control for the SCL0 pin, P0.28.</description>
+ <bitRange>[2:2]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>STANDARD</name>
+ <description>Standard. The SCL0 pin is in the standard drive mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>FAST_MODE_PLUS</name>
+ <description>Fast-mode plus. The SCL0 pin is in Fast Mode Plus drive mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>SCLI2C0</name>
+ <description>I 2C filter mode control for the SCL0 pin, P0.28.</description>
+ <bitRange>[3:3]</bitRange>
+
+ <enumeratedValues>
+ <name>ENUM</name>
+
+ <enumeratedValue>
+ <name>ENABLED</name>
+ <description>Enabled. The SCL0 pin has I2C glitch filtering and slew rate control enabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. The SCL0 pin has I2C glitch filtering and slew rate control disabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[31:4]</bitRange>
+
+
+ </field>
+ </fields>
+ </register>
+
+
+</registers>
+
+
+
+
+
+
+
+
+
+
+
+
+ </peripheral>
+ <peripheral>
+ <name>SSP1</name>
+ <description>SSP1 controller</description>
+ <baseAddress>0x40030000</baseAddress>
+ <addressBlock>
+ <offset>0</offset>
+ <size>0xFFF</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>SSP1</name>
+ <value>15</value>
+
+ </interrupt>
+ <registers>
+ <register>
+ <name>CR0</name>
+ <description>Control Register 0. Selects the serial clock rate, bus type, and data size.</description>
+ <addressOffset>0x000</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>DSS</name>
+ <description>Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.</description>
+ <bitRange>[3:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>4_BIT_TRANSFER</name>
+ <description>4-bit transfer</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>5_BIT_TRANSFER</name>
+ <description>5-bit transfer</description>
+ <value>0x4</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>6_BIT_TRANSFER</name>
+ <description>6-bit transfer</description>
+ <value>0x5</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>7_BIT_TRANSFER</name>
+ <description>7-bit transfer</description>
+ <value>0x6</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>8_BIT_TRANSFER</name>
+ <description>8-bit transfer</description>
+ <value>0x7</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>9_BIT_TRANSFER</name>
+ <description>9-bit transfer</description>
+ <value>0x8</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>10_BIT_TRANSFER</name>
+ <description>10-bit transfer</description>
+ <value>0x9</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>11_BIT_TRANSFER</name>
+ <description>11-bit transfer</description>
+ <value>0xA</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>12_BIT_TRANSFER</name>
+ <description>12-bit transfer</description>
+ <value>0xB</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>13_BIT_TRANSFER</name>
+ <description>13-bit transfer</description>
+ <value>0xC</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>14_BIT_TRANSFER</name>
+ <description>14-bit transfer</description>
+ <value>0xD</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>15_BIT_TRANSFER</name>
+ <description>15-bit transfer</description>
+ <value>0xE</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>16_BIT_TRANSFER</name>
+ <description>16-bit transfer</description>
+ <value>0xF</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>FRF</name>
+ <description>Frame Format.</description>
+ <bitRange>[5:4]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>SPI</name>
+ <description>SPI</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>TI</name>
+ <description>TI</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MICROWIRE</name>
+ <description>Microwire</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>THIS_COMBINATION_IS_</name>
+ <description>This combination is not supported and should not be used.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CPOL</name>
+ <description>Clock Out Polarity. This bit is only used in SPI mode.</description>
+ <bitRange>[6:6]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>BUS_LOW</name>
+ <description>SSP controller maintains the bus clock low between frames.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>BUS_HIGH</name>
+ <description>SSP controller maintains the bus clock high between frames.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CPHA</name>
+ <description>Clock Out Phase. This bit is only used in SPI mode.</description>
+ <bitRange>[7:7]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>FIRST_CLOCK</name>
+ <description>SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SECOND_CLOCK</name>
+ <description>SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>SCR</name>
+ <description>Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1]).</description>
+ <bitRange>[15:8]</bitRange>
+
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:16]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CR1</name>
+ <description>Control Register 1. Selects master/slave and other modes.</description>
+ <addressOffset>0x004</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>LBM</name>
+ <description>Loop Back Mode.</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>NORMAL</name>
+ <description>During normal operation.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OUPTU</name>
+ <description>Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively).</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>SSE</name>
+ <description>SSP Enable.</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>The SSP controller is disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLED</name>
+ <description>The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>MS</name>
+ <description>Master/Slave Mode.This bit can only be written when the SSE bit is 0.</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>MASTER</name>
+ <description>The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SLAVE</name>
+ <description>The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>SOD</name>
+ <description>Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO).</description>
+ <bitRange>[3:3]</bitRange>
+
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:4]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DR</name>
+ <description>Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO.</description>
+ <addressOffset>0x008</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <readAction>modify</readAction>
+ <fields>
+ <field>
+ <name>DATA</name>
+ <description>Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s.</description>
+ <bitRange>[15:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:16]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SR</name>
+ <description>Status Register</description>
+ <addressOffset>0x00C</addressOffset>
+ <access>read-only</access>
+ <resetValue>0x00000003</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>TFE</name>
+ <description>Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>TNF</name>
+ <description>Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>RNE</name>
+ <description>Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>RFF</name>
+ <description>Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>BSY</name>
+ <description>Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:5]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CPSR</name>
+ <description>Clock Prescale Register</description>
+ <addressOffset>0x010</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>CPSDVSR</name>
+ <description>This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0.</description>
+ <bitRange>[7:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IMSC</name>
+ <description>Interrupt Mask Set and Clear Register</description>
+ <addressOffset>0x014</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RORIM</name>
+ <description>Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>RTIM</name>
+ <description>Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]).</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>RXIM</name>
+ <description>Software should set this bit to enable interrupt when the Rx FIFO is at least half full.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>TXIM</name>
+ <description>Software should set this bit to enable interrupt when the Tx FIFO is at least half empty.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:4]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RIS</name>
+ <description>Raw Interrupt Status Register</description>
+ <addressOffset>0x018</addressOffset>
+ <access>read-only</access>
+ <resetValue>0x00000008</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RORRIS</name>
+ <description>This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>RTRIS</name>
+ <description>This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]).</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>RXRIS</name>
+ <description>This bit is 1 if the Rx FIFO is at least half full.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>TXRIS</name>
+ <description>This bit is 1 if the Tx FIFO is at least half empty.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:4]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>MIS</name>
+ <description>Masked Interrupt Status Register</description>
+ <addressOffset>0x01C</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RORMIS</name>
+ <description>This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>RTMIS</name>
+ <description>This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]).</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>RXMIS</name>
+ <description>This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>TXMIS</name>
+ <description>This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:4]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ICR</name>
+ <description>SSPICR Interrupt Clear Register</description>
+ <addressOffset>0x020</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>RORIC</name>
+ <description>Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>RTIC</name>
+ <description>Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1]).</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:2]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMACR</name>
+ <description>SSP0 DMA control register</description>
+ <addressOffset>0x024</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RXDMAE</name>
+ <description>Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>TXDMAE</name>
+ <description>Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:2]</bitRange>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>ADC</name>
+ <description>Analog-to-Digital Converter (ADC) </description>
+ <groupName>ADC</groupName>
+ <baseAddress>0x40034000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0xFFF</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>ADC</name>
+ <value>22</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>CR</name>
+ <description>A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur.</description>
+ <addressOffset>0x000</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>SEL</name>
+ <description>Selects which of the AD0[7:0] pins is (are) to be sampled and converted. For AD0, bit 0 selects Pin AD0[0], and bit 7 selects pin AD0[7]. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones is allowed. All zeroes is equivalent to 0x01.</description>
+ <bitRange>[7:0]</bitRange>
+
+ </field>
+ <field>
+ <name>CLKDIV</name>
+ <description>The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D converter, which should be less than or equal to 12.4 MHz. Typically, software should program the smallest value in this field that yields a clock of 12.4 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable.</description>
+ <bitRange>[15:8]</bitRange>
+
+ </field>
+ <field>
+ <name>BURST</name>
+ <description>Burst mode</description>
+ <bitRange>[16:16]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>BURST</name>
+ <description>The AD converter does repeated conversions at up to 400 kHz, scanning (if necessary) through the pins selected by bits set to ones in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1-bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that's in progress when this bit is cleared will be completed. START bits must be 000 when BURST = 1 or conversions will not start.</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SW</name>
+ <description>Conversions are software controlled and require 31 clocks.</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[20:17]</bitRange>
+
+ </field>
+ <field>
+ <name>PDN</name>
+ <description>Power down mode</description>
+ <bitRange>[21:21]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>POWERED</name>
+ <description>The A/D converter is operational.</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>POWERDOWN</name>
+ <description>The A/D converter is in power-down mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[23:22]</bitRange>
+
+ </field>
+ <field>
+ <name>START</name>
+ <description>When the BURST bit is 0, these bits control whether and when an A/D conversion is started:</description>
+ <bitRange>[26:24]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>NO_START_THIS_VALUE</name>
+ <description>No start (this value should be used when clearing PDN to 0).</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>START_CONVERSION_NOW</name>
+ <description>Start conversion now.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>P2_10</name>
+ <description>Start conversion when the edge selected by bit 27 occurs on the P2[10] pin.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>P1_27</name>
+ <description>Start conversion when the edge selected by bit 27 occurs on the P1[27] pin.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MAT0_1</name>
+ <description>Start conversion when the edge selected by bit 27 occurs on MAT0.1. Note that this does not require that the MAT0.1 function appear on a device pin.</description>
+ <value>0x4</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MAT0_3</name>
+ <description>Start conversion when the edge selected by bit 27 occurs on MAT0.3. Note that it is not possible to cause the MAT0.3 function to appear on a device pin.</description>
+ <value>0x5</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MAT1_0</name>
+ <description>Start conversion when the edge selected by bit 27 occurs on MAT1.0. Note that this does not require that the MAT1.0 function appear on a device pin.</description>
+ <value>0x6</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MAT1_1</name>
+ <description>Start conversion when the edge selected by bit 27 occurs on MAT1.1. Note that this does not require that the MAT1.1 function appear on a device pin.</description>
+ <value>0x7</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>EDGE</name>
+ <description>This bit is significant only when the START field contains 010-111. In these cases:</description>
+ <bitRange>[27:27]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>FALLLING</name>
+ <description>Start conversion on a falling edge on the selected CAP/MAT signal.</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RISING</name>
+ <description>Start conversion on a rising edge on the selected CAP/MAT signal.</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:28]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>GDR</name>
+ <description>A/D Global Data Register. This register contains the ADC's DONE bit and the result of the most recent A/D conversion.</description>
+ <addressOffset>0x004</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[3:0]</bitRange>
+ </field>
+ <field>
+ <name>RESULT</name>
+ <description>When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin selected by the SEL field, as it falls within the range of VREFP to VSS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.</description>
+ <bitRange>[15:4]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[23:16]</bitRange>
+ </field>
+ <field>
+ <name>CHN</name>
+ <description>These bits contain the channel from which the RESULT bits were converted (e.g. 000 identifies channel 0, 001 channel 1...).</description>
+ <bitRange>[26:24]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[29:27]</bitRange>
+ </field>
+ <field>
+ <name>OVERRUN</name>
+ <description>This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits. This bit is cleared by reading this register.</description>
+ <bitRange>[30:30]</bitRange>
+ </field>
+ <field>
+ <name>DONE</name>
+ <description>This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started.</description>
+ <bitRange>[31:31]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>INTEN</name>
+ <description>A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt.</description>
+ <addressOffset>0x00C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0x100</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>ADINTEN0</name>
+ <description>Interrupt enable</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE</name>
+ <description>Completion of a conversion on ADC channel 0 will not generate an interrupt.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE</name>
+ <description>Completion of a conversion on ADC channel 0 will generate an interrupt.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>ADINTEN1</name>
+ <description>Interrupt enable</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE</name>
+ <description>Completion of a conversion on ADC channel 1 will not generate an interrupt.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE</name>
+ <description>Completion of a conversion on ADC channel 1 will generate an interrupt.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>ADINTEN2</name>
+ <description>Interrupt enable</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE</name>
+ <description>Completion of a conversion on ADC channel 2 will not generate an interrupt.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE</name>
+ <description>Completion of a conversion on ADC channel 2 will generate an interrupt.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>ADINTEN3</name>
+ <description>Interrupt enable</description>
+ <bitRange>[3:3]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE</name>
+ <description>Completion of a conversion on ADC channel 3 will not generate an interrupt.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE</name>
+ <description>Completion of a conversion on ADC channel 3 will generate an interrupt.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>ADINTEN4</name>
+ <description>Interrupt enable</description>
+ <bitRange>[4:4]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE</name>
+ <description>Completion of a conversion on ADC channel 4 will not generate an interrupt.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE</name>
+ <description>Completion of a conversion on ADC channel 4 will generate an interrupt.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>ADINTEN5</name>
+ <description>Interrupt enable</description>
+ <bitRange>[5:5]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE</name>
+ <description>Completion of a conversion on ADC channel 5 will not generate an interrupt.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE</name>
+ <description>Completion of a conversion on ADC channel 5 will generate an interrupt.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>ADINTEN6</name>
+ <description>Interrupt enable</description>
+ <bitRange>[6:6]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE</name>
+ <description>Completion of a conversion on ADC channel 6 will not generate an interrupt.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE</name>
+ <description>Completion of a conversion on ADC channel 6 will generate an interrupt.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>ADINTEN7</name>
+ <description>Interrupt enable</description>
+ <bitRange>[7:7]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE</name>
+ <description>Completion of a conversion on ADC channel 7 will not generate an interrupt.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE</name>
+ <description>Completion of a conversion on ADC channel 7 will generate an interrupt.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>ADGINTEN</name>
+ <description>Interrupt enable</description>
+ <bitRange>[8:8]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>CHANNELS</name>
+ <description>Only the individual ADC channels enabled by ADINTEN7:0 will generate interrupts.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>GLOBAL</name>
+ <description>The global DONE flag in ADDR is enabled to generate an interrupt in addition to any individual ADC channels that are enabled to generate interrupts.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:9]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <dim>8</dim>
+ <dimIncrement>0x4</dimIncrement>
+ <dimIndex>0-7</dimIndex>
+ <name>DR[%s]</name>
+ <displayName>DR[%s]</displayName>
+ <description>A/D Channel 0 Data Register. This register contains the result of the most recent conversion completed on channel 0.</description>
+ <addressOffset>0x010</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[3:0]</bitRange>
+ </field>
+ <field>
+ <name>RESULT</name>
+ <description>When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin, as it falls within the range of VREFP to V SS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.</description>
+ <bitRange>[15:4]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[29:16]</bitRange>
+ </field>
+ <field>
+ <name>OVERRUN</name>
+ <description>This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits.This bit is cleared by reading this register.</description>
+ <bitRange>[30:30]</bitRange>
+ </field>
+ <field>
+ <name>DONE</name>
+ <description>This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.</description>
+ <bitRange>[31:31]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>STAT</name>
+ <description>A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt/DMA flag.</description>
+ <addressOffset>0x030</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>DONE0</name>
+ <description>This bit mirrors the DONE status flag from the result register for A/D channel 0.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>DONE1</name>
+ <description>This bit mirrors the DONE status flag from the result register for A/D channel 1.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>DONE2</name>
+ <description>This bit mirrors the DONE status flag from the result register for A/D channel 2.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>DONE3</name>
+ <description>This bit mirrors the DONE status flag from the result register for A/D channel 3.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>DONE4</name>
+ <description>This bit mirrors the DONE status flag from the result register for A/D channel 4.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>DONE5</name>
+ <description>This bit mirrors the DONE status flag from the result register for A/D channel 5.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>DONE6</name>
+ <description>This bit mirrors the DONE status flag from the result register for A/D channel 6.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>DONE7</name>
+ <description>This bit mirrors the DONE status flag from the result register for A/D channel 7.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>OVERRUN0</name>
+ <description>This bit mirrors the OVERRRUN status flag from the result register for A/D channel 0.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>OVERRUN1</name>
+ <description>This bit mirrors the OVERRRUN status flag from the result register for A/D channel 1.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>OVERRUN2</name>
+ <description>This bit mirrors the OVERRRUN status flag from the result register for A/D channel 2.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>OVERRUN3</name>
+ <description>This bit mirrors the OVERRRUN status flag from the result register for A/D channel 3.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>OVERRUN4</name>
+ <description>This bit mirrors the OVERRRUN status flag from the result register for A/D channel 4.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>OVERRUN5</name>
+ <description>This bit mirrors the OVERRRUN status flag from the result register for A/D channel 5.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>OVERRUN6</name>
+ <description>This bit mirrors the OVERRRUN status flag from the result register for A/D channel 6.</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>OVERRUN7</name>
+ <description>This bit mirrors the OVERRRUN status flag from the result register for A/D channel 7.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>ADINT</name>
+ <description>This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register.</description>
+ <bitRange>[16:16]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:17]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TRM</name>
+ <description>ADC trim register.</description>
+ <addressOffset>0x034</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[3:0]</bitRange>
+ </field>
+ <field>
+ <name>ADCOFFS</name>
+ <description>Offset trim bits for ADC operation. Initialized by the boot code. Can be overwritten by the user.</description>
+ <bitRange>[7:4]</bitRange>
+ </field>
+ <field>
+ <name>TRIM</name>
+ <description>written-to by boot code. Can not be overwritten by the user. These bits are locked after boot code write.</description>
+ <bitRange>[11:8]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:12]</bitRange>
+ </field>
+ </fields>
+ </register>
+ </registers>
+</peripheral>
+
+
+
+ <peripheral>
+ <name>CANAFRAM</name>
+ <description>CAN acceptance filter RAM</description>
+ <baseAddress>0x40038000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0xFFF</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <registers>
+ <register>
+ <dim>512</dim>
+ <dimIncrement>0x4</dimIncrement>
+ <dimIndex>0-511</dimIndex>
+ <name>MASK[%s]</name>
+
+ <displayName>MASK[%s]</displayName>
+ <description>CAN AF ram access register</description>
+ <addressOffset>0x000</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>MASK</name>
+ <description>CAN AF RAM mask</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+
+ <peripheral>
+ <name>CANAF</name>
+ <description> CAN controller acceptance filter </description>
+ <groupName>CANAF</groupName>
+ <baseAddress>0x4003C000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0xFFF</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <registers>
+ <register>
+ <name>AFMR</name>
+ <description>Acceptance Filter Register</description>
+ <addressOffset>0x000</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>ACCOFF</name>
+ <description>if AccBP is 0, the Acceptance Filter is not operational. All Rx messages on all CAN buses are ignored.</description>
+ <bitRange>[0:0]</bitRange>
+
+ </field>
+ <field>
+ <name>ACCBP</name>
+ <description>All Rx messages are accepted on enabled CAN controllers. Software must set this bit before modifying the contents of any of the registers described below, and before modifying the contents of Lookup Table RAM in any way other than setting or clearing Disable bits in Standard Identifier entries. When both this bit and AccOff are 0, the Acceptance filter operates to screen received CAN Identifiers.</description>
+ <bitRange>[1:1]</bitRange>
+
+ </field>
+ <field>
+ <name>EFCAN</name>
+ <description>FullCAN mode</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>SOFTWARE_MUST_READ_A</name>
+ <description>Software must read all messages for all enabled IDs on all enabled CAN buses, from the receiving CAN controllers.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>THE_ACCEPTANCE_FILTE</name>
+ <description>The Acceptance Filter itself will take care of receiving and storing messages for selected Standard ID values on selected CAN buses. See Section 21.16 FullCAN mode on page 576.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:3]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SFF_SA</name>
+ <description>Standard Frame Individual Start Address Register</description>
+ <addressOffset>0x004</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[1:0]</bitRange>
+ </field>
+ <field>
+ <name>SFF_SA</name>
+ <description>The start address of the table of individual Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the SFF_GRP_sa register described below. For compatibility with possible future devices, write zeroes in bits 31:11 and 1:0 of this register. If the eFCAN bit in the AFMR is 1, this value also indicates the size of the table of Standard IDs which the Acceptance Filter will search and (if found) automatically store received messages in Acceptance Filter RAM.</description>
+ <bitRange>[10:2]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:11]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SFF_GRP_SA</name>
+ <description>Standard Frame Group Start Address Register</description>
+ <addressOffset>0x008</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[1:0]</bitRange>
+ </field>
+ <field>
+ <name>SFF_GRP_SA</name>
+ <description>The start address of the table of grouped Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_sa register described below. The largest value that should be written to this register is 0x800, when only the Standard Individual table is used, and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register.</description>
+ <bitRange>[11:2]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:12]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>EFF_SA</name>
+ <description>Extended Frame Start Address Register</description>
+ <addressOffset>0x00C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[1:0]</bitRange>
+ </field>
+ <field>
+ <name>EFF_SA</name>
+ <description>The start address of the table of individual Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_GRP_sa register described below. The largest value that should be written to this register is 0x800, when both Extended Tables are empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:11 and 1:0 of this register.</description>
+ <bitRange>[10:2]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:11]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>EFF_GRP_SA</name>
+ <description>Extended Frame Group Start Address Register</description>
+ <addressOffset>0x010</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[1:0]</bitRange>
+ </field>
+ <field>
+ <name>EFF_GRP_SA</name>
+ <description>The start address of the table of grouped Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the ENDofTable register described below. The largest value that should be written to this register is 0x800, when this table is empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register.</description>
+ <bitRange>[11:2]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:12]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ENDOFTABLE</name>
+ <description>End of AF Tables register</description>
+ <addressOffset>0x014</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[1:0]</bitRange>
+ </field>
+ <field>
+ <name>ENDOFTABLE</name>
+ <description>The address above the last active address in the last active AF table. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register. If the eFCAN bit in the AFMR is 0, the largest value that should be written to this register is 0x800, which allows the last word (address 0x7FC) in AF Lookup Table RAM to be used. If the eFCAN bit in the AFMR is 1, this value marks the start of the area of Acceptance Filter RAM, into which the Acceptance Filter will automatically receive messages for selected IDs on selected CAN buses. In this case, the maximum value that should be written to this register is 0x800 minus 6 times the value in SFF_sa. This allows 12 bytes of message storage between this address and the end of Acceptance Filter RAM, for each Standard ID that is specified between the start of Acceptance Filter RAM, and the next active AF table.</description>
+ <bitRange>[11:2]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:12]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>LUTERRAD</name>
+ <description>LUT Error Address register</description>
+ <addressOffset>0x018</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[1:0]</bitRange>
+ </field>
+ <field>
+ <name>LUTERRAD</name>
+ <description>It the LUT Error bit (below) is 1, this read-only field contains the address in AF Lookup Table RAM, at which the Acceptance Filter encountered an error in the content of the tables.</description>
+ <bitRange>[10:2]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:11]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>LUTERR</name>
+ <description>LUT Error Register</description>
+ <addressOffset>0x01C</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>LUTERR</name>
+ <description>This read-only bit is set to 1 if the Acceptance Filter encounters an error in the content of the tables in AF RAM. It is cleared when software reads the LUTerrAd register. This condition is ORed with the other CAN interrupts from the CAN controllers, to produce the request that is connected to the NVIC.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, the value read from a reserved bit is not defined.</description>
+ <bitRange>[31:1]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FCANIE</name>
+ <description>FullCAN interrupt enable register</description>
+ <addressOffset>0x020</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>FCANIE</name>
+ <description>Global FullCAN Interrupt Enable. When 1, this interrupt is enabled.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:1]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FCANIC0</name>
+ <description>FullCAN interrupt and capture register0</description>
+ <addressOffset>0x024</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>INTPND</name>
+ <description>FullCan Interrupt Pending 0 = FullCan Interrupt Pending bit 0. 1 = FullCan Interrupt Pending bit 1. ... 31 = FullCan Interrupt Pending bit 31.</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FCANIC1</name>
+ <description>FullCAN interrupt and capture register1</description>
+ <addressOffset>0x028</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>IntPnd32</name>
+ <description>FullCan Interrupt Pending bit 32. 0 = FullCan Interrupt Pending bit 32. 1 = FullCan Interrupt Pending bit 33. ... 31 = FullCan Interrupt Pending bit 63.</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>CCAN</name>
+ <description>Central CAN controller </description>
+ <groupName>CCAN</groupName>
+ <baseAddress>0x40040000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0xFFF</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>CANActivity</name>
+ <value>34</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>TXSR</name>
+ <description>CAN Central Transmit Status Register</description>
+ <addressOffset>0x000</addressOffset>
+ <access>read-only</access>
+ <resetValue>0x00030300</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>TS1</name>
+ <description>When 1, the CAN controller 1 is sending a message (same as TS in the CAN1GSR).</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>TS2</name>
+ <description>When 1, the CAN controller 2 is sending a message (same as TS in the CAN2GSR)</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, the value read from a reserved bit is not defined.</description>
+ <bitRange>[7:2]</bitRange>
+ </field>
+ <field>
+ <name>TBS1</name>
+ <description>When 1, all 3 Tx Buffers of the CAN1 controller are available to the CPU (same as TBS in CAN1GSR).</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>TBS2</name>
+ <description>When 1, all 3 Tx Buffers of the CAN2 controller are available to the CPU (same as TBS in CAN2GSR).</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, the value read from a reserved bit is not defined.</description>
+ <bitRange>[15:10]</bitRange>
+ </field>
+ <field>
+ <name>TCS1</name>
+ <description>When 1, all requested transmissions have been completed successfully by the CAN1 controller (same as TCS in CAN1GSR).</description>
+ <bitRange>[16:16]</bitRange>
+ </field>
+ <field>
+ <name>TCS2</name>
+ <description>When 1, all requested transmissions have been completed successfully by the CAN2 controller (same as TCS in CAN2GSR).</description>
+ <bitRange>[17:17]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, the value read from a reserved bit is not defined.</description>
+ <bitRange>[31:18]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RXSR</name>
+ <description>CAN Central Receive Status Register</description>
+ <addressOffset>0x004</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RS1</name>
+ <description>When 1, CAN1 is receiving a message (same as RS in CAN1GSR).</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>RS2</name>
+ <description>When 1, CAN2 is receiving a message (same as RS in CAN2GSR).</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, the value read from a reserved bit is not defined.</description>
+ <bitRange>[7:2]</bitRange>
+ </field>
+ <field>
+ <name>RB1</name>
+ <description>When 1, a received message is available in the CAN1 controller (same as RBS in CAN1GSR).</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>RB2</name>
+ <description>When 1, a received message is available in the CAN2 controller (same as RBS in CAN2GSR).</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, the value read from a reserved bit is not defined.</description>
+ <bitRange>[15:10]</bitRange>
+ </field>
+ <field>
+ <name>DOS1</name>
+ <description>When 1, a message was lost because the preceding message to CAN1 controller was not read out quickly enough (same as DOS in CAN1GSR).</description>
+ <bitRange>[16:16]</bitRange>
+ </field>
+ <field>
+ <name>DOS2</name>
+ <description>When 1, a message was lost because the preceding message to CAN2 controller was not read out quickly enough (same as DOS in CAN2GSR).</description>
+ <bitRange>[17:17]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, the value read from a reserved bit is not defined.</description>
+ <bitRange>[31:18]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>MSR</name>
+ <description>CAN Central Miscellaneous Register</description>
+ <addressOffset>0x008</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>E1</name>
+ <description>When 1, one or both of the CAN1 Tx and Rx Error Counters has reached the limit set in the CAN1EWL register (same as ES in CAN1GSR)</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>E2</name>
+ <description>When 1, one or both of the CAN2 Tx and Rx Error Counters has reached the limit set in the CAN2EWL register (same as ES in CAN2GSR)</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, the value read from a reserved bit is not defined.</description>
+ <bitRange>[7:2]</bitRange>
+ </field>
+ <field>
+ <name>BS1</name>
+ <description>When 1, the CAN1 controller is currently involved in bus activities (same as BS in CAN1GSR).</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>BS2</name>
+ <description>When 1, the CAN2 controller is currently involved in bus activities (same as BS in CAN2GSR).</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, the value read from a reserved bit is not defined.</description>
+ <bitRange>[31:10]</bitRange>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>CAN1</name>
+ <description>CAN1 controller </description>
+ <groupName>CAN</groupName>
+ <baseAddress>0x40044000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0xFFF</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>CAN</name>
+ <value>25</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>MOD</name>
+ <description>Controls the operating mode of the CAN Controller.</description>
+ <addressOffset>0x000</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>RM</name>
+ <description>Reset Mode.</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>NORMAL_THE_CAN_CONTR</name>
+ <description>Normal.The CAN Controller is in the Operating Mode, and certain registers can not be written.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESET_CAN_OPERATION</name>
+ <description>Reset. CAN operation is disabled, writable registers can be written and the current transmission/reception of a message is aborted.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>LOM</name>
+ <description>Listen Only Mode.</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>NORMAL_THE_CAN_CONT</name>
+ <description>Normal. The CAN controller acknowledges a successfully received message on the CAN bus. The error counters are stopped at the current value.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>LISTEN_ONLY_THE_CON</name>
+ <description>Listen only. The controller gives no acknowledgment, even if a message is successfully received. Messages cannot be sent, and the controller operates in error passive mode. This mode is intended for software bit rate detection and hot plugging.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>STM</name>
+ <description>Self Test Mode.</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>NORMAL_A_TRANSMITTE</name>
+ <description>Normal. A transmitted message must be acknowledged to be considered successful.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SELF_TEST_THE_CONTR</name>
+ <description>Self test. The controller will consider a Tx message successful even if there is no acknowledgment received. In this mode a full node test is possible without any other active node on the bus using the SRR bit in CANxCMR.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TPM</name>
+ <description>Transmit Priority Mode.</description>
+ <bitRange>[3:3]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>CAN_ID_THE_TRANSMIT</name>
+ <description>CAN ID. The transmit priority for 3 Transmit Buffers depends on the CAN Identifier.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>LOCAL_PRIORITY_THE_</name>
+ <description>Local priority. The transmit priority for 3 Transmit Buffers depends on the contents of the Tx Priority register within the Transmit Buffer.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>SM</name>
+ <description>Sleep Mode.</description>
+ <bitRange>[4:4]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>WAKE_UP_NORMAL_OPER</name>
+ <description>Wake-up. Normal operation.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SLEEP_THE_CAN_CONTR</name>
+ <description>Sleep. The CAN controller enters Sleep Mode if no CAN interrupt is pending and there is no bus activity. See the Sleep Mode description Section 21.8.2 on page 565.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RPM</name>
+ <description>Receive Polarity Mode.</description>
+ <bitRange>[5:5]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>LOW_ACTIVE_RD_INPUT</name>
+ <description>Low active. RD input is active Low (dominant bit = 0).</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>HIGH_ACTIVE_RD_INPU</name>
+ <description>High active. RD input is active High (dominant bit = 1) -- reverse polarity.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[6:6]</bitRange>
+
+ </field>
+ <field>
+ <name>TM</name>
+ <description>Test Mode.</description>
+ <bitRange>[7:7]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLED_NORMAL_OPE</name>
+ <description>Disabled. Normal operation.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLED_THE_TD_PIN_</name>
+ <description>Enabled. The TD pin will reflect the bit, detected on RD pin, with the next positive edge of the system clock.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:8]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CMR</name>
+ <description>Command bits that affect the state of the CAN Controller</description>
+ <addressOffset>0x004</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>TR</name>
+ <description>Transmission Request.</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>ABSENT_NO_TRANSMISSI</name>
+ <description>Absent.No transmission request.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PRESENT_THE_MESSAGE</name>
+ <description>Present. The message, previously written to the CANxTFI, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer. If at two or all three of STB1, STB2 and STB3 bits are selected when TR=1 is written, Transmit Buffer will be selected based on the chosen priority scheme (for details see Section 21.5.3 Transmit Buffers (TXB))</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>AT</name>
+ <description>Abort Transmission.</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>NO_ACTION_DO_NOT_AB</name>
+ <description>No action. Do not abort the transmission.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PRESENT_IF_NOT_ALRE</name>
+ <description>Present. if not already in progress, a pending Transmission Request for the selected Transmit Buffer is cancelled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RRB</name>
+ <description>Release Receive Buffer.</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>NO_ACTION_DO_NOT_RE</name>
+ <description>No action. Do not release the receive buffer.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RELEASED_THE_INFORM</name>
+ <description>Released. The information in the Receive Buffer (consisting of CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers) is released, and becomes eligible for replacement by the next received frame. If the next received frame is not available, writing this command clears the RBS bit in the Status Register(s).</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CDO</name>
+ <description>Clear Data Overrun.</description>
+ <bitRange>[3:3]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>NO_ACTION_DO_NOT_CL</name>
+ <description>No action. Do not clear the data overrun bit.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CLEAR_THE_DATA_OVER</name>
+ <description>Clear. The Data Overrun bit in Status Register(s) is cleared.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>SRR</name>
+ <description>Self Reception Request.</description>
+ <bitRange>[4:4]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>ABSENT_NO_SELF_RECE</name>
+ <description>Absent. No self reception request.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PRESENT_THE_MESSAGE</name>
+ <description>Present. The message, previously written to the CANxTFS, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer and received simultaneously. This differs from the TR bit above in that the receiver is not disabled during the transmission, so that it receives the message if its Identifier is recognized by the Acceptance Filter.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>STB1</name>
+ <description>Select Tx Buffer 1.</description>
+ <bitRange>[5:5]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>NOT_SELECTED_TX_BUF</name>
+ <description>Not selected. Tx Buffer 1 is not selected for transmission.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SELECTED_TX_BUFFER_</name>
+ <description>Selected. Tx Buffer 1 is selected for transmission.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>STB2</name>
+ <description>Select Tx Buffer 2.</description>
+ <bitRange>[6:6]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>NOT_SELECTED_TX_BUF</name>
+ <description>Not selected. Tx Buffer 2 is not selected for transmission.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SELECTED_TX_BUFFER_</name>
+ <description>Selected. Tx Buffer 2 is selected for transmission.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>STB3</name>
+ <description>Select Tx Buffer 3.</description>
+ <bitRange>[7:7]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>NOT_SELECTED_TX_BUF</name>
+ <description>Not selected. Tx Buffer 3 is not selected for transmission.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SELECTED_TX_BUFFER_</name>
+ <description>Selected. Tx Buffer 3 is selected for transmission.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:8]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>GSR</name>
+ <description>Global Controller Status and Error Counters. The error counters can only be written when RM in CANMOD is 1.</description>
+ <addressOffset>0x008</addressOffset>
+ <access>read-only</access>
+ <resetValue>0x3C</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RBS</name>
+ <description>Receive Buffer Status. After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared.</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>EMPTY_NO_MESSAGE_IS</name>
+ <description>Empty. No message is available.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>FULL_AT_LEAST_ONE_C</name>
+ <description>Full. At least one complete message is received by the Double Receive Buffer and available in the CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers. This bit is cleared by the Release Receive Buffer command in CANxCMR, if no subsequent received message is available.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>DOS</name>
+ <description>Data Overrun Status. If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled.</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>ABSENT_NO_DATA_OVER</name>
+ <description>Absent. No data overrun has occurred since the last Clear Data Overrun command was given/written to CANxCMR (or since Reset).</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OVERRUN_A_MESSAGE_W</name>
+ <description>Overrun. A message was lost because the preceding message to this CAN controller was not read and released quickly enough (there was not enough space for a new message in the Double Receive Buffer).</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TBS</name>
+ <description>Transmit Buffer Status.</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>LOCKED_AT_LEAST_ONE</name>
+ <description>Locked. At least one of the Transmit Buffers is not available for the CPU, i.e. at least one previously queued message for this CAN controller has not yet been sent, and therefore software should not write to the CANxTFI, CANxTID, CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s).</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RELEASED_ALL_THREE_</name>
+ <description>Released. All three Transmit Buffers are available for the CPU. No transmit message is pending for this CAN controller (in any of the 3 Tx buffers), and software may write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB registers.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TCS</name>
+ <description>Transmit Complete Status. The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are transmitted successfully.</description>
+ <bitRange>[3:3]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>INCOMPLETE_AT_LEAST</name>
+ <description>Incomplete. At least one requested transmission has not been successfully completed yet.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>COMPLETE_ALL_REQUES</name>
+ <description>Complete. All requested transmission(s) has (have) been successfully completed.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RS</name>
+ <description>Receive Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits.</description>
+ <bitRange>[4:4]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>IDLE_THE_CAN_CONTRO</name>
+ <description>Idle. The CAN controller is idle.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RECEIVE_THE_CAN_CON</name>
+ <description>Receive. The CAN controller is receiving a message.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TS</name>
+ <description>Transmit Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits.</description>
+ <bitRange>[5:5]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>IDLE_THE_CAN_CONTRO</name>
+ <description>Idle. The CAN controller is idle.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>TRANSMIT_THE_CAN_CO</name>
+ <description>Transmit. The CAN controller is sending a message.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>ES</name>
+ <description>Error Status. Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018).</description>
+ <bitRange>[6:6]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>OK_BOTH_ERROR_COUNT</name>
+ <description>OK. Both error counters are below the Error Warning Limit.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ERROR_ONE_OR_BOTH_O</name>
+ <description>Error. One or both of the Transmit and Receive Error Counters has reached the limit set in the Error Warning Limit register.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>BS</name>
+ <description>Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', and the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery.</description>
+ <bitRange>[7:7]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>BUS_ON_THE_CAN_CONT</name>
+ <description>Bus-on. The CAN Controller is involved in bus activities</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>BUS_OFF_THE_CAN_CON</name>
+ <description>Bus-off. The CAN controller is currently not involved/prohibited from bus activity because the Transmit Error Counter reached its limiting value of 255.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[15:8]</bitRange>
+
+ </field>
+ <field>
+ <name>RXERR</name>
+ <description>The current value of the Rx Error Counter (an 8-bit value).</description>
+ <bitRange>[23:16]</bitRange>
+
+ </field>
+ <field>
+ <name>TXERR</name>
+ <description>The current value of the Tx Error Counter (an 8-bit value).</description>
+ <bitRange>[31:24]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ICR</name>
+ <description>Interrupt status, Arbitration Lost Capture, Error Code Capture</description>
+ <addressOffset>0x00C</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RI</name>
+ <description>Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE bit in CANxIER are both 1, indicating that a new message was received and stored in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command Release Receive Buffer will clear RI temporarily. If there is another message available within the Receive Buffer after the release command, RI is set again. Otherwise RI remains cleared.</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>RESET</name>
+ <description>Reset</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SET</name>
+ <description>Set</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TI1</name>
+ <description>Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB1 was successfully transmitted or aborted), indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1.</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>RESET</name>
+ <description>Reset</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SET</name>
+ <description>Set</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>EI</name>
+ <description>Error Warning Interrupt. This bit is set on every change (set or clear) of either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set within the Interrupt Enable Register at the time of the change.</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>RESET</name>
+ <description>Reset</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SET</name>
+ <description>Set</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>DOI</name>
+ <description>Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 to 1 and the DOIE bit in CANxIER is 1.</description>
+ <bitRange>[3:3]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>RESET</name>
+ <description>Reset</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SET</name>
+ <description>Set</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>WUI</name>
+ <description>Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted.</description>
+ <bitRange>[4:4]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>RESET</name>
+ <description>Reset</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SET</name>
+ <description>Set</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>EPI</name>
+ <description>Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the CAN controller switches between Error Passive and Error Active mode in either direction. This is the case when the CAN Controller has reached the Error Passive Status (at least one error counter exceeds the CAN protocol defined level of 127) or if the CAN Controller is in Error Passive Status and enters the Error Active Status again.</description>
+ <bitRange>[5:5]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>RESET</name>
+ <description>Reset</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SET</name>
+ <description>Set</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>ALI</name>
+ <description>Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the CAN controller loses arbitration while attempting to transmit. In this case the CAN node becomes a receiver.</description>
+ <bitRange>[6:6]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>RESET</name>
+ <description>Reset</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SET</name>
+ <description>Set</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>BEI</name>
+ <description>Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN controller detects an error on the bus.</description>
+ <bitRange>[7:7]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>RESET</name>
+ <description>Reset</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SET</name>
+ <description>Set</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>IDI</name>
+ <description>ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN Identifier has been received (a message was successfully transmitted or aborted). This bit is set whenever a message was successfully transmitted or aborted and the IDIE bit is set in the IER register.</description>
+ <bitRange>[8:8]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>RESET</name>
+ <description>Reset</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SET</name>
+ <description>Set</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TI2</name>
+ <description>Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB2 was successfully transmitted or aborted), indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1.</description>
+ <bitRange>[9:9]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>RESET</name>
+ <description>Reset</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SET</name>
+ <description>Set</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TI3</name>
+ <description>Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB3 was successfully transmitted or aborted), indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1.</description>
+ <bitRange>[10:10]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>RESET</name>
+ <description>Reset</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SET</name>
+ <description>Set</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. The value read from a reserved bit is not defined.</description>
+ <bitRange>[15:11]</bitRange>
+
+ </field>
+ <field>
+ <name>ERRBIT4_0</name>
+ <description>Error Code Capture: when the CAN controller detects a bus error, the location of the error within the frame is captured in this field. The value reflects an internal state variable, and as a result is not very linear: 00011 = Start of Frame 00010 = ID28 ... ID21 00110 = ID20 ... ID18 00100 = SRTR Bit 00101 = IDE bit 00111 = ID17 ... 13 01111 = ID12 ... ID5 01110 = ID4 ... ID0 01100 = RTR Bit 01101 = Reserved Bit 1 01001 = Reserved Bit 0 01011 = Data Length Code 01010 = Data Field 01000 = CRC Sequence 11000 = CRC Delimiter 11001 = Acknowledge Slot 11011 = Acknowledge Delimiter 11010 = End of Frame 10010 = Intermission Whenever a bus error occurs, the corresponding bus error interrupt is forced, if enabled. At the same time, the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The content within this register is fixed until the user software has read out its content once. From now on, the capture mechanism is activated again, i.e. reading the CANxICR enables another Bus Error Interrupt.</description>
+ <bitRange>[20:16]</bitRange>
+
+ </field>
+ <field>
+ <name>ERRDIR</name>
+ <description>When the CAN controller detects a bus error, the direction of the current bit is captured in this bit.</description>
+ <bitRange>[21:21]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>ERROR_OCCURRED_DURIN</name>
+ <description>Error occurred during transmitting.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ERROR_OCCURRED_DURIN</name>
+ <description>Error occurred during receiving.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>ERRC1_0</name>
+ <description>When the CAN controller detects a bus error, the type of error is captured in this field:</description>
+ <bitRange>[23:22]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>BIT_ERROR</name>
+ <description>Bit error</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>FORM_ERROR</name>
+ <description>Form error</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>STUFF_ERROR</name>
+ <description>Stuff error</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OTHER_ERROR</name>
+ <description>Other error</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>ALCBIT</name>
+ <description>Each time arbitration is lost while trying to send on the CAN, the bit number within the frame is captured into this field. After the content of ALCBIT is read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 = arbitration lost in the first bit (MS) of identifier ... 11 = arbitration lost in SRTS bit (RTR bit for standard frame messages) 12 = arbitration lost in IDE bit 13 = arbitration lost in 12th bit of identifier (extended frame only) ... 30 = arbitration lost in last bit of identifier (extended frame only) 31 = arbitration lost in RTR bit (extended frame only) On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At that time, the current bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content within this register is fixed until the user application has read out its contents once. From now on, the capture mechanism is activated again.</description>
+ <bitRange>[31:24]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IER</name>
+ <description>Interrupt Enable</description>
+ <addressOffset>0x010</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RIE</name>
+ <description>Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller requests the respective interrupt.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>TIE1</name>
+ <description>Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>EIE</name>
+ <description>Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the CAN Controller requests the respective interrupt.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>DOIE</name>
+ <description>Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the CAN Controller requests the respective interrupt.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>WUIE</name>
+ <description>Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt is requested.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>EPIE</name>
+ <description>Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error active to error passive or vice versa, the respective interrupt is requested.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>ALIE</name>
+ <description>Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective interrupt is requested.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>BEIE</name>
+ <description>Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the respective interrupt.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>IDIE</name>
+ <description>ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller requests the respective interrupt.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>TIE2</name>
+ <description>Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>TIE3</name>
+ <description>Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:11]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BTR</name>
+ <description>Bus Timing. Can only be written when RM in CANMOD is 1.</description>
+ <addressOffset>0x014</addressOffset>
+ <access>read-write</access>
+ <resetValue>0x1C0000</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>BRP</name>
+ <description>Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the CAN clock.</description>
+ <bitRange>[9:0]</bitRange>
+
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[13:10]</bitRange>
+
+ </field>
+ <field>
+ <name>SJW</name>
+ <description>The Synchronization Jump Width is (this value plus one) CAN clocks.</description>
+ <bitRange>[15:14]</bitRange>
+
+ </field>
+ <field>
+ <name>TESG1</name>
+ <description>The delay from the nominal Sync point to the sample point is (this value plus one) CAN clocks.</description>
+ <bitRange>[19:16]</bitRange>
+
+ </field>
+ <field>
+ <name>TESG2</name>
+ <description>The delay from the sample point to the next nominal sync point is (this value plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3) CAN clocks.</description>
+ <bitRange>[22:20]</bitRange>
+
+ </field>
+ <field>
+ <name>SAM</name>
+ <description>Sampling</description>
+ <bitRange>[23:23]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>THE_BUS_IS_SAMPLED_O</name>
+ <description>The bus is sampled once (recommended for high speed buses)</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>THE_BUS_IS_SAMPLED_3</name>
+ <description>The bus is sampled 3 times (recommended for low to medium speed buses to filter spikes on the bus-line)</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:24]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>EWL</name>
+ <description>Error Warning Limit. Can only be written when RM in CANMOD is 1.</description>
+ <addressOffset>0x018</addressOffset>
+ <access>read-write</access>
+ <resetValue>0x60</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>EWL</name>
+ <description>During CAN operation, this value is compared to both the Tx and Rx Error Counters. If either of these counter matches this value, the Error Status (ES) bit in CANSR is set.</description>
+ <bitRange>[7:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SR</name>
+ <description>Status Register</description>
+ <addressOffset>0x01C</addressOffset>
+ <access>read-only</access>
+ <resetValue>0x3C3C3C</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RBS_1</name>
+ <description>Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR.</description>
+ <bitRange>[0:0]</bitRange>
+
+ </field>
+ <field>
+ <name>DOS_1</name>
+ <description>Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR.</description>
+ <bitRange>[1:1]</bitRange>
+
+ </field>
+ <field>
+ <name>TBS1_1</name>
+ <description>Transmit Buffer Status 1.</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>LOCKED_SOFTWARE_CAN</name>
+ <description>Locked. Software cannot access the Tx Buffer 1 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RELEASED_SOFTWARE_M</name>
+ <description>Released. Software may write a message into the Transmit Buffer 1 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TCS1_1</name>
+ <description>Transmission Complete Status.</description>
+ <bitRange>[3:3]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>INCOMPLETE_THE_PREV</name>
+ <description>Incomplete. The previously requested transmission for Tx Buffer 1 is not complete.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>COMPLETE_THE_PREVIO</name>
+ <description>Complete. The previously requested transmission for Tx Buffer 1 has been successfully completed.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RS_1</name>
+ <description>Receive Status. This bit is identical to the RS bit in the GSR.</description>
+ <bitRange>[4:4]</bitRange>
+
+ </field>
+ <field>
+ <name>TS1_1</name>
+ <description>Transmit Status 1.</description>
+ <bitRange>[5:5]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>IDLE_THERE_IS_NO_TR</name>
+ <description>Idle. There is no transmission from Tx Buffer 1.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>TRANSMIT_THE_CAN_CO</name>
+ <description>Transmit. The CAN Controller is transmitting a message from Tx Buffer 1.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>ES_1</name>
+ <description>Error Status. This bit is identical to the ES bit in the CANxGSR.</description>
+ <bitRange>[6:6]</bitRange>
+
+ </field>
+ <field>
+ <name>BS_1</name>
+ <description>Bus Status. This bit is identical to the BS bit in the CANxGSR.</description>
+ <bitRange>[7:7]</bitRange>
+
+ </field>
+ <field>
+ <name>RBS_2</name>
+ <description>Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR.</description>
+ <bitRange>[8:8]</bitRange>
+
+ </field>
+ <field>
+ <name>DOS_2</name>
+ <description>Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR.</description>
+ <bitRange>[9:9]</bitRange>
+
+ </field>
+ <field>
+ <name>TBS2_2</name>
+ <description>Transmit Buffer Status 2.</description>
+ <bitRange>[10:10]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>LOCKED_SOFTWARE_CAN</name>
+ <description>Locked. Software cannot access the Tx Buffer 2 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RELEASED_SOFTWARE_M</name>
+ <description>Released. Software may write a message into the Transmit Buffer 2 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TCS2_2</name>
+ <description>Transmission Complete Status.</description>
+ <bitRange>[11:11]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>INCOMPLETE_THE_PREV</name>
+ <description>Incomplete. The previously requested transmission for Tx Buffer 2 is not complete.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>COMPLETE_THE_PREVIO</name>
+ <description>Complete. The previously requested transmission for Tx Buffer 2 has been successfully completed.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RS_2</name>
+ <description>Receive Status. This bit is identical to the RS bit in the GSR.</description>
+ <bitRange>[12:12]</bitRange>
+
+ </field>
+ <field>
+ <name>TS2_2</name>
+ <description>Transmit Status 2.</description>
+ <bitRange>[13:13]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>IDLE_THERE_IS_NO_TR</name>
+ <description>Idle. There is no transmission from Tx Buffer 2.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>TRANSMIT_THE_CAN_CO</name>
+ <description>Transmit. The CAN Controller is transmitting a message from Tx Buffer 2.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>ES_2</name>
+ <description>Error Status. This bit is identical to the ES bit in the CANxGSR.</description>
+ <bitRange>[14:14]</bitRange>
+
+ </field>
+ <field>
+ <name>BS_2</name>
+ <description>Bus Status. This bit is identical to the BS bit in the CANxGSR.</description>
+ <bitRange>[15:15]</bitRange>
+
+ </field>
+ <field>
+ <name>RBS_3</name>
+ <description>Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR.</description>
+ <bitRange>[16:16]</bitRange>
+
+ </field>
+ <field>
+ <name>DOS_3</name>
+ <description>Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR.</description>
+ <bitRange>[17:17]</bitRange>
+
+ </field>
+ <field>
+ <name>TBS3_3</name>
+ <description>Transmit Buffer Status 3.</description>
+ <bitRange>[18:18]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>LOCKED_SOFTWARE_CAN</name>
+ <description>Locked. Software cannot access the Tx Buffer 3 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RELEASED_SOFTWARE_M</name>
+ <description>Released. Software may write a message into the Transmit Buffer 3 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TCS3_3</name>
+ <description>Transmission Complete Status.</description>
+ <bitRange>[19:19]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>INCOMPLETE_THE_PREV</name>
+ <description>Incomplete. The previously requested transmission for Tx Buffer 3 is not complete.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>COMPLETE_THE_PREVIO</name>
+ <description>Complete. The previously requested transmission for Tx Buffer 3 has been successfully completed.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RS_3</name>
+ <description>Receive Status. This bit is identical to the RS bit in the GSR.</description>
+ <bitRange>[20:20]</bitRange>
+
+ </field>
+ <field>
+ <name>TS3_3</name>
+ <description>Transmit Status 3.</description>
+ <bitRange>[21:21]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>IDLE_THERE_IS_NO_TR</name>
+ <description>Idle. There is no transmission from Tx Buffer 3.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>TRANSMIT_THE_CAN_CO</name>
+ <description>Transmit. The CAN Controller is transmitting a message from Tx Buffer 3.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>ES_3</name>
+ <description>Error Status. This bit is identical to the ES bit in the CANxGSR.</description>
+ <bitRange>[22:22]</bitRange>
+
+ </field>
+ <field>
+ <name>BS_3</name>
+ <description>Bus Status. This bit is identical to the BS bit in the CANxGSR.</description>
+ <bitRange>[23:23]</bitRange>
+
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, the value read from a reserved bit is not defined.</description>
+ <bitRange>[31:24]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RFS</name>
+ <description>Receive frame status. Can only be written when RM in CANMOD is 1.</description>
+ <addressOffset>0x020</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>IDINDEX</name>
+ <description>ID Index. If the BP bit (below) is 0, this value is the zero-based number of the Lookup Table RAM entry at which the Acceptance Filter matched the received Identifier. Disabled entries in the Standard tables are included in this numbering, but will not be matched. See Section 21.17 Examples of acceptance filter tables and ID index values on page 587 for examples of ID Index values.</description>
+ <bitRange>[9:0]</bitRange>
+ </field>
+ <field>
+ <name>BP</name>
+ <description>If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field (above) is meaningless.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. The value read from a reserved bit is not defined.</description>
+ <bitRange>[15:11]</bitRange>
+ </field>
+ <field>
+ <name>DLC</name>
+ <description>The field contains the Data Length Code (DLC) field of the current received message. When RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding.</description>
+ <bitRange>[19:16]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[29:20]</bitRange>
+ </field>
+ <field>
+ <name>RTR</name>
+ <description>This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier.</description>
+ <bitRange>[30:30]</bitRange>
+ </field>
+ <field>
+ <name>FF</name>
+ <description>A 0 in this bit indicates that the current received message included an 11-bit Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below.</description>
+ <bitRange>[31:31]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RID</name>
+ <description>Received Identifier. Can only be written when RM in CANMOD is 1.</description>
+ <addressOffset>0x024</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>ID</name>
+ <description>The 11-bit Identifier field of the current received message. In CAN 2.0A, these bits are called ID10-0, while in CAN 2.0B they're called ID29-18.</description>
+ <bitRange>[10:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:11]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RDA</name>
+ <description>Received data bytes 1-4. Can only be written when RM in CANMOD is 1.</description>
+ <addressOffset>0x028</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>DATA1</name>
+ <description>Data 1. If the DLC field in CANRFS >= 0001, this contains the first Data byte of the current received message.</description>
+ <bitRange>[7:0]</bitRange>
+ </field>
+ <field>
+ <name>DATA2</name>
+ <description>Data 2. If the DLC field in CANRFS >= 0010, this contains the first Data byte of the current received message.</description>
+ <bitRange>[15:8]</bitRange>
+ </field>
+ <field>
+ <name>DATA3</name>
+ <description>Data 3. If the DLC field in CANRFS >= 0011, this contains the first Data byte of the current received message.</description>
+ <bitRange>[23:16]</bitRange>
+ </field>
+ <field>
+ <name>DATA4</name>
+ <description>Data 4. If the DLC field in CANRFS >= 0100, this contains the first Data byte of the current received message.</description>
+ <bitRange>[31:24]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RDB</name>
+ <description>Received data bytes 5-8. Can only be written when RM in CANMOD is 1.</description>
+ <addressOffset>0x02C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>DATA5</name>
+ <description>Data 5. If the DLC field in CANRFS >= 0101, this contains the first Data byte of the current received message.</description>
+ <bitRange>[7:0]</bitRange>
+ </field>
+ <field>
+ <name>DATA6</name>
+ <description>Data 6. If the DLC field in CANRFS >= 0110, this contains the first Data byte of the current received message.</description>
+ <bitRange>[15:8]</bitRange>
+ </field>
+ <field>
+ <name>DATA7</name>
+ <description>Data 7. If the DLC field in CANRFS >= 0111, this contains the first Data byte of the current received message.</description>
+ <bitRange>[23:16]</bitRange>
+ </field>
+ <field>
+ <name>DATA8</name>
+ <description>Data 8. If the DLC field in CANRFS >= 1000, this contains the first Data byte of the current received message.</description>
+ <bitRange>[31:24]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <dim>3</dim>
+ <dimIncrement>0x10</dimIncrement>
+ <dimIndex>1-3</dimIndex>
+ <name>TFI%s</name>
+ <description>Transmit
+frame info (Tx Buffer )</description>
+ <addressOffset>0x030</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>PRIO</name>
+ <description>If the TPM (Transmit Priority Mode) bit in the CANxMOD register is set to 1, enabled Tx Buffers contend for the right to send their messages based on this field. The buffer with the lowest TX Priority value wins the prioritization and is sent first.</description>
+ <bitRange>[7:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[15:8]</bitRange>
+ </field>
+ <field>
+ <name>DLC</name>
+ <description>Data Length Code. This value is sent in the DLC field of the next transmit message. In addition, if RTR = 0, this value controls the number of Data bytes sent in the next transmit message, from the CANxTDA and CANxTDB registers: 0000-0111 = 0-7 bytes 1xxx = 8 bytes</description>
+ <bitRange>[19:16]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[29:20]</bitRange>
+ </field>
+ <field>
+ <name>RTR</name>
+ <description>This value is sent in the RTR bit of the next transmit message. If this bit is 0, the number of data bytes called out by the DLC field are sent from the CANxTDA and CANxTDB registers. If this bit is 1, a Remote Frame is sent, containing a request for that number of bytes.</description>
+ <bitRange>[30:30]</bitRange>
+ </field>
+ <field>
+ <name>FF</name>
+ <description>If this bit is 0, the next transmit message will be sent with an 11-bit Identifier (standard frame format), while if it's 1, the message will be sent with a 29-bit Identifier (extended frame format).</description>
+ <bitRange>[31:31]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <dim>3</dim>
+ <dimIncrement>0x10</dimIncrement>
+ <dimIndex>1-3</dimIndex>
+ <name>TID%s</name>
+ <description>Transmit
+Identifier (Tx Buffer)</description>
+ <addressOffset>0x034</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>ID</name>
+ <description>The 11-bit Identifier to be sent in the next transmit message.</description>
+ <bitRange>[10:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:11]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <dim>3</dim>
+ <dimIncrement>0x10</dimIncrement>
+ <dimIndex>1-3</dimIndex>
+ <name>TDA%s</name>
+ <description>Transmit
+data bytes 1-4 (Tx Buffer)</description>
+ <addressOffset>0x038</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>DATA1</name>
+ <description>Data 1. If RTR = 0 and DLC >= 0001 in the corresponding CANxTFI, this byte is sent as the first Data byte of the next transmit message.</description>
+ <bitRange>[7:0]</bitRange>
+ </field>
+ <field>
+ <name>DATA2</name>
+ <description>Data 2. If RTR = 0 and DLC >= 0010 in the corresponding CANxTFI, this byte is sent as the 2nd Data byte of the next transmit message.</description>
+ <bitRange>[15:8]</bitRange>
+ </field>
+ <field>
+ <name>DATA3</name>
+ <description>Data 3. If RTR = 0 and DLC >= 0011 in the corresponding CANxTFI, this byte is sent as the 3rd Data byte of the next transmit message.</description>
+ <bitRange>[23:16]</bitRange>
+ </field>
+ <field>
+ <name>DATA4</name>
+ <description>Data 4. If RTR = 0 and DLC >= 0100 in the corresponding CANxTFI, this byte is sent as the 4th Data byte of the next transmit message.</description>
+ <bitRange>[31:24]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <dim>3</dim>
+ <dimIncrement>0x10</dimIncrement>
+ <dimIndex>1-3</dimIndex>
+ <name>TDB%s</name>
+ <description>Transmit
+data bytes 5-8 (Tx Buffer )</description>
+ <addressOffset>0x03C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>DATA5</name>
+ <description>Data 5. If RTR = 0 and DLC >= 0101 in the corresponding CANTFI, this byte is sent as the 5th Data byte of the next transmit message.</description>
+ <bitRange>[7:0]</bitRange>
+ </field>
+ <field>
+ <name>DATA6</name>
+ <description>Data 6. If RTR = 0 and DLC >= 0110 in the corresponding CANTFI, this byte is sent as the 6th Data byte of the next transmit message.</description>
+ <bitRange>[15:8]</bitRange>
+ </field>
+ <field>
+ <name>DATA7</name>
+ <description>Data 7. If RTR = 0 and DLC >= 0111 in the corresponding CANTFI, this byte is sent as the 7th Data byte of the next transmit message.</description>
+ <bitRange>[23:16]</bitRange>
+ </field>
+ <field>
+ <name>DATA8</name>
+ <description>Data 8. If RTR = 0 and DLC >= 1000 in the corresponding CANTFI, this byte is sent as the 8th Data byte of the next transmit message.</description>
+ <bitRange>[31:24]</bitRange>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral derivedFrom="CAN1">
+ <name>CAN2</name>
+ <baseAddress>0x40048000</baseAddress>
+ <addressBlock>
+ <offset>0</offset>
+ <size>0xFFF</size>
+ <usage>registers</usage>
+ </addressBlock>
+
+ </peripheral>
+ <peripheral derivedFrom="I2C0">
+ <name>I2C1</name>
+ <baseAddress>0x4005C000</baseAddress>
+ <interrupt>
+ <name>I2C1</name>
+ <value>11</value>
+
+ </interrupt>
+ </peripheral>
+
+
+ <peripheral derivedFrom="SSP1">
+ <name>SSP0</name>
+ <description>SSP controller</description>
+ <groupName>SSP</groupName>
+ <baseAddress>0x40088000</baseAddress>
+ <addressBlock>
+ <offset>0</offset>
+ <size>0x300</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>SSP0</name>
+ <value>14</value>
+
+ </interrupt>
+
+ </peripheral>
+ <peripheral>
+ <name>DAC</name>
+ <description> Digital-to-Analog Converter (DAC) </description>
+ <groupName>DAC</groupName>
+ <baseAddress>0x4008C000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0xFFF</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <registers>
+ <register>
+ <name>CR</name>
+ <description>D/A Converter Register. This register contains the digital value to be converted to analog and a power control bit.</description>
+ <addressOffset>0x000</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[5:0]</bitRange>
+
+ </field>
+ <field>
+ <name>VALUE</name>
+ <description>After the selected settling time after this field is written with a new VALUE, the voltage on the DAC_OUT pin (with respect to VSSA) is VALUE x ((VREFP - V REFN)/1024) + VREFN.</description>
+ <bitRange>[15:6]</bitRange>
+
+ </field>
+ <field>
+ <name>BIAS</name>
+ <description>Settling time The settling times noted in the description of the BIAS bit are valid for a capacitance load on the DAC_OUT pin not exceeding 100 pF. A load impedance value greater than that value will cause settling time longer than the specified time. One or more graphs of load impedance vs. settling time will be included in the final data sheet.</description>
+ <bitRange>[16:16]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>FAST</name>
+ <description>The settling time of the DAC is 1 us max, and the maximum current is 700 uA. This allows a maximum update rate of 1 MHz.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SLOW</name>
+ <description>The settling time of the DAC is 2.5 us and the maximum current is 350 uA. This allows a maximum update rate of 400 kHz.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:17]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CTRL</name>
+ <description>DAC Control register. This register controls DMA and timer operation.</description>
+ <addressOffset>0x004</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>INT_DMA_REQ</name>
+ <description>DMA interrupt request</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>CLEAR_ON_ANY_WRITE_T</name>
+ <description>Clear on any write to the DACR register.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SET_BY_HARDWARE_WHEN</name>
+ <description>Set by hardware when the timer times out.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>DBLBUF_ENA</name>
+ <description>Double buffering</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE</name>
+ <description>Disable</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE_WHEN_THIS_BI</name>
+ <description>Enable. When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CNT_ENA</name>
+ <description>Time-out counter operation</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE</name>
+ <description>Disable</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE</name>
+ <description>Enable</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>DMA_ENA</name>
+ <description>DMA access</description>
+ <bitRange>[3:3]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE</name>
+ <description>Disable</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE_DMA_BURST_RE</name>
+ <description>Enable. DMA Burst Request Input 7 is enabled for the DAC (see Table 672).</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:4]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CNTVAL</name>
+ <description>DAC Counter Value register. This register contains the reload value for the DAC DMA/Interrupt timer.</description>
+ <addressOffset>0x008</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>VALUE</name>
+ <description>16-bit reload value for the DAC interrupt/DMA timer.</description>
+ <bitRange>[15:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <bitRange>[31:16]</bitRange>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral derivedFrom="TIMER0">
+ <name>TIMER2</name>
+ <baseAddress>0x40090000</baseAddress>
+ <addressBlock>
+ <offset>0</offset>
+ <size>0xFFF</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>TIMER2</name>
+ <value>3</value>
+ </interrupt>
+ </peripheral>
+
+ <peripheral derivedFrom="TIMER0">
+ <name>TIMER3</name>
+ <baseAddress>0x40094000</baseAddress>
+ <addressBlock>
+ <offset>0</offset>
+ <size>0xFFF</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>TIMER3</name>
+ <value>4</value>
+ </interrupt>
+ </peripheral>
+ <peripheral derivedFrom="UART0">
+ <name>UART2</name>
+ <baseAddress>0x40098000</baseAddress>
+
+ <addressBlock>
+ <offset>0</offset>
+ <size>0xFFF</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>UART2</name>
+ <value>7</value>
+ </interrupt>
+
+ </peripheral>
+ <peripheral derivedFrom="UART0">
+ <name>UART3</name>
+ <baseAddress>0x4009C000</baseAddress>
+ <addressBlock>
+ <offset>0</offset>
+ <size>0xFFF</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>UART3</name>
+ <value>8</value>
+ </interrupt>
+
+ </peripheral>
+ <peripheral derivedFrom="I2C0">
+ <name>I2C2</name>
+ <baseAddress>0x400A0000</baseAddress>
+ <interrupt>
+ <name>I2C2</name>
+ <value>12</value>
+
+ </interrupt>
+ </peripheral>
+
+
+ <peripheral>
+ <name>I2S</name>
+ <description>I2S interface</description>
+ <groupName>I2S</groupName>
+ <baseAddress>0x400A8000</baseAddress>
+ <addressBlock>
+ <offset>0</offset>
+ <size>0xFFF</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>I2S</name>
+ <value>27</value>
+
+ </interrupt>
+ <registers>
+ <register>
+ <name>DAO</name>
+ <description>I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel.</description>
+ <addressOffset>0x000</addressOffset>
+ <access>read-write</access>
+ <resetValue>0x87E1</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>WORDWIDTH</name>
+ <description>Selects the number of bytes in data as follows:</description>
+ <bitRange>[1:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>8_BIT_DATA</name>
+ <description>8-bit data</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>16_BIT_DATA</name>
+ <description>16-bit data</description>
+ <value>0x1</value>
+ </enumeratedValue>
+
+ <enumeratedValue>
+ <name>32_BIT_DATA</name>
+ <description>32-bit data</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>MONO</name>
+ <description>When 1, data is of monaural format. When 0, the data is in stereo format.</description>
+ <bitRange>[2:2]</bitRange>
+
+ </field>
+ <field>
+ <name>STOP</name>
+ <description>When 1, disables accesses on FIFOs, places the transmit channel in mute mode.</description>
+ <bitRange>[3:3]</bitRange>
+
+ </field>
+ <field>
+ <name>RESET</name>
+ <description>When 1, asynchronously resets the transmit channel and FIFO.</description>
+ <bitRange>[4:4]</bitRange>
+
+ </field>
+ <field>
+ <name>WS_SEL</name>
+ <description>When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE.</description>
+ <bitRange>[5:5]</bitRange>
+
+ </field>
+ <field>
+ <name>WS_HALFPERIOD</name>
+ <description>Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31.</description>
+ <bitRange>[14:6]</bitRange>
+
+ </field>
+ <field>
+ <name>MUTE</name>
+ <description>When 1, the transmit channel sends only zeroes.</description>
+ <bitRange>[15:15]</bitRange>
+
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:16]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DAI</name>
+ <description>I2S Digital Audio Input Register. Contains control bits for the I2S receive channel.</description>
+ <addressOffset>0x004</addressOffset>
+ <access>read-write</access>
+ <resetValue>0x07E1</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>WORDWIDTH</name>
+ <description>Selects the number of bytes in data as follows:</description>
+ <bitRange>[1:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>8_BIT_DATA</name>
+ <description>8-bit data</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>16_BIT_DATA</name>
+ <description>16-bit data</description>
+ <value>0x1</value>
+ </enumeratedValue>
+
+ <enumeratedValue>
+ <name>32_BIT_DATA</name>
+ <description>32-bit data</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>MONO</name>
+ <description>When 1, data is of monaural format. When 0, the data is in stereo format.</description>
+ <bitRange>[2:2]</bitRange>
+
+ </field>
+ <field>
+ <name>STOP</name>
+ <description>When 1, disables accesses on FIFOs, places the transmit channel in mute mode.</description>
+ <bitRange>[3:3]</bitRange>
+
+ </field>
+ <field>
+ <name>RESET</name>
+ <description>When 1, asynchronously reset the transmit channel and FIFO.</description>
+ <bitRange>[4:4]</bitRange>
+
+ </field>
+ <field>
+ <name>WS_SEL</name>
+ <description>When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE.</description>
+ <bitRange>[5:5]</bitRange>
+
+ </field>
+ <field>
+ <name>WS_HALFPERIOD</name>
+ <description>Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31.</description>
+ <bitRange>[14:6]</bitRange>
+
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:15]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TXFIFO</name>
+ <description>I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO.</description>
+ <addressOffset>0x008</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>I2STXFIFO</name>
+ <description>8 x 32-bit transmit FIFO.</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RXFIFO</name>
+ <description>I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO.</description>
+ <addressOffset>0x00C</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <readAction>modify</readAction>
+ <fields>
+ <field>
+ <name>I2SRXFIFO</name>
+ <description>8 x 32-bit transmit FIFO.</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>STATE</name>
+ <description>I2S Status Feedback Register. Contains status information about the I2S interface.</description>
+ <addressOffset>0x010</addressOffset>
+ <access>read-only</access>
+ <resetValue>0x7</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>IRQ</name>
+ <description>This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ register.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>DMAREQ1</name>
+ <description>This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the DMA1 register.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>DMAREQ2</name>
+ <description>This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the DMA2 register.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[7:3]</bitRange>
+ </field>
+ <field>
+ <name>RX_LEVEL</name>
+ <description>Reflects the current level of the Receive FIFO.</description>
+ <bitRange>[11:8]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[15:12]</bitRange>
+ </field>
+ <field>
+ <name>TX_LEVEL</name>
+ <description>Reflects the current level of the Transmit FIFO.</description>
+ <bitRange>[19:16]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:20]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMA1</name>
+ <description>I2S DMA Configuration Register 1. Contains control information for DMA request 1.</description>
+ <addressOffset>0x014</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RX_DMA1_ENABLE</name>
+ <description>When 1, enables DMA1 for I2S receive.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>TX_DMA1_ENABLE</name>
+ <description>When 1, enables DMA1 for I2S transmit.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[7:2]</bitRange>
+ </field>
+ <field>
+ <name>RX_DEPTH_DMA1</name>
+ <description>Set the FIFO level that triggers a receive DMA request on DMA1.</description>
+ <bitRange>[11:8]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[15:12]</bitRange>
+ </field>
+ <field>
+ <name>TX_DEPTH_DMA1</name>
+ <description>Set the FIFO level that triggers a transmit DMA request on DMA1.</description>
+ <bitRange>[19:16]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:20]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMA2</name>
+ <description>I2S DMA Configuration Register 2. Contains control information for DMA request 2.</description>
+ <addressOffset>0x018</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RX_DMA2_ENABLE</name>
+ <description>When 1, enables DMA1 for I2S receive.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>TX_DMA2_ENABLE</name>
+ <description>When 1, enables DMA1 for I2S transmit.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[7:2]</bitRange>
+ </field>
+ <field>
+ <name>RX_DEPTH_DMA2</name>
+ <description>Set the FIFO level that triggers a receive DMA request on DMA2.</description>
+ <bitRange>[11:8]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[15:12]</bitRange>
+ </field>
+ <field>
+ <name>TX_DEPTH_DMA2</name>
+ <description>Set the FIFO level that triggers a transmit DMA request on DMA2.</description>
+ <bitRange>[19:16]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:20]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IRQ</name>
+ <description>I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated.</description>
+ <addressOffset>0x01C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RX_IRQ_ENABLE</name>
+ <description>When 1, enables I2S receive interrupt.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>TX_IRQ_ENABLE</name>
+ <description>When 1, enables I2S transmit interrupt.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[7:2]</bitRange>
+ </field>
+ <field>
+ <name>RX_DEPTH_IRQ</name>
+ <description>Set the FIFO level on which to create an irq request.</description>
+ <bitRange>[11:8]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[15:12]</bitRange>
+ </field>
+ <field>
+ <name>TX_DEPTH_IRQ</name>
+ <description>Set the FIFO level on which to create an irq request.</description>
+ <bitRange>[19:16]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:20]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TXRATE</name>
+ <description>I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK.</description>
+ <addressOffset>0x020</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>Y_DIVIDER</name>
+ <description>I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock.</description>
+ <bitRange>[7:0]</bitRange>
+ </field>
+ <field>
+ <name>X_DIVIDER</name>
+ <description>I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2.</description>
+ <bitRange>[15:8]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:16]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RXRATE</name>
+ <description>I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK.</description>
+ <addressOffset>0x024</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>Y_DIVIDER</name>
+ <description>I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock.</description>
+ <bitRange>[7:0]</bitRange>
+ </field>
+ <field>
+ <name>X_DIVIDER</name>
+ <description>I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2.</description>
+ <bitRange>[15:8]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:16]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TXBITRATE</name>
+ <description>I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock.</description>
+ <addressOffset>0x028</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>TX_BITRATE</name>
+ <description>I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock.</description>
+ <bitRange>[5:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:6]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RXBITRATE</name>
+ <description>I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock.</description>
+ <addressOffset>0x02C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RX_BITRATE</name>
+ <description>I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock.</description>
+ <bitRange>[5:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:6]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TXMODE</name>
+ <description>I2S Transmit mode control.</description>
+ <addressOffset>0x030</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>TXCLKSEL</name>
+ <description>Clock source selection for the transmit bit clock divider.</description>
+ <bitRange>[1:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>SELECT_THE_TX_FRACTI</name>
+ <description>Select the TX fractional rate divider clock output as the source</description>
+ <value>0x0</value>
+ </enumeratedValue>
+
+ <enumeratedValue>
+ <name>SELECT_THE_RX_MCLK_S</name>
+ <description>Select the RX_MCLK signal as the TX_MCLK clock source</description>
+ <value>0x2</value>
+ </enumeratedValue>
+
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TX4PIN</name>
+ <description>Transmit 4-pin mode selection. When 1, enables 4-pin mode.</description>
+ <bitRange>[2:2]</bitRange>
+
+ </field>
+ <field>
+ <name>TXMCENA</name>
+ <description>Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled.</description>
+ <bitRange>[3:3]</bitRange>
+
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:4]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RXMODE</name>
+ <description>I2S Receive mode control.</description>
+ <addressOffset>0x034</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RXCLKSEL</name>
+ <description>Clock source selection for the receive bit clock divider.</description>
+ <bitRange>[1:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>SELECT_THE_RX_FRACTI</name>
+ <description>Select the RX fractional rate divider clock output as the source</description>
+ <value>0x0</value>
+ </enumeratedValue>
+
+ <enumeratedValue>
+ <name>SELECT_THE_TX_MCLK_S</name>
+ <description>Select the TX_MCLK signal as the RX_MCLK clock source</description>
+ <value>0x2</value>
+ </enumeratedValue>
+
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RX4PIN</name>
+ <description>Receive 4-pin mode selection. When 1, enables 4-pin mode.</description>
+ <bitRange>[2:2]</bitRange>
+
+ </field>
+ <field>
+ <name>RXMCENA</name>
+ <description>Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled.</description>
+ <bitRange>[3:3]</bitRange>
+
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:4]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+
+
+ <peripheral>
+ <name>RITIMER</name>
+ <description>Repetitive Interrupt Timer (RIT) </description>
+ <groupName>RIT</groupName>
+ <baseAddress>0x400B0000</baseAddress>
+ <addressBlock>
+ <offset>0</offset>
+ <size>0xFFF</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>RIT</name>
+ <value>29</value>
+
+ </interrupt>
+ <registers>
+ <register>
+ <name>COMPVAL</name>
+ <description>Compare register</description>
+ <addressOffset>0x000</addressOffset>
+ <access>read-write</access>
+ <resetValue>0xFFFFFFFF</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RICOMP</name>
+ <description>Compare register. Holds the compare value which is compared to the counter.</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>MASK</name>
+ <description>Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register.</description>
+ <addressOffset>0x004</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RIMASK</name>
+ <description>Mask register. This register holds the 32-bit mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true).</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CTRL</name>
+ <description>Control register.</description>
+ <addressOffset>0x008</addressOffset>
+ <access>read-write</access>
+ <resetValue>0xC</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RITINT</name>
+ <description>Interrupt flag</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>THIS_BIT_IS_SET_TO_1</name>
+ <description>This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect.</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>THE_COUNTER_VALUE_DO</name>
+ <description>The counter value does not equal the masked compare value.</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RITENCLR</name>
+ <description>Timer enable clear</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>THE_TIMER_WILL_BE_CL</name>
+ <description>The timer will be cleared to 0 whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. This will occur on the same clock that sets the interrupt flag.</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>THE_TIMER_WILL_NOT_B</name>
+ <description>The timer will not be cleared to 0.</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RITENBR</name>
+ <description>Timer enable for debug</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>THE_TIMER_IS_HALTED_</name>
+ <description>The timer is halted when the processor is halted for debugging.</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DEBUG_HAS_NO_EFFECT_</name>
+ <description>Debug has no effect on the timer operation.</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RITEN</name>
+ <description>Timer enable.</description>
+ <bitRange>[3:3]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>TIMER_ENABLED_THIS_</name>
+ <description>Timer enabled. This can be overruled by a debug halt if enabled in bit 2.</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>TIMER_DISABLED_</name>
+ <description>Timer disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:4]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>COUNTER</name>
+ <description>32-bit counter</description>
+ <addressOffset>0x00C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RICOUNTER</name>
+ <description>32-bit up counter. Counts continuously unless RITEN bit in RICTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software.</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+
+ <peripheral>
+ <name>MCPWM</name>
+ <description>Motor Control PWM</description>
+ <groupName>MCPWM</groupName>
+ <baseAddress>0x400B8000</baseAddress>
+ <addressBlock>
+ <offset>0</offset>
+ <size>0xFFF</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>MCPWM</name>
+ <value>30</value>
+
+ </interrupt>
+ <registers>
+ <register>
+ <name>CON</name>
+ <description>PWM Control read address</description>
+ <addressOffset>0x000</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RUN0</name>
+ <description>Stops/starts timer channel 0.</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>STOP_</name>
+ <description>Stop.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RUN_</name>
+ <description>Run.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CENTER0</name>
+ <description>Edge/center aligned operation for channel 0.</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>EDGE_ALIGNED_</name>
+ <description>Edge-aligned.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CENTER_ALIGNED_</name>
+ <description>Center-aligned.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>POLA0</name>
+ <description>Selects polarity of the MCOA0 and MCOB0 pins.</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>PASSIVE_STATE_IS_LOW</name>
+ <description>Passive state is LOW, active state is HIGH.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PASSIVE_STATE_IS_HIG</name>
+ <description>Passive state is HIGH, active state is LOW.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>DTE0</name>
+ <description>Controls the dead-time feature for channel 0.</description>
+ <bitRange>[3:3]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DEAD_TIME_DISABLED_</name>
+ <description>Dead-time disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DEAD_TIME_ENABLED_</name>
+ <description>Dead-time enabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>DISUP0</name>
+ <description>Enable/disable updates of functional registers for channel 0 (see Section 24.8.2).</description>
+ <bitRange>[4:4]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>UPDATE</name>
+ <description>Functional registers are updated from the write registers at the end of each PWM cycle.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>NOUPDATE</name>
+ <description>Functional registers remain the same as long as the timer is running.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[7:5]</bitRange>
+
+ </field>
+ <field>
+ <name>RUN1</name>
+ <description>Stops/starts timer channel 1.</description>
+ <bitRange>[8:8]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>STOP_</name>
+ <description>Stop.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RUN_</name>
+ <description>Run.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CENTER1</name>
+ <description>Edge/center aligned operation for channel 1.</description>
+ <bitRange>[9:9]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>EDGE_ALIGNED_</name>
+ <description>Edge-aligned.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CENTER_ALIGNED_</name>
+ <description>Center-aligned.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>POLA1</name>
+ <description>Selects polarity of the MCOA1 and MCOB1 pins.</description>
+ <bitRange>[10:10]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>PASSIVE_STATE_IS_LOW</name>
+ <description>Passive state is LOW, active state is HIGH.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PASSIVE_STATE_IS_HIG</name>
+ <description>Passive state is HIGH, active state is LOW.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>DTE1</name>
+ <description>Controls the dead-time feature for channel 1.</description>
+ <bitRange>[11:11]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DEAD_TIME_DISABLED_</name>
+ <description>Dead-time disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DEAD_TIME_ENABLED_</name>
+ <description>Dead-time enabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>DISUP1</name>
+ <description>Enable/disable updates of functional registers for channel 1 (see Section 24.8.2).</description>
+ <bitRange>[12:12]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>UPDATE</name>
+ <description>Functional registers are updated from the write registers at the end of each PWM cycle.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>NOUPDATE</name>
+ <description>Functional registers remain the same as long as the timer is running.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[15:13]</bitRange>
+
+ </field>
+ <field>
+ <name>RUN2</name>
+ <description>Stops/starts timer channel 2.</description>
+ <bitRange>[16:16]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>STOP_</name>
+ <description>Stop.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RUN_</name>
+ <description>Run.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CENTER2</name>
+ <description>Edge/center aligned operation for channel 2.</description>
+ <bitRange>[17:17]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>EDGE_ALIGNED_</name>
+ <description>Edge-aligned.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CENTER_ALIGNED_</name>
+ <description>Center-aligned.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>POLA2</name>
+ <description>Selects polarity of the MCOA2 and MCOB2 pins.</description>
+ <bitRange>[18:18]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>PASSIVE_STATE_IS_LOW</name>
+ <description>Passive state is LOW, active state is HIGH.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>PASSIVE_STATE_IS_HIG</name>
+ <description>Passive state is HIGH, active state is LOW.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>DTE2</name>
+ <description>Controls the dead-time feature for channel 1.</description>
+ <bitRange>[19:19]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DEAD_TIME_DISABLED_</name>
+ <description>Dead-time disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DEAD_TIME_ENABLED_</name>
+ <description>Dead-time enabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>DISUP2</name>
+ <description>Enable/disable updates of functional registers for channel 2 (see Section 24.8.2).</description>
+ <bitRange>[20:20]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>UPDATE</name>
+ <description>Functional registers are updated from the write registers at the end of each PWM cycle.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>NOUPDATE</name>
+ <description>Functional registers remain the same as long as the timer is running.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[28:21]</bitRange>
+
+ </field>
+ <field>
+ <name>INVBDC</name>
+ <description>Controls the polarity of the MCOB outputs for all 3 channels. This bit is typically set to 1 only in 3-phase DC mode.</description>
+ <bitRange>[29:29]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>OPPOSITE</name>
+ <description>The MCOB outputs have opposite polarity from the MCOA outputs (aside from dead time).</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SAME</name>
+ <description>The MCOB outputs have the same basic polarity as the MCOA outputs. (see Section 24.8.6)</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>ACMODE</name>
+ <description>3-phase AC mode select (see Section 24.8.7).</description>
+ <bitRange>[30:30]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>3_PHASE_AC_MODE_OFF</name>
+ <description>3-phase AC-mode off: Each PWM channel uses its own timer-counter and period register.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>3_PHASE_AC_MODE_ON_</name>
+ <description>3-phase AC-mode on: All PWM channels use the timer-counter and period register of channel 0.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>DCMODE</name>
+ <description>3-phase DC mode select (see Section 24.8.6).</description>
+ <bitRange>[31:31]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>3_PHASE_DC_MODE_OFF</name>
+ <description>3-phase DC mode off: PWM channels are independent (unless bit ACMODE = 1)</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>3_PHASE_DC_MODE_ON_</name>
+ <description>3-phase DC mode on: The internal MCOA0 output is routed through the CP register (i.e. a mask) register to all six PWM outputs.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CON_SET</name>
+ <description>PWM Control set address</description>
+ <addressOffset>0x004</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>RUN0_SET</name>
+ <description>Writing a one sets the corresponding bit in the CON register.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>CENTER0_SET</name>
+ <description>Writing a one sets the corresponding bit in the CON register.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>POLA0_SET</name>
+ <description>Writing a one sets the corresponding bit in the CON register.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>DTE0_SET</name>
+ <description>Writing a one sets the corresponding bit in the CON register.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>DISUP0_SET</name>
+ <description>Writing a one sets the corresponding bit in the CON register.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Writing a one sets the corresponding bit in the CON register.</description>
+ <bitRange>[7:5]</bitRange>
+ </field>
+ <field>
+ <name>RUN1_SET</name>
+ <description>Writing a one sets the corresponding bit in the CON register.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>CENTER1_SET</name>
+ <description>Writing a one sets the corresponding bit in the CON register.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>POLA1_SET</name>
+ <description>Writing a one sets the corresponding bit in the CON register.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>DTE1_SET</name>
+ <description>Writing a one sets the corresponding bit in the CON register.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>DISUP1_SET</name>
+ <description>Writing a one sets the corresponding bit in the CON register.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Writing a one sets the corresponding bit in the CON register.</description>
+ <bitRange>[15:13]</bitRange>
+ </field>
+ <field>
+ <name>RUN2_SET</name>
+ <description>Writing a one sets the corresponding bit in the CON register.</description>
+ <bitRange>[16:16]</bitRange>
+ </field>
+ <field>
+ <name>CENTER2_SET</name>
+ <description>Writing a one sets the corresponding bit in the CON register.</description>
+ <bitRange>[17:17]</bitRange>
+ </field>
+ <field>
+ <name>POLA2_SET</name>
+ <description>Writing a one sets the corresponding bit in the CON register.</description>
+ <bitRange>[18:18]</bitRange>
+ </field>
+ <field>
+ <name>DTE2_SET</name>
+ <description>Writing a one sets the corresponding bit in the CON register.</description>
+ <bitRange>[19:19]</bitRange>
+ </field>
+ <field>
+ <name>DISUP2_SET</name>
+ <description>Writing a one sets the corresponding bit in the CON register.</description>
+ <bitRange>[20:20]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Writing a one sets the corresponding bit in the CON register.</description>
+ <bitRange>[28:21]</bitRange>
+ </field>
+ <field>
+ <name>INVBDC_SET</name>
+ <description>Writing a one sets the corresponding bit in the CON register.</description>
+ <bitRange>[29:29]</bitRange>
+ </field>
+ <field>
+ <name>ACMODE_SET</name>
+ <description>Writing a one sets the corresponding bit in the CON register.</description>
+ <bitRange>[30:30]</bitRange>
+ </field>
+ <field>
+ <name>DCMODE_SET</name>
+ <description>Writing a one sets the corresponding bit in the CON register.</description>
+ <bitRange>[31:31]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CON_CLR</name>
+ <description>PWM Control clear address</description>
+ <addressOffset>0x008</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>RUN0_CLR</name>
+ <description>Writing a one clears the corresponding bit in the CON register.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>CENTER0_CLR</name>
+ <description>Writing a one clears the corresponding bit in the CON register.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>POLA0_CLR</name>
+ <description>Writing a one clears the corresponding bit in the CON register.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>DTE0_CLR</name>
+ <description>Writing a one clears the corresponding bit in the CON register.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>DISUP0_CLR</name>
+ <description>Writing a one clears the corresponding bit in the CON register.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Writing a one clears the corresponding bit in the CON register.</description>
+ <bitRange>[7:5]</bitRange>
+ </field>
+ <field>
+ <name>RUN1_CLR</name>
+ <description>Writing a one clears the corresponding bit in the CON register.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>CENTER1_CLR</name>
+ <description>Writing a one clears the corresponding bit in the CON register.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>POLA1_CLR</name>
+ <description>Writing a one clears the corresponding bit in the CON register.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>DTE1_CLR</name>
+ <description>Writing a one clears the corresponding bit in the CON register.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>DISUP1_CLR</name>
+ <description>Writing a one clears the corresponding bit in the CON register.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Writing a one clears the corresponding bit in the CON register.</description>
+ <bitRange>[15:13]</bitRange>
+ </field>
+ <field>
+ <name>RUN2_CLR</name>
+ <description>Writing a one clears the corresponding bit in the CON register.</description>
+ <bitRange>[16:16]</bitRange>
+ </field>
+ <field>
+ <name>CENTER2_CLR</name>
+ <description>Writing a one clears the corresponding bit in the CON register.</description>
+ <bitRange>[17:17]</bitRange>
+ </field>
+ <field>
+ <name>POLA2_CLR</name>
+ <description>Writing a one clears the corresponding bit in the CON register.</description>
+ <bitRange>[18:18]</bitRange>
+ </field>
+ <field>
+ <name>DTE2_CLR</name>
+ <description>Writing a one clears the corresponding bit in the CON register.</description>
+ <bitRange>[19:19]</bitRange>
+ </field>
+ <field>
+ <name>DISUP2_CLR</name>
+ <description>Writing a one clears the corresponding bit in the CON register.</description>
+ <bitRange>[20:20]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Writing a one clears the corresponding bit in the CON register.</description>
+ <bitRange>[28:21]</bitRange>
+ </field>
+ <field>
+ <name>INVBDC_CLR</name>
+ <description>Writing a one clears the corresponding bit in the CON register.</description>
+ <bitRange>[29:29]</bitRange>
+ </field>
+ <field>
+ <name>ACMOD_CLR</name>
+ <description>Writing a one clears the corresponding bit in the CON register.</description>
+ <bitRange>[30:30]</bitRange>
+ </field>
+ <field>
+ <name>DCMODE_CLR</name>
+ <description>Writing a one clears the corresponding bit in the CON register.</description>
+ <bitRange>[31:31]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CAPCON</name>
+ <description>Capture Control read address</description>
+ <addressOffset>0x00C</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>CAP0MCI0_RE</name>
+ <description>A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>CAP0MCI0_FE</name>
+ <description>A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>CAP0MCI1_RE</name>
+ <description>A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>CAP0MCI1_FE</name>
+ <description>A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>CAP0MCI2_RE</name>
+ <description>A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>CAP0MCI2_FE</name>
+ <description>A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>CAP1MCI0_RE</name>
+ <description>A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>CAP1MCI0_FE</name>
+ <description>A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>CAP1MCI1_RE</name>
+ <description>A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>CAP1MCI1_FE</name>
+ <description>A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>CAP1MCI2_RE</name>
+ <description>A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>CAP1MCI2_FE</name>
+ <description>A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>CAP2MCI0_RE</name>
+ <description>A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>CAP2MCI0_FE</name>
+ <description>A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>CAP2MCI1_RE</name>
+ <description>A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1.</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>CAP2MCI1_FE</name>
+ <description>A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>CAP2MCI2_RE</name>
+ <description>A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2.</description>
+ <bitRange>[16:16]</bitRange>
+ </field>
+ <field>
+ <name>CAP2MCI2_FE</name>
+ <description>A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2.</description>
+ <bitRange>[17:17]</bitRange>
+ </field>
+ <field>
+ <name>RT0</name>
+ <description>If this bit is 1, TC0 is reset by a channel 0 capture event.</description>
+ <bitRange>[18:18]</bitRange>
+ </field>
+ <field>
+ <name>RT1</name>
+ <description>If this bit is 1, TC1 is reset by a channel 1 capture event.</description>
+ <bitRange>[19:19]</bitRange>
+ </field>
+ <field>
+ <name>RT2</name>
+ <description>If this bit is 1, TC2 is reset by a channel 2 capture event.</description>
+ <bitRange>[20:20]</bitRange>
+ </field>
+
+
+
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[31:21]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CAPCON_SET</name>
+ <description>Capture Control set address</description>
+ <addressOffset>0x010</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>CAP0MCI0_RE_SET</name>
+ <description>Writing a one sets the corresponding bits in the CAPCON register.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>CAP0MCI0_FE_SET</name>
+ <description>Writing a one sets the corresponding bits in the CAPCON register.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>CAP0MCI1_RE_SET</name>
+ <description>Writing a one sets the corresponding bits in the CAPCON register.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>CAP0MCI1_FE_SET</name>
+ <description>Writing a one sets the corresponding bits in the CAPCON register.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>CAP0MCI2_RE_SET</name>
+ <description>Writing a one sets the corresponding bits in the CAPCON register.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>CAP0MCI2_FE_SET</name>
+ <description>Writing a one sets the corresponding bits in the CAPCON register.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>CAP1MCI0_RE_SET</name>
+ <description>Writing a one sets the corresponding bits in the CAPCON register.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>CAP1MCI0_FE_SET</name>
+ <description>Writing a one sets the corresponding bits in the CAPCON register.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>CAP1MCI1_RE_SET</name>
+ <description>Writing a one sets the corresponding bits in the CAPCON register.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>CAP1MCI1_FE_SET</name>
+ <description>Writing a one sets the corresponding bits in the CAPCON register.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>CAP1MCI2_RE_SET</name>
+ <description>Writing a one sets the corresponding bits in the CAPCON register.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>CAP1MCI2_FE_SET</name>
+ <description>Writing a one sets the corresponding bits in the CAPCON register.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>CAP2MCI0_RE_SET</name>
+ <description>Writing a one sets the corresponding bits in the CAPCON register.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>CAP2MCI0_FE_SET</name>
+ <description>Writing a one sets the corresponding bits in the CAPCON register.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>CAP2MCI1_RE_SET</name>
+ <description>Writing a one sets the corresponding bits in the CAPCON register.</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>CAP2MCI1_FE_SET</name>
+ <description>Writing a one sets the corresponding bits in the CAPCON register.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>CAP2MCI2_RE_SET</name>
+ <description>Writing a one sets the corresponding bits in the CAPCON register.</description>
+ <bitRange>[16:16]</bitRange>
+ </field>
+ <field>
+ <name>CAP2MCI2_FE_SET</name>
+ <description>Writing a one sets the corresponding bits in the CAPCON register.</description>
+ <bitRange>[17:17]</bitRange>
+ </field>
+ <field>
+ <name>RT0_SET</name>
+ <description>Writing a one sets the corresponding bits in the CAPCON register.</description>
+ <bitRange>[18:18]</bitRange>
+ </field>
+ <field>
+ <name>RT1_SET</name>
+ <description>Writing a one sets the corresponding bits in the CAPCON register.</description>
+ <bitRange>[19:19]</bitRange>
+ </field>
+ <field>
+ <name>RT2_SET</name>
+ <description>Writing a one sets the corresponding bits in the CAPCON register.</description>
+ <bitRange>[20:20]</bitRange>
+ </field>
+
+
+
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[31:21]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CAPCON_CLR</name>
+ <description>Event Control clear address</description>
+ <addressOffset>0x014</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>CAP0MCI0_RE_CLR</name>
+ <description>Writing a one clears the corresponding bits in the CAPCON register.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>CAP0MCI0_FE_CLR</name>
+ <description>Writing a one clears the corresponding bits in the CAPCON register.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>CAP0MCI1_RE_CLR</name>
+ <description>Writing a one clears the corresponding bits in the CAPCON register.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>CAP0MCI1_FE_CLR</name>
+ <description>Writing a one clears the corresponding bits in the CAPCON register.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>CAP0MCI2_RE_CLR</name>
+ <description>Writing a one clears the corresponding bits in the CAPCON register.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>CAP0MCI2_FE_CLR</name>
+ <description>Writing a one clears the corresponding bits in the CAPCON register.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>CAP1MCI0_RE_CLR</name>
+ <description>Writing a one clears the corresponding bits in the CAPCON register.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>CAP1MCI0_FE_CLR</name>
+ <description>Writing a one clears the corresponding bits in the CAPCON register.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>CAP1MCI1_RE_CLR</name>
+ <description>Writing a one clears the corresponding bits in the CAPCON register.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>CAP1MCI1_FE_CLR</name>
+ <description>Writing a one clears the corresponding bits in the CAPCON register.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>CAP1MCI2_RE_CLR</name>
+ <description>Writing a one clears the corresponding bits in the CAPCON register.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>CAP1MCI2_FE_CLR</name>
+ <description>Writing a one clears the corresponding bits in the CAPCON register.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>CAP2MCI0_RE_CLR</name>
+ <description>Writing a one clears the corresponding bits in the CAPCON register.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>CAP2MCI0_FE_CLR</name>
+ <description>Writing a one clears the corresponding bits in the CAPCON register.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>CAP2MCI1_RE_CLR</name>
+ <description>Writing a one clears the corresponding bits in the CAPCON register.</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>CAP2MCI1_FE_CLR</name>
+ <description>Writing a one clears the corresponding bits in the CAPCON register.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>CAP2MCI2_RE_CLR</name>
+ <description>Writing a one clears the corresponding bits in the CAPCON register.</description>
+ <bitRange>[16:16]</bitRange>
+ </field>
+ <field>
+ <name>CAP2MCI2_FE_CLR</name>
+ <description>Writing a one clears the corresponding bits in the CAPCON register.</description>
+ <bitRange>[17:17]</bitRange>
+ </field>
+ <field>
+ <name>RT0_CLR</name>
+ <description>Writing a one clears the corresponding bits in the CAPCON register.</description>
+ <bitRange>[18:18]</bitRange>
+ </field>
+ <field>
+ <name>RT1_CLR</name>
+ <description>Writing a one clears the corresponding bits in the CAPCON register.</description>
+ <bitRange>[19:19]</bitRange>
+ </field>
+ <field>
+ <name>RT2_CLR</name>
+ <description>Writing a one clears the corresponding bits in the CAPCON register.</description>
+ <bitRange>[20:20]</bitRange>
+ </field>
+
+
+
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[31:21]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <dim>3</dim>
+ <dimIncrement>0x4</dimIncrement>
+ <dimIndex>0-2</dimIndex>
+ <name>TC[%s]</name>
+ <displayName>TC[%s]</displayName>
+ <description>Timer Counter register</description>
+ <addressOffset>0x018</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>MCTC</name>
+ <description>Timer/Counter value.</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <dim>3</dim>
+ <dimIncrement>0x4</dimIncrement>
+ <dimIndex>0-2</dimIndex>
+ <name>LIM[%s]</name>
+ <displayName>LIM[%s]</displayName>
+ <description>Limit register</description>
+ <addressOffset>0x024</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>MCLIM</name>
+ <description>Limit value.</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <dim>3</dim>
+ <dimIncrement>0x4</dimIncrement>
+ <dimIndex>0-2</dimIndex>
+ <name>MAT[%s]</name>
+ <displayName>MAT[%s]</displayName>
+ <description>Match register</description>
+ <addressOffset>0x030</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>MCMAT</name>
+ <description>Match value.</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DT</name>
+ <description>Dead time register</description>
+ <addressOffset>0x03C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0x3FFFFFFF</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>DT0</name>
+ <description>Dead time for channel 0.[1]</description>
+ <bitRange>[9:0]</bitRange>
+ </field>
+ <field>
+ <name>DT1</name>
+ <description>Dead time for channel 1.[2]</description>
+ <bitRange>[19:10]</bitRange>
+ </field>
+ <field>
+ <name>DT2</name>
+ <description>Dead time for channel 2.[2]</description>
+ <bitRange>[29:20]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>reserved</description>
+ <bitRange>[31:30]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CP</name>
+ <description>Communication Pattern register</description>
+ <addressOffset>0x040</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>CCPA0</name>
+ <description>Communication pattern output A, channel 0.</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>MCOA0_PASSIVE_</name>
+ <description>MCOA0 passive.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>INTERNAL_MCOA0_</name>
+ <description>internal MCOA0.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CCPB0</name>
+ <description>Communication pattern output B, channel 0.</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>MCOB0_PASSIVE_</name>
+ <description>MCOB0 passive.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MCOB0_TRACKS_INTERNA</name>
+ <description>MCOB0 tracks internal MCOA0.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CCPA1</name>
+ <description>Communication pattern output A, channel 1.</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>MCOA1_PASSIVE_</name>
+ <description>MCOA1 passive.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MCOA1_TRACKS_INTERNA</name>
+ <description>MCOA1 tracks internal MCOA0.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CCPB1</name>
+ <description>Communication pattern output B, channel 1.</description>
+ <bitRange>[3:3]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>MCOB1_PASSIVE_</name>
+ <description>MCOB1 passive.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MCOB1_TRACKS_INTERNA</name>
+ <description>MCOB1 tracks internal MCOA0.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CCPA2</name>
+ <description>Communication pattern output A, channel 2.</description>
+ <bitRange>[4:4]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>MCOA2_PASSIVE_</name>
+ <description>MCOA2 passive.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MCOA2_TRACKS_INTERNA</name>
+ <description>MCOA2 tracks internal MCOA0.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CCPB2</name>
+ <description>Communication pattern output B, channel 2.</description>
+ <bitRange>[5:5]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>MCOB2_PASSIVE_</name>
+ <description>MCOB2 passive.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>MCOB2_TRACKS_INTERNA</name>
+ <description>MCOB2 tracks internal MCOA0.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[31:6]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <dim>3</dim>
+ <dimIncrement>0x4</dimIncrement>
+ <dimIndex>0-2</dimIndex>
+ <name>CAP[%s]</name>
+ <displayName>CAP[%s]</displayName>
+ <description>Capture register</description>
+ <addressOffset>0x044</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>CAP</name>
+ <description>Current TC value at a capture event.</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>INTEN</name>
+ <description>Interrupt Enable read address</description>
+ <addressOffset>0x050</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>ILIM0</name>
+ <description>Limit interrupt for channel 0.</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>INTERRUPT_DISABLED_</name>
+ <description>Interrupt disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>INTERRUPT_ENABLED_</name>
+ <description>Interrupt enabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>IMAT0</name>
+ <description>Match interrupt for channel 0.</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>INTERRUPT_DISABLED_</name>
+ <description>Interrupt disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>INTERRUPT_ENABLED_</name>
+ <description>Interrupt enabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>ICAP0</name>
+ <description>Capture interrupt for channel 0.</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>INTERRUPT_DISABLED_</name>
+ <description>Interrupt disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>INTERRUPT_ENABLED_</name>
+ <description>Interrupt enabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[3:3]</bitRange>
+
+ </field>
+ <field>
+ <name>ILIM1</name>
+ <description>Limit interrupt for channel 1.</description>
+ <bitRange>[4:4]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>INTERRUPT_DISABLED_</name>
+ <description>Interrupt disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>INTERRUPT_ENABLED_</name>
+ <description>Interrupt enabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>IMAT1</name>
+ <description>Match interrupt for channel 1.</description>
+ <bitRange>[5:5]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>INTERRUPT_DISABLED_</name>
+ <description>Interrupt disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>INTERRUPT_ENABLED_</name>
+ <description>Interrupt enabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>ICAP1</name>
+ <description>Capture interrupt for channel 1.</description>
+ <bitRange>[6:6]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>INTERRUPT_DISABLED_</name>
+ <description>Interrupt disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>INTERRUPT_ENABLED_</name>
+ <description>Interrupt enabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[7:7]</bitRange>
+
+ </field>
+ <field>
+ <name>ILIM2</name>
+ <description>Limit interrupt for channel 2.</description>
+ <bitRange>[8:8]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>INTERRUPT_DISABLED_</name>
+ <description>Interrupt disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>INTERRUPT_ENABLED_</name>
+ <description>Interrupt enabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>IMAT2</name>
+ <description>Match interrupt for channel 2.</description>
+ <bitRange>[9:9]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>INTERRUPT_DISABLED_</name>
+ <description>Interrupt disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>INTERRUPT_ENABLED_</name>
+ <description>Interrupt enabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>ICAP2</name>
+ <description>Capture interrupt for channel 2.</description>
+ <bitRange>[10:10]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>INTERRUPT_DISABLED_</name>
+ <description>Interrupt disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>INTERRUPT_ENABLED_</name>
+ <description>Interrupt enabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[14:11]</bitRange>
+
+ </field>
+ <field>
+ <name>ABORT</name>
+ <description>Fast abort interrupt.</description>
+ <bitRange>[15:15]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>INTERRUPT_DISABLED_</name>
+ <description>Interrupt disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>INTERRUPT_ENABLED_</name>
+ <description>Interrupt enabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[31:16]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>INTEN_SET</name>
+ <description>Interrupt Enable set address</description>
+ <addressOffset>0x054</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>ILIM0_SET</name>
+ <description>Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>IMAT0_SET</name>
+ <description>Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>ICAP0_SET</name>
+ <description>Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>ILIM1_SET</name>
+ <description>Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>IMAT1_SET</name>
+ <description>Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>ICAP1_SET</name>
+ <description>Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>ILIM2_SET</name>
+ <description>Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>IMAT2_SET</name>
+ <description>Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>ICAP2_SET</name>
+ <description>Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[14:12]</bitRange>
+ </field>
+ <field>
+ <name>ABORT_SET</name>
+ <description>Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[31:16]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>INTEN_CLR</name>
+ <description>Interrupt Enable clear address</description>
+ <addressOffset>0x058</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>ILIM0_CLR</name>
+ <description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>IMAT0_CLR</name>
+ <description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>ICAP0_CLR</name>
+ <description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>ILIM1_CLR</name>
+ <description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>IMAT1_CLR</name>
+ <description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>ICAP1_CLR</name>
+ <description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>ILIM2_CLR</name>
+ <description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>IMAT2_CLR</name>
+ <description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>ICAP2_CLR</name>
+ <description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[14:11]</bitRange>
+ </field>
+ <field>
+ <name>ABORT_CLR</name>
+ <description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[31:16]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>INTF</name>
+ <description>Interrupt flags read address</description>
+ <addressOffset>0x068</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>ILIM0_F</name>
+ <description>Limit interrupt flag for channel 0.</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>THIS_INTERRUPT_SOURC</name>
+ <description>This interrupt source is not contributing to the MCPWM interrupt request.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>IF_THE_CORRESPONDING</name>
+ <description>If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>IMAT0_F</name>
+ <description>Match interrupt flag for channel 0.</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>THIS_INTERRUPT_SOURC</name>
+ <description>This interrupt source is not contributing to the MCPWM interrupt request.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>IF_THE_CORRESPONDING</name>
+ <description>If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>ICAP0_F</name>
+ <description>Capture interrupt flag for channel 0.</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>THIS_INTERRUPT_SOURC</name>
+ <description>This interrupt source is not contributing to the MCPWM interrupt request.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>IF_THE_CORRESPONDING</name>
+ <description>If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[3:3]</bitRange>
+
+ </field>
+ <field>
+ <name>ILIM1_F</name>
+ <description>Limit interrupt flag for channel 1.</description>
+ <bitRange>[4:4]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>THIS_INTERRUPT_SOURC</name>
+ <description>This interrupt source is not contributing to the MCPWM interrupt request.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>IF_THE_CORRESPONDING</name>
+ <description>If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>IMAT1_F</name>
+ <description>Match interrupt flag for channel 1.</description>
+ <bitRange>[5:5]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>THIS_INTERRUPT_SOURC</name>
+ <description>This interrupt source is not contributing to the MCPWM interrupt request.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>IF_THE_CORRESPONDING</name>
+ <description>If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>ICAP1_F</name>
+ <description>Capture interrupt flag for channel 1.</description>
+ <bitRange>[6:6]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>THIS_INTERRUPT_SOURC</name>
+ <description>This interrupt source is not contributing to the MCPWM interrupt request.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>IF_THE_CORRESPONDING</name>
+ <description>If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[7:7]</bitRange>
+
+ </field>
+ <field>
+ <name>ILIM2_F</name>
+ <description>Limit interrupt flag for channel 2.</description>
+ <bitRange>[8:8]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>THIS_INTERRUPT_SOURC</name>
+ <description>This interrupt source is not contributing to the MCPWM interrupt request.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>IF_THE_CORRESPONDING</name>
+ <description>If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>IMAT2_F</name>
+ <description>Match interrupt flag for channel 2.</description>
+ <bitRange>[9:9]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>THIS_INTERRUPT_SOURC</name>
+ <description>This interrupt source is not contributing to the MCPWM interrupt request.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>IF_THE_CORRESPONDING</name>
+ <description>If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>ICAP2_F</name>
+ <description>Capture interrupt flag for channel 2.</description>
+ <bitRange>[10:10]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>THIS_INTERRUPT_SOURC</name>
+ <description>This interrupt source is not contributing to the MCPWM interrupt request.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>IF_THE_CORRESPONDING</name>
+ <description>If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[14:11]</bitRange>
+
+ </field>
+ <field>
+ <name>ABORT_F</name>
+ <description>Fast abort interrupt flag.</description>
+ <bitRange>[15:15]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>THIS_INTERRUPT_SOURC</name>
+ <description>This interrupt source is not contributing to the MCPWM interrupt request.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>IF_THE_CORRESPONDING</name>
+ <description>If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[31:16]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>INTF_SET</name>
+ <description>Interrupt flags set address</description>
+ <addressOffset>0x06C</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>ILIM0_F_SET</name>
+ <description>Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>IMAT0_F_SET</name>
+ <description>Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>ICAP0_F_SET</name>
+ <description>Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>ILIM1_F_SET</name>
+ <description>Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>IMAT1_F_SET</name>
+ <description>Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>ICAP1_F_SET</name>
+ <description>Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>ILIM2_F_SET</name>
+ <description>Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>IMAT2_F_SET</name>
+ <description>Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>ICAP2_F_SET</name>
+ <description>Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[14:11]</bitRange>
+ </field>
+ <field>
+ <name>ABORT_F_SET</name>
+ <description>Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[31:16]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>INTF_CLR</name>
+ <description>Interrupt flags clear address</description>
+ <addressOffset>0x070</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>ILIM0_F_CLR</name>
+ <description>Writing a one clears the corresponding bit in the INTF register, thus clearing the corresponding interrupt request.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>IMAT0_F_CLR</name>
+ <description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>ICAP0_F_CLR</name>
+ <description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>ILIM1_F_CLR</name>
+ <description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>IMAT1_F_CLR</name>
+ <description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>ICAP1_F_CLR</name>
+ <description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>ILIM2_F_CLR</name>
+ <description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>IMAT2_F_CLR</name>
+ <description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>ICAP2_F_CLR</name>
+ <description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
+ <bitRange>[14:11]</bitRange>
+ </field>
+ <field>
+ <name>ABORT_F_CLR</name>
+ <description>Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[31:16]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CNTCON</name>
+ <description>Count Control read address</description>
+ <addressOffset>0x05C</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>TC0MCI0_RE</name>
+ <description>Counter 0 rising edge mode, channel 0.</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>A_RISING_EDGE_ON_MCI</name>
+ <description>A rising edge on MCI0 does not affect counter 0.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RISING</name>
+ <description>If MODE0 is 1, counter 0 advances on a rising edge on MCI0.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TC0MCI0_FE</name>
+ <description>Counter 0 falling edge mode, channel 0.</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>A_FALLING_EDGE_ON_MC</name>
+ <description>A falling edge on MCI0 does not affect counter 0.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>FALLING</name>
+ <description>If MODE0 is 1, counter 0 advances on a falling edge on MCI0.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TC0MCI1_RE</name>
+ <description>Counter 0 rising edge mode, channel 1.</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>A_RISING_EDGE_ON_MCI</name>
+ <description>A rising edge on MCI1 does not affect counter 0.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RISING</name>
+ <description>If MODE0 is 1, counter 0 advances on a rising edge on MCI1.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TC0MCI1_FE</name>
+ <description>Counter 0 falling edge mode, channel 1.</description>
+ <bitRange>[3:3]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>A_FALLING_EDGE_ON_MC</name>
+ <description>A falling edge on MCI1 does not affect counter 0.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>FALLING</name>
+ <description>If MODE0 is 1, counter 0 advances on a falling edge on MCI1.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TC0MCI2_RE</name>
+ <description>Counter 0 rising edge mode, channel 2.</description>
+ <bitRange>[4:4]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>A_RISING_EDGE_ON_MCI</name>
+ <description>A rising edge on MCI0 does not affect counter 0.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RISING</name>
+ <description>If MODE0 is 1, counter 0 advances on a rising edge on MCI2.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TC0MCI2_FE</name>
+ <description>Counter 0 falling edge mode, channel 2.</description>
+ <bitRange>[5:5]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>A_FALLING_EDGE_ON_MC</name>
+ <description>A falling edge on MCI0 does not affect counter 0.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>FALLLING</name>
+ <description>If MODE0 is 1, counter 0 advances on a falling edge on MCI2.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TC1MCI0_RE</name>
+ <description>Counter 1 rising edge mode, channel 0.</description>
+ <bitRange>[6:6]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>A_RISING_EDGE_ON_MCI</name>
+ <description>A rising edge on MCI0 does not affect counter 1.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RISING</name>
+ <description>If MODE1 is 1, counter 1 advances on a rising edge on MCI0.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TC1MCI0_FE</name>
+ <description>Counter 1 falling edge mode, channel 0.</description>
+ <bitRange>[7:7]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>A_FALLING_EDGE_ON_MC</name>
+ <description>A falling edge on MCI0 does not affect counter 1.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>FALLING</name>
+ <description>If MODE1 is 1, counter 1 advances on a falling edge on MCI0.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TC1MCI1_RE</name>
+ <description>Counter 1 rising edge mode, channel 1.</description>
+ <bitRange>[8:8]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>A_RISING_EDGE_ON_MCI</name>
+ <description>A rising edge on MCI1 does not affect counter 1.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RISING</name>
+ <description>If MODE1 is 1, counter 1 advances on a rising edge on MCI1.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TC1MCI1_FE</name>
+ <description>Counter 1 falling edge mode, channel 1.</description>
+ <bitRange>[9:9]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>A_FALLING_EDGE_ON_MC</name>
+ <description>A falling edge on MCI0 does not affect counter 1.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>FALLING</name>
+ <description>If MODE1 is 1, counter 1 advances on a falling edge on MCI1.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TC1MCI2_RE</name>
+ <description>Counter 1 rising edge mode, channel 2.</description>
+ <bitRange>[10:10]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>A_RISING_EDGE_ON_MCI</name>
+ <description>A rising edge on MCI2 does not affect counter 1.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RISING</name>
+ <description>If MODE1 is 1, counter 1 advances on a rising edge on MCI2.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TC1MCI2_FE</name>
+ <description>Counter 1 falling edge mode, channel 2.</description>
+ <bitRange>[11:11]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>A_FALLING_EDGE_ON_MC</name>
+ <description>A falling edge on MCI2 does not affect counter 1.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>FALLING</name>
+ <description>If MODE1 is 1, counter 1 advances on a falling edge on MCI2.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TC2MCI0_RE</name>
+ <description>Counter 2 rising edge mode, channel 0.</description>
+ <bitRange>[12:12]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>A_RISING_EDGE_ON_MCI</name>
+ <description>A rising edge on MCI0 does not affect counter 2.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RISING</name>
+ <description>If MODE2 is 1, counter 2 advances on a rising edge on MCI0.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TC2MCI0_FE</name>
+ <description>Counter 2 falling edge mode, channel 0.</description>
+ <bitRange>[13:13]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>A_FALLING_EDGE_ON_MC</name>
+ <description>A falling edge on MCI0 does not affect counter 2.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>FALLING</name>
+ <description>If MODE2 is 1, counter 2 advances on a falling edge on MCI0.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TC2MCI1_RE</name>
+ <description>Counter 2 rising edge mode, channel 1.</description>
+ <bitRange>[14:14]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>A_RISING_EDGE_ON_MCI</name>
+ <description>A rising edge on MCI1 does not affect counter 2.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RISING</name>
+ <description>If MODE2 is 1, counter 2 advances on a rising edge on MCI1.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TC2MCI1_FE</name>
+ <description>Counter 2 falling edge mode, channel 1.</description>
+ <bitRange>[15:15]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>A_FALLING_EDGE_ON_MC</name>
+ <description>A falling edge on MCI1 does not affect counter 2.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>FALLING</name>
+ <description>If MODE2 is 1, counter 2 advances on a falling edge on MCI1.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TC2MCI2_RE</name>
+ <description>Counter 2 rising edge mode, channel 2.</description>
+ <bitRange>[16:16]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>A_RISING_EDGE_ON_MCI</name>
+ <description>A rising edge on MCI2 does not affect counter 2.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RISIING</name>
+ <description>If MODE2 is 1, counter 2 advances on a rising edge on MCI2.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TC2MCI2_FE</name>
+ <description>Counter 2 falling edge mode, channel 2.</description>
+ <bitRange>[17:17]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>A_FALLING_EDGE_ON_MC</name>
+ <description>A falling edge on MCI2 does not affect counter 2.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>FALLING</name>
+ <description>If MODE2 is 1, counter 2 advances on a falling edge on MCI2.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[28:18]</bitRange>
+
+ </field>
+ <field>
+ <name>CNTR0</name>
+ <description>Channel 0 counter/timer mode.</description>
+ <bitRange>[29:29]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>CHANNEL_0_IS_IN_TIME</name>
+ <description>Channel 0 is in timer mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CHANNEL_0_IS_IN_COUN</name>
+ <description>Channel 0 is in counter mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CNTR1</name>
+ <description>Channel 1 counter/timer mode.</description>
+ <bitRange>[30:30]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>CHANNEL_1_IS_IN_TIME</name>
+ <description>Channel 1 is in timer mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CHANNEL_1_IS_IN_COUN</name>
+ <description>Channel 1 is in counter mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CNTR2</name>
+ <description>Channel 2 counter/timer mode.</description>
+ <bitRange>[31:31]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>CHANNEL_2_IS_IN_TIME</name>
+ <description>Channel 2 is in timer mode.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CHANNEL_2_IS_IN_COUN</name>
+ <description>Channel 2 is in counter mode.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CNTCON_SET</name>
+ <description>Count Control set address</description>
+ <addressOffset>0x060</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>TC0MCI0_RE_SET</name>
+ <description>Writing a one sets the corresponding bit in the CNTCON register.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>TC0MCI0_FE_SET</name>
+ <description>Writing a one sets the corresponding bit in the CNTCON register.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>TC0MCI1_RE_SET</name>
+ <description>Writing a one sets the corresponding bit in the CNTCON register.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>TC0MCI1_FE_SET</name>
+ <description>Writing a one sets the corresponding bit in the CNTCON register.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>TC0MCI2_RE_SET</name>
+ <description>Writing a one sets the corresponding bit in the CNTCON register.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>TC0MCI2_FE_SET</name>
+ <description>Writing a one sets the corresponding bit in the CNTCON register.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>TC1MCI0_RE_SET</name>
+ <description>Writing a one sets the corresponding bit in the CNTCON register.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>TC1MCI0_FE_SET</name>
+ <description>Writing a one sets the corresponding bit in the CNTCON register.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>TC1MCI1_RE_SET</name>
+ <description>Writing a one sets the corresponding bit in the CNTCON register.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>TC1MCI1_FE_SET</name>
+ <description>Writing a one sets the corresponding bit in the CNTCON register.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>TC1MCI2_RE_SET</name>
+ <description>Writing a one sets the corresponding bit in the CNTCON register.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>TC1MCI2_FE_SET</name>
+ <description>Writing a one sets the corresponding bit in the CNTCON register.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>TC2MCI0_RE_SET</name>
+ <description>Writing a one sets the corresponding bit in the CNTCON register.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>TC2MCI0_FE_SET</name>
+ <description>Writing a one sets the corresponding bit in the CNTCON register.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>TC2MCI1_RE_SET</name>
+ <description>Writing a one sets the corresponding bit in the CNTCON register.</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>TC2MCI1_FE_SET</name>
+ <description>Writing a one sets the corresponding bit in the CNTCON register.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>TC2MCI2_RE_SET</name>
+ <description>Writing a one sets the corresponding bit in the CNTCON register.</description>
+ <bitRange>[16:16]</bitRange>
+ </field>
+ <field>
+ <name>TC2MCI2_FE_SET</name>
+ <description>Writing a one sets the corresponding bit in the CNTCON register.</description>
+ <bitRange>[17:17]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[28:18]</bitRange>
+ </field>
+ <field>
+ <name>CNTR0_SET</name>
+ <description>Writing a one sets the corresponding bit in the CNTCON register.</description>
+ <bitRange>[29:29]</bitRange>
+ </field>
+ <field>
+ <name>CNTR1_SET</name>
+ <description>Writing a one sets the corresponding bit in the CNTCON register.</description>
+ <bitRange>[30:30]</bitRange>
+ </field>
+ <field>
+ <name>CNTR2_SET</name>
+ <description>Writing a one sets the corresponding bit in the CNTCON register.</description>
+ <bitRange>[31:31]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CNTCON_CLR</name>
+ <description>Count Control clear address</description>
+ <addressOffset>0x064</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>TC0MCI0_RE_CLR</name>
+ <description>Writing a one clears the corresponding bit in the CNTCON register.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>TC0MCI0_FE_CLR</name>
+ <description>Writing a one clears the corresponding bit in the CNTCON register.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>TC0MCI1_RE_CLR</name>
+ <description>Writing a one clears the corresponding bit in the CNTCON register.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>TC0MCI1_FE_CLR</name>
+ <description>Writing a one clears the corresponding bit in the CNTCON register.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>TC0MCI2_RE</name>
+ <description>Writing a one clears the corresponding bit in the CNTCON register.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>TC0MCI2_FE_CLR</name>
+ <description>Writing a one clears the corresponding bit in the CNTCON register.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>TC1MCI0_RE_CLR</name>
+ <description>Writing a one clears the corresponding bit in the CNTCON register.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>TC1MCI0_FE_CLR</name>
+ <description>Writing a one clears the corresponding bit in the CNTCON register.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>TC1MCI1_RE_CLR</name>
+ <description>Writing a one clears the corresponding bit in the CNTCON register.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>TC1MCI1_FE_CLR</name>
+ <description>Writing a one clears the corresponding bit in the CNTCON register.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>TC1MCI2_RE_CLR</name>
+ <description>Writing a one clears the corresponding bit in the CNTCON register.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>TC1MCI2_FE_CLR</name>
+ <description>Writing a one clears the corresponding bit in the CNTCON register.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>TC2MCI0_RE_CLR</name>
+ <description>Writing a one clears the corresponding bit in the CNTCON register.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>TC2MCI0_FE_CLR</name>
+ <description>Writing a one clears the corresponding bit in the CNTCON register.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>TC2MCI1_RE_CLR</name>
+ <description>Writing a one clears the corresponding bit in the CNTCON register.</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>TC2MCI1_FE_CLR</name>
+ <description>Writing a one clears the corresponding bit in the CNTCON register.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>TC2MCI2_RE_CLR</name>
+ <description>Writing a one clears the corresponding bit in the CNTCON register.</description>
+ <bitRange>[16:16]</bitRange>
+ </field>
+ <field>
+ <name>TC2MCI2_FE_CLR</name>
+ <description>Writing a one clears the corresponding bit in the CNTCON register.</description>
+ <bitRange>[17:17]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[28:18]</bitRange>
+ </field>
+ <field>
+ <name>CNTR0_CLR</name>
+ <description>Writing a one clears the corresponding bit in the CNTCON register.</description>
+ <bitRange>[29:29]</bitRange>
+ </field>
+ <field>
+ <name>CNTR1_CLR</name>
+ <description>Writing a one clears the corresponding bit in the CNTCON register.</description>
+ <bitRange>[30:30]</bitRange>
+ </field>
+ <field>
+ <name>CNTR2_CLR</name>
+ <description>Writing a one clears the corresponding bit in the CNTCON register.</description>
+ <bitRange>[31:31]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CAP_CLR</name>
+ <description>Capture clear address</description>
+ <addressOffset>0x074</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>CAP_CLR0</name>
+ <description>Writing a 1 to this bit clears the CAP0 register.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>CAP_CLR1</name>
+ <description>Writing a 1 to this bit clears the CAP1 register.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>CAP_CLR2</name>
+ <description>Writing a 1 to this bit clears the CAP2 register.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <bitRange>[31:3]</bitRange>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+
+ <peripheral>
+ <name>QEI</name>
+ <description>Quadrature Encoder Interface (QEI) </description>
+ <groupName>QEI</groupName>
+ <baseAddress>0x400BC000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0xFFF</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>QEI</name>
+ <value>31</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>CON</name>
+ <description>Control register</description>
+ <addressOffset>0x000</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>RESP</name>
+ <description>Reset position counter. When set = 1, resets the position counter to all zeros. Autoclears when the position counter is cleared.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>RESPI</name>
+ <description>Reset position counter on index. When set = 1, resets the position counter to all zeros once only the first time an index pulse occurs. Autoclears when the position counter is cleared.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>RESV</name>
+ <description>Reset velocity. When set = 1, resets the velocity counter to all zeros, reloads the velocity timer, and presets the velocity compare register. Autoclears when the velocity counter is cleared.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>RESI</name>
+ <description>Reset index counter. When set = 1, resets the index counter to all zeros. Autoclears when the index counter is cleared.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:4]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CONF</name>
+ <description>Configuration register</description>
+ <addressOffset>0x008</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>DIRINV</name>
+ <description>Direction invert. When 1, complements the DIR bit.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>SIGMODE</name>
+ <description>Signal Mode. When 0, PhA and PhB function as quadrature encoder inputs. When 1, PhA functions as the direction signal and PhB functions as the clock signal.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>CAPMODE</name>
+ <description>Capture Mode. When 0, only PhA edges are counted (2X). When 1, BOTH PhA and PhB edges are counted (4X), increasing resolution but decreasing range.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>INVINX</name>
+ <description>Invert Index. When 1, inverts the sense of the index input.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>CRESPI</name>
+ <description>Continuously reset the position counter on index. When 1, resets the position counter to all zeros whenever an index pulse occurs after the next position increase (recalibration).</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[15:5]</bitRange>
+ </field>
+ <field>
+ <name>INXGATE</name>
+ <description>Index gating configuration: When INXGATE[16] = 1, pass the index when PHA = 1 and PHB = 0, otherwise block index. When INXGATE[17] = 1, pass the index when PHA = 1 and PHB = 1, otherwise block index. When INXGATE[18] = 1, pass the index when PHA = 0 and PHB = 1, otherwise block index. When INXGATE[19] = 1, pass the index when PHA = 0 and PHB = 0, otherwise block index.</description>
+ <bitRange>[19:16]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:20]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>STAT</name>
+ <description>Status register</description>
+ <addressOffset>0x004</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>DIR</name>
+ <description>Direction bit. In combination with DIRINV bit indicates forward or reverse direction. See Table 597.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:1]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>POS</name>
+ <description>Position register</description>
+ <addressOffset>0x00C</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>POS</name>
+ <description>Current position value.</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>MAXPOS</name>
+ <description>Maximum position register</description>
+ <addressOffset>0x010</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>MAXPOS</name>
+ <description>Current maximum position value.</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CMPOS0</name>
+ <description>Position compare register 0</description>
+ <addressOffset>0x014</addressOffset>
+ <access>read-write</access>
+ <resetValue>0xFFFFFFFF</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>PCMP0</name>
+ <description>Position compare value 0.</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CMPOS1</name>
+ <description>Position compare register 1</description>
+ <addressOffset>0x018</addressOffset>
+ <access>read-write</access>
+ <resetValue>0xFFFFFFFF</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>PCMP1</name>
+ <description>Position compare value 1.</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CMPOS2</name>
+ <description>Position compare register 2</description>
+ <addressOffset>0x01C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0xFFFFFFFF</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>PCMP2</name>
+ <description>Position compare value 2.</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>INXCNT</name>
+ <description>Index count register 0</description>
+ <addressOffset>0x020</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>ENCPOS</name>
+ <description>Current index counter value.</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>INXCMP0</name>
+ <description>Index compare register 0</description>
+ <addressOffset>0x024</addressOffset>
+ <access>read-write</access>
+ <resetValue>0xFFFFFFFF</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>ICMP0</name>
+ <description>Index compare value 0.</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>LOAD</name>
+ <description>Velocity timer reload register</description>
+ <addressOffset>0x028</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>VELLOAD</name>
+ <description>Current velocity timer load value.</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TIME</name>
+ <description>Velocity timer register</description>
+ <addressOffset>0x02C</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>VELVAL</name>
+ <description>Current velocity timer value.</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>VEL</name>
+ <description>Velocity counter register</description>
+ <addressOffset>0x030</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>VELPC</name>
+ <description>Current velocity pulse count.</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CAP</name>
+ <description>Velocity capture register</description>
+ <addressOffset>0x034</addressOffset>
+ <access>read-only</access>
+ <resetValue>0xFFFFFFFF</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>VELCAP</name>
+ <description>Last velocity capture.</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>VELCOMP</name>
+ <description>Velocity compare register</description>
+ <addressOffset>0x038</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>VELPC</name>
+ <description>Compare velocity pulse count.</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FILTER</name>
+ <description>Digital filter register</description>
+ <addressOffset>0x03C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>FILTA</name>
+ <description>Digital filter sampling delay.</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+
+
+
+
+
+ <register>
+ <name>INTSTAT</name>
+ <description>Interrupt status register</description>
+ <addressOffset>0xFE0</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>INX_INT</name>
+ <description>Indicates that an index pulse was detected.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>TIM_INT</name>
+ <description>Indicates that a velocity timer overflow occurred</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>VELC_INT</name>
+ <description>Indicates that captured velocity is less than compare velocity.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>DIR_INT</name>
+ <description>Indicates that a change of direction was detected.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>ERR_INT</name>
+ <description>Indicates that an encoder phase error was detected.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>ENCLK_INT</name>
+ <description>Indicates that and encoder clock pulse was detected.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>POS0_INT</name>
+ <description>Indicates that the position 0 compare value is equal to the current position.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>POS1_INT</name>
+ <description>Indicates that the position 1compare value is equal to the current position.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>POS2_INT</name>
+ <description>Indicates that the position 2 compare value is equal to the current position.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>REV0_INT</name>
+ <description>Indicates that the index compare 0 value is equal to the current index count.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>POS0REV_INT</name>
+ <description>Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV0_Int is set.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>POS1REV_INT</name>
+ <description>Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV1_Int is set.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>POS2REV_INT</name>
+ <description>Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV2_Int is set.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>REV1_INT</name>
+ <description>Indicates that the index compare 1value is equal to the current index count.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>REV2_INT</name>
+ <description>Indicates that the index compare 2 value is equal to the current index count.</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>MAXPOS_INT</name>
+ <description>Indicates that the current position count goes through the MAXPOS value to zero in the forward direction, or through zero to MAXPOS in the reverse direction.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:16]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SET</name>
+ <description>Interrupt status set register</description>
+ <addressOffset>0xFEC</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>INX_INT</name>
+ <description>Writing a 1 sets the INX_Int bit in QEIINTSTAT.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>TIM_INT</name>
+ <description>Writing a 1 sets the TIN_Int bit in QEIINTSTAT.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>VELC_INT</name>
+ <description>Writing a 1 sets the VELC_Int bit in QEIINTSTAT.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>DIR_INT</name>
+ <description>Writing a 1 sets the DIR_Int bit in QEIINTSTAT.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>ERR_INT</name>
+ <description>Writing a 1 sets the ERR_Int bit in QEIINTSTAT.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>ENCLK_INT</name>
+ <description>Writing a 1 sets the ENCLK_Int bit in QEIINTSTAT.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>POS0_INT</name>
+ <description>Writing a 1 sets the POS0_Int bit in QEIINTSTAT.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>POS1_INT</name>
+ <description>Writing a 1 sets the POS1_Int bit in QEIINTSTAT.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>POS2_INT</name>
+ <description>Writing a 1 sets the POS2_Int bit in QEIINTSTAT.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>REV0_INT</name>
+ <description>Writing a 1 sets the REV0_Int bit in QEIINTSTAT.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>POS0REV_INT</name>
+ <description>Writing a 1 sets the POS0REV_Int bit in QEIINTSTAT.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>POS1REV_INT</name>
+ <description>Writing a 1 sets the POS1REV_Int bit in QEIINTSTAT.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>POS2REV_INT</name>
+ <description>Writing a 1 sets the POS2REV_Int bit in QEIINTSTAT.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>REV1_INT</name>
+ <description>Writing a 1 sets the REV1_Int bit in QEIINTSTAT.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>REV2_INT</name>
+ <description>Writing a 1 sets the REV2_Int bit in QEIINTSTAT.</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>MAXPOS_INT</name>
+ <description>Writing a 1 sets the MAXPOS_Int bit in QEIINTSTAT.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:16]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CLR</name>
+ <description>Interrupt status clear register</description>
+ <addressOffset>0xFE8</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>INX_INT</name>
+ <description>Writing a 1 clears the INX_Int bit in QEIINTSTAT.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>TIM_INT</name>
+ <description>Writing a 1 clears the TIN_Int bit in QEIINTSTAT.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>VELC_INT</name>
+ <description>Writing a 1 clears the VELC_Int bit in QEIINTSTAT.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>DIR_INT</name>
+ <description>Writing a 1 clears the DIR_Int bit in QEIINTSTAT.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>ERR_INT</name>
+ <description>Writing a 1 clears the ERR_Int bit in QEIINTSTAT.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>ENCLK_INT</name>
+ <description>Writing a 1 clears the ENCLK_Int bit in QEIINTSTAT.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>POS0_INT</name>
+ <description>Writing a 1 clears the POS0_Int bit in QEIINTSTAT.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>POS1_INT</name>
+ <description>Writing a 1 clears the POS1_Int bit in QEIINTSTAT.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>POS2_INT</name>
+ <description>Writing a 1 clears the POS2_Int bit in QEIINTSTAT.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>REV0_INT</name>
+ <description>Writing a 1 clears the REV0_Int bit in QEIINTSTAT.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>POS0REV_INT</name>
+ <description>Writing a 1 clears the POS0REV_Int bit in QEIINTSTAT.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>POS1REV_INT</name>
+ <description>Writing a 1 clears the POS1REV_Int bit in QEIINTSTAT.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>POS2REV_INT</name>
+ <description>Writing a 1 clears the POS2REV_Int bit in QEIINTSTAT.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>REV1_INT</name>
+ <description>Writing a 1 clears the REV1_Int bit in QEIINTSTAT.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>REV2_INT</name>
+ <description>Writing a 1 clears the REV2_Int bit in QEIINTSTAT.</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>MAXPOS_INT</name>
+ <description>Writing a 1 clears the MAXPOS_Int bit in QEIINTSTAT.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:16]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IE</name>
+ <description>Interrupt enable register</description>
+ <addressOffset>0xFE4</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>INX_INT</name>
+ <description>When 1, the INX_Int interrupt is enabled.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>TIM_INT</name>
+ <description>When 1, the TIN_Int interrupt is enabled.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>VELC_INT</name>
+ <description>When 1, the VELC_Int interrupt is enabled.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>DIR_INT</name>
+ <description>When 1, the DIR_Int interrupt is enabled.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>ERR_INT</name>
+ <description>When 1, the ERR_Int interrupt is enabled.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>ENCLK_INT</name>
+ <description>When 1, the ENCLK_Int interrupt is enabled.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>POS0_INT</name>
+ <description>When 1, the POS0_Int interrupt is enabled.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>POS1_INT</name>
+ <description>When 1, the POS1_Int interrupt is enabled.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>POS2_INT</name>
+ <description>When 1, the POS2_Int interrupt is enabled.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>REV0_INT</name>
+ <description>When 1, the REV0_Int interrupt is enabled.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>POS0REV_INT</name>
+ <description>When 1, the POS0REV_Int interrupt is enabled.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>POS1REV_INT</name>
+ <description>When 1, the POS1REV_Int interrupt is enabled.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>POS2REV_INT</name>
+ <description>When 1, the POS2REV_Int interrupt is enabled.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>REV1_INT</name>
+ <description>When 1, the REV1_Int interrupt is enabled.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>REV2_INT</name>
+ <description>When 1, the REV2_Int interrupt is enabled.</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>MAXPOS_INT</name>
+ <description>When 1, the MAXPOS_Int interrupt is enabled.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:16]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IES</name>
+ <description>Interrupt enable set register</description>
+ <addressOffset>0xFDC</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>INX_INT</name>
+ <description>Writing a 1 enables the INX_Int interrupt in the QEIIE register.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>TIM_INT</name>
+ <description>Writing a 1 enables the TIN_Int interrupt in the QEIIE register.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>VELC_INT</name>
+ <description>Writing a 1 enables the VELC_Int interrupt in the QEIIE register.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>DIR_INT</name>
+ <description>Writing a 1 enables the DIR_Int interrupt in the QEIIE register.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>ERR_INT</name>
+ <description>Writing a 1 enables the ERR_Int interrupt in the QEIIE register.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>ENCLK_INT</name>
+ <description>Writing a 1 enables the ENCLK_Int interrupt in the QEIIE register.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>POS0_INT</name>
+ <description>Writing a 1 enables the POS0_Int interrupt in the QEIIE register.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>POS1_INT</name>
+ <description>Writing a 1 enables the POS1_Int interrupt in the QEIIE register.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>POS2_INT</name>
+ <description>Writing a 1 enables the POS2_Int interrupt in the QEIIE register.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>REV0_INT</name>
+ <description>Writing a 1 enables the REV0_Int interrupt in the QEIIE register.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>POS0REV_INT</name>
+ <description>Writing a 1 enables the POS0REV_Int interrupt in the QEIIE register.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>POS1REV_INT</name>
+ <description>Writing a 1 enables the POS1REV_Int interrupt in the QEIIE register.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>POS2REV_INT</name>
+ <description>Writing a 1 enables the POS2REV_Int interrupt in the QEIIE register.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>REV1_INT</name>
+ <description>Writing a 1 enables the REV1_Int interrupt in the QEIIE register.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>REV2_INT</name>
+ <description>Writing a 1 enables the REV2_Int interrupt in the QEIIE register.</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>MAXPOS_INT</name>
+ <description>Writing a 1 enables the MAXPOS_Int interrupt in the QEIIE register.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:16]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IEC</name>
+ <description>Interrupt enable clear register</description>
+ <addressOffset>0xFD8</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>INX_INT</name>
+ <description>Writing a 1 disables the INX_Int interrupt in the QEIIE register.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>TIM_INT</name>
+ <description>Writing a 1 disables the TIN_Int interrupt in the QEIIE register.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>VELC_INT</name>
+ <description>Writing a 1 disables the VELC_Int interrupt in the QEIIE register.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>DIR_INT</name>
+ <description>Writing a 1 disables the DIR_Int interrupt in the QEIIE register.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>ERR_INT</name>
+ <description>Writing a 1 disables the ERR_Int interrupt in the QEIIE register.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>ENCLK_INT</name>
+ <description>Writing a 1 disables the ENCLK_Int interrupt in the QEIIE register.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>POS0_INT</name>
+ <description>Writing a 1 disables the POS0_Int interrupt in the QEIIE register.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>POS1_INT</name>
+ <description>Writing a 1 disables the POS1_Int interrupt in the QEIIE register.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>POS2_INT</name>
+ <description>Writing a 1 disables the POS2_Int interrupt in the QEIIE register.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>REV0_INT</name>
+ <description>Writing a 1 disables the REV0_Int interrupt in the QEIIE register.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>POS0REV_INT</name>
+ <description>Writing a 1 disables the POS0REV_Int interrupt in the QEIIE register.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>POS1REV_INT</name>
+ <description>Writing a 1 disables the POS1REV_Int interrupt in the QEIIE register.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>POS2REV_INT</name>
+ <description>Writing a 1 disables the POS2REV_Int interrupt in the QEIIE register.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>REV1_INT</name>
+ <description>Writing a 1 disables the REV1_Int interrupt in the QEIIE register.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>REV2_INT</name>
+ <description>Writing a 1 disables the REV2_Int interrupt in the QEIIE register.</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>MAXPOS_INT</name>
+ <description>Writing a 1 disables the MAXPOS_Int interrupt in the QEIIE register.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:16]</bitRange>
+ </field>
+ </fields>
+ </register>
+ </registers>
+</peripheral>
+
+
+
+
+
+
+
+ <peripheral>
+ <name>SYSCON</name>
+ <description>System and clock control</description>
+ <groupName>SYSCON</groupName>
+ <baseAddress>0x400FC000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0xFFF</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>EINT0</name>
+ <value>18</value>
+ </interrupt>
+ <interrupt>
+ <name>EINT1</name>
+ <value>19</value>
+ </interrupt>
+ <interrupt>
+ <name>EINT2</name>
+ <value>20</value>
+ </interrupt>
+ <interrupt>
+ <name>EINT3</name>
+ <value>21</value>
+ </interrupt>
+ <interrupt>
+ <name>BOD</name>
+ <value>23</value>
+ </interrupt>
+ <interrupt>
+ <name>PLL0</name>
+ <value>16</value>
+ </interrupt>
+ <interrupt>
+ <name>PLL1</name>
+ <value>32</value>
+ </interrupt>
+ <registers>
+
+
+ <register>
+ <name>FLASHCFG</name>
+ <description>Flash Accelerator Configuration Register. Controls flash access timing.</description>
+ <addressOffset>0x000</addressOffset>
+ <access>read-write</access>
+ <resetValue>0x303A</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not change these bits from the reset value.</description>
+ <bitRange>[11:0]</bitRange>
+
+ </field>
+ <field>
+ <name>FLASHTIM</name>
+ <description>Flash access time. The value of this field plus 1 gives the number of CPU clocks used for a flash access. Warning: improper setting of this value may result in incorrect operation of the device. Other values are reserved.</description>
+ <bitRange>[15:12]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>1CLK</name>
+ <description>Flash accesses use 1 CPU clock. Use for up to 20 MHz CPU clock.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>2CLK</name>
+ <description>Flash accesses use 2 CPU clocks. Use for up to 40 MHz CPU clock.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>3CLK</name>
+ <description>Flash accesses use 3 CPU clocks. Use for up to 60 MHz CPU clock.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>4CLK</name>
+ <description>Flash accesses use 4 CPU clocks. Use for up to 80 MHz CPU clock.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>5CLK</name>
+ <description>Flash accesses use 5 CPU clocks. Use for up to 100 MHz CPU clock. Use for up to 120 Mhz for LPC1759 and LPC1769 only.</description>
+ <value>0x4</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>6CLK</name>
+ <description>Flash accesses use 6 CPU clocks. This safe setting will work under any conditions.</description>
+ <value>0x5</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:16]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+
+
+
+
+
+ <register>
+ <name>PLL0CON</name>
+ <description>PLL0 Control Register</description>
+ <addressOffset>0x080</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>PLLE0</name>
+ <description>PLL0 Enable. When one, and after a valid PLL0 feed, this bit will activate PLL0 and allow it to lock to the requested frequency. See PLL0STAT register.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>PLLC0</name>
+ <description>PLL0 Connect. Setting PLLC0 to one after PLL0 has been enabled and locked, then followed by a valid PLL0 feed sequence causes PLL0 to become the clock source for the CPU, AHB peripherals, and used to derive the clocks for APB peripherals. The PLL0 output may potentially be used to clock the USB subsystem if the frequency is 48 MHz. See PLL0STAT register.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:2]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PLL0CFG</name>
+ <description>PLL0 Configuration Register</description>
+ <addressOffset>0x084</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>MSEL0</name>
+ <description>PLL0 Multiplier value. Supplies the value M in PLL0 frequency calculations. The value stored here is M - 1. Note: Not all values of M are needed, and therefore some are not supported by hardware.</description>
+ <bitRange>[14:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>NSEL0</name>
+ <description>PLL0 Pre-Divider value. Supplies the value N in PLL0 frequency calculations. The value stored here is N - 1. Supported values for N are 1 through 32.</description>
+ <bitRange>[23:16]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:24]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PLL0STAT</name>
+ <description>PLL0 Status Register</description>
+ <addressOffset>0x088</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>MSEL0</name>
+ <description>Read-back for the PLL0 Multiplier value. This is the value currently used by PLL0, and is one less than the actual multiplier.</description>
+ <bitRange>[14:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>NSEL0</name>
+ <description>Read-back for the PLL0 Pre-Divider value. This is the value currently used by PLL0, and is one less than the actual divider.</description>
+ <bitRange>[23:16]</bitRange>
+ </field>
+ <field>
+ <name>PLLE0_STAT</name>
+ <description>Read-back for the PLL0 Enable bit. This bit reflects the state of the PLEC0 bit in PLL0CON after a valid PLL0 feed. When one, PLL0 is currently enabled. When zero, PLL0 is turned off. This bit is automatically cleared when Power-down mode is entered.</description>
+ <bitRange>[24:24]</bitRange>
+ </field>
+ <field>
+ <name>PLLC0_STAT</name>
+ <description>Read-back for the PLL0 Connect bit. This bit reflects the state of the PLLC0 bit in PLL0CON after a valid PLL0 feed. When PLLC0 and PLLE0 are both one, PLL0 is connected as the clock source for the CPU. When either PLLC0 or PLLE0 is zero, PLL0 is bypassed. This bit is automatically cleared when Power-down mode is entered.</description>
+ <bitRange>[25:25]</bitRange>
+ </field>
+ <field>
+ <name>PLOCK0</name>
+ <description>Reflects the PLL0 Lock status. When zero, PLL0 is not locked. When one, PLL0 is locked onto the requested frequency. See text for details.</description>
+ <bitRange>[26:26]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:27]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PLL0FEED</name>
+ <description>PLL0 Feed Register</description>
+ <addressOffset>0x08C</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>PLL0FEED</name>
+ <description>The PLL0 feed sequence must be written to this register in order for PLL0 configuration and control register changes to take effect.</description>
+ <bitRange>[7:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PLL1CON</name>
+ <description>PLL1 Control Register</description>
+ <addressOffset>0x0A0</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>PLLE1</name>
+ <description>PLL1 Enable. When one, and after a valid PLL1 feed, this bit will activate PLL1 and allow it to lock to the requested frequency.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>PLLC1</name>
+ <description>PLL1 Connect. Setting PLLC to one after PLL1 has been enabled and locked, then followed by a valid PLL1 feed sequence causes PLL1 to become the clock source for the USB subsystem via the USB clock divider. See PLL1STAT register.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:2]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PLL1CFG</name>
+ <description>PLL1 Configuration Register</description>
+ <addressOffset>0x0A4</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>MSEL1</name>
+ <description>PLL1 Multiplier value. Supplies the value M in the PLL1 frequency calculations.</description>
+ <bitRange>[4:0]</bitRange>
+ </field>
+ <field>
+ <name>PSEL1</name>
+ <description>PLL1 Divider value. Supplies the value P in the PLL1 frequency calculations.</description>
+ <bitRange>[6:5]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:7]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PLL1STAT</name>
+ <description>PLL1 Status Register</description>
+ <addressOffset>0x0A8</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>MSEL1</name>
+ <description>Read-back for the PLL1 Multiplier value. This is the value currently used by PLL1.</description>
+ <bitRange>[4:0]</bitRange>
+ </field>
+ <field>
+ <name>PSEL1</name>
+ <description>Read-back for the PLL1 Divider value. This is the value currently used by PLL1.</description>
+ <bitRange>[6:5]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>PLLE1_STAT</name>
+ <description>Read-back for the PLL1 Enable bit. When one, PLL1 is currently activated. When zero, PLL1 is turned off. This bit is automatically cleared when Power-down mode is activated.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>PLLC1_STAT</name>
+ <description>Read-back for the PLL1 Connect bit. When PLLC and PLLE are both one, PLL1 is connected as the clock source for the microcontroller. When either PLLC or PLLE is zero, PLL1 is bypassed and the oscillator clock is used directly by the microcontroller. This bit is automatically cleared when Power-down mode is activated.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>PLOCK1</name>
+ <description>Reflects the PLL1 Lock status. When zero, PLL1 is not locked. When one, PLL1 is locked onto the requested frequency.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:11]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PLL1FEED</name>
+ <description>PLL1 Feed Register</description>
+ <addressOffset>0x0AC</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>PLL1FEED</name>
+ <description>The PLL1 feed sequence must be written to this register in order for PLL1 configuration and control register changes to take effect.</description>
+ <bitRange>[7:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PCON</name>
+ <description>Power Control Register</description>
+ <addressOffset>0x0C0</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>PM0</name>
+ <description>Power mode control bit 0. This bit controls entry to the Power-down mode.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>PM1</name>
+ <description>Power mode control bit 1. This bit controls entry to the Deep Power-down mode.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>BODRPM</name>
+ <description>Brown-Out Reduced Power Mode. When BODRPM is 1, the Brown-Out Detect circuitry will be turned off when chip Power-down mode or Deep Sleep mode is entered, resulting in a further reduction in power usage. However, the possibility of using Brown-Out Detect as a wake-up source from the reduced power mode will be lost. When 0, the Brown-Out Detect function remains active during Power-down and Deep Sleep modes. See the System Control Block chapter for details of Brown-Out detection.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>BOGD</name>
+ <description>Brown-Out Global Disable. When BOGD is 1, the Brown-Out Detect circuitry is fully disabled at all times, and does not consume power. When 0, the Brown-Out Detect circuitry is enabled. See the System Control Block chapter for details of Brown-Out detection. Note: the Brown-Out Reset Disable (BORD, in this register) and the Brown-Out Interrupt (xx) must be disabled when software changes the value of this bit.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>BORD</name>
+ <description>Brown-Out Reset Disable. When BORD is 1, the BOD will not reset the device when the VDD(REG)(3V3) voltage dips goes below the BOD reset trip level. The Brown-Out interrupt is not affected. When BORD is 0, the BOD reset is enabled.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[7:3]</bitRange>
+ </field>
+ <field>
+ <name>SMFLAG</name>
+ <description>Sleep Mode entry flag. Set when the Sleep mode is successfully entered. Cleared by software writing a one to this bit.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>DSFLAG</name>
+ <description>Deep Sleep entry flag. Set when the Deep Sleep mode is successfully entered. Cleared by software writing a one to this bit.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>PDFLAG</name>
+ <description>Power-down entry flag. Set when the Power-down mode is successfully entered. Cleared by software writing a one to this bit.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>DPDFLAG</name>
+ <description>Deep Power-down entry flag. Set when the Deep Power-down mode is successfully entered. Cleared by software writing a one to this bit.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:12]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PCONP</name>
+ <description>Power Control for Peripherals Register</description>
+ <addressOffset>0x0C4</addressOffset>
+ <access>read-write</access>
+ <resetValue>0x03BE</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>PCTIM0</name>
+ <description>Timer/Counter 0 power/clock control bit.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>PCTIM1</name>
+ <description>Timer/Counter 1 power/clock control bit.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>PCUART0</name>
+ <description>UART0 power/clock control bit.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>PCUART1</name>
+ <description>UART1 power/clock control bit.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>PCPWM1</name>
+ <description>PWM1 power/clock control bit.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>PCI2C0</name>
+ <description>The I2C0 interface power/clock control bit.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>PCSPI</name>
+ <description>The SPI interface power/clock control bit.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>PCRTC</name>
+ <description>The RTC power/clock control bit.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>PCSSP1</name>
+ <description>The SSP 1 interface power/clock control bit.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>PCADC</name>
+ <description>A/D converter (ADC) power/clock control bit. Note: Clear the PDN bit in the AD0CR before clearing this bit, and set this bit before setting PDN.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>PCCAN1</name>
+ <description>CAN Controller 1 power/clock control bit.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>PCCAN2</name>
+ <description>CAN Controller 2 power/clock control bit.</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>PCGPIO</name>
+ <description>Power/clock control bit for IOCON, GPIO, and GPIO interrupts.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>PCRIT</name>
+ <description>Repetitive Interrupt Timer power/clock control bit.</description>
+ <bitRange>[16:16]</bitRange>
+ </field>
+ <field>
+ <name>PCMCPWM</name>
+ <description>Motor Control PWM</description>
+ <bitRange>[17:17]</bitRange>
+ </field>
+ <field>
+ <name>PCQEI</name>
+ <description>Quadrature Encoder Interface power/clock control bit.</description>
+ <bitRange>[18:18]</bitRange>
+ </field>
+ <field>
+ <name>PCI2C1</name>
+ <description>The I2C1 interface power/clock control bit.</description>
+ <bitRange>[19:19]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[20:20]</bitRange>
+ </field>
+ <field>
+ <name>PCSSP0</name>
+ <description>The SSP0 interface power/clock control bit.</description>
+ <bitRange>[21:21]</bitRange>
+ </field>
+ <field>
+ <name>PCTIM2</name>
+ <description>Timer 2 power/clock control bit.</description>
+ <bitRange>[22:22]</bitRange>
+ </field>
+ <field>
+ <name>PCTIM3</name>
+ <description>Timer 3 power/clock control bit.</description>
+ <bitRange>[23:23]</bitRange>
+ </field>
+ <field>
+ <name>PCUART2</name>
+ <description>UART 2 power/clock control bit.</description>
+ <bitRange>[24:24]</bitRange>
+ </field>
+ <field>
+ <name>PCUART3</name>
+ <description>UART 3 power/clock control bit.</description>
+ <bitRange>[25:25]</bitRange>
+ </field>
+ <field>
+ <name>PCI2C2</name>
+ <description>I2C interface 2 power/clock control bit.</description>
+ <bitRange>[26:26]</bitRange>
+ </field>
+ <field>
+ <name>PCI2S</name>
+ <description>I2S interface power/clock control bit.</description>
+ <bitRange>[27:27]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[28:28]</bitRange>
+ </field>
+ <field>
+ <name>PCGPDMA</name>
+ <description>GPDMA function power/clock control bit.</description>
+ <bitRange>[29:29]</bitRange>
+ </field>
+ <field>
+ <name>PCENET</name>
+ <description>Ethernet block power/clock control bit.</description>
+ <bitRange>[30:30]</bitRange>
+ </field>
+ <field>
+ <name>PCUSB</name>
+ <description>USB interface power/clock control bit.</description>
+ <bitRange>[31:31]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CCLKCFG</name>
+ <description>CPU Clock Configuration Register</description>
+ <addressOffset>0x104</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>CCLKSEL</name>
+ <description>Selects the divide value for creating the CPU clock (CCLK) from the PLL0 output. 0 = pllclk is divided by 1 to produce the CPU clock. This setting is not allowed when the PLL0 is connected, because the rate would always be greater than the maximum allowed CPU clock. 1 = pllclk is divided by 2 to produce the CPU clock. This setting is not allowed when the PLL0 is connected, because the rate would always be greater than the maximum allowed CPU clock. 2 = pllclk is divided by 3 to produce the CPU clock. 3 = pllclk is divided by 4 to produce the CPU clock. ... 255 = pllclk is divided by 256 to produce the CPU clock.</description>
+ <bitRange>[7:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>USBCLKCFG</name>
+ <description>USB Clock Configuration Register</description>
+ <addressOffset>0x108</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>USBSEL</name>
+ <description>Selects the divide value for creating the USB clock from the PLL0 output. Only the values shown below can produce even number multiples of 48 MHz from the PLL0 output. Warning: Improper setting of this value will result in incorrect operation of the USB interface. 5 = PLL0 output is divided by 6. PLL0 output must be 288 MHz. 7 = PLL0 output is divided by 8. PLL0 output must be 384 MHz. 9 = PLL0 output is divided by 10. PLL0 output must be 480 MHz.</description>
+ <bitRange>[3:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:4]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CLKSRCSEL</name>
+ <description>Clock Source Select Register</description>
+ <addressOffset>0x10C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>CLKSRC</name>
+ <description>Selects the clock source for PLL0 as follows. Warning: Improper setting of this value, or an incorrect sequence of changing this value may result in incorrect operation of the device.</description>
+ <bitRange>[1:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>SELECTS_THE_INTERNAL</name>
+ <description>Selects the Internal RC oscillator as the PLL0 clock source (default).</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SELECTS_THE_MAIN_OSC</name>
+ <description>Selects the main oscillator as the PLL0 clock source. Select the main oscillator as PLL0 clock source if the PLL0 clock output is used for USB or for CAN with baudrates > 100 kBit/s.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SELECTS_THE_RTC_OSCI</name>
+ <description>Selects the RTC oscillator as the PLL0 clock source.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESERVED</name>
+ <description>Reserved, do not use this setting.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:2]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CANSLEEPCLR</name>
+ <description>Allows clearing the current CAN channel sleep state as well as reading that state.</description>
+ <addressOffset>0x110</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>CAN1SLEEP</name>
+ <description>Sleep status and control for CAN channel 1. Read: when 1, indicates that CAN channel 1 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 1.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>CAN2SLEEP</name>
+ <description>Sleep status and control for CAN channel 2. Read: when 1, indicates that CAN channel 2 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 2.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:3]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CANWAKEFLAGS</name>
+ <description>Allows reading the wake-up state of the CAN channels.</description>
+ <addressOffset>0x114</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>CAN1WAKE</name>
+ <description>Wake-up status for CAN channel 1. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 1. Write: writing a 1 clears this bit.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>CAN2WAKE</name>
+ <description>Wake-up status for CAN channel 2. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 2. Write: writing a 1 clears this bit.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:3]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>EXTINT</name>
+ <description>External Interrupt Flag Register</description>
+ <addressOffset>0x140</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>EINT0</name>
+ <description>In level-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>EINT1</name>
+ <description>In level-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>EINT2</name>
+ <description>In level-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>EINT3</name>
+ <description>In level-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:4]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>EXTMODE</name>
+ <description>External Interrupt Mode register</description>
+ <addressOffset>0x148</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>EXTMODE0</name>
+ <description>External interrupt 0 EINT0 mode.</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>LEVEL_SENSITIVE</name>
+ <description>Level-sensitive. Level-sensitivity is selected for EINT0.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>EDGE_SENSITIVE</name>
+ <description>Edge-sensitive. EINT0 is edge sensitive.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>EXTMODE1</name>
+ <description>External interrupt 1 EINT1 mode.</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>LEVEL_SENSITIVE</name>
+ <description>Level-sensitive. Level-sensitivity is selected for EINT1.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>EDGE_SENSITIVE</name>
+ <description>Edge-sensitive. EINT1 is edge sensitive.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>EXTMODE2</name>
+ <description>External interrupt 2 EINT2 mode.</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>LEVEL_SENSITIVE</name>
+ <description>Level-sensitive. Level-sensitivity is selected for EINT2.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>EDGE_SENSITIVE</name>
+ <description>Edge-sensitive. EINT2 is edge sensitive.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>EXTMODE3</name>
+ <description>External interrupt 3 EINT3 mode.</description>
+ <bitRange>[3:3]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>LEVEL_SENSITIVE</name>
+ <description>Level-sensitive. Level-sensitivity is selected for EINT3.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>EDGE_SENSITIVE</name>
+ <description>Edge-sensitive. EINT3 is edge sensitive.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:4]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>EXTPOLAR</name>
+ <description>External Interrupt Polarity Register</description>
+ <addressOffset>0x14C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>EXTPOLAR0</name>
+ <description>External interrupt 0 EINT0 polarity.</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>FALLING_EDGE</name>
+ <description>Falling edge. EINT0 is low-active or falling-edge sensitive (depending on EXTMODE0).</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RISING_EDGE</name>
+ <description>Rising edge. EINT0 is high-active or rising-edge sensitive (depending on EXTMODE0).</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>EXTPOLAR1</name>
+ <description>External interrupt 1 EINT1 polarity.</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>FALLING_EDGE</name>
+ <description>Falling edge. EINT1 is low-active or falling-edge sensitive (depending on EXTMODE1).</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RISING_EDGE</name>
+ <description>Rising edge. EINT1 is high-active or rising-edge sensitive (depending on EXTMODE1).</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>EXTPOLAR2</name>
+ <description>External interrupt 2 EINT2 polarity.</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>FALLING_EDGE</name>
+ <description>Falling edge. EINT2 is low-active or falling-edge sensitive (depending on EXTMODE2).</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RISING_EDGE</name>
+ <description>Rising edge. EINT2 is high-active or rising-edge sensitive (depending on EXTMODE2).</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>EXTPOLAR3</name>
+ <description>External interrupt 3 EINT3 polarity.</description>
+ <bitRange>[3:3]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>FALLING_EDGE</name>
+ <description>Falling edge. EINT3 is low-active or falling-edge sensitive (depending on EXTMODE3).</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RISING_EDGE</name>
+ <description>Rising edge. EINT3 is high-active or rising-edge sensitive (depending on EXTMODE3).</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:4]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RSID</name>
+ <description>Reset Source Identification Register</description>
+ <addressOffset>0x180</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>POR</name>
+ <description>Assertion of the POR signal sets this bit, and clears all of the other bits in this register. But if another Reset signal (e.g., External Reset) remains asserted after the POR signal is negated, then its bit is set. This bit is not affected by any of the other sources of Reset.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>EXTR</name>
+ <description>Assertion of the RESET signal sets this bit. This bit is cleared only by software or POR.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>WDTR</name>
+ <description>This bit is set when the Watchdog Timer times out and the WDTRESET bit in the Watchdog Mode Register is 1. This bit is cleared only by software or POR.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>BODR</name>
+ <description>This bit is set when the VDD(REG)(3V3) voltage reaches a level below the BOD reset trip level (typically 1.85 V under nominal room temperature conditions). If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and recovers, the BODR bit will be set to 1. If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and continues to decline to the level at which POR is asserted (nominally 1 V), the BODR bit is cleared. If the VDD(REG)(3V3) voltage rises continuously from below 1 V to a level above the BOD reset trip level, the BODR will be set to 1. This bit is cleared only by software or POR. Note: Only in the case where a reset occurs and the POR = 0, the BODR bit indicates if the VDD(REG)(3V3) voltage was below the BOD reset trip level or not.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:4]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SCS</name>
+ <description>System control and status</description>
+ <addressOffset>0x1A0</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[3:0]</bitRange>
+
+ </field>
+ <field>
+ <name>OSCRANGE</name>
+ <description>Main oscillator range select.</description>
+ <bitRange>[4:4]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>LOW</name>
+ <description>Low. The frequency range of the main oscillator is 1 MHz to 20 MHz.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>HIGH</name>
+ <description>High. The frequency range of the main oscillator is 15 MHz to 25 MHz.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>OSCEN</name>
+ <description>Main oscillator enable.</description>
+ <bitRange>[5:5]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disabled. The main oscillator is disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLED</name>
+ <description>Enabled.The main oscillator is enabled, and will start up if the correct external circuitry is connected to the XTAL1 and XTAL2 pins.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>OSCSTAT</name>
+ <description>Main oscillator status.</description>
+ <bitRange>[6:6]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>NOT_READY</name>
+ <description>Not ready. The main oscillator is not ready to be used as a clock source.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>READY</name>
+ <description>Ready. The main oscillator is ready to be used as a clock source. The main oscillator must be enabled via the OSCEN bit.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:7]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PCLKSEL0</name>
+ <description>Peripheral Clock Selection register 0.</description>
+ <addressOffset>0x1A8</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>PCLK_WDT</name>
+ <description>Peripheral clock selection for WDT.</description>
+ <bitRange>[1:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>CCLK_DIV_4</name>
+ <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK</name>
+ <description>CCLK. PCLK_peripheral = CCLK</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_2</name>
+ <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_8</name>
+ <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PCLK_TIMER0</name>
+ <description>Peripheral clock selection for TIMER0.</description>
+ <bitRange>[3:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>CCLK_DIV_4</name>
+ <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK</name>
+ <description>CCLK. PCLK_peripheral = CCLK</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_2</name>
+ <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_8</name>
+ <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PCLK_TIMER1</name>
+ <description>Peripheral clock selection for TIMER1.</description>
+ <bitRange>[5:4]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>CCLK_DIV_4</name>
+ <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK</name>
+ <description>CCLK. PCLK_peripheral = CCLK</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_2</name>
+ <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_8</name>
+ <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PCLK_UART0</name>
+ <description>Peripheral clock selection for UART0.</description>
+ <bitRange>[7:6]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>CCLK_DIV_4</name>
+ <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK</name>
+ <description>CCLK. PCLK_peripheral = CCLK</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_2</name>
+ <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_8</name>
+ <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PCLK_UART1</name>
+ <description>Peripheral clock selection for UART1.</description>
+ <bitRange>[9:8]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>CCLK_DIV_4</name>
+ <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK</name>
+ <description>CCLK. PCLK_peripheral = CCLK</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_2</name>
+ <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_8</name>
+ <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[11:10]</bitRange>
+
+ </field>
+ <field>
+ <name>PCLK_PWM1</name>
+ <description>Peripheral clock selection for PWM1.</description>
+ <bitRange>[13:12]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>CCLK_DIV_4</name>
+ <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK</name>
+ <description>CCLK. PCLK_peripheral = CCLK</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_2</name>
+ <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_8</name>
+ <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PCLK_I2C0</name>
+ <description>Peripheral clock selection for I2C0.</description>
+ <bitRange>[15:14]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>CCLK_DIV_4</name>
+ <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK</name>
+ <description>CCLK. PCLK_peripheral = CCLK</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_2</name>
+ <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_8</name>
+ <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PCLK_SPI</name>
+ <description>Peripheral clock selection for SPI.</description>
+ <bitRange>[17:16]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>CCLK_DIV_4</name>
+ <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK</name>
+ <description>CCLK. PCLK_peripheral = CCLK</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_2</name>
+ <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_8</name>
+ <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[19:18]</bitRange>
+
+ </field>
+ <field>
+ <name>PCLK_SSP1</name>
+ <description>Peripheral clock selection for SSP1.</description>
+ <bitRange>[21:20]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>CCLK_DIV_4</name>
+ <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK</name>
+ <description>CCLK. PCLK_peripheral = CCLK</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_2</name>
+ <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_8</name>
+ <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PCLK_DAC</name>
+ <description>Peripheral clock selection for DAC.</description>
+ <bitRange>[23:22]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>CCLK_DIV_4</name>
+ <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK</name>
+ <description>CCLK. PCLK_peripheral = CCLK</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_2</name>
+ <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_8</name>
+ <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PCLK_ADC</name>
+ <description>Peripheral clock selection for ADC.</description>
+ <bitRange>[25:24]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>CCLK_DIV_4</name>
+ <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK</name>
+ <description>CCLK. PCLK_peripheral = CCLK</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_2</name>
+ <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_8</name>
+ <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PCLK_CAN1</name>
+ <description>Peripheral clock selection for CAN1.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used.</description>
+ <bitRange>[27:26]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>CCLK_DIV_4</name>
+ <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK</name>
+ <description>CCLK. PCLK_peripheral = CCLK</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_2</name>
+ <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_6</name>
+ <description>CCLK div 6. PCLK_peripheral = CCLK/6.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PCLK_CAN2</name>
+ <description>Peripheral clock selection for CAN2.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used.</description>
+ <bitRange>[29:28]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>CCLK_DIV_4</name>
+ <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK</name>
+ <description>CCLK. PCLK_peripheral = CCLK</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_2</name>
+ <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_6</name>
+ <description>CCLK div 6. PCLK_peripheral = CCLK/6,</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PCLK_ACF</name>
+ <description>Peripheral clock selection for CAN acceptance filtering.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used.</description>
+ <bitRange>[31:30]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>CCLK_DIV_4</name>
+ <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK</name>
+ <description>CCLK. PCLK_peripheral = CCLK</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_2</name>
+ <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_6</name>
+ <description>CCLK div 6. PCLK_peripheral = CCLK/6</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>PCLKSEL1</name>
+ <description>Peripheral Clock Selection register 1.</description>
+ <addressOffset>0x1AC</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>PCLK_QEI</name>
+ <description>Peripheral clock selection for the Quadrature Encoder Interface.</description>
+ <bitRange>[1:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>CCLK_DIV_4</name>
+ <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK</name>
+ <description>CCLK. PCLK_peripheral = CCLK</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_2</name>
+ <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_8</name>
+ <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PCLK_GPIOINT</name>
+ <description>Peripheral clock selection for GPIO interrupts.</description>
+ <bitRange>[3:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>CCLK_DIV_4</name>
+ <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK</name>
+ <description>CCLK. PCLK_peripheral = CCLK</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_2</name>
+ <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_8</name>
+ <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PCLK_PCB</name>
+ <description>Peripheral clock selection for the Pin Connect block.</description>
+ <bitRange>[5:4]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>CCLK_DIV_4</name>
+ <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK</name>
+ <description>CCLK. PCLK_peripheral = CCLK</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_2</name>
+ <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_8</name>
+ <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PCLK_I2C1</name>
+ <description>Peripheral clock selection for I2C1.</description>
+ <bitRange>[7:6]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>CCLK_DIV_4</name>
+ <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK</name>
+ <description>CCLK. PCLK_peripheral = CCLK</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_2</name>
+ <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_8</name>
+ <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[9:8]</bitRange>
+
+ </field>
+ <field>
+ <name>PCLK_SSP0</name>
+ <description>Peripheral clock selection for SSP0.</description>
+ <bitRange>[11:10]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>CCLK_DIV_4</name>
+ <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK</name>
+ <description>CCLK. PCLK_peripheral = CCLK</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_2</name>
+ <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_8</name>
+ <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PCLK_TIMER2</name>
+ <description>Peripheral clock selection for TIMER2.</description>
+ <bitRange>[13:12]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>CCLK_DIV_4</name>
+ <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK</name>
+ <description>CCLK. PCLK_peripheral = CCLK</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_2</name>
+ <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_8</name>
+ <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PCLK_TIMER3</name>
+ <description>Peripheral clock selection for TIMER3.</description>
+ <bitRange>[15:14]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>CCLK_DIV_4</name>
+ <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK</name>
+ <description>CCLK. PCLK_peripheral = CCLK</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_2</name>
+ <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_8</name>
+ <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PCLK_UART2</name>
+ <description>Peripheral clock selection for UART2.</description>
+ <bitRange>[17:16]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>CCLK_DIV_4</name>
+ <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK</name>
+ <description>CCLK. PCLK_peripheral = CCLK</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_2</name>
+ <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_8</name>
+ <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PCLK_UART3</name>
+ <description>Peripheral clock selection for UART3.</description>
+ <bitRange>[19:18]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>CCLK_DIV_4</name>
+ <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK</name>
+ <description>CCLK. PCLK_peripheral = CCLK</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_2</name>
+ <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_8</name>
+ <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PCLK_I2C2</name>
+ <description>Peripheral clock selection for I2C2.</description>
+ <bitRange>[21:20]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>CCLK_DIV_4</name>
+ <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK</name>
+ <description>CCLK. PCLK_peripheral = CCLK</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_2</name>
+ <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_8</name>
+ <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PCLK_I2S</name>
+ <description>Peripheral clock selection for I2S.</description>
+ <bitRange>[23:22]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>CCLK_DIV_4</name>
+ <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK</name>
+ <description>CCLK. PCLK_peripheral = CCLK</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_2</name>
+ <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_8</name>
+ <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved.</description>
+ <bitRange>[25:24]</bitRange>
+
+ </field>
+ <field>
+ <name>PCLK_RIT</name>
+ <description>Peripheral clock selection for Repetitive Interrupt Timer.</description>
+ <bitRange>[27:26]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>CCLK_DIV_4</name>
+ <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK</name>
+ <description>CCLK. PCLK_peripheral = CCLK</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_2</name>
+ <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_8</name>
+ <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PCLK_SYSCON</name>
+ <description>Peripheral clock selection for the System Control block.</description>
+ <bitRange>[29:28]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>CCLK_DIV_4</name>
+ <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK</name>
+ <description>CCLK. PCLK_peripheral = CCLK</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_2</name>
+ <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_8</name>
+ <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PCLK_MC</name>
+ <description>Peripheral clock selection for the Motor Control PWM.</description>
+ <bitRange>[31:30]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>CCLK_DIV_4</name>
+ <description>CCLK div 4. PCLK_peripheral = CCLK/4</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK</name>
+ <description>CCLK. PCLK_peripheral = CCLK</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_2</name>
+ <description>CCLK div 2. PCLK_peripheral = CCLK/2</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>CCLK_DIV_8</name>
+ <description>CCLK div 8. PCLK_peripheral = CCLK/8</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>USBINTST</name>
+ <description>USB Interrupt Status</description>
+ <addressOffset>0x1C0</addressOffset>
+ <access>read-write</access>
+ <resetValue>0x80000000</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>USB_INT_REQ_LP</name>
+ <description>Low priority interrupt line status. This bit is read-only.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>USB_INT_REQ_HP</name>
+ <description>High priority interrupt line status. This bit is read-only.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>USB_INT_REQ_DMA</name>
+ <description>DMA interrupt line status. This bit is read-only.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>USB_HOST_INT</name>
+ <description>USB host interrupt line status. This bit is read-only.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>USB_ATX_INT</name>
+ <description>External ATX interrupt line status. This bit is read-only.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>USB_OTG_INT</name>
+ <description>OTG interrupt line status. This bit is read-only.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>USB_I2C_INT</name>
+ <description>I2C module interrupt line status. This bit is read-only.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>USB_NEED_CLK</name>
+ <description>USB need clock indicator. This bit is read-only. This bit is set to 1 when USB activity or a change of state on the USB data pins is detected, and it indicates that a PLL supplied clock of 48 MHz is needed. Once USB_NEED_CLK becomes one, it resets to zero 5 ms after the last packet has been received/sent, or 2 ms after the Suspend Change (SUS_CH) interrupt has occurred. A change of this bit from 0 to 1 can wake up the microcontroller if activity on the USB bus is selected to wake up the part from the Power-down mode (see Section 4.7.9 Wake-up from Reduced Power Modes for details). Also see Section 4.5.8 PLLs and Power-down mode and Section 4.7.10 Power Control for Peripherals register (PCONP - 0x400F C0C4) for considerations about the PLL and invoking the Power-down mode. This bit is read-only.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[30:9]</bitRange>
+ </field>
+ <field>
+ <name>EN_USB_INTS</name>
+ <description>Enable all USB interrupts. When this bit is cleared, the NVIC does not see the ORed output of the USB interrupt lines.</description>
+ <bitRange>[31:31]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMACREQSEL</name>
+ <description>Selects between alternative requests on DMA channels 0 through 7 and 10 through 15</description>
+ <addressOffset>0x1C4</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>DMASEL08</name>
+ <description>Selects the DMA request for GPDMA input 8: 0 - uart0 tx 1 - Timer 0 match 0 is selected.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>DMASEL09</name>
+ <description>Selects the DMA request for GPDMA input 9: 0 - uart0 rx 1 - Timer 0 match 1 is selected.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>DMASEL10</name>
+ <description>Selects the DMA request for GPDMA input 10: 0 - uart1 tx is selected. 1 - Timer 1 match 0 is selected.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>DMASEL11</name>
+ <description>Selects the DMA request for GPDMA input 11: 0 - uart1 rx is selected. 1 - Timer 1 match 1 is selected.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>DMASEL12</name>
+ <description>Selects the DMA request for GPDMA input 12: 0 - uart2 tx is selected. 1 - Timer 2 match 0 is selected.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>DMASEL13</name>
+ <description>Selects the DMA request for GPDMA input 13: 0 - uart2 rx is selected. 1 - Timer 2 match 1 is selected.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>DMASEL14</name>
+ <description>Selects the DMA request for GPDMA input 14: 0 - uart3 tx is selected. 1 - I2S channel 0 is selected.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>DMASEL15</name>
+ <description>Selects the DMA request for GPDMA input 15: 0 - uart3 rx is selected. 1 - I2S channel 1 is selected.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+
+ </fields>
+ </register>
+ <register>
+ <name>CLKOUTCFG</name>
+ <description>Clock Output Configuration Register</description>
+ <addressOffset>0x1C8</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>CLKOUTSEL</name>
+ <description>Selects the clock source for the CLKOUT function. Other values are reserved. Do not use.</description>
+ <bitRange>[3:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>SELECTS_THE_CPU_CLOC</name>
+ <description>Selects the CPU clock as the CLKOUT source.</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SELECTS_THE_MAIN_OSC</name>
+ <description>Selects the main oscillator as the CLKOUT source.</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SELECTS_THE_INTERNAL</name>
+ <description>Selects the Internal RC oscillator as the CLKOUT source.</description>
+ <value>0x2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SELECTS_THE_USB_CLOC</name>
+ <description>Selects the USB clock as the CLKOUT source.</description>
+ <value>0x3</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SELECTS_THE_RTC_OSCI</name>
+ <description>Selects the RTC oscillator as the CLKOUT source.</description>
+ <value>0x4</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CLKOUTDIV</name>
+ <description>Integer value to divide the output clock by, minus one. 0 = Clock is divided by 1 1 = Clock is divided by 2. 2 = Clock is divided by 3. ... 15 = Clock is divided by 16.</description>
+ <bitRange>[7:4]</bitRange>
+
+ </field>
+ <field>
+ <name>CLKOUT_EN</name>
+ <description>CLKOUT enable control, allows switching the CLKOUT source without glitches. Clear to stop CLKOUT on the next falling edge. Set to enable CLKOUT.</description>
+ <bitRange>[8:8]</bitRange>
+
+ </field>
+ <field>
+ <name>CLKOUT_ACT</name>
+ <description>CLKOUT activity indication. Reads as 1 when CLKOUT is enabled. Read as 0 when CLKOUT has been disabled via the CLKOUT_EN bit and the clock has completed being stopped.</description>
+ <bitRange>[9:9]</bitRange>
+
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:10]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+
+</registers>
+
+
+
+
+
+
+</peripheral>
+
+
+ <peripheral>
+ <name>EMAC</name>
+ <description>Ethernet</description>
+ <groupName>ETHERNET</groupName>
+ <baseAddress>0x50000000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0xFFF</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>ENET</name>
+ <value>28</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>MAC1</name>
+ <description>MAC configuration register 1.</description>
+ <addressOffset>0x000</addressOffset>
+ <access>read-write</access>
+ <resetValue>0x8000</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RXENABLE</name>
+ <description>RECEIVE ENABLE. Set this to allow receive frames to be received. Internally the MAC synchronizes this control bit to the incoming receive stream.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>PARF</name>
+ <description>PASS ALL RECEIVE FRAMES. When enabled (set to 1), the MAC will pass all frames regardless of type (normal vs. Control). When disabled, the MAC does not pass valid Control frames.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>RXFLOWCTRL</name>
+ <description>RX FLOW CONTROL. When enabled (set to 1), the MAC acts upon received PAUSE Flow Control frames. When disabled, received PAUSE Flow Control frames are ignored.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>TXFLOWCTRL</name>
+ <description>TX FLOW CONTROL. When enabled (set to 1), PAUSE Flow Control frames are allowed to be transmitted. When disabled, Flow Control frames are blocked.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>LOOPBACK</name>
+ <description>Setting this bit will cause the MAC Transmit interface to be looped back to the MAC Receive interface. Clearing this bit results in normal operation.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused</description>
+ <bitRange>[7:5]</bitRange>
+ </field>
+ <field>
+ <name>RESETTX</name>
+ <description>Setting this bit will put the Transmit Function logic in reset.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>RESETMCSTX</name>
+ <description>Setting this bit resets the MAC Control Sublayer / Transmit logic. The MCS logic implements flow control.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>RESETRX</name>
+ <description>Setting this bit will put the Ethernet receive logic in reset.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>RESETMCSRX</name>
+ <description>Setting this bit resets the MAC Control Sublayer / Receive logic. The MCS logic implements flow control.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[13:12]</bitRange>
+ </field>
+ <field>
+ <name>SIMRESET</name>
+ <description>SIMULATION RESET. Setting this bit will cause a reset to the random number generator within the Transmit Function.</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>SOFTRESET</name>
+ <description>SOFT RESET. Setting this bit will put all modules within the MAC in reset except the Host Interface.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:16]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>MAC2</name>
+ <description>MAC configuration register 2.</description>
+ <addressOffset>0x004</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>FULLDUPLEX</name>
+ <description>When enabled (set to 1), the MAC operates in Full-Duplex mode. When disabled, the MAC operates in Half-Duplex mode.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>FLC</name>
+ <description>FRAMELENGTH CHECKING. When enabled (set to 1), both transmit and receive frame lengths are compared to the Length/Type field. If the Length/Type field represents a length then the check is performed. Mismatches are reported in the StatusInfo word for each received frame.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>HFEN</name>
+ <description>HUGE FRAME ENABLEWhen enabled (set to 1), frames of any length are transmitted and received.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>DELAYEDCRC</name>
+ <description>DELAYED CRC. This bit determines the number of bytes, if any, of proprietary header information that exist on the front of IEEE 802.3 frames. When 1, four bytes of header (ignored by the CRC function) are added. When 0, there is no proprietary header.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>CRCEN</name>
+ <description>CRC ENABLESet this bit to append a CRC to every frame whether padding was required or not. Must be set if PAD/CRC ENABLE is set. Clear this bit if frames presented to the MAC contain a CRC.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>PADCRCEN</name>
+ <description>PAD CRC ENABLE. Set this bit to have the MAC pad all short frames. Clear this bit if frames presented to the MAC have a valid length. This bit is used in conjunction with AUTO PAD ENABLE and VLAN PAD ENABLE. See Table 153 - Pad Operation for details on the pad function.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>VLANPADEN</name>
+ <description>VLAN PAD ENABLE. Set this bit to cause the MAC to pad all short frames to 64 bytes and append a valid CRC. Consult Table 153 - Pad Operation for more information on the various padding features. Note: This bit is ignored if PAD / CRC ENABLE is cleared.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>AUTODETPADEN</name>
+ <description>AUTODETECTPAD ENABLE. Set this bit to cause the MAC to automatically detect the type of frame, either tagged or un-tagged, by comparing the two octets following the source address with 0x8100 (VLAN Protocol ID) and pad accordingly. Table 153 - Pad Operation provides a description of the pad function based on the configuration of this register. Note: This bit is ignored if PAD / CRC ENABLE is cleared.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>PPENF</name>
+ <description>PURE PREAMBLE ENFORCEMEN. When enabled (set to 1), the MAC will verify the content of the preamble to ensure it contains 0x55 and is error-free. A packet with an incorrect preamble is discarded. When disabled, no preamble checking is performed.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>LPENF</name>
+ <description>LONG PREAMBLE ENFORCEMENT. When enabled (set to 1), the MAC only allows receive packets which contain preamble fields less than 12 bytes in length. When disabled, the MAC allows any length preamble as per the Standard.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[11:10]</bitRange>
+ </field>
+ <field>
+ <name>NOBACKOFF</name>
+ <description>When enabled (set to 1), the MAC will immediately retransmit following a collision rather than using the Binary Exponential Backoff algorithm as specified in the Standard.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>BP_NOBACKOFF</name>
+ <description>BACK PRESSURE / NO BACKOFF. When enabled (set to 1), after the MAC incidentally causes a collision during back pressure, it will immediately retransmit without backoff, reducing the chance of further collisions and ensuring transmit packets get sent.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>EXCESSDEFER</name>
+ <description>When enabled (set to 1) the MAC will defer to carrier indefinitely as per the Standard. When disabled, the MAC will abort when the excessive deferral limit is reached.</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:15]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IPGT</name>
+ <description>Back-to-Back Inter-Packet-Gap register.</description>
+ <addressOffset>0x008</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>BTOBINTEGAP</name>
+ <description>BACK-TO-BACK INTER-PACKET-GAP.This is a programmable field representing the nibble time offset of the minimum possible period between the end of any transmitted packet to the beginning of the next. In Full-Duplex mode, the register value should be the desired period in nibble times minus 3. In Half-Duplex mode, the register value should be the desired period in nibble times minus 6. In Full-Duplex the recommended setting is 0x15 (21d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode). In Half-Duplex the recommended setting is 0x12 (18d), which also represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode).</description>
+ <bitRange>[6:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:7]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>IPGR</name>
+ <description>Non Back-to-Back Inter-Packet-Gap register.</description>
+ <addressOffset>0x00C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>NBTOBINTEGAP2</name>
+ <description>NON-BACK-TO-BACK INTER-PACKET-GAP PART2. This is a programmable field representing the Non-Back-to-Back Inter-Packet-Gap. The recommended value is 0x12 (18d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode).</description>
+ <bitRange>[6:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>NBTOBINTEGAP1</name>
+ <description>NON-BACK-TO-BACK INTER-PACKET-GAP PART1. This is a programmable field representing the optional carrierSense window referenced in IEEE 802.3/4.2.3.2.1 'Carrier Deference'. If carrier is detected during the timing of IPGR1, the MAC defers to carrier. If, however, carrier becomes active after IPGR1, the MAC continues timing IPGR2 and transmits, knowingly causing a collision, thus ensuring fair access to medium. Its range of values is 0x0 to IPGR2. The recommended value is 0xC (12d)</description>
+ <bitRange>[14:8]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:15]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CLRT</name>
+ <description>Collision window / Retry register.</description>
+ <addressOffset>0x010</addressOffset>
+ <access>read-write</access>
+ <resetValue>0x370F</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RETRANSMAX</name>
+ <description>RETRANSMISSION MAXIMUM.This is a programmable field specifying the number of retransmission attempts following a collision before aborting the packet due to excessive collisions. The Standard specifies the attemptLimit to be 0xF (15d). See IEEE 802.3/4.2.3.2.5.</description>
+ <bitRange>[3:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[7:4]</bitRange>
+ </field>
+ <field>
+ <name>COLLWIN</name>
+ <description>COLLISION WINDOW. This is a programmable field representing the slot time or collision window during which collisions occur in properly configured networks. The default value of 0x37 (55d) represents a 56 byte window following the preamble and SFD.</description>
+ <bitRange>[13:8]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:14]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>MAXF</name>
+ <description>Maximum Frame register.</description>
+ <addressOffset>0x014</addressOffset>
+ <access>read-write</access>
+ <resetValue>0x0600</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>MAXFLEN</name>
+ <description>MAXIMUM FRAME LENGTH. This field resets to the value 0x0600, which represents a maximum receive frame of 1536 octets. An untagged maximum size Ethernet frame is 1518 octets. A tagged frame adds four octets for a total of 1522 octets. If a shorter maximum length restriction is desired, program this 16-bit field.</description>
+ <bitRange>[15:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused</description>
+ <bitRange>[31:16]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SUPP</name>
+ <description>PHY Support register.</description>
+ <addressOffset>0x018</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused</description>
+ <bitRange>[7:0]</bitRange>
+ </field>
+ <field>
+ <name>SPEED</name>
+ <description>This bit configures the Reduced MII logic for the current operating speed. When set, 100 Mbps mode is selected. When cleared, 10 Mbps mode is selected.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused</description>
+ <bitRange>[31:9]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TEST</name>
+ <description>Test register.</description>
+ <addressOffset>0x01C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>SCPQ</name>
+ <description>SHORTCUT PAUSE QUANTA. This bit reduces the effective PAUSE quanta from 64 byte-times to 1 byte-time.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>TESTPAUSE</name>
+ <description>This bit causes the MAC Control sublayer to inhibit transmissions, just as if a PAUSE Receive Control frame with a nonzero pause time parameter was received.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>TESTBP</name>
+ <description>TEST BACKPRESSURE. Setting this bit will cause the MAC to assert backpressure on the link. Backpressure causes preamble to be transmitted, raising carrier sense. A transmit packet from the system will be sent during backpressure.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused</description>
+ <bitRange>[31:3]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>MCFG</name>
+ <description>MII Mgmt Configuration register.</description>
+ <addressOffset>0x020</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>SCANINC</name>
+ <description>SCAN INCREMENT. Set this bit to cause the MII Management hardware to perform read cycles across a range of PHYs. When set, the MII Management hardware will perform read cycles from address 1 through the value set in PHY ADDRESS[4:0]. Clear this bit to allow continuous reads of the same PHY.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>SUPPPREAMBLE</name>
+ <description>SUPPRESS PREAMBLE. Set this bit to cause the MII Management hardware to perform read/write cycles without the 32-bit preamble field. Clear this bit to cause normal cycles to be performed. Some PHYs support suppressed preamble.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>CLOCKSEL</name>
+ <description>CLOCK SELECT. This field is used by the clock divide logic in creating the MII Management Clock (MDC) which IEEE 802.3u defines to be no faster than 2.5 MHz. Some PHYs support clock rates up to 12.5 MHz, however. The AHB bus clock (HCLK) is divided by the specified amount. Refer to Table 160 below for the definition of values for this field.</description>
+ <bitRange>[5:2]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused</description>
+ <bitRange>[14:6]</bitRange>
+ </field>
+ <field>
+ <name>RESETMIIMGMT</name>
+ <description>RESET MII MGMT. This bit resets the MII Management hardware.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused</description>
+ <bitRange>[31:16]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>MCMD</name>
+ <description>MII Mgmt Command register.</description>
+ <addressOffset>0x024</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>READ</name>
+ <description>This bit causes the MII Management hardware to perform a single Read cycle. The Read data is returned in Register MRDD (MII Mgmt Read Data).</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>SCAN</name>
+ <description>This bit causes the MII Management hardware to perform Read cycles continuously. This is useful for monitoring Link Fail for example.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused</description>
+ <bitRange>[31:2]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>MADR</name>
+ <description>MII Mgmt Address register.</description>
+ <addressOffset>0x028</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>REGADDR</name>
+ <description>REGISTER ADDRESS. This field represents the 5-bit Register Address field of Mgmt cycles. Up to 32 registers can be accessed.</description>
+ <bitRange>[4:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused</description>
+ <bitRange>[7:5]</bitRange>
+ </field>
+ <field>
+ <name>PHYADDR</name>
+ <description>PHY ADDRESS. This field represents the 5-bit PHY Address field of Mgmt cycles. Up to 31 PHYs can be addressed (0 is reserved).</description>
+ <bitRange>[12:8]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused</description>
+ <bitRange>[31:13]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>MWTD</name>
+ <description>MII Mgmt Write Data register.</description>
+ <addressOffset>0x02C</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>WRITEDATA</name>
+ <description>WRITE DATA. When written, an MII Mgmt write cycle is performed using the 16-bit data and the pre-configured PHY and Register addresses from the MII Mgmt Address register (MADR).</description>
+ <bitRange>[15:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused</description>
+ <bitRange>[31:16]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>MRDD</name>
+ <description>MII Mgmt Read Data register.</description>
+ <addressOffset>0x030</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>READDATA</name>
+ <description>READ DATA. Following an MII Mgmt Read Cycle, the 16-bit data can be read from this location.</description>
+ <bitRange>[15:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused</description>
+ <bitRange>[31:16]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>MIND</name>
+ <description>MII Mgmt Indicators register.</description>
+ <addressOffset>0x034</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>BUSY</name>
+ <description>When 1 is returned - indicates MII Mgmt is currently performing an MII Mgmt Read or Write cycle.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>SCANNING</name>
+ <description>When 1 is returned - indicates a scan operation (continuous MII Mgmt Read cycles) is in progress.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>NOTVALID</name>
+ <description>When 1 is returned - indicates MII Mgmt Read cycle has not completed and the Read Data is not yet valid.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>MIILINKFAIL</name>
+ <description>When 1 is returned - indicates that an MII Mgmt link fail has occurred.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused</description>
+ <bitRange>[31:4]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SA0</name>
+ <description>Station Address 0 register.</description>
+ <addressOffset>0x040</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>SADDR2</name>
+ <description>STATION ADDRESS, 2nd octet. This field holds the second octet of the station address.</description>
+ <bitRange>[7:0]</bitRange>
+ </field>
+ <field>
+ <name>SADDR1</name>
+ <description>STATION ADDRESS, 1st octet. This field holds the first octet of the station address.</description>
+ <bitRange>[15:8]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused</description>
+ <bitRange>[31:16]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SA1</name>
+ <description>Station Address 1 register.</description>
+ <addressOffset>0x044</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>SADDR4</name>
+ <description>STATION ADDRESS, 4th octet. This field holds the fourth octet of the station address.</description>
+ <bitRange>[7:0]</bitRange>
+ </field>
+ <field>
+ <name>SADDR3</name>
+ <description>STATION ADDRESS, 3rd octet. This field holds the third octet of the station address.</description>
+ <bitRange>[15:8]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused</description>
+ <bitRange>[31:16]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SA2</name>
+ <description>Station Address 2 register.</description>
+ <addressOffset>0x048</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>SADDR6</name>
+ <description>STATION ADDRESS, 6th octet. This field holds the sixth octet of the station address.</description>
+ <bitRange>[7:0]</bitRange>
+ </field>
+ <field>
+ <name>SADDR5</name>
+ <description>STATION ADDRESS, 5th octet. This field holds the fifth octet of the station address.</description>
+ <bitRange>[15:8]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused</description>
+ <bitRange>[31:16]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>COMMAND</name>
+ <description>Command register.</description>
+ <addressOffset>0x100</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RXENABLE</name>
+ <description>Enable receive.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>TXENABLE</name>
+ <description>Enable transmit.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>REGRESET</name>
+ <description>When a 1 is written, all datapaths and the host registers are reset. The MAC needs to be reset separately.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>TXRESET</name>
+ <description>When a 1 is written, the transmit datapath is reset.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>RXRESET</name>
+ <description>When a 1 is written, the receive datapath is reset.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>PASSRUNTFRAME</name>
+ <description>When set to 1 , passes runt frames s1maller than 64 bytes to memory unless they have a CRC error. If 0 runt frames are filtered out.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>PASSRXFILTER</name>
+ <description>When set to 1 , disables receive filtering i.e. all frames received are written to memory.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>TXFLOWCONTROL</name>
+ <description>Enable IEEE 802.3 / clause 31 flow control sending pause frames in full duplex and continuous preamble in half duplex.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>RMII</name>
+ <description>When set to 1 , RMII mode is selected; if 0, MII mode is selected.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>FULLDUPLEX</name>
+ <description>When set to 1 , indicates full duplex operation.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused</description>
+ <bitRange>[31:11]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>STATUS</name>
+ <description>Status register.</description>
+ <addressOffset>0x104</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RXSTATUS</name>
+ <description>If 1, the receive channel is active. If 0, the receive channel is inactive.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>TXSTATUS</name>
+ <description>If 1, the transmit channel is active. If 0, the transmit channel is inactive.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused</description>
+ <bitRange>[31:2]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RXDESCRIPTOR</name>
+ <description>Receive descriptor base address register.</description>
+ <addressOffset>0x108</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Fixed to 00</description>
+ <bitRange>[1:0]</bitRange>
+ </field>
+ <field>
+ <name>RXDESCRIPTOR</name>
+ <description>MSBs of receive descriptor base address.</description>
+ <bitRange>[31:2]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RXSTATUS</name>
+ <description>Receive status base address register.</description>
+ <addressOffset>0x10C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Fixed to 000</description>
+ <bitRange>[2:0]</bitRange>
+ </field>
+ <field>
+ <name>RXSTATUS</name>
+ <description>MSBs of receive status base address.</description>
+ <bitRange>[31:3]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RXDESCRIPTORNUMBER</name>
+ <description>Receive number of descriptors register.</description>
+ <addressOffset>0x110</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RXDESCRIPTORN</name>
+ <description>RxDescriptorNumber. Number of descriptors in the descriptor array for which RxDescriptor is the base address. The number of descriptors is minus one encoded.</description>
+ <bitRange>[15:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused</description>
+ <bitRange>[31:16]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RXPRODUCEINDEX</name>
+ <description>Receive produce index register.</description>
+ <addressOffset>0x114</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RXPRODUCEIX</name>
+ <description>Index of the descriptor that is going to be filled next by the receive datapath.</description>
+ <bitRange>[15:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused</description>
+ <bitRange>[31:16]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RXCONSUMEINDEX</name>
+ <description>Receive consume index register.</description>
+ <addressOffset>0x118</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RXCONSUMEIX</name>
+ <description>Index of the descriptor that is going to be processed next by the receive</description>
+ <bitRange>[15:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused</description>
+ <bitRange>[31:16]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TXDESCRIPTOR</name>
+ <description>Transmit descriptor base address register.</description>
+ <addressOffset>0x11C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Fixed to 00</description>
+ <bitRange>[1:0]</bitRange>
+ </field>
+ <field>
+ <name>TXD</name>
+ <description>TxDescriptor. MSBs of transmit descriptor base address.</description>
+ <bitRange>[31:2]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TXSTATUS</name>
+ <description>Transmit status base address register.</description>
+ <addressOffset>0x120</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Fixed to 00</description>
+ <bitRange>[1:0]</bitRange>
+ </field>
+ <field>
+ <name>TXSTAT</name>
+ <description>TxStatus. MSBs of transmit status base address.</description>
+ <bitRange>[31:2]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TXDESCRIPTORNUMBER</name>
+ <description>Transmit number of descriptors register.</description>
+ <addressOffset>0x124</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>TXDN</name>
+ <description>TxDescriptorNumber. Number of descriptors in the descriptor array for which TxDescriptor is the base address. The register is minus one encoded.</description>
+ <bitRange>[15:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused</description>
+ <bitRange>[31:16]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TXPRODUCEINDEX</name>
+ <description>Transmit produce index register.</description>
+ <addressOffset>0x128</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>TXPI</name>
+ <description>TxProduceIndex. Index of the descriptor that is going to be filled next by the transmit software driver.</description>
+ <bitRange>[15:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused</description>
+ <bitRange>[31:16]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TXCONSUMEINDEX</name>
+ <description>Transmit consume index register.</description>
+ <addressOffset>0x12C</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>TXCI</name>
+ <description>TxConsumeIndex. Index of the descriptor that is going to be transmitted next by the transmit datapath.</description>
+ <bitRange>[15:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused</description>
+ <bitRange>[31:16]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TSV0</name>
+ <description>Transmit status vector 0 register.</description>
+ <addressOffset>0x158</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>CRCERR</name>
+ <description>CRC error. The attached CRC in the packet did not match the internally generated CRC.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>LCE</name>
+ <description>Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>LOR</name>
+ <description>Length out of range. Indicates that frame type/length field was larger than 1500 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>DONE</name>
+ <description>Transmission of packet was completed.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>MULTICAST</name>
+ <description>Packet's destination was a multicast address.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>BROADCAST</name>
+ <description>Packet's destination was a broadcast address.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>PACKETDEFER</name>
+ <description>Packet was deferred for at least one attempt, but less than an excessive defer.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>EXDF</name>
+ <description>Excessive Defer. Packet was deferred in excess of 6071 nibble times in 100 Mbps or 24287 bit times in 10 Mbps mode.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>EXCOL</name>
+ <description>Excessive Collision. Packet was aborted due to exceeding of maximum allowed number of collisions.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>LCOL</name>
+ <description>Late Collision. Collision occurred beyond collision window, 512 bit times.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>GIANT</name>
+ <description>Byte count in frame was greater than can be represented in the transmit byte count field in TSV1.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>UNDERRUN</name>
+ <description>Host side caused buffer underrun.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>TOTALBYTES</name>
+ <description>The total number of bytes transferred including collided attempts.</description>
+ <bitRange>[27:12]</bitRange>
+ </field>
+ <field>
+ <name>CONTROLFRAME</name>
+ <description>The frame was a control frame.</description>
+ <bitRange>[28:28]</bitRange>
+ </field>
+ <field>
+ <name>PAUSE</name>
+ <description>The frame was a control frame with a valid PAUSE opcode.</description>
+ <bitRange>[29:29]</bitRange>
+ </field>
+ <field>
+ <name>BACKPRESSURE</name>
+ <description>Carrier-sense method backpressure was previously applied.</description>
+ <bitRange>[30:30]</bitRange>
+ </field>
+ <field>
+ <name>VLAN</name>
+ <description>Frame's length/type field contained 0x8100 which is the VLAN protocol identifier.</description>
+ <bitRange>[31:31]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TSV1</name>
+ <description>Transmit status vector 1 register.</description>
+ <addressOffset>0x15C</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>TBC</name>
+ <description>Transmit byte count. The total number of bytes in the frame, not counting the collided bytes.</description>
+ <bitRange>[15:0]</bitRange>
+ </field>
+ <field>
+ <name>TCC</name>
+ <description>Transmit collision count. Number of collisions the current packet incurred during transmission attempts. The maximum number of collisions (16) cannot be represented.</description>
+ <bitRange>[19:16]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused</description>
+ <bitRange>[31:20]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RSV</name>
+ <description>Receive status vector register.</description>
+ <addressOffset>0x160</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RBC</name>
+ <description>Received byte count. Indicates length of received frame.</description>
+ <bitRange>[15:0]</bitRange>
+ </field>
+ <field>
+ <name>PPI</name>
+ <description>Packet previously ignored. Indicates that a packet was dropped.</description>
+ <bitRange>[16:16]</bitRange>
+ </field>
+ <field>
+ <name>RXDVSEEN</name>
+ <description>RXDV event previously seen. Indicates that the last receive event seen was not long enough to be a valid packet.</description>
+ <bitRange>[17:17]</bitRange>
+ </field>
+ <field>
+ <name>CESEEN</name>
+ <description>Carrier event previously seen. Indicates that at some time since the last receive statistics, a carrier event was detected.</description>
+ <bitRange>[18:18]</bitRange>
+ </field>
+ <field>
+ <name>RCV</name>
+ <description>Receive code violation. Indicates that received PHY data does not represent a valid receive code.</description>
+ <bitRange>[19:19]</bitRange>
+ </field>
+ <field>
+ <name>CRCERR</name>
+ <description>CRC error. The attached CRC in the packet did not match the internally generated CRC.</description>
+ <bitRange>[20:20]</bitRange>
+ </field>
+ <field>
+ <name>LCERR</name>
+ <description>Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field.</description>
+ <bitRange>[21:21]</bitRange>
+ </field>
+ <field>
+ <name>LOR</name>
+ <description>Length out of range. Indicates that frame type/length field was larger than 1518 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame.</description>
+ <bitRange>[22:22]</bitRange>
+ </field>
+ <field>
+ <name>ROK</name>
+ <description>Receive OK. The packet had valid CRC and no symbol errors.</description>
+ <bitRange>[23:23]</bitRange>
+ </field>
+ <field>
+ <name>MULTICAST</name>
+ <description>The packet destination was a multicast address.</description>
+ <bitRange>[24:24]</bitRange>
+ </field>
+ <field>
+ <name>BROADCAST</name>
+ <description>The packet destination was a broadcast address.</description>
+ <bitRange>[25:25]</bitRange>
+ </field>
+ <field>
+ <name>DRIBBLENIBBLE</name>
+ <description>Indicates that after the end of packet another 1-7 bits were received. A single nibble, called dribble nibble, is formed but not sent out.</description>
+ <bitRange>[26:26]</bitRange>
+ </field>
+ <field>
+ <name>CONTROLFRAME</name>
+ <description>The frame was a control frame.</description>
+ <bitRange>[27:27]</bitRange>
+ </field>
+ <field>
+ <name>PAUSE</name>
+ <description>The frame was a control frame with a valid PAUSE opcode.</description>
+ <bitRange>[28:28]</bitRange>
+ </field>
+ <field>
+ <name>UO</name>
+ <description>Unsupported Opcode. The current frame was recognized as a Control Frame but contains an unknown opcode.</description>
+ <bitRange>[29:29]</bitRange>
+ </field>
+ <field>
+ <name>VLAN</name>
+ <description>Frame's length/type field contained 0x8100 which is the VLAN protocol identifier.</description>
+ <bitRange>[30:30]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused</description>
+ <bitRange>[31:31]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLOWCONTROLCOUNTER</name>
+ <description>Flow control counter register.</description>
+ <addressOffset>0x170</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>MC</name>
+ <description>MirrorCounter. In full duplex mode the MirrorCounter specifies the number of cycles before re-issuing the Pause control frame.</description>
+ <bitRange>[15:0]</bitRange>
+ </field>
+ <field>
+ <name>PT</name>
+ <description>PauseTimer. In full-duplex mode the PauseTimer specifies the value that is inserted into the pause timer field of a pause flow control frame. In half duplex mode the PauseTimer specifies the number of backpressure cycles.</description>
+ <bitRange>[31:16]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>FLOWCONTROLSTATUS</name>
+ <description>Flow control status register.</description>
+ <addressOffset>0x174</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>MCC</name>
+ <description>MirrorCounterCurrent. In full duplex mode this register represents the current value of the datapath's mirror counter which counts up to the value specified by the MirrorCounter field in the FlowControlCounter register. In half duplex mode the register counts until it reaches the value of the PauseTimer bits in the FlowControlCounter register.</description>
+ <bitRange>[15:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused</description>
+ <bitRange>[31:16]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RXFILTERCTRL</name>
+ <description>Receive filter control register.</description>
+ <addressOffset>0x200</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>AUE</name>
+ <description>AcceptUnicastEn. When set to 1, all unicast frames are accepted.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>ABE</name>
+ <description>AcceptBroadcastEn. When set to 1, all broadcast frames are accepted.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>AME</name>
+ <description>AcceptMulticastEn. When set to 1, all multicast frames are accepted.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>AUHE</name>
+ <description>AcceptUnicastHashEn. When set to 1, unicast frames that pass the imperfect hash filter are accepted.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>AMHE</name>
+ <description>AcceptMulticastHashEn. When set to 1, multicast frames that pass the imperfect hash filter are accepted.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>APE</name>
+ <description>AcceptPerfectEn. When set to 1, the frames with a destination address identical to the station address are accepted.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[11:6]</bitRange>
+ </field>
+ <field>
+ <name>MPEW</name>
+ <description>MagicPacketEnWoL. When set to 1, the result of the magic packet filter will generate a WoL interrupt when there is a match.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>RFEW</name>
+ <description>RxFilterEnWoL. When set to 1, the result of the perfect address matching filter and the imperfect hash filter will generate a WoL interrupt when there is a match.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused</description>
+ <bitRange>[31:14]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RXFILTERWOLSTATUS</name>
+ <description>Receive filter WoL status register.</description>
+ <addressOffset>0x204</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>AUW</name>
+ <description>AcceptUnicastWoL. When the value is 1, a unicast frames caused WoL.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>ABW</name>
+ <description>AcceptBroadcastWoL. When the value is 1, a broadcast frame caused WoL.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>AMW</name>
+ <description>AcceptMulticastWoL. When the value is 1, a multicast frame caused WoL.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>AUHW</name>
+ <description>AcceptUnicastHashWoL. When the value is 1, a unicast frame that passes the imperfect hash filter caused WoL.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>AMHW</name>
+ <description>AcceptMulticastHashWoL. When the value is 1, a multicast frame that passes the imperfect hash filter caused WoL.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>APW</name>
+ <description>AcceptPerfectWoL. When the value is 1, the perfect address matching filter caused WoL.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>RFW</name>
+ <description>RxFilterWoL. When the value is 1, the receive filter caused WoL.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>MPW</name>
+ <description>MagicPacketWoL. When the value is 1, the magic packet filter caused WoL.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused</description>
+ <bitRange>[31:9]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RXFILTERWOLCLEAR</name>
+ <description>Receive filter WoL clear register.</description>
+ <addressOffset>0x208</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>AUWCLR</name>
+ <description>AcceptUnicastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>ABWCLR</name>
+ <description>AcceptBroadcastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>AMWCLR</name>
+ <description>AcceptMulticastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>AUHWCLR</name>
+ <description>AcceptUnicastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>AMHWCLR</name>
+ <description>AcceptMulticastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>APWCLR</name>
+ <description>AcceptPerfectWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>RFWCLR</name>
+ <description>RxFilterWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>MPWCLR</name>
+ <description>MagicPacketWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused</description>
+ <bitRange>[31:9]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HASHFILTERL</name>
+ <description>Hash filter table LSBs register.</description>
+ <addressOffset>0x210</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>HFL</name>
+ <description>HashFilterL. Bits 31:0 of the imperfect filter hash table for receive filtering.</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>HASHFILTERH</name>
+ <description>Hash filter table MSBs register.</description>
+ <addressOffset>0x214</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>HFH</name>
+ <description>Bits 63:32 of the imperfect filter hash table for receive filtering.</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>INTSTATUS</name>
+ <description>Interrupt status register.</description>
+ <addressOffset>0xFE0</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RXOVERRUNINT</name>
+ <description>Interrupt set on a fatal overrun error in the receive queue. The fatal interrupt should be resolved by a Rx soft-reset. The bit is not set when there is a nonfatal overrun error.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>RXERRORINT</name>
+ <description>Interrupt trigger on receive errors: AlignmentError, RangeError, LengthError, SymbolError, CRCError or NoDescriptor or Overrun.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>RXFINISHEDINT</name>
+ <description>Interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>RXDONEINT</name>
+ <description>Interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>TXUNDERRUNINT</name>
+ <description>Interrupt set on a fatal underrun error in the transmit queue. The fatal interrupt should be resolved by a Tx soft-reset. The bit is not set when there is a nonfatal underrun error.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>TXERRORINT</name>
+ <description>Interrupt trigger on transmit errors: LateCollision, ExcessiveCollision and ExcessiveDefer, NoDescriptor or Underrun.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>TXFINISHEDINT</name>
+ <description>Interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>TXDONEINT</name>
+ <description>Interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused</description>
+ <bitRange>[11:8]</bitRange>
+ </field>
+ <field>
+ <name>SOFTINT</name>
+ <description>Interrupt triggered by software writing a 1 to the SoftIntSet bit in the IntSet register.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>WAKEUPINT</name>
+ <description>Interrupt triggered by a Wake-up event detected by the receive filter.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused</description>
+ <bitRange>[31:14]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>INTENABLE</name>
+ <description>Interrupt enable register.</description>
+ <addressOffset>0xFE4</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RXOVERRUNINTEN</name>
+ <description>Enable for interrupt trigger on receive buffer overrun or descriptor underrun situations.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>RXERRORINTEN</name>
+ <description>Enable for interrupt trigger on receive errors.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>RXFINISHEDINTEN</name>
+ <description>Enable for interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>RXDONEINTEN</name>
+ <description>Enable for interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>TXUNDERRUNINTEN</name>
+ <description>Enable for interrupt trigger on transmit buffer or descriptor underrun situations.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>TXERRORINTEN</name>
+ <description>Enable for interrupt trigger on transmit errors.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>TXFINISHEDINTEN</name>
+ <description>Enable for interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>TXDONEINTEN</name>
+ <description>Enable for interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused</description>
+ <bitRange>[11:8]</bitRange>
+ </field>
+ <field>
+ <name>SOFTINTEN</name>
+ <description>Enable for interrupt triggered by the SoftInt bit in the IntStatus register, caused by software writing a 1 to the SoftIntSet bit in the IntSet register.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>WAKEUPINTEN</name>
+ <description>Enable for interrupt triggered by a Wake-up event detected by the receive filter.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused</description>
+ <bitRange>[31:14]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>INTCLEAR</name>
+ <description>Interrupt clear register.</description>
+ <addressOffset>0xFE8</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RXOVERRUNINTCLR</name>
+ <description>Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>RXERRORINTCLR</name>
+ <description>Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>RXFINISHEDINTCLR</name>
+ <description>Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>RXDONEINTCLR</name>
+ <description>Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>TXUNDERRUNINTCLR</name>
+ <description>Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>TXERRORINTCLR</name>
+ <description>Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>TXFINISHEDINTCLR</name>
+ <description>Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>TXDONEINTCLR</name>
+ <description>Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused</description>
+ <bitRange>[11:8]</bitRange>
+ </field>
+ <field>
+ <name>SOFTINTCLR</name>
+ <description>Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>WAKEUPINTCLR</name>
+ <description>Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused</description>
+ <bitRange>[31:14]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>INTSET</name>
+ <description>Interrupt set register.</description>
+ <addressOffset>0xFEC</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RXOVERRUNINTSET</name>
+ <description>Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>RXERRORINTSET</name>
+ <description>Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>RXFINISHEDINTSET</name>
+ <description>Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>RXDONEINTSET</name>
+ <description>Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>TXUNDERRUNINTSET</name>
+ <description>Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>TXERRORINTSET</name>
+ <description>Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>TXFINISHEDINTSET</name>
+ <description>Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>TXDONEINTSET</name>
+ <description>Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused</description>
+ <bitRange>[11:8]</bitRange>
+ </field>
+ <field>
+ <name>SOFTINTSET</name>
+ <description>Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>WAKEUPINTSET</name>
+ <description>Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused</description>
+ <bitRange>[31:14]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>POWERDOWN</name>
+ <description>Power-down register.</description>
+ <addressOffset>0xFF4</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Unused</description>
+ <bitRange>[30:0]</bitRange>
+ </field>
+ <field>
+ <name>PD</name>
+ <description>PowerDownMACAHB. If true, all AHB accesses will return a read/write error, except accesses to the Power-Down register.</description>
+ <bitRange>[31:31]</bitRange>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+
+ <peripheral>
+ <name>GPDMA</name>
+ <description>General purpose DMA controller</description>
+ <groupName>GPDMA</groupName>
+ <baseAddress>0x50004000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0xFFF</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>DMA</name>
+ <value>26</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>INTSTAT</name>
+ <description>DMA Interrupt Status Register</description>
+ <addressOffset>0x000</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>INTSTAT0</name>
+ <description>Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>INTSTAT1</name>
+ <description>Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>INTSTAT2</name>
+ <description>Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>INTSTAT3</name>
+ <description>Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>INTSTAT4</name>
+ <description>Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>INTSTAT5</name>
+ <description>Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>INTSTAT6</name>
+ <description>Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>INTSTAT7</name>
+ <description>Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>INTTCSTAT</name>
+ <description>DMA Interrupt Terminal Count Request Status Register</description>
+ <addressOffset>0x004</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>INTTCSTAT0</name>
+ <description>Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>INTTCSTAT1</name>
+ <description>Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>INTTCSTAT2</name>
+ <description>Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>INTTCSTAT3</name>
+ <description>Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>INTTCSTAT4</name>
+ <description>Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>INTTCSTAT5</name>
+ <description>Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>INTTCSTAT6</name>
+ <description>Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>INTTCSTAT7</name>
+ <description>Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>INTTCCLEAR</name>
+ <description>DMA Interrupt Terminal Count Request Clear Register</description>
+ <addressOffset>0x008</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>INTTCCLEAR0</name>
+ <description>Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>INTTCCLEAR1</name>
+ <description>Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>INTTCCLEAR2</name>
+ <description>Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>INTTCCLEAR3</name>
+ <description>Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>INTTCCLEAR4</name>
+ <description>Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>INTTCCLEAR5</name>
+ <description>Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>INTTCCLEAR6</name>
+ <description>Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>INTTCCLEAR7</name>
+ <description>Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>INTERRSTAT</name>
+ <description>DMA Interrupt Error Status Register</description>
+ <addressOffset>0x00C</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>INTERRSTAT0</name>
+ <description>Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>INTERRSTAT1</name>
+ <description>Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>INTERRSTAT2</name>
+ <description>Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>INTERRSTAT3</name>
+ <description>Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>INTERRSTAT4</name>
+ <description>Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>INTERRSTAT5</name>
+ <description>Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>INTERRSTAT6</name>
+ <description>Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>INTERRSTAT7</name>
+ <description>Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>INTERRCLR</name>
+ <description>DMA Interrupt Error Clear Register</description>
+ <addressOffset>0x010</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>INTERRCLR0</name>
+ <description>Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>INTERRCLR1</name>
+ <description>Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>INTERRCLR2</name>
+ <description>Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>INTERRCLR3</name>
+ <description>Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>INTERRCLR4</name>
+ <description>Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>INTERRCLR5</name>
+ <description>Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>INTERRCLR6</name>
+ <description>Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>INTERRCLR7</name>
+ <description>Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RAWINTTCSTAT</name>
+ <description>DMA Raw Interrupt Terminal Count Status Register</description>
+ <addressOffset>0x014</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RAWINTTCSTAT0</name>
+ <description>Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>RAWINTTCSTAT1</name>
+ <description>Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>RAWINTTCSTAT2</name>
+ <description>Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>RAWINTTCSTAT3</name>
+ <description>Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>RAWINTTCSTAT4</name>
+ <description>Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>RAWINTTCSTAT5</name>
+ <description>Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>RAWINTTCSTAT6</name>
+ <description>Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>RAWINTTCSTAT7</name>
+ <description>Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RAWINTERRSTAT</name>
+ <description>DMA Raw Error Interrupt Status Register</description>
+ <addressOffset>0x018</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RAWINTERRSTAT0</name>
+ <description>Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>RAWINTERRSTAT1</name>
+ <description>Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>RAWINTERRSTAT2</name>
+ <description>Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>RAWINTERRSTAT3</name>
+ <description>Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>RAWINTERRSTAT4</name>
+ <description>Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>RAWINTERRSTAT5</name>
+ <description>Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>RAWINTERRSTAT6</name>
+ <description>Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>RAWINTERRSTAT7</name>
+ <description>Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ENBLDCHNS</name>
+ <description>DMA Enabled Channel Register</description>
+ <addressOffset>0x01C</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>ENABLEDCHANNELS0</name>
+ <description>Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>ENABLEDCHANNELS1</name>
+ <description>Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>ENABLEDCHANNELS2</name>
+ <description>Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>ENABLEDCHANNELS3</name>
+ <description>Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>ENABLEDCHANNELS4</name>
+ <description>Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>ENABLEDCHANNELS5</name>
+ <description>Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>ENABLEDCHANNELS6</name>
+ <description>Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>ENABLEDCHANNELS7</name>
+ <description>Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SOFTBREQ</name>
+ <description>DMA Software Burst Request Register</description>
+ <addressOffset>0x020</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>SOFTBREQ0</name>
+ <description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>SOFTBREQ1</name>
+ <description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>SOFTBREQ2</name>
+ <description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>SOFTBREQ3</name>
+ <description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>SOFTBREQ4</name>
+ <description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>SOFTBREQ5</name>
+ <description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>SOFTBREQ6</name>
+ <description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>SOFTBREQ7</name>
+ <description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>SOFTBREQ8</name>
+ <description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>SOFTBREQ9</name>
+ <description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>SOFTBREQ10</name>
+ <description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>SOFTBREQ11</name>
+ <description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>SOFTBREQ12</name>
+ <description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>SOFTBREQ13</name>
+ <description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>SOFTBREQ14</name>
+ <description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>SOFTBREQ15</name>
+ <description>Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:16]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SOFTSREQ</name>
+ <description>DMA Software Single Request Register</description>
+ <addressOffset>0x024</addressOffset>
+ <access>read-write</access>
+ <resetValue>0x00000000</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>SOFTSREQ0</name>
+ <description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>SOFTSREQ1</name>
+ <description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>SOFTSREQ2</name>
+ <description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>SOFTSREQ3</name>
+ <description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>SOFTSREQ4</name>
+ <description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>SOFTSREQ5</name>
+ <description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>SOFTSREQ6</name>
+ <description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>SOFTSREQ7</name>
+ <description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>SOFTSREQ8</name>
+ <description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>SOFTSREQ9</name>
+ <description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>SOFTSREQ10</name>
+ <description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>SOFTSREQ11</name>
+ <description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>SOFTSREQ12</name>
+ <description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>SOFTSREQ13</name>
+ <description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>SOFTSREQ14</name>
+ <description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>SOFTSREQ15</name>
+ <description>Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read undefined. Write reserved bits as zero.</description>
+ <bitRange>[31:16]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SOFTLBREQ</name>
+ <description>DMA Software Last Burst Request Register</description>
+ <addressOffset>0x028</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>SOFTLBREQ0</name>
+ <description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>SOFTLBREQ1</name>
+ <description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>SOFTLBREQ2</name>
+ <description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>SOFTLBREQ3</name>
+ <description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>SOFTLBREQ4</name>
+ <description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>SOFTLBREQ5</name>
+ <description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>SOFTLBREQ6</name>
+ <description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>SOFTLBREQ7</name>
+ <description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>SOFTLBREQ8</name>
+ <description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>SOFTLBREQ9</name>
+ <description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>SOFTLBREQ10</name>
+ <description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>SOFTLBREQ11</name>
+ <description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>SOFTLBREQ12</name>
+ <description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>SOFTLBREQ13</name>
+ <description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>SOFTLBREQ14</name>
+ <description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>SOFTLBREQ15</name>
+ <description>Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:16]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SOFTLSREQ</name>
+ <description>DMA Software Last Single Request Register</description>
+ <addressOffset>0x02C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>SOFTLSREQ0</name>
+ <description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>SOFTLSREQ1</name>
+ <description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>SOFTLSREQ2</name>
+ <description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>SOFTLSREQ3</name>
+ <description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>SOFTLSREQ4</name>
+ <description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>SOFTLSREQ5</name>
+ <description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>SOFTLSREQ6</name>
+ <description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>SOFTLSREQ7</name>
+ <description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>SOFTLSREQ8</name>
+ <description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>SOFTLSREQ9</name>
+ <description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>SOFTLSREQ10</name>
+ <description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>SOFTLSREQ11</name>
+ <description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>SOFTLSREQ12</name>
+ <description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>SOFTLSREQ13</name>
+ <description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>SOFTLSREQ14</name>
+ <description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>SOFTLSREQ15</name>
+ <description>Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:16]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CONFIG</name>
+ <description>DMA Configuration Register</description>
+ <addressOffset>0x030</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>E</name>
+ <description>DMA Controller enable: 0 = disabled (default). Disabling the DMA Controller reduces power consumption. 1 = enabled.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>M</name>
+ <description>AHB Master endianness configuration: 0 = little-endian mode (default). 1 = big-endian mode.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:2]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SYNC</name>
+ <description>DMA Synchronization Register</description>
+ <addressOffset>0x034</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>DMACSYNC0</name>
+ <description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>DMACSYNC1</name>
+ <description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>DMACSYNC2</name>
+ <description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>DMACSYNC3</name>
+ <description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>DMACSYNC4</name>
+ <description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>DMACSYNC5</name>
+ <description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>DMACSYNC6</name>
+ <description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>DMACSYNC7</name>
+ <description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>DMACSYNC8</name>
+ <description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>DMACSYNC9</name>
+ <description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>DMACSYNC10</name>
+ <description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>DMACSYNC11</name>
+ <description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>DMACSYNC12</name>
+ <description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>DMACSYNC13</name>
+ <description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>DMACSYNC14</name>
+ <description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>DMACSYNC15</name>
+ <description>Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:16]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <dim>8</dim>
+ <dimIncrement>0x20</dimIncrement>
+ <dimIndex>0-7</dimIndex>
+ <name>SRCADDR%s</name>
+
+ <description>DMA Channel 0 Source Address Register</description>
+ <addressOffset>0x100</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>SRCADDR</name>
+ <description>DMA source address. Reading this register will return the current source address.</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <dim>8</dim>
+ <dimIncrement>0x20</dimIncrement>
+ <dimIndex>0-7</dimIndex>
+ <name>DESTADDR%s</name>
+
+ <description>DMA Channel 0 Destination Address Register</description>
+ <addressOffset>0x104</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>DESTADDR</name>
+ <description>DMA Destination address. Reading this register will return the current destination address.</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <dim>8</dim>
+ <dimIncrement>0x20</dimIncrement>
+ <dimIndex>0-7</dimIndex>
+ <name>LLI%s</name>
+
+ <description>DMA Channel 0 Linked List Item Register</description>
+ <addressOffset>0x108</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, and must be written as 0.</description>
+ <bitRange>[1:0]</bitRange>
+ </field>
+ <field>
+ <name>LLI</name>
+ <description>Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0.</description>
+ <bitRange>[31:2]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <dim>8</dim>
+ <dimIncrement>0x20</dimIncrement>
+ <dimIndex>0-7</dimIndex>
+ <name>CONTROL%s</name>
+
+ <description>DMA Channel 0 Control Register</description>
+ <addressOffset>0x10C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>TRANSFERSIZE</name>
+ <description>Transfer size. This field sets the size of the transfer when the DMA controller is the flow controller, in which case the value must be set before the channel is enabled. Transfer size is updated as data transfers are completed. A read from this field indicates the number of transfers completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time that the software has processed the value read, the channel might have progressed. It is intended to be used only when a channel is enabled and then disabled. The transfer size value is not used if a peripheral is the flow controller.</description>
+ <bitRange>[11:0]</bitRange>
+ </field>
+ <field>
+ <name>SBSIZE</name>
+ <description>Source burst size. Indicates the number of transfers that make up a source burst. This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the source peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256</description>
+ <bitRange>[14:12]</bitRange>
+ </field>
+ <field>
+ <name>DBSIZE</name>
+ <description>Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. This value must be set to the burst size of the destination peripheral or, if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACBREQ signal goes active in the destination peripheral. 000 - 1 001 - 4 010 - 8 011 - 16 100 - 32 101 - 64 110 - 128 111 - 256</description>
+ <bitRange>[17:15]</bitRange>
+ </field>
+ <field>
+ <name>SWIDTH</name>
+ <description>Source transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved</description>
+ <bitRange>[20:18]</bitRange>
+ </field>
+ <field>
+ <name>DWIDTH</name>
+ <description>Destination transfer width. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data as required. 000 - Byte (8-bit) 001 - Halfword (16-bit) 010 - Word (32-bit) 011 to 111 - Reserved</description>
+ <bitRange>[23:21]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved, and must be written as 0.</description>
+ <bitRange>[25:24]</bitRange>
+ </field>
+ <field>
+ <name>SI</name>
+ <description>Source increment: 0 - the source address is not incremented after each transfer. 1 - the source address is incremented after each transfer.</description>
+ <bitRange>[26:26]</bitRange>
+ </field>
+ <field>
+ <name>DI</name>
+ <description>Destination increment: 0 - the destination address is not incremented after each transfer. 1 - the destination address is incremented after each transfer.</description>
+ <bitRange>[27:27]</bitRange>
+ </field>
+ <field>
+ <name>PROT1</name>
+ <description>This is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode. This information is not used in the LPC178x/177x. 0 - access is in user mode. 1 - access is in privileged mode.</description>
+ <bitRange>[28:28]</bitRange>
+ </field>
+ <field>
+ <name>PROT2</name>
+ <description>This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable. This information is not used in the LPC178x/177x. 0 - access is not bufferable. 1 - access is bufferable.</description>
+ <bitRange>[29:29]</bitRange>
+ </field>
+ <field>
+ <name>PROT3</name>
+ <description>This is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable. This information is not used in the LPC178x/177x. 0 - access is not cacheable. 1 - access is cacheable.</description>
+ <bitRange>[30:30]</bitRange>
+ </field>
+ <field>
+ <name>I</name>
+ <description>Terminal count interrupt enable bit. 0 - the terminal count interrupt is disabled. 1 - the terminal count interrupt is enabled.</description>
+ <bitRange>[31:31]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <dim>8</dim>
+ <dimIncrement>0x20</dimIncrement>
+ <dimIndex>0-7</dimIndex>
+ <name>CONFIG%s</name>
+
+ <description>DMA Channel 0 Configuration Register[1]</description>
+ <addressOffset>0x110</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>E</name>
+ <description>Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled. 1 = channel enabled. The Channel Enable bit status can also be found by reading the DMACEnbldChns Register. A channel is enabled by setting this bit. A channel can be disabled by clearing the Enable bit. This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled. Any data in the FIFO of the relevant channel is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects, the channel must be fully re-initialized. The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached, the DMA transfer is completed, or if a channel error is encountered. If a channel must be disabled without losing data in the FIFO, the Halt bit must be set so that further DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the FIFO. Finally, the Channel Enable bit can be cleared.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>SRCPERIPHERAL</name>
+ <description>Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. See Table 672 for peripheral identification.</description>
+ <bitRange>[5:1]</bitRange>
+ </field>
+ <field>
+ <name>DESTPERIPHERAL</name>
+ <description>Destination peripheral. This value selects the DMA destination request peripheral. This field is ignored if the destination of the transfer is to memory. See Table 672 for peripheral identification.</description>
+ <bitRange>[10:6]</bitRange>
+ </field>
+ <field>
+ <name>TRANSFERTYPE</name>
+ <description>This value indicates the type of transfer and specifies the flow controller. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. Flow can be controlled by the DMA controller, the source peripheral, or the destination peripheral. Refer to Table 694 for the encoding of this field.</description>
+ <bitRange>[13:11]</bitRange>
+ </field>
+ <field>
+ <name>IE</name>
+ <description>Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel.</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>ITC</name>
+ <description>Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>L</name>
+ <description>Lock. When set, this bit enables locked transfers. This information is not used in the LPC178x/177x.</description>
+ <bitRange>[16:16]</bitRange>
+ </field>
+ <field>
+ <name>A</name>
+ <description>Active: 0 = there is no data in the FIFO of the channel. 1 = the channel FIFO has data. This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel. This is a read-only bit.</description>
+ <bitRange>[17:17]</bitRange>
+ </field>
+ <field>
+ <name>H</name>
+ <description>Halt: 0 = enable DMA requests. 1 = ignore further source DMA requests. The contents of the channel FIFO are drained. This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.</description>
+ <bitRange>[18:18]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:19]</bitRange>
+ </field>
+ </fields>
+ </register>
+ </registers>
+</peripheral>
+
+
+
+ <peripheral>
+ <name>USB</name>
+ <description>USB device/host/OTG controller</description>
+ <groupName>USB</groupName>
+ <baseAddress>0x5000c000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0xFFF</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt>
+ <name>USB</name>
+ <value>24</value>
+ </interrupt>
+ <interrupt>
+ <name>USBActivity</name>
+ <value>33</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>INTST</name>
+ <description>OTG Interrupt Status</description>
+ <addressOffset>0x100</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>TMR</name>
+ <description>Timer time-out.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>REMOVE_PU</name>
+ <description>Remove pull-up. This bit is set by hardware to indicate that software needs to disable the D+ pull-up resistor.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>HNP_FAILURE</name>
+ <description>HNP failed. This bit is set by hardware to indicate that the HNP switching has failed.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>HNP_SUCCESS</name>
+ <description>HNP succeeded. This bit is set by hardware to indicate that the HNP switching has succeeded.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:4]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>INTEN</name>
+ <description>OTG Interrupt Enable</description>
+ <addressOffset>0x104</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>TMR_EN</name>
+ <description>1 = enable the corresponding bit in the IntSt register.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>REMOVE_PU_EN</name>
+ <description>1 = enable the corresponding bit in the IntSt register.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>HNP_FAILURE_EN</name>
+ <description>1 = enable the corresponding bit in the IntSt register.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>HNP_SUCCES_EN</name>
+ <description>1 = enable the corresponding bit in the IntSt register.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:4]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>INTSET</name>
+ <description>OTG Interrupt Set</description>
+ <addressOffset>0x108</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>TMR_SET</name>
+ <description>0 = no effect. 1 = set the corresponding bit in the IntSt register.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>REMOVE_PU_SET</name>
+ <description>0 = no effect. 1 = set the corresponding bit in the IntSt register.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>HNP_FAILURE_SET</name>
+ <description>0 = no effect. 1 = set the corresponding bit in the IntSt register.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>HNP_SUCCES_SET</name>
+ <description>0 = no effect. 1 = set the corresponding bit in the IntSt register.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:4]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>INTCLR</name>
+ <description>OTG Interrupt Clear</description>
+ <addressOffset>0x10C</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>TMR_CLR</name>
+ <description>0 = no effect. 1 = clear the corresponding bit in the IntSt register.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>REMOVE_PU_CLR</name>
+ <description>0 = no effect. 1 = clear the corresponding bit in the IntSt register.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>HNP_FAILURE_CLR</name>
+ <description>0 = no effect. 1 = clear the corresponding bit in the IntSt register.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>HNP_SUCCES_CLR</name>
+ <description>0 = no effect. 1 = clear the corresponding bit in the IntSt register.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:4]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>STCTRL</name>
+ <description>OTG Status and Control and USB port select</description>
+ <addressOffset>0x110</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>PORT_FUNC</name>
+ <description>Controls connection of USB functions (see Figure 51). Bit 0 is set or cleared by hardware when B_HNP_TRACK or A_HNP_TRACK is set and HNP succeeds. See Section 14.9. 00: U1 = device (OTG), U2 = host 01: U1 = host (OTG), U2 = host 10: Reserved 11: U1 = host, U2 = device In a device-only configuration, the following values are allowed: 00: U1 = device. The USB device controller signals are mapped to the U1 port: USB_CONNECT1, USB_UP_LED1, USB_D+1, USB_D-1. 11: U2 = device. The USB device controller signals are mapped to the U2 port: USB_CONNECT2, USB_UP_LED2, USB_D+2, USB_D-2.</description>
+ <bitRange>[1:0]</bitRange>
+ </field>
+ <field>
+ <name>TMR_SCALE</name>
+ <description>Timer scale selection. This field determines the duration of each timer count. 00: 10 ms (100 KHz) 01: 100 ms (10 KHz) 10: 1000 ms (1 KHz) 11: Reserved</description>
+ <bitRange>[3:2]</bitRange>
+ </field>
+ <field>
+ <name>TMR_MODE</name>
+ <description>Timer mode selection. 0: monoshot 1: free running</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>TMR_EN</name>
+ <description>Timer enable. When set, TMR_CNT increments. When cleared, TMR_CNT is reset to 0.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>TMR_RST</name>
+ <description>Timer reset. Writing one to this bit resets TMR_CNT to 0. This provides a single bit control for the software to restart the timer when the timer is enabled.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>B_HNP_TRACK</name>
+ <description>Enable HNP tracking for B-device (peripheral), see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>A_HNP_TRACK</name>
+ <description>Enable HNP tracking for A-device (host), see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>PU_REMOVED</name>
+ <description>When the B-device changes its role from peripheral to host, software sets this bit when it removes the D+ pull-up, see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[15:11]</bitRange>
+ </field>
+ <field>
+ <name>TMR_CNT</name>
+ <description>Current timer count value.</description>
+ <bitRange>[31:16]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TMR</name>
+ <description>OTG Timer</description>
+ <addressOffset>0x114</addressOffset>
+ <access>read-write</access>
+ <resetValue>0xFFFF</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>TIMEOUT_CNT</name>
+ <description>The TMR interrupt is set when TMR_CNT reaches this value.</description>
+ <bitRange>[15:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:16]</bitRange>
+ </field>
+ </fields>
+ </register>
+
+
+
+ <register>
+ <name>DEVINTST</name>
+ <description>USB Device Interrupt Status</description>
+ <addressOffset>0x200</addressOffset>
+ <access>read-only</access>
+ <resetValue>0x10</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>FRAME</name>
+ <description>The frame interrupt occurs every 1 ms. This is used in isochronous packet transfers.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>EP_FAST</name>
+ <description>Fast endpoint interrupt. If an Endpoint Interrupt Priority register (USBEpIntPri) bit is set, the corresponding endpoint interrupt will be routed to this bit.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>EP_SLOW</name>
+ <description>Slow endpoints interrupt. If an Endpoint Interrupt Priority Register (USBEpIntPri) bit is not set, the corresponding endpoint interrupt will be routed to this bit.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>DEV_STAT</name>
+ <description>Set when USB Bus reset, USB suspend change or Connect change event occurs. Refer to Section 13.12.6 Set Device Status (Command: 0xFE, Data: write 1 byte) on page 366.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>CCEMPTY</name>
+ <description>The command code register (USBCmdCode) is empty (New command can be written).</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>CDFULL</name>
+ <description>Command data register (USBCmdData) is full (Data can be read now).</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>RxENDPKT</name>
+ <description>The current packet in the endpoint buffer is transferred to the CPU.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>TxENDPKT</name>
+ <description>The number of data bytes transferred to the endpoint buffer equals the number of bytes programmed in the TxPacket length register (USBTxPLen).</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>EP_RLZED</name>
+ <description>Endpoints realized. Set when Realize Endpoint register (USBReEp) or MaxPacketSize register (USBMaxPSize) is updated and the corresponding operation is completed.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>ERR_INT</name>
+ <description>Error Interrupt. Any bus error interrupt from the USB device. Refer to Section 13.12.9 Read Error Status (Command: 0xFB, Data: read 1 byte) on page 368</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:10]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DEVINTEN</name>
+ <description>USB Device Interrupt Enable</description>
+ <addressOffset>0x204</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>FRAMEEN</name>
+ <description>0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>EP_FASTEN</name>
+ <description>0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>EP_SLOWEN</name>
+ <description>0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>DEV_STATEN</name>
+ <description>0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>CCEMPTYEN</name>
+ <description>0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>CDFULLEN</name>
+ <description>0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>RxENDPKTEN</name>
+ <description>0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>TxENDPKTEN</name>
+ <description>0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>EP_RLZEDEN</name>
+ <description>0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>ERR_INTEN</name>
+ <description>0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <bitRange>[31:10]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DEVINTCLR</name>
+ <description>USB Device Interrupt Clear</description>
+ <addressOffset>0x208</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>FRAMECLR</name>
+ <description>0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>EP_FASTCLR</name>
+ <description>0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>EP_SLOWCLR</name>
+ <description>0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>DEV_STATCLR</name>
+ <description>0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>CCEMPTYCLR</name>
+ <description>0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>CDFULLCLR</name>
+ <description>0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>RxENDPKTCLR</name>
+ <description>0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>TxENDPKTCLR</name>
+ <description>0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>EP_RLZEDCLR</name>
+ <description>0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>ERR_INTCLR</name>
+ <description>0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <bitRange>[31:10]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DEVINTSET</name>
+ <description>USB Device Interrupt Set</description>
+ <addressOffset>0x20C</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>FRAMESET</name>
+ <description>0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>EP_FASTSET</name>
+ <description>0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>EP_SLOWSET</name>
+ <description>0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>DEV_STATSET</name>
+ <description>0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>CCEMPTYSET</name>
+ <description>0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>CDFULLSET</name>
+ <description>0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>RxENDPKTSET</name>
+ <description>0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>TxENDPKTSET</name>
+ <description>0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>EP_RLZEDSET</name>
+ <description>0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>ERR_INTSET</name>
+ <description>0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved</description>
+ <bitRange>[31:10]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CMDCODE</name>
+ <description>USB Command Code</description>
+ <addressOffset>0x210</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[7:0]</bitRange>
+
+ </field>
+ <field>
+ <name>CMD_PHASE</name>
+ <description>The command phase:</description>
+ <bitRange>[15:8]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>READ</name>
+ <description>Read</description>
+ <value>0x02</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>WRITE</name>
+ <description>Write</description>
+ <value>0x01</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>COMMAND</name>
+ <description>Command</description>
+ <value>0x05</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CMD_CODE_WDATA</name>
+ <description>This is a multi-purpose field. When CMD_PHASE is Command or Read, this field contains the code for the command (CMD_CODE). When CMD_PHASE is Write, this field contains the command write data (CMD_WDATA).</description>
+ <bitRange>[23:16]</bitRange>
+
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:24]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CMDDATA</name>
+ <description>USB Command Data</description>
+ <addressOffset>0x214</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>CMD_RDATA</name>
+ <description>Command Read Data.</description>
+ <bitRange>[7:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RXDATA</name>
+ <description>USB Receive Data</description>
+ <addressOffset>0x218</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RX_DATA</name>
+ <description>Data received.</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TXDATA</name>
+ <description>USB Transmit Data</description>
+ <addressOffset>0x21C</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>TX_DATA</name>
+ <description>Transmit Data.</description>
+ <bitRange>[31:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>RXPLEN</name>
+ <description>USB Receive Packet Length</description>
+ <addressOffset>220</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>PKT_LNGTH</name>
+ <description>The remaining number of bytes to be read from the currently selected endpoint's buffer. When this field decrements to 0, the RxENDPKT bit will be set in USBDevIntSt.</description>
+ <bitRange>[9:0]</bitRange>
+
+ </field>
+ <field>
+ <name>DV</name>
+ <description>Data valid. This bit is useful for isochronous endpoints. Non-isochronous endpoints do not raise an interrupt when an erroneous data packet is received. But invalid data packet can be produced with a bus reset. For isochronous endpoints, data transfer will happen even if an erroneous packet is received. In this case DV bit will not be set for the packet.</description>
+ <bitRange>[10:10]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DATA_IS_INVALID_</name>
+ <description>Data is invalid.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DATA_IS_VALID_</name>
+ <description>Data is valid.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>PKT_RDY</name>
+ <description>The PKT_LNGTH field is valid and the packet is ready for reading.</description>
+ <bitRange>[11:11]</bitRange>
+
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:12]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TXPLEN</name>
+ <description>USB Transmit Packet Length</description>
+ <addressOffset>0x224</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>PKT_LNGTH</name>
+ <description>The remaining number of bytes to be written to the selected endpoint buffer. This field is decremented by 4 by hardware after each write to USBTxData. When this field decrements to 0, the TxENDPKT bit will be set in USBDevIntSt.</description>
+ <bitRange>[9:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:10]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CTRL</name>
+ <description>USB Control</description>
+ <addressOffset>0x228</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RD_EN</name>
+ <description>Read mode control. Enables reading data from the OUT endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBRxData register. This bit is cleared by hardware when the last word of the current packet is read from USBRxData.</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLED_</name>
+ <description>Disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLED_</name>
+ <description>Enabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>WR_EN</name>
+ <description>Write mode control. Enables writing data to the IN endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBTxData register. This bit is cleared by hardware when the number of bytes in USBTxLen have been sent.</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLED_</name>
+ <description>Disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLED_</name>
+ <description>Enabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>LOG_ENDPOINT</name>
+ <description>Logical Endpoint number.</description>
+ <bitRange>[5:2]</bitRange>
+
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:6]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DEVINTPRI</name>
+ <description>USB Device Interrupt Priority</description>
+ <addressOffset>0x22C</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>FRAME</name>
+ <description>Frame interrupt routing</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>LP</name>
+ <description>FRAME interrupt is routed to USB_INT_REQ_LP.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>HP</name>
+ <description>FRAME interrupt is routed to USB_INT_REQ_HP.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>EP_FAST</name>
+ <description>Fast endpoint interrupt routing</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>LP</name>
+ <description>EP_FAST interrupt is routed to USB_INT_REQ_LP.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>HP</name>
+ <description>EP_FAST interrupt is routed to USB_INT_REQ_HP.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:2]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>EPINTST</name>
+ <description>USB Endpoint Interrupt Status</description>
+ <addressOffset>0x230</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>EPST0</name>
+ <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>EPST1</name>
+ <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>EPST2</name>
+ <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>EPST3</name>
+ <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>EPST4</name>
+ <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>EPST5</name>
+ <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>EPST6</name>
+ <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>EPST7</name>
+ <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>EPST8</name>
+ <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>EPST9</name>
+ <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>EPST10</name>
+ <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>EPST11</name>
+ <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>EPST12</name>
+ <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>EPST13</name>
+ <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>EPST14</name>
+ <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>EPST15</name>
+ <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>EPST16</name>
+ <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
+ <bitRange>[16:16]</bitRange>
+ </field>
+ <field>
+ <name>EPST17</name>
+ <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
+ <bitRange>[17:17]</bitRange>
+ </field>
+ <field>
+ <name>EPST18</name>
+ <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
+ <bitRange>[18:18]</bitRange>
+ </field>
+ <field>
+ <name>EPST19</name>
+ <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
+ <bitRange>[19:19]</bitRange>
+ </field>
+ <field>
+ <name>EPST20</name>
+ <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
+ <bitRange>[20:20]</bitRange>
+ </field>
+ <field>
+ <name>EPST21</name>
+ <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
+ <bitRange>[21:21]</bitRange>
+ </field>
+ <field>
+ <name>EPST22</name>
+ <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
+ <bitRange>[22:22]</bitRange>
+ </field>
+ <field>
+ <name>EPST23</name>
+ <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
+ <bitRange>[23:23]</bitRange>
+ </field>
+ <field>
+ <name>EPST24</name>
+ <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
+ <bitRange>[24:24]</bitRange>
+ </field>
+ <field>
+ <name>EPST25</name>
+ <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
+ <bitRange>[25:25]</bitRange>
+ </field>
+ <field>
+ <name>EPST26</name>
+ <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
+ <bitRange>[26:26]</bitRange>
+ </field>
+ <field>
+ <name>EPST27</name>
+ <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
+ <bitRange>[27:27]</bitRange>
+ </field>
+ <field>
+ <name>EPST28</name>
+ <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
+ <bitRange>[28:28]</bitRange>
+ </field>
+ <field>
+ <name>EPST29</name>
+ <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
+ <bitRange>[29:29]</bitRange>
+ </field>
+ <field>
+ <name>EPST30</name>
+ <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
+ <bitRange>[30:30]</bitRange>
+ </field>
+ <field>
+ <name>EPST31</name>
+ <description>1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.</description>
+ <bitRange>[31:31]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>EPINTEN</name>
+ <description>USB Endpoint Interrupt Enable</description>
+ <addressOffset>0x234</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>EPEN0</name>
+ <description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>EPEN1</name>
+ <description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>EPEN2</name>
+ <description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>EPEN3</name>
+ <description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>EPEN4</name>
+ <description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>EPEN5</name>
+ <description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>EPEN6</name>
+ <description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>EPEN7</name>
+ <description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>EPEN8</name>
+ <description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>EPEN9</name>
+ <description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>EPEN10</name>
+ <description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>EPEN11</name>
+ <description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>EPEN12</name>
+ <description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>EPEN13</name>
+ <description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>EPEN14</name>
+ <description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>EPEN15</name>
+ <description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>EPEN16</name>
+ <description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
+ <bitRange>[16:16]</bitRange>
+ </field>
+ <field>
+ <name>EPEN17</name>
+ <description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
+ <bitRange>[17:17]</bitRange>
+ </field>
+ <field>
+ <name>EPEN18</name>
+ <description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
+ <bitRange>[18:18]</bitRange>
+ </field>
+ <field>
+ <name>EPEN19</name>
+ <description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
+ <bitRange>[19:19]</bitRange>
+ </field>
+ <field>
+ <name>EPEN20</name>
+ <description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
+ <bitRange>[20:20]</bitRange>
+ </field>
+ <field>
+ <name>EPEN21</name>
+ <description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
+ <bitRange>[21:21]</bitRange>
+ </field>
+ <field>
+ <name>EPEN22</name>
+ <description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
+ <bitRange>[22:22]</bitRange>
+ </field>
+ <field>
+ <name>EPEN23</name>
+ <description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
+ <bitRange>[23:23]</bitRange>
+ </field>
+ <field>
+ <name>EPEN24</name>
+ <description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
+ <bitRange>[24:24]</bitRange>
+ </field>
+ <field>
+ <name>EPEN25</name>
+ <description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
+ <bitRange>[25:25]</bitRange>
+ </field>
+ <field>
+ <name>EPEN26</name>
+ <description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
+ <bitRange>[26:26]</bitRange>
+ </field>
+ <field>
+ <name>EPEN27</name>
+ <description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
+ <bitRange>[27:27]</bitRange>
+ </field>
+ <field>
+ <name>EPEN28</name>
+ <description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
+ <bitRange>[28:28]</bitRange>
+ </field>
+ <field>
+ <name>EPEN29</name>
+ <description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
+ <bitRange>[29:29]</bitRange>
+ </field>
+ <field>
+ <name>EPEN30</name>
+ <description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
+ <bitRange>[30:30]</bitRange>
+ </field>
+ <field>
+ <name>EPEN31</name>
+ <description>0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.</description>
+ <bitRange>[31:31]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>EPINTCLR</name>
+ <description>USB Endpoint Interrupt Clear</description>
+ <addressOffset>0x238</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>EPCLR0</name>
+ <description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>EPCLR1</name>
+ <description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>EPCLR2</name>
+ <description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>EPCLR3</name>
+ <description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>EPCLR4</name>
+ <description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>EPCLR5</name>
+ <description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>EPCLR6</name>
+ <description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>EPCLR7</name>
+ <description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>EPCLR8</name>
+ <description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>EPCLR9</name>
+ <description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>EPCLR10</name>
+ <description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>EPCLR11</name>
+ <description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>EPCLR12</name>
+ <description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>EPCLR13</name>
+ <description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>EPCLR14</name>
+ <description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>EPCLR15</name>
+ <description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>EPCLR16</name>
+ <description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
+ <bitRange>[16:16]</bitRange>
+ </field>
+ <field>
+ <name>EPCLR17</name>
+ <description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
+ <bitRange>[17:17]</bitRange>
+ </field>
+ <field>
+ <name>EPCLR18</name>
+ <description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
+ <bitRange>[18:18]</bitRange>
+ </field>
+ <field>
+ <name>EPCLR19</name>
+ <description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
+ <bitRange>[19:19]</bitRange>
+ </field>
+ <field>
+ <name>EPCLR20</name>
+ <description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
+ <bitRange>[20:20]</bitRange>
+ </field>
+ <field>
+ <name>EPCLR21</name>
+ <description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
+ <bitRange>[21:21]</bitRange>
+ </field>
+ <field>
+ <name>EPCLR22</name>
+ <description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
+ <bitRange>[22:22]</bitRange>
+ </field>
+ <field>
+ <name>EPCLR23</name>
+ <description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
+ <bitRange>[23:23]</bitRange>
+ </field>
+ <field>
+ <name>EPCLR24</name>
+ <description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
+ <bitRange>[24:24]</bitRange>
+ </field>
+ <field>
+ <name>EPCLR25</name>
+ <description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
+ <bitRange>[25:25]</bitRange>
+ </field>
+ <field>
+ <name>EPCLR26</name>
+ <description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
+ <bitRange>[26:26]</bitRange>
+ </field>
+ <field>
+ <name>EPCLR27</name>
+ <description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
+ <bitRange>[27:27]</bitRange>
+ </field>
+ <field>
+ <name>EPCLR28</name>
+ <description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
+ <bitRange>[28:28]</bitRange>
+ </field>
+ <field>
+ <name>EPCLR29</name>
+ <description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
+ <bitRange>[29:29]</bitRange>
+ </field>
+ <field>
+ <name>EPCLR30</name>
+ <description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
+ <bitRange>[30:30]</bitRange>
+ </field>
+ <field>
+ <name>EPCLR31</name>
+ <description>0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.</description>
+ <bitRange>[31:31]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>EPINTSET</name>
+ <description>USB Endpoint Interrupt Set</description>
+ <addressOffset>0x23C</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>EPSET0</name>
+ <description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>EPSET1</name>
+ <description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>EPSET2</name>
+ <description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>EPSET3</name>
+ <description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>EPSET4</name>
+ <description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>EPSET5</name>
+ <description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>EPSET6</name>
+ <description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>EPSET7</name>
+ <description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>EPSET8</name>
+ <description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>EPSET9</name>
+ <description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>EPSET10</name>
+ <description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>EPSET11</name>
+ <description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>EPSET12</name>
+ <description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>EPSET13</name>
+ <description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>EPSET14</name>
+ <description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>EPSET15</name>
+ <description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>EPSET16</name>
+ <description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
+ <bitRange>[16:16]</bitRange>
+ </field>
+ <field>
+ <name>EPSET17</name>
+ <description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
+ <bitRange>[17:17]</bitRange>
+ </field>
+ <field>
+ <name>EPSET18</name>
+ <description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
+ <bitRange>[18:18]</bitRange>
+ </field>
+ <field>
+ <name>EPSET19</name>
+ <description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
+ <bitRange>[19:19]</bitRange>
+ </field>
+ <field>
+ <name>EPSET20</name>
+ <description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
+ <bitRange>[20:20]</bitRange>
+ </field>
+ <field>
+ <name>EPSET21</name>
+ <description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
+ <bitRange>[21:21]</bitRange>
+ </field>
+ <field>
+ <name>EPSET22</name>
+ <description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
+ <bitRange>[22:22]</bitRange>
+ </field>
+ <field>
+ <name>EPSET23</name>
+ <description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
+ <bitRange>[23:23]</bitRange>
+ </field>
+ <field>
+ <name>EPSET24</name>
+ <description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
+ <bitRange>[24:24]</bitRange>
+ </field>
+ <field>
+ <name>EPSET25</name>
+ <description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
+ <bitRange>[25:25]</bitRange>
+ </field>
+ <field>
+ <name>EPSET26</name>
+ <description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
+ <bitRange>[26:26]</bitRange>
+ </field>
+ <field>
+ <name>EPSET27</name>
+ <description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
+ <bitRange>[27:27]</bitRange>
+ </field>
+ <field>
+ <name>EPSET28</name>
+ <description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
+ <bitRange>[28:28]</bitRange>
+ </field>
+ <field>
+ <name>EPSET29</name>
+ <description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
+ <bitRange>[29:29]</bitRange>
+ </field>
+ <field>
+ <name>EPSET30</name>
+ <description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
+ <bitRange>[30:30]</bitRange>
+ </field>
+ <field>
+ <name>EPSET31</name>
+ <description>0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.</description>
+ <bitRange>[31:31]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>EPINTPRI</name>
+ <description>USB Endpoint Priority</description>
+ <addressOffset>0x240</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>EPPRI0</name>
+ <description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>EPPRI1</name>
+ <description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>EPPRI2</name>
+ <description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>EPPRI3</name>
+ <description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>EPPRI4</name>
+ <description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>EPPRI5</name>
+ <description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>EPPRI6</name>
+ <description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>EPPRI7</name>
+ <description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>EPPRI8</name>
+ <description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>EPPRI9</name>
+ <description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>EPPRI10</name>
+ <description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>EPPRI11</name>
+ <description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>EPPRI12</name>
+ <description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>EPPRI13</name>
+ <description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>EPPRI14</name>
+ <description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>EPPRI15</name>
+ <description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>EPPRI16</name>
+ <description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
+ <bitRange>[16:16]</bitRange>
+ </field>
+ <field>
+ <name>EPPRI17</name>
+ <description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
+ <bitRange>[17:17]</bitRange>
+ </field>
+ <field>
+ <name>EPPRI18</name>
+ <description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
+ <bitRange>[18:18]</bitRange>
+ </field>
+ <field>
+ <name>EPPRI19</name>
+ <description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
+ <bitRange>[19:19]</bitRange>
+ </field>
+ <field>
+ <name>EPPRI20</name>
+ <description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
+ <bitRange>[20:20]</bitRange>
+ </field>
+ <field>
+ <name>EPPRI21</name>
+ <description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
+ <bitRange>[21:21]</bitRange>
+ </field>
+ <field>
+ <name>EPPRI22</name>
+ <description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
+ <bitRange>[22:22]</bitRange>
+ </field>
+ <field>
+ <name>EPPRI23</name>
+ <description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
+ <bitRange>[23:23]</bitRange>
+ </field>
+ <field>
+ <name>EPPRI24</name>
+ <description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
+ <bitRange>[24:24]</bitRange>
+ </field>
+ <field>
+ <name>EPPRI25</name>
+ <description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
+ <bitRange>[25:25]</bitRange>
+ </field>
+ <field>
+ <name>EPPRI26</name>
+ <description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
+ <bitRange>[26:26]</bitRange>
+ </field>
+ <field>
+ <name>EPPRI27</name>
+ <description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
+ <bitRange>[27:27]</bitRange>
+ </field>
+ <field>
+ <name>EPPRI28</name>
+ <description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
+ <bitRange>[28:28]</bitRange>
+ </field>
+ <field>
+ <name>EPPRI29</name>
+ <description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
+ <bitRange>[29:29]</bitRange>
+ </field>
+ <field>
+ <name>EPPRI30</name>
+ <description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
+ <bitRange>[30:30]</bitRange>
+ </field>
+ <field>
+ <name>EPPRI31</name>
+ <description>0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt</description>
+ <bitRange>[31:31]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>REEP</name>
+ <description>USB Realize Endpoint</description>
+ <addressOffset>0x244</addressOffset>
+ <access>read-write</access>
+ <resetValue>0x3</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>EPR0</name>
+ <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>EPR1</name>
+ <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>EPR2</name>
+ <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>EPR3</name>
+ <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>EPR4</name>
+ <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>EPR5</name>
+ <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>EPR6</name>
+ <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>EPR7</name>
+ <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>EPR8</name>
+ <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>EPR9</name>
+ <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>EPR10</name>
+ <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>EPR11</name>
+ <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>EPR12</name>
+ <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>EPR13</name>
+ <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>EPR14</name>
+ <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>EPR15</name>
+ <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>EPR16</name>
+ <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
+ <bitRange>[16:16]</bitRange>
+ </field>
+ <field>
+ <name>EPR17</name>
+ <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
+ <bitRange>[17:17]</bitRange>
+ </field>
+ <field>
+ <name>EPR18</name>
+ <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
+ <bitRange>[18:18]</bitRange>
+ </field>
+ <field>
+ <name>EPR19</name>
+ <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
+ <bitRange>[19:19]</bitRange>
+ </field>
+ <field>
+ <name>EPR20</name>
+ <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
+ <bitRange>[20:20]</bitRange>
+ </field>
+ <field>
+ <name>EPR21</name>
+ <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
+ <bitRange>[21:21]</bitRange>
+ </field>
+ <field>
+ <name>EPR22</name>
+ <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
+ <bitRange>[22:22]</bitRange>
+ </field>
+ <field>
+ <name>EPR23</name>
+ <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
+ <bitRange>[23:23]</bitRange>
+ </field>
+ <field>
+ <name>EPR24</name>
+ <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
+ <bitRange>[24:24]</bitRange>
+ </field>
+ <field>
+ <name>EPR25</name>
+ <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
+ <bitRange>[25:25]</bitRange>
+ </field>
+ <field>
+ <name>EPR26</name>
+ <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
+ <bitRange>[26:26]</bitRange>
+ </field>
+ <field>
+ <name>EPR27</name>
+ <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
+ <bitRange>[27:27]</bitRange>
+ </field>
+ <field>
+ <name>EPR28</name>
+ <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
+ <bitRange>[28:28]</bitRange>
+ </field>
+ <field>
+ <name>EPR29</name>
+ <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
+ <bitRange>[29:29]</bitRange>
+ </field>
+ <field>
+ <name>EPR30</name>
+ <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
+ <bitRange>[30:30]</bitRange>
+ </field>
+ <field>
+ <name>EPR31</name>
+ <description>0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.</description>
+ <bitRange>[31:31]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>EPIND</name>
+ <description>USB Endpoint Index</description>
+ <addressOffset>0x248</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>PHY_EP</name>
+ <description>Physical endpoint number (0-31)</description>
+ <bitRange>[4:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:5]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>MAXPSIZE</name>
+ <description>USB MaxPacketSize</description>
+ <addressOffset>0x24C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0x8</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>MPS</name>
+ <description>The maximum packet size value.</description>
+ <bitRange>[9:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:10]</bitRange>
+ </field>
+ </fields>
+ </register>
+
+
+
+
+
+
+
+ <register>
+ <name>DMARST</name>
+ <description>USB DMA Request Status</description>
+ <addressOffset>0x250</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>EPRST0</name>
+ <description>Control endpoint OUT (DMA cannot be enabled for this endpoint and EP0 bit must be 0).</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>EPRST1</name>
+ <description>Control endpoint IN (DMA cannot be enabled for this endpoint and EP1 bit must be 0).</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>EPRST2</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>EPRST3</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>EPRST4</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>EPRST5</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>EPRST6</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>EPRST7</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>EPRST8</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>EPRST9</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>EPRST10</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>EPRST11</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>EPRST12</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>EPRST13</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>EPRST14</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>EPRST15</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>EPRST16</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
+ <bitRange>[16:16]</bitRange>
+ </field>
+ <field>
+ <name>EPRST17</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
+ <bitRange>[17:17]</bitRange>
+ </field>
+ <field>
+ <name>EPRST18</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
+ <bitRange>[18:18]</bitRange>
+ </field>
+ <field>
+ <name>EPRST19</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
+ <bitRange>[19:19]</bitRange>
+ </field>
+ <field>
+ <name>EPRST20</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
+ <bitRange>[20:20]</bitRange>
+ </field>
+ <field>
+ <name>EPRST21</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
+ <bitRange>[21:21]</bitRange>
+ </field>
+ <field>
+ <name>EPRST22</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
+ <bitRange>[22:22]</bitRange>
+ </field>
+ <field>
+ <name>EPRST23</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
+ <bitRange>[23:23]</bitRange>
+ </field>
+ <field>
+ <name>EPRST24</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
+ <bitRange>[24:24]</bitRange>
+ </field>
+ <field>
+ <name>EPRST25</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
+ <bitRange>[25:25]</bitRange>
+ </field>
+ <field>
+ <name>EPRST26</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
+ <bitRange>[26:26]</bitRange>
+ </field>
+ <field>
+ <name>EPRST27</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
+ <bitRange>[27:27]</bitRange>
+ </field>
+ <field>
+ <name>EPRST28</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
+ <bitRange>[28:28]</bitRange>
+ </field>
+ <field>
+ <name>EPRST29</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
+ <bitRange>[29:29]</bitRange>
+ </field>
+ <field>
+ <name>EPRST30</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
+ <bitRange>[30:30]</bitRange>
+ </field>
+ <field>
+ <name>EPRST31</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.</description>
+ <bitRange>[31:31]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMARCLR</name>
+ <description>USB DMA Request Clear</description>
+ <addressOffset>0x254</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>EPRCLR0</name>
+ <description>Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0).</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>EPRCLR1</name>
+ <description>Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0).</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>EPRCLR2</name>
+ <description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>EPRCLR3</name>
+ <description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>EPRCLR4</name>
+ <description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>EPRCLR5</name>
+ <description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>EPRCLR6</name>
+ <description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>EPRCLR7</name>
+ <description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>EPRCLR8</name>
+ <description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>EPRCLR9</name>
+ <description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>EPRCLR10</name>
+ <description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>EPRCLR11</name>
+ <description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>EPRCLR12</name>
+ <description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>EPRCLR13</name>
+ <description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>EPRCLR14</name>
+ <description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>EPRCLR15</name>
+ <description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>EPRCLR16</name>
+ <description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
+ <bitRange>[16:16]</bitRange>
+ </field>
+ <field>
+ <name>EPRCLR17</name>
+ <description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
+ <bitRange>[17:17]</bitRange>
+ </field>
+ <field>
+ <name>EPRCLR18</name>
+ <description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
+ <bitRange>[18:18]</bitRange>
+ </field>
+ <field>
+ <name>EPRCLR19</name>
+ <description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
+ <bitRange>[19:19]</bitRange>
+ </field>
+ <field>
+ <name>EPRCLR20</name>
+ <description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
+ <bitRange>[20:20]</bitRange>
+ </field>
+ <field>
+ <name>EPRCLR21</name>
+ <description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
+ <bitRange>[21:21]</bitRange>
+ </field>
+ <field>
+ <name>EPRCLR22</name>
+ <description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
+ <bitRange>[22:22]</bitRange>
+ </field>
+ <field>
+ <name>EPRCLR23</name>
+ <description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
+ <bitRange>[23:23]</bitRange>
+ </field>
+ <field>
+ <name>EPRCLR24</name>
+ <description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
+ <bitRange>[24:24]</bitRange>
+ </field>
+ <field>
+ <name>EPRCLR25</name>
+ <description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
+ <bitRange>[25:25]</bitRange>
+ </field>
+ <field>
+ <name>EPRCLR26</name>
+ <description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
+ <bitRange>[26:26]</bitRange>
+ </field>
+ <field>
+ <name>EPRCLR27</name>
+ <description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
+ <bitRange>[27:27]</bitRange>
+ </field>
+ <field>
+ <name>EPRCLR28</name>
+ <description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
+ <bitRange>[28:28]</bitRange>
+ </field>
+ <field>
+ <name>EPRCLR29</name>
+ <description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
+ <bitRange>[29:29]</bitRange>
+ </field>
+ <field>
+ <name>EPRCLR30</name>
+ <description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
+ <bitRange>[30:30]</bitRange>
+ </field>
+ <field>
+ <name>EPRCLR31</name>
+ <description>Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.</description>
+ <bitRange>[31:31]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMARSET</name>
+ <description>USB DMA Request Set</description>
+ <addressOffset>0x258</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>EPRSET0</name>
+ <description>Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0).</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>EPRSET1</name>
+ <description>Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0).</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>EPRSET2</name>
+ <description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>EPRSET3</name>
+ <description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>EPRSET4</name>
+ <description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>EPRSET5</name>
+ <description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>EPRSET6</name>
+ <description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>EPRSET7</name>
+ <description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>EPRSET8</name>
+ <description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>EPRSET9</name>
+ <description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>EPRSET10</name>
+ <description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>EPRSET11</name>
+ <description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>EPRSET12</name>
+ <description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>EPRSET13</name>
+ <description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>EPRSET14</name>
+ <description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>EPRSET15</name>
+ <description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>EPRSET16</name>
+ <description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
+ <bitRange>[16:16]</bitRange>
+ </field>
+ <field>
+ <name>EPRSET17</name>
+ <description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
+ <bitRange>[17:17]</bitRange>
+ </field>
+ <field>
+ <name>EPRSET18</name>
+ <description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
+ <bitRange>[18:18]</bitRange>
+ </field>
+ <field>
+ <name>EPRSET19</name>
+ <description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
+ <bitRange>[19:19]</bitRange>
+ </field>
+ <field>
+ <name>EPRSET20</name>
+ <description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
+ <bitRange>[20:20]</bitRange>
+ </field>
+ <field>
+ <name>EPRSET21</name>
+ <description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
+ <bitRange>[21:21]</bitRange>
+ </field>
+ <field>
+ <name>EPRSET22</name>
+ <description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
+ <bitRange>[22:22]</bitRange>
+ </field>
+ <field>
+ <name>EPRSET23</name>
+ <description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
+ <bitRange>[23:23]</bitRange>
+ </field>
+ <field>
+ <name>EPRSET24</name>
+ <description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
+ <bitRange>[24:24]</bitRange>
+ </field>
+ <field>
+ <name>EPRSET25</name>
+ <description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
+ <bitRange>[25:25]</bitRange>
+ </field>
+ <field>
+ <name>EPRSET26</name>
+ <description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
+ <bitRange>[26:26]</bitRange>
+ </field>
+ <field>
+ <name>EPRSET27</name>
+ <description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
+ <bitRange>[27:27]</bitRange>
+ </field>
+ <field>
+ <name>EPRSET28</name>
+ <description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
+ <bitRange>[28:28]</bitRange>
+ </field>
+ <field>
+ <name>EPRSET29</name>
+ <description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
+ <bitRange>[29:29]</bitRange>
+ </field>
+ <field>
+ <name>EPRSET30</name>
+ <description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
+ <bitRange>[30:30]</bitRange>
+ </field>
+ <field>
+ <name>EPRSET31</name>
+ <description>Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.</description>
+ <bitRange>[31:31]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>UDCAH</name>
+ <description>USB UDCA Head</description>
+ <addressOffset>0x280</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written. The UDCA is aligned to 128-byte boundaries.</description>
+ <bitRange>[6:0]</bitRange>
+ </field>
+ <field>
+ <name>UDCA_ADDR</name>
+ <description>Start address of the UDCA.</description>
+ <bitRange>[31:7]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>EPDMAST</name>
+ <description>USB Endpoint DMA Status</description>
+ <addressOffset>0x284</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>EP_DMA_ST0</name>
+ <description>Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit must be 0).</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_ST1</name>
+ <description>Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0).</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_ST2</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_ST3</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_ST4</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_ST5</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_ST6</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_ST7</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_ST8</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_ST9</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_ST10</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_ST11</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_ST12</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_ST13</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_ST14</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_ST15</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_ST16</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
+ <bitRange>[16:16]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_ST17</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
+ <bitRange>[17:17]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_ST18</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
+ <bitRange>[18:18]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_ST19</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
+ <bitRange>[19:19]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_ST20</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
+ <bitRange>[20:20]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_ST21</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
+ <bitRange>[21:21]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_ST22</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
+ <bitRange>[22:22]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_ST23</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
+ <bitRange>[23:23]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_ST24</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
+ <bitRange>[24:24]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_ST25</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
+ <bitRange>[25:25]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_ST26</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
+ <bitRange>[26:26]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_ST27</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
+ <bitRange>[27:27]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_ST28</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
+ <bitRange>[28:28]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_ST29</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
+ <bitRange>[29:29]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_ST30</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
+ <bitRange>[30:30]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_ST31</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.</description>
+ <bitRange>[31:31]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>EPDMAEN</name>
+ <description>USB Endpoint DMA Enable</description>
+ <addressOffset>0x288</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>EP_DMA_EN0</name>
+ <description>Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit value must be 0).</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_EN1</name>
+ <description>Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0).</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_EN</name>
+ <description>Endpoint xx(2 <= xx <= 31) DMA enable control bit. 0 = No effect. 1 = Enable the DMA operation for endpoint EPxx.</description>
+ <bitRange>[31:2]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>EPDMADIS</name>
+ <description>USB Endpoint DMA Disable</description>
+ <addressOffset>0x28C</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>EP_DMA_DIS0</name>
+ <description>Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_DISABLE bit value must be 0).</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_DIS1</name>
+ <description>Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_DISABLE bit value must be 0).</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_DIS2</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_DIS3</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_DIS4</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_DIS5</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_DIS6</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_DIS7</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_DIS8</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_DIS9</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_DIS10</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_DIS11</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_DIS12</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_DIS13</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_DIS14</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_DIS15</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_DIS16</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
+ <bitRange>[16:16]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_DIS17</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
+ <bitRange>[17:17]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_DIS18</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
+ <bitRange>[18:18]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_DIS19</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
+ <bitRange>[19:19]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_DIS20</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
+ <bitRange>[20:20]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_DIS21</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
+ <bitRange>[21:21]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_DIS22</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
+ <bitRange>[22:22]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_DIS23</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
+ <bitRange>[23:23]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_DIS24</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
+ <bitRange>[24:24]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_DIS25</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
+ <bitRange>[25:25]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_DIS26</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
+ <bitRange>[26:26]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_DIS27</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
+ <bitRange>[27:27]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_DIS28</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
+ <bitRange>[28:28]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_DIS29</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
+ <bitRange>[29:29]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_DIS30</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
+ <bitRange>[30:30]</bitRange>
+ </field>
+ <field>
+ <name>EP_DMA_DIS31</name>
+ <description>Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.</description>
+ <bitRange>[31:31]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMAINTST</name>
+ <description>USB DMA Interrupt Status</description>
+ <addressOffset>0x290</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>EOT</name>
+ <description>End of Transfer Interrupt bit.</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>ALL_BITS_IN_THE_USBE</name>
+ <description>All bits in the USBEoTIntSt register are 0.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>AT_LEAST_ONE_BIT_IN_</name>
+ <description>At least one bit in the USBEoTIntSt is set.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>NDDR</name>
+ <description>New DD Request Interrupt bit.</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>ALL_BITS_IN_THE_USBN</name>
+ <description>All bits in the USBNDDRIntSt register are 0.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>AT_LEAST_ONE_BIT_IN_</name>
+ <description>At least one bit in the USBNDDRIntSt is set.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>ERR</name>
+ <description>System Error Interrupt bit.</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>ALL_BITS_IN_THE_USBS</name>
+ <description>All bits in the USBSysErrIntSt register are 0.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>AT_LEAST_ONE_BIT_IN_</name>
+ <description>At least one bit in the USBSysErrIntSt is set.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:3]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>DMAINTEN</name>
+ <description>USB DMA Interrupt Enable</description>
+ <addressOffset>0x294</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>EOT</name>
+ <description>End of Transfer Interrupt enable bit.</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLED_</name>
+ <description>Disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLED_</name>
+ <description>Enabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>NDDR</name>
+ <description>New DD Request Interrupt enable bit.</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLED_</name>
+ <description>Disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLED_</name>
+ <description>Enabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>ERR</name>
+ <description>System Error Interrupt enable bit.</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLED_</name>
+ <description>Disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLED_</name>
+ <description>Enabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:3]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>EOTINTST</name>
+ <description>USB End of Transfer Interrupt Status</description>
+ <addressOffset>0x2A0</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>EPTXINTST0</name>
+ <description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>EPTXINTST1</name>
+ <description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>EPTXINTST2</name>
+ <description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>EPTXINTST3</name>
+ <description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>EPTXINTST4</name>
+ <description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>EPTXINTST5</name>
+ <description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>EPTXINTST6</name>
+ <description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>EPTXINTST7</name>
+ <description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>EPTXINTST8</name>
+ <description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>EPTXINTST9</name>
+ <description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>EPTXINTST10</name>
+ <description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>EPTXINTST11</name>
+ <description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>EPTXINTST12</name>
+ <description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>EPTXINTST13</name>
+ <description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>EPTXINTST14</name>
+ <description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>EPTXINTST15</name>
+ <description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>EPTXINTST16</name>
+ <description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
+ <bitRange>[16:16]</bitRange>
+ </field>
+ <field>
+ <name>EPTXINTST17</name>
+ <description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
+ <bitRange>[17:17]</bitRange>
+ </field>
+ <field>
+ <name>EPTXINTST18</name>
+ <description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
+ <bitRange>[18:18]</bitRange>
+ </field>
+ <field>
+ <name>EPTXINTST19</name>
+ <description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
+ <bitRange>[19:19]</bitRange>
+ </field>
+ <field>
+ <name>EPTXINTST20</name>
+ <description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
+ <bitRange>[20:20]</bitRange>
+ </field>
+ <field>
+ <name>EPTXINTST21</name>
+ <description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
+ <bitRange>[21:21]</bitRange>
+ </field>
+ <field>
+ <name>EPTXINTST22</name>
+ <description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
+ <bitRange>[22:22]</bitRange>
+ </field>
+ <field>
+ <name>EPTXINTST23</name>
+ <description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
+ <bitRange>[23:23]</bitRange>
+ </field>
+ <field>
+ <name>EPTXINTST24</name>
+ <description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
+ <bitRange>[24:24]</bitRange>
+ </field>
+ <field>
+ <name>EPTXINTST25</name>
+ <description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
+ <bitRange>[25:25]</bitRange>
+ </field>
+ <field>
+ <name>EPTXINTST26</name>
+ <description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
+ <bitRange>[26:26]</bitRange>
+ </field>
+ <field>
+ <name>EPTXINTST27</name>
+ <description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
+ <bitRange>[27:27]</bitRange>
+ </field>
+ <field>
+ <name>EPTXINTST28</name>
+ <description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
+ <bitRange>[28:28]</bitRange>
+ </field>
+ <field>
+ <name>EPTXINTST29</name>
+ <description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
+ <bitRange>[29:29]</bitRange>
+ </field>
+ <field>
+ <name>EPTXINTST30</name>
+ <description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
+ <bitRange>[30:30]</bitRange>
+ </field>
+ <field>
+ <name>EPTXINTST31</name>
+ <description>Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.</description>
+ <bitRange>[31:31]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>EOTINTCLR</name>
+ <description>USB End of Transfer Interrupt Clear</description>
+ <addressOffset>0x2A4</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>EPTXINTCLR0</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>EPTXINTCLR1</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[1:1]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTCLR2</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[2:2]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTCLR3</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[3:3]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTCLR4</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[4:4]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTCLR5</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[5:5]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTCLR6</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[6:6]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTCLR7</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[7:7]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTCLR8</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[8:8]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTCLR9</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[9:9]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTCLR10</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[10:10]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTCLR11</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[11:11]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTCLR12</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[12:12]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTCLR13</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[13:13]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTCLR14</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[14:14]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTCLR15</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[15:15]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTCLR16</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[16:16]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTCLR17</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[17:17]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTCLR18</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[18:18]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTCLR19</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[19:19]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTCLR20</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[20:20]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTCLR21</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[21:21]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTCLR22</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[22:22]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTCLR23</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[23:23]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTCLR24</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[24:24]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTCLR25</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[25:25]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTCLR26</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[26:26]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTCLR27</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[27:27]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTCLR28</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[28:28]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTCLR29</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[29:29]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTCLR30</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[30:30]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTCLR31</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[31:31]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>EOTINTSET</name>
+ <description>USB End of Transfer Interrupt Set</description>
+ <addressOffset>0x2A8</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>EPTXINTSET0</name>
+ <description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[0:0]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTSET1</name>
+ <description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[1:1]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTSET2</name>
+ <description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[2:2]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTSET3</name>
+ <description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[3:3]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTSET4</name>
+ <description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[4:4]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTSET5</name>
+ <description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[5:5]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTSET6</name>
+ <description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[6:6]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTSET7</name>
+ <description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[7:7]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTSET8</name>
+ <description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[8:8]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTSET9</name>
+ <description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[9:9]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTSET10</name>
+ <description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[10:10]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTSET11</name>
+ <description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[11:11]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTSET12</name>
+ <description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[12:12]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTSET13</name>
+ <description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[13:13]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTSET14</name>
+ <description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[14:14]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTSET15</name>
+ <description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[15:15]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTSET16</name>
+ <description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[16:16]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTSET17</name>
+ <description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[17:17]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTSET18</name>
+ <description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[18:18]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTSET19</name>
+ <description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[19:19]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTSET20</name>
+ <description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[20:20]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTSET21</name>
+ <description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[21:21]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTSET22</name>
+ <description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[22:22]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTSET23</name>
+ <description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[23:23]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTSET24</name>
+ <description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[24:24]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTSET25</name>
+ <description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[25:25]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTSET26</name>
+ <description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[26:26]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTSET27</name>
+ <description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[27:27]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTSET28</name>
+ <description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[28:28]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTSET29</name>
+ <description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[29:29]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTSET30</name>
+ <description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[30:30]</bitRange>
+
+ </field>
+ <field>
+ <name>EPTXINTSET31</name>
+ <description>Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.</description>
+ <bitRange>[31:31]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>NDDRINTST</name>
+ <description>USB New DD Request Interrupt Status</description>
+ <addressOffset>0x2AC</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>EPNDDINTST0</name>
+ <description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
+ <bitRange>[0:0]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTST1</name>
+ <description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
+ <bitRange>[1:1]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTST2</name>
+ <description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
+ <bitRange>[2:2]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTST3</name>
+ <description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
+ <bitRange>[3:3]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTST4</name>
+ <description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
+ <bitRange>[4:4]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTST5</name>
+ <description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
+ <bitRange>[5:5]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTST6</name>
+ <description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
+ <bitRange>[6:6]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTST7</name>
+ <description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
+ <bitRange>[7:7]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTST8</name>
+ <description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
+ <bitRange>[8:8]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTST9</name>
+ <description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
+ <bitRange>[9:9]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTST10</name>
+ <description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
+ <bitRange>[10:10]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTST11</name>
+ <description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
+ <bitRange>[11:11]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTST12</name>
+ <description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
+ <bitRange>[12:12]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTST13</name>
+ <description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
+ <bitRange>[13:13]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTST14</name>
+ <description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
+ <bitRange>[14:14]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTST15</name>
+ <description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
+ <bitRange>[15:15]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTST16</name>
+ <description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
+ <bitRange>[16:16]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTST17</name>
+ <description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
+ <bitRange>[17:17]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTST18</name>
+ <description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
+ <bitRange>[18:18]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTST19</name>
+ <description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
+ <bitRange>[19:19]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTST20</name>
+ <description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
+ <bitRange>[20:20]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTST21</name>
+ <description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
+ <bitRange>[21:21]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTST22</name>
+ <description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
+ <bitRange>[22:22]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTST23</name>
+ <description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
+ <bitRange>[23:23]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTST24</name>
+ <description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
+ <bitRange>[24:24]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTST25</name>
+ <description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
+ <bitRange>[25:25]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTST26</name>
+ <description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
+ <bitRange>[26:26]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTST27</name>
+ <description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
+ <bitRange>[27:27]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTST28</name>
+ <description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
+ <bitRange>[28:28]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTST29</name>
+ <description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
+ <bitRange>[29:29]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTST30</name>
+ <description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
+ <bitRange>[30:30]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTST31</name>
+ <description>Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.</description>
+ <bitRange>[31:31]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>NDDRINTCLR</name>
+ <description>USB New DD Request Interrupt Clear</description>
+ <addressOffset>0x2B0</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>EPNDDINTCLR0</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[0:0]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTCLR1</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[1:1]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTCLR2</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[2:2]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTCLR3</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[3:3]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTCLR4</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[4:4]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTCLR5</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[5:5]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTCLR6</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[6:6]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTCLR7</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[7:7]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTCLR8</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[8:8]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTCLR9</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[9:9]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTCLR10</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[10:10]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTCLR11</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[11:11]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTCLR12</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[12:12]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTCLR13</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[13:13]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTCLR14</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[14:14]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTCLR15</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[15:15]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTCLR16</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[16:16]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTCLR17</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[17:17]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTCLR18</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[18:18]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTCLR19</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[19:19]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTCLR20</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[20:20]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTCLR21</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[21:21]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTCLR22</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[22:22]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTCLR23</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[23:23]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTCLR24</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[24:24]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTCLR25</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[25:25]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTCLR26</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[26:26]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTCLR27</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[27:27]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTCLR28</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[28:28]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTCLR29</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[29:29]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTCLR30</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[30:30]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTCLR31</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[31:31]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>NDDRINTSET</name>
+ <description>USB New DD Request Interrupt Set</description>
+ <addressOffset>0x2B4</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>EPNDDINTSET0</name>
+ <description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[0:0]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTSET1</name>
+ <description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[1:1]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTSET2</name>
+ <description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[2:2]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTSET3</name>
+ <description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[3:3]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTSET4</name>
+ <description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[4:4]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTSET5</name>
+ <description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[5:5]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTSET6</name>
+ <description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[6:6]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTSET7</name>
+ <description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[7:7]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTSET8</name>
+ <description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[8:8]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTSET9</name>
+ <description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[9:9]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTSET10</name>
+ <description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[10:10]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTSET11</name>
+ <description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[11:11]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTSET12</name>
+ <description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[12:12]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTSET13</name>
+ <description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[13:13]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTSET14</name>
+ <description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[14:14]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTSET15</name>
+ <description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[15:15]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTSET16</name>
+ <description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[16:16]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTSET17</name>
+ <description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[17:17]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTSET18</name>
+ <description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[18:18]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTSET19</name>
+ <description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[19:19]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTSET20</name>
+ <description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[20:20]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTSET21</name>
+ <description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[21:21]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTSET22</name>
+ <description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[22:22]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTSET23</name>
+ <description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[23:23]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTSET24</name>
+ <description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[24:24]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTSET25</name>
+ <description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[25:25]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTSET26</name>
+ <description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[26:26]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTSET27</name>
+ <description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[27:27]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTSET28</name>
+ <description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[28:28]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTSET29</name>
+ <description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[29:29]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTSET30</name>
+ <description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[30:30]</bitRange>
+
+ </field>
+ <field>
+ <name>EPNDDINTSET31</name>
+ <description>Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.</description>
+ <bitRange>[31:31]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SYSERRINTST</name>
+ <description>USB System Error Interrupt Status</description>
+ <addressOffset>0x2B8</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>EPERRINTST0</name>
+ <description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
+ <bitRange>[0:0]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTST1</name>
+ <description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
+ <bitRange>[1:1]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTST2</name>
+ <description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
+ <bitRange>[2:2]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTST3</name>
+ <description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
+ <bitRange>[3:3]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTST4</name>
+ <description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
+ <bitRange>[4:4]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTST5</name>
+ <description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
+ <bitRange>[5:5]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTST6</name>
+ <description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
+ <bitRange>[6:6]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTST7</name>
+ <description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
+ <bitRange>[7:7]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTST8</name>
+ <description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
+ <bitRange>[8:8]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTST9</name>
+ <description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
+ <bitRange>[9:9]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTST10</name>
+ <description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
+ <bitRange>[10:10]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTST11</name>
+ <description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
+ <bitRange>[11:11]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTST12</name>
+ <description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
+ <bitRange>[12:12]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTST13</name>
+ <description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
+ <bitRange>[13:13]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTST14</name>
+ <description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
+ <bitRange>[14:14]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTST15</name>
+ <description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
+ <bitRange>[15:15]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTST16</name>
+ <description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
+ <bitRange>[16:16]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTST17</name>
+ <description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
+ <bitRange>[17:17]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTST18</name>
+ <description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
+ <bitRange>[18:18]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTST19</name>
+ <description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
+ <bitRange>[19:19]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTST20</name>
+ <description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
+ <bitRange>[20:20]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTST21</name>
+ <description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
+ <bitRange>[21:21]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTST22</name>
+ <description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
+ <bitRange>[22:22]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTST23</name>
+ <description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
+ <bitRange>[23:23]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTST24</name>
+ <description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
+ <bitRange>[24:24]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTST25</name>
+ <description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
+ <bitRange>[25:25]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTST26</name>
+ <description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
+ <bitRange>[26:26]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTST27</name>
+ <description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
+ <bitRange>[27:27]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTST28</name>
+ <description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
+ <bitRange>[28:28]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTST29</name>
+ <description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
+ <bitRange>[29:29]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTST30</name>
+ <description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
+ <bitRange>[30:30]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTST31</name>
+ <description>Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.</description>
+ <bitRange>[31:31]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SYSERRINTCLR</name>
+ <description>USB System Error Interrupt Clear</description>
+ <addressOffset>0x2BC</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>EPERRINTCLR0</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[0:0]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTCLR1</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[1:1]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTCLR2</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[2:2]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTCLR3</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[3:3]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTCLR4</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[4:4]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTCLR5</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[5:5]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTCLR6</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[6:6]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTCLR7</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[7:7]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTCLR8</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[8:8]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTCLR9</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[9:9]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTCLR10</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[10:10]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTCLR11</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[11:11]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTCLR12</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[12:12]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTCLR13</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[13:13]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTCLR14</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[14:14]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTCLR15</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[15:15]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTCLR16</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[16:16]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTCLR17</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[17:17]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTCLR18</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[18:18]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTCLR19</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[19:19]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTCLR20</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[20:20]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTCLR21</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[21:21]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTCLR22</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[22:22]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTCLR23</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[23:23]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTCLR24</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[24:24]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTCLR25</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[25:25]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTCLR26</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[26:26]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTCLR27</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[27:27]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTCLR28</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[28:28]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTCLR29</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[29:29]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTCLR30</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[30:30]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTCLR31</name>
+ <description>Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[31:31]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>SYSERRINTSET</name>
+ <description>USB System Error Interrupt Set</description>
+ <addressOffset>0x2C0</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>EPERRINTSET0</name>
+ <description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[0:0]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTSET1</name>
+ <description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[1:1]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTSET2</name>
+ <description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[2:2]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTSET3</name>
+ <description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[3:3]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTSET4</name>
+ <description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[4:4]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTSET5</name>
+ <description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[5:5]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTSET6</name>
+ <description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[6:6]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTSET7</name>
+ <description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[7:7]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTSET8</name>
+ <description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[8:8]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTSET9</name>
+ <description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[9:9]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTSET10</name>
+ <description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[10:10]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTSET11</name>
+ <description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[11:11]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTSET12</name>
+ <description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[12:12]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTSET13</name>
+ <description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[13:13]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTSET14</name>
+ <description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[14:14]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTSET15</name>
+ <description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[15:15]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTSET16</name>
+ <description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[16:16]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTSET17</name>
+ <description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[17:17]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTSET18</name>
+ <description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[18:18]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTSET19</name>
+ <description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[19:19]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTSET20</name>
+ <description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[20:20]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTSET21</name>
+ <description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[21:21]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTSET22</name>
+ <description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[22:22]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTSET23</name>
+ <description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[23:23]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTSET24</name>
+ <description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[24:24]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTSET25</name>
+ <description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[25:25]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTSET26</name>
+ <description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[26:26]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTSET27</name>
+ <description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[27:27]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTSET28</name>
+ <description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[28:28]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTSET29</name>
+ <description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[29:29]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTSET30</name>
+ <description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[30:30]</bitRange>
+
+ </field>
+ <field>
+ <name>EPERRINTSET31</name>
+ <description>Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.</description>
+ <bitRange>[31:31]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+
+
+
+
+
+
+
+
+
+
+
+
+
+ <register>
+ <name>I2C_RX</name>
+ <description>I2C Receive</description>
+ <addressOffset>0x300</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>RXDATA</name>
+ <description>Receive data.</description>
+ <bitRange>[7:0]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>I2C_WO</name>
+ <description>I2C Transmit</description>
+ <alternateRegister>I2C_RX</alternateRegister>
+ <addressOffset>0x300</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>TXDATA</name>
+ <description>Transmit data.</description>
+ <bitRange>[7:0]</bitRange>
+ </field>
+ <field>
+ <name>START</name>
+ <description>When 1, issue a START condition before transmitting this byte.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>STOP</name>
+ <description>When 1, issue a STOP condition after transmitting this byte.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:10]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>I2C_STS</name>
+ <description>I2C Status</description>
+ <addressOffset>0x304</addressOffset>
+ <access>read-only</access>
+ <resetValue>0x0A00</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>TDI</name>
+ <description>Transaction Done Interrupt. This flag is set if a transaction completes successfully. It is cleared by writing a one to bit 0 of the status register. It is unaffected by slave transactions.</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>NOT_COMPLETE</name>
+ <description>Transaction has not completed.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>COMPLETE</name>
+ <description>Transaction completed.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>AFI</name>
+ <description>Arbitration Failure Interrupt. When transmitting, if the SDA is low when SDAOUT is high, then this I2C has lost the arbitration to another device on the bus. The Arbitration Failure bit is set when this happens. It is cleared by writing a one to bit 1 of the status register.</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>NO_ARBITRATION_FAILU</name>
+ <description>No arbitration failure on last transmission.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ARBITRATION_FAILURE_</name>
+ <description>Arbitration failure occurred on last transmission.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>NAI</name>
+ <description>No Acknowledge Interrupt. After every byte of data is sent, the transmitter expects an acknowledge from the receiver. This bit is set if the acknowledge is not received. It is cleared when a byte is written to the master TX FIFO.</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>ACKNOWLEDGE_RCVD</name>
+ <description>Last transmission received an acknowledge.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>NO_ACKNOWLEDGE_RCVD</name>
+ <description>Last transmission did not receive an acknowledge.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>DRMI</name>
+ <description>Master Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a stop condition or it will hold SCL low until more data is available. The Master Data Request bit is set when the master transmitter is data-starved. If the master TX FIFO is empty and the last byte did not have a STOP condition flag, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the master TX FIFO.</description>
+ <bitRange>[3:3]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>BUSY</name>
+ <description>Master transmitter does not need data.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>NEED_DATA</name>
+ <description>Master transmitter needs data.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>DRSI</name>
+ <description>Slave Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a STOP condition or it will hold SCL low until more data is available. The Slave Data Request bit is set when the slave transmitter is data-starved. If the slave TX FIFO is empty and the last byte transmitted was acknowledged, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the slave Tx FIFO.</description>
+ <bitRange>[4:4]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>BUSY</name>
+ <description>Slave transmitter does not need data.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>NEED_DATA</name>
+ <description>Slave transmitter needs data.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>Active</name>
+ <description>Indicates whether the bus is busy. This bit is set when a START condition has been seen. It is cleared when a STOP condition is seen..</description>
+ <bitRange>[5:5]</bitRange>
+
+ </field>
+ <field>
+ <name>SCL</name>
+ <description>The current value of the SCL signal.</description>
+ <bitRange>[6:6]</bitRange>
+
+ </field>
+ <field>
+ <name>SDA</name>
+ <description>The current value of the SDA signal.</description>
+ <bitRange>[7:7]</bitRange>
+
+ </field>
+ <field>
+ <name>RFF</name>
+ <description>Receive FIFO Full (RFF). This bit is set when the RX FIFO is full and cannot accept any more data. It is cleared when the RX FIFO is not full. If a byte arrives when the Receive FIFO is full, the SCL is held low until the CPU reads the RX FIFO and makes room for it.</description>
+ <bitRange>[8:8]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>RX_FIFO_IS_NOT_FULL</name>
+ <description>RX FIFO is not full</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RX_FIFO_IS_FULL</name>
+ <description>RX FIFO is full</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RFE</name>
+ <description>Receive FIFO Empty. RFE is set when the RX FIFO is empty and is cleared when the RX FIFO contains valid data.</description>
+ <bitRange>[9:9]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DATA</name>
+ <description>RX FIFO contains data.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>EMPTY</name>
+ <description>RX FIFO is empty</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TFF</name>
+ <description>Transmit FIFO Full. TFF is set when the TX FIFO is full and is cleared when the TX FIFO is not full.</description>
+ <bitRange>[10:10]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>TX_FIFO_IS_NOT_FULL_</name>
+ <description>TX FIFO is not full.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>TX_FIFO_IS_FULL</name>
+ <description>TX FIFO is full</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TFE</name>
+ <description>Transmit FIFO Empty. TFE is set when the TX FIFO is empty and is cleared when the TX FIFO contains valid data.</description>
+ <bitRange>[11:11]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>VALID_DATA</name>
+ <description>TX FIFO contains valid data.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>EMPTY</name>
+ <description>TX FIFO is empty</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:12]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>I2C_CTL</name>
+ <description>I2C Control</description>
+ <addressOffset>0x308</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>TDIE</name>
+ <description>Transmit Done Interrupt Enable. This enables the TDI interrupt signalling that this I2C issued a STOP condition.</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE_THE_TDI_INTE</name>
+ <description>Disable the TDI interrupt.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE_THE_TDI_INTER</name>
+ <description>Enable the TDI interrupt.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>AFIE</name>
+ <description>Transmitter Arbitration Failure Interrupt Enable. This enables the AFI interrupt which is asserted during transmission when trying to set SDA high, but the bus is driven low by another device.</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE_THE_AFI_</name>
+ <description>Disable the AFI.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE_THE_AFI_</name>
+ <description>Enable the AFI.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>NAIE</name>
+ <description>Transmitter No Acknowledge Interrupt Enable. This enables the NAI interrupt signalling that transmitted byte was not acknowledged.</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE_THE_NAI_</name>
+ <description>Disable the NAI.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE_THE_NAI_</name>
+ <description>Enable the NAI.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>DRMIE</name>
+ <description>Master Transmitter Data Request Interrupt Enable. This enables the DRMI interrupt which signals that the master transmitter has run out of data, has not issued a STOP, and is holding the SCL line low.</description>
+ <bitRange>[3:3]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE_THE_DRMI_INT</name>
+ <description>Disable the DRMI interrupt.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE_THE_DRMI_INTE</name>
+ <description>Enable the DRMI interrupt.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>DRSIE</name>
+ <description>Slave Transmitter Data Request Interrupt Enable. This enables the DRSI interrupt which signals that the slave transmitter has run out of data and the last byte was acknowledged, so the SCL line is being held low.</description>
+ <bitRange>[4:4]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE_THE_DRSI_INT</name>
+ <description>Disable the DRSI interrupt.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE_THE_DRSI_INTE</name>
+ <description>Enable the DRSI interrupt.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>REFIE</name>
+ <description>Receive FIFO Full Interrupt Enable. This enables the Receive FIFO Full interrupt to indicate that the receive FIFO cannot accept any more data.</description>
+ <bitRange>[5:5]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE_THE_RFFI_</name>
+ <description>Disable the RFFI.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE_THE_RFFI_</name>
+ <description>Enable the RFFI.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RFDAIE</name>
+ <description>Receive Data Available Interrupt Enable. This enables the DAI interrupt to indicate that data is available in the receive FIFO (i.e. not empty).</description>
+ <bitRange>[6:6]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE_THE_DAI_</name>
+ <description>Disable the DAI.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE_THE_DAI_</name>
+ <description>Enable the DAI.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TFFIE</name>
+ <description>Transmit FIFO Not Full Interrupt Enable. This enables the Transmit FIFO Not Full interrupt to indicate that the more data can be written to the transmit FIFO. Note that this is not full. It is intended help the CPU to write to the I2C block only when there is room in the FIFO and do this without polling the status register.</description>
+ <bitRange>[7:7]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE_THE_TFFI_</name>
+ <description>Disable the TFFI.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE_THE_TFFI_</name>
+ <description>Enable the TFFI.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>SRST</name>
+ <description>Soft reset. This is only needed in unusual circumstances. If a device issues a start condition without issuing a stop condition. A system timer may be used to reset the I2C if the bus remains busy longer than the time-out period. On a soft reset, the Tx and Rx FIFOs are flushed, I2C_STS register is cleared, and all internal state machines are reset to appear idle. The I2C_CLKHI, I2C_CLKLO and I2C_CTL (except Soft Reset Bit) are NOT modified by a soft reset.</description>
+ <bitRange>[8:8]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>NO_RESET</name>
+ <description>No reset.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>RESET</name>
+ <description>Reset the I2C to idle state. Self clearing.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:9]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>I2C_CLKHI</name>
+ <description>I2C Clock High</description>
+ <addressOffset>0x30C</addressOffset>
+ <access>read-write</access>
+ <resetValue>0xB9</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>CDHI</name>
+ <description>Clock divisor high. This value is the number of 48 MHz clocks the serial clock (SCL) will be high.</description>
+ <bitRange>[7:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>I2C_CLKLO</name>
+ <description>I2C Clock Low</description>
+ <addressOffset>0x310</addressOffset>
+ <access>write-only</access>
+ <resetValue>0xB9</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>CDLO</name>
+ <description>Clock divisor low. This value is the number of 48 MHz clocks the serial clock (SCL) will be low.</description>
+ <bitRange>[7:0]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:8]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>USBCLKCTRL</name>
+ <description>USB Clock Control</description>
+
+ <addressOffset>0xFF4</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>DEV_CLK_EN</name>
+ <description>Device clock enable. Enables the usbclk input to the device controller</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>PORTSEL_CLK_EN</name>
+ <description>Port select register clock enable.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>AHB_CLK_EN</name>
+ <description>AHB clock enable</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:5]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>OTGCLKCTRL</name>
+ <description>OTG clock controller</description>
+ <alternateRegister>USBCLKCTRL</alternateRegister>
+ <addressOffset>0xFF4</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>HOST_CLK_EN</name>
+ <description>Host clock enable</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE_THE_HOST_CLO</name>
+ <description>Disable the Host clock.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE_THE_HOST_CLOC</name>
+ <description>Enable the Host clock.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>DEV_CLK_EN</name>
+ <description>Device clock enable</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE_THE_DEVICE_C</name>
+ <description>Disable the Device clock.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE_THE_DEVICE_CL</name>
+ <description>Enable the Device clock.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>I2C_CLK_EN</name>
+ <description>I2C clock enable</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE_THE_I2C_CLOC</name>
+ <description>Disable the I2C clock.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE_THE_I2C_CLOCK</name>
+ <description>Enable the I2C clock.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>OTG_CLK_EN</name>
+ <description>OTG clock enable. In device-only applications, this bit enables access to the PORTSEL register.</description>
+ <bitRange>[3:3]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE_THE_OTG_CLOC</name>
+ <description>Disable the OTG clock.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE_THE_OTG_CLOCK</name>
+ <description>Enable the OTG clock.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>AHB_CLK_EN</name>
+ <description>AHB master clock enable</description>
+ <bitRange>[4:4]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DISABLE_THE_AHB_CLOC</name>
+ <description>Disable the AHB clock.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ENABLE_THE_AHB_CLOCK</name>
+ <description>Enable the AHB clock.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:5]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>USBCLKST</name>
+ <description>USB Clock Status</description>
+
+ <addressOffset>0xFF8</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>DEV_CLK_ON</name>
+ <description>Device clock on. The usbclk input to the device controller is active .</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>PORTSEL_CLK_ON</name>
+ <description>Port select register clock on.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>AHB_CLK_ON</name>
+ <description>AHB clock on.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. The value read from a reserved bit is not defined.</description>
+ <bitRange>[31:5]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>OTGCLKST</name>
+ <description>OTG clock status</description>
+ <alternateRegister>USBCLKST</alternateRegister>
+ <addressOffset>0xFF8</addressOffset>
+ <access>read-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>HOST_CLK_ON</name>
+ <description>Host clock status.</description>
+ <bitRange>[0:0]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>HOST_CLOCK_IS_NOT_AV</name>
+ <description>Host clock is not available.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>HOST_CLOCK_IS_AVAILA</name>
+ <description>Host clock is available.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>DEV_CLK_ON</name>
+ <description>Device clock status.</description>
+ <bitRange>[1:1]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>DEVICE_CLOCK_IS_NOT_</name>
+ <description>Device clock is not available.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DEVICE_CLOCK_IS_AVAI</name>
+ <description>Device clock is available.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>I2C_CLK_ON</name>
+ <description>I2C clock status.</description>
+ <bitRange>[2:2]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>I2C_CLOCK_IS_NOT_AVA</name>
+ <description>I2C clock is not available.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>I2C_CLOCK_IS_AVAILAB</name>
+ <description>I2C clock is available.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>OTG_CLK_ON</name>
+ <description>OTG clock status.</description>
+ <bitRange>[3:3]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>OTG_CLOCK_IS_NOT_AVA</name>
+ <description>OTG clock is not available.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>OTG_CLOCK_IS_AVAILAB</name>
+ <description>OTG clock is available.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>AHB_CLK_ON</name>
+ <description>AHB master clock status.</description>
+ <bitRange>[4:4]</bitRange>
+ <enumeratedValues>
+ <name>ENUM</name>
+ <enumeratedValue>
+ <name>AHB_CLOCK_IS_NOT_AVA</name>
+ <description>AHB clock is not available.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>AHB_CLOCK_IS_AVAILAB</name>
+ <description>AHB clock is available.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>RESERVED</name>
+ <description>Reserved. Read value is undefined, only zero should be written.</description>
+ <bitRange>[31:5]</bitRange>
+
+ </field>
+ </fields>
+ </register>
+
+
+
+
+
+
+ </registers>
+ </peripheral>
+
+ <peripheral>
+ <name>GPIO</name>
+ <description>General Purpose I/O </description>
+ <groupName>GPIO</groupName>
+ <baseAddress>0x2009C000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0xFFF</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <registers>
+ <register>
+ <dim>5</dim>
+ <dimIncrement>0x20</dimIncrement>
+ <dimIndex>0-4</dimIndex>
+ <name>DIR%s</name>
+ <description>GPIO Port Direction control register.</description>
+ <addressOffset>0x000</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>PINDIR0</name>
+ <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>PINDIR1</name>
+ <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>PINDIR2</name>
+ <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>PINDIR3</name>
+ <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>PINDIR4</name>
+ <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>PINDIR5</name>
+ <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>PINDIR6</name>
+ <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>PINDIR7</name>
+ <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>PINDIR8</name>
+ <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>PINDIR9</name>
+ <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>PINDIR10</name>
+ <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>PINDIR11</name>
+ <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>PINDIR12</name>
+ <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>PINDIR13</name>
+ <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>PINDIR14</name>
+ <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>PINDIR15</name>
+ <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>PINDIR16</name>
+ <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
+ <bitRange>[16:16]</bitRange>
+ </field>
+ <field>
+ <name>PINDIR17</name>
+ <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
+ <bitRange>[17:17]</bitRange>
+ </field>
+ <field>
+ <name>PINDIR18</name>
+ <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
+ <bitRange>[18:18]</bitRange>
+ </field>
+ <field>
+ <name>PINDIR19</name>
+ <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
+ <bitRange>[19:19]</bitRange>
+ </field>
+ <field>
+ <name>PINDIR20</name>
+ <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
+ <bitRange>[20:20]</bitRange>
+ </field>
+ <field>
+ <name>PINDIR21</name>
+ <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
+ <bitRange>[21:21]</bitRange>
+ </field>
+ <field>
+ <name>PINDIR22</name>
+ <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
+ <bitRange>[22:22]</bitRange>
+ </field>
+ <field>
+ <name>PINDIR23</name>
+ <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
+ <bitRange>[23:23]</bitRange>
+ </field>
+ <field>
+ <name>PINDIR24</name>
+ <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
+ <bitRange>[24:24]</bitRange>
+ </field>
+ <field>
+ <name>PINDIR25</name>
+ <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
+ <bitRange>[25:25]</bitRange>
+ </field>
+ <field>
+ <name>PINDIR26</name>
+ <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
+ <bitRange>[26:26]</bitRange>
+ </field>
+ <field>
+ <name>PINDIR27</name>
+ <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
+ <bitRange>[27:27]</bitRange>
+ </field>
+ <field>
+ <name>PINDIR28</name>
+ <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
+ <bitRange>[28:28]</bitRange>
+ </field>
+ <field>
+ <name>PINDIR29</name>
+ <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
+ <bitRange>[29:29]</bitRange>
+ </field>
+ <field>
+ <name>PINDIR30</name>
+ <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
+ <bitRange>[30:30]</bitRange>
+ </field>
+ <field>
+ <name>PINDIR31</name>
+ <description>Fast GPIO Direction PORTx control bits. Bit 0 in DIRx controls pin Px[0], bit 31 in DIRx controls pin Px[31]. 0 = Controlled pin is input. 1 = Controlled pin is output.</description>
+ <bitRange>[31:31]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <dim>5</dim>
+ <dimIncrement>0x20</dimIncrement>
+ <dimIndex>0-4</dimIndex>
+ <name>MASK%s</name>
+ <description>Mask register for Port.</description>
+ <addressOffset>0x010</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>PINMASK0</name>
+ <description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>PINMASK1</name>
+ <description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>PINMASK2</name>
+ <description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>PINMASK3</name>
+ <description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>PINMASK4</name>
+ <description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>PINMASK5</name>
+ <description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>PINMASK6</name>
+ <description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>PINMASK7</name>
+ <description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>PINMASK8</name>
+ <description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>PINMASK9</name>
+ <description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>PINMASK10</name>
+ <description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>PINMASK11</name>
+ <description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>PINMASK12</name>
+ <description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>PINMASK13</name>
+ <description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>PINMASK14</name>
+ <description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin.</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>PINMASK15</name>
+ <description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>PINMASK16</name>
+ <description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin.</description>
+ <bitRange>[16:16]</bitRange>
+ </field>
+ <field>
+ <name>PINMASK17</name>
+ <description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin.</description>
+ <bitRange>[17:17]</bitRange>
+ </field>
+ <field>
+ <name>PINMASK18</name>
+ <description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin.</description>
+ <bitRange>[18:18]</bitRange>
+ </field>
+ <field>
+ <name>PINMASK19</name>
+ <description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin.</description>
+ <bitRange>[19:19]</bitRange>
+ </field>
+ <field>
+ <name>PINMASK20</name>
+ <description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin.</description>
+ <bitRange>[20:20]</bitRange>
+ </field>
+ <field>
+ <name>PINMASK21</name>
+ <description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin.</description>
+ <bitRange>[21:21]</bitRange>
+ </field>
+ <field>
+ <name>PINMASK22</name>
+ <description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin.</description>
+ <bitRange>[22:22]</bitRange>
+ </field>
+ <field>
+ <name>PINMASK23</name>
+ <description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin.</description>
+ <bitRange>[23:23]</bitRange>
+ </field>
+ <field>
+ <name>PINMASK24</name>
+ <description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin.</description>
+ <bitRange>[24:24]</bitRange>
+ </field>
+ <field>
+ <name>PINMASK25</name>
+ <description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin.</description>
+ <bitRange>[25:25]</bitRange>
+ </field>
+ <field>
+ <name>PINMASK26</name>
+ <description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin.</description>
+ <bitRange>[26:26]</bitRange>
+ </field>
+ <field>
+ <name>PINMASK27</name>
+ <description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin.</description>
+ <bitRange>[27:27]</bitRange>
+ </field>
+ <field>
+ <name>PINMASK28</name>
+ <description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin.</description>
+ <bitRange>[28:28]</bitRange>
+ </field>
+ <field>
+ <name>PINMASK29</name>
+ <description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin.</description>
+ <bitRange>[29:29]</bitRange>
+ </field>
+ <field>
+ <name>PINMASK30</name>
+ <description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin.</description>
+ <bitRange>[30:30]</bitRange>
+ </field>
+ <field>
+ <name>PINMASK31</name>
+ <description>Fast GPIO physical pin access control. 0 = Controlled pin is affected by writes to the port's SETx, CLRx, and PINx register(s). Current state of the pin can be read from the PINx register. 1 = Controlled pin is not affected by writes into the port's SETx, CLRx and PINx register(s). When the PINx register is read, this bit will not be updated with the state of the physical pin.</description>
+ <bitRange>[31:31]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <dim>5</dim>
+ <dimIncrement>0x20</dimIncrement>
+ <dimIndex>0-4</dimIndex>
+ <name>PIN%s</name>
+ <description>Port Pin value register using FIOMASK.</description>
+ <addressOffset>0x014</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>PINVAL0</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>PINVAL1</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>PINVAL2</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>PINVAL3</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>PINVAL4</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>PINVAL5</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>PINVAL6</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>PINVAL7</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>PINVAL8</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>PINVAL9</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>PINVAL10</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>PINVAL11</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>PINVAL12</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>PINVAL13</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>PINVAL14</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>PINVAL15</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>PINVAL16</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[16:16]</bitRange>
+ </field>
+ <field>
+ <name>PINVAL17</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[17:17]</bitRange>
+ </field>
+ <field>
+ <name>PINVAL18</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[18:18]</bitRange>
+ </field>
+ <field>
+ <name>PINVAL19</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[19:19]</bitRange>
+ </field>
+ <field>
+ <name>PINVAL20</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[20:20]</bitRange>
+ </field>
+ <field>
+ <name>PINVAL21</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[21:21]</bitRange>
+ </field>
+ <field>
+ <name>PINVAL22</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[22:22]</bitRange>
+ </field>
+ <field>
+ <name>PINVAL23</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[23:23]</bitRange>
+ </field>
+ <field>
+ <name>PINVAL24</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[24:24]</bitRange>
+ </field>
+ <field>
+ <name>PINVAL25</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[25:25]</bitRange>
+ </field>
+ <field>
+ <name>PINVAL26</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[26:26]</bitRange>
+ </field>
+ <field>
+ <name>PINVAL27</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[27:27]</bitRange>
+ </field>
+ <field>
+ <name>PINVAL28</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[28:28]</bitRange>
+ </field>
+ <field>
+ <name>PINVAL29</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[29:29]</bitRange>
+ </field>
+ <field>
+ <name>PINVAL30</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[30:30]</bitRange>
+ </field>
+ <field>
+ <name>PINVAL31</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in PINx corresponds to pin Px[0], bit 31 in PINx corresponds to pin Px[31]. 0 = Controlled pin output is set to LOW. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[31:31]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <dim>5</dim>
+ <dimIncrement>0x20</dimIncrement>
+ <dimIndex>0-4</dimIndex>
+ <name>SET%s</name>
+ <description>Port Output Set register using FIOMASK.</description>
+ <addressOffset>0x018</addressOffset>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>PINSET0</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>PINSET1</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>PINSET2</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>PINSET3</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>PINSET4</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>PINSET5</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>PINSET6</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>PINSET7</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>PINSET8</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>PINSET9</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>PINSET10</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>PINSET11</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>PINSET12</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>PINSET13</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>PINSET14</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>PINSET15</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>PINSET16</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[16:16]</bitRange>
+ </field>
+ <field>
+ <name>PINSET17</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[17:17]</bitRange>
+ </field>
+ <field>
+ <name>PINSET18</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[18:18]</bitRange>
+ </field>
+ <field>
+ <name>PINSET19</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[19:19]</bitRange>
+ </field>
+ <field>
+ <name>PINSET20</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[20:20]</bitRange>
+ </field>
+ <field>
+ <name>PINSET21</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[21:21]</bitRange>
+ </field>
+ <field>
+ <name>PINSET22</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[22:22]</bitRange>
+ </field>
+ <field>
+ <name>PINSET23</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[23:23]</bitRange>
+ </field>
+ <field>
+ <name>PINSET24</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[24:24]</bitRange>
+ </field>
+ <field>
+ <name>PINSET25</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[25:25]</bitRange>
+ </field>
+ <field>
+ <name>PINSET26</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[26:26]</bitRange>
+ </field>
+ <field>
+ <name>PINSET27</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[27:27]</bitRange>
+ </field>
+ <field>
+ <name>PINSET28</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[28:28]</bitRange>
+ </field>
+ <field>
+ <name>PINSET29</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[29:29]</bitRange>
+ </field>
+ <field>
+ <name>PINSET30</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[30:30]</bitRange>
+ </field>
+ <field>
+ <name>PINSET31</name>
+ <description>Fast GPIO output value Set bits. Bit 0 in SETx controls pin Px[0], bit 31 in SETx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to HIGH.</description>
+ <bitRange>[31:31]</bitRange>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <dim>5</dim>
+ <dimIncrement>0x20</dimIncrement>
+ <dimIndex>0-4</dimIndex>
+ <name>CLR%s</name>
+ <description>Port Output Clear register using FIOMASK.</description>
+ <addressOffset>0x01C</addressOffset>
+ <access>write-only</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xFFFFFFFF</resetMask>
+ <fields>
+ <field>
+ <name>PINCLR0</name>
+ <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
+ <bitRange>[0:0]</bitRange>
+ </field>
+ <field>
+ <name>PINCLR1</name>
+ <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
+ <bitRange>[1:1]</bitRange>
+ </field>
+ <field>
+ <name>PINCLR2</name>
+ <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>PINCLR3</name>
+ <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>PINCLR4</name>
+ <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>PINCLR5</name>
+ <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
+ <field>
+ <name>PINCLR6</name>
+ <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
+ <bitRange>[6:6]</bitRange>
+ </field>
+ <field>
+ <name>PINCLR7</name>
+ <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
+ <bitRange>[7:7]</bitRange>
+ </field>
+ <field>
+ <name>PINCLR8</name>
+ <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
+ <bitRange>[8:8]</bitRange>
+ </field>
+ <field>
+ <name>PINCLR9</name>
+ <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
+ <bitRange>[9:9]</bitRange>
+ </field>
+ <field>
+ <name>PINCLR10</name>
+ <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
+ <bitRange>[10:10]</bitRange>
+ </field>
+ <field>
+ <name>PINCLR11</name>
+ <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
+ <bitRange>[11:11]</bitRange>
+ </field>
+ <field>
+ <name>PINCLR12</name>
+ <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
+ <bitRange>[12:12]</bitRange>
+ </field>
+ <field>
+ <name>PINCLR13</name>
+ <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
+ <bitRange>[13:13]</bitRange>
+ </field>
+ <field>
+ <name>PINCLR14</name>
+ <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
+ <bitRange>[14:14]</bitRange>
+ </field>
+ <field>
+ <name>PINCLR15</name>
+ <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
+ <bitRange>[15:15]</bitRange>
+ </field>
+ <field>
+ <name>PINCLR16</name>
+ <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
+ <bitRange>[16:16]</bitRange>
+ </field>
+ <field>
+ <name>PINCLR17</name>
+ <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
+ <bitRange>[17:17]</bitRange>
+ </field>
+ <field>
+ <name>PINCLR18</name>
+ <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
+ <bitRange>[18:18]</bitRange>
+ </field>
+ <field>
+ <name>PINCLR19</name>
+ <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
+ <bitRange>[19:19]</bitRange>
+ </field>
+ <field>
+ <name>PINCLR20</name>
+ <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
+ <bitRange>[20:20]</bitRange>
+ </field>
+ <field>
+ <name>PINCLR21</name>
+ <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
+ <bitRange>[21:21]</bitRange>
+ </field>
+ <field>
+ <name>PINCLR22</name>
+ <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
+ <bitRange>[22:22]</bitRange>
+ </field>
+ <field>
+ <name>PINCLR23</name>
+ <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
+ <bitRange>[23:23]</bitRange>
+ </field>
+ <field>
+ <name>PINCLR24</name>
+ <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
+ <bitRange>[24:24]</bitRange>
+ </field>
+ <field>
+ <name>PINCLR25</name>
+ <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
+ <bitRange>[25:25]</bitRange>
+ </field>
+ <field>
+ <name>PINCLR26</name>
+ <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
+ <bitRange>[26:26]</bitRange>
+ </field>
+ <field>
+ <name>PINCLR27</name>
+ <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
+ <bitRange>[27:27]</bitRange>
+ </field>
+ <field>
+ <name>PINCLR28</name>
+ <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
+ <bitRange>[28:28]</bitRange>
+ </field>
+ <field>
+ <name>PINCLR29</name>
+ <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
+ <bitRange>[29:29]</bitRange>
+ </field>
+ <field>
+ <name>PINCLR30</name>
+ <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
+ <bitRange>[30:30]</bitRange>
+ </field>
+ <field>
+ <name>PINCLR31</name>
+ <description>Fast GPIO output value Clear bits. Bit 0 in CLRx controls pin Px[0], bit 31 in CLRx controls pin Px[31]. 0 = Controlled pin output is unchanged. 1 = Controlled pin output is set to LOW.</description>
+ <bitRange>[31:31]</bitRange>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ </peripherals>
+</device>
diff --git a/Makefile b/Makefile
@@ -0,0 +1,153 @@
+# Be silent per default, but 'make V=1' will show all compiler calls.
+ifneq ($(V),1)
+Q := @
+NULL := 2>/dev/null
+endif
+
+.DEFAULT_GOAL := all
+
+# toolchain
+TOOLCHAIN = arm-none-eabi-
+CC = $(TOOLCHAIN)gcc
+DB = $(TOOLCHAIN)gdb
+CP = $(TOOLCHAIN)objcopy
+# AS = $(TOOLCHAIN)gcc -x assembler-with-cpp
+AS = $(TOOLCHAIN)as
+HEX = $(CP) -O ihex
+BIN = $(CP) -O binary #-S --gap-fill 0xFF
+
+# define mcu, specify the target processor
+MCU = cortex-m3
+
+ROOT_DIR = .
+SRC_DIR = $(ROOT_DIR)/src
+include $(SRC_DIR)/globals/make-version.mk
+include $(SRC_DIR)/app/make-app.mk
+include $(SRC_DIR)/shared/make-shared.mk
+# include $(SRC_DIR)/bl/make-bl.mk
+
+# all the files will be generated with this name (main.elf, main.bin, main.hex, etc)
+PROJECT_NAME = app
+APP_NAME = $(PROJECT_NAME)-$(VERSION)
+# BL_NAME = $(PROJECT_NAME)-bl
+
+APP_INC += -I$(SRC_DIR) $(APPLICATION_INC)
+
+# CPU defs
+# DEFS += -DSTM32F4
+# FP_FLAGS ?= -mfloat-abi=hard -mfpu=fpv4-sp-d16
+ARCH_FLAGS = -mthumb -mcpu=$(MCU) #$(FP_FLAGS)
+
+# Compile flags
+OPT := -Os
+DEBUG := -ggdb3
+CSTD ?= -std=c11
+
+BUILD_DIR = $(ROOT_DIR)/build
+
+APP_OBJ = $(addprefix $(BUILD_DIR)/,$(notdir $(APP_SRC_C:.c=.o)))
+APP_OBJ += $(addprefix $(BUILD_DIR)/,$(notdir $(APP_SRC_S:.s=.o)))
+vpath %.c $(sort $(dir $(APP_SRC_C)))
+vpath %.s $(sort $(dir $(APP_SRC_S)))
+
+# BL_OBJ = $(addprefix $(BUILD_DIR)/,$(notdir $(BL_SRC:.c=.o)))
+# vpath %.c $(sort $(dir $(BL_SRC)))
+
+
+
+###############################################################################
+# C flags
+TGT_CFLAGS += $(OPT) $(CSTD) $(DEBUG)
+TGT_CFLAGS += $(ARCH_FLAGS)
+TGT_CFLAGS += -Wall -Wextra -Wpedantic -Wshadow -Wdouble-promotion -Wformat=2 \
+ -Wformat-truncation -Wundef -fno-common -MD $(DEFS) -Wimplicit-function-declaration \
+
+TGT_CFLAGS += -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes
+TGT_CFLAGS += -ffunction-sections -fdata-sections
+
+TGT_AFLAGS = -mcpu=$(MCU)
+TGT_AFLAGS += -gdwarf-2
+
+###############################################################################
+# Linker flags
+TGT_LDFLAGS += --static -nostartfiles
+TGT_LDFLAGS += $(ARCH_FLAGS) $(DEBUG)
+TGT_LDFLAGS += -Wl,--cref
+TGT_LDFLAGS += -Wl,--gc-sections
+TGT_LDFLAGS += -Wl,--print-memory-usage
+TGT_LDFLAGS += --specs=rdimon.specs -u _printf_float
+ifeq ($(V),99)
+TGT_LDFLAGS += -Wl,--print-gc-sections
+endif
+
+###############################################################################
+# Used libraries
+LDLIBS += -Wl,--start-group -lc -lgcc -lnosys -Wl,--end-group
+
+APP_LDFLAGS += -Wl,-Map=$(BUILD_DIR)/$(APP_NAME).map $(TGT_LDFLAGS) -T$(APP_LINKER_SCRIPT) $(LDLIBS) -lm # -DBOOTLOADER=0
+
+# BL_LDFLAGS += -Wl,-Map=$(BUILD_DIR)/$(BL_NAME).map $(TGT_LDFLAGS) -T$(BL_LINKER_SCRIPT) $(LDLIBS) -DBOOTLOADER=1
+
+
+all: update_bin tags
+
+update_bin: version app
+ $(eval APP_ELF = $(notdir $(shell ls -t $(BUILD_DIR)/$(APP_NAME).elf)))
+ @(cp $(BUILD_DIR)/$(APP_ELF) $(BUILD_DIR)/fw.elf)
+
+app: $(BUILD_DIR)/$(APP_NAME).elf $(BUILD_DIR)/$(APP_NAME).bin $(BUILD_DIR)/$(APP_NAME).hex
+ $(Q)$(TOOLCHAIN)size $(BUILD_DIR)/$(APP_NAME).elf
+
+OPENOCD_INTERFACE = /usr/share/openocd/scripts/interface/ftdi/ft232h.cfg
+OPENOCD_TARGET = /usr/share/openocd/scripts/target/lpc17xx.cfg
+
+flash-app: update_bin
+ $(Q)openocd -d0 -f $(OPENOCD_INTERFACE) -f $(OPENOCD_TARGET) -c "program $(BUILD_DIR)/"$(APP_ELF)" reset exit"
+
+fw-debug: update_bin
+ $(Q)openocd -d0 -f $(OPENOCD_INTERFACE) -f $(OPENOCD_TARGET) &
+ $(Q)sleep 1
+ $(Q)if pidof openocd 2>/dev/null; then \
+ $(DB) $(BUILD_DIR)/$(APP_ELF); \
+ pgrep -f openocd | xargs kill; \
+ else \
+ exit 1; \
+ fi
+
+# Force to re-build version file
+$(BUILD_DIR)/firmware_info.o: .FORCE
+
+.PHONY: .FORCE
+
+.FORCE:
+
+$(BUILD_DIR)/%.o: %.c | $(BUILD_DIR)
+ @printf " CC $(<F)\n"
+ $(Q)$(CC) -c $(TGT_CFLAGS) $(APP_INC) $< -o $@
+
+$(BUILD_DIR)/%.o: %.s | $(BUILD_DIR)
+ @printf " AS $(<F)\n"
+ $(Q)$(AS) -c $(TGT_AFLAGS) $(APP_INC) $< -o $@
+
+$(BUILD_DIR)/$(APP_NAME).elf: $(APP_OBJ)
+ $(Q)$(CC) $(APP_OBJ) $(APP_LDFLAGS) -o $@
+
+# $(BUILD_DIR)/$(BL_NAME).elf: $(BL_OBJ)
+# $(Q)$(CC) $(BL_OBJ) $(BL_LDFLAGS) -o $@
+# $(Q)printf "\n"
+
+$(BUILD_DIR)/%.hex: $(BUILD_DIR)/%.elf
+ $(Q)$(HEX) $< $@
+
+$(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf
+ $(Q)$(BIN) $< $@
+
+$(BUILD_DIR):
+ $(Q)mkdir -p $(BUILD_DIR)
+
+clean:
+ $(Q)rm -rf $(BUILD_DIR)
+
+tags: $(APP_OBJ) #$(BL_OBJ)
+ $(Q)@printf "Generating tags ...\n"
+ $(Q)ctags -R .
diff --git a/README.md b/README.md
@@ -0,0 +1,75 @@
+## Template for programming LPC1768 MCU
+If you don't like Keil (obviously) and also want to go deeper than mbed's abstraction layers, try this to build your LPC1768 project.
+- Sources used:
+ - [libopencm3](https://github.com/libopencm3/libopencm3)
+ - [CMSIS drivers for LPC1768](https://drive.google.com/open?id=1qdtXqvLqQoIKSMrtabgRIH5fCs94qsPv)
+
+### Structure
+
+```
+src
+├── app
+├── globals
+└── shared
+```
+
+The shared directory contains library and driver sources which can be shared between applications.
+The app directory contains code for the main application.
+The global directory can be used for soem definitions that are accessible for all parts of the project (e.g. `version.h`)
+Each subdirectory has a make module that sets up srouces and include paths for that specific part of the project.
+The main Makefile at the root brings in all definitions of the make modules and builds the application to the `build`
+directory.
+
+User can create additional subdirectories for different applications like bootloader and etc. The linker script,
+Makefile should be modified to create the binaries and executable based on the project needs.
+
+### Building
+- Dependencies:
+ - `arm-none-eabi-gcc` compiler
+ - make
+
+```
+git clone https://github.com/mdnrz/lpc-field.git
+cd lpc-field
+make
+```
+The object files and the final `.elf`, `.bin`, `.hex`, and `.map` files will be on the `build` directory. The name
+of the final output files will be based on the latest tag and commit hash and updates automatically with new
+commits.
+
+Also a copy of the latest firmware will be created as `fw.elf` which will be used in `fw-debug` target.
+
+### Flashing
+- Dependencies:
+ - openocd
+ - jlink or ft232h debugger
+
+By default the ft232h board is used as debug interface
+(look
+[here](https://github.com/m3y54m/cjmcu-ft232hq-programmer?utm_source=pocket_shared)
+for more information)
+User can change the debugger on the root Makefile by changing the `OPENOCD_INTERFACE` variable.
+
+```
+make flash-app
+```
+
+### Debugging
+- Dependencies:
+ - arm-none-eabi-gdb (Can be changed by `DB` variable in Makefile)
+ - openocd
+ - [cmsis-svd](https://github.com/cmsis-svd/cmsis-svd) python package (optional)
+
+```
+make fw-debug
+```
+This command flashes the latest firmware on the board, starts an openocd process in the background, runs
+gdb and connects to the remote target and brings up gdb tui interface halted at the `main()`.
+
+The `.gdbinit` file contains configs and commands executed at gdb startup. If you don't want to use svd
+when debugging, comment out these two lines:
+```
+source /home/mehdi/extra/gits/svd-tools/gdb-svd.py
+svd LPC176x5x.svd
+```
+Quiting gdb will also automatically kill the openocd process.
diff --git a/links b/links
@@ -0,0 +1 @@
+Linker scripts: https://home.cs.colorado.edu/~main/cs1300/doc/gnu/ld_3.html
diff --git a/src/app/app.c b/src/app/app.c
@@ -0,0 +1,89 @@
+#include "LPC17xx.h"
+#include "vector.h"
+#include "lpc17xx_clkpwr.h"
+#include "lpc17xx_uart.h"
+#include "lpc17xx_pinsel.h"
+#include "lpc17xx_systick.h"
+
+volatile uint32_t tick;
+uint32_t get_tick(void);
+void delay(uint32_t ms_time);
+
+// Set p[0]:2 as uart tx
+PINSEL_CFG_Type pinsel_config_tx = {
+ .Portnum = PINSEL_PORT_0,
+ .Pinnum = PINSEL_PIN_2,
+ .Funcnum = PINSEL_FUNC_1,
+};
+
+// Set p[0]:3 as uart rx
+PINSEL_CFG_Type pinsel_config_rx = {
+ .Portnum = PINSEL_PORT_0,
+ .Pinnum = PINSEL_PIN_3,
+ .Funcnum = PINSEL_FUNC_1,
+};
+
+// Config uart as 8N1, 115200
+UART_CFG_Type uart_config = {
+ .Baud_rate = 115200,
+ .Parity = UART_PARITY_NONE,
+ .Databits = UART_DATABIT_8,
+ .Stopbits = UART_STOPBIT_1,
+};
+
+char *buffer = "hello, from lpc\r\n";
+
+int main(void)
+{
+ // Clock source initialization
+ SystemInit();
+
+ // Configuring system tick
+ SYSTICK_InternalInit(10); // 10ms interrupts
+ SYSTICK_Cmd(ENABLE);
+ SYSTICK_IntCmd(ENABLE);
+
+ // Enable uart0 clock
+ CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCUART0, ENABLE);
+
+ UART_Init(LPC_UART0, &uart_config);
+
+ // Set alternate functions for tx and rx pins
+ PINSEL_ConfigPin(&pinsel_config_tx);
+ PINSEL_ConfigPin(&pinsel_config_rx);
+
+ // Enable uart tx pin
+ UART_TxCmd(LPC_UART0, ENABLE);
+
+ uint32_t now = get_tick();
+ uint32_t delay_10ms = 200; // 2 sec delay
+
+ while (1) {
+ if ((get_tick() - now) > delay_10ms) {
+ UART_Send(LPC_UART0, (uint8_t *)buffer, 17, BLOCKING);
+ now = get_tick();
+ }
+ }
+ return 0;
+}
+
+uint32_t get_tick(void)
+{
+ return tick;
+}
+
+void delay(uint32_t ms_time)
+{
+ // FIXME: This is not relaiable. Defuse the overflow
+ uint32_t now = get_tick();
+ if (ms_time < 10) ms_time = 10; // Minimum delay time is 10 ms
+ ms_time /= 10;
+ while((get_tick() - now) < ms_time) {
+ __asm__("nop");
+ }
+}
+
+void systick_handler(void)
+{
+ tick++;
+}
diff --git a/src/app/linker.ld b/src/app/linker.ld
@@ -0,0 +1,48 @@
+
+MEMORY
+{
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 512K
+ ram (rwx) : ORIGIN = 0x10000000, LENGTH = 32K
+
+ ram1(rwx) : ORIGIN = 0x2007C000, LENGTH = 16k
+ ram2(rwx) : ORIGIN = 0x20080000, LENGTH = 16k
+}
+
+EXTERN(vector_table)
+ENTRY(reset_handler)
+
+SECTIONS
+{
+ .text :
+ {
+ *(.vectors)
+ *(.text*)
+ . = ALIGN(4);
+ *(.rodata*)
+ . = ALIGN(4);
+ } > rom
+ . = ALIGN(4);
+ _etext = .;
+
+ .data :
+ {
+ _data = .;
+ *(.data*)
+ . = ALIGN(4);
+ _edata = .;
+ } > ram AT > rom
+ _data_lma = LOADADDR(.data);
+
+ .bss :
+ {
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ } > ram AT > rom
+
+ end = .;
+
+}
+
+PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram));
diff --git a/src/app/make-app.mk b/src/app/make-app.mk
@@ -0,0 +1,14 @@
+APP_DIR = $(SRC_DIR)/app
+
+include $(SRC_DIR)/shared/make-shared.mk
+
+# Modules
+APP_SRC_C += $(APP_DIR)/app.c \
+ $(SHARED_SRC_C)
+
+APP_SRC_S += $(SHARED_SRC_S)
+
+APPLICATION_INC += $(SHARED_INC)
+
+APP_LINKER_SCRIPT = $(APP_DIR)/linker.ld
+
diff --git a/src/globals/make-version.mk b/src/globals/make-version.mk
@@ -0,0 +1,21 @@
+GLOBAL_DIR = $(SRC_DIR)/globals
+###############################################################################
+# Versioning
+VERSION = $(shell git describe --always --abbrev=4 --long)
+VERSION_MAJOR = $(shell git describe --always --long | sed "s/^v\([0-9]\+\).*/\1/")
+VERSION_MINOR = $(shell git describe --always --long | sed "s/^v[0-9]\+\.\([0-9]\+\).*/\1/")
+VERSION_PATCH = $(shell git describe --always --long | sed "s/^v[0-9]\+\.[0-9]\+-\([0-9]\+\).*/\1/")
+VERSION_HASH = $(shell git describe --always --abbrev=4 --long | sed "s/^v[0-9]\+\.[0-9]\+-[0-9]\+-\([a-Z0-9]\{5\}\).*/\1/")
+
+VERSION_FILE = $(GLOBAL_DIR)/version.h
+
+version: | $(VERSION_FILE)
+ $(Q)printf "// fw version: $(VERSION)\n \
+ #include <stdint.h>\n \
+ const uint8_t gGIT_VERSION_MAJOR = $(VERSION_MAJOR);\n \
+ const uint8_t gGIT_VERSION_MINOR = $(VERSION_MINOR);\n \
+ const uint8_t gGIT_VERSION_PATCH = $(VERSION_PATCH);\n \
+ #define gGIT_VERSION_HASH \"$(VERSION_HASH)\"\n" > $(VERSION_FILE)
+
+$(VERSION_FILE):
+ $(shell touch $(VERSION_FILE)) \
diff --git a/src/globals/version.h b/src/globals/version.h
@@ -0,0 +1,6 @@
+// fw version: v0.0-1-gc20b
+ #include <stdint.h>
+ const uint8_t gGIT_VERSION_MAJOR = 0;
+ const uint8_t gGIT_VERSION_MINOR = 0;
+ const uint8_t gGIT_VERSION_PATCH = 1;
+ #define gGIT_VERSION_HASH "gc20b"
diff --git a/src/shared/cmsis/Core/CMSIS/Include/arm_common_tables.h b/src/shared/cmsis/Core/CMSIS/Include/arm_common_tables.h
@@ -0,0 +1,35 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010 ARM Limited. All rights reserved.
+*
+* $Date: 11. November 2010
+* $Revision: V1.0.2
+*
+* Project: CMSIS DSP Library
+* Title: arm_common_tables.h
+*
+* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Version 1.0.2 2010/11/11
+* Documentation updated.
+*
+* Version 1.0.1 2010/10/05
+* Production release and review comments incorporated.
+*
+* Version 1.0.0 2010/09/20
+* Production release and review comments incorporated.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern uint16_t armBitRevTable[256];
+extern q15_t armRecipTableQ15[64];
+extern q31_t armRecipTableQ31[64];
+extern const q31_t realCoefAQ31[1024];
+extern const q31_t realCoefBQ31[1024];
+
+#endif /* ARM_COMMON_TABLES_H */
diff --git a/src/shared/cmsis/Core/CMSIS/Include/arm_math.h b/src/shared/cmsis/Core/CMSIS/Include/arm_math.h
@@ -0,0 +1,7064 @@
+/* ----------------------------------------------------------------------
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ *
+ * $Date: 15. July 2011
+ * $Revision: V1.0.10
+ *
+ * Project: CMSIS DSP Library
+ * Title: arm_math.h
+ *
+ * Description: Public header file for CMSIS DSP Library
+ *
+ * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+ *
+ * Version 1.0.10 2011/7/15
+ * Big Endian support added and Merged M0 and M3/M4 Source code.
+ *
+ * Version 1.0.3 2010/11/29
+ * Re-organized the CMSIS folders and updated documentation.
+ *
+ * Version 1.0.2 2010/11/11
+ * Documentation updated.
+ *
+ * Version 1.0.1 2010/10/05
+ * Production release and review comments incorporated.
+ *
+ * Version 1.0.0 2010/09/20
+ * Production release and review comments incorporated.
+ * -------------------------------------------------------------------- */
+
+/**
+ \mainpage CMSIS DSP Software Library
+ *
+ * <b>Introduction</b>
+ *
+ * This user manual describes the CMSIS DSP software library,
+ * a suite of common signal processing functions for use on Cortex-M processor based devices.
+ *
+ * The library is divided into a number of modules each covering a specific category:
+ * - Basic math functions
+ * - Fast math functions
+ * - Complex math functions
+ * - Filters
+ * - Matrix functions
+ * - Transforms
+ * - Motor control functions
+ * - Statistical functions
+ * - Support functions
+ * - Interpolation functions
+ *
+ * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+ * 32-bit integer and 32-bit floating-point values.
+ *
+ * <b>Processor Support</b>
+ *
+ * The library is completely written in C and is fully CMSIS compliant.
+ * High performance is achieved through maximum use of Cortex-M4 intrinsics.
+ *
+ * The supplied library source code also builds and runs on the Cortex-M3 and Cortex-M0 processor,
+ * with the DSP intrinsics being emulated through software.
+ *
+ *
+ * <b>Toolchain Support</b>
+ *
+ * The library has been developed and tested with MDK-ARM version 4.21.
+ * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+ *
+ * <b>Using the Library</b>
+ *
+ * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
+ * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
+ * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
+ * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
+ * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
+ * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
+ * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
+ * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)
+ * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)
+ *
+ * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
+ * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+ * public header file <code> arm_math.h</code> for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+ * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or
+ * ARM_MATH_CM0 depending on the target processor in the application.
+ *
+ * <b>Examples</b>
+ *
+ * The library ships with a number of examples which demonstrate how to use the library functions.
+ *
+ * <b>Building the Library</b>
+ *
+ * The library installer contains project files to re build libraries on MDK Tool chain in the <code>CMSIS\DSP_Lib\Source\ARM</code> folder.
+ * - arm_cortexM0b_math.uvproj
+ * - arm_cortexM0l_math.uvproj
+ * - arm_cortexM3b_math.uvproj
+ * - arm_cortexM3l_math.uvproj
+ * - arm_cortexM4b_math.uvproj
+ * - arm_cortexM4l_math.uvproj
+ * - arm_cortexM4bf_math.uvproj
+ * - arm_cortexM4lf_math.uvproj
+ *
+ * Each library project have differant pre-processor macros.
+ *
+ * <b>ARM_MATH_CMx:</b>
+ * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+ * and ARM_MATH_CM0 for building library on cortex-M0 target.
+ *
+ * <b>ARM_MATH_BIG_ENDIAN:</b>
+ * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+ *
+ * <b>ARM_MATH_MATRIX_CHECK:</b>
+ * Define macro for checking on the input and output sizes of matrices
+ *
+ * <b>ARM_MATH_ROUNDING:</b>
+ * Define macro for rounding on support functions
+ *
+ * <b>__FPU_PRESENT:</b>
+ * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
+ *
+ *
+ * The project can be built by opening the appropriate project in MDK-ARM 4.21 chain and defining the optional pre processor MACROs detailed above.
+ *
+ * <b>Copyright Notice</b>
+ *
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ */
+
+
+/**
+ * @ingroup DSP_Functions
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @ingroup DSP_Functions
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @ingroup DSP_Functions
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+
+/**
+ * @ingroup DSP_Functions
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @ingroup DSP_Functions
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures. For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * <pre>
+ * typedef struct
+ * {
+ * uint16_t numRows; // number of rows of the matrix.
+ * uint16_t numCols; // number of columns of the matrix.
+ * float32_t *pData; // points to the data of the matrix.
+ * } arm_matrix_instance_f32;
+ * </pre>
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data. The array is of size <code>numRows X numCols</code>
+ * and the values are arranged in row order. That is, the
+ * matrix element (i, j) is stored at:
+ * <pre>
+ * pData[i*numCols + j]
+ * </pre>
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types, respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure. For example:
+ * <pre>
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
+ * </pre>
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
+ * specifies the number of columns, and <code>pData</code> points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices. For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns. If the size check fails the functions return:
+ * <pre>
+ * ARM_MATH_SIZE_MISMATCH
+ * </pre>
+ * Otherwise the functions return
+ * <pre>
+ * ARM_MATH_SUCCESS
+ * </pre>
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the #define
+ * <pre>
+ * ARM_MATH_MATRIX_CHECK
+ * </pre>
+ * within the library project settings. By default this macro is defined
+ * and size checking is enabled. By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster. With size checking disabled the functions always
+ * return <code>ARM_MATH_SUCCESS</code>.
+ */
+
+/**
+ * @ingroup DSP_Functions
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @ingroup DSP_Functions
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @ingroup DSP_Functions
+ * @defgroup groupStats Statistics Functions
+ */
+
+/**
+ * @ingroup DSP_Functions
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @ingroup DSP_Functions
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @ingroup DSP_Lib
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+#define __CMSIS_GENERIC /* disable NVIC and Systick functions */
+
+#if defined (ARM_MATH_CM4)
+ #include "core_cm4.h"
+#elif defined (ARM_MATH_CM3)
+ #include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+ #include "core_cm0.h"
+#else
+#include "ARMCM4.h"
+#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....."
+#endif
+
+#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */
+#include "string.h"
+ #include "math.h"
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+ /**
+ * @brief Macros required for reciprocal calculation in Normalized LMS
+ */
+
+#define DELTA_Q31 (0x100)
+#define DELTA_Q15 0x5
+#define INDEX_MASK 0x0000003F
+#define PI 3.14159265358979f
+
+ /**
+ * @brief Macros required for SINE and COSINE Fast math approximations
+ */
+
+#define TABLE_SIZE 256
+#define TABLE_SPACING_Q31 0x800000
+#define TABLE_SPACING_Q15 0x80
+
+ /**
+ * @brief Macros required for SINE and COSINE Controller functions
+ */
+ /* 1.31(q31) Fixed value of 2/360 */
+ /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING 0xB60B61
+
+
+ /**
+ * @brief Error status returned by some functions in the library.
+ */
+
+ typedef enum
+ {
+ ARM_MATH_SUCCESS = 0, /**< No error */
+ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
+ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
+ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */
+ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
+ ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */
+ } arm_status;
+
+ /**
+ * @brief 8-bit fractional data type in 1.7 format.
+ */
+ typedef int8_t q7_t;
+
+ /**
+ * @brief 16-bit fractional data type in 1.15 format.
+ */
+ typedef int16_t q15_t;
+
+ /**
+ * @brief 32-bit fractional data type in 1.31 format.
+ */
+ typedef int32_t q31_t;
+
+ /**
+ * @brief 64-bit fractional data type in 1.63 format.
+ */
+ typedef int64_t q63_t;
+
+ /**
+ * @brief 32-bit floating-point type definition.
+ */
+ typedef float float32_t;
+
+ /**
+ * @brief 64-bit floating-point type definition.
+ */
+ typedef double float64_t;
+
+ /**
+ * @brief definition to read/write two 16 bit values.
+ */
+#define __SIMD32(addr) (*(int32_t **) & (addr))
+
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0)
+ /**
+ * @brief definition to pack two 16 bit values.
+ */
+#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \
+ (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )
+
+#endif
+
+
+ /**
+ * @brief definition to pack four 8 bit values.
+ */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
+
+#endif
+
+
+ /**
+ * @brief Clips Q63 to Q31 values.
+ */
+ static __INLINE q31_t clip_q63_to_q31(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+ }
+
+ /**
+ * @brief Clips Q63 to Q15 values.
+ */
+ static __INLINE q15_t clip_q63_to_q15(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+ }
+
+ /**
+ * @brief Clips Q31 to Q7 values.
+ */
+ static __INLINE q7_t clip_q31_to_q7(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+ ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+ }
+
+ /**
+ * @brief Clips Q31 to Q15 values.
+ */
+ static __INLINE q15_t clip_q31_to_q15(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+ }
+
+ /**
+ * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+ */
+
+ static __INLINE q63_t mult32x64(
+ q63_t x,
+ q31_t y)
+ {
+ return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+ (((q63_t) (x >> 32) * y)));
+ }
+
+
+#if defined (ARM_MATH_CM0) && defined ( __CC_ARM )
+#define __CLZ __clz
+#endif
+
+#if defined (ARM_MATH_CM0) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) )
+
+ static __INLINE uint32_t __CLZ(q31_t data);
+
+
+ static __INLINE uint32_t __CLZ(q31_t data)
+ {
+ uint32_t count = 0;
+ uint32_t mask = 0x80000000;
+
+ while((data & mask) == 0)
+ {
+ count += 1u;
+ mask = mask >> 1u;
+ }
+
+ return(count);
+
+ }
+
+#endif
+
+ /**
+ * @brief Function to Calculates 1/in(reciprocal) value of Q31 Data type.
+ */
+
+ static __INLINE uint32_t arm_recip_q31(
+ q31_t in,
+ q31_t * dst,
+ q31_t * pRecipTable)
+ {
+
+ uint32_t out, tempVal;
+ uint32_t index, i;
+ uint32_t signBits;
+
+ if(in > 0)
+ {
+ signBits = __CLZ(in) - 1;
+ }
+ else
+ {
+ signBits = __CLZ(-in) - 1;
+ }
+
+ /* Convert input sample to 1.31 format */
+ in = in << signBits;
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t) (in >> 24u);
+ index = (index & INDEX_MASK);
+
+ /* 1.31 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0u; i < 2u; i++)
+ {
+ tempVal = (q31_t) (((q63_t) in * out) >> 31u);
+ tempVal = 0x7FFFFFFF - tempVal;
+ /* 1.31 with exp 1 */
+ //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
+ out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1u);
+
+ }
+
+ /**
+ * @brief Function to Calculates 1/in(reciprocal) value of Q15 Data type.
+ */
+ static __INLINE uint32_t arm_recip_q15(
+ q15_t in,
+ q15_t * dst,
+ q15_t * pRecipTable)
+ {
+
+ uint32_t out = 0, tempVal = 0;
+ uint32_t index = 0, i = 0;
+ uint32_t signBits = 0;
+
+ if(in > 0)
+ {
+ signBits = __CLZ(in) - 17;
+ }
+ else
+ {
+ signBits = __CLZ(-in) - 17;
+ }
+
+ /* Convert input sample to 1.15 format */
+ in = in << signBits;
+
+ /* calculation of index for initial approximated Val */
+ index = in >> 8;
+ index = (index & INDEX_MASK);
+
+ /* 1.15 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0; i < 2; i++)
+ {
+ tempVal = (q15_t) (((q31_t) in * out) >> 15);
+ tempVal = 0x7FFF - tempVal;
+ /* 1.15 with exp 1 */
+ out = (q15_t) (((q31_t) out * tempVal) >> 14);
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1);
+
+ }
+
+
+ /*
+ * @brief C custom defined intrinisic function for only M0 processors
+ */
+#if defined(ARM_MATH_CM0)
+
+ static __INLINE q31_t __SSAT(
+ q31_t x,
+ uint32_t y)
+ {
+ int32_t posMax, negMin;
+ uint32_t i;
+
+ posMax = 1;
+ for (i = 0; i < (y - 1); i++)
+ {
+ posMax = posMax * 2;
+ }
+
+ if(x > 0)
+ {
+ posMax = (posMax - 1);
+
+ if(x > posMax)
+ {
+ x = posMax;
+ }
+ }
+ else
+ {
+ negMin = -posMax;
+
+ if(x < negMin)
+ {
+ x = negMin;
+ }
+ }
+ return (x);
+
+
+ }
+
+#endif /* end of ARM_MATH_CM0 */
+
+
+
+ /*
+ * @brief C custom defined intrinsic function for M3 and M0 processors
+ */
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0)
+
+ /*
+ * @brief C custom defined QADD8 for M3 and M0 processors
+ */
+ static __INLINE q31_t __QADD8(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q7_t r, s, t, u;
+
+ r = (char) x;
+ s = (char) y;
+
+ r = __SSAT((q31_t) (r + s), 8);
+ s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
+ t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
+ u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
+
+ sum = (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
+ (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
+
+ return sum;
+
+ }
+
+ /*
+ * @brief C custom defined QSUB8 for M3 and M0 processors
+ */
+ static __INLINE q31_t __QSUB8(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s, t, u;
+
+ r = (char) x;
+ s = (char) y;
+
+ r = __SSAT((r - s), 8);
+ s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
+ t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
+ u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
+
+ sum =
+ (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & 0x000000FF);
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined QADD16 for M3 and M0 processors
+ */
+
+ /*
+ * @brief C custom defined QADD16 for M3 and M0 processors
+ */
+ static __INLINE q31_t __QADD16(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = __SSAT(r + s, 16);
+ s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+
+ }
+
+ /*
+ * @brief C custom defined SHADD16 for M3 and M0 processors
+ */
+ static __INLINE q31_t __SHADD16(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = ((r >> 1) + (s >> 1));
+ s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+
+ }
+
+ /*
+ * @brief C custom defined QSUB16 for M3 and M0 processors
+ */
+ static __INLINE q31_t __QSUB16(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = __SSAT(r - s, 16);
+ s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined SHSUB16 for M3 and M0 processors
+ */
+ static __INLINE q31_t __SHSUB16(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t diff;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = ((r >> 1) - (s >> 1));
+ s = (((x >> 17) - (y >> 17)) << 16);
+
+ diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return diff;
+ }
+
+ /*
+ * @brief C custom defined QASX for M3 and M0 processors
+ */
+ static __INLINE q31_t __QASX(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum = 0;
+
+ sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) +
+ clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16)));
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined SHASX for M3 and M0 processors
+ */
+ static __INLINE q31_t __SHASX(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = ((r >> 1) - (y >> 17));
+ s = (((x >> 17) + (s >> 1)) << 16);
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+ }
+
+
+ /*
+ * @brief C custom defined QSAX for M3 and M0 processors
+ */
+ static __INLINE q31_t __QSAX(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum = 0;
+
+ sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) +
+ clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16)));
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined SHSAX for M3 and M0 processors
+ */
+ static __INLINE q31_t __SHSAX(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = ((r >> 1) + (y >> 17));
+ s = (((x >> 17) - (s >> 1)) << 16);
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined SMUSDX for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMUSDX(
+ q31_t x,
+ q31_t y)
+ {
+
+ return ((q31_t)(((short) x * (short) (y >> 16)) -
+ ((short) (x >> 16) * (short) y)));
+ }
+
+ /*
+ * @brief C custom defined SMUADX for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMUADX(
+ q31_t x,
+ q31_t y)
+ {
+
+ return ((q31_t)(((short) x * (short) (y >> 16)) +
+ ((short) (x >> 16) * (short) y)));
+ }
+
+ /*
+ * @brief C custom defined QADD for M3 and M0 processors
+ */
+ static __INLINE q31_t __QADD(
+ q31_t x,
+ q31_t y)
+ {
+ return clip_q63_to_q31((q63_t) x + y);
+ }
+
+ /*
+ * @brief C custom defined QSUB for M3 and M0 processors
+ */
+ static __INLINE q31_t __QSUB(
+ q31_t x,
+ q31_t y)
+ {
+ return clip_q63_to_q31((q63_t) x - y);
+ }
+
+ /*
+ * @brief C custom defined SMLAD for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMLAD(
+ q31_t x,
+ q31_t y,
+ q31_t sum)
+ {
+
+ return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
+ ((short) x * (short) y));
+ }
+
+ /*
+ * @brief C custom defined SMLADX for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMLADX(
+ q31_t x,
+ q31_t y,
+ q31_t sum)
+ {
+
+ return (sum + ((short) (x >> 16) * (short) (y)) +
+ ((short) x * (short) (y >> 16)));
+ }
+
+ /*
+ * @brief C custom defined SMLSDX for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMLSDX(
+ q31_t x,
+ q31_t y,
+ q31_t sum)
+ {
+
+ return (sum - ((short) (x >> 16) * (short) (y)) +
+ ((short) x * (short) (y >> 16)));
+ }
+
+ /*
+ * @brief C custom defined SMLALD for M3 and M0 processors
+ */
+ static __INLINE q63_t __SMLALD(
+ q31_t x,
+ q31_t y,
+ q63_t sum)
+ {
+
+ return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
+ ((short) x * (short) y));
+ }
+
+ /*
+ * @brief C custom defined SMLALDX for M3 and M0 processors
+ */
+ static __INLINE q63_t __SMLALDX(
+ q31_t x,
+ q31_t y,
+ q63_t sum)
+ {
+
+ return (sum + ((short) (x >> 16) * (short) y)) +
+ ((short) x * (short) (y >> 16));
+ }
+
+ /*
+ * @brief C custom defined SMUAD for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMUAD(
+ q31_t x,
+ q31_t y)
+ {
+
+ return (((x >> 16) * (y >> 16)) +
+ (((x << 16) >> 16) * ((y << 16) >> 16)));
+ }
+
+ /*
+ * @brief C custom defined SMUSD for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMUSD(
+ q31_t x,
+ q31_t y)
+ {
+
+ return (-((x >> 16) * (y >> 16)) +
+ (((x << 16) >> 16) * ((y << 16) >> 16)));
+ }
+
+
+
+
+#endif /* (ARM_MATH_CM3) || defined (ARM_MATH_CM0) */
+
+
+ /**
+ * @brief Instance structure for the Q7 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q7;
+
+ /**
+ * @brief Instance structure for the Q15 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q7 FIR filter.
+ * @param[in] *S points to an instance of the Q7 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_q7(
+ const arm_fir_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q7 FIR filter.
+ * @param[in,out] *S points to an instance of the Q7 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed.
+ * @return none
+ */
+ void arm_fir_init_q7(
+ arm_fir_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR filter.
+ * @param[in] *S points to an instance of the Q15 FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q15 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_fast_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q15 FIR filter.
+ * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+ * <code>numTaps</code> is not a supported value.
+ */
+
+ arm_status arm_fir_init_q15(
+ arm_fir_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR filter.
+ * @param[in] *S points to an instance of the Q31 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q31 FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_fast_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 FIR filter.
+ * @param[in,out] *S points to an instance of the Q31 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return none.
+ */
+ void arm_fir_init_q31(
+ arm_fir_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the floating-point FIR filter.
+ * @param[in] *S points to an instance of the floating-point FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_f32(
+ const arm_fir_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point FIR filter.
+ * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return none.
+ */
+ void arm_fir_init_f32(
+ arm_fir_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+
+ } arm_biquad_casd_df1_inst_q15;
+
+
+ /**
+ * @brief Instance structure for the Q31 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+
+ } arm_biquad_casd_df1_inst_q31;
+
+ /**
+ * @brief Instance structure for the floating-point Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+
+
+ } arm_biquad_casd_df1_inst_f32;
+
+
+
+ /**
+ * @brief Processing function for the Q15 Biquad cascade filter.
+ * @param[in] *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q15 Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ * @return none
+ */
+
+ void arm_biquad_cascade_df1_init_q15(
+ arm_biquad_casd_df1_inst_q15 * S,
+ uint8_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int8_t postShift);
+
+
+ /**
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_fast_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 Biquad cascade filter
+ * @param[in] *S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_fast_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ * @return none
+ */
+
+ void arm_biquad_cascade_df1_init_q31(
+ arm_biquad_casd_df1_inst_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int8_t postShift);
+
+ /**
+ * @brief Processing function for the floating-point Biquad cascade filter.
+ * @param[in] *S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_f32(
+ const arm_biquad_casd_df1_inst_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @return none
+ */
+
+ void arm_biquad_cascade_df1_init_f32(
+ arm_biquad_casd_df1_inst_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float32_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q15 matrix structure.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q15_t *pData; /**< points to the data of the matrix. */
+
+ } arm_matrix_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 matrix structure.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q31_t *pData; /**< points to the data of the matrix. */
+
+ } arm_matrix_instance_q31;
+
+
+
+ /**
+ * @brief Floating-point matrix addition.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_add_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix addition.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_add_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix addition.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_add_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix transpose.
+ * @param[in] *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_trans_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix transpose.
+ * @param[in] *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_trans_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix transpose.
+ * @param[in] *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_trans_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix multiplication
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix multiplication
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+ /**
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @param[in] *pState points to the array for storing intermediate results
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_fast_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+ /**
+ * @brief Q31 matrix multiplication
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_fast_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix subtraction
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_sub_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix subtraction
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_sub_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix subtraction
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_sub_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Floating-point matrix scaling.
+ * @param[in] *pSrc points to the input matrix
+ * @param[in] scale scale factor
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_scale_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ float32_t scale,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix scaling.
+ * @param[in] *pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to output matrix
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_scale_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ q15_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix scaling.
+ * @param[in] *pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_scale_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ q31_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Q31 matrix initialization.
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] *pData points to the matrix data array.
+ * @return none
+ */
+
+ void arm_mat_init_q31(
+ arm_matrix_instance_q31 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q31_t *pData);
+
+ /**
+ * @brief Q15 matrix initialization.
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] *pData points to the matrix data array.
+ * @return none
+ */
+
+ void arm_mat_init_q15(
+ arm_matrix_instance_q15 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q15_t *pData);
+
+ /**
+ * @brief Floating-point matrix initialization.
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] *pData points to the matrix data array.
+ * @return none
+ */
+
+ void arm_mat_init_f32(
+ arm_matrix_instance_f32 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ float32_t *pData);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 PID Control.
+ */
+ typedef struct
+ {
+ q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ #ifdef ARM_MATH_CM0
+ q15_t A1;
+ q15_t A2;
+ #else
+ q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+ #endif
+ q15_t state[3]; /**< The state array of length 3. */
+ q15_t Kp; /**< The proportional gain. */
+ q15_t Ki; /**< The integral gain. */
+ q15_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 PID Control.
+ */
+ typedef struct
+ {
+ q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ q31_t A2; /**< The derived gain, A2 = Kd . */
+ q31_t state[3]; /**< The state array of length 3. */
+ q31_t Kp; /**< The proportional gain. */
+ q31_t Ki; /**< The integral gain. */
+ q31_t Kd; /**< The derivative gain. */
+
+ } arm_pid_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point PID Control.
+ */
+ typedef struct
+ {
+ float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ float32_t A2; /**< The derived gain, A2 = Kd . */
+ float32_t state[3]; /**< The state array of length 3. */
+ float32_t Kp; /**< The proportional gain. */
+ float32_t Ki; /**< The integral gain. */
+ float32_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_f32;
+
+
+
+ /**
+ * @brief Initialization function for the floating-point PID Control.
+ * @param[in,out] *S points to an instance of the PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ */
+ void arm_pid_init_f32(
+ arm_pid_instance_f32 * S,
+ int32_t resetStateFlag);
+
+ /**
+ * @brief Reset function for the floating-point PID Control.
+ * @param[in,out] *S is an instance of the floating-point PID Control structure
+ * @return none
+ */
+ void arm_pid_reset_f32(
+ arm_pid_instance_f32 * S);
+
+
+ /**
+ * @brief Initialization function for the Q31 PID Control.
+ * @param[in,out] *S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ */
+ void arm_pid_init_q31(
+ arm_pid_instance_q31 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the Q31 PID Control.
+ * @param[in,out] *S points to an instance of the Q31 PID Control structure
+ * @return none
+ */
+
+ void arm_pid_reset_q31(
+ arm_pid_instance_q31 * S);
+
+ /**
+ * @brief Initialization function for the Q15 PID Control.
+ * @param[in,out] *S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ */
+ void arm_pid_init_q15(
+ arm_pid_instance_q15 * S,
+ int32_t resetStateFlag);
+
+ /**
+ * @brief Reset function for the Q15 PID Control.
+ * @param[in,out] *S points to an instance of the q15 PID Control structure
+ * @return none
+ */
+ void arm_pid_reset_q15(
+ arm_pid_instance_q15 * S);
+
+
+ /**
+ * @brief Instance structure for the floating-point Linear Interpolate function.
+ */
+ typedef struct
+ {
+ uint32_t nValues;
+ float32_t x1;
+ float32_t xSpacing;
+ float32_t *pYData; /**< pointer to the table of Y values */
+ } arm_linear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point bilinear interpolation function.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ float32_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 bilinear interpolation function.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q31_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q15_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q7_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q7;
+
+
+ /**
+ * @brief Q7 vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_mult_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q15 vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_mult_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q31 vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_mult_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Floating-point vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_mult_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix4_instance_f32;
+
+ /**
+ * @brief Processing function for the Q15 CFFT/CIFFT.
+ * @param[in] *S points to an instance of the Q15 CFFT/CIFFT structure.
+ * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+ * @return none.
+ */
+
+ void arm_cfft_radix4_q15(
+ const arm_cfft_radix4_instance_q15 * S,
+ q15_t * pSrc);
+
+ /**
+ * @brief Initialization function for the Q15 CFFT/CIFFT.
+ * @param[in,out] *S points to an instance of the Q15 CFFT/CIFFT structure.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
+ */
+
+ arm_status arm_cfft_radix4_init_q15(
+ arm_cfft_radix4_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Processing function for the Q31 CFFT/CIFFT.
+ * @param[in] *S points to an instance of the Q31 CFFT/CIFFT structure.
+ * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+ * @return none.
+ */
+
+ void arm_cfft_radix4_q31(
+ const arm_cfft_radix4_instance_q31 * S,
+ q31_t * pSrc);
+
+ /**
+ * @brief Initialization function for the Q31 CFFT/CIFFT.
+ * @param[in,out] *S points to an instance of the Q31 CFFT/CIFFT structure.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
+ */
+
+ arm_status arm_cfft_radix4_init_q31(
+ arm_cfft_radix4_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Processing function for the floating-point CFFT/CIFFT.
+ * @param[in] *S points to an instance of the floating-point CFFT/CIFFT structure.
+ * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+ * @return none.
+ */
+
+ void arm_cfft_radix4_f32(
+ const arm_cfft_radix4_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Initialization function for the floating-point CFFT/CIFFT.
+ * @param[in,out] *S points to an instance of the floating-point CFFT/CIFFT structure.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
+ */
+
+ arm_status arm_cfft_radix4_init_f32(
+ arm_cfft_radix4_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+
+
+ /*----------------------------------------------------------------------
+ * Internal functions prototypes FFT function
+ ----------------------------------------------------------------------*/
+
+ /**
+ * @brief Core function for the floating-point CFFT butterfly process.
+ * @param[in, out] *pSrc points to the in-place buffer of floating-point data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef points to the twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+ void arm_radix4_butterfly_f32(
+ float32_t * pSrc,
+ uint16_t fftLen,
+ float32_t * pCoef,
+ uint16_t twidCoefModifier);
+
+ /**
+ * @brief Core function for the floating-point CIFFT butterfly process.
+ * @param[in, out] *pSrc points to the in-place buffer of floating-point data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef points to twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @param[in] onebyfftLen value of 1/fftLen.
+ * @return none.
+ */
+
+ void arm_radix4_butterfly_inverse_f32(
+ float32_t * pSrc,
+ uint16_t fftLen,
+ float32_t * pCoef,
+ uint16_t twidCoefModifier,
+ float32_t onebyfftLen);
+
+ /**
+ * @brief In-place bit reversal function.
+ * @param[in, out] *pSrc points to the in-place buffer of floating-point data type.
+ * @param[in] fftSize length of the FFT.
+ * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table.
+ * @param[in] *pBitRevTab points to the bit reversal table.
+ * @return none.
+ */
+
+ void arm_bitreversal_f32(
+ float32_t *pSrc,
+ uint16_t fftSize,
+ uint16_t bitRevFactor,
+ uint16_t *pBitRevTab);
+
+ /**
+ * @brief Core function for the Q31 CFFT butterfly process.
+ * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef points to twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+ void arm_radix4_butterfly_q31(
+ q31_t *pSrc,
+ uint32_t fftLen,
+ q31_t *pCoef,
+ uint32_t twidCoefModifier);
+
+ /**
+ * @brief Core function for the Q31 CIFFT butterfly process.
+ * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef points to twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+ void arm_radix4_butterfly_inverse_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ q31_t * pCoef,
+ uint32_t twidCoefModifier);
+
+ /**
+ * @brief In-place bit reversal function.
+ * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table
+ * @param[in] *pBitRevTab points to bit reversal table.
+ * @return none.
+ */
+
+ void arm_bitreversal_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ uint16_t bitRevFactor,
+ uint16_t *pBitRevTab);
+
+ /**
+ * @brief Core function for the Q15 CFFT butterfly process.
+ * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef16 points to twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+ void arm_radix4_butterfly_q15(
+ q15_t *pSrc16,
+ uint32_t fftLen,
+ q15_t *pCoef16,
+ uint32_t twidCoefModifier);
+
+ /**
+ * @brief Core function for the Q15 CIFFT butterfly process.
+ * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef16 points to twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+ void arm_radix4_butterfly_inverse_q15(
+ q15_t *pSrc16,
+ uint32_t fftLen,
+ q15_t *pCoef16,
+ uint32_t twidCoefModifier);
+
+ /**
+ * @brief In-place bit reversal function.
+ * @param[in, out] *pSrc points to the in-place buffer of Q15 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table
+ * @param[in] *pBitRevTab points to bit reversal table.
+ * @return none.
+ */
+
+ void arm_bitreversal_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ uint16_t bitRevFactor,
+ uint16_t *pBitRevTab);
+
+ /**
+ * @brief Instance structure for the Q15 RFFT/RIFFT function.
+ */
+
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint32_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 RFFT/RIFFT function.
+ */
+
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint32_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint16_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_f32;
+
+ /**
+ * @brief Processing function for the Q15 RFFT/RIFFT.
+ * @param[in] *S points to an instance of the Q15 RFFT/RIFFT structure.
+ * @param[in] *pSrc points to the input buffer.
+ * @param[out] *pDst points to the output buffer.
+ * @return none.
+ */
+
+ void arm_rfft_q15(
+ const arm_rfft_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst);
+
+ /**
+ * @brief Initialization function for the Q15 RFFT/RIFFT.
+ * @param[in, out] *S points to an instance of the Q15 RFFT/RIFFT structure.
+ * @param[in] *S_CFFT points to an instance of the Q15 CFFT/CIFFT structure.
+ * @param[in] fftLenReal length of the FFT.
+ * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.
+ */
+
+ arm_status arm_rfft_init_q15(
+ arm_rfft_instance_q15 * S,
+ arm_cfft_radix4_instance_q15 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ /**
+ * @brief Processing function for the Q31 RFFT/RIFFT.
+ * @param[in] *S points to an instance of the Q31 RFFT/RIFFT structure.
+ * @param[in] *pSrc points to the input buffer.
+ * @param[out] *pDst points to the output buffer.
+ * @return none.
+ */
+
+ void arm_rfft_q31(
+ const arm_rfft_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst);
+
+ /**
+ * @brief Initialization function for the Q31 RFFT/RIFFT.
+ * @param[in, out] *S points to an instance of the Q31 RFFT/RIFFT structure.
+ * @param[in, out] *S_CFFT points to an instance of the Q31 CFFT/CIFFT structure.
+ * @param[in] fftLenReal length of the FFT.
+ * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.
+ */
+
+ arm_status arm_rfft_init_q31(
+ arm_rfft_instance_q31 * S,
+ arm_cfft_radix4_instance_q31 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ /**
+ * @brief Initialization function for the floating-point RFFT/RIFFT.
+ * @param[in,out] *S points to an instance of the floating-point RFFT/RIFFT structure.
+ * @param[in,out] *S_CFFT points to an instance of the floating-point CFFT/CIFFT structure.
+ * @param[in] fftLenReal length of the FFT.
+ * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
+ * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.
+ */
+
+ arm_status arm_rfft_init_f32(
+ arm_rfft_instance_f32 * S,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ /**
+ * @brief Processing function for the floating-point RFFT/RIFFT.
+ * @param[in] *S points to an instance of the floating-point RFFT/RIFFT structure.
+ * @param[in] *pSrc points to the input buffer.
+ * @param[out] *pDst points to the output buffer.
+ * @return none.
+ */
+
+ void arm_rfft_f32(
+ const arm_rfft_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+ */
+
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ float32_t normalize; /**< normalizing factor. */
+ float32_t *pTwiddle; /**< points to the twiddle factor table. */
+ float32_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_f32;
+
+ /**
+ * @brief Initialization function for the floating-point DCT4/IDCT4.
+ * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure.
+ * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
+ * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+ */
+
+ arm_status arm_dct4_init_f32(
+ arm_dct4_instance_f32 * S,
+ arm_rfft_instance_f32 * S_RFFT,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ float32_t normalize);
+
+ /**
+ * @brief Processing function for the floating-point DCT4/IDCT4.
+ * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure.
+ * @param[in] *pState points to state buffer.
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ */
+
+ void arm_dct4_f32(
+ const arm_dct4_instance_f32 * S,
+ float32_t * pState,
+ float32_t * pInlineBuffer);
+
+ /**
+ * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+ */
+
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q31_t normalize; /**< normalizing factor. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ q31_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q31;
+
+ /**
+ * @brief Initialization function for the Q31 DCT4/IDCT4.
+ * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure.
+ * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure
+ * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+ */
+
+ arm_status arm_dct4_init_q31(
+ arm_dct4_instance_q31 * S,
+ arm_rfft_instance_q31 * S_RFFT,
+ arm_cfft_radix4_instance_q31 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q31_t normalize);
+
+ /**
+ * @brief Processing function for the Q31 DCT4/IDCT4.
+ * @param[in] *S points to an instance of the Q31 DCT4 structure.
+ * @param[in] *pState points to state buffer.
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ */
+
+ void arm_dct4_q31(
+ const arm_dct4_instance_q31 * S,
+ q31_t * pState,
+ q31_t * pInlineBuffer);
+
+ /**
+ * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+ */
+
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q15_t normalize; /**< normalizing factor. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ q15_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q15;
+
+ /**
+ * @brief Initialization function for the Q15 DCT4/IDCT4.
+ * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure.
+ * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
+ * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+ */
+
+ arm_status arm_dct4_init_q15(
+ arm_dct4_instance_q15 * S,
+ arm_rfft_instance_q15 * S_RFFT,
+ arm_cfft_radix4_instance_q15 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q15_t normalize);
+
+ /**
+ * @brief Processing function for the Q15 DCT4/IDCT4.
+ * @param[in] *S points to an instance of the Q15 DCT4 structure.
+ * @param[in] *pState points to state buffer.
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ */
+
+ void arm_dct4_q15(
+ const arm_dct4_instance_q15 * S,
+ q15_t * pState,
+ q15_t * pInlineBuffer);
+
+ /**
+ * @brief Floating-point vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_add_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q7 vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_add_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q15 vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_add_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q31 vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_add_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Floating-point vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_sub_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q7 vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_sub_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q15 vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_sub_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q31 vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_sub_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Multiplies a floating-point vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scale scale factor to be applied
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_scale_f32(
+ float32_t * pSrc,
+ float32_t scale,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Multiplies a Q7 vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_scale_q7(
+ q7_t * pSrc,
+ q7_t scaleFract,
+ int8_t shift,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Multiplies a Q15 vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_scale_q15(
+ q15_t * pSrc,
+ q15_t scaleFract,
+ int8_t shift,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Multiplies a Q31 vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_scale_q31(
+ q31_t * pSrc,
+ q31_t scaleFract,
+ int8_t shift,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q7 vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_abs_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Floating-point vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_abs_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q15 vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_abs_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q31 vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_abs_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Dot product of floating-point vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+ void arm_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t blockSize,
+ float32_t * result);
+
+ /**
+ * @brief Dot product of Q7 vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+ void arm_dot_prod_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ uint32_t blockSize,
+ q31_t * result);
+
+ /**
+ * @brief Dot product of Q15 vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+ void arm_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+ /**
+ * @brief Dot product of Q31 vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+ void arm_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+ /**
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_shift_q7(
+ q7_t * pSrc,
+ int8_t shiftBits,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_shift_q15(
+ q15_t * pSrc,
+ int8_t shiftBits,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_shift_q31(
+ q31_t * pSrc,
+ int8_t shiftBits,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Adds a constant offset to a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_offset_f32(
+ float32_t * pSrc,
+ float32_t offset,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Adds a constant offset to a Q7 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_offset_q7(
+ q7_t * pSrc,
+ q7_t offset,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Adds a constant offset to a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_offset_q15(
+ q15_t * pSrc,
+ q15_t offset,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Adds a constant offset to a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_offset_q31(
+ q31_t * pSrc,
+ q31_t offset,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Negates the elements of a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_negate_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Negates the elements of a Q7 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_negate_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Negates the elements of a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_negate_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Negates the elements of a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_negate_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+ /**
+ * @brief Copies the elements of a floating-point vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_copy_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Copies the elements of a Q7 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_copy_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Copies the elements of a Q15 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_copy_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Copies the elements of a Q31 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_copy_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+ /**
+ * @brief Fills a constant value into a floating-point vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_fill_f32(
+ float32_t value,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fills a constant value into a Q7 vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_fill_q7(
+ q7_t value,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fills a constant value into a Q15 vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_fill_q15(
+ q15_t value,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fills a constant value into a Q31 vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_fill_q31(
+ q31_t value,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+ /**
+ * @brief Convolution of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+ /**
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+ /**
+ * @brief Partial convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+ /**
+ * @brief Partial convolution of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+ /**
+ * @brief Partial convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR decimator.
+ */
+
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR decimator.
+ */
+
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+ } arm_fir_decimate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR decimator.
+ */
+
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+ } arm_fir_decimate_instance_f32;
+
+
+
+ /**
+ * @brief Processing function for the floating-point FIR decimator.
+ * @param[in] *S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_f32(
+ const arm_fir_decimate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR decimator.
+ * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+
+ arm_status arm_fir_decimate_init_f32(
+ arm_fir_decimate_instance_f32 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator.
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_fast_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR decimator.
+ * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+
+ arm_status arm_fir_decimate_init_q15(
+ arm_fir_decimate_instance_q15 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator.
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_q31(
+ const arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_fast_q31(
+ arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR decimator.
+ * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+
+ arm_status arm_fir_decimate_init_q31(
+ arm_fir_decimate_instance_q31 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR interpolator.
+ */
+
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR interpolator.
+ */
+
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR interpolator.
+ */
+
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+ } arm_fir_interpolate_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q15 FIR interpolator.
+ * @param[in] *S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_interpolate_q15(
+ const arm_fir_interpolate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR interpolator.
+ * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+
+ arm_status arm_fir_interpolate_init_q15(
+ arm_fir_interpolate_instance_q15 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR interpolator.
+ * @param[in] *S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_interpolate_q31(
+ const arm_fir_interpolate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 FIR interpolator.
+ * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+
+ arm_status arm_fir_interpolate_init_q31(
+ arm_fir_interpolate_instance_q31 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR interpolator.
+ * @param[in] *S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_interpolate_f32(
+ const arm_fir_interpolate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point FIR interpolator.
+ * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+
+ arm_status arm_fir_interpolate_init_f32(
+ arm_fir_interpolate_instance_f32 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+ */
+
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */
+
+ } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+ /**
+ * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cas_df1_32x64_q31(
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format
+ * @return none
+ */
+
+ void arm_biquad_cas_df1_32x64_init_q31(
+ arm_biquad_cas_df1_32x64_ins_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q63_t * pState,
+ uint8_t postShift);
+
+
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f32;
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] *S points to an instance of the filter data structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df2T_f32(
+ const arm_biquad_cascade_df2T_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @return none
+ */
+
+ void arm_biquad_cascade_df2T_init_f32(
+ arm_biquad_cascade_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR lattice filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR lattice filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR lattice filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_f32;
+
+ /**
+ * @brief Initialization function for the Q15 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] *pState points to the state buffer. The array is of length numStages.
+ * @return none.
+ */
+
+ void arm_fir_lattice_init_q15(
+ arm_fir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_lattice_q15(
+ const arm_fir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] *pState points to the state buffer. The array is of length numStages.
+ * @return none.
+ */
+
+ void arm_fir_lattice_init_q31(
+ arm_fir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_fir_lattice_q31(
+ const arm_fir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] *pState points to the state buffer. The array is of length numStages.
+ * @return none.
+ */
+
+ void arm_fir_lattice_init_f32(
+ arm_fir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+ /**
+ * @brief Processing function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_fir_lattice_f32(
+ const arm_fir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the Q15 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_f32;
+
+ /**
+ * @brief Processing function for the floating-point IIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_f32(
+ const arm_iir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point IIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_init_f32(
+ arm_iir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t *pkCoeffs,
+ float32_t *pvCoeffs,
+ float32_t *pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_q31(
+ const arm_iir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_init_q31(
+ arm_iir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t *pkCoeffs,
+ q31_t *pvCoeffs,
+ q31_t *pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_q15(
+ const arm_iir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages.
+ * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] *pState points to state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ */
+
+ void arm_iir_lattice_init_q15(
+ arm_iir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t *pkCoeffs,
+ q15_t *pvCoeffs,
+ q15_t *pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the floating-point LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that controls filter coefficient updates. */
+ } arm_lms_instance_f32;
+
+ /**
+ * @brief Processing function for floating-point LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_f32(
+ const arm_lms_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for floating-point LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to the coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_init_f32(
+ arm_lms_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the Q15 LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+ } arm_lms_instance_q15;
+
+
+ /**
+ * @brief Initialization function for the Q15 LMS filter.
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to the coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+ void arm_lms_init_q15(
+ arm_lms_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+ /**
+ * @brief Processing function for Q15 LMS filter.
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_q15(
+ const arm_lms_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+
+ } arm_lms_instance_q31;
+
+ /**
+ * @brief Processing function for Q31 LMS filter.
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_q31(
+ const arm_lms_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for Q31 LMS filter.
+ * @param[in] *S points to an instance of the Q31 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+ void arm_lms_init_q31(
+ arm_lms_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t *pCoeffs,
+ q31_t *pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+ /**
+ * @brief Instance structure for the floating-point normalized LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that control filter coefficient updates. */
+ float32_t energy; /**< saves previous frame energy. */
+ float32_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_f32;
+
+ /**
+ * @brief Processing function for floating-point normalized LMS filter.
+ * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_norm_f32(
+ arm_lms_norm_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for floating-point normalized LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_norm_init_f32(
+ arm_lms_norm_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q31_t *recipTable; /**< points to the reciprocal initial value table. */
+ q31_t energy; /**< saves previous frame energy. */
+ q31_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q31;
+
+ /**
+ * @brief Processing function for Q31 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_norm_q31(
+ arm_lms_norm_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for Q31 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+ void arm_lms_norm_init_q31(
+ arm_lms_norm_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+ /**
+ * @brief Instance structure for the Q15 normalized LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< Number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q15_t *recipTable; /**< Points to the reciprocal initial value table. */
+ q15_t energy; /**< saves previous frame energy. */
+ q15_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q15;
+
+ /**
+ * @brief Processing function for Q15 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_norm_q15(
+ arm_lms_norm_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q15 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+ void arm_lms_norm_init_q15(
+ arm_lms_norm_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+ /**
+ * @brief Correlation of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+ /**
+ * @brief Correlation of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+ /**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+ /**
+ * @brief Correlation of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+ /**
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 sparse FIR filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 sparse FIR filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q7 sparse FIR filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q7;
+
+ /**
+ * @brief Processing function for the floating-point sparse FIR filter.
+ * @param[in] *S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_sparse_f32(
+ arm_fir_sparse_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ float32_t * pScratchIn,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point sparse FIR filter.
+ * @param[in,out] *S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ */
+
+ void arm_fir_sparse_init_f32(
+ arm_fir_sparse_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 sparse FIR filter.
+ * @param[in] *S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_sparse_q31(
+ arm_fir_sparse_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ q31_t * pScratchIn,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 sparse FIR filter.
+ * @param[in,out] *S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ */
+
+ void arm_fir_sparse_init_q31(
+ arm_fir_sparse_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q15 sparse FIR filter.
+ * @param[in] *S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] *pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_sparse_q15(
+ arm_fir_sparse_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ q15_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 sparse FIR filter.
+ * @param[in,out] *S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ */
+
+ void arm_fir_sparse_init_q15(
+ arm_fir_sparse_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q7 sparse FIR filter.
+ * @param[in] *S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] *pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_sparse_q7(
+ arm_fir_sparse_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ q7_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q7 sparse FIR filter.
+ * @param[in,out] *S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ */
+
+ void arm_fir_sparse_init_q7(
+ arm_fir_sparse_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ int32_t *pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /*
+ * @brief Floating-point sin_cos function.
+ * @param[in] theta input value in degrees
+ * @param[out] *pSinVal points to the processed sine output.
+ * @param[out] *pCosVal points to the processed cos output.
+ * @return none.
+ */
+
+ void arm_sin_cos_f32(
+ float32_t theta,
+ float32_t *pSinVal,
+ float32_t *pCcosVal);
+
+ /*
+ * @brief Q31 sin_cos function.
+ * @param[in] theta scaled input value in degrees
+ * @param[out] *pSinVal points to the processed sine output.
+ * @param[out] *pCosVal points to the processed cosine output.
+ * @return none.
+ */
+
+ void arm_sin_cos_q31(
+ q31_t theta,
+ q31_t *pSinVal,
+ q31_t *pCosVal);
+
+
+ /**
+ * @brief Floating-point complex conjugate.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_conj_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex conjugate.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_conj_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q15 complex conjugate.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_conj_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+
+ /**
+ * @brief Floating-point complex magnitude squared
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_squared_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex magnitude squared
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_squared_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q15 complex magnitude squared
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_squared_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup PID PID Motor Control
+ *
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control
+ * loop mechanism widely used in industrial control systems.
+ * A PID controller is the most commonly used type of feedback controller.
+ *
+ * This set of functions implements (PID) controllers
+ * for Q15, Q31, and floating-point data types. The functions operate on a single sample
+ * of data and each call to the function returns a single processed value.
+ * <code>S</code> points to an instance of the PID control data structure. <code>in</code>
+ * is the input sample value. The functions return the output value.
+ *
+ * \par Algorithm:
+ * <pre>
+ * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+ * A0 = Kp + Ki + Kd
+ * A1 = (-Kp ) - (2 * Kd )
+ * A2 = Kd </pre>
+ *
+ * \par
+ * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+ *
+ * \par
+ * \image html PID.gif "Proportional Integral Derivative Controller"
+ *
+ * \par
+ * The PID controller calculates an "error" value as the difference between
+ * the measured output and the reference input.
+ * The controller attempts to minimize the error by adjusting the process control inputs.
+ * The proportional value determines the reaction to the current error,
+ * the integral value determines the reaction based on the sum of recent errors,
+ * and the derivative value determines the reaction based on the rate at which the error has been changing.
+ *
+ * \par Instance Structure
+ * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+ * A separate instance structure must be defined for each PID Controller.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Reset Functions
+ * There is also an associated reset function for each data type which clears the state array.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+ * - Zeros out the values in the state buffer.
+ *
+ * \par
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the PID Controller functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point PID Control.
+ * @param[in,out] *S is an instance of the floating-point PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ */
+
+
+ static __INLINE float32_t arm_pid_f32(
+ arm_pid_instance_f32 * S,
+ float32_t in)
+ {
+ float32_t out;
+
+ /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */
+ out = (S->A0 * in) +
+ (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ * @brief Process function for the Q31 PID Control.
+ * @param[in,out] *S points to an instance of the Q31 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+ */
+
+ static __INLINE q31_t arm_pid_q31(
+ arm_pid_instance_q31 * S,
+ q31_t in)
+ {
+ q63_t acc;
+ q31_t out;
+
+ /* acc = A0 * x[n] */
+ acc = (q63_t) S->A0 * in;
+
+ /* acc += A1 * x[n-1] */
+ acc += (q63_t) S->A1 * S->state[0];
+
+ /* acc += A2 * x[n-2] */
+ acc += (q63_t) S->A2 * S->state[1];
+
+ /* convert output to 1.31 format to add y[n-1] */
+ out = (q31_t) (acc >> 31u);
+
+ /* out += y[n-1] */
+ out += S->state[2];
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ * @brief Process function for the Q15 PID Control.
+ * @param[in,out] *S points to an instance of the Q15 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ */
+
+ static __INLINE q15_t arm_pid_q15(
+ arm_pid_instance_q15 * S,
+ q15_t in)
+ {
+ q63_t acc;
+ q15_t out;
+
+ /* Implementation of PID controller */
+
+ #ifdef ARM_MATH_CM0
+
+ /* acc = A0 * x[n] */
+ acc = ((q31_t) S->A0 )* in ;
+
+ #else
+
+ /* acc = A0 * x[n] */
+ acc = (q31_t) __SMUAD(S->A0, in);
+
+ #endif
+
+ #ifdef ARM_MATH_CM0
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ acc += (q31_t) S->A1 * S->state[0] ;
+ acc += (q31_t) S->A2 * S->state[1] ;
+
+ #else
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ acc = __SMLALD(S->A1, (q31_t)__SIMD32(S->state), acc);
+
+ #endif
+
+ /* acc += y[n-1] */
+ acc += (q31_t) S->state[2] << 15;
+
+ /* saturate the output */
+ out = (q15_t) (__SSAT((acc >> 15), 16));
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ * @} end of PID group
+ */
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] *src points to the instance of the input floating-point matrix structure.
+ * @param[out] *dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+
+ arm_status arm_mat_inverse_f32(
+ const arm_matrix_instance_f32 * src,
+ arm_matrix_instance_f32 * dst);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+
+ /**
+ * @defgroup clarke Vector Clarke Transform
+ * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+ * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
+ * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
+ * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
+ * \image html clarke.gif Stator current space vector and its components in (a,b).
+ * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
+ * can be calculated using only <code>Ia</code> and <code>Ib</code>.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeFormula.gif
+ * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
+ * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup clarke
+ * @{
+ */
+
+ /**
+ *
+ * @brief Floating-point Clarke transform
+ * @param[in] Ia input three-phase coordinate <code>a</code>
+ * @param[in] Ib input three-phase coordinate <code>b</code>
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
+ * @return none.
+ */
+
+ static __INLINE void arm_clarke_f32(
+ float32_t Ia,
+ float32_t Ib,
+ float32_t * pIalpha,
+ float32_t * pIbeta)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+ *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+
+ }
+
+ /**
+ * @brief Clarke transform for Q31 version
+ * @param[in] Ia input three-phase coordinate <code>a</code>
+ * @param[in] Ib input three-phase coordinate <code>b</code>
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+
+ static __INLINE void arm_clarke_q31(
+ q31_t Ia,
+ q31_t Ib,
+ q31_t * pIalpha,
+ q31_t * pIbeta)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+ /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+ /* pIbeta is calculated by adding the intermediate products */
+ *pIbeta = __QADD(product1, product2);
+ }
+
+ /**
+ * @} end of clarke group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q31 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_q7_to_q31(
+ q7_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_clarke Vector Inverse Clarke Transform
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeInvFormula.gif
+ * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
+ * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_clarke
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Clarke transform
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] *pIa points to output three-phase coordinate <code>a</code>
+ * @param[out] *pIb points to output three-phase coordinate <code>b</code>
+ * @return none.
+ */
+
+
+ static __INLINE void arm_inv_clarke_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pIa,
+ float32_t * pIb)
+ {
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+ *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
+
+ }
+
+ /**
+ * @brief Inverse Clarke transform for Q31 version
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] *pIa points to output three-phase coordinate <code>a</code>
+ * @param[out] *pIb points to output three-phase coordinate <code>b</code>
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the subtraction, hence there is no risk of overflow.
+ */
+
+ static __INLINE void arm_inv_clarke_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pIa,
+ q31_t * pIb)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+ /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+ /* pIb is calculated by subtracting the products */
+ *pIb = __QSUB(product2, product1);
+
+ }
+
+ /**
+ * @} end of inv_clarke group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q15 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_q7_to_q15(
+ q7_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup park Vector Park Transform
+ *
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+ * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
+ * from the stationary to the moving reference frame and control the spatial relationship between
+ * the stator vector current and rotor flux vector.
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+ * current vector and the relationship from the two reference frames:
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkFormula.gif
+ * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
+ * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Park transform
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] *pId points to output rotor reference frame d
+ * @param[out] *pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none.
+ *
+ * The function implements the forward Park transform.
+ *
+ */
+
+ static __INLINE void arm_park_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pId,
+ float32_t * pIq,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+ *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+ /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+ *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+
+ }
+
+ /**
+ * @brief Park transform for Q31 version
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] *pId points to output rotor reference frame d
+ * @param[out] *pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+ */
+
+
+ static __INLINE void arm_park_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pId,
+ q31_t * pIq,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Ialpha * cosVal) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * sinVal) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Ialpha * sinVal) */
+ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * cosVal) */
+ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+ /* Calculate pId by adding the two intermediate products 1 and 2 */
+ *pId = __QADD(product1, product2);
+
+ /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+ *pIq = __QSUB(product4, product3);
+ }
+
+ /**
+ * @} end of park group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q7_to_float(
+ q7_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_park Vector Inverse Park transform
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkInvFormula.gif
+ * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
+ * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Park transform
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none.
+ */
+
+ static __INLINE void arm_inv_park_f32(
+ float32_t Id,
+ float32_t Iq,
+ float32_t * pIalpha,
+ float32_t * pIbeta,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+ *pIalpha = Id * cosVal - Iq * sinVal;
+
+ /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+ *pIbeta = Id * sinVal + Iq * cosVal;
+
+ }
+
+
+ /**
+ * @brief Inverse Park transform for Q31 version
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+
+
+ static __INLINE void arm_inv_park_q31(
+ q31_t Id,
+ q31_t Iq,
+ q31_t * pIalpha,
+ q31_t * pIbeta,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Id * cosVal) */
+ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * sinVal) */
+ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Id * sinVal) */
+ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * cosVal) */
+ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+ /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+ *pIalpha = __QSUB(product1, product2);
+
+ /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+ *pIbeta = __QADD(product4, product3);
+
+ }
+
+ /**
+ * @} end of Inverse park group
+ */
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q31_to_float(
+ q31_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup LinearInterpolate Linear Interpolation
+ *
+ * Linear interpolation is a method of curve fitting using linear polynomials.
+ * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+ *
+ * \par
+ * \image html LinearInterp.gif "Linear interpolation"
+ *
+ * \par
+ * A Linear Interpolate function calculates an output value(y), for the input(x)
+ * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+ *
+ * \par Algorithm:
+ * <pre>
+ * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+ * where x0, x1 are nearest values of input x
+ * y0, y1 are nearest values to output y
+ * </pre>
+ *
+ * \par
+ * This set of functions implements Linear interpolation process
+ * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single
+ * sample of data and each call to the function returns a single processed value.
+ * <code>S</code> points to an instance of the Linear Interpolate function data structure.
+ * <code>x</code> is the input sample value. The functions returns the output value.
+ *
+ * \par
+ * if x is outside of the table boundary, Linear interpolation returns first value of the table
+ * if x is below input range and returns last value of table if x is above range.
+ */
+
+ /**
+ * @addtogroup LinearInterpolate
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point Linear Interpolation Function.
+ * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
+ * @param[in] x input sample to process
+ * @return y processed output sample.
+ *
+ */
+
+ static __INLINE float32_t arm_linear_interp_f32(
+ arm_linear_interp_instance_f32 * S,
+ float32_t x)
+ {
+
+ float32_t y;
+ float32_t x0, x1; /* Nearest input values */
+ float32_t y0, y1; /* Nearest output values */
+ float32_t xSpacing = S->xSpacing; /* spacing between input values */
+ int32_t i; /* Index variable */
+ float32_t *pYData = S->pYData; /* pointer to output table */
+
+ /* Calculation of index */
+ i = (x - S->x1) / xSpacing;
+
+ if(i < 0)
+ {
+ /* Iniatilize output for below specified range as least output value of table */
+ y = pYData[0];
+ }
+ else if(i >= S->nValues)
+ {
+ /* Iniatilize output for above specified range as last output value of table */
+ y = pYData[S->nValues-1];
+ }
+ else
+ {
+ /* Calculation of nearest input values */
+ x0 = S->x1 + i * xSpacing;
+ x1 = S->x1 + (i +1) * xSpacing;
+
+ /* Read of nearest output values */
+ y0 = pYData[i];
+ y1 = pYData[i + 1];
+
+ /* Calculation of output */
+ y = y0 + (x - x0) * ((y1 - y0)/(x1-x0));
+
+ }
+
+ /* returns output value */
+ return (y);
+ }
+
+ /**
+ *
+ * @brief Process function for the Q31 Linear Interpolation Function.
+ * @param[in] *pYData pointer to Q31 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+
+
+ static __INLINE q31_t arm_linear_interp_q31(q31_t *pYData,
+ q31_t x, uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q31_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & 0xFFF00000) >> 20);
+
+ if(index >= (nValues - 1))
+ {
+ return(pYData[nValues - 1]);
+ }
+ else if(index < 0)
+ {
+ return(pYData[0]);
+ }
+ else
+ {
+
+ /* 20 bits for the fractional part */
+ /* shift left by 11 to keep fract in 1.31 format */
+ fract = (x & 0x000FFFFF) << 11;
+
+ /* Read two nearest output values from the index in 1.31(q31) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1u];
+
+ /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+ /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+ y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+ /* Convert y to 1.31 format */
+ return (y << 1u);
+
+ }
+
+ }
+
+ /**
+ *
+ * @brief Process function for the Q15 Linear Interpolation Function.
+ * @param[in] *pYData pointer to Q15 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+
+
+ static __INLINE q15_t arm_linear_interp_q15(q15_t *pYData, q31_t x, uint32_t nValues)
+ {
+ q63_t y; /* output */
+ q15_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & 0xFFF00000) >> 20u);
+
+ if(index >= (nValues - 1))
+ {
+ return(pYData[nValues - 1]);
+ }
+ else if(index < 0)
+ {
+ return(pYData[0]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y0 = pYData[index];
+ y1 = pYData[index + 1u];
+
+ /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+ y = ((q63_t) y0 * (0xFFFFF - fract));
+
+ /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+ y += ((q63_t) y1 * (fract));
+
+ /* convert y to 1.15 format */
+ return (y >> 20);
+ }
+
+
+ }
+
+ /**
+ *
+ * @brief Process function for the Q7 Linear Interpolation Function.
+ * @param[in] *pYData pointer to Q7 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ */
+
+
+ static __INLINE q7_t arm_linear_interp_q7(q7_t *pYData, q31_t x, uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q7_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & 0xFFF00000) >> 20u);
+
+
+ if(index >= (nValues - 1))
+ {
+ return(pYData[nValues - 1]);
+ }
+ else if(index < 0)
+ {
+ return(pYData[0]);
+ }
+ else
+ {
+
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index and are in 1.7(q7) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1u];
+
+ /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+ y = ((y0 * (0xFFFFF - fract)));
+
+ /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+ y += (y1 * fract);
+
+ /* convert y to 1.7(q7) format */
+ return (y >> 20u);
+
+ }
+
+ }
+ /**
+ * @} end of LinearInterpolate group
+ */
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return sin(x).
+ */
+
+ float32_t arm_sin_f32(
+ float32_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+
+ q31_t arm_sin_q31(
+ q31_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+
+ q15_t arm_sin_q15(
+ q15_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return cos(x).
+ */
+
+ float32_t arm_cos_f32(
+ float32_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+
+ q31_t arm_cos_q31(
+ q31_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+
+ q15_t arm_cos_q15(
+ q15_t x);
+
+
+ /**
+ * @ingroup groupFastMath
+ */
+
+
+ /**
+ * @defgroup SQRT Square Root
+ *
+ * Computes the square root of a number.
+ * There are separate functions for Q15, Q31, and floating-point data types.
+ * The square root function is computed using the Newton-Raphson algorithm.
+ * This is an iterative algorithm of the form:
+ * <pre>
+ * x1 = x0 - f(x0)/f'(x0)
+ * </pre>
+ * where <code>x1</code> is the current estimate,
+ * <code>x0</code> is the previous estimate and
+ * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
+ * For the square root function, the algorithm reduces to:
+ * <pre>
+ * x0 = in/2 [initial guess]
+ * x1 = 1/2 * ( x0 + in / x0) [each iteration]
+ * </pre>
+ */
+
+
+ /**
+ * @addtogroup SQRT
+ * @{
+ */
+
+ /**
+ * @brief Floating-point square root function.
+ * @param[in] in input value.
+ * @param[out] *pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * <code>in</code> is negative value and returns zero output for negative values.
+ */
+
+ static __INLINE arm_status arm_sqrt_f32(
+ float32_t in, float32_t *pOut)
+ {
+ if(in > 0)
+ {
+
+// #if __FPU_USED
+ #if (__FPU_USED == 1) && defined ( __CC_ARM )
+ *pOut = __sqrtf(in);
+ #else
+ *pOut = sqrtf(in);
+ #endif
+
+ return (ARM_MATH_SUCCESS);
+ }
+ else
+ {
+ *pOut = 0.0f;
+ return (ARM_MATH_ARGUMENT_ERROR);
+ }
+
+ }
+
+
+ /**
+ * @brief Q31 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+ * @param[out] *pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * <code>in</code> is negative value and returns zero output for negative values.
+ */
+ arm_status arm_sqrt_q31(
+ q31_t in, q31_t *pOut);
+
+ /**
+ * @brief Q15 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+ * @param[out] *pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * <code>in</code> is negative value and returns zero output for negative values.
+ */
+ arm_status arm_sqrt_q15(
+ q15_t in, q15_t *pOut);
+
+ /**
+ * @} end of SQRT group
+ */
+
+
+
+
+
+
+ /**
+ * @brief floating-point Circular write function.
+ */
+
+ static __INLINE void arm_circularWrite_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const int32_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = wOffset;
+ }
+
+
+
+ /**
+ * @brief floating-point Circular Read function.
+ */
+ static __INLINE void arm_circularRead_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ int32_t * dst,
+ int32_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (int32_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+ /**
+ * @brief Q15 Circular write function.
+ */
+
+ static __INLINE void arm_circularWrite_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q15_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = wOffset;
+ }
+
+
+
+ /**
+ * @brief Q15 Circular Read function.
+ */
+ static __INLINE void arm_circularRead_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q15_t * dst,
+ q15_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (q15_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Q7 Circular write function.
+ */
+
+ static __INLINE void arm_circularWrite_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q7_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = wOffset;
+ }
+
+
+
+ /**
+ * @brief Q7 Circular Read function.
+ */
+ static __INLINE void arm_circularRead_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q7_t * dst,
+ q7_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (q7_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_power_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+ /**
+ * @brief Sum of the squares of the elements of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_power_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Sum of the squares of the elements of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_power_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+ /**
+ * @brief Sum of the squares of the elements of a Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_power_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Mean value of a Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_mean_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult);
+
+ /**
+ * @brief Mean value of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+ void arm_mean_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+ /**
+ * @brief Mean value of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+ void arm_mean_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Mean value of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+ void arm_mean_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Variance of the elements of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_var_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Variance of the elements of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_var_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+ /**
+ * @brief Variance of the elements of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_var_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Root Mean Square of the elements of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_rms_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Root Mean Square of the elements of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_rms_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Root Mean Square of the elements of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_rms_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+ /**
+ * @brief Standard deviation of the elements of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_std_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Standard deviation of the elements of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_std_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Standard deviation of the elements of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_std_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+ /**
+ * @brief Floating-point complex magnitude
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex magnitude
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q15 complex magnitude
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q15 complex dot product
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] *realResult real part of the result returned here
+ * @param[out] *imagResult imaginary part of the result returned here
+ * @return none.
+ */
+
+ void arm_cmplx_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t numSamples,
+ q31_t * realResult,
+ q31_t * imagResult);
+
+ /**
+ * @brief Q31 complex dot product
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] *realResult real part of the result returned here
+ * @param[out] *imagResult imaginary part of the result returned here
+ * @return none.
+ */
+
+ void arm_cmplx_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t numSamples,
+ q63_t * realResult,
+ q63_t * imagResult);
+
+ /**
+ * @brief Floating-point complex dot product
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] *realResult real part of the result returned here
+ * @param[out] *imagResult imaginary part of the result returned here
+ * @return none.
+ */
+
+ void arm_cmplx_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t numSamples,
+ float32_t * realResult,
+ float32_t * imagResult);
+
+ /**
+ * @brief Q15 complex-by-real multiplication
+ * @param[in] *pSrcCmplx points to the complex input vector
+ * @param[in] *pSrcReal points to the real input vector
+ * @param[out] *pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_real_q15(
+ q15_t * pSrcCmplx,
+ q15_t * pSrcReal,
+ q15_t * pCmplxDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex-by-real multiplication
+ * @param[in] *pSrcCmplx points to the complex input vector
+ * @param[in] *pSrcReal points to the real input vector
+ * @param[out] *pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_real_q31(
+ q31_t * pSrcCmplx,
+ q31_t * pSrcReal,
+ q31_t * pCmplxDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Floating-point complex-by-real multiplication
+ * @param[in] *pSrcCmplx points to the complex input vector
+ * @param[in] *pSrcReal points to the real input vector
+ * @param[out] *pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_real_f32(
+ float32_t * pSrcCmplx,
+ float32_t * pSrcReal,
+ float32_t * pCmplxDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Minimum value of a Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *result is output pointer
+ * @param[in] index is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+
+ void arm_min_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * result,
+ uint32_t * index);
+
+ /**
+ * @brief Minimum value of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output pointer
+ * @param[in] *pIndex is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+
+ void arm_min_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ * @brief Minimum value of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output pointer
+ * @param[out] *pIndex is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+ void arm_min_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ * @brief Minimum value of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output pointer
+ * @param[out] *pIndex is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+
+ void arm_min_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in] *pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+ void arm_max_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in] *pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+ void arm_max_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in] *pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+ void arm_max_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in] *pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+ void arm_max_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ * @brief Q15 complex-by-complex multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_cmplx_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex-by-complex multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_cmplx_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Floating-point complex-by-complex multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_cmplx_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q31 vector.
+ * @param[in] *pSrc points to the floating-point input vector
+ * @param[out] *pDst points to the Q31 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ */
+ void arm_float_to_q31(
+ float32_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q15 vector.
+ * @param[in] *pSrc points to the floating-point input vector
+ * @param[out] *pDst points to the Q15 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none
+ */
+ void arm_float_to_q15(
+ float32_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q7 vector.
+ * @param[in] *pSrc points to the floating-point input vector
+ * @param[out] *pDst points to the Q7 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none
+ */
+ void arm_float_to_q7(
+ float32_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q31_to_q15(
+ q31_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q31_to_q7(
+ q31_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Converts the elements of the Q15 vector to floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q15_to_float(
+ q15_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q15_to_q31(
+ q15_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q15_to_q7(
+ q15_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup BilinearInterpolate Bilinear Interpolation
+ *
+ * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+ * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
+ * determines values between the grid points.
+ * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+ * Bilinear interpolation is often used in image processing to rescale images.
+ * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+ *
+ * <b>Algorithm</b>
+ * \par
+ * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+ * For floating-point, the instance structure is defined as:
+ * <pre>
+ * typedef struct
+ * {
+ * uint16_t numRows;
+ * uint16_t numCols;
+ * float32_t *pData;
+ * } arm_bilinear_interp_instance_f32;
+ * </pre>
+ *
+ * \par
+ * where <code>numRows</code> specifies the number of rows in the table;
+ * <code>numCols</code> specifies the number of columns in the table;
+ * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
+ * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
+ * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
+ *
+ * \par
+ * Let <code>(x, y)</code> specify the desired interpolation point. Then define:
+ * <pre>
+ * XF = floor(x)
+ * YF = floor(y)
+ * </pre>
+ * \par
+ * The interpolated output point is computed as:
+ * <pre>
+ * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+ * + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+ * + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+ * + f(XF+1, YF+1) * (x-XF)*(y-YF)
+ * </pre>
+ * Note that the coordinates (x, y) contain integer and fractional components.
+ * The integer components specify which portion of the table to use while the
+ * fractional components control the interpolation processor.
+ *
+ * \par
+ * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+ */
+
+ /**
+ * @addtogroup BilinearInterpolate
+ * @{
+ */
+
+ /**
+ *
+ * @brief Floating-point bilinear interpolation.
+ * @param[in,out] *S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate.
+ * @param[in] Y interpolation coordinate.
+ * @return out interpolated value.
+ */
+
+
+ static __INLINE float32_t arm_bilinear_interp_f32(
+ const arm_bilinear_interp_instance_f32 * S,
+ float32_t X,
+ float32_t Y)
+ {
+ float32_t out;
+ float32_t f00, f01, f10, f11;
+ float32_t *pData = S->pData;
+ int32_t xIndex, yIndex, index;
+ float32_t xdiff, ydiff;
+ float32_t b1, b2, b3, b4;
+
+ xIndex = (int32_t) X;
+ yIndex = (int32_t) Y;
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(xIndex < 0 || xIndex > (S->numRows-1) || yIndex < 0 || yIndex > ( S->numCols-1))
+ {
+ return(0);
+ }
+
+ /* Calculation of index for two nearest points in X-direction */
+ index = (xIndex - 1) + (yIndex-1) * S->numCols ;
+
+
+ /* Read two nearest points in X-direction */
+ f00 = pData[index];
+ f01 = pData[index + 1];
+
+ /* Calculation of index for two nearest points in Y-direction */
+ index = (xIndex-1) + (yIndex) * S->numCols;
+
+
+ /* Read two nearest points in Y-direction */
+ f10 = pData[index];
+ f11 = pData[index + 1];
+
+ /* Calculation of intermediate values */
+ b1 = f00;
+ b2 = f01 - f00;
+ b3 = f10 - f00;
+ b4 = f00 - f01 - f10 + f11;
+
+ /* Calculation of fractional part in X */
+ xdiff = X - xIndex;
+
+ /* Calculation of fractional part in Y */
+ ydiff = Y - yIndex;
+
+ /* Calculation of bi-linear interpolated output */
+ out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ *
+ * @brief Q31 bilinear interpolation.
+ * @param[in,out] *S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+
+ static __INLINE q31_t arm_bilinear_interp_q31(
+ arm_bilinear_interp_instance_q31 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q31_t out; /* Temporary output */
+ q31_t acc = 0; /* output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q31_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q31_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & 0xFFF00000) >> 20u);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & 0xFFF00000) >> 20u);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1))
+ {
+ return(0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* shift left xfract by 11 to keep 1.31 format */
+ xfract = (X & 0x000FFFFF) << 11u;
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + nCols * (cI)];
+ x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+ /* 20 bits for the fractional part */
+ /* shift left yfract by 11 to keep 1.31 format */
+ yfract = (Y & 0x000FFFFF) << 11u;
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + nCols * (cI + 1)];
+ y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+ out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+ acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+ /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+ /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* Convert acc to 1.31(q31) format */
+ return (acc << 2u);
+
+ }
+
+ /**
+ * @brief Q15 bilinear interpolation.
+ * @param[in,out] *S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+
+ static __INLINE q15_t arm_bilinear_interp_q15(
+ arm_bilinear_interp_instance_q15 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q15_t x1, x2, y1, y2; /* Nearest output values */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ int32_t rI, cI; /* Row and column indices */
+ q15_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & 0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & 0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1))
+ {
+ return(0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + nCols * (cI)];
+ x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + nCols * (cI + 1)];
+ y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+ /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+ /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */
+ out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+ acc = ((q63_t) out * (0xFFFFF - yfract));
+
+ /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+ acc += ((q63_t) out * (xfract));
+
+ /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+ acc += ((q63_t) out * (yfract));
+
+ /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+ acc += ((q63_t) out * (yfract));
+
+ /* acc is in 13.51 format and down shift acc by 36 times */
+ /* Convert out to 1.15 format */
+ return (acc >> 36);
+
+ }
+
+ /**
+ * @brief Q7 bilinear interpolation.
+ * @param[in,out] *S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+
+ static __INLINE q7_t arm_bilinear_interp_q7(
+ arm_bilinear_interp_instance_q7 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q7_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q7_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & 0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & 0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1))
+ {
+ return(0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + nCols * (cI)];
+ x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + nCols * (cI + 1)];
+ y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+ out = ((x1 * (0xFFFFF - xfract)));
+ acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+ /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */
+ out = ((x2 * (0xFFFFF - yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y1 * (0xFFFFF - xfract)));
+ acc += (((q63_t) out * (yfract)));
+
+ /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y2 * (yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+ return (acc >> 40);
+
+ }
+
+ /**
+ * @} end of BilinearInterpolate group
+ */
+
+
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* _ARM_MATH_H */
+
+
+/**
+ *
+ * End of file.
+ */
diff --git a/src/shared/cmsis/Core/CMSIS/Include/core_cm3.h b/src/shared/cmsis/Core/CMSIS/Include/core_cm3.h
@@ -0,0 +1,1227 @@
+/**************************************************************************//**
+ * @file core_cm3.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version V2.10
+ * @date 19. July 2011
+ *
+ * @note
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+
+/** \ingroup CMSIS_Core
+ \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions
+ CMSIS violates following MISRA-C2004 Rules:
+
+ - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup CMSIS_Core
+ \defgroup CMSIS_core_definitions CMSIS Core Definitions
+ This file defines all structures and symbols for CMSIS core:
+ - CMSIS version number
+ - Cortex-M core
+ - Cortex-M core Revision Number
+ @{
+ */
+
+/* CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x03) /*!< Cortex core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+
+#endif
+
+/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ /* add preprocessor checks */
+#endif
+
+#include <stdint.h> /*!< standard types definitions */
+#include "core_cmInstr.h" /*!< Core Instruction Access */
+#include "core_cmFunc.h" /*!< Core Function Access */
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM3_REV
+ #define __CM3_REV 0x0200
+ #warning "__CM3_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+#ifdef __cplusplus
+ #define __I volatile /*!< defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< defines 'read only' permissions */
+#endif
+#define __O volatile /*!< defines 'write only' permissions */
+#define __IO volatile /*!< defines 'read / write' permissions */
+
+/*@} end of group CMSIS_core_definitions */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ ******************************************************************************/
+/** \ingroup CMSIS_Core
+ \defgroup CMSIS_core_register CMSIS Core Register
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE CMSIS Core
+ Type definitions for the Cortex-M Core Registers
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC CMSIS NVIC
+ Type definitions for the Cortex-M NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB CMSIS SCB
+ Type definitions for the Cortex-M System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5];
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB
+ Type definitions for the Cortex-M System Control and ID Register not in the SCB
+ @{
+ */
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+#else
+ uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick CMSIS SysTick
+ Type definitions for the Cortex-M System Timer Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM CMSIS ITM
+ Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */
+#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU CMSIS MPU
+ Type definitions for the Cortex-M Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug CMSIS Core Debug
+ Type definitions for the Cortex-M Core Debug Registers
+ @{
+ */
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ ******************************************************************************/
+/** \ingroup CMSIS_Core
+ \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
+ @{
+ */
+
+/** \brief Set Priority Grouping
+
+ This function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field
+ */
+static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/** \brief Get Priority Grouping
+
+ This function gets the priority grouping from NVIC Interrupt Controller.
+ Priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
+
+ \return Priority grouping field
+ */
+static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+}
+
+
+/** \brief Enable External Interrupt
+
+ This function enables a device specific interrupt in the NVIC interrupt controller.
+ The interrupt number cannot be a negative value.
+
+ \param [in] IRQn Number of the external interrupt to enable
+ */
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief Disable External Interrupt
+
+ This function disables a device specific interrupt in the NVIC interrupt controller.
+ The interrupt number cannot be a negative value.
+
+ \param [in] IRQn Number of the external interrupt to disable
+ */
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief Get Pending Interrupt
+
+ This function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Number of the interrupt for get pending
+ \return 0 Interrupt status is not pending
+ \return 1 Interrupt status is pending
+ */
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief Set Pending Interrupt
+
+ This function sets the pending bit for the specified interrupt.
+ The interrupt number cannot be a negative value.
+
+ \param [in] IRQn Number of the interrupt for set pending
+ */
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ This function clears the pending bit for the specified interrupt.
+ The interrupt number cannot be a negative value.
+
+ \param [in] IRQn Number of the interrupt for clear pending
+ */
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Get Active Interrupt
+
+ This function reads the active register in NVIC and returns the active bit.
+ \param [in] IRQn Number of the interrupt for get active
+ \return 0 Interrupt status is not active
+ \return 1 Interrupt status is active
+ */
+static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ This function sets the priority for the specified interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+ Note: The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Number of the interrupt for set priority
+ \param [in] priority Priority to set
+ */
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
+ else {
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+}
+
+
+/** \brief Get Interrupt Priority
+
+ This function reads the priority for the specified interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+ The returned priority value is automatically aligned to the implemented
+ priority bits of the microcontroller.
+
+ \param [in] IRQn Number of the interrupt for get priority
+ \return Interrupt Priority
+ */
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
+ else {
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief Encode Priority
+
+ This function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value and sub priority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+ The returned priority value can be used for NVIC_SetPriority(...) function
+
+ \param [in] PriorityGroup Used priority group
+ \param [in] PreemptPriority Preemptive priority value (starting from 0)
+ \param [in] SubPriority Sub priority value (starting from 0)
+ \return Encoded priority for the interrupt
+ */
+static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ return (
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ );
+}
+
+
+/** \brief Decode Priority
+
+ This function decodes an interrupt priority value with the given priority group to
+ preemptive priority value and sub priority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+ The priority value can be retrieved with NVIC_GetPriority(...) function
+
+ \param [in] Priority Priority value
+ \param [in] PriorityGroup Used priority group
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0)
+ \param [out] pSubPriority Sub priority value (starting from 0)
+ */
+static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+}
+
+
+/** \brief System Reset
+
+ This function initiate a system reset request to reset the MCU.
+ */
+static __INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ This function initialises the system tick timer and its interrupt and start the system tick timer.
+ Counter is in free running mode to generate periodical interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
+
+
+/** \brief ITM Send Character
+
+ This function transmits a character via the ITM channel 0.
+ It just returns when no debugger is connected that has booked the output.
+ It is blocking when a debugger is connected, but the previous character send is not transmitted.
+
+ \param [in] ch Character to transmit
+ \return Character to transmit
+ */
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */
+ (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t) ch;
+ }
+ return (ch);
+}
+
+
+/** \brief ITM Receive Character
+
+ This function inputs a character via external variable ITM_RxBuffer.
+ It just returns when no debugger is connected that has booked the output.
+ It is blocking when a debugger is connected, but the previous character send is not transmitted.
+
+ \return Received character
+ \return -1 No character received
+ */
+static __INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/** \brief ITM Check Character
+
+ This function checks external variable ITM_RxBuffer whether a character is available or not.
+ It returns '1' if a character is available and '0' if no character is available.
+
+ \return 0 No character available
+ \return 1 Character available
+ */
+static __INLINE int32_t ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/src/shared/cmsis/Core/CMSIS/Include/core_cmFunc.h b/src/shared/cmsis/Core/CMSIS/Include/core_cmFunc.h
@@ -0,0 +1,609 @@
+/**************************************************************************//**
+ * @file core_cmFunc.h
+ * @brief CMSIS Cortex-M Core Function Access Header File
+ * @version V2.10
+ * @date 26. July 2011
+ *
+ * @note
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq(); */
+/* intrinsic void __disable_irq(); */
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+static __INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+static __INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/** \brief Get ISPR Register
+
+ This function returns the content of the ISPR Register.
+
+ \return ISPR Register value
+ */
+static __INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+static __INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+static __INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+static __INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+static __INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+static __INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+static __INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+static __INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+static __INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+static __INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+static __INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+static __INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+static __INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+static __INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+static __INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief Enable IRQ Interrupts
+
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i");
+}
+
+
+/** \brief Disable IRQ Interrupts
+
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i");
+}
+
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) );
+}
+
+
+/** \brief Get ISPR Register
+
+ This function returns the content of the ISPR Register.
+
+ \return ISPR Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f");
+}
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f");
+}
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) );
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ uint32_t result;
+
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ return(result);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/src/shared/cmsis/Core/CMSIS/Include/core_cmInstr.h b/src/shared/cmsis/Core/CMSIS/Include/core_cmInstr.h
@@ -0,0 +1,586 @@
+/**************************************************************************//**
+ * @file core_cmInstr.h
+ * @brief CMSIS Cortex-M Core Instruction Access Header File
+ * @version V2.10
+ * @date 19. July 2011
+ *
+ * @note
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \ingroup CMSIS_Core
+ \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+#define __ISB() __isb(0xF)
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __dsb(0xF)
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __dmb(0xF)
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+static __INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+static __INLINE __ASM int32_t __REVSH(int32_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __rbit
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW(value, ptr) __strex(value, ptr)
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX __clrex
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
+{
+ __ASM volatile ("nop");
+}
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
+{
+ __ASM volatile ("wfi");
+}
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
+{
+ __ASM volatile ("wfe");
+}
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
+{
+ __ASM volatile ("sev");
+}
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
+{
+ __ASM volatile ("isb");
+}
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
+{
+ __ASM volatile ("dsb");
+}
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
+{
+ __ASM volatile ("dmb");
+}
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint8_t result;
+
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint16_t result;
+
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex");
+}
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
+{
+ uint8_t result;
+
+ __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/src/shared/cmsis/Core/Device/NXP/LPC17xx/Include/LPC17xx.h b/src/shared/cmsis/Core/Device/NXP/LPC17xx/Include/LPC17xx.h
@@ -0,0 +1,1078 @@
+/**************************************************************************//**
+ * @file LPC17xx.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
+ * NXP LPC17xx Device Series
+ * @version: V1.09
+ * @date: 25. July. 2011
+ *
+ * @note
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __LPC17xx_H__
+#define __LPC17xx_H__
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+
+/** @addtogroup LPC17xx_System
+ * @{
+ */
+
+/** @brief IRQ interrupt source definition */
+typedef enum IRQn
+{
+/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
+
+/****** LPC17xx Specific Interrupt Numbers *******************************************************/
+ WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
+ TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
+ TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
+ TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
+ TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
+ UART0_IRQn = 5, /*!< UART0 Interrupt */
+ UART1_IRQn = 6, /*!< UART1 Interrupt */
+ UART2_IRQn = 7, /*!< UART2 Interrupt */
+ UART3_IRQn = 8, /*!< UART3 Interrupt */
+ PWM1_IRQn = 9, /*!< PWM1 Interrupt */
+ I2C0_IRQn = 10, /*!< I2C0 Interrupt */
+ I2C1_IRQn = 11, /*!< I2C1 Interrupt */
+ I2C2_IRQn = 12, /*!< I2C2 Interrupt */
+ SPI_IRQn = 13, /*!< SPI Interrupt */
+ SSP0_IRQn = 14, /*!< SSP0 Interrupt */
+ SSP1_IRQn = 15, /*!< SSP1 Interrupt */
+ PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
+ RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
+ EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
+ EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
+ EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
+ EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
+ ADC_IRQn = 22, /*!< A/D Converter Interrupt */
+ BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
+ USB_IRQn = 24, /*!< USB Interrupt */
+ CAN_IRQn = 25, /*!< CAN Interrupt */
+ DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
+ I2S_IRQn = 27, /*!< I2S Interrupt */
+ ENET_IRQn = 28, /*!< Ethernet Interrupt */
+ RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
+ MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
+ QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
+ PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
+ USBActivity_IRQn = 33, /*!< USB Activity Interrupt */
+ CANActivity_IRQn = 34 /*!< CAN Activity Interrupt */
+} IRQn_Type;
+
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the Cortex-M3 Processor and Core Peripherals */
+#define __MPU_PRESENT 1 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+
+#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
+#include "system_LPC17xx.h" /* System Header */
+
+
+/******************************************************************************/
+/* Device Specific Peripheral registers structures */
+/******************************************************************************/
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/*------------- System Control (SC) ------------------------------------------*/
+/** @brief System Control (SC) register structure definition */
+typedef struct
+{
+ __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
+ uint32_t RESERVED0[31];
+ __IO uint32_t PLL0CON; /* Clocking and Power Control */
+ __IO uint32_t PLL0CFG;
+ __I uint32_t PLL0STAT;
+ __O uint32_t PLL0FEED;
+ uint32_t RESERVED1[4];
+ __IO uint32_t PLL1CON;
+ __IO uint32_t PLL1CFG;
+ __I uint32_t PLL1STAT;
+ __O uint32_t PLL1FEED;
+ uint32_t RESERVED2[4];
+ __IO uint32_t PCON;
+ __IO uint32_t PCONP;
+ uint32_t RESERVED3[15];
+ __IO uint32_t CCLKCFG;
+ __IO uint32_t USBCLKCFG;
+ __IO uint32_t CLKSRCSEL;
+ __IO uint32_t CANSLEEPCLR;
+ __IO uint32_t CANWAKEFLAGS;
+ uint32_t RESERVED4[10];
+ __IO uint32_t EXTINT; /* External Interrupts */
+ uint32_t RESERVED5;
+ __IO uint32_t EXTMODE;
+ __IO uint32_t EXTPOLAR;
+ uint32_t RESERVED6[12];
+ __IO uint32_t RSID; /* Reset */
+ uint32_t RESERVED7[7];
+ __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
+ __IO uint32_t IRCTRIM; /* Clock Dividers */
+ __IO uint32_t PCLKSEL0;
+ __IO uint32_t PCLKSEL1;
+ uint32_t RESERVED8[4];
+ __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
+ __IO uint32_t DMAREQSEL;
+ __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
+ } LPC_SC_TypeDef;
+
+/*------------- Pin Connect Block (PINCON) -----------------------------------*/
+/** @brief Pin Connect Block (PINCON) register structure definition */
+typedef struct
+{
+ __IO uint32_t PINSEL0;
+ __IO uint32_t PINSEL1;
+ __IO uint32_t PINSEL2;
+ __IO uint32_t PINSEL3;
+ __IO uint32_t PINSEL4;
+ __IO uint32_t PINSEL5;
+ __IO uint32_t PINSEL6;
+ __IO uint32_t PINSEL7;
+ __IO uint32_t PINSEL8;
+ __IO uint32_t PINSEL9;
+ __IO uint32_t PINSEL10;
+ uint32_t RESERVED0[5];
+ __IO uint32_t PINMODE0;
+ __IO uint32_t PINMODE1;
+ __IO uint32_t PINMODE2;
+ __IO uint32_t PINMODE3;
+ __IO uint32_t PINMODE4;
+ __IO uint32_t PINMODE5;
+ __IO uint32_t PINMODE6;
+ __IO uint32_t PINMODE7;
+ __IO uint32_t PINMODE8;
+ __IO uint32_t PINMODE9;
+ __IO uint32_t PINMODE_OD0;
+ __IO uint32_t PINMODE_OD1;
+ __IO uint32_t PINMODE_OD2;
+ __IO uint32_t PINMODE_OD3;
+ __IO uint32_t PINMODE_OD4;
+ __IO uint32_t I2CPADCFG;
+} LPC_PINCON_TypeDef;
+
+/*------------- General Purpose Input/Output (GPIO) --------------------------*/
+/** @brief General Purpose Input/Output (GPIO) register structure definition */
+typedef struct
+{
+ union {
+ __IO uint32_t FIODIR;
+ struct {
+ __IO uint16_t FIODIRL;
+ __IO uint16_t FIODIRH;
+ };
+ struct {
+ __IO uint8_t FIODIR0;
+ __IO uint8_t FIODIR1;
+ __IO uint8_t FIODIR2;
+ __IO uint8_t FIODIR3;
+ };
+ };
+ uint32_t RESERVED0[3];
+ union {
+ __IO uint32_t FIOMASK;
+ struct {
+ __IO uint16_t FIOMASKL;
+ __IO uint16_t FIOMASKH;
+ };
+ struct {
+ __IO uint8_t FIOMASK0;
+ __IO uint8_t FIOMASK1;
+ __IO uint8_t FIOMASK2;
+ __IO uint8_t FIOMASK3;
+ };
+ };
+ union {
+ __IO uint32_t FIOPIN;
+ struct {
+ __IO uint16_t FIOPINL;
+ __IO uint16_t FIOPINH;
+ };
+ struct {
+ __IO uint8_t FIOPIN0;
+ __IO uint8_t FIOPIN1;
+ __IO uint8_t FIOPIN2;
+ __IO uint8_t FIOPIN3;
+ };
+ };
+ union {
+ __IO uint32_t FIOSET;
+ struct {
+ __IO uint16_t FIOSETL;
+ __IO uint16_t FIOSETH;
+ };
+ struct {
+ __IO uint8_t FIOSET0;
+ __IO uint8_t FIOSET1;
+ __IO uint8_t FIOSET2;
+ __IO uint8_t FIOSET3;
+ };
+ };
+ union {
+ __O uint32_t FIOCLR;
+ struct {
+ __O uint16_t FIOCLRL;
+ __O uint16_t FIOCLRH;
+ };
+ struct {
+ __O uint8_t FIOCLR0;
+ __O uint8_t FIOCLR1;
+ __O uint8_t FIOCLR2;
+ __O uint8_t FIOCLR3;
+ };
+ };
+} LPC_GPIO_TypeDef;
+
+/** @brief General Purpose Input/Output interrupt (GPIOINT) register structure definition */
+typedef struct
+{
+ __I uint32_t IntStatus;
+ __I uint32_t IO0IntStatR;
+ __I uint32_t IO0IntStatF;
+ __O uint32_t IO0IntClr;
+ __IO uint32_t IO0IntEnR;
+ __IO uint32_t IO0IntEnF;
+ uint32_t RESERVED0[3];
+ __I uint32_t IO2IntStatR;
+ __I uint32_t IO2IntStatF;
+ __O uint32_t IO2IntClr;
+ __IO uint32_t IO2IntEnR;
+ __IO uint32_t IO2IntEnF;
+} LPC_GPIOINT_TypeDef;
+
+/*------------- Timer (TIM) --------------------------------------------------*/
+/** @brief Timer (TIM) register structure definition */
+typedef struct
+{
+ __IO uint32_t IR;
+ __IO uint32_t TCR;
+ __IO uint32_t TC;
+ __IO uint32_t PR;
+ __IO uint32_t PC;
+ __IO uint32_t MCR;
+ __IO uint32_t MR0;
+ __IO uint32_t MR1;
+ __IO uint32_t MR2;
+ __IO uint32_t MR3;
+ __IO uint32_t CCR;
+ __I uint32_t CR0;
+ __I uint32_t CR1;
+ uint32_t RESERVED0[2];
+ __IO uint32_t EMR;
+ uint32_t RESERVED1[12];
+ __IO uint32_t CTCR;
+} LPC_TIM_TypeDef;
+
+/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
+/** @brief Pulse-Width Modulation (PWM) register structure definition */
+typedef struct
+{
+ __IO uint32_t IR;
+ __IO uint32_t TCR;
+ __IO uint32_t TC;
+ __IO uint32_t PR;
+ __IO uint32_t PC;
+ __IO uint32_t MCR;
+ __IO uint32_t MR0;
+ __IO uint32_t MR1;
+ __IO uint32_t MR2;
+ __IO uint32_t MR3;
+ __IO uint32_t CCR;
+ __I uint32_t CR0;
+ __I uint32_t CR1;
+ __I uint32_t CR2;
+ __I uint32_t CR3;
+ uint32_t RESERVED0;
+ __IO uint32_t MR4;
+ __IO uint32_t MR5;
+ __IO uint32_t MR6;
+ __IO uint32_t PCR;
+ __IO uint32_t LER;
+ uint32_t RESERVED1[7];
+ __IO uint32_t CTCR;
+} LPC_PWM_TypeDef;
+
+/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
+/** @brief Universal Asynchronous Receiver Transmitter (UART) register structure definition */
+typedef struct
+{
+ union {
+ __I uint8_t RBR;
+ __O uint8_t THR;
+ __IO uint8_t DLL;
+ uint32_t RESERVED0;
+ };
+ union {
+ __IO uint8_t DLM;
+ __IO uint32_t IER;
+ };
+ union {
+ __I uint32_t IIR;
+ __O uint8_t FCR;
+ };
+ __IO uint8_t LCR;
+ uint8_t RESERVED1[7];
+ __I uint8_t LSR;
+ uint8_t RESERVED2[7];
+ __IO uint8_t SCR;
+ uint8_t RESERVED3[3];
+ __IO uint32_t ACR;
+ __IO uint8_t ICR;
+ uint8_t RESERVED4[3];
+ __IO uint8_t FDR;
+ uint8_t RESERVED5[7];
+ __IO uint8_t TER;
+ uint8_t RESERVED6[39];
+ __I uint8_t FIFOLVL;
+} LPC_UART_TypeDef;
+
+/** @brief Universal Asynchronous Receiver Transmitter 0 (UART0) register structure definition */
+typedef struct
+{
+ union {
+ __I uint8_t RBR;
+ __O uint8_t THR;
+ __IO uint8_t DLL;
+ uint32_t RESERVED0;
+ };
+ union {
+ __IO uint8_t DLM;
+ __IO uint32_t IER;
+ };
+ union {
+ __I uint32_t IIR;
+ __O uint8_t FCR;
+ };
+ __IO uint8_t LCR;
+ uint8_t RESERVED1[7];
+ __I uint8_t LSR;
+ uint8_t RESERVED2[7];
+ __IO uint8_t SCR;
+ uint8_t RESERVED3[3];
+ __IO uint32_t ACR;
+ __IO uint8_t ICR;
+ uint8_t RESERVED4[3];
+ __IO uint8_t FDR;
+ uint8_t RESERVED5[7];
+ __IO uint8_t TER;
+ uint8_t RESERVED6[39];
+ __I uint8_t FIFOLVL;
+} LPC_UART0_TypeDef;
+
+/** @brief Universal Asynchronous Receiver Transmitter 1 (UART1) register structure definition */
+typedef struct
+{
+ union {
+ __I uint8_t RBR;
+ __O uint8_t THR;
+ __IO uint8_t DLL;
+ uint32_t RESERVED0;
+ };
+ union {
+ __IO uint8_t DLM;
+ __IO uint32_t IER;
+ };
+ union {
+ __I uint32_t IIR;
+ __O uint8_t FCR;
+ };
+ __IO uint8_t LCR;
+ uint8_t RESERVED1[3];
+ __IO uint8_t MCR;
+ uint8_t RESERVED2[3];
+ __I uint8_t LSR;
+ uint8_t RESERVED3[3];
+ __I uint8_t MSR;
+ uint8_t RESERVED4[3];
+ __IO uint8_t SCR;
+ uint8_t RESERVED5[3];
+ __IO uint32_t ACR;
+ uint32_t RESERVED6;
+ __IO uint32_t FDR;
+ uint32_t RESERVED7;
+ __IO uint8_t TER;
+ uint8_t RESERVED8[27];
+ __IO uint8_t RS485CTRL;
+ uint8_t RESERVED9[3];
+ __IO uint8_t ADRMATCH;
+ uint8_t RESERVED10[3];
+ __IO uint8_t RS485DLY;
+ uint8_t RESERVED11[3];
+ __I uint8_t FIFOLVL;
+} LPC_UART1_TypeDef;
+
+/*------------- Serial Peripheral Interface (SPI) ----------------------------*/
+/** @brief Serial Peripheral Interface (SPI) register structure definition */
+typedef struct
+{
+ __IO uint32_t SPCR;
+ __I uint32_t SPSR;
+ __IO uint32_t SPDR;
+ __IO uint32_t SPCCR;
+ uint32_t RESERVED0[3];
+ __IO uint32_t SPINT;
+} LPC_SPI_TypeDef;
+
+/*------------- Synchronous Serial Communication (SSP) -----------------------*/
+/** @brief Synchronous Serial Communication (SSP) register structure definition */
+typedef struct
+{
+ __IO uint32_t CR0;
+ __IO uint32_t CR1;
+ __IO uint32_t DR;
+ __I uint32_t SR;
+ __IO uint32_t CPSR;
+ __IO uint32_t IMSC;
+ __IO uint32_t RIS;
+ __IO uint32_t MIS;
+ __IO uint32_t ICR;
+ __IO uint32_t DMACR;
+} LPC_SSP_TypeDef;
+
+/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
+/** @brief Inter-Integrated Circuit (I2C) register structure definition */
+typedef struct
+{
+ __IO uint32_t I2CONSET;
+ __I uint32_t I2STAT;
+ __IO uint32_t I2DAT;
+ __IO uint32_t I2ADR0;
+ __IO uint32_t I2SCLH;
+ __IO uint32_t I2SCLL;
+ __O uint32_t I2CONCLR;
+ __IO uint32_t MMCTRL;
+ __IO uint32_t I2ADR1;
+ __IO uint32_t I2ADR2;
+ __IO uint32_t I2ADR3;
+ __I uint32_t I2DATA_BUFFER;
+ __IO uint32_t I2MASK0;
+ __IO uint32_t I2MASK1;
+ __IO uint32_t I2MASK2;
+ __IO uint32_t I2MASK3;
+} LPC_I2C_TypeDef;
+
+/*------------- Inter IC Sound (I2S) -----------------------------------------*/
+/** @brief Inter IC Sound (I2S) register structure definition */
+typedef struct
+{
+ __IO uint32_t I2SDAO;
+ __IO uint32_t I2SDAI;
+ __O uint32_t I2STXFIFO;
+ __I uint32_t I2SRXFIFO;
+ __I uint32_t I2SSTATE;
+ __IO uint32_t I2SDMA1;
+ __IO uint32_t I2SDMA2;
+ __IO uint32_t I2SIRQ;
+ __IO uint32_t I2STXRATE;
+ __IO uint32_t I2SRXRATE;
+ __IO uint32_t I2STXBITRATE;
+ __IO uint32_t I2SRXBITRATE;
+ __IO uint32_t I2STXMODE;
+ __IO uint32_t I2SRXMODE;
+} LPC_I2S_TypeDef;
+
+/*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
+/** @brief Repetitive Interrupt Timer (RIT) register structure definition */
+typedef struct
+{
+ __IO uint32_t RICOMPVAL;
+ __IO uint32_t RIMASK;
+ __IO uint8_t RICTRL;
+ uint8_t RESERVED0[3];
+ __IO uint32_t RICOUNTER;
+} LPC_RIT_TypeDef;
+
+/*------------- Real-Time Clock (RTC) ----------------------------------------*/
+/** @brief Real-Time Clock (RTC) register structure definition */
+typedef struct
+{
+ __IO uint8_t ILR;
+ uint8_t RESERVED0[7];
+ __IO uint8_t CCR;
+ uint8_t RESERVED1[3];
+ __IO uint8_t CIIR;
+ uint8_t RESERVED2[3];
+ __IO uint8_t AMR;
+ uint8_t RESERVED3[3];
+ __I uint32_t CTIME0;
+ __I uint32_t CTIME1;
+ __I uint32_t CTIME2;
+ __IO uint8_t SEC;
+ uint8_t RESERVED4[3];
+ __IO uint8_t MIN;
+ uint8_t RESERVED5[3];
+ __IO uint8_t HOUR;
+ uint8_t RESERVED6[3];
+ __IO uint8_t DOM;
+ uint8_t RESERVED7[3];
+ __IO uint8_t DOW;
+ uint8_t RESERVED8[3];
+ __IO uint16_t DOY;
+ uint16_t RESERVED9;
+ __IO uint8_t MONTH;
+ uint8_t RESERVED10[3];
+ __IO uint16_t YEAR;
+ uint16_t RESERVED11;
+ __IO uint32_t CALIBRATION;
+ __IO uint32_t GPREG0;
+ __IO uint32_t GPREG1;
+ __IO uint32_t GPREG2;
+ __IO uint32_t GPREG3;
+ __IO uint32_t GPREG4;
+ __IO uint8_t RTC_AUXEN;
+ uint8_t RESERVED12[3];
+ __IO uint8_t RTC_AUX;
+ uint8_t RESERVED13[3];
+ __IO uint8_t ALSEC;
+ uint8_t RESERVED14[3];
+ __IO uint8_t ALMIN;
+ uint8_t RESERVED15[3];
+ __IO uint8_t ALHOUR;
+ uint8_t RESERVED16[3];
+ __IO uint8_t ALDOM;
+ uint8_t RESERVED17[3];
+ __IO uint8_t ALDOW;
+ uint8_t RESERVED18[3];
+ __IO uint16_t ALDOY;
+ uint16_t RESERVED19;
+ __IO uint8_t ALMON;
+ uint8_t RESERVED20[3];
+ __IO uint16_t ALYEAR;
+ uint16_t RESERVED21;
+} LPC_RTC_TypeDef;
+
+/*------------- Watchdog Timer (WDT) -----------------------------------------*/
+/** @brief Watchdog Timer (WDT) register structure definition */
+typedef struct
+{
+ __IO uint8_t WDMOD;
+ uint8_t RESERVED0[3];
+ __IO uint32_t WDTC;
+ __O uint8_t WDFEED;
+ uint8_t RESERVED1[3];
+ __I uint32_t WDTV;
+ __IO uint32_t WDCLKSEL;
+} LPC_WDT_TypeDef;
+
+/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
+/** @brief Analog-to-Digital Converter (ADC) register structure definition */
+typedef struct
+{
+ __IO uint32_t ADCR;
+ __IO uint32_t ADGDR;
+ uint32_t RESERVED0;
+ __IO uint32_t ADINTEN;
+ __I uint32_t ADDR0;
+ __I uint32_t ADDR1;
+ __I uint32_t ADDR2;
+ __I uint32_t ADDR3;
+ __I uint32_t ADDR4;
+ __I uint32_t ADDR5;
+ __I uint32_t ADDR6;
+ __I uint32_t ADDR7;
+ __I uint32_t ADSTAT;
+ __IO uint32_t ADTRM;
+} LPC_ADC_TypeDef;
+
+/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
+/** @brief Digital-to-Analog Converter (DAC) register structure definition */
+typedef struct
+{
+ __IO uint32_t DACR;
+ __IO uint32_t DACCTRL;
+ __IO uint16_t DACCNTVAL;
+} LPC_DAC_TypeDef;
+
+/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
+/** @brief Motor Control Pulse-Width Modulation (MCPWM) register structure definition */
+typedef struct
+{
+ __I uint32_t MCCON;
+ __O uint32_t MCCON_SET;
+ __O uint32_t MCCON_CLR;
+ __I uint32_t MCCAPCON;
+ __O uint32_t MCCAPCON_SET;
+ __O uint32_t MCCAPCON_CLR;
+ __IO uint32_t MCTIM0;
+ __IO uint32_t MCTIM1;
+ __IO uint32_t MCTIM2;
+ __IO uint32_t MCPER0;
+ __IO uint32_t MCPER1;
+ __IO uint32_t MCPER2;
+ __IO uint32_t MCPW0;
+ __IO uint32_t MCPW1;
+ __IO uint32_t MCPW2;
+ __IO uint32_t MCDEADTIME;
+ __IO uint32_t MCCCP;
+ __IO uint32_t MCCR0;
+ __IO uint32_t MCCR1;
+ __IO uint32_t MCCR2;
+ __I uint32_t MCINTEN;
+ __O uint32_t MCINTEN_SET;
+ __O uint32_t MCINTEN_CLR;
+ __I uint32_t MCCNTCON;
+ __O uint32_t MCCNTCON_SET;
+ __O uint32_t MCCNTCON_CLR;
+ __I uint32_t MCINTFLAG;
+ __O uint32_t MCINTFLAG_SET;
+ __O uint32_t MCINTFLAG_CLR;
+ __O uint32_t MCCAP_CLR;
+} LPC_MCPWM_TypeDef;
+
+/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
+/** @brief Quadrature Encoder Interface (QEI) register structure definition */
+typedef struct
+{
+ __O uint32_t QEICON;
+ __I uint32_t QEISTAT;
+ __IO uint32_t QEICONF;
+ __I uint32_t QEIPOS;
+ __IO uint32_t QEIMAXPOS;
+ __IO uint32_t CMPOS0;
+ __IO uint32_t CMPOS1;
+ __IO uint32_t CMPOS2;
+ __I uint32_t INXCNT;
+ __IO uint32_t INXCMP;
+ __IO uint32_t QEILOAD;
+ __I uint32_t QEITIME;
+ __I uint32_t QEIVEL;
+ __I uint32_t QEICAP;
+ __IO uint32_t VELCOMP;
+ __IO uint32_t FILTER;
+ uint32_t RESERVED0[998];
+ __O uint32_t QEIIEC;
+ __O uint32_t QEIIES;
+ __I uint32_t QEIINTSTAT;
+ __I uint32_t QEIIE;
+ __O uint32_t QEICLR;
+ __O uint32_t QEISET;
+} LPC_QEI_TypeDef;
+
+/*------------- Controller Area Network (CAN) --------------------------------*/
+/** @brief Controller Area Network Acceptance Filter RAM (CANAF_RAM)structure definition */
+typedef struct
+{
+ __IO uint32_t mask[512]; /* ID Masks */
+} LPC_CANAF_RAM_TypeDef;
+
+/** @brief Controller Area Network Acceptance Filter(CANAF) register structure definition */
+typedef struct /* Acceptance Filter Registers */
+{
+ __IO uint32_t AFMR;
+ __IO uint32_t SFF_sa;
+ __IO uint32_t SFF_GRP_sa;
+ __IO uint32_t EFF_sa;
+ __IO uint32_t EFF_GRP_sa;
+ __IO uint32_t ENDofTable;
+ __I uint32_t LUTerrAd;
+ __I uint32_t LUTerr;
+ __IO uint32_t FCANIE;
+ __IO uint32_t FCANIC0;
+ __IO uint32_t FCANIC1;
+} LPC_CANAF_TypeDef;
+
+/** @brief Controller Area Network Central (CANCR) register structure definition */
+typedef struct /* Central Registers */
+{
+ __I uint32_t CANTxSR;
+ __I uint32_t CANRxSR;
+ __I uint32_t CANMSR;
+} LPC_CANCR_TypeDef;
+
+/** @brief Controller Area Network Controller (CAN) register structure definition */
+typedef struct /* Controller Registers */
+{
+ __IO uint32_t MOD;
+ __O uint32_t CMR;
+ __IO uint32_t GSR;
+ __I uint32_t ICR;
+ __IO uint32_t IER;
+ __IO uint32_t BTR;
+ __IO uint32_t EWL;
+ __I uint32_t SR;
+ __IO uint32_t RFS;
+ __IO uint32_t RID;
+ __IO uint32_t RDA;
+ __IO uint32_t RDB;
+ __IO uint32_t TFI1;
+ __IO uint32_t TID1;
+ __IO uint32_t TDA1;
+ __IO uint32_t TDB1;
+ __IO uint32_t TFI2;
+ __IO uint32_t TID2;
+ __IO uint32_t TDA2;
+ __IO uint32_t TDB2;
+ __IO uint32_t TFI3;
+ __IO uint32_t TID3;
+ __IO uint32_t TDA3;
+ __IO uint32_t TDB3;
+} LPC_CAN_TypeDef;
+
+/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
+/** @brief General Purpose Direct Memory Access (GPDMA) register structure definition */
+typedef struct /* Common Registers */
+{
+ __I uint32_t DMACIntStat;
+ __I uint32_t DMACIntTCStat;
+ __O uint32_t DMACIntTCClear;
+ __I uint32_t DMACIntErrStat;
+ __O uint32_t DMACIntErrClr;
+ __I uint32_t DMACRawIntTCStat;
+ __I uint32_t DMACRawIntErrStat;
+ __I uint32_t DMACEnbldChns;
+ __IO uint32_t DMACSoftBReq;
+ __IO uint32_t DMACSoftSReq;
+ __IO uint32_t DMACSoftLBReq;
+ __IO uint32_t DMACSoftLSReq;
+ __IO uint32_t DMACConfig;
+ __IO uint32_t DMACSync;
+} LPC_GPDMA_TypeDef;
+
+/** @brief General Purpose Direct Memory Access Channel (GPDMACH) register structure definition */
+typedef struct /* Channel Registers */
+{
+ __IO uint32_t DMACCSrcAddr;
+ __IO uint32_t DMACCDestAddr;
+ __IO uint32_t DMACCLLI;
+ __IO uint32_t DMACCControl;
+ __IO uint32_t DMACCConfig;
+} LPC_GPDMACH_TypeDef;
+
+/*------------- Universal Serial Bus (USB) -----------------------------------*/
+/** @brief Universal Serial Bus (USB) register structure definition */
+typedef struct
+{
+ __I uint32_t HcRevision; /* USB Host Registers */
+ __IO uint32_t HcControl;
+ __IO uint32_t HcCommandStatus;
+ __IO uint32_t HcInterruptStatus;
+ __IO uint32_t HcInterruptEnable;
+ __IO uint32_t HcInterruptDisable;
+ __IO uint32_t HcHCCA;
+ __I uint32_t HcPeriodCurrentED;
+ __IO uint32_t HcControlHeadED;
+ __IO uint32_t HcControlCurrentED;
+ __IO uint32_t HcBulkHeadED;
+ __IO uint32_t HcBulkCurrentED;
+ __I uint32_t HcDoneHead;
+ __IO uint32_t HcFmInterval;
+ __I uint32_t HcFmRemaining;
+ __I uint32_t HcFmNumber;
+ __IO uint32_t HcPeriodicStart;
+ __IO uint32_t HcLSTreshold;
+ __IO uint32_t HcRhDescriptorA;
+ __IO uint32_t HcRhDescriptorB;
+ __IO uint32_t HcRhStatus;
+ __IO uint32_t HcRhPortStatus1;
+ __IO uint32_t HcRhPortStatus2;
+ uint32_t RESERVED0[40];
+ __I uint32_t Module_ID;
+
+ __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
+ __IO uint32_t OTGIntEn;
+ __O uint32_t OTGIntSet;
+ __O uint32_t OTGIntClr;
+ __IO uint32_t OTGStCtrl;
+ __IO uint32_t OTGTmr;
+ uint32_t RESERVED1[58];
+
+ __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
+ __IO uint32_t USBDevIntEn;
+ __O uint32_t USBDevIntClr;
+ __O uint32_t USBDevIntSet;
+
+ __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
+ __I uint32_t USBCmdData;
+
+ __I uint32_t USBRxData; /* USB Device Transfer Registers */
+ __O uint32_t USBTxData;
+ __I uint32_t USBRxPLen;
+ __O uint32_t USBTxPLen;
+ __IO uint32_t USBCtrl;
+ __O uint32_t USBDevIntPri;
+
+ __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
+ __IO uint32_t USBEpIntEn;
+ __O uint32_t USBEpIntClr;
+ __O uint32_t USBEpIntSet;
+ __O uint32_t USBEpIntPri;
+
+ __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
+ __O uint32_t USBEpInd;
+ __IO uint32_t USBMaxPSize;
+
+ __I uint32_t USBDMARSt; /* USB Device DMA Registers */
+ __O uint32_t USBDMARClr;
+ __O uint32_t USBDMARSet;
+ uint32_t RESERVED2[9];
+ __IO uint32_t USBUDCAH;
+ __I uint32_t USBEpDMASt;
+ __O uint32_t USBEpDMAEn;
+ __O uint32_t USBEpDMADis;
+ __I uint32_t USBDMAIntSt;
+ __IO uint32_t USBDMAIntEn;
+ uint32_t RESERVED3[2];
+ __I uint32_t USBEoTIntSt;
+ __O uint32_t USBEoTIntClr;
+ __O uint32_t USBEoTIntSet;
+ __I uint32_t USBNDDRIntSt;
+ __O uint32_t USBNDDRIntClr;
+ __O uint32_t USBNDDRIntSet;
+ __I uint32_t USBSysErrIntSt;
+ __O uint32_t USBSysErrIntClr;
+ __O uint32_t USBSysErrIntSet;
+ uint32_t RESERVED4[15];
+
+ union {
+ __I uint32_t I2C_RX; /* USB OTG I2C Registers */
+ __O uint32_t I2C_TX;
+ };
+ __I uint32_t I2C_STS;
+ __IO uint32_t I2C_CTL;
+ __IO uint32_t I2C_CLKHI;
+ __O uint32_t I2C_CLKLO;
+ uint32_t RESERVED5[824];
+
+ union {
+ __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
+ __IO uint32_t OTGClkCtrl;
+ };
+ union {
+ __I uint32_t USBClkSt;
+ __I uint32_t OTGClkSt;
+ };
+} LPC_USB_TypeDef;
+
+/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
+/** @brief Ethernet Media Access Controller (EMAC) register structure definition */
+typedef struct
+{
+ __IO uint32_t MAC1; /* MAC Registers */
+ __IO uint32_t MAC2;
+ __IO uint32_t IPGT;
+ __IO uint32_t IPGR;
+ __IO uint32_t CLRT;
+ __IO uint32_t MAXF;
+ __IO uint32_t SUPP;
+ __IO uint32_t TEST;
+ __IO uint32_t MCFG;
+ __IO uint32_t MCMD;
+ __IO uint32_t MADR;
+ __O uint32_t MWTD;
+ __I uint32_t MRDD;
+ __I uint32_t MIND;
+ uint32_t RESERVED0[2];
+ __IO uint32_t SA0;
+ __IO uint32_t SA1;
+ __IO uint32_t SA2;
+ uint32_t RESERVED1[45];
+ __IO uint32_t Command; /* Control Registers */
+ __I uint32_t Status;
+ __IO uint32_t RxDescriptor;
+ __IO uint32_t RxStatus;
+ __IO uint32_t RxDescriptorNumber;
+ __I uint32_t RxProduceIndex;
+ __IO uint32_t RxConsumeIndex;
+ __IO uint32_t TxDescriptor;
+ __IO uint32_t TxStatus;
+ __IO uint32_t TxDescriptorNumber;
+ __IO uint32_t TxProduceIndex;
+ __I uint32_t TxConsumeIndex;
+ uint32_t RESERVED2[10];
+ __I uint32_t TSV0;
+ __I uint32_t TSV1;
+ __I uint32_t RSV;
+ uint32_t RESERVED3[3];
+ __IO uint32_t FlowControlCounter;
+ __I uint32_t FlowControlStatus;
+ uint32_t RESERVED4[34];
+ __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
+ __IO uint32_t RxFilterWoLStatus;
+ __IO uint32_t RxFilterWoLClear;
+ uint32_t RESERVED5;
+ __IO uint32_t HashFilterL;
+ __IO uint32_t HashFilterH;
+ uint32_t RESERVED6[882];
+ __I uint32_t IntStatus; /* Module Control Registers */
+ __IO uint32_t IntEnable;
+ __O uint32_t IntClear;
+ __O uint32_t IntSet;
+ uint32_t RESERVED7;
+ __IO uint32_t PowerDown;
+ uint32_t RESERVED8;
+ __IO uint32_t Module_ID;
+} LPC_EMAC_TypeDef;
+
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+/* Base addresses */
+#define LPC_FLASH_BASE (0x00000000UL)
+#define LPC_RAM_BASE (0x10000000UL)
+#ifdef __LPC17XX_REV00
+#define LPC_AHBRAM0_BASE (0x20000000UL)
+#define LPC_AHBRAM1_BASE (0x20004000UL)
+#else
+#define LPC_AHBRAM0_BASE (0x2007C000UL)
+#define LPC_AHBRAM1_BASE (0x20080000UL)
+#endif
+#define LPC_GPIO_BASE (0x2009C000UL)
+#define LPC_APB0_BASE (0x40000000UL)
+#define LPC_APB1_BASE (0x40080000UL)
+#define LPC_AHB_BASE (0x50000000UL)
+#define LPC_CM3_BASE (0xE0000000UL)
+
+/* APB0 peripherals */
+#define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
+#define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
+#define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
+#define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
+#define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
+#define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
+#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
+#define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
+#define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
+#define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
+#define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
+#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
+#define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
+#define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
+#define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
+#define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
+#define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
+#define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
+#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
+
+/* APB1 peripherals */
+#define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
+#define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
+#define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
+#define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
+#define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
+#define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
+#define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
+#define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
+#define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
+#define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
+#define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
+#define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
+
+/* AHB peripherals */
+#define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
+#define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
+#define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
+#define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
+#define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
+#define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
+#define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
+#define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
+#define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
+#define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
+#define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
+
+/* GPIOs */
+#define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
+#define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
+#define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
+#define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
+#define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
+
+/******************************************************************************/
+/* Peripheral declaration */
+/******************************************************************************/
+#define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
+#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
+#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
+#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
+#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
+#define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
+#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
+#define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
+#define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
+#define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
+#define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
+#define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
+#define LPC_UART0 ((LPC_UART_TypeDef *) LPC_UART0_BASE )
+#define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
+#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
+#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
+#define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
+#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
+#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
+#define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
+#define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
+#define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
+#define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
+#define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
+#define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
+#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
+#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
+#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
+#define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
+#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
+#define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
+#define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
+#define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
+#define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
+#define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
+#define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
+#define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
+#define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
+#define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
+#define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
+#define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
+#define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
+#define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
+#define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
+#define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
+#define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
+#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
+
+/**
+ * @}
+ */
+
+#endif // __LPC17xx_H__
diff --git a/src/shared/cmsis/Core/Device/NXP/LPC17xx/Include/system_LPC17xx.h b/src/shared/cmsis/Core/Device/NXP/LPC17xx/Include/system_LPC17xx.h
@@ -0,0 +1,72 @@
+/**************************************************************************//**
+ * @file system_LPC17xx.h
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File
+ * for the NXP LPC17xx Device Series
+ * @version V1.02
+ * @date 08. September 2009
+ *
+ * @note
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __SYSTEM_LPC17xx_H
+#define __SYSTEM_LPC17xx_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/** @addtogroup LPC17xx_System
+ * @{
+ */
+
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* __SYSTEM_LPC17xx_H */
diff --git a/src/shared/cmsis/Drivers/include/debug_frmwrk.h b/src/shared/cmsis/Drivers/include/debug_frmwrk.h
@@ -0,0 +1,80 @@
+/**********************************************************************
+* $Id$ debug_frmwrk.h 2010-05-21
+*//**
+* @file debug_frmwrk.h
+* @brief Contains some utilities that used for debugging through UART
+* @version 2.0
+* @date 21. May. 2010
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2010, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+#ifndef DEBUG_FRMWRK_H_
+#define DEBUG_FRMWRK_H_
+
+//#include <stdarg.h>
+#include "lpc17xx_uart.h"
+
+#define USED_UART_DEBUG_PORT 0
+
+#if (USED_UART_DEBUG_PORT==0)
+#define DEBUG_UART_PORT LPC_UART0
+#elif (USED_UART_DEBUG_PORT==1)
+#define DEBUG_UART_PORT LPC_UART1
+#endif
+
+#define _DBG(x) _db_msg(DEBUG_UART_PORT, x)
+#define _DBG_(x) _db_msg_(DEBUG_UART_PORT, x)
+#define _DBC(x) _db_char(DEBUG_UART_PORT, x)
+#define _DBD(x) _db_dec(DEBUG_UART_PORT, x)
+#define _DBD16(x) _db_dec_16(DEBUG_UART_PORT, x)
+#define _DBD32(x) _db_dec_32(DEBUG_UART_PORT, x)
+#define _DBH(x) _db_hex(DEBUG_UART_PORT, x)
+#define _DBH16(x) _db_hex_16(DEBUG_UART_PORT, x)
+#define _DBH32(x) _db_hex_32(DEBUG_UART_PORT, x)
+#define _DG _db_get_char(DEBUG_UART_PORT)
+//void _printf (const char *format, ...);
+
+extern void (*_db_msg)(LPC_UART_TypeDef *UARTx, const void *s);
+extern void (*_db_msg_)(LPC_UART_TypeDef *UARTx, const void *s);
+extern void (*_db_char)(LPC_UART_TypeDef *UARTx, uint8_t ch);
+extern void (*_db_dec)(LPC_UART_TypeDef *UARTx, uint8_t decn);
+extern void (*_db_dec_16)(LPC_UART_TypeDef *UARTx, uint16_t decn);
+extern void (*_db_dec_32)(LPC_UART_TypeDef *UARTx, uint32_t decn);
+extern void (*_db_hex)(LPC_UART_TypeDef *UARTx, uint8_t hexn);
+extern void (*_db_hex_16)(LPC_UART_TypeDef *UARTx, uint16_t hexn);
+extern void (*_db_hex_32)(LPC_UART_TypeDef *UARTx, uint32_t hexn);
+extern uint8_t (*_db_get_char)(LPC_UART_TypeDef *UARTx);
+
+void UARTPutChar (LPC_UART_TypeDef *UARTx, uint8_t ch);
+void UARTPuts(LPC_UART_TypeDef *UARTx, const void *str);
+void UARTPuts_(LPC_UART_TypeDef *UARTx, const void *str);
+void UARTPutDec(LPC_UART_TypeDef *UARTx, uint8_t decnum);
+void UARTPutDec16(LPC_UART_TypeDef *UARTx, uint16_t decnum);
+void UARTPutDec32(LPC_UART_TypeDef *UARTx, uint32_t decnum);
+void UARTPutHex (LPC_UART_TypeDef *UARTx, uint8_t hexnum);
+void UARTPutHex16 (LPC_UART_TypeDef *UARTx, uint16_t hexnum);
+void UARTPutHex32 (LPC_UART_TypeDef *UARTx, uint32_t hexnum);
+uint8_t UARTGetChar (LPC_UART_TypeDef *UARTx);
+void debug_frmwrk_init(void);
+
+#endif /* DEBUG_FRMWRK_H_ */
diff --git a/src/shared/cmsis/Drivers/include/lpc17xx_adc.h b/src/shared/cmsis/Drivers/include/lpc17xx_adc.h
@@ -0,0 +1,303 @@
+/**********************************************************************
+* $Id$ lpc17xx_adc.h 2008-07-27
+*//**
+* @file lpc17xx_adc.h
+* @brief Contains the NXP ABL typedefs for C standard types.
+* It is intended to be used in ISO C conforming development
+* environments and checks for this insofar as it is possible
+* to do so.
+* @version 2.0
+* @date 27 Jul. 2008
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2008, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup ADC ADC (Analog-to-Digital Converter)
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_ADC_H_
+#define LPC17XX_ADC_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Private macros ------------------------------------------------------------- */
+/** @defgroup ADC_Private_Macros ADC Private Macros
+ * @{
+ */
+
+/* -------------------------- BIT DEFINITIONS ----------------------------------- */
+/*********************************************************************//**
+ * Macro defines for ADC control register
+ **********************************************************************/
+/** Selects which of the AD0.0:7 pins is (are) to be sampled and converted */
+#define ADC_CR_CH_SEL(n) ((1UL << n))
+/** The APB clock (PCLK) is divided by (this value plus one)
+* to produce the clock for the A/D */
+#define ADC_CR_CLKDIV(n) ((n<<8))
+/** Repeated conversions A/D enable bit */
+#define ADC_CR_BURST ((1UL<<16))
+/** ADC convert in power down mode */
+#define ADC_CR_PDN ((1UL<<21))
+/** Start mask bits */
+#define ADC_CR_START_MASK ((7UL<<24))
+/** Select Start Mode */
+#define ADC_CR_START_MODE_SEL(SEL) ((SEL<<24))
+/** Start conversion now */
+#define ADC_CR_START_NOW ((1UL<<24))
+/** Start conversion when the edge selected by bit 27 occurs on P2.10/EINT0 */
+#define ADC_CR_START_EINT0 ((2UL<<24))
+/** Start conversion when the edge selected by bit 27 occurs on P1.27/CAP0.1 */
+#define ADC_CR_START_CAP01 ((3UL<<24))
+/** Start conversion when the edge selected by bit 27 occurs on MAT0.1 */
+#define ADC_CR_START_MAT01 ((4UL<<24))
+/** Start conversion when the edge selected by bit 27 occurs on MAT0.3 */
+#define ADC_CR_START_MAT03 ((5UL<<24))
+/** Start conversion when the edge selected by bit 27 occurs on MAT1.0 */
+#define ADC_CR_START_MAT10 ((6UL<<24))
+/** Start conversion when the edge selected by bit 27 occurs on MAT1.1 */
+#define ADC_CR_START_MAT11 ((7UL<<24))
+/** Start conversion on a falling edge on the selected CAP/MAT signal */
+#define ADC_CR_EDGE ((1UL<<27))
+
+/*********************************************************************//**
+ * Macro defines for ADC Global Data register
+ **********************************************************************/
+/** When DONE is 1, this field contains result value of ADC conversion */
+#define ADC_GDR_RESULT(n) (((n>>4)&0xFFF))
+/** These bits contain the channel from which the LS bits were converted */
+#define ADC_GDR_CH(n) (((n>>24)&0x7))
+/** This bit is 1 in burst mode if the results of one or
+ * more conversions was (were) lost */
+#define ADC_GDR_OVERRUN_FLAG ((1UL<<30))
+/** This bit is set to 1 when an A/D conversion completes */
+#define ADC_GDR_DONE_FLAG ((1UL<<31))
+
+/** This bits is used to mask for Channel */
+#define ADC_GDR_CH_MASK ((7UL<<24))
+/*********************************************************************//**
+ * Macro defines for ADC Interrupt register
+ **********************************************************************/
+/** These bits allow control over which A/D channels generate
+ * interrupts for conversion completion */
+#define ADC_INTEN_CH(n) ((1UL<<n))
+/** When 1, enables the global DONE flag in ADDR to generate an interrupt */
+#define ADC_INTEN_GLOBAL ((1UL<<8))
+
+/*********************************************************************//**
+ * Macro defines for ADC Data register
+ **********************************************************************/
+/** When DONE is 1, this field contains result value of ADC conversion */
+#define ADC_DR_RESULT(n) (((n>>4)&0xFFF))
+/** These bits mirror the OVERRRUN status flags that appear in the
+ * result register for each A/D channel */
+#define ADC_DR_OVERRUN_FLAG ((1UL<<30))
+/** This bit is set to 1 when an A/D conversion completes. It is cleared
+ * when this register is read */
+#define ADC_DR_DONE_FLAG ((1UL<<31))
+
+/*********************************************************************//**
+ * Macro defines for ADC Status register
+**********************************************************************/
+/** These bits mirror the DONE status flags that appear in the result
+ * register for each A/D channel */
+#define ADC_STAT_CH_DONE_FLAG(n) ((n&0xFF))
+/** These bits mirror the OVERRRUN status flags that appear in the
+ * result register for each A/D channel */
+#define ADC_STAT_CH_OVERRUN_FLAG(n) (((n>>8)&0xFF))
+/** This bit is the A/D interrupt flag */
+#define ADC_STAT_INT_FLAG ((1UL<<16))
+
+/*********************************************************************//**
+ * Macro defines for ADC Trim register
+**********************************************************************/
+/** Offset trim bits for ADC operation */
+#define ADC_ADCOFFS(n) (((n&0xF)<<4))
+/** Written to boot code*/
+#define ADC_TRIM(n) (((n&0xF)<<8))
+
+/* ------------------- CHECK PARAM DEFINITIONS ------------------------- */
+/** Check ADC parameter */
+#define PARAM_ADCx(n) (((uint32_t *)n)==((uint32_t *)LPC_ADC))
+
+/** Check ADC state parameter */
+#define PARAM_ADC_START_ON_EDGE_OPT(OPT) ((OPT == ADC_START_ON_RISING)||(OPT == ADC_START_ON_FALLING))
+
+/** Check ADC state parameter */
+#define PARAM_ADC_DATA_STATUS(OPT) ((OPT== ADC_DATA_BURST)||(OPT== ADC_DATA_DONE))
+
+/** Check ADC rate parameter */
+#define PARAM_ADC_RATE(rate) ((rate>0)&&(rate<=200000))
+
+/** Check ADC channel selection parameter */
+#define PARAM_ADC_CHANNEL_SELECTION(SEL) ((SEL == ADC_CHANNEL_0)||(ADC_CHANNEL_1)\
+||(SEL == ADC_CHANNEL_2)|(ADC_CHANNEL_3)\
+||(SEL == ADC_CHANNEL_4)||(ADC_CHANNEL_5)\
+||(SEL == ADC_CHANNEL_6)||(ADC_CHANNEL_7))
+
+/** Check ADC start option parameter */
+#define PARAM_ADC_START_OPT(OPT) ((OPT == ADC_START_CONTINUOUS)||(OPT == ADC_START_NOW)\
+||(OPT == ADC_START_ON_EINT0)||(OPT == ADC_START_ON_CAP01)\
+||(OPT == ADC_START_ON_MAT01)||(OPT == ADC_START_ON_MAT03)\
+||(OPT == ADC_START_ON_MAT10)||(OPT == ADC_START_ON_MAT11))
+
+/** Check ADC interrupt type parameter */
+#define PARAM_ADC_TYPE_INT_OPT(OPT) ((OPT == ADC_ADINTEN0)||(OPT == ADC_ADINTEN1)\
+||(OPT == ADC_ADINTEN2)||(OPT == ADC_ADINTEN3)\
+||(OPT == ADC_ADINTEN4)||(OPT == ADC_ADINTEN5)\
+||(OPT == ADC_ADINTEN6)||(OPT == ADC_ADINTEN7)\
+||(OPT == ADC_ADGINTEN))
+
+/**
+ * @}
+ */
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup ADC_Public_Types ADC Public Types
+ * @{
+ */
+
+/*********************************************************************//**
+ * @brief ADC enumeration
+ **********************************************************************/
+/** @brief Channel Selection */
+typedef enum
+{
+ ADC_CHANNEL_0 = 0, /*!< Channel 0 */
+ ADC_CHANNEL_1, /*!< Channel 1 */
+ ADC_CHANNEL_2, /*!< Channel 2 */
+ ADC_CHANNEL_3, /*!< Channel 3 */
+ ADC_CHANNEL_4, /*!< Channel 4 */
+ ADC_CHANNEL_5, /*!< Channel 5 */
+ ADC_CHANNEL_6, /*!< Channel 6 */
+ ADC_CHANNEL_7 /*!< Channel 7 */
+}ADC_CHANNEL_SELECTION;
+
+/** @brief Type of start option */
+typedef enum
+{
+ ADC_START_CONTINUOUS =0, /*!< Continuous mode */
+ ADC_START_NOW, /*!< Start conversion now */
+ ADC_START_ON_EINT0, /*!< Start conversion when the edge selected
+ * by bit 27 occurs on P2.10/EINT0 */
+ ADC_START_ON_CAP01, /*!< Start conversion when the edge selected
+ * by bit 27 occurs on P1.27/CAP0.1 */
+ ADC_START_ON_MAT01, /*!< Start conversion when the edge selected
+ * by bit 27 occurs on MAT0.1 */
+ ADC_START_ON_MAT03, /*!< Start conversion when the edge selected
+ * by bit 27 occurs on MAT0.3 */
+ ADC_START_ON_MAT10, /*!< Start conversion when the edge selected
+ * by bit 27 occurs on MAT1.0 */
+ ADC_START_ON_MAT11 /*!< Start conversion when the edge selected
+ * by bit 27 occurs on MAT1.1 */
+} ADC_START_OPT;
+
+
+/** @brief Type of edge when start conversion on the selected CAP/MAT signal */
+typedef enum
+{
+ ADC_START_ON_RISING = 0, /*!< Start conversion on a rising edge
+ *on the selected CAP/MAT signal */
+ ADC_START_ON_FALLING /*!< Start conversion on a falling edge
+ *on the selected CAP/MAT signal */
+} ADC_START_ON_EDGE_OPT;
+
+/** @brief* ADC type interrupt enum */
+typedef enum
+{
+ ADC_ADINTEN0 = 0, /*!< Interrupt channel 0 */
+ ADC_ADINTEN1, /*!< Interrupt channel 1 */
+ ADC_ADINTEN2, /*!< Interrupt channel 2 */
+ ADC_ADINTEN3, /*!< Interrupt channel 3 */
+ ADC_ADINTEN4, /*!< Interrupt channel 4 */
+ ADC_ADINTEN5, /*!< Interrupt channel 5 */
+ ADC_ADINTEN6, /*!< Interrupt channel 6 */
+ ADC_ADINTEN7, /*!< Interrupt channel 7 */
+ ADC_ADGINTEN /*!< Individual channel/global flag done generate an interrupt */
+}ADC_TYPE_INT_OPT;
+
+/** @brief ADC Data status */
+typedef enum
+{
+ ADC_DATA_BURST = 0, /*Burst bit*/
+ ADC_DATA_DONE /*Done bit*/
+}ADC_DATA_STATUS;
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup ADC_Public_Functions ADC Public Functions
+ * @{
+ */
+/* Init/DeInit ADC peripheral ----------------*/
+void ADC_Init(LPC_ADC_TypeDef *ADCx, uint32_t rate);
+void ADC_DeInit(LPC_ADC_TypeDef *ADCx);
+
+/* Enable/Disable ADC functions --------------*/
+void ADC_BurstCmd(LPC_ADC_TypeDef *ADCx, FunctionalState NewState);
+void ADC_PowerdownCmd(LPC_ADC_TypeDef *ADCx, FunctionalState NewState);
+void ADC_StartCmd(LPC_ADC_TypeDef *ADCx, uint8_t start_mode);
+void ADC_ChannelCmd (LPC_ADC_TypeDef *ADCx, uint8_t Channel, FunctionalState NewState);
+
+/* Configure ADC functions -------------------*/
+void ADC_EdgeStartConfig(LPC_ADC_TypeDef *ADCx, uint8_t EdgeOption);
+void ADC_IntConfig (LPC_ADC_TypeDef *ADCx, ADC_TYPE_INT_OPT IntType, FunctionalState NewState);
+
+/* Get ADC information functions -------------------*/
+uint16_t ADC_ChannelGetData(LPC_ADC_TypeDef *ADCx, uint8_t channel);
+FlagStatus ADC_ChannelGetStatus(LPC_ADC_TypeDef *ADCx, uint8_t channel, uint32_t StatusType);
+uint32_t ADC_GlobalGetData(LPC_ADC_TypeDef *ADCx);
+FlagStatus ADC_GlobalGetStatus(LPC_ADC_TypeDef *ADCx, uint32_t StatusType);
+uint32_t ADC_GetData(uint32_t channel);
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* LPC17XX_ADC_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/src/shared/cmsis/Drivers/include/lpc17xx_can.h b/src/shared/cmsis/Drivers/include/lpc17xx_can.h
@@ -0,0 +1,872 @@
+/**********************************************************************
+* $Id$ lpc17xx_can.h 2010-06-18
+*//**
+* @file lpc17xx_can.h
+* @brief Contains all macro definitions and function prototypes
+* support for CAN firmware library on LPC17xx
+* @version 3.0
+* @date 18. June. 2010
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2010, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup CAN CAN (Control Area Network)
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_CAN_H_
+#define LPC17XX_CAN_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup CAN_Public_Macros CAN Public Macros
+ * @{
+ */
+#define MSG_ENABLE ((uint8_t)(0))
+#define MSG_DISABLE ((uint8_t)(1))
+#define CAN1_CTRL ((uint8_t)(0))
+#define CAN2_CTRL ((uint8_t)(1))
+#define PARAM_FULLCAN_IC(n) ((n==FULLCAN_IC0)||(n==FULLCAN_IC1))
+#define ID_11 1
+#define MAX_HW_FULLCAN_OBJ 64
+#define MAX_SW_FULLCAN_OBJ 32
+
+/**
+ * @}
+ */
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup CAN_Private_Macros CAN Private Macros
+ * @{
+ */
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/*********************************************************************//**
+ * Macro defines for CAN Mode Register
+ **********************************************************************/
+/** CAN Reset mode */
+#define CAN_MOD_RM ((uint32_t)(1))
+/** CAN Listen Only Mode */
+#define CAN_MOD_LOM ((uint32_t)(1<<1))
+/** CAN Self Test mode */
+#define CAN_MOD_STM ((uint32_t)(1<<2))
+/** CAN Transmit Priority mode */
+#define CAN_MOD_TPM ((uint32_t)(1<<3))
+/** CAN Sleep mode */
+#define CAN_MOD_SM ((uint32_t)(1<<4))
+/** CAN Receive Polarity mode */
+#define CAN_MOD_RPM ((uint32_t)(1<<5))
+/** CAN Test mode */
+#define CAN_MOD_TM ((uint32_t)(1<<7))
+
+/*********************************************************************//**
+ * Macro defines for CAN Command Register
+ **********************************************************************/
+/** CAN Transmission Request */
+#define CAN_CMR_TR ((uint32_t)(1))
+/** CAN Abort Transmission */
+#define CAN_CMR_AT ((uint32_t)(1<<1))
+/** CAN Release Receive Buffer */
+#define CAN_CMR_RRB ((uint32_t)(1<<2))
+/** CAN Clear Data Overrun */
+#define CAN_CMR_CDO ((uint32_t)(1<<3))
+/** CAN Self Reception Request */
+#define CAN_CMR_SRR ((uint32_t)(1<<4))
+/** CAN Select Tx Buffer 1 */
+#define CAN_CMR_STB1 ((uint32_t)(1<<5))
+/** CAN Select Tx Buffer 2 */
+#define CAN_CMR_STB2 ((uint32_t)(1<<6))
+/** CAN Select Tx Buffer 3 */
+#define CAN_CMR_STB3 ((uint32_t)(1<<7))
+
+/*********************************************************************//**
+ * Macro defines for CAN Global Status Register
+ **********************************************************************/
+/** CAN Receive Buffer Status */
+#define CAN_GSR_RBS ((uint32_t)(1))
+/** CAN Data Overrun Status */
+#define CAN_GSR_DOS ((uint32_t)(1<<1))
+/** CAN Transmit Buffer Status */
+#define CAN_GSR_TBS ((uint32_t)(1<<2))
+/** CAN Transmit Complete Status */
+#define CAN_GSR_TCS ((uint32_t)(1<<3))
+/** CAN Receive Status */
+#define CAN_GSR_RS ((uint32_t)(1<<4))
+/** CAN Transmit Status */
+#define CAN_GSR_TS ((uint32_t)(1<<5))
+/** CAN Error Status */
+#define CAN_GSR_ES ((uint32_t)(1<<6))
+/** CAN Bus Status */
+#define CAN_GSR_BS ((uint32_t)(1<<7))
+/** CAN Current value of the Rx Error Counter */
+#define CAN_GSR_RXERR(n) ((uint32_t)((n&0xFF)<<16))
+/** CAN Current value of the Tx Error Counter */
+#define CAN_GSR_TXERR(n) ((uint32_t)(n&0xFF)<<24))
+
+/*********************************************************************//**
+ * Macro defines for CAN Interrupt and Capture Register
+ **********************************************************************/
+/** CAN Receive Interrupt */
+#define CAN_ICR_RI ((uint32_t)(1))
+/** CAN Transmit Interrupt 1 */
+#define CAN_ICR_TI1 ((uint32_t)(1<<1))
+/** CAN Error Warning Interrupt */
+#define CAN_ICR_EI ((uint32_t)(1<<2))
+/** CAN Data Overrun Interrupt */
+#define CAN_ICR_DOI ((uint32_t)(1<<3))
+/** CAN Wake-Up Interrupt */
+#define CAN_ICR_WUI ((uint32_t)(1<<4))
+/** CAN Error Passive Interrupt */
+#define CAN_ICR_EPI ((uint32_t)(1<<5))
+/** CAN Arbitration Lost Interrupt */
+#define CAN_ICR_ALI ((uint32_t)(1<<6))
+/** CAN Bus Error Interrupt */
+#define CAN_ICR_BEI ((uint32_t)(1<<7))
+/** CAN ID Ready Interrupt */
+#define CAN_ICR_IDI ((uint32_t)(1<<8))
+/** CAN Transmit Interrupt 2 */
+#define CAN_ICR_TI2 ((uint32_t)(1<<9))
+/** CAN Transmit Interrupt 3 */
+#define CAN_ICR_TI3 ((uint32_t)(1<<10))
+/** CAN Error Code Capture */
+#define CAN_ICR_ERRBIT(n) ((uint32_t)((n&0x1F)<<16))
+/** CAN Error Direction */
+#define CAN_ICR_ERRDIR ((uint32_t)(1<<21))
+/** CAN Error Capture */
+#define CAN_ICR_ERRC(n) ((uint32_t)((n&0x3)<<22))
+/** CAN Arbitration Lost Capture */
+#define CAN_ICR_ALCBIT(n) ((uint32_t)((n&0xFF)<<24))
+
+/*********************************************************************//**
+ * Macro defines for CAN Interrupt Enable Register
+ **********************************************************************/
+/** CAN Receive Interrupt Enable */
+#define CAN_IER_RIE ((uint32_t)(1))
+/** CAN Transmit Interrupt Enable for buffer 1 */
+#define CAN_IER_TIE1 ((uint32_t)(1<<1))
+/** CAN Error Warning Interrupt Enable */
+#define CAN_IER_EIE ((uint32_t)(1<<2))
+/** CAN Data Overrun Interrupt Enable */
+#define CAN_IER_DOIE ((uint32_t)(1<<3))
+/** CAN Wake-Up Interrupt Enable */
+#define CAN_IER_WUIE ((uint32_t)(1<<4))
+/** CAN Error Passive Interrupt Enable */
+#define CAN_IER_EPIE ((uint32_t)(1<<5))
+/** CAN Arbitration Lost Interrupt Enable */
+#define CAN_IER_ALIE ((uint32_t)(1<<6))
+/** CAN Bus Error Interrupt Enable */
+#define CAN_IER_BEIE ((uint32_t)(1<<7))
+/** CAN ID Ready Interrupt Enable */
+#define CAN_IER_IDIE ((uint32_t)(1<<8))
+/** CAN Transmit Enable Interrupt for Buffer 2 */
+#define CAN_IER_TIE2 ((uint32_t)(1<<9))
+/** CAN Transmit Enable Interrupt for Buffer 3 */
+#define CAN_IER_TIE3 ((uint32_t)(1<<10))
+
+/*********************************************************************//**
+ * Macro defines for CAN Bus Timing Register
+ **********************************************************************/
+/** CAN Baudrate Prescaler */
+#define CAN_BTR_BRP(n) ((uint32_t)(n&0x3FF))
+/** CAN Synchronization Jump Width */
+#define CAN_BTR_SJM(n) ((uint32_t)((n&0x3)<<14))
+/** CAN Time Segment 1 */
+#define CAN_BTR_TESG1(n) ((uint32_t)(n&0xF)<<16))
+/** CAN Time Segment 2 */
+#define CAN_BTR_TESG2(n) ((uint32_t)(n&0xF)<<20))
+/** CAN Sampling */
+#define CAN_BTR_SAM(n) ((uint32_t)(1<<23))
+
+/*********************************************************************//**
+ * Macro defines for CAN Error Warning Limit Register
+ **********************************************************************/
+/** CAN Error Warning Limit */
+#define CAN_EWL_EWL(n) ((uint32_t)(n&0xFF))
+
+/*********************************************************************//**
+ * Macro defines for CAN Status Register
+ **********************************************************************/
+/** CAN Receive Buffer Status */
+#define CAN_SR_RBS ((uint32_t)(1))
+/** CAN Data Overrun Status */
+#define CAN_SR_DOS ((uint32_t)(1<<1))
+/** CAN Transmit Buffer Status 1 */
+#define CAN_SR_TBS1 ((uint32_t)(1<<2))
+/** CAN Transmission Complete Status of Buffer 1 */
+#define CAN_SR_TCS1 ((uint32_t)(1<<3))
+/** CAN Receive Status */
+#define CAN_SR_RS ((uint32_t)(1<<4))
+/** CAN Transmit Status 1 */
+#define CAN_SR_TS1 ((uint32_t)(1<<5))
+/** CAN Error Status */
+#define CAN_SR_ES ((uint32_t)(1<<6))
+/** CAN Bus Status */
+#define CAN_SR_BS ((uint32_t)(1<<7))
+/** CAN Transmit Buffer Status 2 */
+#define CAN_SR_TBS2 ((uint32_t)(1<<10))
+/** CAN Transmission Complete Status of Buffer 2 */
+#define CAN_SR_TCS2 ((uint32_t)(1<<11))
+/** CAN Transmit Status 2 */
+#define CAN_SR_TS2 ((uint32_t)(1<<13))
+/** CAN Transmit Buffer Status 2 */
+#define CAN_SR_TBS3 ((uint32_t)(1<<18))
+/** CAN Transmission Complete Status of Buffer 2 */
+#define CAN_SR_TCS3 ((uint32_t)(1<<19))
+/** CAN Transmit Status 2 */
+#define CAN_SR_TS3 ((uint32_t)(1<<21))
+
+/*********************************************************************//**
+ * Macro defines for CAN Receive Frame Status Register
+ **********************************************************************/
+/** CAN ID Index */
+#define CAN_RFS_ID_INDEX(n) ((uint32_t)(n&0x3FF))
+/** CAN Bypass */
+#define CAN_RFS_BP ((uint32_t)(1<<10))
+/** CAN Data Length Code */
+#define CAN_RFS_DLC(n) ((uint32_t)((n&0xF)<<16)
+/** CAN Remote Transmission Request */
+#define CAN_RFS_RTR ((uint32_t)(1<<30))
+/** CAN control 11 bit or 29 bit Identifier */
+#define CAN_RFS_FF ((uint32_t)(1<<31))
+
+/*********************************************************************//**
+ * Macro defines for CAN Receive Identifier Register
+ **********************************************************************/
+/** CAN 11 bit Identifier */
+#define CAN_RID_ID_11(n) ((uint32_t)(n&0x7FF))
+/** CAN 29 bit Identifier */
+#define CAN_RID_ID_29(n) ((uint32_t)(n&0x1FFFFFFF))
+
+/*********************************************************************//**
+ * Macro defines for CAN Receive Data A Register
+ **********************************************************************/
+/** CAN Receive Data 1 */
+#define CAN_RDA_DATA1(n) ((uint32_t)(n&0xFF))
+/** CAN Receive Data 2 */
+#define CAN_RDA_DATA2(n) ((uint32_t)((n&0xFF)<<8))
+/** CAN Receive Data 3 */
+#define CAN_RDA_DATA3(n) ((uint32_t)((n&0xFF)<<16))
+/** CAN Receive Data 4 */
+#define CAN_RDA_DATA4(n) ((uint32_t)((n&0xFF)<<24))
+
+/*********************************************************************//**
+ * Macro defines for CAN Receive Data B Register
+ **********************************************************************/
+/** CAN Receive Data 5 */
+#define CAN_RDB_DATA5(n) ((uint32_t)(n&0xFF))
+/** CAN Receive Data 6 */
+#define CAN_RDB_DATA6(n) ((uint32_t)((n&0xFF)<<8))
+/** CAN Receive Data 7 */
+#define CAN_RDB_DATA7(n) ((uint32_t)((n&0xFF)<<16))
+/** CAN Receive Data 8 */
+#define CAN_RDB_DATA8(n) ((uint32_t)((n&0xFF)<<24))
+
+/*********************************************************************//**
+ * Macro defines for CAN Transmit Frame Information Register
+ **********************************************************************/
+/** CAN Priority */
+#define CAN_TFI_PRIO(n) ((uint32_t)(n&0xFF))
+/** CAN Data Length Code */
+#define CAN_TFI_DLC(n) ((uint32_t)((n&0xF)<<16))
+/** CAN Remote Frame Transmission */
+#define CAN_TFI_RTR ((uint32_t)(1<<30))
+/** CAN control 11-bit or 29-bit Identifier */
+#define CAN_TFI_FF ((uint32_t)(1<<31))
+
+/*********************************************************************//**
+ * Macro defines for CAN Transmit Identifier Register
+ **********************************************************************/
+/** CAN 11-bit Identifier */
+#define CAN_TID_ID11(n) ((uint32_t)(n&0x7FF))
+/** CAN 11-bit Identifier */
+#define CAN_TID_ID29(n) ((uint32_t)(n&0x1FFFFFFF))
+
+/*********************************************************************//**
+ * Macro defines for CAN Transmit Data A Register
+ **********************************************************************/
+/** CAN Transmit Data 1 */
+#define CAN_TDA_DATA1(n) ((uint32_t)(n&0xFF))
+/** CAN Transmit Data 2 */
+#define CAN_TDA_DATA2(n) ((uint32_t)((n&0xFF)<<8))
+/** CAN Transmit Data 3 */
+#define CAN_TDA_DATA3(n) ((uint32_t)((n&0xFF)<<16))
+/** CAN Transmit Data 4 */
+#define CAN_TDA_DATA4(n) ((uint32_t)((n&0xFF)<<24))
+
+/*********************************************************************//**
+ * Macro defines for CAN Transmit Data B Register
+ **********************************************************************/
+/** CAN Transmit Data 5 */
+#define CAN_TDA_DATA5(n) ((uint32_t)(n&0xFF))
+/** CAN Transmit Data 6 */
+#define CAN_TDA_DATA6(n) ((uint32_t)((n&0xFF)<<8))
+/** CAN Transmit Data 7 */
+#define CAN_TDA_DATA7(n) ((uint32_t)((n&0xFF)<<16))
+/** CAN Transmit Data 8 */
+#define CAN_TDA_DATA8(n) ((uint32_t)((n&0xFF)<<24))
+
+/*********************************************************************//**
+ * Macro defines for CAN Sleep Clear Register
+ **********************************************************************/
+/** CAN1 Sleep mode */
+#define CAN1SLEEPCLR ((uint32_t)(1<<1))
+/** CAN2 Sleep Mode */
+#define CAN2SLEEPCLR ((uint32_t)(1<<2))
+
+/*********************************************************************//**
+ * Macro defines for CAN Wake up Flags Register
+ **********************************************************************/
+/** CAN1 Sleep mode */
+#define CAN_WAKEFLAGES_CAN1WAKE ((uint32_t)(1<<1))
+/** CAN2 Sleep Mode */
+#define CAN_WAKEFLAGES_CAN2WAKE ((uint32_t)(1<<2))
+
+/*********************************************************************//**
+ * Macro defines for Central transmit Status Register
+ **********************************************************************/
+/** CAN Transmit 1 */
+#define CAN_TSR_TS1 ((uint32_t)(1))
+/** CAN Transmit 2 */
+#define CAN_TSR_TS2 ((uint32_t)(1<<1))
+/** CAN Transmit Buffer Status 1 */
+#define CAN_TSR_TBS1 ((uint32_t)(1<<8))
+/** CAN Transmit Buffer Status 2 */
+#define CAN_TSR_TBS2 ((uint32_t)(1<<9))
+/** CAN Transmission Complete Status 1 */
+#define CAN_TSR_TCS1 ((uint32_t)(1<<16))
+/** CAN Transmission Complete Status 2 */
+#define CAN_TSR_TCS2 ((uint32_t)(1<<17))
+
+/*********************************************************************//**
+ * Macro defines for Central Receive Status Register
+ **********************************************************************/
+/** CAN Receive Status 1 */
+#define CAN_RSR_RS1 ((uint32_t)(1))
+/** CAN Receive Status 1 */
+#define CAN_RSR_RS2 ((uint32_t)(1<<1))
+/** CAN Receive Buffer Status 1*/
+#define CAN_RSR_RB1 ((uint32_t)(1<<8))
+/** CAN Receive Buffer Status 2*/
+#define CAN_RSR_RB2 ((uint32_t)(1<<9))
+/** CAN Data Overrun Status 1 */
+#define CAN_RSR_DOS1 ((uint32_t)(1<<16))
+/** CAN Data Overrun Status 1 */
+#define CAN_RSR_DOS2 ((uint32_t)(1<<17))
+
+/*********************************************************************//**
+ * Macro defines for Central Miscellaneous Status Register
+ **********************************************************************/
+/** Same CAN Error Status in CAN1GSR */
+#define CAN_MSR_E1 ((uint32_t)(1))
+/** Same CAN Error Status in CAN2GSR */
+#define CAN_MSR_E2 ((uint32_t)(1<<1))
+/** Same CAN Bus Status in CAN1GSR */
+#define CAN_MSR_BS1 ((uint32_t)(1<<8))
+/** Same CAN Bus Status in CAN2GSR */
+#define CAN_MSR_BS2 ((uint32_t)(1<<9))
+
+/*********************************************************************//**
+ * Macro defines for Acceptance Filter Mode Register
+ **********************************************************************/
+/** CAN Acceptance Filter Off mode */
+#define CAN_AFMR_AccOff ((uint32_t)(1))
+/** CAN Acceptance File Bypass mode */
+#define CAN_AFMR_AccBP ((uint32_t)(1<<1))
+/** FullCAN Mode Enhancements */
+#define CAN_AFMR_eFCAN ((uint32_t)(1<<2))
+
+/*********************************************************************//**
+ * Macro defines for Standard Frame Individual Start Address Register
+ **********************************************************************/
+/** The start address of the table of individual Standard Identifier */
+#define CAN_STT_sa(n) ((uint32_t)((n&1FF)<<2))
+
+/*********************************************************************//**
+ * Macro defines for Standard Frame Group Start Address Register
+ **********************************************************************/
+/** The start address of the table of grouped Standard Identifier */
+#define CAN_SFF_GRP_sa(n) ((uint32_t)((n&3FF)<<2))
+
+/*********************************************************************//**
+ * Macro defines for Extended Frame Start Address Register
+ **********************************************************************/
+/** The start address of the table of individual Extended Identifier */
+#define CAN_EFF_sa(n) ((uint32_t)((n&1FF)<<2))
+
+/*********************************************************************//**
+ * Macro defines for Extended Frame Group Start Address Register
+ **********************************************************************/
+/** The start address of the table of grouped Extended Identifier */
+#define CAN_Eff_GRP_sa(n) ((uint32_t)((n&3FF)<<2))
+
+/*********************************************************************//**
+ * Macro defines for End Of AF Table Register
+ **********************************************************************/
+/** The End of Table of AF LookUp Table */
+#define CAN_EndofTable(n) ((uint32_t)((n&3FF)<<2))
+
+/*********************************************************************//**
+ * Macro defines for LUT Error Address Register
+ **********************************************************************/
+/** CAN Look-Up Table Error Address */
+#define CAN_LUTerrAd(n) ((uint32_t)((n&1FF)<<2))
+
+/*********************************************************************//**
+ * Macro defines for LUT Error Register
+ **********************************************************************/
+/** CAN Look-Up Table Error */
+#define CAN_LUTerr ((uint32_t)(1))
+
+/*********************************************************************//**
+ * Macro defines for Global FullCANInterrupt Enable Register
+ **********************************************************************/
+/** Global FullCANInterrupt Enable */
+#define CAN_FCANIE ((uint32_t)(1))
+
+/*********************************************************************//**
+ * Macro defines for FullCAN Interrupt and Capture Register 0
+ **********************************************************************/
+/** FullCAN Interrupt and Capture (0-31)*/
+#define CAN_FCANIC0_IntPnd(n) ((uint32_t)(1<<n))
+
+/*********************************************************************//**
+ * Macro defines for FullCAN Interrupt and Capture Register 1
+ **********************************************************************/
+/** FullCAN Interrupt and Capture (0-31)*/
+#define CAN_FCANIC1_IntPnd(n) ((uint32_t)(1<<(n-32)))
+
+
+/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
+/** Macro to determine if it is valid CAN peripheral or not */
+#define PARAM_CANx(x) ((((uint32_t*)x)==((uint32_t *)LPC_CAN1)) \
+||(((uint32_t*)x)==((uint32_t *)LPC_CAN2)))
+
+/* Macro to determine if it is valid CANAF or not*/
+#define PARAM_CANAFx(x) (((uint32_t*)x)== ((uint32_t*)LPC_CANAF))
+
+/* Macro to determine if it is valid CANAF RAM or not*/
+#define PARAM_CANAFRAMx(x) (((uint32_t*)x)== (uint32_t*)LPC_CANAF_RAM)
+
+/* Macro to determine if it is valid CANCR or not*/
+#define PARAM_CANCRx(x) (((uint32_t*)x)==((uint32_t*)LPC_CANCR))
+
+/** Macro to check Data to send valid */
+#define PARAM_I2S_DATA(data) ((data>=0)&&(data <= 0xFFFFFFFF))
+
+/** Macro to check frequency value */
+#define PRAM_I2S_FREQ(freq) ((freq>=16000)&&(freq <= 96000))
+
+/** Macro to check Frame Identifier */
+#define PARAM_ID_11(n) ((n>>11)==0) /*-- 11 bit --*/
+#define PARAM_ID_29(n) ((n>>29)==0) /*-- 29 bit --*/
+
+/** Macro to check DLC value */
+#define PARAM_DLC(n) ((n>>4)==0) /*-- 4 bit --*/
+/** Macro to check ID format type */
+#define PARAM_ID_FORMAT(n) ((n==STD_ID_FORMAT)||(n==EXT_ID_FORMAT))
+
+/** Macro to check Group identifier */
+#define PARAM_GRP_ID(x, y) ((x<=y))
+
+/** Macro to check Frame type */
+#define PARAM_FRAME_TYPE(n) ((n==DATA_FRAME)||(n==REMOTE_FRAME))
+
+/** Macro to check Control/Central Status type parameter */
+#define PARAM_CTRL_STS_TYPE(n) ((n==CANCTRL_GLOBAL_STS)||(n==CANCTRL_INT_CAP) \
+||(n==CANCTRL_ERR_WRN)||(n==CANCTRL_STS))
+
+/** Macro to check CR status type */
+#define PARAM_CR_STS_TYPE(n) ((n==CANCR_TX_STS)||(n==CANCR_RX_STS) \
+||(n==CANCR_MS))
+/** Macro to check AF Mode type parameter */
+#define PARAM_AFMODE_TYPE(n) ((n==CAN_Normal)||(n==CAN_AccOff) \
+||(n==CAN_AccBP)||(n==CAN_eFCAN))
+
+/** Macro to check Operation Mode */
+#define PARAM_MODE_TYPE(n) ((n==CAN_OPERATING_MODE)||(n==CAN_RESET_MODE) \
+||(n==CAN_LISTENONLY_MODE)||(n==CAN_SELFTEST_MODE) \
+||(n==CAN_TXPRIORITY_MODE)||(n==CAN_SLEEP_MODE) \
+||(n==CAN_RXPOLARITY_MODE)||(n==CAN_TEST_MODE))
+
+/** Macro define for struct AF_Section parameter */
+#define PARAM_CTRL(n) ((n==CAN1_CTRL)|(n==CAN2_CTRL))
+
+/** Macro define for struct AF_Section parameter */
+#define PARAM_MSG_DISABLE(n) ((n==MSG_ENABLE)|(n==MSG_DISABLE))
+
+/**Macro to check Interrupt Type parameter */
+#define PARAM_INT_EN_TYPE(n) ((n==CANINT_RIE)||(n==CANINT_TIE1) \
+||(n==CANINT_EIE)||(n==CANINT_DOIE) \
+||(n==CANINT_WUIE)||(n==CANINT_EPIE) \
+||(n==CANINT_ALIE)||(n==CANINT_BEIE) \
+||(n==CANINT_IDIE)||(n==CANINT_TIE2) \
+||(n==CANINT_TIE3)||(n==CANINT_FCE))
+
+/** Macro to check AFLUT Entry type */
+#define PARAM_AFLUT_ENTRY_TYPE(n) ((n==FULLCAN_ENTRY)||(n==EXPLICIT_STANDARD_ENTRY)\
+||(n==GROUP_STANDARD_ENTRY)||(n==EXPLICIT_EXTEND_ENTRY) \
+||(n==GROUP_EXTEND_ENTRY))
+
+/** Macro to check position */
+#define PARAM_POSITION(n) (n<512)
+
+/**
+ * @}
+ */
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup CAN_Public_Types CAN Public Types
+ * @{
+ */
+
+/** CAN configuration structure */
+/***********************************************************************
+ * CAN device configuration commands (IOCTL commands and arguments)
+ **********************************************************************/
+/**
+ * @brief CAN ID format definition
+ */
+typedef enum {
+ STD_ID_FORMAT = 0, /**< Use standard ID format (11 bit ID) */
+ EXT_ID_FORMAT = 1 /**< Use extended ID format (29 bit ID) */
+} CAN_ID_FORMAT_Type;
+
+/**
+ * @brief AFLUT Entry type definition
+ */
+typedef enum {
+ FULLCAN_ENTRY = 0,
+ EXPLICIT_STANDARD_ENTRY,
+ GROUP_STANDARD_ENTRY,
+ EXPLICIT_EXTEND_ENTRY,
+ GROUP_EXTEND_ENTRY
+} AFLUT_ENTRY_Type;
+
+/**
+ * @brief Symbolic names for type of CAN message
+ */
+typedef enum {
+ DATA_FRAME = 0, /**< Data frame */
+ REMOTE_FRAME = 1 /**< Remote frame */
+} CAN_FRAME_Type;
+
+/**
+ * @brief CAN Control status definition
+ */
+typedef enum {
+ CANCTRL_GLOBAL_STS = 0, /**< CAN Global Status */
+ CANCTRL_INT_CAP, /**< CAN Interrupt and Capture */
+ CANCTRL_ERR_WRN, /**< CAN Error Warning Limit */
+ CANCTRL_STS /**< CAN Control Status */
+} CAN_CTRL_STS_Type;
+
+/**
+ * @brief Central CAN status type definition
+ */
+typedef enum {
+ CANCR_TX_STS = 0, /**< Central CAN Tx Status */
+ CANCR_RX_STS, /**< Central CAN Rx Status */
+ CANCR_MS /**< Central CAN Miscellaneous Status */
+} CAN_CR_STS_Type;
+
+/**
+ * @brief FullCAN Interrupt Capture type definition
+ */
+typedef enum{
+ FULLCAN_IC0, /**< FullCAN Interrupt and Capture 0 */
+ FULLCAN_IC1 /**< FullCAN Interrupt and Capture 1 */
+}FullCAN_IC_Type;
+
+/**
+ * @brief CAN interrupt enable type definition
+ */
+typedef enum {
+ CANINT_RIE = 0, /**< CAN Receiver Interrupt Enable */
+ CANINT_TIE1, /**< CAN Transmit Interrupt Enable */
+ CANINT_EIE, /**< CAN Error Warning Interrupt Enable */
+ CANINT_DOIE, /**< CAN Data Overrun Interrupt Enable */
+ CANINT_WUIE, /**< CAN Wake-Up Interrupt Enable */
+ CANINT_EPIE, /**< CAN Error Passive Interrupt Enable */
+ CANINT_ALIE, /**< CAN Arbitration Lost Interrupt Enable */
+ CANINT_BEIE, /**< CAN Bus Error Inter rupt Enable */
+ CANINT_IDIE, /**< CAN ID Ready Interrupt Enable */
+ CANINT_TIE2, /**< CAN Transmit Interrupt Enable for Buffer2 */
+ CANINT_TIE3, /**< CAN Transmit Interrupt Enable for Buffer3 */
+ CANINT_FCE /**< FullCAN Interrupt Enable */
+} CAN_INT_EN_Type;
+
+/**
+ * @brief Acceptance Filter Mode type definition
+ */
+typedef enum {
+ CAN_Normal = 0, /**< Normal Mode */
+ CAN_AccOff, /**< Acceptance Filter Off Mode */
+ CAN_AccBP, /**< Acceptance Fileter Bypass Mode */
+ CAN_eFCAN /**< FullCAN Mode Enhancement */
+} CAN_AFMODE_Type;
+
+/**
+ * @brief CAN Mode Type definition
+ */
+typedef enum {
+ CAN_OPERATING_MODE = 0, /**< Operating Mode */
+ CAN_RESET_MODE, /**< Reset Mode */
+ CAN_LISTENONLY_MODE, /**< Listen Only Mode */
+ CAN_SELFTEST_MODE, /**< Seft Test Mode */
+ CAN_TXPRIORITY_MODE, /**< Transmit Priority Mode */
+ CAN_SLEEP_MODE, /**< Sleep Mode */
+ CAN_RXPOLARITY_MODE, /**< Receive Polarity Mode */
+ CAN_TEST_MODE /**< Test Mode */
+} CAN_MODE_Type;
+
+/**
+ * @brief Error values that functions can return
+ */
+typedef enum {
+ CAN_OK = 1, /**< No error */
+ CAN_OBJECTS_FULL_ERROR, /**< No more rx or tx objects available */
+ CAN_FULL_OBJ_NOT_RCV, /**< Full CAN object not received */
+ CAN_NO_RECEIVE_DATA, /**< No have receive data available */
+ CAN_AF_ENTRY_ERROR, /**< Entry load in AFLUT is unvalid */
+ CAN_CONFLICT_ID_ERROR, /**< Conflict ID occur */
+ CAN_ENTRY_NOT_EXIT_ERROR /**< Entry remove outo AFLUT is not exit */
+} CAN_ERROR;
+
+/**
+ * @brief Pin Configuration structure
+ */
+typedef struct {
+ uint8_t RD; /**< Serial Inputs, from CAN transceivers, should be:
+ ** For CAN1:
+ - CAN_RD1_P0_0: RD pin is on P0.0
+ - CAN_RD1_P0_21 : RD pin is on P0.21
+ ** For CAN2:
+ - CAN_RD2_P0_4: RD pin is on P0.4
+ - CAN_RD2_P2_7: RD pin is on P2.7
+ */
+ uint8_t TD; /**< Serial Outputs, To CAN transceivers, should be:
+ ** For CAN1:
+ - CAN_TD1_P0_1: TD pin is on P0.1
+ - CAN_TD1_P0_22: TD pin is on P0.22
+ ** For CAN2:
+ - CAN_TD2_P0_5: TD pin is on P0.5
+ - CAN_TD2_P2_8: TD pin is on P2.8
+ */
+} CAN_PinCFG_Type;
+
+/**
+ * @brief CAN message object structure
+ */
+typedef struct {
+ uint32_t id; /**< 29 bit identifier, it depend on "format" value
+ - if format = STD_ID_FORMAT, id should be 11 bit identifier
+ - if format = EXT_ID_FORMAT, id should be 29 bit identifier
+ */
+ uint8_t dataA[4]; /**< Data field A */
+ uint8_t dataB[4]; /**< Data field B */
+ uint8_t len; /**< Length of data field in bytes, should be:
+ - 0000b-0111b: 0-7 bytes
+ - 1xxxb: 8 bytes
+ */
+ uint8_t format; /**< Identifier Format, should be:
+ - STD_ID_FORMAT: Standard ID - 11 bit format
+ - EXT_ID_FORMAT: Extended ID - 29 bit format
+ */
+ uint8_t type; /**< Remote Frame transmission, should be:
+ - DATA_FRAME: the number of data bytes called out by the DLC
+ field are send from the CANxTDA and CANxTDB registers
+ - REMOTE_FRAME: Remote Frame is sent
+ */
+} CAN_MSG_Type;
+
+/**
+ * @brief FullCAN Entry structure
+ */
+typedef struct {
+ uint8_t controller; /**< CAN Controller, should be:
+ - CAN1_CTRL: CAN1 Controller
+ - CAN2_CTRL: CAN2 Controller
+ */
+ uint8_t disable; /**< Disable bit, should be:
+ - MSG_ENABLE: disable bit = 0
+ - MSG_DISABLE: disable bit = 1
+ */
+ uint16_t id_11; /**< Standard ID, should be 11-bit value */
+} FullCAN_Entry;
+
+/**
+ * @brief Standard ID Frame Format Entry structure
+ */
+typedef struct {
+ uint8_t controller; /**< CAN Controller, should be:
+ - CAN1_CTRL: CAN1 Controller
+ - CAN2_CTRL: CAN2 Controller
+ */
+ uint8_t disable; /**< Disable bit, should be:
+ - MSG_ENABLE: disable bit = 0
+ - MSG_DISABLE: disable bit = 1
+ */
+ uint16_t id_11; /**< Standard ID, should be 11-bit value */
+} SFF_Entry;
+
+/**
+ * @brief Group of Standard ID Frame Format Entry structure
+ */
+typedef struct {
+ uint8_t controller1; /**< First CAN Controller, should be:
+ - CAN1_CTRL: CAN1 Controller
+ - CAN2_CTRL: CAN2 Controller
+ */
+ uint8_t disable1; /**< First Disable bit, should be:
+ - MSG_ENABLE: disable bit = 0)
+ - MSG_DISABLE: disable bit = 1
+ */
+ uint16_t lowerID; /**< ID lower bound, should be 11-bit value */
+ uint8_t controller2; /**< Second CAN Controller, should be:
+ - CAN1_CTRL: CAN1 Controller
+ - CAN2_CTRL: CAN2 Controller
+ */
+ uint8_t disable2; /**< Second Disable bit, should be:
+ - MSG_ENABLE: disable bit = 0
+ - MSG_DISABLE: disable bit = 1
+ */
+ uint16_t upperID; /**< ID upper bound, should be 11-bit value and
+ equal or greater than lowerID
+ */
+} SFF_GPR_Entry;
+
+/**
+ * @brief Extended ID Frame Format Entry structure
+ */
+typedef struct {
+ uint8_t controller; /**< CAN Controller, should be:
+ - CAN1_CTRL: CAN1 Controller
+ - CAN2_CTRL: CAN2 Controller
+ */
+ uint32_t ID_29; /**< Extend ID, shoud be 29-bit value */
+} EFF_Entry;
+
+
+/**
+ * @brief Group of Extended ID Frame Format Entry structure
+ */
+typedef struct {
+ uint8_t controller1; /**< First CAN Controller, should be:
+ - CAN1_CTRL: CAN1 Controller
+ - CAN2_CTRL: CAN2 Controller
+ */
+ uint8_t controller2; /**< Second Disable bit, should be:
+ - MSG_ENABLE: disable bit = 0(default)
+ - MSG_DISABLE: disable bit = 1
+ */
+ uint32_t lowerEID; /**< Extended ID lower bound, should be 29-bit value */
+ uint32_t upperEID; /**< Extended ID upper bound, should be 29-bit value */
+} EFF_GPR_Entry;
+
+
+/**
+ * @brief Acceptance Filter Section Table structure
+ */
+typedef struct {
+ FullCAN_Entry* FullCAN_Sec; /**< The pointer point to FullCAN_Entry */
+ uint8_t FC_NumEntry; /**< FullCAN Entry Number */
+ SFF_Entry* SFF_Sec; /**< The pointer point to SFF_Entry */
+ uint8_t SFF_NumEntry; /**< Standard ID Entry Number */
+ SFF_GPR_Entry* SFF_GPR_Sec; /**< The pointer point to SFF_GPR_Entry */
+ uint8_t SFF_GPR_NumEntry; /**< Group Standard ID Entry Number */
+ EFF_Entry* EFF_Sec; /**< The pointer point to EFF_Entry */
+ uint8_t EFF_NumEntry; /**< Extended ID Entry Number */
+ EFF_GPR_Entry* EFF_GPR_Sec; /**< The pointer point to EFF_GPR_Entry */
+ uint8_t EFF_GPR_NumEntry; /**< Group Extended ID Entry Number */
+} AF_SectionDef;
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup CAN_Public_Functions CAN Public Functions
+ * @{
+ */
+
+/* Init/DeInit CAN peripheral -----------*/
+void CAN_Init(LPC_CAN_TypeDef *CANx, uint32_t baudrate);
+void CAN_DeInit(LPC_CAN_TypeDef *CANx);
+
+/* CAN messages functions ---------------*/
+Status CAN_SendMsg(LPC_CAN_TypeDef *CANx, CAN_MSG_Type *CAN_Msg);
+Status CAN_ReceiveMsg(LPC_CAN_TypeDef *CANx, CAN_MSG_Type *CAN_Msg);
+CAN_ERROR FCAN_ReadObj(LPC_CANAF_TypeDef* CANAFx, CAN_MSG_Type *CAN_Msg);
+
+/* CAN configure functions ---------------*/
+void CAN_ModeConfig(LPC_CAN_TypeDef* CANx, CAN_MODE_Type mode,
+ FunctionalState NewState);
+void CAN_SetAFMode(LPC_CANAF_TypeDef* CANAFx, CAN_AFMODE_Type AFmode);
+void CAN_SetCommand(LPC_CAN_TypeDef* CANx, uint32_t CMRType);
+
+/* AFLUT functions ---------------------- */
+CAN_ERROR CAN_SetupAFLUT(LPC_CANAF_TypeDef* CANAFx, AF_SectionDef* AFSection);
+CAN_ERROR CAN_LoadFullCANEntry(LPC_CAN_TypeDef* CANx, uint16_t ID);
+CAN_ERROR CAN_LoadExplicitEntry(LPC_CAN_TypeDef* CANx, uint32_t ID,
+ CAN_ID_FORMAT_Type format);
+CAN_ERROR CAN_LoadGroupEntry(LPC_CAN_TypeDef* CANx, uint32_t lowerID,
+ uint32_t upperID, CAN_ID_FORMAT_Type format);
+CAN_ERROR CAN_RemoveEntry(AFLUT_ENTRY_Type EntryType, uint16_t position);
+
+/* CAN interrupt functions -----------------*/
+void CAN_IRQCmd(LPC_CAN_TypeDef* CANx, CAN_INT_EN_Type arg, FunctionalState NewState);
+uint32_t CAN_IntGetStatus(LPC_CAN_TypeDef* CANx);
+
+/* CAN get status functions ----------------*/
+IntStatus CAN_FullCANIntGetStatus (LPC_CANAF_TypeDef* CANAFx);
+uint32_t CAN_FullCANPendGetStatus (LPC_CANAF_TypeDef* CANAFx, FullCAN_IC_Type type);
+uint32_t CAN_GetCTRLStatus(LPC_CAN_TypeDef* CANx, CAN_CTRL_STS_Type arg);
+uint32_t CAN_GetCRStatus(LPC_CANCR_TypeDef* CANCRx, CAN_CR_STS_Type arg);
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC17XX_CAN_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/src/shared/cmsis/Drivers/include/lpc17xx_clkpwr.h b/src/shared/cmsis/Drivers/include/lpc17xx_clkpwr.h
@@ -0,0 +1,406 @@
+/**********************************************************************
+* $Id$ lpc17xx_clkpwr.h 2010-05-21
+*//**
+* @file lpc17xx_clkpwr.h
+* @brief Contains all macro definitions and function prototypes
+* support for Clock and Power Control firmware library on LPC17xx
+* @version 2.0
+* @date 21. May. 2010
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2010, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup CLKPWR CLKPWR (Clock Power)
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_CLKPWR_H_
+#define LPC17XX_CLKPWR_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup CLKPWR_Public_Macros CLKPWR Public Macros
+ * @{
+ */
+
+/**********************************************************************
+ * Peripheral Clock Selection Definitions
+ **********************************************************************/
+/** Peripheral clock divider bit position for WDT */
+#define CLKPWR_PCLKSEL_WDT ((uint32_t)(0))
+/** Peripheral clock divider bit position for TIMER0 */
+#define CLKPWR_PCLKSEL_TIMER0 ((uint32_t)(2))
+/** Peripheral clock divider bit position for TIMER1 */
+#define CLKPWR_PCLKSEL_TIMER1 ((uint32_t)(4))
+/** Peripheral clock divider bit position for UART0 */
+#define CLKPWR_PCLKSEL_UART0 ((uint32_t)(6))
+/** Peripheral clock divider bit position for UART1 */
+#define CLKPWR_PCLKSEL_UART1 ((uint32_t)(8))
+/** Peripheral clock divider bit position for PWM1 */
+#define CLKPWR_PCLKSEL_PWM1 ((uint32_t)(12))
+/** Peripheral clock divider bit position for I2C0 */
+#define CLKPWR_PCLKSEL_I2C0 ((uint32_t)(14))
+/** Peripheral clock divider bit position for SPI */
+#define CLKPWR_PCLKSEL_SPI ((uint32_t)(16))
+/** Peripheral clock divider bit position for SSP1 */
+#define CLKPWR_PCLKSEL_SSP1 ((uint32_t)(20))
+/** Peripheral clock divider bit position for DAC */
+#define CLKPWR_PCLKSEL_DAC ((uint32_t)(22))
+/** Peripheral clock divider bit position for ADC */
+#define CLKPWR_PCLKSEL_ADC ((uint32_t)(24))
+/** Peripheral clock divider bit position for CAN1 */
+#define CLKPWR_PCLKSEL_CAN1 ((uint32_t)(26))
+/** Peripheral clock divider bit position for CAN2 */
+#define CLKPWR_PCLKSEL_CAN2 ((uint32_t)(28))
+/** Peripheral clock divider bit position for ACF */
+#define CLKPWR_PCLKSEL_ACF ((uint32_t)(30))
+/** Peripheral clock divider bit position for QEI */
+#define CLKPWR_PCLKSEL_QEI ((uint32_t)(32))
+/** Peripheral clock divider bit position for PCB */
+#define CLKPWR_PCLKSEL_PCB ((uint32_t)(36))
+/** Peripheral clock divider bit position for I2C1 */
+#define CLKPWR_PCLKSEL_I2C1 ((uint32_t)(38))
+/** Peripheral clock divider bit position for SSP0 */
+#define CLKPWR_PCLKSEL_SSP0 ((uint32_t)(42))
+/** Peripheral clock divider bit position for TIMER2 */
+#define CLKPWR_PCLKSEL_TIMER2 ((uint32_t)(44))
+/** Peripheral clock divider bit position for TIMER3 */
+#define CLKPWR_PCLKSEL_TIMER3 ((uint32_t)(46))
+/** Peripheral clock divider bit position for UART2 */
+#define CLKPWR_PCLKSEL_UART2 ((uint32_t)(48))
+/** Peripheral clock divider bit position for UART3 */
+#define CLKPWR_PCLKSEL_UART3 ((uint32_t)(50))
+/** Peripheral clock divider bit position for I2C2 */
+#define CLKPWR_PCLKSEL_I2C2 ((uint32_t)(52))
+/** Peripheral clock divider bit position for I2S */
+#define CLKPWR_PCLKSEL_I2S ((uint32_t)(54))
+/** Peripheral clock divider bit position for RIT */
+#define CLKPWR_PCLKSEL_RIT ((uint32_t)(58))
+/** Peripheral clock divider bit position for SYSCON */
+#define CLKPWR_PCLKSEL_SYSCON ((uint32_t)(60))
+/** Peripheral clock divider bit position for MC */
+#define CLKPWR_PCLKSEL_MC ((uint32_t)(62))
+
+/** Macro for Peripheral Clock Selection register bit values
+ * Note: When CCLK_DIV_8, Peripheral’s clock is selected to
+ * PCLK_xyz = CCLK/8 except for CAN1, CAN2, and CAN filtering
+ * when ’11’selects PCLK_xyz = CCLK/6 */
+/* Peripheral clock divider is set to 4 from CCLK */
+#define CLKPWR_PCLKSEL_CCLK_DIV_4 ((uint32_t)(0))
+/** Peripheral clock divider is the same with CCLK */
+#define CLKPWR_PCLKSEL_CCLK_DIV_1 ((uint32_t)(1))
+/** Peripheral clock divider is set to 2 from CCLK */
+#define CLKPWR_PCLKSEL_CCLK_DIV_2 ((uint32_t)(2))
+
+
+/********************************************************************
+* Power Control for Peripherals Definitions
+**********************************************************************/
+/** Timer/Counter 0 power/clock control bit */
+#define CLKPWR_PCONP_PCTIM0 ((uint32_t)(1<<1))
+/* Timer/Counter 1 power/clock control bit */
+#define CLKPWR_PCONP_PCTIM1 ((uint32_t)(1<<2))
+/** UART0 power/clock control bit */
+#define CLKPWR_PCONP_PCUART0 ((uint32_t)(1<<3))
+/** UART1 power/clock control bit */
+#define CLKPWR_PCONP_PCUART1 ((uint32_t)(1<<4))
+/** PWM1 power/clock control bit */
+#define CLKPWR_PCONP_PCPWM1 ((uint32_t)(1<<6))
+/** The I2C0 interface power/clock control bit */
+#define CLKPWR_PCONP_PCI2C0 ((uint32_t)(1<<7))
+/** The SPI interface power/clock control bit */
+#define CLKPWR_PCONP_PCSPI ((uint32_t)(1<<8))
+/** The RTC power/clock control bit */
+#define CLKPWR_PCONP_PCRTC ((uint32_t)(1<<9))
+/** The SSP1 interface power/clock control bit */
+#define CLKPWR_PCONP_PCSSP1 ((uint32_t)(1<<10))
+/** A/D converter 0 (ADC0) power/clock control bit */
+#define CLKPWR_PCONP_PCAD ((uint32_t)(1<<12))
+/** CAN Controller 1 power/clock control bit */
+#define CLKPWR_PCONP_PCAN1 ((uint32_t)(1<<13))
+/** CAN Controller 2 power/clock control bit */
+#define CLKPWR_PCONP_PCAN2 ((uint32_t)(1<<14))
+/** GPIO power/clock control bit */
+#define CLKPWR_PCONP_PCGPIO ((uint32_t)(1<<15))
+/** Repetitive Interrupt Timer power/clock control bit */
+#define CLKPWR_PCONP_PCRIT ((uint32_t)(1<<16))
+/** Motor Control PWM */
+#define CLKPWR_PCONP_PCMC ((uint32_t)(1<<17))
+/** Quadrature Encoder Interface power/clock control bit */
+#define CLKPWR_PCONP_PCQEI ((uint32_t)(1<<18))
+/** The I2C1 interface power/clock control bit */
+#define CLKPWR_PCONP_PCI2C1 ((uint32_t)(1<<19))
+/** The SSP0 interface power/clock control bit */
+#define CLKPWR_PCONP_PCSSP0 ((uint32_t)(1<<21))
+/** Timer 2 power/clock control bit */
+#define CLKPWR_PCONP_PCTIM2 ((uint32_t)(1<<22))
+/** Timer 3 power/clock control bit */
+#define CLKPWR_PCONP_PCTIM3 ((uint32_t)(1<<23))
+/** UART 2 power/clock control bit */
+#define CLKPWR_PCONP_PCUART2 ((uint32_t)(1<<24))
+/** UART 3 power/clock control bit */
+#define CLKPWR_PCONP_PCUART3 ((uint32_t)(1<<25))
+/** I2C interface 2 power/clock control bit */
+#define CLKPWR_PCONP_PCI2C2 ((uint32_t)(1<<26))
+/** I2S interface power/clock control bit*/
+#define CLKPWR_PCONP_PCI2S ((uint32_t)(1<<27))
+/** GP DMA function power/clock control bit*/
+#define CLKPWR_PCONP_PCGPDMA ((uint32_t)(1<<29))
+/** Ethernet block power/clock control bit*/
+#define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30))
+/** USB interface power/clock control bit*/
+#define CLKPWR_PCONP_PCUSB ((uint32_t)(1<<31))
+
+
+/**
+ * @}
+ */
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup CLKPWR_Private_Macros CLKPWR Private Macros
+ * @{
+ */
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/*********************************************************************//**
+ * Macro defines for Clock Source Select Register
+ **********************************************************************/
+/** Internal RC oscillator */
+#define CLKPWR_CLKSRCSEL_CLKSRC_IRC ((uint32_t)(0x00))
+/** Main oscillator */
+#define CLKPWR_CLKSRCSEL_CLKSRC_MAINOSC ((uint32_t)(0x01))
+/** RTC oscillator */
+#define CLKPWR_CLKSRCSEL_CLKSRC_RTC ((uint32_t)(0x02))
+/** Clock source selection bit mask */
+#define CLKPWR_CLKSRCSEL_BITMASK ((uint32_t)(0x03))
+
+/*********************************************************************//**
+ * Macro defines for Clock Output Configuration Register
+ **********************************************************************/
+/* Clock Output Configuration register definition */
+/** Selects the CPU clock as the CLKOUT source */
+#define CLKPWR_CLKOUTCFG_CLKOUTSEL_CPU ((uint32_t)(0x00))
+/** Selects the main oscillator as the CLKOUT source */
+#define CLKPWR_CLKOUTCFG_CLKOUTSEL_MAINOSC ((uint32_t)(0x01))
+/** Selects the Internal RC oscillator as the CLKOUT source */
+#define CLKPWR_CLKOUTCFG_CLKOUTSEL_RC ((uint32_t)(0x02))
+/** Selects the USB clock as the CLKOUT source */
+#define CLKPWR_CLKOUTCFG_CLKOUTSEL_USB ((uint32_t)(0x03))
+/** Selects the RTC oscillator as the CLKOUT source */
+#define CLKPWR_CLKOUTCFG_CLKOUTSEL_RTC ((uint32_t)(0x04))
+/** Integer value to divide the output clock by, minus one */
+#define CLKPWR_CLKOUTCFG_CLKOUTDIV(n) ((uint32_t)((n&0x0F)<<4))
+/** CLKOUT enable control */
+#define CLKPWR_CLKOUTCFG_CLKOUT_EN ((uint32_t)(1<<8))
+/** CLKOUT activity indication */
+#define CLKPWR_CLKOUTCFG_CLKOUT_ACT ((uint32_t)(1<<9))
+/** Clock source selection bit mask */
+#define CLKPWR_CLKOUTCFG_BITMASK ((uint32_t)(0x3FF))
+
+/*********************************************************************//**
+ * Macro defines for PPL0 Control Register
+ **********************************************************************/
+/** PLL 0 control enable */
+#define CLKPWR_PLL0CON_ENABLE ((uint32_t)(0x01))
+/** PLL 0 control connect */
+#define CLKPWR_PLL0CON_CONNECT ((uint32_t)(0x02))
+/** PLL 0 control bit mask */
+#define CLKPWR_PLL0CON_BITMASK ((uint32_t)(0x03))
+
+/*********************************************************************//**
+ * Macro defines for PPL0 Configuration Register
+ **********************************************************************/
+/** PLL 0 Configuration MSEL field */
+#define CLKPWR_PLL0CFG_MSEL(n) ((uint32_t)(n&0x7FFF))
+/** PLL 0 Configuration NSEL field */
+#define CLKPWR_PLL0CFG_NSEL(n) ((uint32_t)((n<<16)&0xFF0000))
+/** PLL 0 Configuration bit mask */
+#define CLKPWR_PLL0CFG_BITMASK ((uint32_t)(0xFF7FFF))
+
+
+/*********************************************************************//**
+ * Macro defines for PPL0 Status Register
+ **********************************************************************/
+/** PLL 0 MSEL value */
+#define CLKPWR_PLL0STAT_MSEL(n) ((uint32_t)(n&0x7FFF))
+/** PLL NSEL get value */
+#define CLKPWR_PLL0STAT_NSEL(n) ((uint32_t)((n>>16)&0xFF))
+/** PLL status enable bit */
+#define CLKPWR_PLL0STAT_PLLE ((uint32_t)(1<<24))
+/** PLL status Connect bit */
+#define CLKPWR_PLL0STAT_PLLC ((uint32_t)(1<<25))
+/** PLL status lock */
+#define CLKPWR_PLL0STAT_PLOCK ((uint32_t)(1<<26))
+
+/*********************************************************************//**
+ * Macro defines for PPL0 Feed Register
+ **********************************************************************/
+/** PLL0 Feed bit mask */
+#define CLKPWR_PLL0FEED_BITMASK ((uint32_t)0xFF)
+
+/*********************************************************************//**
+ * Macro defines for PLL1 Control Register
+ **********************************************************************/
+/** USB PLL control enable */
+#define CLKPWR_PLL1CON_ENABLE ((uint32_t)(0x01))
+/** USB PLL control connect */
+#define CLKPWR_PLL1CON_CONNECT ((uint32_t)(0x02))
+/** USB PLL control bit mask */
+#define CLKPWR_PLL1CON_BITMASK ((uint32_t)(0x03))
+
+/*********************************************************************//**
+ * Macro defines for PLL1 Configuration Register
+ **********************************************************************/
+/** USB PLL MSEL set value */
+#define CLKPWR_PLL1CFG_MSEL(n) ((uint32_t)(n&0x1F))
+/** USB PLL PSEL set value */
+#define CLKPWR_PLL1CFG_PSEL(n) ((uint32_t)((n&0x03)<<5))
+/** USB PLL configuration bit mask */
+#define CLKPWR_PLL1CFG_BITMASK ((uint32_t)(0x7F))
+
+/*********************************************************************//**
+ * Macro defines for PLL1 Status Register
+ **********************************************************************/
+/** USB PLL MSEL get value */
+#define CLKPWR_PLL1STAT_MSEL(n) ((uint32_t)(n&0x1F))
+/** USB PLL PSEL get value */
+#define CLKPWR_PLL1STAT_PSEL(n) ((uint32_t)((n>>5)&0x03))
+/** USB PLL status enable bit */
+#define CLKPWR_PLL1STAT_PLLE ((uint32_t)(1<<8))
+/** USB PLL status Connect bit */
+#define CLKPWR_PLL1STAT_PLLC ((uint32_t)(1<<9))
+/** USB PLL status lock */
+#define CLKPWR_PLL1STAT_PLOCK ((uint32_t)(1<<10))
+
+/*********************************************************************//**
+ * Macro defines for PLL1 Feed Register
+ **********************************************************************/
+/** PLL1 Feed bit mask */
+#define CLKPWR_PLL1FEED_BITMASK ((uint32_t)0xFF)
+
+/*********************************************************************//**
+ * Macro defines for CPU Clock Configuration Register
+ **********************************************************************/
+/** CPU Clock configuration bit mask */
+#define CLKPWR_CCLKCFG_BITMASK ((uint32_t)(0xFF))
+
+/*********************************************************************//**
+ * Macro defines for USB Clock Configuration Register
+ **********************************************************************/
+/** USB Clock Configuration bit mask */
+#define CLKPWR_USBCLKCFG_BITMASK ((uint32_t)(0x0F))
+
+/*********************************************************************//**
+ * Macro defines for IRC Trim Register
+ **********************************************************************/
+/** IRC Trim bit mask */
+#define CLKPWR_IRCTRIM_BITMASK ((uint32_t)(0x0F))
+
+/*********************************************************************//**
+ * Macro defines for Peripheral Clock Selection Register 0 and 1
+ **********************************************************************/
+/** Peripheral Clock Selection 0 mask bit */
+#define CLKPWR_PCLKSEL0_BITMASK ((uint32_t)(0xFFF3F3FF))
+/** Peripheral Clock Selection 1 mask bit */
+#define CLKPWR_PCLKSEL1_BITMASK ((uint32_t)(0xFCF3F0F3))
+/** Macro to set peripheral clock of each type
+ * p: position of two bits that hold divider of peripheral clock
+ * n: value of divider of peripheral clock to be set */
+#define CLKPWR_PCLKSEL_SET(p,n) _SBF(p,n)
+/** Macro to mask peripheral clock of each type */
+#define CLKPWR_PCLKSEL_BITMASK(p) _SBF(p,0x03)
+/** Macro to get peripheral clock of each type */
+#define CLKPWR_PCLKSEL_GET(p, n) ((uint32_t)((n>>p)&0x03))
+
+/*********************************************************************//**
+ * Macro defines for Power Mode Control Register
+ **********************************************************************/
+/** Power mode control bit 0 */
+#define CLKPWR_PCON_PM0 ((uint32_t)(1<<0))
+/** Power mode control bit 1 */
+#define CLKPWR_PCON_PM1 ((uint32_t)(1<<1))
+/** Brown-Out Reduced Power Mode */
+#define CLKPWR_PCON_BODPDM ((uint32_t)(1<<2))
+/** Brown-Out Global Disable */
+#define CLKPWR_PCON_BOGD ((uint32_t)(1<<3))
+/** Brown Out Reset Disable */
+#define CLKPWR_PCON_BORD ((uint32_t)(1<<4))
+/** Sleep Mode entry flag */
+#define CLKPWR_PCON_SMFLAG ((uint32_t)(1<<8))
+/** Deep Sleep entry flag */
+#define CLKPWR_PCON_DSFLAG ((uint32_t)(1<<9))
+/** Power-down entry flag */
+#define CLKPWR_PCON_PDFLAG ((uint32_t)(1<<10))
+/** Deep Power-down entry flag */
+#define CLKPWR_PCON_DPDFLAG ((uint32_t)(1<<11))
+
+/*********************************************************************//**
+ * Macro defines for Power Control for Peripheral Register
+ **********************************************************************/
+/** Power Control for Peripherals bit mask */
+#define CLKPWR_PCONP_BITMASK 0xEFEFF7DE
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup CLKPWR_Public_Functions CLKPWR Public Functions
+ * @{
+ */
+
+void CLKPWR_SetPCLKDiv (uint32_t ClkType, uint32_t DivVal);
+uint32_t CLKPWR_GetPCLKSEL (uint32_t ClkType);
+uint32_t CLKPWR_GetPCLK (uint32_t ClkType);
+void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState);
+void CLKPWR_Sleep(void);
+void CLKPWR_DeepSleep(void);
+void CLKPWR_PowerDown(void);
+void CLKPWR_DeepPowerDown(void);
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC17XX_CLKPWR_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/src/shared/cmsis/Drivers/include/lpc17xx_dac.h b/src/shared/cmsis/Drivers/include/lpc17xx_dac.h
@@ -0,0 +1,154 @@
+/**********************************************************************
+* $Id$ lpc17xx_dac.h 2010-05-21
+*//**
+* @file lpc17xx_dac.h
+* @brief Contains all macro definitions and function prototypes
+* support for Clock and Power Control firmware library on LPC17xx
+* @version 2.0
+* @date 21. May. 2010
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2010, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup DAC DAC (Digital-to-Analog Controller)
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_DAC_H_
+#define LPC17XX_DAC_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup DAC_Private_Macros DAC Private Macros
+ * @{
+ */
+
+/** After the selected settling time after this field is written with a
+new VALUE, the voltage on the AOUT pin (with respect to VSSA)
+is VALUE/1024 × VREF */
+#define DAC_VALUE(n) ((uint32_t)((n&0x3FF)<<6))
+/** If this bit = 0: The settling time of the DAC is 1 microsecond max,
+ * and the maximum current is 700 microAmpere
+ * If this bit = 1: The settling time of the DAC is 2.5 microsecond
+ * and the maximum current is 350 microAmpere */
+#define DAC_BIAS_EN ((uint32_t)(1<<16))
+/** Value to reload interrupt DMA counter */
+#define DAC_CCNT_VALUE(n) ((uint32_t)(n&0xffff))
+
+/** DCAR double buffering */
+#define DAC_DBLBUF_ENA ((uint32_t)(1<<1))
+/** DCAR Time out count enable */
+#define DAC_CNT_ENA ((uint32_t)(1<<2))
+/** DCAR DMA access */
+#define DAC_DMA_ENA ((uint32_t)(1<<3))
+/** DCAR DACCTRL mask bit */
+#define DAC_DACCTRL_MASK ((uint32_t)(0x0F))
+
+/** Macro to determine if it is valid DAC peripheral */
+#define PARAM_DACx(n) (((uint32_t *)n)==((uint32_t *)LPC_DAC))
+
+/** Macro to check DAC current optional parameter */
+#define PARAM_DAC_CURRENT_OPT(OPTION) ((OPTION == DAC_MAX_CURRENT_700uA)\
+||(OPTION == DAC_MAX_CURRENT_350uA))
+/**
+ * @}
+ */
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup DAC_Public_Types DAC Public Types
+ * @{
+ */
+
+/**
+ * @brief Current option in DAC configuration option */
+typedef enum
+{
+ DAC_MAX_CURRENT_700uA = 0, /*!< The settling time of the DAC is 1 us max,
+ and the maximum current is 700 uA */
+ DAC_MAX_CURRENT_350uA /*!< The settling time of the DAC is 2.5 us
+ and the maximum current is 350 uA */
+} DAC_CURRENT_OPT;
+
+/**
+ * @brief Configuration for DAC converter control register */
+typedef struct
+{
+
+ uint8_t DBLBUF_ENA; /**<
+ -0: Disable DACR double buffering
+ -1: when bit CNT_ENA, enable DACR double buffering feature
+ */
+ uint8_t CNT_ENA; /*!<
+ -0: Time out counter is disable
+ -1: Time out conter is enable
+ */
+ uint8_t DMA_ENA; /*!<
+ -0: DMA access is disable
+ -1: DMA burst request
+ */
+ uint8_t RESERVED;
+
+} DAC_CONVERTER_CFG_Type;
+
+/**
+ * @}
+ */
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup DAC_Public_Functions DAC Public Functions
+ * @{
+ */
+
+void DAC_Init(LPC_DAC_TypeDef *DACx);
+void DAC_UpdateValue (LPC_DAC_TypeDef *DACx, uint32_t dac_value);
+void DAC_SetBias (LPC_DAC_TypeDef *DACx,uint32_t bias);
+void DAC_ConfigDAConverterControl (LPC_DAC_TypeDef *DACx,DAC_CONVERTER_CFG_Type *DAC_ConverterConfigStruct);
+void DAC_SetDMATimeOut(LPC_DAC_TypeDef *DACx,uint32_t time_out);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* LPC17XX_DAC_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
+
diff --git a/src/shared/cmsis/Drivers/include/lpc17xx_emac.h b/src/shared/cmsis/Drivers/include/lpc17xx_emac.h
@@ -0,0 +1,711 @@
+/**********************************************************************
+* $Id$ lpc17xx_emac.h 2010-05-21
+*//**
+* @file lpc17xx_emac.h
+* @brief Contains all macro definitions and function prototypes
+* support for Ethernet MAC firmware library on LPC17xx
+* @version 2.0
+* @date 21. May. 2010
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2010, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup EMAC EMAC (Ethernet Media Access Controller)
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_EMAC_H_
+#define LPC17XX_EMAC_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#define MCB_LPC_1768
+//#define IAR_LPC_1768
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup EMAC_Public_Macros EMAC Public Macros
+ * @{
+ */
+
+
+/* EMAC PHY status type definitions */
+#define EMAC_PHY_STAT_LINK (0) /**< Link Status */
+#define EMAC_PHY_STAT_SPEED (1) /**< Speed Status */
+#define EMAC_PHY_STAT_DUP (2) /**< Duplex Status */
+
+/* EMAC PHY device Speed definitions */
+#define EMAC_MODE_AUTO (0) /**< Auto-negotiation mode */
+#define EMAC_MODE_10M_FULL (1) /**< 10Mbps FullDuplex mode */
+#define EMAC_MODE_10M_HALF (2) /**< 10Mbps HalfDuplex mode */
+#define EMAC_MODE_100M_FULL (3) /**< 100Mbps FullDuplex mode */
+#define EMAC_MODE_100M_HALF (4) /**< 100Mbps HalfDuplex mode */
+
+/**
+ * @}
+ */
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup EMAC_Private_Macros EMAC Private Macros
+ * @{
+ */
+
+
+/* EMAC Memory Buffer configuration for 16K Ethernet RAM */
+#define EMAC_NUM_RX_FRAG 4 /**< Num.of RX Fragments 4*1536= 6.0kB */
+#define EMAC_NUM_TX_FRAG 3 /**< Num.of TX Fragments 3*1536= 4.6kB */
+#define EMAC_ETH_MAX_FLEN 1536 /**< Max. Ethernet Frame Size */
+#define EMAC_TX_FRAME_TOUT 0x00100000 /**< Frame Transmit timeout count */
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/*********************************************************************//**
+ * Macro defines for MAC Configuration Register 1
+ **********************************************************************/
+#define EMAC_MAC1_REC_EN 0x00000001 /**< Receive Enable */
+#define EMAC_MAC1_PASS_ALL 0x00000002 /**< Pass All Receive Frames */
+#define EMAC_MAC1_RX_FLOWC 0x00000004 /**< RX Flow Control */
+#define EMAC_MAC1_TX_FLOWC 0x00000008 /**< TX Flow Control */
+#define EMAC_MAC1_LOOPB 0x00000010 /**< Loop Back Mode */
+#define EMAC_MAC1_RES_TX 0x00000100 /**< Reset TX Logic */
+#define EMAC_MAC1_RES_MCS_TX 0x00000200 /**< Reset MAC TX Control Sublayer */
+#define EMAC_MAC1_RES_RX 0x00000400 /**< Reset RX Logic */
+#define EMAC_MAC1_RES_MCS_RX 0x00000800 /**< Reset MAC RX Control Sublayer */
+#define EMAC_MAC1_SIM_RES 0x00004000 /**< Simulation Reset */
+#define EMAC_MAC1_SOFT_RES 0x00008000 /**< Soft Reset MAC */
+
+/*********************************************************************//**
+ * Macro defines for MAC Configuration Register 2
+ **********************************************************************/
+#define EMAC_MAC2_FULL_DUP 0x00000001 /**< Full-Duplex Mode */
+#define EMAC_MAC2_FRM_LEN_CHK 0x00000002 /**< Frame Length Checking */
+#define EMAC_MAC2_HUGE_FRM_EN 0x00000004 /**< Huge Frame Enable */
+#define EMAC_MAC2_DLY_CRC 0x00000008 /**< Delayed CRC Mode */
+#define EMAC_MAC2_CRC_EN 0x00000010 /**< Append CRC to every Frame */
+#define EMAC_MAC2_PAD_EN 0x00000020 /**< Pad all Short Frames */
+#define EMAC_MAC2_VLAN_PAD_EN 0x00000040 /**< VLAN Pad Enable */
+#define EMAC_MAC2_ADET_PAD_EN 0x00000080 /**< Auto Detect Pad Enable */
+#define EMAC_MAC2_PPREAM_ENF 0x00000100 /**< Pure Preamble Enforcement */
+#define EMAC_MAC2_LPREAM_ENF 0x00000200 /**< Long Preamble Enforcement */
+#define EMAC_MAC2_NO_BACKOFF 0x00001000 /**< No Backoff Algorithm */
+#define EMAC_MAC2_BACK_PRESSURE 0x00002000 /**< Backoff Presurre / No Backoff */
+#define EMAC_MAC2_EXCESS_DEF 0x00004000 /**< Excess Defer */
+
+/*********************************************************************//**
+ * Macro defines for Back-to-Back Inter-Packet-Gap Register
+ **********************************************************************/
+/** Programmable field representing the nibble time offset of the minimum possible period
+ * between the end of any transmitted packet to the beginning of the next */
+#define EMAC_IPGT_BBIPG(n) (n&0x7F)
+/** Recommended value for Full Duplex of Programmable field representing the nibble time
+ * offset of the minimum possible period between the end of any transmitted packet to the
+ * beginning of the next */
+#define EMAC_IPGT_FULL_DUP (EMAC_IPGT_BBIPG(0x15))
+/** Recommended value for Half Duplex of Programmable field representing the nibble time
+ * offset of the minimum possible period between the end of any transmitted packet to the
+ * beginning of the next */
+#define EMAC_IPGT_HALF_DUP (EMAC_IPGT_BBIPG(0x12))
+
+/*********************************************************************//**
+ * Macro defines for Non Back-to-Back Inter-Packet-Gap Register
+ **********************************************************************/
+/** Programmable field representing the Non-Back-to-Back Inter-Packet-Gap */
+#define EMAC_IPGR_NBBIPG_P2(n) (n&0x7F)
+/** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 1 */
+#define EMAC_IPGR_P2_DEF (EMAC_IPGR_NBBIPG_P2(0x12))
+/** Programmable field representing the optional carrierSense window referenced in
+ * IEEE 802.3/4.2.3.2.1 'Carrier Deference' */
+#define EMAC_IPGR_NBBIPG_P1(n) ((n&0x7F)<<8)
+/** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 2 */
+#define EMAC_IPGR_P1_DEF EMAC_IPGR_NBBIPG_P1(0x0C)
+
+/*********************************************************************//**
+ * Macro defines for Collision Window/Retry Register
+ **********************************************************************/
+/** Programmable field specifying the number of retransmission attempts following a collision before
+ * aborting the packet due to excessive collisions */
+#define EMAC_CLRT_MAX_RETX(n) (n&0x0F)
+/** Programmable field representing the slot time or collision window during which collisions occur
+ * in properly configured networks */
+#define EMAC_CLRT_COLL(n) ((n&0x3F)<<8)
+/** Default value for Collision Window / Retry register */
+#define EMAC_CLRT_DEF ((EMAC_CLRT_MAX_RETX(0x0F))|(EMAC_CLRT_COLL(0x37)))
+
+/*********************************************************************//**
+ * Macro defines for Maximum Frame Register
+ **********************************************************************/
+/** Represents a maximum receive frame of 1536 octets */
+#define EMAC_MAXF_MAXFRMLEN(n) (n&0xFFFF)
+
+/*********************************************************************//**
+ * Macro defines for PHY Support Register
+ **********************************************************************/
+#define EMAC_SUPP_SPEED 0x00000100 /**< Reduced MII Logic Current Speed */
+//#define EMAC_SUPP_RES_RMII 0x00000800 /**< Reset Reduced MII Logic */
+
+/*********************************************************************//**
+ * Macro defines for Test Register
+ **********************************************************************/
+#define EMAC_TEST_SHCUT_PQUANTA 0x00000001 /**< Shortcut Pause Quanta */
+#define EMAC_TEST_TST_PAUSE 0x00000002 /**< Test Pause */
+#define EMAC_TEST_TST_BACKP 0x00000004 /**< Test Back Pressure */
+
+/*********************************************************************//**
+ * Macro defines for MII Management Configuration Register
+ **********************************************************************/
+#define EMAC_MCFG_SCAN_INC 0x00000001 /**< Scan Increment PHY Address */
+#define EMAC_MCFG_SUPP_PREAM 0x00000002 /**< Suppress Preamble */
+#define EMAC_MCFG_CLK_SEL(n) ((n&0x0F)<<2) /**< Clock Select Field */
+#define EMAC_MCFG_RES_MII 0x00008000 /**< Reset MII Management Hardware */
+#define EMAC_MCFG_MII_MAXCLK 2500000UL /**< MII Clock max */
+
+/*********************************************************************//**
+ * Macro defines for MII Management Command Register
+ **********************************************************************/
+#define EMAC_MCMD_READ 0x00000001 /**< MII Read */
+#define EMAC_MCMD_SCAN 0x00000002 /**< MII Scan continuously */
+
+#define EMAC_MII_WR_TOUT 0x00050000 /**< MII Write timeout count */
+#define EMAC_MII_RD_TOUT 0x00050000 /**< MII Read timeout count */
+
+/*********************************************************************//**
+ * Macro defines for MII Management Address Register
+ **********************************************************************/
+#define EMAC_MADR_REG_ADR(n) (n&0x1F) /**< MII Register Address field */
+#define EMAC_MADR_PHY_ADR(n) ((n&0x1F)<<8) /**< PHY Address Field */
+
+/*********************************************************************//**
+ * Macro defines for MII Management Write Data Register
+ **********************************************************************/
+#define EMAC_MWTD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Write Data register */
+
+/*********************************************************************//**
+ * Macro defines for MII Management Read Data Register
+ **********************************************************************/
+#define EMAC_MRDD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Read Data register */
+
+/*********************************************************************//**
+ * Macro defines for MII Management Indicators Register
+ **********************************************************************/
+#define EMAC_MIND_BUSY 0x00000001 /**< MII is Busy */
+#define EMAC_MIND_SCAN 0x00000002 /**< MII Scanning in Progress */
+#define EMAC_MIND_NOT_VAL 0x00000004 /**< MII Read Data not valid */
+#define EMAC_MIND_MII_LINK_FAIL 0x00000008 /**< MII Link Failed */
+
+/* Station Address 0 Register */
+/* Station Address 1 Register */
+/* Station Address 2 Register */
+
+
+/* Control register definitions --------------------------------------------------------------------------- */
+/*********************************************************************//**
+ * Macro defines for Command Register
+ **********************************************************************/
+#define EMAC_CR_RX_EN 0x00000001 /**< Enable Receive */
+#define EMAC_CR_TX_EN 0x00000002 /**< Enable Transmit */
+#define EMAC_CR_REG_RES 0x00000008 /**< Reset Host Registers */
+#define EMAC_CR_TX_RES 0x00000010 /**< Reset Transmit Datapath */
+#define EMAC_CR_RX_RES 0x00000020 /**< Reset Receive Datapath */
+#define EMAC_CR_PASS_RUNT_FRM 0x00000040 /**< Pass Runt Frames */
+#define EMAC_CR_PASS_RX_FILT 0x00000080 /**< Pass RX Filter */
+#define EMAC_CR_TX_FLOW_CTRL 0x00000100 /**< TX Flow Control */
+#define EMAC_CR_RMII 0x00000200 /**< Reduced MII Interface */
+#define EMAC_CR_FULL_DUP 0x00000400 /**< Full Duplex */
+
+/*********************************************************************//**
+ * Macro defines for Status Register
+ **********************************************************************/
+#define EMAC_SR_RX_EN 0x00000001 /**< Enable Receive */
+#define EMAC_SR_TX_EN 0x00000002 /**< Enable Transmit */
+
+/*********************************************************************//**
+ * Macro defines for Transmit Status Vector 0 Register
+ **********************************************************************/
+#define EMAC_TSV0_CRC_ERR 0x00000001 /**< CRC error */
+#define EMAC_TSV0_LEN_CHKERR 0x00000002 /**< Length Check Error */
+#define EMAC_TSV0_LEN_OUTRNG 0x00000004 /**< Length Out of Range */
+#define EMAC_TSV0_DONE 0x00000008 /**< Tramsmission Completed */
+#define EMAC_TSV0_MCAST 0x00000010 /**< Multicast Destination */
+#define EMAC_TSV0_BCAST 0x00000020 /**< Broadcast Destination */
+#define EMAC_TSV0_PKT_DEFER 0x00000040 /**< Packet Deferred */
+#define EMAC_TSV0_EXC_DEFER 0x00000080 /**< Excessive Packet Deferral */
+#define EMAC_TSV0_EXC_COLL 0x00000100 /**< Excessive Collision */
+#define EMAC_TSV0_LATE_COLL 0x00000200 /**< Late Collision Occured */
+#define EMAC_TSV0_GIANT 0x00000400 /**< Giant Frame */
+#define EMAC_TSV0_UNDERRUN 0x00000800 /**< Buffer Underrun */
+#define EMAC_TSV0_BYTES 0x0FFFF000 /**< Total Bytes Transferred */
+#define EMAC_TSV0_CTRL_FRAME 0x10000000 /**< Control Frame */
+#define EMAC_TSV0_PAUSE 0x20000000 /**< Pause Frame */
+#define EMAC_TSV0_BACK_PRESS 0x40000000 /**< Backpressure Method Applied */
+#define EMAC_TSV0_VLAN 0x80000000 /**< VLAN Frame */
+
+/*********************************************************************//**
+ * Macro defines for Transmit Status Vector 1 Register
+ **********************************************************************/
+#define EMAC_TSV1_BYTE_CNT 0x0000FFFF /**< Transmit Byte Count */
+#define EMAC_TSV1_COLL_CNT 0x000F0000 /**< Transmit Collision Count */
+
+/*********************************************************************//**
+ * Macro defines for Receive Status Vector Register
+ **********************************************************************/
+#define EMAC_RSV_BYTE_CNT 0x0000FFFF /**< Receive Byte Count */
+#define EMAC_RSV_PKT_IGNORED 0x00010000 /**< Packet Previously Ignored */
+#define EMAC_RSV_RXDV_SEEN 0x00020000 /**< RXDV Event Previously Seen */
+#define EMAC_RSV_CARR_SEEN 0x00040000 /**< Carrier Event Previously Seen */
+#define EMAC_RSV_REC_CODEV 0x00080000 /**< Receive Code Violation */
+#define EMAC_RSV_CRC_ERR 0x00100000 /**< CRC Error */
+#define EMAC_RSV_LEN_CHKERR 0x00200000 /**< Length Check Error */
+#define EMAC_RSV_LEN_OUTRNG 0x00400000 /**< Length Out of Range */
+#define EMAC_RSV_REC_OK 0x00800000 /**< Frame Received OK */
+#define EMAC_RSV_MCAST 0x01000000 /**< Multicast Frame */
+#define EMAC_RSV_BCAST 0x02000000 /**< Broadcast Frame */
+#define EMAC_RSV_DRIB_NIBB 0x04000000 /**< Dribble Nibble */
+#define EMAC_RSV_CTRL_FRAME 0x08000000 /**< Control Frame */
+#define EMAC_RSV_PAUSE 0x10000000 /**< Pause Frame */
+#define EMAC_RSV_UNSUPP_OPC 0x20000000 /**< Unsupported Opcode */
+#define EMAC_RSV_VLAN 0x40000000 /**< VLAN Frame */
+
+/*********************************************************************//**
+ * Macro defines for Flow Control Counter Register
+ **********************************************************************/
+#define EMAC_FCC_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter */
+#define EMAC_FCC_PAUSE_TIM(n) ((n&0xFFFF)<<16) /**< Pause Timer */
+
+/*********************************************************************//**
+ * Macro defines for Flow Control Status Register
+ **********************************************************************/
+#define EMAC_FCS_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter Current */
+
+
+/* Receive filter register definitions -------------------------------------------------------- */
+/*********************************************************************//**
+ * Macro defines for Receive Filter Control Register
+ **********************************************************************/
+#define EMAC_RFC_UCAST_EN 0x00000001 /**< Accept Unicast Frames Enable */
+#define EMAC_RFC_BCAST_EN 0x00000002 /**< Accept Broadcast Frames Enable */
+#define EMAC_RFC_MCAST_EN 0x00000004 /**< Accept Multicast Frames Enable */
+#define EMAC_RFC_UCAST_HASH_EN 0x00000008 /**< Accept Unicast Hash Filter Frames */
+#define EMAC_RFC_MCAST_HASH_EN 0x00000010 /**< Accept Multicast Hash Filter Fram.*/
+#define EMAC_RFC_PERFECT_EN 0x00000020 /**< Accept Perfect Match Enable */
+#define EMAC_RFC_MAGP_WOL_EN 0x00001000 /**< Magic Packet Filter WoL Enable */
+#define EMAC_RFC_PFILT_WOL_EN 0x00002000 /**< Perfect Filter WoL Enable */
+
+/*********************************************************************//**
+ * Macro defines for Receive Filter WoL Status/Clear Registers
+ **********************************************************************/
+#define EMAC_WOL_UCAST 0x00000001 /**< Unicast Frame caused WoL */
+#define EMAC_WOL_BCAST 0x00000002 /**< Broadcast Frame caused WoL */
+#define EMAC_WOL_MCAST 0x00000004 /**< Multicast Frame caused WoL */
+#define EMAC_WOL_UCAST_HASH 0x00000008 /**< Unicast Hash Filter Frame WoL */
+#define EMAC_WOL_MCAST_HASH 0x00000010 /**< Multicast Hash Filter Frame WoL */
+#define EMAC_WOL_PERFECT 0x00000020 /**< Perfect Filter WoL */
+#define EMAC_WOL_RX_FILTER 0x00000080 /**< RX Filter caused WoL */
+#define EMAC_WOL_MAG_PACKET 0x00000100 /**< Magic Packet Filter caused WoL */
+#define EMAC_WOL_BITMASK 0x01BF /**< Receive Filter WoL Status/Clear bitmasl value */
+
+
+/* Module control register definitions ---------------------------------------------------- */
+/*********************************************************************//**
+ * Macro defines for Interrupt Status/Enable/Clear/Set Registers
+ **********************************************************************/
+#define EMAC_INT_RX_OVERRUN 0x00000001 /**< Overrun Error in RX Queue */
+#define EMAC_INT_RX_ERR 0x00000002 /**< Receive Error */
+#define EMAC_INT_RX_FIN 0x00000004 /**< RX Finished Process Descriptors */
+#define EMAC_INT_RX_DONE 0x00000008 /**< Receive Done */
+#define EMAC_INT_TX_UNDERRUN 0x00000010 /**< Transmit Underrun */
+#define EMAC_INT_TX_ERR 0x00000020 /**< Transmit Error */
+#define EMAC_INT_TX_FIN 0x00000040 /**< TX Finished Process Descriptors */
+#define EMAC_INT_TX_DONE 0x00000080 /**< Transmit Done */
+#define EMAC_INT_SOFT_INT 0x00001000 /**< Software Triggered Interrupt */
+#define EMAC_INT_WAKEUP 0x00002000 /**< Wakeup Event Interrupt */
+
+/*********************************************************************//**
+ * Macro defines for Power Down Register
+ **********************************************************************/
+#define EMAC_PD_POWER_DOWN 0x80000000 /**< Power Down MAC */
+
+/* Descriptor and status formats ---------------------------------------------------- */
+/*********************************************************************//**
+ * Macro defines for RX Descriptor Control Word
+ **********************************************************************/
+#define EMAC_RCTRL_SIZE(n) (n&0x7FF) /**< Buffer size field */
+#define EMAC_RCTRL_INT 0x80000000 /**< Generate RxDone Interrupt */
+
+/*********************************************************************//**
+ * Macro defines for RX Status Hash CRC Word
+ **********************************************************************/
+#define EMAC_RHASH_SA 0x000001FF /**< Hash CRC for Source Address */
+#define EMAC_RHASH_DA 0x001FF000 /**< Hash CRC for Destination Address */
+
+/*********************************************************************//**
+ * Macro defines for RX Status Information Word
+ **********************************************************************/
+#define EMAC_RINFO_SIZE 0x000007FF /**< Data size in bytes */
+#define EMAC_RINFO_CTRL_FRAME 0x00040000 /**< Control Frame */
+#define EMAC_RINFO_VLAN 0x00080000 /**< VLAN Frame */
+#define EMAC_RINFO_FAIL_FILT 0x00100000 /**< RX Filter Failed */
+#define EMAC_RINFO_MCAST 0x00200000 /**< Multicast Frame */
+#define EMAC_RINFO_BCAST 0x00400000 /**< Broadcast Frame */
+#define EMAC_RINFO_CRC_ERR 0x00800000 /**< CRC Error in Frame */
+#define EMAC_RINFO_SYM_ERR 0x01000000 /**< Symbol Error from PHY */
+#define EMAC_RINFO_LEN_ERR 0x02000000 /**< Length Error */
+#define EMAC_RINFO_RANGE_ERR 0x04000000 /**< Range Error (exceeded max. size) */
+#define EMAC_RINFO_ALIGN_ERR 0x08000000 /**< Alignment Error */
+#define EMAC_RINFO_OVERRUN 0x10000000 /**< Receive overrun */
+#define EMAC_RINFO_NO_DESCR 0x20000000 /**< No new Descriptor available */
+#define EMAC_RINFO_LAST_FLAG 0x40000000 /**< Last Fragment in Frame */
+#define EMAC_RINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
+#define EMAC_RINFO_ERR_MASK (EMAC_RINFO_FAIL_FILT | EMAC_RINFO_CRC_ERR | EMAC_RINFO_SYM_ERR | \
+EMAC_RINFO_LEN_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN)
+
+/*********************************************************************//**
+ * Macro defines for TX Descriptor Control Word
+ **********************************************************************/
+#define EMAC_TCTRL_SIZE 0x000007FF /**< Size of data buffer in bytes */
+#define EMAC_TCTRL_OVERRIDE 0x04000000 /**< Override Default MAC Registers */
+#define EMAC_TCTRL_HUGE 0x08000000 /**< Enable Huge Frame */
+#define EMAC_TCTRL_PAD 0x10000000 /**< Pad short Frames to 64 bytes */
+#define EMAC_TCTRL_CRC 0x20000000 /**< Append a hardware CRC to Frame */
+#define EMAC_TCTRL_LAST 0x40000000 /**< Last Descriptor for TX Frame */
+#define EMAC_TCTRL_INT 0x80000000 /**< Generate TxDone Interrupt */
+
+/*********************************************************************//**
+ * Macro defines for TX Status Information Word
+ **********************************************************************/
+#define EMAC_TINFO_COL_CNT 0x01E00000 /**< Collision Count */
+#define EMAC_TINFO_DEFER 0x02000000 /**< Packet Deferred (not an error) */
+#define EMAC_TINFO_EXCESS_DEF 0x04000000 /**< Excessive Deferral */
+#define EMAC_TINFO_EXCESS_COL 0x08000000 /**< Excessive Collision */
+#define EMAC_TINFO_LATE_COL 0x10000000 /**< Late Collision Occured */
+#define EMAC_TINFO_UNDERRUN 0x20000000 /**< Transmit Underrun */
+#define EMAC_TINFO_NO_DESCR 0x40000000 /**< No new Descriptor available */
+#define EMAC_TINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
+
+#ifdef MCB_LPC_1768
+/* DP83848C PHY definition ------------------------------------------------------------ */
+
+/** PHY device reset time out definition */
+#define EMAC_PHY_RESP_TOUT 0x100000UL
+
+/* ENET Device Revision ID */
+#define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */
+
+/*********************************************************************//**
+ * Macro defines for DP83848C PHY Registers
+ **********************************************************************/
+#define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */
+#define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */
+#define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */
+#define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */
+#define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */
+#define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */
+#define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */
+#define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */
+#define EMAC_PHY_REG_LPNPA 0x08
+
+/*********************************************************************//**
+ * Macro defines for PHY Extended Registers
+ **********************************************************************/
+#define EMAC_PHY_REG_STS 0x10 /**< Status Register */
+#define EMAC_PHY_REG_MICR 0x11 /**< MII Interrupt Control Register */
+#define EMAC_PHY_REG_MISR 0x12 /**< MII Interrupt Status Register */
+#define EMAC_PHY_REG_FCSCR 0x14 /**< False Carrier Sense Counter */
+#define EMAC_PHY_REG_RECR 0x15 /**< Receive Error Counter */
+#define EMAC_PHY_REG_PCSR 0x16 /**< PCS Sublayer Config. and Status */
+#define EMAC_PHY_REG_RBR 0x17 /**< RMII and Bypass Register */
+#define EMAC_PHY_REG_LEDCR 0x18 /**< LED Direct Control Register */
+#define EMAC_PHY_REG_PHYCR 0x19 /**< PHY Control Register */
+#define EMAC_PHY_REG_10BTSCR 0x1A /**< 10Base-T Status/Control Register */
+#define EMAC_PHY_REG_CDCTRL1 0x1B /**< CD Test Control and BIST Extens. */
+#define EMAC_PHY_REG_EDCR 0x1D /**< Energy Detect Control Register */
+
+/*********************************************************************//**
+ * Macro defines for PHY Basic Mode Control Register
+ **********************************************************************/
+#define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */
+#define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */
+#define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */
+#define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */
+#define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */
+#define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */
+#define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */
+#define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */
+
+/*********************************************************************//**
+ * Macro defines for PHY Basic Mode Status Status Register
+ **********************************************************************/
+#define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */
+#define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */
+#define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */
+#define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */
+#define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */
+#define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */
+#define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */
+#define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */
+#define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */
+#define EMAC_PHY_BMSR_LINK_ESTABLISHED (1<<2) /**< Link status */
+
+/*********************************************************************//**
+ * Macro defines for PHY Status Register
+ **********************************************************************/
+#define EMAC_PHY_SR_REMOTE_FAULT (1<<6) /**< Remote Fault */
+#define EMAC_PHY_SR_JABBER (1<<5) /**< Jabber detect */
+#define EMAC_PHY_SR_AUTO_DONE (1<<4) /**< Auto Negotiation complete */
+#define EMAC_PHY_SR_LOOPBACK (1<<3) /**< Loop back status */
+#define EMAC_PHY_SR_DUP (1<<2) /**< Duplex status */
+#define EMAC_PHY_SR_SPEED (1<<1) /**< Speed status */
+#define EMAC_PHY_SR_LINK (1<<0) /**< Link Status */
+
+#define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */
+#define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */
+#define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */
+#define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */
+#define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */
+
+#define EMAC_DEF_ADR 0x0100 /**< Default PHY device address */
+#define EMAC_DP83848C_ID 0x20005C90 /**< PHY Identifier */
+
+#define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13))
+#define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12))
+#define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */
+
+#elif defined(IAR_LPC_1768)
+/* KSZ8721BL PHY definition ------------------------------------------------------------ */
+/** PHY device reset time out definition */
+#define EMAC_PHY_RESP_TOUT 0x100000UL
+
+/* ENET Device Revision ID */
+#define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */
+
+/*********************************************************************//**
+ * Macro defines for KSZ8721BL PHY Registers
+ **********************************************************************/
+#define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */
+#define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */
+#define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */
+#define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */
+#define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */
+#define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */
+#define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */
+#define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */
+#define EMAC_PHY_REG_LPNPA 0x08 /**< Link Partner Next Page Ability */
+#define EMAC_PHY_REG_REC 0x15 /**< RXError Counter Register */
+#define EMAC_PHY_REG_ISC 0x1b /**< Interrupt Control/Status Register */
+#define EMAC_PHY_REG_100BASE 0x1f /**< 100BASE-TX PHY Control Register */
+
+/*********************************************************************//**
+ * Macro defines for PHY Basic Mode Control Register
+ **********************************************************************/
+#define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */
+#define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */
+#define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */
+#define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */
+#define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */
+#define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */
+#define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */
+#define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */
+#define EMAC_PHY_BMCR_COLLISION (1<<7) /**< Collision test */
+#define EMAC_PHY_BMCR_TXDIS (1<<0) /**< Disable transmit */
+
+/*********************************************************************//**
+ * Macro defines for PHY Basic Mode Status Register
+ **********************************************************************/
+#define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */
+#define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */
+#define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */
+#define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */
+#define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */
+#define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */
+#define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */
+#define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */
+#define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */
+#define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */
+#define EMAC_PHY_BMSR_JABBER_DETECT (1<<1) /**< Jabber detect */
+#define EMAC_PHY_BMSR_EXTEND (1<<0) /**< Extended support */
+
+/*********************************************************************//**
+ * Macro defines for PHY Identifier
+ **********************************************************************/
+/* PHY Identifier 1 bitmap definitions */
+#define EMAC_PHY_IDR1(n) (n & 0xFFFF) /**< PHY ID1 Number */
+
+/* PHY Identifier 2 bitmap definitions */
+#define EMAC_PHY_IDR2(n) (n & 0xFFFF) /**< PHY ID2 Number */
+
+/*********************************************************************//**
+ * Macro defines for Auto-Negotiation Advertisement
+ **********************************************************************/
+#define EMAC_PHY_AN_NEXTPAGE (1<<15) /**< Next page capable */
+#define EMAC_PHY_AN_REMOTE_FAULT (1<<13) /**< Remote Fault support */
+#define EMAC_PHY_AN_PAUSE (1<<10) /**< Pause support */
+#define EMAC_PHY_AN_100BASE_T4 (1<<9) /**< T4 capable */
+#define EMAC_PHY_AN_100BASE_TX_FD (1<<8) /**< TX with Full-duplex capable */
+#define EMAC_PHY_AN_100BASE_TX (1<<7) /**< TX capable */
+#define EMAC_PHY_AN_10BASE_T_FD (1<<6) /**< 10Mbps with full-duplex capable */
+#define EMAC_PHY_AN_10BASE_T (1<<5) /**< 10Mbps capable */
+#define EMAC_PHY_AN_FIELD(n) (n & 0x1F) /**< Selector Field */
+
+#define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */
+#define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */
+#define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */
+#define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */
+#define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */
+
+#define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13))
+#define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12))
+
+#define EMAC_DEF_ADR (0x01<<8) /**< Default PHY device address */
+#define EMAC_KSZ8721BL_ID ((0x22 << 16) | 0x1619 ) /**< PHY Identifier */
+#endif
+
+/**
+ * @}
+ */
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup EMAC_Public_Types EMAC Public Types
+ * @{
+ */
+
+/* Descriptor and status formats ---------------------------------------------- */
+
+/**
+ * @brief RX Descriptor structure type definition
+ */
+typedef struct {
+ uint32_t Packet; /**< Receive Packet Descriptor */
+ uint32_t Ctrl; /**< Receive Control Descriptor */
+} RX_Desc;
+
+/**
+ * @brief RX Status structure type definition
+ */
+typedef struct {
+ uint32_t Info; /**< Receive Information Status */
+ uint32_t HashCRC; /**< Receive Hash CRC Status */
+} RX_Stat;
+
+/**
+ * @brief TX Descriptor structure type definition
+ */
+typedef struct {
+ uint32_t Packet; /**< Transmit Packet Descriptor */
+ uint32_t Ctrl; /**< Transmit Control Descriptor */
+} TX_Desc;
+
+/**
+ * @brief TX Status structure type definition
+ */
+typedef struct {
+ uint32_t Info; /**< Transmit Information Status */
+} TX_Stat;
+
+
+/**
+ * @brief TX Data Buffer structure definition
+ */
+typedef struct {
+ uint32_t ulDataLen; /**< Data length */
+ uint32_t *pbDataBuf; /**< A word-align data pointer to data buffer */
+} EMAC_PACKETBUF_Type;
+
+/**
+ * @brief EMAC configuration structure definition
+ */
+typedef struct {
+ uint32_t Mode; /**< Supported EMAC PHY device speed, should be one of the following:
+ - EMAC_MODE_AUTO
+ - EMAC_MODE_10M_FULL
+ - EMAC_MODE_10M_HALF
+ - EMAC_MODE_100M_FULL
+ - EMAC_MODE_100M_HALF
+ */
+ uint8_t *pbEMAC_Addr; /**< Pointer to EMAC Station address that contains 6-bytes
+ of MAC address, it must be sorted in order (bEMAC_Addr[0]..[5])
+ */
+} EMAC_CFG_Type;
+
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup EMAC_Public_Functions EMAC Public Functions
+ * @{
+ */
+/* Init/DeInit EMAC peripheral */
+Status EMAC_Init(EMAC_CFG_Type *EMAC_ConfigStruct);
+void EMAC_DeInit(void);
+
+/* PHY functions --------------*/
+int32_t EMAC_CheckPHYStatus(uint32_t ulPHYState);
+int32_t EMAC_SetPHYMode(uint32_t ulPHYMode);
+int32_t EMAC_UpdatePHYStatus(void);
+
+/* Filter functions ----------*/
+void EMAC_SetHashFilter(uint8_t dstMAC_addr[], FunctionalState NewState);
+void EMAC_SetFilterMode(uint32_t ulFilterMode, FunctionalState NewState);
+
+/* EMAC Packet Buffer functions */
+void EMAC_WritePacketBuffer(EMAC_PACKETBUF_Type *pDataStruct);
+void EMAC_ReadPacketBuffer(EMAC_PACKETBUF_Type *pDataStruct);
+
+/* EMAC Interrupt functions -------*/
+void EMAC_IntCmd(uint32_t ulIntType, FunctionalState NewState);
+IntStatus EMAC_IntGetStatus(uint32_t ulIntType);
+
+/* EMAC Index functions -----------*/
+Bool EMAC_CheckReceiveIndex(void);
+Bool EMAC_CheckTransmitIndex(void);
+void EMAC_UpdateRxConsumeIndex(void);
+void EMAC_UpdateTxProduceIndex(void);
+
+FlagStatus EMAC_CheckReceiveDataStatus(uint32_t ulRxStatType);
+uint32_t EMAC_GetReceiveDataSize(void);
+FlagStatus EMAC_GetWoLStatus(uint32_t ulWoLMode);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC17XX_EMAC_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/src/shared/cmsis/Drivers/include/lpc17xx_exti.h b/src/shared/cmsis/Drivers/include/lpc17xx_exti.h
@@ -0,0 +1,155 @@
+/**********************************************************************
+* $Id$ lpc17xx_exti.h 2010-05-21
+*//**
+* @file lpc17xx_exti.h
+* @brief Contains all macro definitions and function prototypes
+* support for External interrupt firmware library on LPC17xx
+* @version 2.0
+* @date 21. May. 2010
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2010, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup EXTI EXTI (External Interrupt)
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_EXTI_H_
+#define LPC17XX_EXTI_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup EXTI_Private_Macros EXTI Private Macros
+ * @{
+ */
+/*********************************************************************//**
+ * Macro defines for EXTI control register
+ **********************************************************************/
+#define EXTI_EINT0_BIT_MARK 0x01
+#define EXTI_EINT1_BIT_MARK 0x02
+#define EXTI_EINT2_BIT_MARK 0x04
+#define EXTI_EINT3_BIT_MARK 0x08
+
+/**
+ * @}
+ */
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup EXTI_Public_Types EXTI Public Types
+ * @{
+ */
+
+/**
+ * @brief EXTI external interrupt line option
+ */
+typedef enum
+{
+ EXTI_EINT0, /*!< External interrupt 0, P2.10 */
+ EXTI_EINT1, /*!< External interrupt 0, P2.11 */
+ EXTI_EINT2, /*!< External interrupt 0, P2.12 */
+ EXTI_EINT3 /*!< External interrupt 0, P2.13 */
+} EXTI_LINE_ENUM;
+
+/**
+ * @brief EXTI mode option
+ */
+typedef enum
+{
+ EXTI_MODE_LEVEL_SENSITIVE, /*!< Level sensitivity is selected */
+ EXTI_MODE_EDGE_SENSITIVE /*!< Edge sensitivity is selected */
+} EXTI_MODE_ENUM;
+
+/**
+ * @brief EXTI polarity option
+ */
+typedef enum
+{
+ EXTI_POLARITY_LOW_ACTIVE_OR_FALLING_EDGE, /*!< Low active or falling edge sensitive
+ depending on pin mode */
+ EXTI_POLARITY_HIGH_ACTIVE_OR_RISING_EDGE /*!< High active or rising edge sensitive
+ depending on pin mode */
+} EXTI_POLARITY_ENUM;
+
+/**
+ * @brief EXTI Initialize structure
+ */
+typedef struct
+{
+ EXTI_LINE_ENUM EXTI_Line; /*!<Select external interrupt pin (EINT0, EINT1, EINT 2, EINT3) */
+
+ EXTI_MODE_ENUM EXTI_Mode; /*!< Choose between Level-sensitivity or Edge sensitivity */
+
+ EXTI_POLARITY_ENUM EXTI_polarity; /*!< If EXTI mode is level-sensitive: this element use to select low or high active level
+ if EXTI mode is polarity-sensitive: this element use to select falling or rising edge */
+
+}EXTI_InitTypeDef;
+
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup EXTI_Public_Functions EXTI Public Functions
+ * @{
+ */
+
+void EXTI_Init(void);
+void EXTI_DeInit(void);
+
+void EXTI_Config(EXTI_InitTypeDef *EXTICfg);
+void EXTI_SetMode(EXTI_LINE_ENUM EXTILine, EXTI_MODE_ENUM mode);
+void EXTI_SetPolarity(EXTI_LINE_ENUM EXTILine, EXTI_POLARITY_ENUM polarity);
+void EXTI_ClearEXTIFlag(EXTI_LINE_ENUM EXTILine);
+
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* LPC17XX_EXTI_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/src/shared/cmsis/Drivers/include/lpc17xx_gpdma.h b/src/shared/cmsis/Drivers/include/lpc17xx_gpdma.h
@@ -0,0 +1,429 @@
+/**********************************************************************
+* $Id$ lpc17xx_gpdma.h 2010-05-21
+*//**
+* @file lpc17xx_gpdma.h
+* @brief Contains all macro definitions and function prototypes
+* support for GPDMA firmware library on LPC17xx
+* @version 2.0
+* @date 21. May. 2010
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2010, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup GPDMA GPDMA (General Purpose Direct Memory Access)
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_GPDMA_H_
+#define LPC17XX_GPDMA_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup GPDMA_Public_Macros GPDMA Public Macros
+ * @{
+ */
+
+/** DMA Connection number definitions */
+#define GPDMA_CONN_SSP0_Tx ((0UL)) /**< SSP0 Tx */
+#define GPDMA_CONN_SSP0_Rx ((1UL)) /**< SSP0 Rx */
+#define GPDMA_CONN_SSP1_Tx ((2UL)) /**< SSP1 Tx */
+#define GPDMA_CONN_SSP1_Rx ((3UL)) /**< SSP1 Rx */
+#define GPDMA_CONN_ADC ((4UL)) /**< ADC */
+#define GPDMA_CONN_I2S_Channel_0 ((5UL)) /**< I2S channel 0 */
+#define GPDMA_CONN_I2S_Channel_1 ((6UL)) /**< I2S channel 1 */
+#define GPDMA_CONN_DAC ((7UL)) /**< DAC */
+#define GPDMA_CONN_UART0_Tx ((8UL)) /**< UART0 Tx */
+#define GPDMA_CONN_UART0_Rx ((9UL)) /**< UART0 Rx */
+#define GPDMA_CONN_UART1_Tx ((10UL)) /**< UART1 Tx */
+#define GPDMA_CONN_UART1_Rx ((11UL)) /**< UART1 Rx */
+#define GPDMA_CONN_UART2_Tx ((12UL)) /**< UART2 Tx */
+#define GPDMA_CONN_UART2_Rx ((13UL)) /**< UART2 Rx */
+#define GPDMA_CONN_UART3_Tx ((14UL)) /**< UART3 Tx */
+#define GPDMA_CONN_UART3_Rx ((15UL)) /**< UART3 Rx */
+#define GPDMA_CONN_MAT0_0 ((16UL)) /**< MAT0.0 */
+#define GPDMA_CONN_MAT0_1 ((17UL)) /**< MAT0.1 */
+#define GPDMA_CONN_MAT1_0 ((18UL)) /**< MAT1.0 */
+#define GPDMA_CONN_MAT1_1 ((19UL)) /**< MAT1.1 */
+#define GPDMA_CONN_MAT2_0 ((20UL)) /**< MAT2.0 */
+#define GPDMA_CONN_MAT2_1 ((21UL)) /**< MAT2.1 */
+#define GPDMA_CONN_MAT3_0 ((22UL)) /**< MAT3.0 */
+#define GPDMA_CONN_MAT3_1 ((23UL)) /**< MAT3.1 */
+
+/** GPDMA Transfer type definitions */
+#define GPDMA_TRANSFERTYPE_M2M ((0UL)) /**< Memory to memory - DMA control */
+#define GPDMA_TRANSFERTYPE_M2P ((1UL)) /**< Memory to peripheral - DMA control */
+#define GPDMA_TRANSFERTYPE_P2M ((2UL)) /**< Peripheral to memory - DMA control */
+#define GPDMA_TRANSFERTYPE_P2P ((3UL)) /**< Source peripheral to destination peripheral - DMA control */
+
+/** Burst size in Source and Destination definitions */
+#define GPDMA_BSIZE_1 ((0UL)) /**< Burst size = 1 */
+#define GPDMA_BSIZE_4 ((1UL)) /**< Burst size = 4 */
+#define GPDMA_BSIZE_8 ((2UL)) /**< Burst size = 8 */
+#define GPDMA_BSIZE_16 ((3UL)) /**< Burst size = 16 */
+#define GPDMA_BSIZE_32 ((4UL)) /**< Burst size = 32 */
+#define GPDMA_BSIZE_64 ((5UL)) /**< Burst size = 64 */
+#define GPDMA_BSIZE_128 ((6UL)) /**< Burst size = 128 */
+#define GPDMA_BSIZE_256 ((7UL)) /**< Burst size = 256 */
+
+/** Width in Source transfer width and Destination transfer width definitions */
+#define GPDMA_WIDTH_BYTE ((0UL)) /**< Width = 1 byte */
+#define GPDMA_WIDTH_HALFWORD ((1UL)) /**< Width = 2 bytes */
+#define GPDMA_WIDTH_WORD ((2UL)) /**< Width = 4 bytes */
+
+/** DMA Request Select Mode definitions */
+#define GPDMA_REQSEL_UART ((0UL)) /**< UART TX/RX is selected */
+#define GPDMA_REQSEL_TIMER ((1UL)) /**< Timer match is selected */
+
+/**
+ * @}
+ */
+
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup GPDMA_Private_Macros GPDMA Private Macros
+ * @{
+ */
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/*********************************************************************//**
+ * Macro defines for DMA Interrupt Status register
+ **********************************************************************/
+#define GPDMA_DMACIntStat_Ch(n) (((1UL<<n)&0xFF))
+#define GPDMA_DMACIntStat_BITMASK ((0xFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Interrupt Terminal Count Request Status register
+ **********************************************************************/
+#define GPDMA_DMACIntTCStat_Ch(n) (((1UL<<n)&0xFF))
+#define GPDMA_DMACIntTCStat_BITMASK ((0xFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Interrupt Terminal Count Request Clear register
+ **********************************************************************/
+#define GPDMA_DMACIntTCClear_Ch(n) (((1UL<<n)&0xFF))
+#define GPDMA_DMACIntTCClear_BITMASK ((0xFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Interrupt Error Status register
+ **********************************************************************/
+#define GPDMA_DMACIntErrStat_Ch(n) (((1UL<<n)&0xFF))
+#define GPDMA_DMACIntErrStat_BITMASK ((0xFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Interrupt Error Clear register
+ **********************************************************************/
+#define GPDMA_DMACIntErrClr_Ch(n) (((1UL<<n)&0xFF))
+#define GPDMA_DMACIntErrClr_BITMASK ((0xFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Raw Interrupt Terminal Count Status register
+ **********************************************************************/
+#define GPDMA_DMACRawIntTCStat_Ch(n) (((1UL<<n)&0xFF))
+#define GPDMA_DMACRawIntTCStat_BITMASK ((0xFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Raw Error Interrupt Status register
+ **********************************************************************/
+#define GPDMA_DMACRawIntErrStat_Ch(n) (((1UL<<n)&0xFF))
+#define GPDMA_DMACRawIntErrStat_BITMASK ((0xFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Enabled Channel register
+ **********************************************************************/
+#define GPDMA_DMACEnbldChns_Ch(n) (((1UL<<n)&0xFF))
+#define GPDMA_DMACEnbldChns_BITMASK ((0xFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Software Burst Request register
+ **********************************************************************/
+#define GPDMA_DMACSoftBReq_Src(n) (((1UL<<n)&0xFFFF))
+#define GPDMA_DMACSoftBReq_BITMASK ((0xFFFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Software Single Request register
+ **********************************************************************/
+#define GPDMA_DMACSoftSReq_Src(n) (((1UL<<n)&0xFFFF))
+#define GPDMA_DMACSoftSReq_BITMASK ((0xFFFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Software Last Burst Request register
+ **********************************************************************/
+#define GPDMA_DMACSoftLBReq_Src(n) (((1UL<<n)&0xFFFF))
+#define GPDMA_DMACSoftLBReq_BITMASK ((0xFFFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Software Last Single Request register
+ **********************************************************************/
+#define GPDMA_DMACSoftLSReq_Src(n) (((1UL<<n)&0xFFFF))
+#define GPDMA_DMACSoftLSReq_BITMASK ((0xFFFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Configuration register
+ **********************************************************************/
+#define GPDMA_DMACConfig_E ((0x01)) /**< DMA Controller enable*/
+#define GPDMA_DMACConfig_M ((0x02)) /**< AHB Master endianness configuration*/
+#define GPDMA_DMACConfig_BITMASK ((0x03))
+
+/*********************************************************************//**
+ * Macro defines for DMA Synchronization register
+ **********************************************************************/
+#define GPDMA_DMACSync_Src(n) (((1UL<<n)&0xFFFF))
+#define GPDMA_DMACSync_BITMASK ((0xFFFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Request Select register
+ **********************************************************************/
+#define GPDMA_DMAReqSel_Input(n) (((1UL<<(n-8))&0xFF))
+#define GPDMA_DMAReqSel_BITMASK ((0xFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Channel Linked List Item registers
+ **********************************************************************/
+/** DMA Channel Linked List Item registers bit mask*/
+#define GPDMA_DMACCxLLI_BITMASK ((0xFFFFFFFC))
+
+/*********************************************************************//**
+ * Macro defines for DMA channel control registers
+ **********************************************************************/
+#define GPDMA_DMACCxControl_TransferSize(n) (((n&0xFFF)<<0)) /**< Transfer size*/
+#define GPDMA_DMACCxControl_SBSize(n) (((n&0x07)<<12)) /**< Source burst size*/
+#define GPDMA_DMACCxControl_DBSize(n) (((n&0x07)<<15)) /**< Destination burst size*/
+#define GPDMA_DMACCxControl_SWidth(n) (((n&0x07)<<18)) /**< Source transfer width*/
+#define GPDMA_DMACCxControl_DWidth(n) (((n&0x07)<<21)) /**< Destination transfer width*/
+#define GPDMA_DMACCxControl_SI ((1UL<<26)) /**< Source increment*/
+#define GPDMA_DMACCxControl_DI ((1UL<<27)) /**< Destination increment*/
+#define GPDMA_DMACCxControl_Prot1 ((1UL<<28)) /**< Indicates that the access is in user mode or privileged mode*/
+#define GPDMA_DMACCxControl_Prot2 ((1UL<<29)) /**< Indicates that the access is bufferable or not bufferable*/
+#define GPDMA_DMACCxControl_Prot3 ((1UL<<30)) /**< Indicates that the access is cacheable or not cacheable*/
+#define GPDMA_DMACCxControl_I ((1UL<<31)) /**< Terminal count interrupt enable bit */
+/** DMA channel control registers bit mask */
+#define GPDMA_DMACCxControl_BITMASK ((0xFCFFFFFF))
+
+/*********************************************************************//**
+ * Macro defines for DMA Channel Configuration registers
+ **********************************************************************/
+#define GPDMA_DMACCxConfig_E ((1UL<<0)) /**< DMA control enable*/
+#define GPDMA_DMACCxConfig_SrcPeripheral(n) (((n&0x1F)<<1)) /**< Source peripheral*/
+#define GPDMA_DMACCxConfig_DestPeripheral(n) (((n&0x1F)<<6)) /**< Destination peripheral*/
+#define GPDMA_DMACCxConfig_TransferType(n) (((n&0x7)<<11)) /**< This value indicates the type of transfer*/
+#define GPDMA_DMACCxConfig_IE ((1UL<<14)) /**< Interrupt error mask*/
+#define GPDMA_DMACCxConfig_ITC ((1UL<<15)) /**< Terminal count interrupt mask*/
+#define GPDMA_DMACCxConfig_L ((1UL<<16)) /**< Lock*/
+#define GPDMA_DMACCxConfig_A ((1UL<<17)) /**< Active*/
+#define GPDMA_DMACCxConfig_H ((1UL<<18)) /**< Halt*/
+/** DMA Channel Configuration registers bit mask */
+#define GPDMA_DMACCxConfig_BITMASK ((0x7FFFF))
+
+/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
+/* Macros check GPDMA channel */
+#define PARAM_GPDMA_CHANNEL(n) (n<=7)
+
+/* Macros check GPDMA connection type */
+#define PARAM_GPDMA_CONN(n) ((n==GPDMA_CONN_SSP0_Tx) || (n==GPDMA_CONN_SSP0_Rx) \
+|| (n==GPDMA_CONN_SSP1_Tx) || (n==GPDMA_CONN_SSP1_Rx) \
+|| (n==GPDMA_CONN_ADC) || (n==GPDMA_CONN_I2S_Channel_0) \
+|| (n==GPDMA_CONN_I2S_Channel_1) || (n==GPDMA_CONN_DAC) \
+|| (n==GPDMA_CONN_UART0_Tx) || (n==GPDMA_CONN_UART0_Rx) \
+|| (n==GPDMA_CONN_UART1_Tx) || (n==GPDMA_CONN_UART1_Rx) \
+|| (n==GPDMA_CONN_UART2_Tx) || (n==GPDMA_CONN_UART2_Rx) \
+|| (n==GPDMA_CONN_UART3_Tx) || (n==GPDMA_CONN_UART3_Rx) \
+|| (n==GPDMA_CONN_MAT0_0) || (n==GPDMA_CONN_MAT0_1) \
+|| (n==GPDMA_CONN_MAT1_0) || (n==GPDMA_CONN_MAT1_1) \
+|| (n==GPDMA_CONN_MAT2_0) || (n==GPDMA_CONN_MAT2_1) \
+|| (n==GPDMA_CONN_MAT3_0) || (n==GPDMA_CONN_MAT3_1))
+
+/* Macros check GPDMA burst size type */
+#define PARAM_GPDMA_BSIZE(n) ((n==GPDMA_BSIZE_1) || (n==GPDMA_BSIZE_4) \
+|| (n==GPDMA_BSIZE_8) || (n==GPDMA_BSIZE_16) \
+|| (n==GPDMA_BSIZE_32) || (n==GPDMA_BSIZE_64) \
+|| (n==GPDMA_BSIZE_128) || (n==GPDMA_BSIZE_256))
+
+/* Macros check GPDMA width type */
+#define PARAM_GPDMA_WIDTH(n) ((n==GPDMA_WIDTH_BYTE) || (n==GPDMA_WIDTH_HALFWORD) \
+|| (n==GPDMA_WIDTH_WORD))
+
+/* Macros check GPDMA status type */
+#define PARAM_GPDMA_STAT(n) ((n==GPDMA_STAT_INT) || (n==GPDMA_STAT_INTTC) \
+|| (n==GPDMA_STAT_INTERR) || (n==GPDMA_STAT_RAWINTTC) \
+|| (n==GPDMA_STAT_RAWINTERR) || (n==GPDMA_STAT_ENABLED_CH))
+
+/* Macros check GPDMA transfer type */
+#define PARAM_GPDMA_TRANSFERTYPE(n) ((n==GPDMA_TRANSFERTYPE_M2M)||(n==GPDMA_TRANSFERTYPE_M2P) \
+||(n==GPDMA_TRANSFERTYPE_P2M)||(n==GPDMA_TRANSFERTYPE_P2P))
+
+/* Macros check GPDMA state clear type */
+#define PARAM_GPDMA_STATCLR(n) ((n==GPDMA_STATCLR_INTTC) || (n==GPDMA_STATCLR_INTERR))
+
+/* Macros check GPDMA request select type */
+#define PARAM_GPDMA_REQSEL(n) ((n==GPDMA_REQSEL_UART) || (n==GPDMA_REQSEL_TIMER))
+/**
+ * @}
+ */
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup GPDMA_Public_Types GPDMA Public Types
+ * @{
+ */
+
+/**
+ * @brief GPDMA Status enumeration
+ */
+typedef enum {
+ GPDMA_STAT_INT, /**< GPDMA Interrupt Status */
+ GPDMA_STAT_INTTC, /**< GPDMA Interrupt Terminal Count Request Status */
+ GPDMA_STAT_INTERR, /**< GPDMA Interrupt Error Status */
+ GPDMA_STAT_RAWINTTC, /**< GPDMA Raw Interrupt Terminal Count Status */
+ GPDMA_STAT_RAWINTERR, /**< GPDMA Raw Error Interrupt Status */
+ GPDMA_STAT_ENABLED_CH /**< GPDMA Enabled Channel Status */
+} GPDMA_Status_Type;
+
+/**
+ * @brief GPDMA Interrupt clear status enumeration
+ */
+typedef enum{
+ GPDMA_STATCLR_INTTC, /**< GPDMA Interrupt Terminal Count Request Clear */
+ GPDMA_STATCLR_INTERR /**< GPDMA Interrupt Error Clear */
+}GPDMA_StateClear_Type;
+
+/**
+ * @brief GPDMA Channel configuration structure type definition
+ */
+typedef struct {
+ uint32_t ChannelNum; /**< DMA channel number, should be in
+ range from 0 to 7.
+ Note: DMA channel 0 has the highest priority
+ and DMA channel 7 the lowest priority.
+ */
+ uint32_t TransferSize; /**< Length/Size of transfer */
+ uint32_t TransferWidth; /**< Transfer width - used for TransferType is GPDMA_TRANSFERTYPE_M2M only */
+ uint32_t SrcMemAddr; /**< Physical Source Address, used in case TransferType is chosen as
+ GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_M2P */
+ uint32_t DstMemAddr; /**< Physical Destination Address, used in case TransferType is chosen as
+ GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_P2M */
+ uint32_t TransferType; /**< Transfer Type, should be one of the following:
+ - GPDMA_TRANSFERTYPE_M2M: Memory to memory - DMA control
+ - GPDMA_TRANSFERTYPE_M2P: Memory to peripheral - DMA control
+ - GPDMA_TRANSFERTYPE_P2M: Peripheral to memory - DMA control
+ - GPDMA_TRANSFERTYPE_P2P: Source peripheral to destination peripheral - DMA control
+ */
+ uint32_t SrcConn; /**< Peripheral Source Connection type, used in case TransferType is chosen as
+ GPDMA_TRANSFERTYPE_P2M or GPDMA_TRANSFERTYPE_P2P, should be one of
+ following:
+ - GPDMA_CONN_SSP0_Tx: SSP0, Tx
+ - GPDMA_CONN_SSP0_Rx: SSP0, Rx
+ - GPDMA_CONN_SSP1_Tx: SSP1, Tx
+ - GPDMA_CONN_SSP1_Rx: SSP1, Rx
+ - GPDMA_CONN_ADC: ADC
+ - GPDMA_CONN_I2S_Channel_0: I2S Channel 0
+ - GPDMA_CONN_I2S_Channel_1: I2S Channel 1
+ - GPDMA_CONN_DAC: DAC
+ - GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0
+ - GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1
+ - GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0
+ - GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1
+ - GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0
+ - GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1
+ - GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0
+ - GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1
+ */
+ uint32_t DstConn; /**< Peripheral Destination Connection type, used in case TransferType is chosen as
+ GPDMA_TRANSFERTYPE_M2P or GPDMA_TRANSFERTYPE_P2P, should be one of
+ following:
+ - GPDMA_CONN_SSP0_Tx: SSP0, Tx
+ - GPDMA_CONN_SSP0_Rx: SSP0, Rx
+ - GPDMA_CONN_SSP1_Tx: SSP1, Tx
+ - GPDMA_CONN_SSP1_Rx: SSP1, Rx
+ - GPDMA_CONN_ADC: ADC
+ - GPDMA_CONN_I2S_Channel_0: I2S Channel 0
+ - GPDMA_CONN_I2S_Channel_1: I2S Channel 1
+ - GPDMA_CONN_DAC: DAC
+ - GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0
+ - GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1
+ - GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0
+ - GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1
+ - GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0
+ - GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1
+ - GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0
+ - GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1
+ */
+ uint32_t DMALLI; /**< Linker List Item structure data address
+ if there's no Linker List, set as '0'
+ */
+} GPDMA_Channel_CFG_Type;
+
+/**
+ * @brief GPDMA Linker List Item structure type definition
+ */
+typedef struct {
+ uint32_t SrcAddr; /**< Source Address */
+ uint32_t DstAddr; /**< Destination address */
+ uint32_t NextLLI; /**< Next LLI address, otherwise set to '0' */
+ uint32_t Control; /**< GPDMA Control of this LLI */
+} GPDMA_LLI_Type;
+
+
+/**
+ * @}
+ */
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup GPDMA_Public_Functions GPDMA Public Functions
+ * @{
+ */
+
+void GPDMA_Init(void);
+//Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig, fnGPDMACbs_Type *pfnGPDMACbs);
+Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig);
+IntStatus GPDMA_IntGetStatus(GPDMA_Status_Type type, uint8_t channel);
+void GPDMA_ClearIntPending(GPDMA_StateClear_Type type, uint8_t channel);
+void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState);
+//void GPDMA_IntHandler(void);
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC17XX_GPDMA_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/src/shared/cmsis/Drivers/include/lpc17xx_gpio.h b/src/shared/cmsis/Drivers/include/lpc17xx_gpio.h
@@ -0,0 +1,177 @@
+/**********************************************************************
+* $Id$ lpc17xx_gpio.h 2010-06-18
+*//**
+* @file lpc17xx_gpio.h
+* @brief Contains all macro definitions and function prototypes
+* support for GPDMA firmware library on LPC17xx
+* @version 3.0
+* @date 18. June. 2010
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2010, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup GPIO GPIO (General Purpose Input/Output)
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_GPIO_H_
+#define LPC17XX_GPIO_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup GPIO_Public_Macros GPIO Public Macros
+ * @{
+ */
+
+/** Fast GPIO port 0 byte accessible definition */
+#define GPIO0_Byte ((GPIO_Byte_TypeDef *)(LPC_GPIO0_BASE))
+/** Fast GPIO port 1 byte accessible definition */
+#define GPIO1_Byte ((GPIO_Byte_TypeDef *)(LPC_GPIO1_BASE))
+/** Fast GPIO port 2 byte accessible definition */
+#define GPIO2_Byte ((GPIO_Byte_TypeDef *)(LPC_GPIO2_BASE))
+/** Fast GPIO port 3 byte accessible definition */
+#define GPIO3_Byte ((GPIO_Byte_TypeDef *)(LPC_GPIO3_BASE))
+/** Fast GPIO port 4 byte accessible definition */
+#define GPIO4_Byte ((GPIO_Byte_TypeDef *)(LPC_GPIO4_BASE))
+
+
+/** Fast GPIO port 0 half-word accessible definition */
+#define GPIO0_HalfWord ((GPIO_HalfWord_TypeDef *)(LPC_GPIO0_BASE))
+/** Fast GPIO port 1 half-word accessible definition */
+#define GPIO1_HalfWord ((GPIO_HalfWord_TypeDef *)(LPC_GPIO1_BASE))
+/** Fast GPIO port 2 half-word accessible definition */
+#define GPIO2_HalfWord ((GPIO_HalfWord_TypeDef *)(LPC_GPIO2_BASE))
+/** Fast GPIO port 3 half-word accessible definition */
+#define GPIO3_HalfWord ((GPIO_HalfWord_TypeDef *)(LPC_GPIO3_BASE))
+/** Fast GPIO port 4 half-word accessible definition */
+#define GPIO4_HalfWord ((GPIO_HalfWord_TypeDef *)(LPC_GPIO4_BASE))
+
+/**
+ * @}
+ */
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup GPIO_Public_Types GPIO Public Types
+ * @{
+ */
+
+/**
+ * @brief Fast GPIO port byte type definition
+ */
+typedef struct {
+ __IO uint8_t FIODIR[4]; /**< FIO direction register in byte-align */
+ uint32_t RESERVED0[3]; /**< Reserved */
+ __IO uint8_t FIOMASK[4]; /**< FIO mask register in byte-align */
+ __IO uint8_t FIOPIN[4]; /**< FIO pin register in byte align */
+ __IO uint8_t FIOSET[4]; /**< FIO set register in byte-align */
+ __O uint8_t FIOCLR[4]; /**< FIO clear register in byte-align */
+} GPIO_Byte_TypeDef;
+
+
+/**
+ * @brief Fast GPIO port half-word type definition
+ */
+typedef struct {
+ __IO uint16_t FIODIRL; /**< FIO direction register lower halfword part */
+ __IO uint16_t FIODIRU; /**< FIO direction register upper halfword part */
+ uint32_t RESERVED0[3]; /**< Reserved */
+ __IO uint16_t FIOMASKL; /**< FIO mask register lower halfword part */
+ __IO uint16_t FIOMASKU; /**< FIO mask register upper halfword part */
+ __IO uint16_t FIOPINL; /**< FIO pin register lower halfword part */
+ __IO uint16_t FIOPINU; /**< FIO pin register upper halfword part */
+ __IO uint16_t FIOSETL; /**< FIO set register lower halfword part */
+ __IO uint16_t FIOSETU; /**< FIO set register upper halfword part */
+ __O uint16_t FIOCLRL; /**< FIO clear register lower halfword part */
+ __O uint16_t FIOCLRU; /**< FIO clear register upper halfword part */
+} GPIO_HalfWord_TypeDef;
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup GPIO_Public_Functions GPIO Public Functions
+ * @{
+ */
+
+/* GPIO style ------------------------------- */
+void GPIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t dir);
+void GPIO_SetValue(uint8_t portNum, uint32_t bitValue);
+void GPIO_ClearValue(uint8_t portNum, uint32_t bitValue);
+uint32_t GPIO_ReadValue(uint8_t portNum);
+void GPIO_IntCmd(uint8_t portNum, uint32_t bitValue, uint8_t edgeState);
+FunctionalState GPIO_GetIntStatus(uint8_t portNum, uint32_t pinNum, uint8_t edgeState);
+void GPIO_ClearInt(uint8_t portNum, uint32_t bitValue);
+
+/* FIO (word-accessible) style ------------------------------- */
+void FIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t dir);
+void FIO_SetValue(uint8_t portNum, uint32_t bitValue);
+void FIO_ClearValue(uint8_t portNum, uint32_t bitValue);
+uint32_t FIO_ReadValue(uint8_t portNum);
+void FIO_SetMask(uint8_t portNum, uint32_t bitValue, uint8_t maskValue);
+void FIO_IntCmd(uint8_t portNum, uint32_t bitValue, uint8_t edgeState);
+FunctionalState FIO_GetIntStatus(uint8_t portNum, uint32_t pinNum, uint8_t edgeState);
+void FIO_ClearInt(uint8_t portNum, uint32_t pinNum);
+
+/* FIO (halfword-accessible) style ------------------------------- */
+void FIO_HalfWordSetDir(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue, uint8_t dir);
+void FIO_HalfWordSetMask(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue, uint8_t maskValue);
+void FIO_HalfWordSetValue(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue);
+void FIO_HalfWordClearValue(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue);
+uint16_t FIO_HalfWordReadValue(uint8_t portNum, uint8_t halfwordNum);
+
+/* FIO (byte-accessible) style ------------------------------- */
+void FIO_ByteSetDir(uint8_t portNum, uint8_t byteNum, uint8_t bitValue, uint8_t dir);
+void FIO_ByteSetMask(uint8_t portNum, uint8_t byteNum, uint8_t bitValue, uint8_t maskValue);
+void FIO_ByteSetValue(uint8_t portNum, uint8_t byteNum, uint8_t bitValue);
+void FIO_ByteClearValue(uint8_t portNum, uint8_t byteNum, uint8_t bitValue);
+uint8_t FIO_ByteReadValue(uint8_t portNum, uint8_t byteNum);
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC17XX_GPIO_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/src/shared/cmsis/Drivers/include/lpc17xx_i2c.h b/src/shared/cmsis/Drivers/include/lpc17xx_i2c.h
@@ -0,0 +1,435 @@
+/**********************************************************************
+* $Id$ lpc17xx_i2c.h 2010-05-21
+*//**
+* @file lpc17xx_i2c.h
+* @brief Contains all macro definitions and function prototypes
+* support for I2C firmware library on LPC17xx
+* @version 2.0
+* @date 21. May. 2010
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2010, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup I2C I2C (Inter-IC Control bus)
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_I2C_H_
+#define LPC17XX_I2C_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup I2C_Private_Macros I2C Private Macros
+ * @{
+ */
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/*******************************************************************//**
+ * I2C Control Set register description
+ *********************************************************************/
+#define I2C_I2CONSET_AA ((0x04)) /*!< Assert acknowledge flag */
+#define I2C_I2CONSET_SI ((0x08)) /*!< I2C interrupt flag */
+#define I2C_I2CONSET_STO ((0x10)) /*!< STOP flag */
+#define I2C_I2CONSET_STA ((0x20)) /*!< START flag */
+#define I2C_I2CONSET_I2EN ((0x40)) /*!< I2C interface enable */
+
+/*******************************************************************//**
+ * I2C Control Clear register description
+ *********************************************************************/
+/** Assert acknowledge Clear bit */
+#define I2C_I2CONCLR_AAC ((1<<2))
+/** I2C interrupt Clear bit */
+#define I2C_I2CONCLR_SIC ((1<<3))
+/** I2C STOP Clear bit */
+#define I2C_I2CONCLR_STOC ((1<<4))
+/** START flag Clear bit */
+#define I2C_I2CONCLR_STAC ((1<<5))
+/** I2C interface Disable bit */
+#define I2C_I2CONCLR_I2ENC ((1<<6))
+
+/********************************************************************//**
+ * I2C Status Code definition (I2C Status register)
+ *********************************************************************/
+/* Return Code in I2C status register */
+#define I2C_STAT_CODE_BITMASK ((0xF8))
+
+/* I2C return status code definitions ----------------------------- */
+
+/** No relevant information */
+#define I2C_I2STAT_NO_INF ((0xF8))
+
+/** Bus Error */
+#define I2C_I2STAT_BUS_ERROR ((0x00))
+
+/* Master transmit mode -------------------------------------------- */
+/** A start condition has been transmitted */
+#define I2C_I2STAT_M_TX_START ((0x08))
+
+/** A repeat start condition has been transmitted */
+#define I2C_I2STAT_M_TX_RESTART ((0x10))
+
+/** SLA+W has been transmitted, ACK has been received */
+#define I2C_I2STAT_M_TX_SLAW_ACK ((0x18))
+
+/** SLA+W has been transmitted, NACK has been received */
+#define I2C_I2STAT_M_TX_SLAW_NACK ((0x20))
+
+/** Data has been transmitted, ACK has been received */
+#define I2C_I2STAT_M_TX_DAT_ACK ((0x28))
+
+/** Data has been transmitted, NACK has been received */
+#define I2C_I2STAT_M_TX_DAT_NACK ((0x30))
+
+/** Arbitration lost in SLA+R/W or Data bytes */
+#define I2C_I2STAT_M_TX_ARB_LOST ((0x38))
+
+/* Master receive mode -------------------------------------------- */
+/** A start condition has been transmitted */
+#define I2C_I2STAT_M_RX_START ((0x08))
+
+/** A repeat start condition has been transmitted */
+#define I2C_I2STAT_M_RX_RESTART ((0x10))
+
+/** Arbitration lost */
+#define I2C_I2STAT_M_RX_ARB_LOST ((0x38))
+
+/** SLA+R has been transmitted, ACK has been received */
+#define I2C_I2STAT_M_RX_SLAR_ACK ((0x40))
+
+/** SLA+R has been transmitted, NACK has been received */
+#define I2C_I2STAT_M_RX_SLAR_NACK ((0x48))
+
+/** Data has been received, ACK has been returned */
+#define I2C_I2STAT_M_RX_DAT_ACK ((0x50))
+
+/** Data has been received, NACK has been return */
+#define I2C_I2STAT_M_RX_DAT_NACK ((0x58))
+
+/* Slave receive mode -------------------------------------------- */
+/** Own slave address has been received, ACK has been returned */
+#define I2C_I2STAT_S_RX_SLAW_ACK ((0x60))
+
+/** Arbitration lost in SLA+R/W as master */
+#define I2C_I2STAT_S_RX_ARB_LOST_M_SLA ((0x68))
+
+/** General call address has been received, ACK has been returned */
+#define I2C_I2STAT_S_RX_GENCALL_ACK ((0x70))
+
+/** Arbitration lost in SLA+R/W (GENERAL CALL) as master */
+#define I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL ((0x78))
+
+/** Previously addressed with own SLV address;
+ * Data has been received, ACK has been return */
+#define I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK ((0x80))
+
+/** Previously addressed with own SLA;
+ * Data has been received and NOT ACK has been return */
+#define I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK ((0x88))
+
+/** Previously addressed with General Call;
+ * Data has been received and ACK has been return */
+#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK ((0x90))
+
+/** Previously addressed with General Call;
+ * Data has been received and NOT ACK has been return */
+#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK ((0x98))
+
+/** A STOP condition or repeated START condition has
+ * been received while still addressed as SLV/REC
+ * (Slave Receive) or SLV/TRX (Slave Transmit) */
+#define I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX ((0xA0))
+
+/** Slave transmit mode */
+/** Own SLA+R has been received, ACK has been returned */
+#define I2C_I2STAT_S_TX_SLAR_ACK ((0xA8))
+
+/** Arbitration lost in SLA+R/W as master */
+#define I2C_I2STAT_S_TX_ARB_LOST_M_SLA ((0xB0))
+
+/** Data has been transmitted, ACK has been received */
+#define I2C_I2STAT_S_TX_DAT_ACK ((0xB8))
+
+/** Data has been transmitted, NACK has been received */
+#define I2C_I2STAT_S_TX_DAT_NACK ((0xC0))
+
+/** Last data byte in I2DAT has been transmitted (AA = 0);
+ ACK has been received */
+#define I2C_I2STAT_S_TX_LAST_DAT_ACK ((0xC8))
+
+/** Time out in case of using I2C slave mode */
+#define I2C_SLAVE_TIME_OUT 0x10000UL
+
+/********************************************************************//**
+ * I2C Data register definition
+ *********************************************************************/
+/** Mask for I2DAT register*/
+#define I2C_I2DAT_BITMASK ((0xFF))
+
+/** Idle data value will be send out in slave mode in case of the actual
+ * expecting data requested from the master is greater than its sending data
+ * length that can be supported */
+#define I2C_I2DAT_IDLE_CHAR (0xFF)
+
+/********************************************************************//**
+ * I2C Monitor mode control register description
+ *********************************************************************/
+#define I2C_I2MMCTRL_MM_ENA ((1<<0)) /**< Monitor mode enable */
+#define I2C_I2MMCTRL_ENA_SCL ((1<<1)) /**< SCL output enable */
+#define I2C_I2MMCTRL_MATCH_ALL ((1<<2)) /**< Select interrupt register match */
+#define I2C_I2MMCTRL_BITMASK ((0x07)) /**< Mask for I2MMCTRL register */
+
+/********************************************************************//**
+ * I2C Data buffer register description
+ *********************************************************************/
+/** I2C Data buffer register bit mask */
+#define I2DATA_BUFFER_BITMASK ((0xFF))
+
+/********************************************************************//**
+ * I2C Slave Address registers definition
+ *********************************************************************/
+/** General Call enable bit */
+#define I2C_I2ADR_GC ((1<<0))
+
+/** I2C Slave Address registers bit mask */
+#define I2C_I2ADR_BITMASK ((0xFF))
+
+/********************************************************************//**
+ * I2C Mask Register definition
+ *********************************************************************/
+/** I2C Mask Register mask field */
+#define I2C_I2MASK_MASK(n) ((n&0xFE))
+
+/********************************************************************//**
+ * I2C SCL HIGH duty cycle Register definition
+ *********************************************************************/
+/** I2C SCL HIGH duty cycle Register bit mask */
+#define I2C_I2SCLH_BITMASK ((0xFFFF))
+
+/********************************************************************//**
+ * I2C SCL LOW duty cycle Register definition
+ *********************************************************************/
+/** I2C SCL LOW duty cycle Register bit mask */
+#define I2C_I2SCLL_BITMASK ((0xFFFF))
+
+
+/* I2C status values */
+#define I2C_SETUP_STATUS_ARBF (1<<8) /**< Arbitration false */
+#define I2C_SETUP_STATUS_NOACKF (1<<9) /**< No ACK returned */
+#define I2C_SETUP_STATUS_DONE (1<<10) /**< Status DONE */
+
+/*********************************************************************//**
+ * I2C monitor control configuration defines
+ **********************************************************************/
+#define I2C_MONITOR_CFG_SCL_OUTPUT I2C_I2MMCTRL_ENA_SCL /**< SCL output enable */
+#define I2C_MONITOR_CFG_MATCHALL I2C_I2MMCTRL_MATCH_ALL /**< Select interrupt register match */
+
+/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
+/* Macros check I2C slave address */
+#define PARAM_I2C_SLAVEADDR_CH(n) (n<=3)
+
+/** Macro to determine if it is valid SSP port number */
+#define PARAM_I2Cx(n) ((((uint32_t *)n)==((uint32_t *)LPC_I2C0)) \
+|| (((uint32_t *)n)==((uint32_t *)LPC_I2C1)) \
+|| (((uint32_t *)n)==((uint32_t *)LPC_I2C2)))
+
+/* Macros check I2C monitor configuration type */
+#define PARAM_I2C_MONITOR_CFG(n) ((n==I2C_MONITOR_CFG_SCL_OUTPUT) || (I2C_MONITOR_CFG_MATCHALL))
+
+/* I2C state handle return values */
+#define I2C_OK 0x00
+#define I2C_BYTE_SENT 0x01
+#define I2C_BYTE_RECV 0x02
+#define I2C_LAST_BYTE_RECV 0x04
+#define I2C_SEND_END 0x08
+#define I2C_RECV_END 0x10
+#define I2C_STA_STO_RECV 0x20
+
+#define I2C_ERR (0x10000000)
+#define I2C_NAK_RECV (0x10000000 |0x01)
+
+#define I2C_CheckError(ErrorCode) (ErrorCode & 0x10000000)
+
+/**
+ * @}
+ */
+
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup I2C_Public_Types I2C Public Types
+ * @{
+ */
+
+typedef enum
+{
+ I2C_0 = 0,
+ I2C_1,
+ I2C_2
+} en_I2C_unitId;
+
+typedef enum
+{
+ I2C_MASTER_MODE,
+ I2C_SLAVE_MODE,
+ I2C_GENERAL_MODE,
+} en_I2C_Mode;
+/**
+ * @brief I2C Own slave address setting structure
+ */
+typedef struct {
+ uint8_t SlaveAddrChannel; /**< Slave Address channel in I2C control,
+ should be in range from 0..3
+ */
+ uint8_t SlaveAddr_7bit; /**< Value of 7-bit slave address */
+ uint8_t GeneralCallState; /**< Enable/Disable General Call Functionality
+ when I2C control being in Slave mode, should be:
+ - ENABLE: Enable General Call function.
+ - DISABLE: Disable General Call function.
+ */
+ uint8_t SlaveAddrMaskValue; /**< Any bit in this 8-bit value (bit 7:1)
+ which is set to '1' will cause an automatic compare on
+ the corresponding bit of the received address when it
+ is compared to the SlaveAddr_7bit value associated with this
+ mask register. In other words, bits in SlaveAddr_7bit value
+ which are masked are not taken into account in determining
+ an address match
+ */
+} I2C_OWNSLAVEADDR_CFG_Type;
+
+
+/**
+ * @brief Master transfer setup data structure definitions
+ */
+typedef struct
+{
+ uint32_t sl_addr7bit; /**< Slave address in 7bit mode */
+ __IO uint8_t* tx_data; /**< Pointer to Transmit data - NULL if data transmit
+ is not used */
+ uint32_t tx_length; /**< Transmit data length - 0 if data transmit
+ is not used*/
+ __IO uint32_t tx_count; /**< Current Transmit data counter */
+ __IO uint8_t* rx_data; /**< Pointer to Receive data - NULL if data receive
+ is not used */
+ uint32_t rx_length; /**< Receive data length - 0 if data receive is
+ not used */
+ __IO uint32_t rx_count; /**< Current Receive data counter */
+ uint32_t retransmissions_max; /**< Max Re-Transmission value */
+ uint32_t retransmissions_count; /**< Current Re-Transmission counter */
+ __IO uint32_t status; /**< Current status of I2C activity */
+ void (*callback)(void); /**< Pointer to Call back function when transmission complete
+ used in interrupt transfer mode */
+} I2C_M_SETUP_Type;
+
+
+/**
+ * @brief Slave transfer setup data structure definitions
+ */
+typedef struct
+{
+ __IO uint8_t* tx_data;
+ uint32_t tx_length;
+ __IO uint32_t tx_count;
+ __IO uint8_t* rx_data;
+ uint32_t rx_length;
+ __IO uint32_t rx_count;
+ __IO uint32_t status;
+ void (*callback)(void);
+} I2C_S_SETUP_Type;
+
+/**
+ * @brief Transfer option type definitions
+ */
+typedef enum {
+ I2C_TRANSFER_POLLING = 0, /**< Transfer in polling mode */
+ I2C_TRANSFER_INTERRUPT /**< Transfer in interrupt mode */
+} I2C_TRANSFER_OPT_Type;
+
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup I2C_Public_Functions I2C Public Functions
+ * @{
+ */
+
+/* I2C Init/DeInit functions ---------- */
+void I2C_Init(LPC_I2C_TypeDef *I2Cx, uint32_t clockrate);
+void I2C_DeInit(LPC_I2C_TypeDef* I2Cx);
+void I2C_Cmd(LPC_I2C_TypeDef* I2Cx, en_I2C_Mode Mode, FunctionalState NewState);
+
+/* I2C transfer data functions -------- */
+Status I2C_MasterTransferData(LPC_I2C_TypeDef *I2Cx, \
+ I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
+Status I2C_SlaveTransferData(LPC_I2C_TypeDef *I2Cx, \
+ I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
+uint32_t I2C_MasterTransferComplete(LPC_I2C_TypeDef *I2Cx);
+uint32_t I2C_SlaveTransferComplete(LPC_I2C_TypeDef *I2Cx);
+
+
+void I2C_SetOwnSlaveAddr(LPC_I2C_TypeDef *I2Cx, I2C_OWNSLAVEADDR_CFG_Type *OwnSlaveAddrConfigStruct);
+uint8_t I2C_GetLastStatusCode(LPC_I2C_TypeDef* I2Cx);
+
+/* I2C Monitor functions ---------------*/
+void I2C_MonitorModeConfig(LPC_I2C_TypeDef *I2Cx, uint32_t MonitorCfgType, FunctionalState NewState);
+void I2C_MonitorModeCmd(LPC_I2C_TypeDef *I2Cx, FunctionalState NewState);
+uint8_t I2C_MonitorGetDatabuffer(LPC_I2C_TypeDef *I2Cx);
+BOOL_8 I2C_MonitorHandler(LPC_I2C_TypeDef *I2Cx, uint8_t *buffer, uint32_t size);
+
+/* I2C Interrupt handler functions ------*/
+void I2C_IntCmd (LPC_I2C_TypeDef *I2Cx, Bool NewState);
+void I2C_MasterHandler (LPC_I2C_TypeDef *I2Cx);
+void I2C_SlaveHandler (LPC_I2C_TypeDef *I2Cx);
+int32_t I2C_MasterHanleStates(LPC_I2C_TypeDef *I2Cx, uint32_t CodeStatus, I2C_M_SETUP_Type *TransferCfg);
+int32_t I2C_SlaveHanleStates(LPC_I2C_TypeDef *I2Cx, uint32_t CodeStatus, I2C_S_SETUP_Type *TransferCfg);
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC17XX_I2C_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/src/shared/cmsis/Drivers/include/lpc17xx_i2s.h b/src/shared/cmsis/Drivers/include/lpc17xx_i2s.h
@@ -0,0 +1,384 @@
+/**********************************************************************
+* $Id$ lpc17xx_i2s.h 2011-06-06
+*//**
+* @file lpc17xx_i2s.h
+* @brief Contains all macro definitions and function prototypes
+* support for I2S firmware library on LPC17xx
+* @version 3.1
+* @date 06. June. 2011
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup I2S I2S (Inter-IC Sound bus)
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_I2S_H_
+#define LPC17XX_I2S_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup I2S_Public_Macros I2S Public Macros
+ * @{
+ */
+
+/*********************************************************************//**
+ * I2S configuration parameter defines
+ **********************************************************************/
+/** I2S Wordwidth bit */
+#define I2S_WORDWIDTH_8 ((uint32_t)(0))
+#define I2S_WORDWIDTH_16 ((uint32_t)(1))
+#define I2S_WORDWIDTH_32 ((uint32_t)(3))
+/** I2S Channel bit */
+#define I2S_STEREO ((uint32_t)(0))
+#define I2S_MONO ((uint32_t)(1))
+/** I2S Master/Slave mode bit */
+#define I2S_MASTER_MODE ((uint8_t)(0))
+#define I2S_SLAVE_MODE ((uint8_t)(1))
+/** I2S Stop bit */
+#define I2S_STOP_ENABLE ((uint8_t)(1))
+#define I2S_STOP_DISABLE ((uint8_t)(0))
+/** I2S Reset bit */
+#define I2S_RESET_ENABLE ((uint8_t)(1))
+#define I2S_RESET_DISABLE ((uint8_t)(0))
+/** I2S Mute bit */
+#define I2S_MUTE_ENABLE ((uint8_t)(1))
+#define I2S_MUTE_DISABLE ((uint8_t)(0))
+/** I2S Transmit/Receive bit */
+#define I2S_TX_MODE ((uint8_t)(0))
+#define I2S_RX_MODE ((uint8_t)(1))
+/** I2S Clock Select bit */
+#define I2S_CLKSEL_FRDCLK ((uint8_t)(0))
+#define I2S_CLKSEL_MCLK ((uint8_t)(2))
+/** I2S 4-pin Mode bit */
+#define I2S_4PIN_ENABLE ((uint8_t)(1))
+#define I2S_4PIN_DISABLE ((uint8_t)(0))
+/** I2S MCLK Enable bit */
+#define I2S_MCLK_ENABLE ((uint8_t)(1))
+#define I2S_MCLK_DISABLE ((uint8_t)(0))
+/** I2S select DMA bit */
+#define I2S_DMA_1 ((uint8_t)(0))
+#define I2S_DMA_2 ((uint8_t)(1))
+
+/**
+ * @}
+ */
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup I2S_Private_Macros I2S Private Macros
+ * @{
+ */
+
+/*********************************************************************//**
+ * Macro defines for DAO-Digital Audio Output register
+ **********************************************************************/
+/** I2S wordwide - the number of bytes in data*/
+#define I2S_DAO_WORDWIDTH_8 ((uint32_t)(0)) /** 8 bit */
+#define I2S_DAO_WORDWIDTH_16 ((uint32_t)(1)) /** 16 bit */
+#define I2S_DAO_WORDWIDTH_32 ((uint32_t)(3)) /** 32 bit */
+/** I2S control mono or stereo format */
+#define I2S_DAO_MONO ((uint32_t)(1<<2))
+/** I2S control stop mode */
+#define I2S_DAO_STOP ((uint32_t)(1<<3))
+/** I2S control reset mode */
+#define I2S_DAO_RESET ((uint32_t)(1<<4))
+/** I2S control master/slave mode */
+#define I2S_DAO_SLAVE ((uint32_t)(1<<5))
+/** I2S word select half period minus one */
+#define I2S_DAO_WS_HALFPERIOD(n) ((uint32_t)(n<<6))
+/** I2S control mute mode */
+#define I2S_DAO_MUTE ((uint32_t)(1<<15))
+
+/*********************************************************************//**
+ * Macro defines for DAI-Digital Audio Input register
+**********************************************************************/
+/** I2S wordwide - the number of bytes in data*/
+#define I2S_DAI_WORDWIDTH_8 ((uint32_t)(0)) /** 8 bit */
+#define I2S_DAI_WORDWIDTH_16 ((uint32_t)(1)) /** 16 bit */
+#define I2S_DAI_WORDWIDTH_32 ((uint32_t)(3)) /** 32 bit */
+/** I2S control mono or stereo format */
+#define I2S_DAI_MONO ((uint32_t)(1<<2))
+/** I2S control stop mode */
+#define I2S_DAI_STOP ((uint32_t)(1<<3))
+/** I2S control reset mode */
+#define I2S_DAI_RESET ((uint32_t)(1<<4))
+/** I2S control master/slave mode */
+#define I2S_DAI_SLAVE ((uint32_t)(1<<5))
+/** I2S word select half period minus one (9 bits)*/
+#define I2S_DAI_WS_HALFPERIOD(n) ((uint32_t)((n&0x1FF)<<6))
+/** I2S control mute mode */
+#define I2S_DAI_MUTE ((uint32_t)(1<<15))
+
+/*********************************************************************//**
+ * Macro defines for STAT register (Status Feedback register)
+**********************************************************************/
+/** I2S Status Receive or Transmit Interrupt */
+#define I2S_STATE_IRQ ((uint32_t)(1))
+/** I2S Status Receive or Transmit DMA1 */
+#define I2S_STATE_DMA1 ((uint32_t)(1<<1))
+/** I2S Status Receive or Transmit DMA2 */
+#define I2S_STATE_DMA2 ((uint32_t)(1<<2))
+/** I2S Status Current level of the Receive FIFO (5 bits)*/
+#define I2S_STATE_RX_LEVEL(n) ((uint32_t)((n&1F)<<8))
+/** I2S Status Current level of the Transmit FIFO (5 bits)*/
+#define I2S_STATE_TX_LEVEL(n) ((uint32_t)((n&1F)<<16))
+
+/*********************************************************************//**
+ * Macro defines for DMA1 register (DMA1 Configuration register)
+**********************************************************************/
+/** I2S control DMA1 for I2S receive */
+#define I2S_DMA1_RX_ENABLE ((uint32_t)(1))
+/** I2S control DMA1 for I2S transmit */
+#define I2S_DMA1_TX_ENABLE ((uint32_t)(1<<1))
+/** I2S set FIFO level that trigger a receive DMA request on DMA1 */
+#define I2S_DMA1_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))
+/** I2S set FIFO level that trigger a transmit DMA request on DMA1 */
+#define I2S_DMA1_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))
+
+/*********************************************************************//**
+ * Macro defines for DMA2 register (DMA2 Configuration register)
+**********************************************************************/
+/** I2S control DMA2 for I2S receive */
+#define I2S_DMA2_RX_ENABLE ((uint32_t)(1))
+/** I2S control DMA1 for I2S transmit */
+#define I2S_DMA2_TX_ENABLE ((uint32_t)(1<<1))
+/** I2S set FIFO level that trigger a receive DMA request on DMA1 */
+#define I2S_DMA2_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))
+/** I2S set FIFO level that trigger a transmit DMA request on DMA1 */
+#define I2S_DMA2_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))
+
+/*********************************************************************//**
+* Macro defines for IRQ register (Interrupt Request Control register)
+**********************************************************************/
+/** I2S control I2S receive interrupt */
+#define I2S_IRQ_RX_ENABLE ((uint32_t)(1))
+/** I2S control I2S transmit interrupt */
+#define I2S_IRQ_TX_ENABLE ((uint32_t)(1<<1))
+/** I2S set the FIFO level on which to create an irq request */
+#define I2S_IRQ_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))
+/** I2S set the FIFO level on which to create an irq request */
+#define I2S_IRQ_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))
+
+/********************************************************************************//**
+ * Macro defines for TXRATE/RXRATE register (Transmit/Receive Clock Rate register)
+*********************************************************************************/
+/** I2S Transmit MCLK rate denominator */
+#define I2S_TXRATE_Y_DIVIDER(n) ((uint32_t)(n&0xFF))
+/** I2S Transmit MCLK rate denominator */
+#define I2S_TXRATE_X_DIVIDER(n) ((uint32_t)((n&0xFF)<<8))
+/** I2S Receive MCLK rate denominator */
+#define I2S_RXRATE_Y_DIVIDER(n) ((uint32_t)(n&0xFF))
+/** I2S Receive MCLK rate denominator */
+#define I2S_RXRATE_X_DIVIDER(n) ((uint32_t)((n&0xFF)<<8))
+
+/*************************************************************************************//**
+ * Macro defines for TXBITRATE & RXBITRATE register (Transmit/Receive Bit Rate register)
+**************************************************************************************/
+#define I2S_TXBITRATE(n) ((uint32_t)(n&0x3F))
+#define I2S_RXBITRATE(n) ((uint32_t)(n&0x3F))
+
+/**********************************************************************************//**
+ * Macro defines for TXMODE/RXMODE register (Transmit/Receive Mode Control register)
+************************************************************************************/
+/** I2S Transmit select clock source (2 bits)*/
+#define I2S_TXMODE_CLKSEL(n) ((uint32_t)(n&0x03))
+/** I2S Transmit control 4-pin mode */
+#define I2S_TXMODE_4PIN_ENABLE ((uint32_t)(1<<2))
+/** I2S Transmit control the TX_MCLK output */
+#define I2S_TXMODE_MCENA ((uint32_t)(1<<3))
+/** I2S Receive select clock source */
+#define I2S_RXMODE_CLKSEL(n) ((uint32_t)(n&0x03))
+/** I2S Receive control 4-pin mode */
+#define I2S_RXMODE_4PIN_ENABLE ((uint32_t)(1<<2))
+/** I2S Receive control the TX_MCLK output */
+#define I2S_RXMODE_MCENA ((uint32_t)(1<<3))
+
+
+/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
+/** Macro to determine if it is valid I2S peripheral */
+#define PARAM_I2Sx(n) (((uint32_t *)n)==((uint32_t *)LPC_I2S))
+/** Macro to check Data to send valid */
+#define PRAM_I2S_FREQ(freq) ((freq>=16000)&&(freq <= 96000))
+/* Macro check I2S word width type */
+#define PARAM_I2S_WORDWIDTH(n) ((n==I2S_WORDWIDTH_8)||(n==I2S_WORDWIDTH_16)\
+||(n==I2S_WORDWIDTH_32))
+/* Macro check I2S channel type */
+#define PARAM_I2S_CHANNEL(n) ((n==I2S_STEREO)||(n==I2S_MONO))
+/* Macro check I2S master/slave mode */
+#define PARAM_I2S_WS_SEL(n) ((n==I2S_MASTER_MODE)||(n==I2S_SLAVE_MODE))
+/* Macro check I2S stop mode */
+#define PARAM_I2S_STOP(n) ((n==I2S_STOP_ENABLE)||(n==I2S_STOP_DISABLE))
+/* Macro check I2S reset mode */
+#define PARAM_I2S_RESET(n) ((n==I2S_RESET_ENABLE)||(n==I2S_RESET_DISABLE))
+/* Macro check I2S reset mode */
+#define PARAM_I2S_MUTE(n) ((n==I2S_MUTE_ENABLE)||(n==I2S_MUTE_DISABLE))
+/* Macro check I2S transmit/receive mode */
+#define PARAM_I2S_TRX(n) ((n==I2S_TX_MODE)||(n==I2S_RX_MODE))
+/* Macro check I2S clock select mode */
+#define PARAM_I2S_CLKSEL(n) ((n==I2S_CLKSEL_FRDCLK)||(n==I2S_CLKSEL_MCLK))
+/* Macro check I2S 4-pin mode */
+#define PARAM_I2S_4PIN(n) ((n==I2S_4PIN_ENABLE)||(n==I2S_4PIN_DISABLE))
+/* Macro check I2S MCLK mode */
+#define PARAM_I2S_MCLK(n) ((n==I2S_MCLK_ENABLE)||(n==I2S_MCLK_DISABLE))
+/* Macro check I2S DMA mode */
+#define PARAM_I2S_DMA(n) ((n==I2S_DMA_1)||(n==I2S_DMA_2))
+/* Macro check I2S DMA depth value */
+#define PARAM_I2S_DMA_DEPTH(n) (n<=31)
+/* Macro check I2S irq level value */
+#define PARAM_I2S_IRQ_LEVEL(n) (n<=31)
+/* Macro check I2S half-period value */
+#define PARAM_I2S_HALFPERIOD(n) (n<512)
+/* Macro check I2S bit-rate value */
+#define PARAM_I2S_BITRATE(n) (n<=63)
+/**
+ * @}
+ */
+
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup I2S_Public_Types I2S Public Types
+ * @{
+ */
+
+/**
+ * @brief I2S configuration structure definition
+ */
+typedef struct {
+ uint8_t wordwidth; /** the number of bytes in data as follow:
+ -I2S_WORDWIDTH_8: 8 bit data
+ -I2S_WORDWIDTH_16: 16 bit data
+ -I2S_WORDWIDTH_32: 32 bit data */
+ uint8_t mono; /** Set mono/stereo mode, should be:
+ - I2S_STEREO: stereo mode
+ - I2S_MONO: mono mode */
+ uint8_t stop; /** Disables accesses on FIFOs, should be:
+ - I2S_STOP_ENABLE: enable stop mode
+ - I2S_STOP_DISABLE: disable stop mode */
+ uint8_t reset; /** Asynchronously reset tje transmit channel and FIFO, should be:
+ - I2S_RESET_ENABLE: enable reset mode
+ - I2S_RESET_DISABLE: disable reset mode */
+ uint8_t ws_sel; /** Set Master/Slave mode, should be:
+ - I2S_MASTER_MODE: I2S master mode
+ - I2S_SLAVE_MODE: I2S slave mode */
+ uint8_t mute; /** MUTE mode: when true, the transmit channel sends only zeroes, shoule be:
+ - I2S_MUTE_ENABLE: enable mute mode
+ - I2S_MUTE_DISABLE: disable mute mode */
+ uint8_t Reserved0[2];
+} I2S_CFG_Type;
+
+/**
+ * @brief I2S DMA configuration structure definition
+ */
+typedef struct {
+ uint8_t DMAIndex; /** Select DMA1 or DMA2, should be:
+ - I2S_DMA_1: DMA1
+ - I2S_DMA_2: DMA2 */
+ uint8_t depth; /** FIFO level that triggers a DMA request */
+ uint8_t Reserved0[2];
+}I2S_DMAConf_Type;
+
+/**
+ * @brief I2S mode configuration structure definition
+ */
+typedef struct{
+ uint8_t clksel; /** Clock source selection, should be:
+ - I2S_CLKSEL_FRDCLK: Select the fractional rate divider clock output
+ - I2S_CLKSEL_MCLK: Select the MCLK signal as the clock source */
+ uint8_t fpin; /** Select four pin mode, should be:
+ - I2S_4PIN_ENABLE: 4-pin enable
+ - I2S_4PIN_DISABLE: 4-pin disable */
+ uint8_t mcena; /** Select MCLK mode, should be:
+ - I2S_MCLK_ENABLE: MCLK enable for output
+ - I2S_MCLK_DISABLE: MCLK disable for output */
+ uint8_t Reserved;
+}I2S_MODEConf_Type;
+
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup I2S_Public_Functions I2S Public Functions
+ * @{
+ */
+/* I2S Init/DeInit functions ---------*/
+void I2S_Init(LPC_I2S_TypeDef *I2Sx);
+void I2S_DeInit(LPC_I2S_TypeDef *I2Sx);
+
+/* I2S configuration functions --------*/
+void I2S_Config(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, I2S_CFG_Type* ConfigStruct);
+Status I2S_FreqConfig(LPC_I2S_TypeDef *I2Sx, uint32_t Freq, uint8_t TRMode);
+void I2S_SetBitRate(LPC_I2S_TypeDef *I2Sx, uint8_t bitrate, uint8_t TRMode);
+void I2S_ModeConfig(LPC_I2S_TypeDef *I2Sx, I2S_MODEConf_Type* ModeConfig, uint8_t TRMode);
+uint8_t I2S_GetLevel(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
+
+/* I2S operate functions -------------*/
+void I2S_Send(LPC_I2S_TypeDef *I2Sx, uint32_t BufferData);
+uint32_t I2S_Receive(LPC_I2S_TypeDef* I2Sx);
+void I2S_Start(LPC_I2S_TypeDef *I2Sx);
+void I2S_Pause(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
+void I2S_Mute(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
+void I2S_Stop(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
+
+/* I2S DMA functions ----------------*/
+void I2S_DMAConfig(LPC_I2S_TypeDef *I2Sx, I2S_DMAConf_Type* DMAConfig, uint8_t TRMode);
+void I2S_DMACmd(LPC_I2S_TypeDef *I2Sx, uint8_t DMAIndex,uint8_t TRMode, FunctionalState NewState);
+
+/* I2S IRQ functions ----------------*/
+void I2S_IRQCmd(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode, FunctionalState NewState);
+void I2S_IRQConfig(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, uint8_t level);
+FunctionalState I2S_GetIRQStatus(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode);
+uint8_t I2S_GetIRQDepth(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode);
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* LPC17XX_SSP_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/src/shared/cmsis/Drivers/include/lpc17xx_iap.h b/src/shared/cmsis/Drivers/include/lpc17xx_iap.h
@@ -0,0 +1,153 @@
+/**********************************************************************
+* $Id$ lpc17xx_iap.h 2012-04-18
+*//**
+* @file lpc17xx_iap.h
+* @brief Contains all functions support for IAP
+* on lpc17xx
+* @version 1.0
+* @date 18. April. 2012
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+#ifndef _LPC17xx_IAP_H
+#define _LPC17xx_IAP_H
+#include "lpc_types.h"
+
+/** @defgroup IAP IAP (In Application Programming)
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+/** @defgroup IAP_Public_Macros IAP Public Macros
+ * @{
+ */
+
+/** IAP entry location */
+#define IAP_LOCATION (0x1FFF1FF1UL)
+
+/**
+ * @}
+ */
+
+/** @defgroup IAP_Public_Types IAP Public Types
+ * @{
+ */
+
+/**
+ * @brief IAP command code definitions
+ */
+typedef enum
+{
+ IAP_PREPARE = 50, // Prepare sector(s) for write operation
+ IAP_COPY_RAM2FLASH = 51, // Copy RAM to Flash
+ IAP_ERASE = 52, // Erase sector(s)
+ IAP_BLANK_CHECK = 53, // Blank check sector(s)
+ IAP_READ_PART_ID = 54, // Read chip part ID
+ IAP_READ_BOOT_VER = 55, // Read chip boot code version
+ IAP_COMPARE = 56, // Compare memory areas
+ IAP_REINVOKE_ISP = 57, // Reinvoke ISP
+ IAP_READ_SERIAL_NUMBER = 58, // Read serial number
+} IAP_COMMAND_CODE;
+
+/**
+ * @brief IAP status code definitions
+ */
+typedef enum
+{
+ CMD_SUCCESS, // Command is executed successfully.
+ INVALID_COMMAND, // Invalid command.
+ SRC_ADDR_ERROR, // Source address is not on a word boundary.
+ DST_ADDR_ERROR, // Destination address is not on a correct boundary.
+ SRC_ADDR_NOT_MAPPED, // Source address is not mapped in the memory map.
+ DST_ADDR_NOT_MAPPED, // Destination address is not mapped in the memory map.
+ COUNT_ERROR, // Byte count is not multiple of 4 or is not a permitted value.
+ INVALID_SECTOR, // Sector number is invalid.
+ SECTOR_NOT_BLANK, // Sector is not blank.
+ SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION, // Command to prepare sector for write operation was not executed.
+ COMPARE_ERROR, // Source and destination data is not same.
+ BUSY, // Flash programming hardware interface is busy.
+} IAP_STATUS_CODE;
+
+/**
+ * @brief IAP write length definitions
+ */
+typedef enum {
+ IAP_WRITE_256 = 256,
+ IAP_WRITE_512 = 512,
+ IAP_WRITE_1024 = 1024,
+ IAP_WRITE_4096 = 4096,
+} IAP_WRITE_SIZE;
+
+/**
+ * @brief IAP command structure
+ */
+typedef struct {
+ uint32_t cmd; // Command
+ uint32_t param[4]; // Parameters
+ uint32_t status; // status code
+ uint32_t result[4]; // Result
+} IAP_COMMAND_Type;
+
+/**
+ * @}
+ */
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup IAP_Public_Functions IAP Public Functions
+ * @{
+ */
+
+/** Get sector number of an address */
+uint32_t GetSecNum (uint32_t adr);
+/** Prepare sector(s) for write operation */
+IAP_STATUS_CODE PrepareSector(uint32_t start_sec, uint32_t end_sec);
+/** Copy RAM to Flash */
+IAP_STATUS_CODE CopyRAM2Flash(uint8_t * dest, uint8_t* source, IAP_WRITE_SIZE size);
+/** Prepare sector(s) for write operation */
+IAP_STATUS_CODE EraseSector(uint32_t start_sec, uint32_t end_sec);
+/** Blank check sectors */
+IAP_STATUS_CODE BlankCheckSector(uint32_t start_sec, uint32_t end_sec,
+ uint32_t *first_nblank_loc,
+ uint32_t *first_nblank_val);
+/** Read part identification number */
+IAP_STATUS_CODE ReadPartID(uint32_t *partID);
+/** Read boot code version */
+IAP_STATUS_CODE ReadBootCodeVer(uint8_t *major, uint8_t* minor);
+/** Read Device serial number */
+IAP_STATUS_CODE ReadDeviceSerialNum(uint32_t *uid);
+/** Compare memory */
+IAP_STATUS_CODE Compare(uint8_t *addr1, uint8_t *addr2, uint32_t size);
+/** Invoke ISP */
+void InvokeISP(void);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /*_LPC17xx_IAP_H*/
+
diff --git a/src/shared/cmsis/Drivers/include/lpc17xx_libcfg_default.h b/src/shared/cmsis/Drivers/include/lpc17xx_libcfg_default.h
@@ -0,0 +1,182 @@
+/**********************************************************************
+* $Id$ lpc17xx_libcfg_default.h 2010-05-21
+*//**
+* @file lpc17xx_libcfg_default.h
+* @brief Default Library configuration header file
+* @version 2.0
+* @date 21. May. 2010
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2010, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Library Configuration group ----------------------------------------------------------- */
+/** @defgroup LIBCFG_DEFAULT LIBCFG_DEFAULT (Default Library Configuration)
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_LIBCFG_DEFAULT_H_
+#define LPC17XX_LIBCFG_DEFAULT_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "lpc_types.h"
+
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup LIBCFG_DEFAULT_Public_Macros LIBCFG_DEFAULT Public Macros
+ * @{
+ */
+
+/************************** DEBUG MODE DEFINITIONS *********************************/
+/* Un-comment the line below to compile the library in DEBUG mode, this will expanse
+ the "CHECK_PARAM" macro in the FW library code */
+
+#define DEBUG
+
+
+/******************* PERIPHERAL FW LIBRARY CONFIGURATION DEFINITIONS ***********************/
+/* Comment the line below to disable the specific peripheral inclusion */
+
+/* DEBUG_FRAMWORK ------------------------------ */
+#define _DBGFWK
+
+/* GPIO ------------------------------- */
+#define _GPIO
+
+/* EXTI ------------------------------- */
+#define _EXTI
+
+/* UART ------------------------------- */
+#define _UART
+#define _UART0
+#define _UART1
+#define _UART2
+#define _UART3
+
+/* SPI ------------------------------- */
+#define _SPI
+
+/* SYSTICK --------------------------- */
+#define _SYSTICK
+
+/* SSP ------------------------------- */
+#define _SSP
+#define _SSP0
+#define _SSP1
+
+
+/* I2C ------------------------------- */
+#define _I2C
+#define _I2C0
+#define _I2C1
+#define _I2C2
+
+/* TIMER ------------------------------- */
+#define _TIM
+
+/* WDT ------------------------------- */
+#define _WDT
+
+
+/* GPDMA ------------------------------- */
+#define _GPDMA
+
+
+/* DAC ------------------------------- */
+#define _DAC
+
+/* DAC ------------------------------- */
+#define _ADC
+
+
+/* PWM ------------------------------- */
+#define _PWM
+#define _PWM1
+
+/* RTC ------------------------------- */
+#define _RTC
+
+/* I2S ------------------------------- */
+#define _I2S
+
+/* USB device ------------------------------- */
+#define _USBDEV
+#define _USB_DMA
+
+/* QEI ------------------------------- */
+#define _QEI
+
+/* MCPWM ------------------------------- */
+#define _MCPWM
+
+/* CAN--------------------------------*/
+#define _CAN
+
+/* RIT ------------------------------- */
+#define _RIT
+
+/* EMAC ------------------------------ */
+#define _EMAC
+
+/************************** GLOBAL/PUBLIC MACRO DEFINITIONS *********************************/
+
+#ifdef DEBUG
+/*******************************************************************************
+* @brief The CHECK_PARAM macro is used for function's parameters check.
+* It is used only if the library is compiled in DEBUG mode.
+* @param[in] expr - If expr is false, it calls check_failed() function
+* which reports the name of the source file and the source
+* line number of the call that failed.
+* - If expr is true, it returns no value.
+* @return None
+*******************************************************************************/
+#define CHECK_PARAM(expr) ((expr) ? (void)0 : check_failed((uint8_t *)__FILE__, __LINE__))
+#else
+#define CHECK_PARAM(expr)
+#endif /* DEBUG */
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup LIBCFG_DEFAULT_Public_Functions LIBCFG_DEFAULT Public Functions
+ * @{
+ */
+
+#ifdef DEBUG
+void check_failed(uint8_t *file, uint32_t line);
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* LPC17XX_LIBCFG_DEFAULT_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/src/shared/cmsis/Drivers/include/lpc17xx_mcpwm.h b/src/shared/cmsis/Drivers/include/lpc17xx_mcpwm.h
@@ -0,0 +1,329 @@
+/**********************************************************************
+* $Id$ lpc17xx_mcpwm.h 2010-05-21
+*//**
+* @file lpc17xx_mcpwm.h
+* @brief Contains all macro definitions and function prototypes
+* support for Motor Control PWM firmware library on LPC17xx
+* @version 2.0
+* @date 21. May. 2010
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2010, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup MCPWM MCPWM (Motor Control PWM)
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_MCPWM_H_
+#define LPC17XX_MCPWM_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup MCPWM_Public_Macros MCPWM Public Macros
+ * @{
+ */
+
+
+/** Edge aligned mode for channel in MCPWM */
+#define MCPWM_CHANNEL_EDGE_MODE ((uint32_t)(0))
+/** Center aligned mode for channel in MCPWM */
+#define MCPWM_CHANNEL_CENTER_MODE ((uint32_t)(1))
+
+/** Polarity of the MCOA and MCOB pins: Passive state is LOW, active state is HIGH */
+#define MCPWM_CHANNEL_PASSIVE_LO ((uint32_t)(0))
+/** Polarity of the MCOA and MCOB pins: Passive state is HIGH, active state is LOW */
+#define MCPWM_CHANNEL_PASSIVE_HI ((uint32_t)(1))
+
+/* Output Patent in 3-phase DC mode, the internal MCOA0 signal is routed to any or all of
+ * the six output pins under the control of the bits in this register */
+#define MCPWM_PATENT_A0 ((uint32_t)(1<<0)) /**< MCOA0 tracks internal MCOA0 */
+#define MCPWM_PATENT_B0 ((uint32_t)(1<<1)) /**< MCOB0 tracks internal MCOA0 */
+#define MCPWM_PATENT_A1 ((uint32_t)(1<<2)) /**< MCOA1 tracks internal MCOA0 */
+#define MCPWM_PATENT_B1 ((uint32_t)(1<<3)) /**< MCOB1 tracks internal MCOA0 */
+#define MCPWM_PATENT_A2 ((uint32_t)(1<<4)) /**< MCOA2 tracks internal MCOA0 */
+#define MCPWM_PATENT_B2 ((uint32_t)(1<<5)) /**< MCOB2 tracks internal MCOA0 */
+
+/* Interrupt type in MCPWM */
+/** Limit interrupt for channel (0) */
+#define MCPWM_INTFLAG_LIM0 MCPWM_INT_ILIM(0)
+/** Match interrupt for channel (0) */
+#define MCPWM_INTFLAG_MAT0 MCPWM_INT_IMAT(0)
+/** Capture interrupt for channel (0) */
+#define MCPWM_INTFLAG_CAP0 MCPWM_INT_ICAP(0)
+
+/** Limit interrupt for channel (1) */
+#define MCPWM_INTFLAG_LIM1 MCPWM_INT_ILIM(1)
+/** Match interrupt for channel (1) */
+#define MCPWM_INTFLAG_MAT1 MCPWM_INT_IMAT(1)
+/** Capture interrupt for channel (1) */
+#define MCPWM_INTFLAG_CAP1 MCPWM_INT_ICAP(1)
+
+/** Limit interrupt for channel (2) */
+#define MCPWM_INTFLAG_LIM2 MCPWM_INT_ILIM(2)
+/** Match interrupt for channel (2) */
+#define MCPWM_INTFLAG_MAT2 MCPWM_INT_IMAT(2)
+/** Capture interrupt for channel (2) */
+#define MCPWM_INTFLAG_CAP2 MCPWM_INT_ICAP(2)
+
+/** Fast abort interrupt */
+#define MCPWM_INTFLAG_ABORT MCPWM_INT_ABORT
+
+/**
+ * @}
+ */
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup MCPWM_Private_Macros MCPWM Private Macros
+ * @{
+ */
+
+/*********************************************************************//**
+ * Macro defines for MCPWM Control register
+ **********************************************************************/
+/* MCPWM Control register, these macro definitions below can be applied for these
+ * register type:
+ * - MCPWM Control read address
+ * - MCPWM Control set address
+ * - MCPWM Control clear address
+ */
+#define MCPWM_CON_RUN(n) ((n<=2) ? ((uint32_t)(1<<((n*8)+0))) : (0)) /**< Stops/starts timer channel n */
+#define MCPWM_CON_CENTER(n) ((n<=2) ? ((uint32_t)(1<<((n*8)+1))) : (0)) /**< Edge/center aligned operation for channel n */
+#define MCPWM_CON_POLAR(n) ((n<=2) ? ((uint32_t)(1<<((n*8)+2))) : (0)) /**< Select polarity of the MCOAn and MCOBn pin */
+#define MCPWM_CON_DTE(n) ((n<=2) ? ((uint32_t)(1<<((n*8)+3))) : (0)) /**< Control the dead-time feature for channel n */
+#define MCPWM_CON_DISUP(n) ((n<=2) ? ((uint32_t)(1<<((n*8)+4))) : (0)) /**< Enable/Disable update of functional register for channel n */
+#define MCPWM_CON_INVBDC ((uint32_t)(1<<29)) /**< Control the polarity for all 3 channels */
+#define MCPWM_CON_ACMODE ((uint32_t)(1<<30)) /**< 3-phase AC mode select */
+#define MCPWM_CON_DCMODE ((uint32_t)(0x80000000)) /**< 3-phase DC mode select */
+
+/*********************************************************************//**
+ * Macro defines for MCPWM Capture Control register
+ **********************************************************************/
+/* Capture Control register, these macro definitions below can be applied for these
+ * register type:
+ * - MCPWM Capture Control read address
+ * - MCPWM Capture Control set address
+ * - MCPWM Capture control clear address
+ */
+/** Enables/Disable channel (cap) capture event on a rising edge on MCI(mci) */
+#define MCPWM_CAPCON_CAPMCI_RE(cap,mci) (((cap<=2)&&(mci<=2)) ? ((uint32_t)(1<<((cap*6)+(mci*2)+0))) : (0))
+/** Enables/Disable channel (cap) capture event on a falling edge on MCI(mci) */
+#define MCPWM_CAPCON_CAPMCI_FE(cap,mci) (((cap<=2)&&(mci<=2)) ? ((uint32_t)(1<<((cap*6)+(mci*2)+1))) : (0))
+/** TC(n) is reset by channel (n) capture event */
+#define MCPWM_CAPCON_RT(n) ((n<=2) ? ((uint32_t)(1<<(18+(n)))) : (0))
+/** Hardware noise filter: channel (n) capture events are delayed */
+#define MCPWM_CAPCON_HNFCAP(n) ((n<=2) ? ((uint32_t)(1<<(21+(n)))) : (0))
+
+/*********************************************************************//**
+ * Macro defines for MCPWM Interrupt register
+ **********************************************************************/
+/* Interrupt registers, these macro definitions below can be applied for these
+ * register type:
+ * - MCPWM Interrupt Enable read address
+ * - MCPWM Interrupt Enable set address
+ * - MCPWM Interrupt Enable clear address
+ * - MCPWM Interrupt Flags read address
+ * - MCPWM Interrupt Flags set address
+ * - MCPWM Interrupt Flags clear address
+ */
+/** Limit interrupt for channel (n) */
+#define MCPWM_INT_ILIM(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+0))) : (0))
+/** Match interrupt for channel (n) */
+#define MCPWM_INT_IMAT(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+1))) : (0))
+/** Capture interrupt for channel (n) */
+#define MCPWM_INT_ICAP(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+2))) : (0))
+/** Fast abort interrupt */
+#define MCPWM_INT_ABORT ((uint32_t)(1<<15))
+
+/*********************************************************************//**
+ * Macro defines for MCPWM Count Control register
+ **********************************************************************/
+/* MCPWM Count Control register, these macro definitions below can be applied for these
+ * register type:
+ * - MCPWM Count Control read address
+ * - MCPWM Count Control set address
+ * - MCPWM Count Control clear address
+ */
+/** Counter(tc) advances on a rising edge on MCI(mci) pin */
+#define MCPWM_CNTCON_TCMCI_RE(tc,mci) (((tc<=2)&&(mci<=2)) ? ((uint32_t)(1<<((6*tc)+(2*mci)+0))) : (0))
+/** Counter(cnt) advances on a falling edge on MCI(mci) pin */
+#define MCPWM_CNTCON_TCMCI_FE(tc,mci) (((tc<=2)&&(mci<=2)) ? ((uint32_t)(1<<((6*tc)+(2*mci)+1))) : (0))
+/** Channel (n) is in counter mode */
+#define MCPWM_CNTCON_CNTR(n) ((n<=2) ? ((uint32_t)(1<<(29+n))) : (0))
+
+/*********************************************************************//**
+ * Macro defines for MCPWM Dead-time register
+ **********************************************************************/
+/** Dead time value x for channel n */
+#define MCPWM_DT(n,x) ((n<=2) ? ((uint32_t)((x&0x3FF)<<(n*10))) : (0))
+
+/*********************************************************************//**
+ * Macro defines for MCPWM Communication Pattern register
+ **********************************************************************/
+#define MCPWM_CP_A0 ((uint32_t)(1<<0)) /**< MCOA0 tracks internal MCOA0 */
+#define MCPWM_CP_B0 ((uint32_t)(1<<1)) /**< MCOB0 tracks internal MCOA0 */
+#define MCPWM_CP_A1 ((uint32_t)(1<<2)) /**< MCOA1 tracks internal MCOA0 */
+#define MCPWM_CP_B1 ((uint32_t)(1<<3)) /**< MCOB1 tracks internal MCOA0 */
+#define MCPWM_CP_A2 ((uint32_t)(1<<4)) /**< MCOA2 tracks internal MCOA0 */
+#define MCPWM_CP_B2 ((uint32_t)(1<<5)) /**< MCOB2 tracks internal MCOA0 */
+
+/*********************************************************************//**
+ * Macro defines for MCPWM Capture clear address register
+ **********************************************************************/
+/** Clear the MCCAP (n) register */
+#define MCPWM_CAPCLR_CAP(n) ((n<=2) ? ((uint32_t)(1<<n)) : (0))
+
+
+/**
+ * @}
+ */
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup MCPWM_Public_Types MCPWM Public Types
+ * @{
+ */
+
+/**
+ * @brief Motor Control PWM Channel Configuration structure type definition
+ */
+typedef struct {
+ uint32_t channelType; /**< Edge/center aligned mode for this channel,
+ should be:
+ - MCPWM_CHANNEL_EDGE_MODE: Channel is in Edge mode
+ - MCPWM_CHANNEL_CENTER_MODE: Channel is in Center mode
+ */
+ uint32_t channelPolarity; /**< Polarity of the MCOA and MCOB pins, should be:
+ - MCPWM_CHANNEL_PASSIVE_LO: Passive state is LOW, active state is HIGH
+ - MCPWM_CHANNEL_PASSIVE_HI: Passive state is HIGH, active state is LOW
+ */
+ uint32_t channelDeadtimeEnable; /**< Enable/Disable DeadTime function for channel, should be:
+ - ENABLE.
+ - DISABLE.
+ */
+ uint32_t channelDeadtimeValue; /**< DeadTime value, should be less than 0x3FF */
+ uint32_t channelUpdateEnable; /**< Enable/Disable updates of functional registers,
+ should be:
+ - ENABLE.
+ - DISABLE.
+ */
+ uint32_t channelTimercounterValue; /**< MCPWM Timer Counter value */
+ uint32_t channelPeriodValue; /**< MCPWM Period value */
+ uint32_t channelPulsewidthValue; /**< MCPWM Pulse Width value */
+} MCPWM_CHANNEL_CFG_Type;
+
+/**
+ * @brief MCPWM Capture Configuration type definition
+ */
+typedef struct {
+ uint32_t captureChannel; /**< Capture Channel Number, should be in range from 0 to 2 */
+ uint32_t captureRising; /**< Enable/Disable Capture on Rising Edge event, should be:
+ - ENABLE.
+ - DISABLE.
+ */
+ uint32_t captureFalling; /**< Enable/Disable Capture on Falling Edge event, should be:
+ - ENABLE.
+ - DISABLE.
+ */
+ uint32_t timerReset; /**< Enable/Disable Timer reset function an capture, should be:
+ - ENABLE.
+ - DISABLE.
+ */
+ uint32_t hnfEnable; /**< Enable/Disable Hardware noise filter function, should be:
+ - ENABLE.
+ - DISABLE.
+ */
+} MCPWM_CAPTURE_CFG_Type;
+
+
+/**
+ * @brief MCPWM Count Control Configuration type definition
+ */
+typedef struct {
+ uint32_t counterChannel; /**< Counter Channel Number, should be in range from 0 to 2 */
+ uint32_t countRising; /**< Enable/Disable Capture on Rising Edge event, should be:
+ - ENABLE.
+ - DISABLE.
+ */
+ uint32_t countFalling; /**< Enable/Disable Capture on Falling Edge event, should be:
+ - ENABLE.
+ - DISABLE.
+ */
+} MCPWM_COUNT_CFG_Type;
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup MCPWM_Public_Functions MCPWM Public Functions
+ * @{
+ */
+
+void MCPWM_Init(LPC_MCPWM_TypeDef *MCPWMx);
+void MCPWM_ConfigChannel(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
+ MCPWM_CHANNEL_CFG_Type * channelSetup);
+void MCPWM_WriteToShadow(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
+ MCPWM_CHANNEL_CFG_Type *channelSetup);
+void MCPWM_ConfigCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
+ MCPWM_CAPTURE_CFG_Type *captureConfig);
+void MCPWM_ClearCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t captureChannel);
+uint32_t MCPWM_GetCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t captureChannel);
+void MCPWM_CountConfig(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
+ uint32_t countMode, MCPWM_COUNT_CFG_Type *countConfig);
+void MCPWM_Start(LPC_MCPWM_TypeDef *MCPWMx,uint32_t channel0, uint32_t channel1, uint32_t channel2);
+void MCPWM_Stop(LPC_MCPWM_TypeDef *MCPWMx,uint32_t channel0, uint32_t channel1, uint32_t channel2);
+void MCPWM_ACMode(LPC_MCPWM_TypeDef *MCPWMx,uint32_t acMode);
+void MCPWM_DCMode(LPC_MCPWM_TypeDef *MCPWMx, uint32_t dcMode,
+ uint32_t outputInvered, uint32_t outputPattern);
+void MCPWM_IntConfig(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType, FunctionalState NewState);
+void MCPWM_IntSet(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType);
+void MCPWM_IntClear(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType);
+FlagStatus MCPWM_GetIntStatus(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC17XX_MCPWM_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/src/shared/cmsis/Drivers/include/lpc17xx_nvic.h b/src/shared/cmsis/Drivers/include/lpc17xx_nvic.h
@@ -0,0 +1,76 @@
+/**********************************************************************
+* $Id$ lpc17xx_nvic.h 2010-05-21
+*//**
+* @file lpc17xx_nvic.h
+* @brief Contains all macro definitions and function prototypes
+* support for Nesting Vectored Interrupt firmware library
+* on LPC17xx
+* @version 2.0
+* @date 21. May. 2010
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2010, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup NVIC NVIC (Nested Vectored Interrupt Controller)
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_NVIC_H_
+#define LPC17XX_NVIC_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup NVIC_Public_Functions NVIC Public Functions
+ * @{
+ */
+
+void NVIC_DeInit(void);
+void NVIC_SCBDeInit(void);
+void NVIC_SetVTOR(uint32_t offset);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC17XX_NVIC_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/src/shared/cmsis/Drivers/include/lpc17xx_pinsel.h b/src/shared/cmsis/Drivers/include/lpc17xx_pinsel.h
@@ -0,0 +1,203 @@
+/**********************************************************************
+* $Id$ lpc17xx_pinsel.h 2010-05-21
+*//**
+* @file lpc17xx_pinsel.h
+* @brief Contains all macro definitions and function prototypes
+* support for Pin connect block firmware library on LPC17xx
+* @version 2.0
+* @date 21. May. 2010
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2010, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup PINSEL PINSEL (Pin Selection)
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_PINSEL_H_
+#define LPC17XX_PINSEL_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup PINSEL_Public_Macros PINSEL Public Macros
+ * @{
+ */
+
+/*********************************************************************//**
+ *!< Macros define for PORT Selection
+ ***********************************************************************/
+#define PINSEL_PORT_0 ((0)) /**< PORT 0*/
+#define PINSEL_PORT_1 ((1)) /**< PORT 1*/
+#define PINSEL_PORT_2 ((2)) /**< PORT 2*/
+#define PINSEL_PORT_3 ((3)) /**< PORT 3*/
+#define PINSEL_PORT_4 ((4)) /**< PORT 4*/
+
+/***********************************************************************
+ * Macros define for Pin Function selection
+ **********************************************************************/
+#define PINSEL_FUNC_0 ((0)) /**< default function*/
+#define PINSEL_FUNC_1 ((1)) /**< first alternate function*/
+#define PINSEL_FUNC_2 ((2)) /**< second alternate function*/
+#define PINSEL_FUNC_3 ((3)) /**< third or reserved alternate function*/
+
+/***********************************************************************
+ * Macros define for Pin Number of Port
+ **********************************************************************/
+#define PINSEL_PIN_0 ((0)) /**< Pin 0 */
+#define PINSEL_PIN_1 ((1)) /**< Pin 1 */
+#define PINSEL_PIN_2 ((2)) /**< Pin 2 */
+#define PINSEL_PIN_3 ((3)) /**< Pin 3 */
+#define PINSEL_PIN_4 ((4)) /**< Pin 4 */
+#define PINSEL_PIN_5 ((5)) /**< Pin 5 */
+#define PINSEL_PIN_6 ((6)) /**< Pin 6 */
+#define PINSEL_PIN_7 ((7)) /**< Pin 7 */
+#define PINSEL_PIN_8 ((8)) /**< Pin 8 */
+#define PINSEL_PIN_9 ((9)) /**< Pin 9 */
+#define PINSEL_PIN_10 ((10)) /**< Pin 10 */
+#define PINSEL_PIN_11 ((11)) /**< Pin 11 */
+#define PINSEL_PIN_12 ((12)) /**< Pin 12 */
+#define PINSEL_PIN_13 ((13)) /**< Pin 13 */
+#define PINSEL_PIN_14 ((14)) /**< Pin 14 */
+#define PINSEL_PIN_15 ((15)) /**< Pin 15 */
+#define PINSEL_PIN_16 ((16)) /**< Pin 16 */
+#define PINSEL_PIN_17 ((17)) /**< Pin 17 */
+#define PINSEL_PIN_18 ((18)) /**< Pin 18 */
+#define PINSEL_PIN_19 ((19)) /**< Pin 19 */
+#define PINSEL_PIN_20 ((20)) /**< Pin 20 */
+#define PINSEL_PIN_21 ((21)) /**< Pin 21 */
+#define PINSEL_PIN_22 ((22)) /**< Pin 22 */
+#define PINSEL_PIN_23 ((23)) /**< Pin 23 */
+#define PINSEL_PIN_24 ((24)) /**< Pin 24 */
+#define PINSEL_PIN_25 ((25)) /**< Pin 25 */
+#define PINSEL_PIN_26 ((26)) /**< Pin 26 */
+#define PINSEL_PIN_27 ((27)) /**< Pin 27 */
+#define PINSEL_PIN_28 ((28)) /**< Pin 28 */
+#define PINSEL_PIN_29 ((29)) /**< Pin 29 */
+#define PINSEL_PIN_30 ((30)) /**< Pin 30 */
+#define PINSEL_PIN_31 ((31)) /**< Pin 31 */
+
+/***********************************************************************
+ * Macros define for Pin mode
+ **********************************************************************/
+#define PINSEL_PINMODE_PULLUP ((0)) /**< Internal pull-up resistor*/
+#define PINSEL_PINMODE_TRISTATE ((2)) /**< Tri-state */
+#define PINSEL_PINMODE_PULLDOWN ((3)) /**< Internal pull-down resistor */
+
+/***********************************************************************
+ * Macros define for Pin mode (normal/open drain)
+ **********************************************************************/
+#define PINSEL_PINMODE_NORMAL ((0)) /**< Pin is in the normal (not open drain) mode.*/
+#define PINSEL_PINMODE_OPENDRAIN ((1)) /**< Pin is in the open drain mode */
+
+/***********************************************************************
+ * Macros define for I2C mode
+ ***********************************************************************/
+#define PINSEL_I2C_Normal_Mode ((0)) /**< The standard drive mode */
+#define PINSEL_I2C_Fast_Mode ((1)) /**< Fast Mode Plus drive mode */
+
+/**
+ * @}
+ */
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup PINSEL_Private_Macros PINSEL Private Macros
+ * @{
+ */
+
+/* Pin selection define */
+/* I2C Pin Configuration register bit description */
+#define PINSEL_I2CPADCFG_SDADRV0 _BIT(0) /**< Drive mode control for the SDA0 pin, P0.27 */
+#define PINSEL_I2CPADCFG_SDAI2C0 _BIT(1) /**< I2C mode control for the SDA0 pin, P0.27 */
+#define PINSEL_I2CPADCFG_SCLDRV0 _BIT(2) /**< Drive mode control for the SCL0 pin, P0.28 */
+#define PINSEL_I2CPADCFG_SCLI2C0 _BIT(3) /**< I2C mode control for the SCL0 pin, P0.28 */
+
+/**
+ * @}
+ */
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup PINSEL_Public_Types PINSEL Public Types
+ * @{
+ */
+
+/** @brief Pin configuration structure */
+typedef struct
+{
+ uint8_t Portnum; /**< Port Number, should be PINSEL_PORT_x,
+ where x should be in range from 0 to 4 */
+ uint8_t Pinnum; /**< Pin Number, should be PINSEL_PIN_x,
+ where x should be in range from 0 to 31 */
+ uint8_t Funcnum; /**< Function Number, should be PINSEL_FUNC_x,
+ where x should be in range from 0 to 3 */
+ uint8_t Pinmode; /**< Pin Mode, should be:
+ - PINSEL_PINMODE_PULLUP: Internal pull-up resistor
+ - PINSEL_PINMODE_TRISTATE: Tri-state
+ - PINSEL_PINMODE_PULLDOWN: Internal pull-down resistor */
+ uint8_t OpenDrain; /**< OpenDrain mode, should be:
+ - PINSEL_PINMODE_NORMAL: Pin is in the normal (not open drain) mode
+ - PINSEL_PINMODE_OPENDRAIN: Pin is in the open drain mode */
+} PINSEL_CFG_Type;
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup PINSEL_Public_Functions PINSEL Public Functions
+ * @{
+ */
+
+void PINSEL_ConfigPin(PINSEL_CFG_Type *PinCfg);
+void PINSEL_ConfigTraceFunc (FunctionalState NewState);
+void PINSEL_SetI2C0Pins(uint8_t i2cPinMode, FunctionalState filterSlewRateEnable);
+
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC17XX_PINSEL_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
+
diff --git a/src/shared/cmsis/Drivers/include/lpc17xx_pwm.h b/src/shared/cmsis/Drivers/include/lpc17xx_pwm.h
@@ -0,0 +1,349 @@
+/**********************************************************************
+* $Id$ lpc17xx_pwm.h 2011-03-31
+*//**
+* @file lpc17xx_pwm.h
+* @brief Contains all macro definitions and function prototypes
+* support for PWM firmware library on LPC17xx
+* @version 2.1
+* @date 31. Mar. 2011
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup PWM PWM (Pulse Width Modulator)
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_PWM_H_
+#define LPC17XX_PWM_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup PWM_Private_Macros PWM Private Macros
+ * @{
+ */
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/**********************************************************************
+* IR register definitions
+**********************************************************************/
+/** Interrupt flag for PWM match channel for 6 channel */
+#define PWM_IR_PWMMRn(n) ((uint32_t)((n<4)?(1<<n):(1<<(n+4))))
+/** Interrupt flag for capture input */
+#define PWM_IR_PWMCAPn(n) ((uint32_t)(1<<(n+4)))
+/** IR register mask */
+#define PWM_IR_BITMASK ((uint32_t)(0x0000073F))
+
+/**********************************************************************
+* TCR register definitions
+**********************************************************************/
+/** TCR register mask */
+#define PWM_TCR_BITMASK ((uint32_t)(0x0000000B))
+#define PWM_TCR_COUNTER_ENABLE ((uint32_t)(1<<0)) /*!< PWM Counter Enable */
+#define PWM_TCR_COUNTER_RESET ((uint32_t)(1<<1)) /*!< PWM Counter Reset */
+#define PWM_TCR_PWM_ENABLE ((uint32_t)(1<<3)) /*!< PWM Enable */
+
+/**********************************************************************
+* CTCR register definitions
+**********************************************************************/
+/** CTCR register mask */
+#define PWM_CTCR_BITMASK ((uint32_t)(0x0000000F))
+/** PWM Counter-Timer Mode */
+#define PWM_CTCR_MODE(n) ((uint32_t)(n&0x03))
+/** PWM Capture input select */
+#define PWM_CTCR_SELECT_INPUT(n) ((uint32_t)((n&0x03)<<2))
+
+/**********************************************************************
+* MCR register definitions
+**********************************************************************/
+/** MCR register mask */
+#define PWM_MCR_BITMASK ((uint32_t)(0x001FFFFF))
+/** generate a PWM interrupt when a MATCHn occurs */
+#define PWM_MCR_INT_ON_MATCH(n) ((uint32_t)(1<<(((n&0x7)<<1)+(n&0x07))))
+/** reset the PWM when a MATCHn occurs */
+#define PWM_MCR_RESET_ON_MATCH(n) ((uint32_t)(1<<(((n&0x7)<<1)+(n&0x07)+1)))
+/** stop the PWM when a MATCHn occurs */
+#define PWM_MCR_STOP_ON_MATCH(n) ((uint32_t)(1<<(((n&0x7)<<1)+(n&0x07)+2)))
+
+/**********************************************************************
+* CCR register definitions
+**********************************************************************/
+/** CCR register mask */
+#define PWM_CCR_BITMASK ((uint32_t)(0x0000003F))
+/** PCAPn is rising edge sensitive */
+#define PWM_CCR_CAP_RISING(n) ((uint32_t)(1<<(((n&0x2)<<1)+(n&0x1))))
+/** PCAPn is falling edge sensitive */
+#define PWM_CCR_CAP_FALLING(n) ((uint32_t)(1<<(((n&0x2)<<1)+(n&0x1)+1)))
+/** PWM interrupt is generated on a PCAP event */
+#define PWM_CCR_INT_ON_CAP(n) ((uint32_t)(1<<(((n&0x2)<<1)+(n&0x1)+2)))
+
+/**********************************************************************
+* PCR register definitions
+**********************************************************************/
+/** PCR register mask */
+#define PWM_PCR_BITMASK (uint32_t)0x00007E7C
+/** PWM output n is a single edge controlled output */
+#define PWM_PCR_PWMSELn(n) ((uint32_t)(((n&0x7)<2) ? 0 : (1<<n)))
+/** enable PWM output n */
+#define PWM_PCR_PWMENAn(n) ((uint32_t)(((n&0x7)<1) ? 0 : (1<<(n+8))))
+
+/**********************************************************************
+* LER register definitions
+**********************************************************************/
+/** LER register mask*/
+#define PWM_LER_BITMASK ((uint32_t)(0x0000007F))
+/** PWM MATCHn register update control */
+#define PWM_LER_EN_MATCHn_LATCH(n) ((uint32_t)((n<7) ? (1<<n) : 0))
+
+/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
+/** Macro to determine if it is valid PWM peripheral or not */
+#define PARAM_PWMx(n) (((uint32_t *)n)==((uint32_t *)LPC_PWM1))
+
+/** Macro check PWM1 match channel value */
+#define PARAM_PWM1_MATCH_CHANNEL(n) (n<=6)
+
+/** Macro check PWM1 channel value */
+#define PARAM_PWM1_CHANNEL(n) ((n>=1) && (n<=6))
+
+/** Macro check PWM1 edge channel mode */
+#define PARAM_PWM1_EDGE_MODE_CHANNEL(n) ((n>=2) && (n<=6))
+
+/** Macro check PWM1 capture channel mode */
+#define PARAM_PWM1_CAPTURE_CHANNEL(n) ((n==0) || (n==1))
+
+/** Macro check PWM1 interrupt status type */
+#define PARAM_PWM_INTSTAT(n) ((n==PWM_INTSTAT_MR0) || (n==PWM_INTSTAT_MR1) || (n==PWM_INTSTAT_MR2) \
+|| (n==PWM_INTSTAT_MR3) || (n==PWM_INTSTAT_MR4) || (n==PWM_INTSTAT_MR5) \
+|| (n==PWM_INTSTAT_MR6) || (n==PWM_INTSTAT_CAP0) || (n==PWM_INTSTAT_CAP1))
+/**
+ * @}
+ */
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup PWM_Public_Types PWM Public Types
+ * @{
+ */
+
+/** @brief Configuration structure in PWM TIMER mode */
+typedef struct {
+
+ uint8_t PrescaleOption; /**< Prescale option, should be:
+ - PWM_TIMER_PRESCALE_TICKVAL: Prescale in absolute value
+ - PWM_TIMER_PRESCALE_USVAL: Prescale in microsecond value
+ */
+ uint8_t Reserved[3];
+ uint32_t PrescaleValue; /**< Prescale value, 32-bit long, should be matched
+ with PrescaleOption
+ */
+} PWM_TIMERCFG_Type;
+
+/** @brief Configuration structure in PWM COUNTER mode */
+typedef struct {
+
+ uint8_t CounterOption; /**< Counter Option, should be:
+ - PWM_COUNTER_RISING: Rising Edge
+ - PWM_COUNTER_FALLING: Falling Edge
+ - PWM_COUNTER_ANY: Both rising and falling mode
+ */
+ uint8_t CountInputSelect; /**< Counter input select, should be:
+ - PWM_COUNTER_PCAP1_0: PWM Counter input selected is PCAP1.0 pin
+ - PWM_COUNTER_PCAP1_1: PWM Counter input selected is PCAP1.1 pin
+ */
+ uint8_t Reserved[2];
+} PWM_COUNTERCFG_Type;
+
+/** @brief PWM Match channel configuration structure */
+typedef struct {
+ uint8_t MatchChannel; /**< Match channel, should be in range
+ from 0..6 */
+ uint8_t IntOnMatch; /**< Interrupt On match, should be:
+ - ENABLE: Enable this function.
+ - DISABLE: Disable this function.
+ */
+ uint8_t StopOnMatch; /**< Stop On match, should be:
+ - ENABLE: Enable this function.
+ - DISABLE: Disable this function.
+ */
+ uint8_t ResetOnMatch; /**< Reset On match, should be:
+ - ENABLE: Enable this function.
+ - DISABLE: Disable this function.
+ */
+} PWM_MATCHCFG_Type;
+
+
+/** @brief PWM Capture Input configuration structure */
+typedef struct {
+ uint8_t CaptureChannel; /**< Capture channel, should be in range
+ from 0..1 */
+ uint8_t RisingEdge; /**< caption rising edge, should be:
+ - ENABLE: Enable rising edge.
+ - DISABLE: Disable this function.
+ */
+ uint8_t FallingEdge; /**< caption falling edge, should be:
+ - ENABLE: Enable falling edge.
+ - DISABLE: Disable this function.
+ */
+ uint8_t IntOnCaption; /**< Interrupt On caption, should be:
+ - ENABLE: Enable interrupt function.
+ - DISABLE: Disable this function.
+ */
+} PWM_CAPTURECFG_Type;
+
+/* Timer/Counter in PWM configuration type definition -----------------------------------*/
+
+/** @brief PMW TC mode select option */
+typedef enum {
+ PWM_MODE_TIMER = 0, /*!< PWM using Timer mode */
+ PWM_MODE_COUNTER /*!< PWM using Counter mode */
+} PWM_TC_MODE_OPT;
+
+#define PARAM_PWM_TC_MODE(n) ((n==PWM_MODE_TIMER) || (n==PWM_MODE_COUNTER))
+
+
+/** @brief PWM Timer/Counter prescale option */
+typedef enum
+{
+ PWM_TIMER_PRESCALE_TICKVAL = 0, /*!< Prescale in absolute value */
+ PWM_TIMER_PRESCALE_USVAL /*!< Prescale in microsecond value */
+} PWM_TIMER_PRESCALE_OPT;
+
+#define PARAM_PWM_TIMER_PRESCALE(n) ((n==PWM_TIMER_PRESCALE_TICKVAL) || (n==PWM_TIMER_PRESCALE_USVAL))
+
+
+/** @brief PWM Input Select in counter mode */
+typedef enum {
+ PWM_COUNTER_PCAP1_0 = 0, /*!< PWM Counter input selected is PCAP1.0 pin */
+ PWM_COUNTER_PCAP1_1 /*!< PWM counter input selected is CAP1.1 pin */
+} PWM_COUNTER_INPUTSEL_OPT;
+
+#define PARAM_PWM_COUNTER_INPUTSEL(n) ((n==PWM_COUNTER_PCAP1_0) || (n==PWM_COUNTER_PCAP1_1))
+
+/** @brief PWM Input Edge Option in counter mode */
+typedef enum {
+ PWM_COUNTER_RISING = 1, /*!< Rising edge mode */
+ PWM_COUNTER_FALLING = 2, /*!< Falling edge mode */
+ PWM_COUNTER_ANY = 3 /*!< Both rising and falling mode */
+} PWM_COUNTER_EDGE_OPT;
+
+#define PARAM_PWM_COUNTER_EDGE(n) ((n==PWM_COUNTER_RISING) || (n==PWM_COUNTER_FALLING) \
+|| (n==PWM_COUNTER_ANY))
+
+
+/* PWM configuration type definition ----------------------------------------------------- */
+/** @brief PWM operating mode options */
+typedef enum {
+ PWM_CHANNEL_SINGLE_EDGE, /*!< PWM Channel Single edge mode */
+ PWM_CHANNEL_DUAL_EDGE /*!< PWM Channel Dual edge mode */
+} PWM_CHANNEL_EDGE_OPT;
+
+#define PARAM_PWM_CHANNEL_EDGE(n) ((n==PWM_CHANNEL_SINGLE_EDGE) || (n==PWM_CHANNEL_DUAL_EDGE))
+
+
+/** @brief PWM update type */
+typedef enum {
+ PWM_MATCH_UPDATE_NOW = 0, /**< PWM Match Channel Update Now */
+ PWM_MATCH_UPDATE_NEXT_RST /**< PWM Match Channel Update on next
+ PWM Counter resetting */
+} PWM_MATCH_UPDATE_OPT;
+
+#define PARAM_PWM_MATCH_UPDATE(n) ((n==PWM_MATCH_UPDATE_NOW) || (n==PWM_MATCH_UPDATE_NEXT_RST))
+
+
+/** @brief PWM interrupt status type definition ----------------------------------------------------- */
+/** @brief PWM Interrupt status type */
+typedef enum
+{
+ PWM_INTSTAT_MR0 = PWM_IR_PWMMRn(0), /**< Interrupt flag for PWM match channel 0 */
+ PWM_INTSTAT_MR1 = PWM_IR_PWMMRn(1), /**< Interrupt flag for PWM match channel 1 */
+ PWM_INTSTAT_MR2 = PWM_IR_PWMMRn(2), /**< Interrupt flag for PWM match channel 2 */
+ PWM_INTSTAT_MR3 = PWM_IR_PWMMRn(3), /**< Interrupt flag for PWM match channel 3 */
+ PWM_INTSTAT_CAP0 = PWM_IR_PWMCAPn(0), /**< Interrupt flag for capture input 0 */
+ PWM_INTSTAT_CAP1 = PWM_IR_PWMCAPn(1), /**< Interrupt flag for capture input 1 */
+ PWM_INTSTAT_MR4 = PWM_IR_PWMMRn(4), /**< Interrupt flag for PWM match channel 4 */
+ PWM_INTSTAT_MR6 = PWM_IR_PWMMRn(5), /**< Interrupt flag for PWM match channel 5 */
+ PWM_INTSTAT_MR5 = PWM_IR_PWMMRn(6) /**< Interrupt flag for PWM match channel 6 */
+}PWM_INTSTAT_TYPE;
+
+/** @brief Match update structure */
+typedef struct
+{
+ uint32_t Matchvalue;
+ FlagStatus Status;
+}PWM_Match_T;
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup PWM_Public_Functions PWM Public Functions
+ * @{
+ */
+
+void PWM_PinConfig(LPC_PWM_TypeDef *PWMx, uint8_t PWM_Channel, uint8_t PinselOption);
+IntStatus PWM_GetIntStatus(LPC_PWM_TypeDef *PWMx, uint32_t IntFlag);
+void PWM_ClearIntPending(LPC_PWM_TypeDef *PWMx, uint32_t IntFlag);
+void PWM_ConfigStructInit(uint8_t PWMTimerCounterMode, void *PWM_InitStruct);
+void PWM_Init(LPC_PWM_TypeDef *PWMx, uint32_t PWMTimerCounterMode, void *PWM_ConfigStruct);
+void PWM_DeInit (LPC_PWM_TypeDef *PWMx);
+void PWM_Cmd(LPC_PWM_TypeDef *PWMx, FunctionalState NewState);
+void PWM_CounterCmd(LPC_PWM_TypeDef *PWMx, FunctionalState NewState);
+void PWM_ResetCounter(LPC_PWM_TypeDef *PWMx);
+void PWM_ConfigMatch(LPC_PWM_TypeDef *PWMx, PWM_MATCHCFG_Type *PWM_MatchConfigStruct);
+void PWM_ConfigCapture(LPC_PWM_TypeDef *PWMx, PWM_CAPTURECFG_Type *PWM_CaptureConfigStruct);
+uint32_t PWM_GetCaptureValue(LPC_PWM_TypeDef *PWMx, uint8_t CaptureChannel);
+void PWM_MatchUpdate(LPC_PWM_TypeDef *PWMx, uint8_t MatchChannel, \
+ uint32_t MatchValue, uint8_t UpdateType);
+void PWM_ChannelConfig(LPC_PWM_TypeDef *PWMx, uint8_t PWMChannel, uint8_t ModeOption);
+void PWM_ChannelCmd(LPC_PWM_TypeDef *PWMx, uint8_t PWMChannel, FunctionalState NewState);
+void PWM_MultiMatchUpdate(LPC_PWM_TypeDef *PWMx, PWM_Match_T *MatchStruct , uint8_t UpdateType);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC17XX_PWM_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/src/shared/cmsis/Drivers/include/lpc17xx_qei.h b/src/shared/cmsis/Drivers/include/lpc17xx_qei.h
@@ -0,0 +1,424 @@
+/**********************************************************************
+* $Id$ lpc17xx_qei.h 2010-05-21
+*//**
+* @file lpc17xx_qei.h
+* @brief Contains all macro definitions and function prototypes
+* support for QEI firmware library on LPC17xx
+* @version 2.0
+* @date 21. May. 2010
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2010, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup QEI QEI (Quadrature Encoder Interface)
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_QEI_H_
+#define LPC17XX_QEI_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup QEI_Public_Macros QEI Public Macros
+ * @{
+ */
+
+/* QEI Reset types */
+#define QEI_RESET_POS QEI_CON_RESP /**< Reset position counter */
+#define QEI_RESET_POSOnIDX QEI_CON_RESPI /**< Reset Posistion Counter on Index */
+#define QEI_RESET_VEL QEI_CON_RESV /**< Reset Velocity */
+#define QEI_RESET_IDX QEI_CON_RESI /**< Reset Index Counter */
+
+/* QEI Direction Invert Type Option */
+#define QEI_DIRINV_NONE ((uint32_t)(0)) /**< Direction is not inverted */
+#define QEI_DIRINV_CMPL ((uint32_t)(1)) /**< Direction is complemented */
+
+/* QEI Signal Mode Option */
+#define QEI_SIGNALMODE_QUAD ((uint32_t)(0)) /**< Signal operation: Quadrature phase mode */
+#define QEI_SIGNALMODE_CLKDIR ((uint32_t)(1)) /**< Signal operation: Clock/Direction mode */
+
+/* QEI Capture Mode Option */
+#define QEI_CAPMODE_2X ((uint32_t)(0)) /**< Capture mode: Only Phase-A edges are counted (2X) */
+#define QEI_CAPMODE_4X ((uint32_t)(1)) /**< Capture mode: BOTH PhA and PhB edges are counted (4X)*/
+
+/* QEI Invert Index Signal Option */
+#define QEI_INVINX_NONE ((uint32_t)(0)) /**< Invert Index signal option: None */
+#define QEI_INVINX_EN ((uint32_t)(1)) /**< Invert Index signal option: Enable */
+
+/* QEI timer reload option */
+#define QEI_TIMERRELOAD_TICKVAL ((uint8_t)(0)) /**< Reload value in absolute value */
+#define QEI_TIMERRELOAD_USVAL ((uint8_t)(1)) /**< Reload value in microsecond value */
+
+/* QEI Flag Status type */
+#define QEI_STATUS_DIR ((uint32_t)(1<<0)) /**< Direction status */
+
+/* QEI Compare Position channel option */
+#define QEI_COMPPOS_CH_0 ((uint8_t)(0)) /**< QEI compare position channel 0 */
+#define QEI_COMPPOS_CH_1 ((uint8_t)(1)) /**< QEI compare position channel 1 */
+#define QEI_COMPPOS_CH_2 ((uint8_t)(2)) /**< QEI compare position channel 2 */
+
+/* QEI interrupt flag type */
+#define QEI_INTFLAG_INX_Int ((uint32_t)(1<<0)) /**< index pulse was detected interrupt */
+#define QEI_INTFLAG_TIM_Int ((uint32_t)(1<<1)) /**< Velocity timer over flow interrupt */
+#define QEI_INTFLAG_VELC_Int ((uint32_t)(1<<2)) /**< Capture velocity is less than compare interrupt */
+#define QEI_INTFLAG_DIR_Int ((uint32_t)(1<<3)) /**< Change of direction interrupt */
+#define QEI_INTFLAG_ERR_Int ((uint32_t)(1<<4)) /**< An encoder phase error interrupt */
+#define QEI_INTFLAG_ENCLK_Int ((uint32_t)(1<<5)) /**< An encoder clock pulse was detected interrupt */
+#define QEI_INTFLAG_POS0_Int ((uint32_t)(1<<6)) /**< position 0 compare value is equal to the
+ current position interrupt */
+#define QEI_INTFLAG_POS1_Int ((uint32_t)(1<<7)) /**< position 1 compare value is equal to the
+ current position interrupt */
+#define QEI_INTFLAG_POS2_Int ((uint32_t)(1<<8)) /**< position 2 compare value is equal to the
+ current position interrupt */
+#define QEI_INTFLAG_REV_Int ((uint32_t)(1<<9)) /**< Index compare value is equal to the current
+ index count interrupt */
+#define QEI_INTFLAG_POS0REV_Int ((uint32_t)(1<<10)) /**< Combined position 0 and revolution count interrupt */
+#define QEI_INTFLAG_POS1REV_Int ((uint32_t)(1<<11)) /**< Combined position 1 and revolution count interrupt */
+#define QEI_INTFLAG_POS2REV_Int ((uint32_t)(1<<12)) /**< Combined position 2 and revolution count interrupt */
+
+/**
+ * @}
+ */
+
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup QEI_Private_Macros QEI Private Macros
+ * @{
+ */
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/* Quadrature Encoder Interface Control Register Definition --------------------- */
+/*********************************************************************//**
+ * Macro defines for QEI Control register
+ **********************************************************************/
+#define QEI_CON_RESP ((uint32_t)(1<<0)) /**< Reset position counter */
+#define QEI_CON_RESPI ((uint32_t)(1<<1)) /**< Reset Posistion Counter on Index */
+#define QEI_CON_RESV ((uint32_t)(1<<2)) /**< Reset Velocity */
+#define QEI_CON_RESI ((uint32_t)(1<<3)) /**< Reset Index Counter */
+#define QEI_CON_BITMASK ((uint32_t)(0x0F)) /**< QEI Control register bit-mask */
+
+/*********************************************************************//**
+ * Macro defines for QEI Configuration register
+ **********************************************************************/
+#define QEI_CONF_DIRINV ((uint32_t)(1<<0)) /**< Direction Invert */
+#define QEI_CONF_SIGMODE ((uint32_t)(1<<1)) /**< Signal mode */
+#define QEI_CONF_CAPMODE ((uint32_t)(1<<2)) /**< Capture mode */
+#define QEI_CONF_INVINX ((uint32_t)(1<<3)) /**< Invert index */
+#define QEI_CONF_BITMASK ((uint32_t)(0x0F)) /**< QEI Configuration register bit-mask */
+
+/*********************************************************************//**
+ * Macro defines for QEI Status register
+ **********************************************************************/
+#define QEI_STAT_DIR ((uint32_t)(1<<0)) /**< Direction bit */
+#define QEI_STAT_BITMASK ((uint32_t)(1<<0)) /**< QEI status register bit-mask */
+
+/* Quadrature Encoder Interface Interrupt registers definitions --------------------- */
+/*********************************************************************//**
+ * Macro defines for QEI Interrupt Status register
+ **********************************************************************/
+#define QEI_INTSTAT_INX_Int ((uint32_t)(1<<0)) /**< Indicates that an index pulse was detected */
+#define QEI_INTSTAT_TIM_Int ((uint32_t)(1<<1)) /**< Indicates that a velocity timer overflow occurred */
+#define QEI_INTSTAT_VELC_Int ((uint32_t)(1<<2)) /**< Indicates that capture velocity is less than compare velocity */
+#define QEI_INTSTAT_DIR_Int ((uint32_t)(1<<3)) /**< Indicates that a change of direction was detected */
+#define QEI_INTSTAT_ERR_Int ((uint32_t)(1<<4)) /**< Indicates that an encoder phase error was detected */
+#define QEI_INTSTAT_ENCLK_Int ((uint32_t)(1<<5)) /**< Indicates that and encoder clock pulse was detected */
+#define QEI_INTSTAT_POS0_Int ((uint32_t)(1<<6)) /**< Indicates that the position 0 compare value is equal to the
+ current position */
+#define QEI_INTSTAT_POS1_Int ((uint32_t)(1<<7)) /**< Indicates that the position 1compare value is equal to the
+ current position */
+#define QEI_INTSTAT_POS2_Int ((uint32_t)(1<<8)) /**< Indicates that the position 2 compare value is equal to the
+ current position */
+#define QEI_INTSTAT_REV_Int ((uint32_t)(1<<9)) /**< Indicates that the index compare value is equal to the current
+ index count */
+#define QEI_INTSTAT_POS0REV_Int ((uint32_t)(1<<10)) /**< Combined position 0 and revolution count interrupt. Set when
+ both the POS0_Int bit is set and the REV_Int is set */
+#define QEI_INTSTAT_POS1REV_Int ((uint32_t)(1<<11)) /**< Combined position 1 and revolution count interrupt. Set when
+ both the POS1_Int bit is set and the REV_Int is set */
+#define QEI_INTSTAT_POS2REV_Int ((uint32_t)(1<<12)) /**< Combined position 2 and revolution count interrupt. Set when
+ both the POS2_Int bit is set and the REV_Int is set */
+#define QEI_INTSTAT_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Status register bit-mask */
+
+/*********************************************************************//**
+ * Macro defines for QEI Interrupt Set register
+ **********************************************************************/
+#define QEI_INTSET_INX_Int ((uint32_t)(1<<0)) /**< Set Bit Indicates that an index pulse was detected */
+#define QEI_INTSET_TIM_Int ((uint32_t)(1<<1)) /**< Set Bit Indicates that a velocity timer overflow occurred */
+#define QEI_INTSET_VELC_Int ((uint32_t)(1<<2)) /**< Set Bit Indicates that capture velocity is less than compare velocity */
+#define QEI_INTSET_DIR_Int ((uint32_t)(1<<3)) /**< Set Bit Indicates that a change of direction was detected */
+#define QEI_INTSET_ERR_Int ((uint32_t)(1<<4)) /**< Set Bit Indicates that an encoder phase error was detected */
+#define QEI_INTSET_ENCLK_Int ((uint32_t)(1<<5)) /**< Set Bit Indicates that and encoder clock pulse was detected */
+#define QEI_INTSET_POS0_Int ((uint32_t)(1<<6)) /**< Set Bit Indicates that the position 0 compare value is equal to the
+ current position */
+#define QEI_INTSET_POS1_Int ((uint32_t)(1<<7)) /**< Set Bit Indicates that the position 1compare value is equal to the
+ current position */
+#define QEI_INTSET_POS2_Int ((uint32_t)(1<<8)) /**< Set Bit Indicates that the position 2 compare value is equal to the
+ current position */
+#define QEI_INTSET_REV_Int ((uint32_t)(1<<9)) /**< Set Bit Indicates that the index compare value is equal to the current
+ index count */
+#define QEI_INTSET_POS0REV_Int ((uint32_t)(1<<10)) /**< Set Bit that combined position 0 and revolution count interrupt */
+#define QEI_INTSET_POS1REV_Int ((uint32_t)(1<<11)) /**< Set Bit that Combined position 1 and revolution count interrupt */
+#define QEI_INTSET_POS2REV_Int ((uint32_t)(1<<12)) /**< Set Bit that Combined position 2 and revolution count interrupt */
+#define QEI_INTSET_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Set register bit-mask */
+
+/*********************************************************************//**
+ * Macro defines for QEI Interrupt Clear register
+ **********************************************************************/
+#define QEI_INTCLR_INX_Int ((uint32_t)(1<<0)) /**< Clear Bit Indicates that an index pulse was detected */
+#define QEI_INTCLR_TIM_Int ((uint32_t)(1<<1)) /**< Clear Bit Indicates that a velocity timer overflow occurred */
+#define QEI_INTCLR_VELC_Int ((uint32_t)(1<<2)) /**< Clear Bit Indicates that capture velocity is less than compare velocity */
+#define QEI_INTCLR_DIR_Int ((uint32_t)(1<<3)) /**< Clear Bit Indicates that a change of direction was detected */
+#define QEI_INTCLR_ERR_Int ((uint32_t)(1<<4)) /**< Clear Bit Indicates that an encoder phase error was detected */
+#define QEI_INTCLR_ENCLK_Int ((uint32_t)(1<<5)) /**< Clear Bit Indicates that and encoder clock pulse was detected */
+#define QEI_INTCLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Bit Indicates that the position 0 compare value is equal to the
+ current position */
+#define QEI_INTCLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Bit Indicates that the position 1compare value is equal to the
+ current position */
+#define QEI_INTCLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Bit Indicates that the position 2 compare value is equal to the
+ current position */
+#define QEI_INTCLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Bit Indicates that the index compare value is equal to the current
+ index count */
+#define QEI_INTCLR_POS0REV_Int ((uint32_t)(1<<10)) /**< Clear Bit that combined position 0 and revolution count interrupt */
+#define QEI_INTCLR_POS1REV_Int ((uint32_t)(1<<11)) /**< Clear Bit that Combined position 1 and revolution count interrupt */
+#define QEI_INTCLR_POS2REV_Int ((uint32_t)(1<<12)) /**< Clear Bit that Combined position 2 and revolution count interrupt */
+#define QEI_INTCLR_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Clear register bit-mask */
+
+/*********************************************************************//**
+ * Macro defines for QEI Interrupt Enable register
+ **********************************************************************/
+#define QEI_INTEN_INX_Int ((uint32_t)(1<<0)) /**< Enabled Interrupt Bit Indicates that an index pulse was detected */
+#define QEI_INTEN_TIM_Int ((uint32_t)(1<<1)) /**< Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */
+#define QEI_INTEN_VELC_Int ((uint32_t)(1<<2)) /**< Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */
+#define QEI_INTEN_DIR_Int ((uint32_t)(1<<3)) /**< Enabled Interrupt Bit Indicates that a change of direction was detected */
+#define QEI_INTEN_ERR_Int ((uint32_t)(1<<4)) /**< Enabled Interrupt Bit Indicates that an encoder phase error was detected */
+#define QEI_INTEN_ENCLK_Int ((uint32_t)(1<<5)) /**< Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */
+#define QEI_INTEN_POS0_Int ((uint32_t)(1<<6)) /**< Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the
+ current position */
+#define QEI_INTEN_POS1_Int ((uint32_t)(1<<7)) /**< Enabled Interrupt Bit Indicates that the position 1compare value is equal to the
+ current position */
+#define QEI_INTEN_POS2_Int ((uint32_t)(1<<8)) /**< Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the
+ current position */
+#define QEI_INTEN_REV_Int ((uint32_t)(1<<9)) /**< Enabled Interrupt Bit Indicates that the index compare value is equal to the current
+ index count */
+#define QEI_INTEN_POS0REV_Int ((uint32_t)(1<<10)) /**< Enabled Interrupt Bit that combined position 0 and revolution count interrupt */
+#define QEI_INTEN_POS1REV_Int ((uint32_t)(1<<11)) /**< Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */
+#define QEI_INTEN_POS2REV_Int ((uint32_t)(1<<12)) /**< Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */
+#define QEI_INTEN_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable register bit-mask */
+
+/*********************************************************************//**
+ * Macro defines for QEI Interrupt Enable Set register
+ **********************************************************************/
+#define QEI_IESET_INX_Int ((uint32_t)(1<<0)) /**< Set Enable Interrupt Bit Indicates that an index pulse was detected */
+#define QEI_IESET_TIM_Int ((uint32_t)(1<<1)) /**< Set Enable Interrupt Bit Indicates that a velocity timer overflow occurred */
+#define QEI_IESET_VELC_Int ((uint32_t)(1<<2)) /**< Set Enable Interrupt Bit Indicates that capture velocity is less than compare velocity */
+#define QEI_IESET_DIR_Int ((uint32_t)(1<<3)) /**< Set Enable Interrupt Bit Indicates that a change of direction was detected */
+#define QEI_IESET_ERR_Int ((uint32_t)(1<<4)) /**< Set Enable Interrupt Bit Indicates that an encoder phase error was detected */
+#define QEI_IESET_ENCLK_Int ((uint32_t)(1<<5)) /**< Set Enable Interrupt Bit Indicates that and encoder clock pulse was detected */
+#define QEI_IESET_POS0_Int ((uint32_t)(1<<6)) /**< Set Enable Interrupt Bit Indicates that the position 0 compare value is equal to the
+ current position */
+#define QEI_IESET_POS1_Int ((uint32_t)(1<<7)) /**< Set Enable Interrupt Bit Indicates that the position 1compare value is equal to the
+ current position */
+#define QEI_IESET_POS2_Int ((uint32_t)(1<<8)) /**< Set Enable Interrupt Bit Indicates that the position 2 compare value is equal to the
+ current position */
+#define QEI_IESET_REV_Int ((uint32_t)(1<<9)) /**< Set Enable Interrupt Bit Indicates that the index compare value is equal to the current
+ index count */
+#define QEI_IESET_POS0REV_Int ((uint32_t)(1<<10)) /**< Set Enable Interrupt Bit that combined position 0 and revolution count interrupt */
+#define QEI_IESET_POS1REV_Int ((uint32_t)(1<<11)) /**< Set Enable Interrupt Bit that Combined position 1 and revolution count interrupt */
+#define QEI_IESET_POS2REV_Int ((uint32_t)(1<<12)) /**< Set Enable Interrupt Bit that Combined position 2 and revolution count interrupt */
+#define QEI_IESET_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable Set register bit-mask */
+
+/*********************************************************************//**
+ * Macro defines for QEI Interrupt Enable Clear register
+ **********************************************************************/
+#define QEI_IECLR_INX_Int ((uint32_t)(1<<0)) /**< Clear Enabled Interrupt Bit Indicates that an index pulse was detected */
+#define QEI_IECLR_TIM_Int ((uint32_t)(1<<1)) /**< Clear Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */
+#define QEI_IECLR_VELC_Int ((uint32_t)(1<<2)) /**< Clear Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */
+#define QEI_IECLR_DIR_Int ((uint32_t)(1<<3)) /**< Clear Enabled Interrupt Bit Indicates that a change of direction was detected */
+#define QEI_IECLR_ERR_Int ((uint32_t)(1<<4)) /**< Clear Enabled Interrupt Bit Indicates that an encoder phase error was detected */
+#define QEI_IECLR_ENCLK_Int ((uint32_t)(1<<5)) /**< Clear Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */
+#define QEI_IECLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the
+ current position */
+#define QEI_IECLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Enabled Interrupt Bit Indicates that the position 1compare value is equal to the
+ current position */
+#define QEI_IECLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the
+ current position */
+#define QEI_IECLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Enabled Interrupt Bit Indicates that the index compare value is equal to the current
+ index count */
+#define QEI_IECLR_POS0REV_Int ((uint32_t)(1<<10)) /**< Clear Enabled Interrupt Bit that combined position 0 and revolution count interrupt */
+#define QEI_IECLR_POS1REV_Int ((uint32_t)(1<<11)) /**< Clear Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */
+#define QEI_IECLR_POS2REV_Int ((uint32_t)(1<<12)) /**< Clear Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */
+#define QEI_IECLR_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable Clear register bit-mask */
+
+
+/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
+/* Macro check QEI peripheral */
+#define PARAM_QEIx(n) ((n==LPC_QEI))
+
+/* Macro check QEI reset type */
+#define PARAM_QEI_RESET(n) ((n==QEI_CON_RESP) \
+|| (n==QEI_RESET_POSOnIDX) \
+|| (n==QEI_RESET_VEL) \
+|| (n==QEI_RESET_IDX))
+
+/* Macro check QEI Direction invert mode */
+#define PARAM_QEI_DIRINV(n) ((n==QEI_DIRINV_NONE) || (n==QEI_DIRINV_CMPL))
+
+/* Macro check QEI signal mode */
+#define PARAM_QEI_SIGNALMODE(n) ((n==QEI_SIGNALMODE_QUAD) || (n==QEI_SIGNALMODE_CLKDIR))
+
+/* Macro check QEI Capture mode */
+#define PARAM_QEI_CAPMODE(n) ((n==QEI_CAPMODE_2X) || (n==QEI_CAPMODE_4X))
+
+/* Macro check QEI Invert index mode */
+#define PARAM_QEI_INVINX(n) ((n==QEI_INVINX_NONE) || (n==QEI_INVINX_EN))
+
+/* Macro check QEI Direction invert mode */
+#define PARAM_QEI_TIMERRELOAD(n) ((n==QEI_TIMERRELOAD_TICKVAL) || (n==QEI_TIMERRELOAD_USVAL))
+
+/* Macro check QEI status type */
+#define PARAM_QEI_STATUS(n) ((n==QEI_STATUS_DIR))
+
+/* Macro check QEI combine position type */
+#define PARAM_QEI_COMPPOS_CH(n) ((n==QEI_COMPPOS_CH_0) || (n==QEI_COMPPOS_CH_1) || (n==QEI_COMPPOS_CH_2))
+
+/* Macro check QEI interrupt flag type */
+#define PARAM_QEI_INTFLAG(n) ((n==QEI_INTFLAG_INX_Int) \
+|| (n==QEI_INTFLAG_TIM_Int) \
+|| (n==QEI_INTFLAG_VELC_Int) \
+|| (n==QEI_INTFLAG_DIR_Int) \
+|| (n==QEI_INTFLAG_ERR_Int) \
+|| (n==QEI_INTFLAG_ENCLK_Int) \
+|| (n==QEI_INTFLAG_POS0_Int) \
+|| (n==QEI_INTFLAG_POS1_Int) \
+|| (n==QEI_INTFLAG_POS2_Int) \
+|| (n==QEI_INTFLAG_REV_Int) \
+|| (n==QEI_INTFLAG_POS0REV_Int) \
+|| (n==QEI_INTFLAG_POS1REV_Int) \
+|| (n==QEI_INTFLAG_POS2REV_Int))
+/**
+ * @}
+ */
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup QEI_Public_Types QEI Public Types
+ * @{
+ */
+
+/**
+ * @brief QEI Configuration structure type definition
+ */
+typedef struct {
+ uint32_t DirectionInvert :1; /**< Direction invert option:
+ - QEI_DIRINV_NONE: QEI Direction is normal
+ - QEI_DIRINV_CMPL: QEI Direction is complemented
+ */
+ uint32_t SignalMode :1; /**< Signal mode Option:
+ - QEI_SIGNALMODE_QUAD: Signal is in Quadrature phase mode
+ - QEI_SIGNALMODE_CLKDIR: Signal is in Clock/Direction mode
+ */
+ uint32_t CaptureMode :1; /**< Capture Mode Option:
+ - QEI_CAPMODE_2X: Only Phase-A edges are counted (2X)
+ - QEI_CAPMODE_4X: BOTH Phase-A and Phase-B edges are counted (4X)
+ */
+ uint32_t InvertIndex :1; /**< Invert Index Option:
+ - QEI_INVINX_NONE: the sense of the index input is normal
+ - QEI_INVINX_EN: inverts the sense of the index input
+ */
+} QEI_CFG_Type;
+
+/**
+ * @brief Timer Reload Configuration structure type definition
+ */
+typedef struct {
+
+ uint8_t ReloadOption; /**< Velocity Timer Reload Option, should be:
+ - QEI_TIMERRELOAD_TICKVAL: Reload value in absolute value
+ - QEI_TIMERRELOAD_USVAL: Reload value in microsecond value
+ */
+ uint8_t Reserved[3];
+ uint32_t ReloadValue; /**< Velocity Timer Reload Value, 32-bit long, should be matched
+ with Velocity Timer Reload Option
+ */
+} QEI_RELOADCFG_Type;
+
+/**
+ * @}
+ */
+
+
+
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup QEI_Public_Functions QEI Public Functions
+ * @{
+ */
+
+void QEI_Reset(LPC_QEI_TypeDef *QEIx, uint32_t ulResetType);
+void QEI_Init(LPC_QEI_TypeDef *QEIx, QEI_CFG_Type *QEI_ConfigStruct);
+void QEI_ConfigStructInit(QEI_CFG_Type *QIE_InitStruct);
+void QEI_DeInit(LPC_QEI_TypeDef *QEIx);
+FlagStatus QEI_GetStatus(LPC_QEI_TypeDef *QEIx, uint32_t ulFlagType);
+uint32_t QEI_GetPosition(LPC_QEI_TypeDef *QEIx);
+void QEI_SetMaxPosition(LPC_QEI_TypeDef *QEIx, uint32_t ulMaxPos);
+void QEI_SetPositionComp(LPC_QEI_TypeDef *QEIx, uint8_t bPosCompCh, uint32_t ulPosComp);
+uint32_t QEI_GetIndex(LPC_QEI_TypeDef *QEIx);
+void QEI_SetIndexComp(LPC_QEI_TypeDef *QEIx, uint32_t ulIndexComp);
+void QEI_SetTimerReload(LPC_QEI_TypeDef *QEIx, QEI_RELOADCFG_Type *QEIReloadStruct);
+uint32_t QEI_GetTimer(LPC_QEI_TypeDef *QEIx);
+uint32_t QEI_GetVelocity(LPC_QEI_TypeDef *QEIx);
+uint32_t QEI_GetVelocityCap(LPC_QEI_TypeDef *QEIx);
+void QEI_SetVelocityComp(LPC_QEI_TypeDef *QEIx, uint32_t ulVelComp);
+void QEI_SetDigiFilter(LPC_QEI_TypeDef *QEIx, uint32_t ulSamplingPulse);
+FlagStatus QEI_GetIntStatus(LPC_QEI_TypeDef *QEIx, uint32_t ulIntType);
+void QEI_IntCmd(LPC_QEI_TypeDef *QEIx, uint32_t ulIntType, FunctionalState NewState);
+void QEI_IntSet(LPC_QEI_TypeDef *QEIx, uint32_t ulIntType);
+void QEI_IntClear(LPC_QEI_TypeDef *QEIx, uint32_t ulIntType);
+uint32_t QEI_CalculateRPM(LPC_QEI_TypeDef *QEIx, uint32_t ulVelCapValue, uint32_t ulPPR);
+
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC17XX_QEI_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/src/shared/cmsis/Drivers/include/lpc17xx_rit.h b/src/shared/cmsis/Drivers/include/lpc17xx_rit.h
@@ -0,0 +1,112 @@
+/**********************************************************************
+* $Id$ lpc17xx_rit.h 2010-05-21
+*//**
+* @file lpc17xx_rit.h
+* @brief Contains all macro definitions and function prototypes
+* support for RIT firmware library on LPC17xx
+* @version 2.0
+* @date 21. May. 2010
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2010, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup RIT RIT (Repetitive Interrupt Timer)
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_RIT_H_
+#define LPC17XX_RIT_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup RIT_Private_Macros RIT Private Macros
+ * @{
+ */
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/*********************************************************************//**
+ * Macro defines for RIT control register
+ **********************************************************************/
+/** Set interrupt flag when the counter value equals the masked compare value */
+#define RIT_CTRL_INTEN ((uint32_t) (1))
+/** Set timer enable clear to 0 when the counter value equals the masked compare value */
+#define RIT_CTRL_ENCLR ((uint32_t) _BIT(1))
+/** Set timer enable on debug */
+#define RIT_CTRL_ENBR ((uint32_t) _BIT(2))
+/** Set timer enable */
+#define RIT_CTRL_TEN ((uint32_t) _BIT(3))
+
+/** Macro to determine if it is valid RIT peripheral */
+#define PARAM_RITx(n) (((uint32_t *)n)==((uint32_t *)LPC_RIT))
+/**
+ * @}
+ */
+
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup RIT_Public_Functions RIT Public Functions
+ * @{
+ */
+/* RIT Init/DeInit functions */
+void RIT_Init(LPC_RIT_TypeDef *RITx);
+void RIT_DeInit(LPC_RIT_TypeDef *RITx);
+
+/* RIT config timer functions */
+void RIT_TimerConfig(LPC_RIT_TypeDef *RITx, uint32_t time_interval);
+
+/* Enable/Disable RIT functions */
+void RIT_TimerClearCmd(LPC_RIT_TypeDef *RITx, FunctionalState NewState);
+void RIT_Cmd(LPC_RIT_TypeDef *RITx, FunctionalState NewState);
+void RIT_TimerDebugCmd(LPC_RIT_TypeDef *RITx, FunctionalState NewState);
+
+/* RIT Interrupt functions */
+IntStatus RIT_GetIntStatus(LPC_RIT_TypeDef *RITx);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC17XX_RIT_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/src/shared/cmsis/Drivers/include/lpc17xx_rtc.h b/src/shared/cmsis/Drivers/include/lpc17xx_rtc.h
@@ -0,0 +1,314 @@
+/**********************************************************************
+* $Id$ lpc17xx_rtc.h 2010-05-21
+*//**
+* @file lpc17xx_rtc.h
+* @brief Contains all macro definitions and function prototypes
+* support for RTC firmware library on LPC17xx
+* @version 2.0
+* @date 21. May. 2010
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2010, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup RTC RTC (Real Time Clock)
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_RTC_H_
+#define LPC17XX_RTC_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup RTC_Private_Macros RTC Private Macros
+ * @{
+ */
+
+/* ----------------------- BIT DEFINITIONS ----------------------------------- */
+/* Miscellaneous register group --------------------------------------------- */
+/**********************************************************************
+* ILR register definitions
+**********************************************************************/
+/** ILR register mask */
+#define RTC_ILR_BITMASK ((0x00000003))
+/** Bit inform the source interrupt is counter increment*/
+#define RTC_IRL_RTCCIF ((1<<0))
+/** Bit inform the source interrupt is alarm match*/
+#define RTC_IRL_RTCALF ((1<<1))
+
+/**********************************************************************
+* CCR register definitions
+**********************************************************************/
+/** CCR register mask */
+#define RTC_CCR_BITMASK ((0x00000013))
+/** Clock enable */
+#define RTC_CCR_CLKEN ((1<<0))
+/** Clock reset */
+#define RTC_CCR_CTCRST ((1<<1))
+/** Calibration counter enable */
+#define RTC_CCR_CCALEN ((1<<4))
+
+/**********************************************************************
+* CIIR register definitions
+**********************************************************************/
+/** Counter Increment Interrupt bit for second */
+#define RTC_CIIR_IMSEC ((1<<0))
+/** Counter Increment Interrupt bit for minute */
+#define RTC_CIIR_IMMIN ((1<<1))
+/** Counter Increment Interrupt bit for hour */
+#define RTC_CIIR_IMHOUR ((1<<2))
+/** Counter Increment Interrupt bit for day of month */
+#define RTC_CIIR_IMDOM ((1<<3))
+/** Counter Increment Interrupt bit for day of week */
+#define RTC_CIIR_IMDOW ((1<<4))
+/** Counter Increment Interrupt bit for day of year */
+#define RTC_CIIR_IMDOY ((1<<5))
+/** Counter Increment Interrupt bit for month */
+#define RTC_CIIR_IMMON ((1<<6))
+/** Counter Increment Interrupt bit for year */
+#define RTC_CIIR_IMYEAR ((1<<7))
+/** CIIR bit mask */
+#define RTC_CIIR_BITMASK ((0xFF))
+
+/**********************************************************************
+* AMR register definitions
+**********************************************************************/
+/** Counter Increment Select Mask bit for second */
+#define RTC_AMR_AMRSEC ((1<<0))
+/** Counter Increment Select Mask bit for minute */
+#define RTC_AMR_AMRMIN ((1<<1))
+/** Counter Increment Select Mask bit for hour */
+#define RTC_AMR_AMRHOUR ((1<<2))
+/** Counter Increment Select Mask bit for day of month */
+#define RTC_AMR_AMRDOM ((1<<3))
+/** Counter Increment Select Mask bit for day of week */
+#define RTC_AMR_AMRDOW ((1<<4))
+/** Counter Increment Select Mask bit for day of year */
+#define RTC_AMR_AMRDOY ((1<<5))
+/** Counter Increment Select Mask bit for month */
+#define RTC_AMR_AMRMON ((1<<6))
+/** Counter Increment Select Mask bit for year */
+#define RTC_AMR_AMRYEAR ((1<<7))
+/** AMR bit mask */
+#define RTC_AMR_BITMASK ((0xFF))
+
+/**********************************************************************
+* RTC_AUX register definitions
+**********************************************************************/
+/** RTC Oscillator Fail detect flag */
+#define RTC_AUX_RTC_OSCF ((1<<4))
+
+/**********************************************************************
+* RTC_AUXEN register definitions
+**********************************************************************/
+/** Oscillator Fail Detect interrupt enable*/
+#define RTC_AUXEN_RTC_OSCFEN ((1<<4))
+
+/* Consolidated time register group ----------------------------------- */
+/**********************************************************************
+* Consolidated Time Register 0 definitions
+**********************************************************************/
+#define RTC_CTIME0_SECONDS_MASK ((0x3F))
+#define RTC_CTIME0_MINUTES_MASK ((0x3F00))
+#define RTC_CTIME0_HOURS_MASK ((0x1F0000))
+#define RTC_CTIME0_DOW_MASK ((0x7000000))
+
+/**********************************************************************
+* Consolidated Time Register 1 definitions
+**********************************************************************/
+#define RTC_CTIME1_DOM_MASK ((0x1F))
+#define RTC_CTIME1_MONTH_MASK ((0xF00))
+#define RTC_CTIME1_YEAR_MASK ((0xFFF0000))
+
+/**********************************************************************
+* Consolidated Time Register 2 definitions
+**********************************************************************/
+#define RTC_CTIME2_DOY_MASK ((0xFFF))
+
+/**********************************************************************
+* Time Counter Group and Alarm register group
+**********************************************************************/
+/** SEC register mask */
+#define RTC_SEC_MASK (0x0000003F)
+/** MIN register mask */
+#define RTC_MIN_MASK (0x0000003F)
+/** HOUR register mask */
+#define RTC_HOUR_MASK (0x0000001F)
+/** DOM register mask */
+#define RTC_DOM_MASK (0x0000001F)
+/** DOW register mask */
+#define RTC_DOW_MASK (0x00000007)
+/** DOY register mask */
+#define RTC_DOY_MASK (0x000001FF)
+/** MONTH register mask */
+#define RTC_MONTH_MASK (0x0000000F)
+/** YEAR register mask */
+#define RTC_YEAR_MASK (0x00000FFF)
+
+#define RTC_SECOND_MAX 59 /*!< Maximum value of second */
+#define RTC_MINUTE_MAX 59 /*!< Maximum value of minute*/
+#define RTC_HOUR_MAX 23 /*!< Maximum value of hour*/
+#define RTC_MONTH_MIN 1 /*!< Minimum value of month*/
+#define RTC_MONTH_MAX 12 /*!< Maximum value of month*/
+#define RTC_DAYOFMONTH_MIN 1 /*!< Minimum value of day of month*/
+#define RTC_DAYOFMONTH_MAX 31 /*!< Maximum value of day of month*/
+#define RTC_DAYOFWEEK_MAX 6 /*!< Maximum value of day of week*/
+#define RTC_DAYOFYEAR_MIN 1 /*!< Minimum value of day of year*/
+#define RTC_DAYOFYEAR_MAX 366 /*!< Maximum value of day of year*/
+#define RTC_YEAR_MAX 4095 /*!< Maximum value of year*/
+
+/**********************************************************************
+* Calibration register
+**********************************************************************/
+/* Calibration register */
+/** Calibration value */
+#define RTC_CALIBRATION_CALVAL_MASK ((0x1FFFF))
+/** Calibration direction */
+#define RTC_CALIBRATION_LIBDIR ((1<<17))
+/** Calibration max value */
+#define RTC_CALIBRATION_MAX ((0x20000))
+/** Calibration definitions */
+#define RTC_CALIB_DIR_FORWARD ((uint8_t)(0))
+#define RTC_CALIB_DIR_BACKWARD ((uint8_t)(1))
+
+
+/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
+/** Macro to determine if it is valid RTC peripheral */
+#define PARAM_RTCx(x) (((uint32_t *)x)==((uint32_t *)LPC_RTC))
+
+/* Macro check RTC interrupt type */
+#define PARAM_RTC_INT(n) ((n==RTC_INT_COUNTER_INCREASE) || (n==RTC_INT_ALARM))
+
+/* Macro check RTC time type */
+#define PARAM_RTC_TIMETYPE(n) ((n==RTC_TIMETYPE_SECOND) || (n==RTC_TIMETYPE_MINUTE) \
+|| (n==RTC_TIMETYPE_HOUR) || (n==RTC_TIMETYPE_DAYOFWEEK) \
+|| (n==RTC_TIMETYPE_DAYOFMONTH) || (n==RTC_TIMETYPE_DAYOFYEAR) \
+|| (n==RTC_TIMETYPE_MONTH) || (n==RTC_TIMETYPE_YEAR))
+
+/* Macro check RTC calibration type */
+#define PARAM_RTC_CALIB_DIR(n) ((n==RTC_CALIB_DIR_FORWARD) || (n==RTC_CALIB_DIR_BACKWARD))
+
+/* Macro check RTC GPREG type */
+#define PARAM_RTC_GPREG_CH(n) (n<=4)
+
+/**
+ * @}
+ */
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup RTC_Public_Types RTC Public Types
+ * @{
+ */
+
+/** @brief Time structure definitions for easy manipulate the data */
+typedef struct {
+ uint32_t SEC; /*!< Seconds Register */
+ uint32_t MIN; /*!< Minutes Register */
+ uint32_t HOUR; /*!< Hours Register */
+ uint32_t DOM; /*!< Day of Month Register */
+ uint32_t DOW; /*!< Day of Week Register */
+ uint32_t DOY; /*!< Day of Year Register */
+ uint32_t MONTH; /*!< Months Register */
+ uint32_t YEAR; /*!< Years Register */
+} RTC_TIME_Type;
+
+/** @brief RTC interrupt source */
+typedef enum {
+ RTC_INT_COUNTER_INCREASE = RTC_IRL_RTCCIF, /*!< Counter Increment Interrupt */
+ RTC_INT_ALARM = RTC_IRL_RTCALF /*!< The alarm interrupt */
+} RTC_INT_OPT;
+
+
+/** @brief RTC time type option */
+typedef enum {
+ RTC_TIMETYPE_SECOND = 0, /*!< Second */
+ RTC_TIMETYPE_MINUTE = 1, /*!< Month */
+ RTC_TIMETYPE_HOUR = 2, /*!< Hour */
+ RTC_TIMETYPE_DAYOFWEEK = 3, /*!< Day of week */
+ RTC_TIMETYPE_DAYOFMONTH = 4, /*!< Day of month */
+ RTC_TIMETYPE_DAYOFYEAR = 5, /*!< Day of year */
+ RTC_TIMETYPE_MONTH = 6, /*!< Month */
+ RTC_TIMETYPE_YEAR = 7 /*!< Year */
+} RTC_TIMETYPE_Num;
+
+/**
+ * @}
+ */
+
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup RTC_Public_Functions RTC Public Functions
+ * @{
+ */
+
+void RTC_Init (LPC_RTC_TypeDef *RTCx);
+void RTC_DeInit(LPC_RTC_TypeDef *RTCx);
+void RTC_ResetClockTickCounter(LPC_RTC_TypeDef *RTCx);
+void RTC_Cmd (LPC_RTC_TypeDef *RTCx, FunctionalState NewState);
+void RTC_CntIncrIntConfig (LPC_RTC_TypeDef *RTCx, uint32_t CntIncrIntType, \
+ FunctionalState NewState);
+void RTC_AlarmIntConfig (LPC_RTC_TypeDef *RTCx, uint32_t AlarmTimeType, \
+ FunctionalState NewState);
+void RTC_SetTime (LPC_RTC_TypeDef *RTCx, uint32_t Timetype, uint32_t TimeValue);
+uint32_t RTC_GetTime(LPC_RTC_TypeDef *RTCx, uint32_t Timetype);
+void RTC_SetFullTime (LPC_RTC_TypeDef *RTCx, RTC_TIME_Type *pFullTime);
+void RTC_GetFullTime (LPC_RTC_TypeDef *RTCx, RTC_TIME_Type *pFullTime);
+void RTC_SetAlarmTime (LPC_RTC_TypeDef *RTCx, uint32_t Timetype, uint32_t ALValue);
+uint32_t RTC_GetAlarmTime (LPC_RTC_TypeDef *RTCx, uint32_t Timetype);
+void RTC_SetFullAlarmTime (LPC_RTC_TypeDef *RTCx, RTC_TIME_Type *pFullTime);
+void RTC_GetFullAlarmTime (LPC_RTC_TypeDef *RTCx, RTC_TIME_Type *pFullTime);
+IntStatus RTC_GetIntPending (LPC_RTC_TypeDef *RTCx, uint32_t IntType);
+void RTC_ClearIntPending (LPC_RTC_TypeDef *RTCx, uint32_t IntType);
+void RTC_CalibCounterCmd(LPC_RTC_TypeDef *RTCx, FunctionalState NewState);
+void RTC_CalibConfig(LPC_RTC_TypeDef *RTCx, uint32_t CalibValue, uint8_t CalibDir);
+void RTC_WriteGPREG (LPC_RTC_TypeDef *RTCx, uint8_t Channel, uint32_t Value);
+uint32_t RTC_ReadGPREG (LPC_RTC_TypeDef *RTCx, uint8_t Channel);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC17XX_RTC_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/src/shared/cmsis/Drivers/include/lpc17xx_spi.h b/src/shared/cmsis/Drivers/include/lpc17xx_spi.h
@@ -0,0 +1,328 @@
+/**********************************************************************
+* $Id$ lpc17xx_spi.h 2010-05-21
+*//**
+* @file lpc17xx_spi.h
+* @brief Contains all macro definitions and function prototypes
+* support for SPI firmware library on LPC17xx
+* @version 2.0
+* @date 21. May. 2010
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2010, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup SPI SPI (Serial Peripheral Interface)
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_SPI_H_
+#define LPC17XX_SPI_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup SPI_Public_Macros SPI Public Macros
+ * @{
+ */
+
+/*********************************************************************//**
+ * SPI configuration parameter defines
+ **********************************************************************/
+/** Clock phase control bit */
+#define SPI_CPHA_FIRST ((uint32_t)(0))
+#define SPI_CPHA_SECOND ((uint32_t)(1<<3))
+
+/** Clock polarity control bit */
+#define SPI_CPOL_HI ((uint32_t)(0))
+#define SPI_CPOL_LO ((uint32_t)(1<<4))
+
+/** SPI master mode enable */
+#define SPI_SLAVE_MODE ((uint32_t)(0))
+#define SPI_MASTER_MODE ((uint32_t)(1<<5))
+
+/** LSB enable bit */
+#define SPI_DATA_MSB_FIRST ((uint32_t)(0))
+#define SPI_DATA_LSB_FIRST ((uint32_t)(1<<6))
+
+/** SPI data bit number defines */
+#define SPI_DATABIT_16 SPI_SPCR_BITS(0) /*!< Databit number = 16 */
+#define SPI_DATABIT_8 SPI_SPCR_BITS(0x08) /*!< Databit number = 8 */
+#define SPI_DATABIT_9 SPI_SPCR_BITS(0x09) /*!< Databit number = 9 */
+#define SPI_DATABIT_10 SPI_SPCR_BITS(0x0A) /*!< Databit number = 10 */
+#define SPI_DATABIT_11 SPI_SPCR_BITS(0x0B) /*!< Databit number = 11 */
+#define SPI_DATABIT_12 SPI_SPCR_BITS(0x0C) /*!< Databit number = 12 */
+#define SPI_DATABIT_13 SPI_SPCR_BITS(0x0D) /*!< Databit number = 13 */
+#define SPI_DATABIT_14 SPI_SPCR_BITS(0x0E) /*!< Databit number = 14 */
+#define SPI_DATABIT_15 SPI_SPCR_BITS(0x0F) /*!< Databit number = 15 */
+
+/*********************************************************************//**
+ * SPI Status Flag defines
+ **********************************************************************/
+/** Slave abort */
+#define SPI_STAT_ABRT SPI_SPSR_ABRT
+/** Mode fault */
+#define SPI_STAT_MODF SPI_SPSR_MODF
+/** Read overrun */
+#define SPI_STAT_ROVR SPI_SPSR_ROVR
+/** Write collision */
+#define SPI_STAT_WCOL SPI_SPSR_WCOL
+/** SPI transfer complete flag */
+#define SPI_STAT_SPIF SPI_SPSR_SPIF
+
+/* SPI Status Implementation definitions */
+#define SPI_STAT_DONE (1UL<<8) /**< Done */
+#define SPI_STAT_ERROR (1UL<<9) /**< Error */
+
+/**
+ * @}
+ */
+
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup SPI_Private_Macros SPI Private Macros
+ * @{
+ */
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/*********************************************************************//**
+ * Macro defines for SPI Control Register
+ **********************************************************************/
+/** Bit enable, the SPI controller sends and receives the number
+ * of bits selected by bits 11:8 */
+#define SPI_SPCR_BIT_EN ((uint32_t)(1<<2))
+/** Clock phase control bit */
+#define SPI_SPCR_CPHA_SECOND ((uint32_t)(1<<3))
+/** Clock polarity control bit */
+#define SPI_SPCR_CPOL_LOW ((uint32_t)(1<<4))
+/** SPI master mode enable */
+#define SPI_SPCR_MSTR ((uint32_t)(1<<5))
+/** LSB enable bit */
+#define SPI_SPCR_LSBF ((uint32_t)(1<<6))
+/** SPI interrupt enable bit */
+#define SPI_SPCR_SPIE ((uint32_t)(1<<7))
+/** When bit 2 of this register is 1, this field controls the
+number of bits per transfer */
+#define SPI_SPCR_BITS(n) ((n==0) ? ((uint32_t)0) : ((uint32_t)((n&0x0F)<<8)))
+/** SPI Control bit mask */
+#define SPI_SPCR_BITMASK ((uint32_t)(0xFFC))
+
+/*********************************************************************//**
+ * Macro defines for SPI Status Register
+ **********************************************************************/
+/** Slave abort */
+#define SPI_SPSR_ABRT ((uint32_t)(1<<3))
+/** Mode fault */
+#define SPI_SPSR_MODF ((uint32_t)(1<<4))
+/** Read overrun */
+#define SPI_SPSR_ROVR ((uint32_t)(1<<5))
+/** Write collision */
+#define SPI_SPSR_WCOL ((uint32_t)(1<<6))
+/** SPI transfer complete flag */
+#define SPI_SPSR_SPIF ((uint32_t)(1<<7))
+/** SPI Status bit mask */
+#define SPI_SPSR_BITMASK ((uint32_t)(0xF8))
+
+/*********************************************************************//**
+ * Macro defines for SPI Data Register
+ **********************************************************************/
+/** SPI Data low bit-mask */
+#define SPI_SPDR_LO_MASK ((uint32_t)(0xFF))
+/** SPI Data high bit-mask */
+#define SPI_SPDR_HI_MASK ((uint32_t)(0xFF00))
+/** SPI Data bit-mask */
+#define SPI_SPDR_BITMASK ((uint32_t)(0xFFFF))
+
+/*********************************************************************//**
+ * Macro defines for SPI Clock Counter Register
+ **********************************************************************/
+/** SPI clock counter setting */
+#define SPI_SPCCR_COUNTER(n) ((uint32_t)(n&0xFF))
+/** SPI clock counter bit-mask */
+#define SPI_SPCCR_BITMASK ((uint32_t)(0xFF))
+
+/***********************************************************************
+ * Macro defines for SPI Test Control Register
+ **********************************************************************/
+/** SPI Test bit */
+#define SPI_SPTCR_TEST_MASK ((uint32_t)(0xFE))
+/** SPI Test register bit mask */
+#define SPI_SPTCR_BITMASK ((uint32_t)(0xFE))
+
+/*********************************************************************//**
+ * Macro defines for SPI Test Status Register
+ **********************************************************************/
+/** Slave abort */
+#define SPI_SPTSR_ABRT ((uint32_t)(1<<3))
+/** Mode fault */
+#define SPI_SPTSR_MODF ((uint32_t)(1<<4))
+/** Read overrun */
+#define SPI_SPTSR_ROVR ((uint32_t)(1<<5))
+/** Write collision */
+#define SPI_SPTSR_WCOL ((uint32_t)(1<<6))
+/** SPI transfer complete flag */
+#define SPI_SPTSR_SPIF ((uint32_t)(1<<7))
+/** SPI Status bit mask */
+#define SPI_SPTSR_MASKBIT ((uint32_t)(0xF8))
+
+/*********************************************************************//**
+ * Macro defines for SPI Interrupt Register
+ **********************************************************************/
+/** SPI interrupt flag */
+#define SPI_SPINT_INTFLAG ((uint32_t)(1<<0))
+/** SPI interrupt register bit mask */
+#define SPI_SPINT_BITMASK ((uint32_t)(0x01))
+
+
+/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
+/** Macro to determine if it is valid SPI port number */
+#define PARAM_SPIx(n) (((uint32_t *)n)==((uint32_t *)LPC_SPI))
+
+/** Macro check Clock phase control mode */
+#define PARAM_SPI_CPHA(n) ((n==SPI_CPHA_FIRST) || (n==SPI_CPHA_SECOND))
+
+/** Macro check Clock polarity control mode */
+#define PARAM_SPI_CPOL(n) ((n==SPI_CPOL_HI) || (n==SPI_CPOL_LO))
+
+/** Macro check master/slave mode */
+#define PARAM_SPI_MODE(n) ((n==SPI_SLAVE_MODE) || (n==SPI_MASTER_MODE))
+
+/** Macro check LSB/MSB mode */
+#define PARAM_SPI_DATA_ORDER(n) ((n==SPI_DATA_MSB_FIRST) || (n==SPI_DATA_LSB_FIRST))
+
+/** Macro check databit value */
+#define PARAM_SPI_DATABIT(n) ((n==SPI_DATABIT_16) || (n==SPI_DATABIT_8) \
+|| (n==SPI_DATABIT_9) || (n==SPI_DATABIT_10) \
+|| (n==SPI_DATABIT_11) || (n==SPI_DATABIT_12) \
+|| (n==SPI_DATABIT_13) || (n==SPI_DATABIT_14) \
+|| (n==SPI_DATABIT_15))
+
+/** Macro check status flag */
+#define PARAM_SPI_STAT(n) ((n==SPI_STAT_ABRT) || (n==SPI_STAT_MODF) \
+|| (n==SPI_STAT_ROVR) || (n==SPI_STAT_WCOL) \
+|| (n==SPI_STAT_SPIF))
+
+/**
+ * @}
+ */
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup SPI_Public_Types SPI Public Types
+ * @{
+ */
+
+/** @brief SPI configuration structure */
+typedef struct {
+ uint32_t Databit; /** Databit number, should be SPI_DATABIT_x,
+ where x is in range from 8 - 16 */
+ uint32_t CPHA; /** Clock phase, should be:
+ - SPI_CPHA_FIRST: first clock edge
+ - SPI_CPHA_SECOND: second clock edge */
+ uint32_t CPOL; /** Clock polarity, should be:
+ - SPI_CPOL_HI: high level
+ - SPI_CPOL_LO: low level */
+ uint32_t Mode; /** SPI mode, should be:
+ - SPI_MASTER_MODE: Master mode
+ - SPI_SLAVE_MODE: Slave mode */
+ uint32_t DataOrder; /** Data order, should be:
+ - SPI_DATA_MSB_FIRST: MSB first
+ - SPI_DATA_LSB_FIRST: LSB first */
+ uint32_t ClockRate; /** Clock rate,in Hz, should not exceed
+ (SPI peripheral clock)/8 */
+} SPI_CFG_Type;
+
+
+/**
+ * @brief SPI Transfer Type definitions
+ */
+typedef enum {
+ SPI_TRANSFER_POLLING = 0, /**< Polling transfer */
+ SPI_TRANSFER_INTERRUPT /**< Interrupt transfer */
+} SPI_TRANSFER_Type;
+
+/**
+ * @brief SPI Data configuration structure definitions
+ */
+typedef struct {
+ void *tx_data; /**< Pointer to transmit data */
+ void *rx_data; /**< Pointer to transmit data */
+ uint32_t length; /**< Length of transfer data */
+ uint32_t counter; /**< Data counter index */
+ uint32_t status; /**< Current status of SPI activity */
+} SPI_DATA_SETUP_Type;
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup SPI_Public_Functions SPI Public Functions
+ * @{
+ */
+
+/* SPI Init/DeInit functions ---------*/
+void SPI_Init(LPC_SPI_TypeDef *SPIx, SPI_CFG_Type *SPI_ConfigStruct);
+void SPI_DeInit(LPC_SPI_TypeDef *SPIx);
+void SPI_SetClock (LPC_SPI_TypeDef *SPIx, uint32_t target_clock);
+void SPI_ConfigStructInit(SPI_CFG_Type *SPI_InitStruct);
+
+/* SPI transfer functions ------------*/
+void SPI_SendData(LPC_SPI_TypeDef *SPIx, uint16_t Data);
+uint16_t SPI_ReceiveData(LPC_SPI_TypeDef *SPIx);
+int32_t SPI_ReadWrite (LPC_SPI_TypeDef *SPIx, SPI_DATA_SETUP_Type *dataCfg, SPI_TRANSFER_Type xfType);
+
+/* SPI Interrupt functions ---------*/
+void SPI_IntCmd(LPC_SPI_TypeDef *SPIx, FunctionalState NewState);
+IntStatus SPI_GetIntStatus (LPC_SPI_TypeDef *SPIx);
+void SPI_ClearIntPending(LPC_SPI_TypeDef *SPIx);
+
+/* SPI get information functions-----*/
+uint8_t SPI_GetDataSize (LPC_SPI_TypeDef *SPIx);
+uint32_t SPI_GetStatus(LPC_SPI_TypeDef *SPIx);
+FlagStatus SPI_CheckStatus (uint32_t inputSPIStatus, uint8_t SPIStatus);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC17XX_SPI_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/src/shared/cmsis/Drivers/include/lpc17xx_ssp.h b/src/shared/cmsis/Drivers/include/lpc17xx_ssp.h
@@ -0,0 +1,472 @@
+/**********************************************************************
+* $Id$ lpc17xx_ssp.h 2010-06-18
+*//**
+* @file lpc17xx_ssp.h
+* @brief Contains all macro definitions and function prototypes
+* support for SSP firmware library on LPC17xx
+* @version 3.0
+* @date 18. June. 2010
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2010, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup SSP SSP (Synchronous Serial Port)
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_SSP_H_
+#define LPC17XX_SSP_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup SSP_Public_Macros SSP Public Macros
+ * @{
+ */
+
+/*********************************************************************//**
+ * SSP configuration parameter defines
+ **********************************************************************/
+/** Clock phase control bit */
+#define SSP_CPHA_FIRST ((uint32_t)(0))
+#define SSP_CPHA_SECOND SSP_CR0_CPHA_SECOND
+
+
+/** Clock polarity control bit */
+/* There's no bug here!!!
+ * - If bit[6] in SSPnCR0 is 0: SSP controller maintains the bus clock low between frames.
+ * That means the active clock is in HI state.
+ * - If bit[6] in SSPnCR0 is 1 (SSP_CR0_CPOL_HI): SSP controller maintains the bus clock
+ * high between frames. That means the active clock is in LO state.
+ */
+#define SSP_CPOL_HI ((uint32_t)(0))
+#define SSP_CPOL_LO SSP_CR0_CPOL_HI
+
+/** SSP master mode enable */
+#define SSP_SLAVE_MODE SSP_CR1_SLAVE_EN
+#define SSP_MASTER_MODE ((uint32_t)(0))
+
+/** SSP data bit number defines */
+#define SSP_DATABIT_4 SSP_CR0_DSS(4) /*!< Databit number = 4 */
+#define SSP_DATABIT_5 SSP_CR0_DSS(5) /*!< Databit number = 5 */
+#define SSP_DATABIT_6 SSP_CR0_DSS(6) /*!< Databit number = 6 */
+#define SSP_DATABIT_7 SSP_CR0_DSS(7) /*!< Databit number = 7 */
+#define SSP_DATABIT_8 SSP_CR0_DSS(8) /*!< Databit number = 8 */
+#define SSP_DATABIT_9 SSP_CR0_DSS(9) /*!< Databit number = 9 */
+#define SSP_DATABIT_10 SSP_CR0_DSS(10) /*!< Databit number = 10 */
+#define SSP_DATABIT_11 SSP_CR0_DSS(11) /*!< Databit number = 11 */
+#define SSP_DATABIT_12 SSP_CR0_DSS(12) /*!< Databit number = 12 */
+#define SSP_DATABIT_13 SSP_CR0_DSS(13) /*!< Databit number = 13 */
+#define SSP_DATABIT_14 SSP_CR0_DSS(14) /*!< Databit number = 14 */
+#define SSP_DATABIT_15 SSP_CR0_DSS(15) /*!< Databit number = 15 */
+#define SSP_DATABIT_16 SSP_CR0_DSS(16) /*!< Databit number = 16 */
+
+/** SSP Frame Format definition */
+/** Motorola SPI mode */
+#define SSP_FRAME_SPI SSP_CR0_FRF_SPI
+/** TI synchronous serial mode */
+#define SSP_FRAME_TI SSP_CR0_FRF_TI
+/** National Micro-wire mode */
+#define SSP_FRAME_MICROWIRE SSP_CR0_FRF_MICROWIRE
+
+/*********************************************************************//**
+ * SSP Status defines
+ **********************************************************************/
+/** SSP status TX FIFO Empty bit */
+#define SSP_STAT_TXFIFO_EMPTY SSP_SR_TFE
+/** SSP status TX FIFO not full bit */
+#define SSP_STAT_TXFIFO_NOTFULL SSP_SR_TNF
+/** SSP status RX FIFO not empty bit */
+#define SSP_STAT_RXFIFO_NOTEMPTY SSP_SR_RNE
+/** SSP status RX FIFO full bit */
+#define SSP_STAT_RXFIFO_FULL SSP_SR_RFF
+/** SSP status SSP Busy bit */
+#define SSP_STAT_BUSY SSP_SR_BSY
+
+/*********************************************************************//**
+ * SSP Interrupt Configuration defines
+ **********************************************************************/
+/** Receive Overrun */
+#define SSP_INTCFG_ROR SSP_IMSC_ROR
+/** Receive TimeOut */
+#define SSP_INTCFG_RT SSP_IMSC_RT
+/** Rx FIFO is at least half full */
+#define SSP_INTCFG_RX SSP_IMSC_RX
+/** Tx FIFO is at least half empty */
+#define SSP_INTCFG_TX SSP_IMSC_TX
+
+/*********************************************************************//**
+ * SSP Configured Interrupt Status defines
+ **********************************************************************/
+/** Receive Overrun */
+#define SSP_INTSTAT_ROR SSP_MIS_ROR
+/** Receive TimeOut */
+#define SSP_INTSTAT_RT SSP_MIS_RT
+/** Rx FIFO is at least half full */
+#define SSP_INTSTAT_RX SSP_MIS_RX
+/** Tx FIFO is at least half empty */
+#define SSP_INTSTAT_TX SSP_MIS_TX
+
+/*********************************************************************//**
+ * SSP Raw Interrupt Status defines
+ **********************************************************************/
+/** Receive Overrun */
+#define SSP_INTSTAT_RAW_ROR SSP_RIS_ROR
+/** Receive TimeOut */
+#define SSP_INTSTAT_RAW_RT SSP_RIS_RT
+/** Rx FIFO is at least half full */
+#define SSP_INTSTAT_RAW_RX SSP_RIS_RX
+/** Tx FIFO is at least half empty */
+#define SSP_INTSTAT_RAW_TX SSP_RIS_TX
+
+/*********************************************************************//**
+ * SSP Interrupt Clear defines
+ **********************************************************************/
+/** Writing a 1 to this bit clears the "frame was received when
+ * RxFIFO was full" interrupt */
+#define SSP_INTCLR_ROR SSP_ICR_ROR
+/** Writing a 1 to this bit clears the "Rx FIFO was not empty and
+ * has not been read for a timeout period" interrupt */
+#define SSP_INTCLR_RT SSP_ICR_RT
+
+/*********************************************************************//**
+ * SSP DMA defines
+ **********************************************************************/
+/** SSP bit for enabling RX DMA */
+#define SSP_DMA_RX SSP_DMA_RXDMA_EN
+/** SSP bit for enabling TX DMA */
+#define SSP_DMA_TX SSP_DMA_TXDMA_EN
+
+/* SSP Status Implementation definitions */
+#define SSP_STAT_DONE (1UL<<8) /**< Done */
+#define SSP_STAT_ERROR (1UL<<9) /**< Error */
+
+/**
+ * @}
+ */
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup SSP_Private_Macros SSP Private Macros
+ * @{
+ */
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/*********************************************************************//**
+ * Macro defines for CR0 register
+ **********************************************************************/
+/** SSP data size select, must be 4 bits to 16 bits */
+#define SSP_CR0_DSS(n) ((uint32_t)((n-1)&0xF))
+/** SSP control 0 Motorola SPI mode */
+#define SSP_CR0_FRF_SPI ((uint32_t)(0<<4))
+/** SSP control 0 TI synchronous serial mode */
+#define SSP_CR0_FRF_TI ((uint32_t)(1<<4))
+/** SSP control 0 National Micro-wire mode */
+#define SSP_CR0_FRF_MICROWIRE ((uint32_t)(2<<4))
+/** SPI clock polarity bit (used in SPI mode only), (1) = maintains the
+ bus clock high between frames, (0) = low */
+#define SSP_CR0_CPOL_HI ((uint32_t)(1<<6))
+/** SPI clock out phase bit (used in SPI mode only), (1) = captures data
+ on the second clock transition of the frame, (0) = first */
+#define SSP_CR0_CPHA_SECOND ((uint32_t)(1<<7))
+/** SSP serial clock rate value load macro, divider rate is
+ PERIPH_CLK / (cpsr * (SCR + 1)) */
+#define SSP_CR0_SCR(n) ((uint32_t)((n&0xFF)<<8))
+/** SSP CR0 bit mask */
+#define SSP_CR0_BITMASK ((uint32_t)(0xFFFF))
+
+/*********************************************************************//**
+ * Macro defines for CR1 register
+ **********************************************************************/
+/** SSP control 1 loopback mode enable bit */
+#define SSP_CR1_LBM_EN ((uint32_t)(1<<0))
+/** SSP control 1 enable bit */
+#define SSP_CR1_SSP_EN ((uint32_t)(1<<1))
+/** SSP control 1 slave enable */
+#define SSP_CR1_SLAVE_EN ((uint32_t)(1<<2))
+/** SSP control 1 slave out disable bit, disables transmit line in slave
+ mode */
+#define SSP_CR1_SO_DISABLE ((uint32_t)(1<<3))
+/** SSP CR1 bit mask */
+#define SSP_CR1_BITMASK ((uint32_t)(0x0F))
+
+/*********************************************************************//**
+ * Macro defines for DR register
+ **********************************************************************/
+/** SSP data bit mask */
+#define SSP_DR_BITMASK(n) ((n)&0xFFFF)
+
+/*********************************************************************//**
+ * Macro defines for SR register
+ **********************************************************************/
+/** SSP status TX FIFO Empty bit */
+#define SSP_SR_TFE ((uint32_t)(1<<0))
+/** SSP status TX FIFO not full bit */
+#define SSP_SR_TNF ((uint32_t)(1<<1))
+/** SSP status RX FIFO not empty bit */
+#define SSP_SR_RNE ((uint32_t)(1<<2))
+/** SSP status RX FIFO full bit */
+#define SSP_SR_RFF ((uint32_t)(1<<3))
+/** SSP status SSP Busy bit */
+#define SSP_SR_BSY ((uint32_t)(1<<4))
+/** SSP SR bit mask */
+#define SSP_SR_BITMASK ((uint32_t)(0x1F))
+
+/*********************************************************************//**
+ * Macro defines for CPSR register
+ **********************************************************************/
+/** SSP clock prescaler */
+#define SSP_CPSR_CPDVSR(n) ((uint32_t)(n&0xFF))
+/** SSP CPSR bit mask */
+#define SSP_CPSR_BITMASK ((uint32_t)(0xFF))
+
+/*********************************************************************//**
+ * Macro define for (IMSC) Interrupt Mask Set/Clear registers
+ **********************************************************************/
+/** Receive Overrun */
+#define SSP_IMSC_ROR ((uint32_t)(1<<0))
+/** Receive TimeOut */
+#define SSP_IMSC_RT ((uint32_t)(1<<1))
+/** Rx FIFO is at least half full */
+#define SSP_IMSC_RX ((uint32_t)(1<<2))
+/** Tx FIFO is at least half empty */
+#define SSP_IMSC_TX ((uint32_t)(1<<3))
+/** IMSC bit mask */
+#define SSP_IMSC_BITMASK ((uint32_t)(0x0F))
+
+/*********************************************************************//**
+ * Macro define for (RIS) Raw Interrupt Status registers
+ **********************************************************************/
+/** Receive Overrun */
+#define SSP_RIS_ROR ((uint32_t)(1<<0))
+/** Receive TimeOut */
+#define SSP_RIS_RT ((uint32_t)(1<<1))
+/** Rx FIFO is at least half full */
+#define SSP_RIS_RX ((uint32_t)(1<<2))
+/** Tx FIFO is at least half empty */
+#define SSP_RIS_TX ((uint32_t)(1<<3))
+/** RIS bit mask */
+#define SSP_RIS_BITMASK ((uint32_t)(0x0F))
+
+/*********************************************************************//**
+ * Macro define for (MIS) Masked Interrupt Status registers
+ **********************************************************************/
+/** Receive Overrun */
+#define SSP_MIS_ROR ((uint32_t)(1<<0))
+/** Receive TimeOut */
+#define SSP_MIS_RT ((uint32_t)(1<<1))
+/** Rx FIFO is at least half full */
+#define SSP_MIS_RX ((uint32_t)(1<<2))
+/** Tx FIFO is at least half empty */
+#define SSP_MIS_TX ((uint32_t)(1<<3))
+/** MIS bit mask */
+#define SSP_MIS_BITMASK ((uint32_t)(0x0F))
+
+/*********************************************************************//**
+ * Macro define for (ICR) Interrupt Clear registers
+ **********************************************************************/
+/** Writing a 1 to this bit clears the "frame was received when
+ * RxFIFO was full" interrupt */
+#define SSP_ICR_ROR ((uint32_t)(1<<0))
+/** Writing a 1 to this bit clears the "Rx FIFO was not empty and
+ * has not been read for a timeout period" interrupt */
+#define SSP_ICR_RT ((uint32_t)(1<<1))
+/** ICR bit mask */
+#define SSP_ICR_BITMASK ((uint32_t)(0x03))
+
+/*********************************************************************//**
+ * Macro defines for DMACR register
+ **********************************************************************/
+/** SSP bit for enabling RX DMA */
+#define SSP_DMA_RXDMA_EN ((uint32_t)(1<<0))
+/** SSP bit for enabling TX DMA */
+#define SSP_DMA_TXDMA_EN ((uint32_t)(1<<1))
+/** DMACR bit mask */
+#define SSP_DMA_BITMASK ((uint32_t)(0x03))
+
+
+/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
+/** Macro to determine if it is valid SSP port number */
+#define PARAM_SSPx(n) ((((uint32_t *)n)==((uint32_t *)LPC_SSP0)) \
+|| (((uint32_t *)n)==((uint32_t *)LPC_SSP1)))
+
+/** Macro check clock phase control mode */
+#define PARAM_SSP_CPHA(n) ((n==SSP_CPHA_FIRST) || (n==SSP_CPHA_SECOND))
+
+/** Macro check clock polarity mode */
+#define PARAM_SSP_CPOL(n) ((n==SSP_CPOL_HI) || (n==SSP_CPOL_LO))
+
+/* Macro check master/slave mode */
+#define PARAM_SSP_MODE(n) ((n==SSP_SLAVE_MODE) || (n==SSP_MASTER_MODE))
+
+/* Macro check databit value */
+#define PARAM_SSP_DATABIT(n) ((n==SSP_DATABIT_4) || (n==SSP_DATABIT_5) \
+|| (n==SSP_DATABIT_6) || (n==SSP_DATABIT_16) \
+|| (n==SSP_DATABIT_7) || (n==SSP_DATABIT_8) \
+|| (n==SSP_DATABIT_9) || (n==SSP_DATABIT_10) \
+|| (n==SSP_DATABIT_11) || (n==SSP_DATABIT_12) \
+|| (n==SSP_DATABIT_13) || (n==SSP_DATABIT_14) \
+|| (n==SSP_DATABIT_15))
+
+/* Macro check frame type */
+#define PARAM_SSP_FRAME(n) ((n==SSP_FRAME_SPI) || (n==SSP_FRAME_TI)\
+|| (n==SSP_FRAME_MICROWIRE))
+
+/* Macro check SSP status */
+#define PARAM_SSP_STAT(n) ((n==SSP_STAT_TXFIFO_EMPTY) || (n==SSP_STAT_TXFIFO_NOTFULL) \
+|| (n==SSP_STAT_RXFIFO_NOTEMPTY) || (n==SSP_STAT_RXFIFO_FULL) \
+|| (n==SSP_STAT_BUSY))
+
+/* Macro check interrupt configuration */
+#define PARAM_SSP_INTCFG(n) ((n==SSP_INTCFG_ROR) || (n==SSP_INTCFG_RT) \
+|| (n==SSP_INTCFG_RX) || (n==SSP_INTCFG_TX))
+
+/* Macro check interrupt status value */
+#define PARAM_SSP_INTSTAT(n) ((n==SSP_INTSTAT_ROR) || (n==SSP_INTSTAT_RT) \
+|| (n==SSP_INTSTAT_RX) || (n==SSP_INTSTAT_TX))
+
+/* Macro check interrupt status raw value */
+#define PARAM_SSP_INTSTAT_RAW(n) ((n==SSP_INTSTAT_RAW_ROR) || (n==SSP_INTSTAT_RAW_RT) \
+|| (n==SSP_INTSTAT_RAW_RX) || (n==SSP_INTSTAT_RAW_TX))
+
+/* Macro check interrupt clear mode */
+#define PARAM_SSP_INTCLR(n) ((n==SSP_INTCLR_ROR) || (n==SSP_INTCLR_RT))
+
+/* Macro check DMA mode */
+#define PARAM_SSP_DMA(n) ((n==SSP_DMA_TX) || (n==SSP_DMA_RX))
+/**
+ * @}
+ */
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup SSP_Public_Types SSP Public Types
+ * @{
+ */
+
+/** @brief SSP configuration structure */
+typedef struct {
+ uint32_t Databit; /** Databit number, should be SSP_DATABIT_x,
+ where x is in range from 4 - 16 */
+ uint32_t CPHA; /** Clock phase, should be:
+ - SSP_CPHA_FIRST: first clock edge
+ - SSP_CPHA_SECOND: second clock edge */
+ uint32_t CPOL; /** Clock polarity, should be:
+ - SSP_CPOL_HI: high level
+ - SSP_CPOL_LO: low level */
+ uint32_t Mode; /** SSP mode, should be:
+ - SSP_MASTER_MODE: Master mode
+ - SSP_SLAVE_MODE: Slave mode */
+ uint32_t FrameFormat; /** Frame Format:
+ - SSP_FRAME_SPI: Motorola SPI frame format
+ - SSP_FRAME_TI: TI frame format
+ - SSP_FRAME_MICROWIRE: National Microwire frame format */
+ uint32_t ClockRate; /** Clock rate,in Hz */
+} SSP_CFG_Type;
+
+/**
+ * @brief SSP Transfer Type definitions
+ */
+typedef enum {
+ SSP_TRANSFER_POLLING = 0, /**< Polling transfer */
+ SSP_TRANSFER_INTERRUPT /**< Interrupt transfer */
+} SSP_TRANSFER_Type;
+
+/**
+ * @brief SPI Data configuration structure definitions
+ */
+typedef struct {
+ void *tx_data; /**< Pointer to transmit data */
+ uint32_t tx_cnt; /**< Transmit counter */
+ void *rx_data; /**< Pointer to transmit data */
+ uint32_t rx_cnt; /**< Receive counter */
+ uint32_t length; /**< Length of transfer data */
+ uint32_t status; /**< Current status of SSP activity */
+} SSP_DATA_SETUP_Type;
+
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup SSP_Public_Functions SSP Public Functions
+ * @{
+ */
+
+/* SSP Init/DeInit functions --------------------------------------------------*/
+void SSP_Init(LPC_SSP_TypeDef *SSPx, SSP_CFG_Type *SSP_ConfigStruct);
+void SSP_DeInit(LPC_SSP_TypeDef* SSPx);
+
+/* SSP configure functions ----------------------------------------------------*/
+void SSP_ConfigStructInit(SSP_CFG_Type *SSP_InitStruct);
+
+/* SSP enable/disable functions -----------------------------------------------*/
+void SSP_Cmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState);
+void SSP_LoopBackCmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState);
+void SSP_SlaveOutputCmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState);
+void SSP_DMACmd(LPC_SSP_TypeDef *SSPx, uint32_t DMAMode, FunctionalState NewState);
+
+/* SSP get information functions ----------------------------------------------*/
+FlagStatus SSP_GetStatus(LPC_SSP_TypeDef* SSPx, uint32_t FlagType);
+uint8_t SSP_GetDataSize(LPC_SSP_TypeDef* SSPx);
+IntStatus SSP_GetRawIntStatus(LPC_SSP_TypeDef *SSPx, uint32_t RawIntType);
+uint32_t SSP_GetRawIntStatusReg(LPC_SSP_TypeDef *SSPx);
+IntStatus SSP_GetIntStatus (LPC_SSP_TypeDef *SSPx, uint32_t IntType);
+
+/* SSP transfer data functions ------------------------------------------------*/
+void SSP_SendData(LPC_SSP_TypeDef* SSPx, uint16_t Data);
+uint16_t SSP_ReceiveData(LPC_SSP_TypeDef* SSPx);
+int32_t SSP_ReadWrite (LPC_SSP_TypeDef *SSPx, SSP_DATA_SETUP_Type *dataCfg, \
+ SSP_TRANSFER_Type xfType);
+
+/* SSP IRQ function ------------------------------------------------------------*/
+void SSP_IntConfig(LPC_SSP_TypeDef *SSPx, uint32_t IntType, FunctionalState NewState);
+void SSP_ClearIntPending(LPC_SSP_TypeDef *SSPx, uint32_t IntType);
+
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC17XX_SSP_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/src/shared/cmsis/Drivers/include/lpc17xx_systick.h b/src/shared/cmsis/Drivers/include/lpc17xx_systick.h
@@ -0,0 +1,119 @@
+/**********************************************************************
+* $Id$ lpc17xx_systick.h 2010-05-21
+*//**
+* @file lpc17xx_systick.h
+* @brief Contains all macro definitions and function prototypes
+* support for SYSTICK firmware library on LPC17xx
+* @version 2.0
+* @date 21. May. 2010
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2010, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup SYSTICK SYSTICK (System Tick)
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_SYSTICK_H_
+#define LPC17XX_SYSTICK_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup SYSTICK_Private_Macros SYSTICK Private Macros
+ * @{
+ */
+/*********************************************************************//**
+ * Macro defines for System Timer Control and status (STCTRL) register
+ **********************************************************************/
+#define ST_CTRL_ENABLE ((uint32_t)(1<<0))
+#define ST_CTRL_TICKINT ((uint32_t)(1<<1))
+#define ST_CTRL_CLKSOURCE ((uint32_t)(1<<2))
+#define ST_CTRL_COUNTFLAG ((uint32_t)(1<<16))
+
+/*********************************************************************//**
+ * Macro defines for System Timer Reload value (STRELOAD) register
+ **********************************************************************/
+#define ST_RELOAD_RELOAD(n) ((uint32_t)(n & 0x00FFFFFF))
+
+/*********************************************************************//**
+ * Macro defines for System Timer Current value (STCURRENT) register
+ **********************************************************************/
+#define ST_RELOAD_CURRENT(n) ((uint32_t)(n & 0x00FFFFFF))
+
+/*********************************************************************//**
+ * Macro defines for System Timer Calibration value (STCALIB) register
+ **********************************************************************/
+#define ST_CALIB_TENMS(n) ((uint32_t)(n & 0x00FFFFFF))
+#define ST_CALIB_SKEW ((uint32_t)(1<<30))
+#define ST_CALIB_NOREF ((uint32_t)(1<<31))
+
+#define CLKSOURCE_EXT ((uint32_t)(0))
+#define CLKSOURCE_CPU ((uint32_t)(1))
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup SYSTICK_Public_Functions SYSTICK Public Functions
+ * @{
+ */
+
+void SYSTICK_InternalInit(uint32_t time);
+void SYSTICK_ExternalInit(uint32_t freq, uint32_t time);
+
+void SYSTICK_Cmd(FunctionalState NewState);
+void SYSTICK_IntCmd(FunctionalState NewState);
+uint32_t SYSTICK_GetCurrentValue(void);
+void SYSTICK_ClearCounterFlag(void);
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* LPC17XX_SYSTICK_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/src/shared/cmsis/Drivers/include/lpc17xx_timer.h b/src/shared/cmsis/Drivers/include/lpc17xx_timer.h
@@ -0,0 +1,348 @@
+/**********************************************************************
+* $Id$ lpc17xx_timer.h 2010-05-21
+*//**
+* @file lpc17xx_timer.h
+* @brief Contains all macro definitions and function prototypes
+* support for Timer firmware library on LPC17xx
+* @version 2.0
+* @date 21. May. 2010
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2010, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup TIM TIM (Timer)
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef __LPC17XX_TIMER_H_
+#define __LPC17XX_TIMER_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup TIM_Private_Macros TIM Private Macros
+ * @{
+ */
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/**********************************************************************
+** Interrupt information
+**********************************************************************/
+/** Macro to clean interrupt pending */
+#define TIM_IR_CLR(n) _BIT(n)
+
+/**********************************************************************
+** Timer interrupt register definitions
+**********************************************************************/
+/** Macro for getting a timer match interrupt bit */
+#define TIM_MATCH_INT(n) (_BIT(n & 0x0F))
+/** Macro for getting a capture event interrupt bit */
+#define TIM_CAP_INT(n) (_BIT(((n & 0x0F) + 4)))
+
+/**********************************************************************
+* Timer control register definitions
+**********************************************************************/
+/** Timer/counter enable bit */
+#define TIM_ENABLE ((uint32_t)(1<<0))
+/** Timer/counter reset bit */
+#define TIM_RESET ((uint32_t)(1<<1))
+/** Timer control bit mask */
+#define TIM_TCR_MASKBIT ((uint32_t)(3))
+
+/**********************************************************************
+* Timer match control register definitions
+**********************************************************************/
+/** Bit location for interrupt on MRx match, n = 0 to 3 */
+#define TIM_INT_ON_MATCH(n) (_BIT((n * 3)))
+/** Bit location for reset on MRx match, n = 0 to 3 */
+#define TIM_RESET_ON_MATCH(n) (_BIT(((n * 3) + 1)))
+/** Bit location for stop on MRx match, n = 0 to 3 */
+#define TIM_STOP_ON_MATCH(n) (_BIT(((n * 3) + 2)))
+/** Timer Match control bit mask */
+#define TIM_MCR_MASKBIT ((uint32_t)(0x0FFF))
+/** Timer Match control bit mask for specific channel*/
+#define TIM_MCR_CHANNEL_MASKBIT(n) ((uint32_t)(7<<(n*3)))
+
+/**********************************************************************
+* Timer capture control register definitions
+**********************************************************************/
+/** Bit location for CAP.n on CRx rising edge, n = 0 to 3 */
+#define TIM_CAP_RISING(n) (_BIT((n * 3)))
+/** Bit location for CAP.n on CRx falling edge, n = 0 to 3 */
+#define TIM_CAP_FALLING(n) (_BIT(((n * 3) + 1)))
+/** Bit location for CAP.n on CRx interrupt enable, n = 0 to 3 */
+#define TIM_INT_ON_CAP(n) (_BIT(((n * 3) + 2)))
+/** Mask bit for rising and falling edge bit */
+#define TIM_EDGE_MASK(n) (_SBF((n * 3), 0x03))
+/** Timer capture control bit mask */
+#define TIM_CCR_MASKBIT ((uint32_t)(0x3F))
+/** Timer Capture control bit mask for specific channel*/
+#define TIM_CCR_CHANNEL_MASKBIT(n) ((uint32_t)(7<<(n*3)))
+
+/**********************************************************************
+* Timer external match register definitions
+**********************************************************************/
+/** Bit location for output state change of MAT.n when external match
+ happens, n = 0 to 3 */
+#define TIM_EM(n) _BIT(n)
+/** Output state change of MAT.n when external match happens: no change */
+#define TIM_EM_NOTHING ((uint8_t)(0x0))
+/** Output state change of MAT.n when external match happens: low */
+#define TIM_EM_LOW ((uint8_t)(0x1))
+/** Output state change of MAT.n when external match happens: high */
+#define TIM_EM_HIGH ((uint8_t)(0x2))
+/** Output state change of MAT.n when external match happens: toggle */
+#define TIM_EM_TOGGLE ((uint8_t)(0x3))
+/** Macro for setting for the MAT.n change state bits */
+#define TIM_EM_SET(n,s) (_SBF(((n << 1) + 4), (s & 0x03)))
+/** Mask for the MAT.n change state bits */
+#define TIM_EM_MASK(n) (_SBF(((n << 1) + 4), 0x03))
+/** Timer external match bit mask */
+#define TIM_EMR_MASKBIT 0x0FFF
+
+/**********************************************************************
+* Timer Count Control Register definitions
+**********************************************************************/
+/** Mask to get the Counter/timer mode bits */
+#define TIM_CTCR_MODE_MASK 0x3
+/** Mask to get the count input select bits */
+#define TIM_CTCR_INPUT_MASK 0xC
+/** Timer Count control bit mask */
+#define TIM_CTCR_MASKBIT 0xF
+#define TIM_COUNTER_MODE ((uint8_t)(1))
+
+
+/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
+/** Macro to determine if it is valid TIMER peripheral */
+#define PARAM_TIMx(n) ((((uint32_t *)n)==((uint32_t *)LPC_TIM0)) || (((uint32_t *)n)==((uint32_t *)LPC_TIM1)) \
+|| (((uint32_t *)n)==((uint32_t *)LPC_TIM2)) || (((uint32_t *)n)==((uint32_t *)LPC_TIM3)))
+
+/* Macro check interrupt type */
+#define PARAM_TIM_INT_TYPE(TYPE) ((TYPE ==TIM_MR0_INT)||(TYPE ==TIM_MR1_INT)\
+||(TYPE ==TIM_MR2_INT)||(TYPE ==TIM_MR3_INT)\
+||(TYPE ==TIM_CR0_INT)||(TYPE ==TIM_CR1_INT))
+
+/* Macro check TIMER mode */
+#define PARAM_TIM_MODE_OPT(MODE) ((MODE == TIM_TIMER_MODE)||(MODE == TIM_COUNTER_RISING_MODE)\
+|| (MODE == TIM_COUNTER_RISING_MODE)||(MODE == TIM_COUNTER_RISING_MODE))
+
+/* Macro check TIMER prescale value */
+#define PARAM_TIM_PRESCALE_OPT(OPT) ((OPT == TIM_PRESCALE_TICKVAL)||(OPT == TIM_PRESCALE_USVAL))
+
+/* Macro check TIMER counter intput mode */
+#define PARAM_TIM_COUNTER_INPUT_OPT(OPT) ((OPT == TIM_COUNTER_INCAP0)||(OPT == TIM_COUNTER_INCAP1))
+
+/* Macro check TIMER external match mode */
+#define PARAM_TIM_EXTMATCH_OPT(OPT) ((OPT == TIM_EXTMATCH_NOTHING)||(OPT == TIM_EXTMATCH_LOW)\
+||(OPT == TIM_EXTMATCH_HIGH)||(OPT == TIM_EXTMATCH_TOGGLE))
+
+/* Macro check TIMER external match mode */
+#define PARAM_TIM_CAP_MODE_OPT(OPT) ((OPT == TIM_CAPTURE_NONE)||(OPT == TIM_CAPTURE_RISING) \
+||(OPT == TIM_CAPTURE_FALLING)||(OPT == TIM_CAPTURE_ANY))
+
+/**
+ * @}
+ */
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup TIM_Public_Types TIM Public Types
+ * @{
+ */
+
+/***********************************************************************
+ * Timer device enumeration
+**********************************************************************/
+/** @brief interrupt type */
+typedef enum
+{
+ TIM_MR0_INT =0, /*!< interrupt for Match channel 0*/
+ TIM_MR1_INT =1, /*!< interrupt for Match channel 1*/
+ TIM_MR2_INT =2, /*!< interrupt for Match channel 2*/
+ TIM_MR3_INT =3, /*!< interrupt for Match channel 3*/
+ TIM_CR0_INT =4, /*!< interrupt for Capture channel 0*/
+ TIM_CR1_INT =5 /*!< interrupt for Capture channel 1*/
+}TIM_INT_TYPE;
+
+/** @brief Timer/counter operating mode */
+typedef enum
+{
+ TIM_TIMER_MODE = 0, /*!< Timer mode */
+ TIM_COUNTER_RISING_MODE, /*!< Counter rising mode */
+ TIM_COUNTER_FALLING_MODE, /*!< Counter falling mode */
+ TIM_COUNTER_ANY_MODE /*!< Counter on both edges */
+} TIM_MODE_OPT;
+
+/** @brief Timer/Counter prescale option */
+typedef enum
+{
+ TIM_PRESCALE_TICKVAL = 0, /*!< Prescale in absolute value */
+ TIM_PRESCALE_USVAL /*!< Prescale in microsecond value */
+} TIM_PRESCALE_OPT;
+
+/** @brief Counter input option */
+typedef enum
+{
+ TIM_COUNTER_INCAP0 = 0, /*!< CAPn.0 input pin for TIMERn */
+ TIM_COUNTER_INCAP1, /*!< CAPn.1 input pin for TIMERn */
+} TIM_COUNTER_INPUT_OPT;
+
+/** @brief Timer/Counter external match option */
+typedef enum
+{
+ TIM_EXTMATCH_NOTHING = 0, /*!< Do nothing for external output pin if match */
+ TIM_EXTMATCH_LOW, /*!< Force external output pin to low if match */
+ TIM_EXTMATCH_HIGH, /*!< Force external output pin to high if match */
+ TIM_EXTMATCH_TOGGLE /*!< Toggle external output pin if match */
+}TIM_EXTMATCH_OPT;
+
+/** @brief Timer/counter capture mode options */
+typedef enum {
+ TIM_CAPTURE_NONE = 0, /*!< No Capture */
+ TIM_CAPTURE_RISING, /*!< Rising capture mode */
+ TIM_CAPTURE_FALLING, /*!< Falling capture mode */
+ TIM_CAPTURE_ANY /*!< On both edges */
+} TIM_CAP_MODE_OPT;
+
+/** @brief Configuration structure in TIMER mode */
+typedef struct
+{
+
+ uint8_t PrescaleOption; /**< Timer Prescale option, should be:
+ - TIM_PRESCALE_TICKVAL: Prescale in absolute value
+ - TIM_PRESCALE_USVAL: Prescale in microsecond value
+ */
+ uint8_t Reserved[3]; /**< Reserved */
+ uint32_t PrescaleValue; /**< Prescale value */
+} TIM_TIMERCFG_Type;
+
+/** @brief Configuration structure in COUNTER mode */
+typedef struct {
+
+ uint8_t CounterOption; /**< Counter Option, should be:
+ - TIM_COUNTER_INCAP0: CAPn.0 input pin for TIMERn
+ - TIM_COUNTER_INCAP1: CAPn.1 input pin for TIMERn
+ */
+ uint8_t CountInputSelect;
+ uint8_t Reserved[2];
+} TIM_COUNTERCFG_Type;
+
+/** @brief Match channel configuration structure */
+typedef struct {
+ uint8_t MatchChannel; /**< Match channel, should be in range
+ from 0..3 */
+ uint8_t IntOnMatch; /**< Interrupt On match, should be:
+ - ENABLE: Enable this function.
+ - DISABLE: Disable this function.
+ */
+ uint8_t StopOnMatch; /**< Stop On match, should be:
+ - ENABLE: Enable this function.
+ - DISABLE: Disable this function.
+ */
+ uint8_t ResetOnMatch; /**< Reset On match, should be:
+ - ENABLE: Enable this function.
+ - DISABLE: Disable this function.
+ */
+
+ uint8_t ExtMatchOutputType; /**< External Match Output type, should be:
+ - TIM_EXTMATCH_NOTHING: Do nothing for external output pin if match
+ - TIM_EXTMATCH_LOW: Force external output pin to low if match
+ - TIM_EXTMATCH_HIGH: Force external output pin to high if match
+ - TIM_EXTMATCH_TOGGLE: Toggle external output pin if match.
+ */
+ uint8_t Reserved[3]; /** Reserved */
+ uint32_t MatchValue; /** Match value */
+} TIM_MATCHCFG_Type;
+
+/** @brief Capture Input configuration structure */
+typedef struct {
+ uint8_t CaptureChannel; /**< Capture channel, should be in range
+ from 0..1 */
+ uint8_t RisingEdge; /**< caption rising edge, should be:
+ - ENABLE: Enable rising edge.
+ - DISABLE: Disable this function.
+ */
+ uint8_t FallingEdge; /**< caption falling edge, should be:
+ - ENABLE: Enable falling edge.
+ - DISABLE: Disable this function.
+ */
+ uint8_t IntOnCaption; /**< Interrupt On caption, should be:
+ - ENABLE: Enable interrupt function.
+ - DISABLE: Disable this function.
+ */
+
+} TIM_CAPTURECFG_Type;
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup TIM_Public_Functions TIM Public Functions
+ * @{
+ */
+/* Init/DeInit TIM functions -----------*/
+void TIM_Init(LPC_TIM_TypeDef *TIMx, TIM_MODE_OPT TimerCounterMode, void *TIM_ConfigStruct);
+void TIM_DeInit(LPC_TIM_TypeDef *TIMx);
+
+/* TIM interrupt functions -------------*/
+void TIM_ClearIntPending(LPC_TIM_TypeDef *TIMx, TIM_INT_TYPE IntFlag);
+void TIM_ClearIntCapturePending(LPC_TIM_TypeDef *TIMx, TIM_INT_TYPE IntFlag);
+FlagStatus TIM_GetIntStatus(LPC_TIM_TypeDef *TIMx, TIM_INT_TYPE IntFlag);
+FlagStatus TIM_GetIntCaptureStatus(LPC_TIM_TypeDef *TIMx, TIM_INT_TYPE IntFlag);
+
+/* TIM configuration functions --------*/
+void TIM_ConfigStructInit(TIM_MODE_OPT TimerCounterMode, void *TIM_ConfigStruct);
+void TIM_ConfigMatch(LPC_TIM_TypeDef *TIMx, TIM_MATCHCFG_Type *TIM_MatchConfigStruct);
+void TIM_UpdateMatchValue(LPC_TIM_TypeDef *TIMx,uint8_t MatchChannel, uint32_t MatchValue);
+void TIM_SetMatchExt(LPC_TIM_TypeDef *TIMx,TIM_EXTMATCH_OPT ext_match );
+void TIM_ConfigCapture(LPC_TIM_TypeDef *TIMx, TIM_CAPTURECFG_Type *TIM_CaptureConfigStruct);
+void TIM_Cmd(LPC_TIM_TypeDef *TIMx, FunctionalState NewState);
+
+uint32_t TIM_GetCaptureValue(LPC_TIM_TypeDef *TIMx, TIM_COUNTER_INPUT_OPT CaptureChannel);
+void TIM_ResetCounter(LPC_TIM_TypeDef *TIMx);
+
+/**
+ * @}
+ */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LPC17XX_TIMER_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/src/shared/cmsis/Drivers/include/lpc17xx_uart.h b/src/shared/cmsis/Drivers/include/lpc17xx_uart.h
@@ -0,0 +1,656 @@
+/**********************************************************************
+* $Id$ lpc17xx_uart.h 2010-06-18
+*//**
+* @file lpc17xx_uart.h
+* @brief Contains all macro definitions and function prototypes
+* support for UART firmware library on LPC17xx
+* @version 3.0
+* @date 18. June. 2010
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2010, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup UART UART (Universal Asynchronous Receiver/Transmitter)
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef __LPC17XX_UART_H
+#define __LPC17XX_UART_H
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup UART_Public_Macros UART Public Macros
+ * @{
+ */
+
+/** UART time-out definitions in case of using Read() and Write function
+ * with Blocking Flag mode
+ */
+#define UART_BLOCKING_TIMEOUT (0xFFFFFFFFUL)
+
+/**
+ * @}
+ */
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup UART_Private_Macros UART Private Macros
+ * @{
+ */
+
+/* Accepted Error baud rate value (in percent unit) */
+#define UART_ACCEPTED_BAUDRATE_ERROR (3) /*!< Acceptable UART baudrate error */
+
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/*********************************************************************//**
+ * Macro defines for Macro defines for UARTn Receiver Buffer Register
+ **********************************************************************/
+#define UART_RBR_MASKBIT ((uint8_t)0xFF) /*!< UART Received Buffer mask bit (8 bits) */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UARTn Transmit Holding Register
+ **********************************************************************/
+#define UART_THR_MASKBIT ((uint8_t)0xFF) /*!< UART Transmit Holding mask bit (8 bits) */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UARTn Divisor Latch LSB register
+ **********************************************************************/
+#define UART_LOAD_DLL(div) ((div) & 0xFF) /**< Macro for loading least significant halfs of divisors */
+#define UART_DLL_MASKBIT ((uint8_t)0xFF) /*!< Divisor latch LSB bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UARTn Divisor Latch MSB register
+ **********************************************************************/
+#define UART_DLM_MASKBIT ((uint8_t)0xFF) /*!< Divisor latch MSB bit mask */
+#define UART_LOAD_DLM(div) (((div) >> 8) & 0xFF) /**< Macro for loading most significant halfs of divisors */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART interrupt enable register
+ **********************************************************************/
+#define UART_IER_RBRINT_EN ((uint32_t)(1<<0)) /*!< RBR Interrupt enable*/
+#define UART_IER_THREINT_EN ((uint32_t)(1<<1)) /*!< THR Interrupt enable*/
+#define UART_IER_RLSINT_EN ((uint32_t)(1<<2)) /*!< RX line status interrupt enable*/
+#define UART1_IER_MSINT_EN ((uint32_t)(1<<3)) /*!< Modem status interrupt enable */
+#define UART1_IER_CTSINT_EN ((uint32_t)(1<<7)) /*!< CTS1 signal transition interrupt enable */
+#define UART_IER_ABEOINT_EN ((uint32_t)(1<<8)) /*!< Enables the end of auto-baud interrupt */
+#define UART_IER_ABTOINT_EN ((uint32_t)(1<<9)) /*!< Enables the auto-baud time-out interrupt */
+#define UART_IER_BITMASK ((uint32_t)(0x307)) /*!< UART interrupt enable register bit mask */
+#define UART1_IER_BITMASK ((uint32_t)(0x38F)) /*!< UART1 interrupt enable register bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART interrupt identification register
+ **********************************************************************/
+#define UART_IIR_INTSTAT_PEND ((uint32_t)(1<<0)) /*!<Interrupt Status - Active low */
+#define UART_IIR_INTID_RLS ((uint32_t)(3<<1)) /*!<Interrupt identification: Receive line status*/
+#define UART_IIR_INTID_RDA ((uint32_t)(2<<1)) /*!<Interrupt identification: Receive data available*/
+#define UART_IIR_INTID_CTI ((uint32_t)(6<<1)) /*!<Interrupt identification: Character time-out indicator*/
+#define UART_IIR_INTID_THRE ((uint32_t)(1<<1)) /*!<Interrupt identification: THRE interrupt*/
+#define UART1_IIR_INTID_MODEM ((uint32_t)(0<<1)) /*!<Interrupt identification: Modem interrupt*/
+#define UART_IIR_INTID_MASK ((uint32_t)(7<<1)) /*!<Interrupt identification: Interrupt ID mask */
+#define UART_IIR_FIFO_EN ((uint32_t)(3<<6)) /*!<These bits are equivalent to UnFCR[0] */
+#define UART_IIR_ABEO_INT ((uint32_t)(1<<8)) /*!< End of auto-baud interrupt */
+#define UART_IIR_ABTO_INT ((uint32_t)(1<<9)) /*!< Auto-baud time-out interrupt */
+#define UART_IIR_BITMASK ((uint32_t)(0x3CF)) /*!< UART interrupt identification register bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART FIFO control register
+ **********************************************************************/
+#define UART_FCR_FIFO_EN ((uint8_t)(1<<0)) /*!< UART FIFO enable */
+#define UART_FCR_RX_RS ((uint8_t)(1<<1)) /*!< UART FIFO RX reset */
+#define UART_FCR_TX_RS ((uint8_t)(1<<2)) /*!< UART FIFO TX reset */
+#define UART_FCR_DMAMODE_SEL ((uint8_t)(1<<3)) /*!< UART DMA mode selection */
+#define UART_FCR_TRG_LEV0 ((uint8_t)(0)) /*!< UART FIFO trigger level 0: 1 character */
+#define UART_FCR_TRG_LEV1 ((uint8_t)(1<<6)) /*!< UART FIFO trigger level 1: 4 character */
+#define UART_FCR_TRG_LEV2 ((uint8_t)(2<<6)) /*!< UART FIFO trigger level 2: 8 character */
+#define UART_FCR_TRG_LEV3 ((uint8_t)(3<<6)) /*!< UART FIFO trigger level 3: 14 character */
+#define UART_FCR_BITMASK ((uint8_t)(0xCF)) /*!< UART FIFO control bit mask */
+#define UART_TX_FIFO_SIZE (16)
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART line control register
+ **********************************************************************/
+#define UART_LCR_WLEN5 ((uint8_t)(0)) /*!< UART 5 bit data mode */
+#define UART_LCR_WLEN6 ((uint8_t)(1<<0)) /*!< UART 6 bit data mode */
+#define UART_LCR_WLEN7 ((uint8_t)(2<<0)) /*!< UART 7 bit data mode */
+#define UART_LCR_WLEN8 ((uint8_t)(3<<0)) /*!< UART 8 bit data mode */
+#define UART_LCR_STOPBIT_SEL ((uint8_t)(1<<2)) /*!< UART Two Stop Bits Select */
+#define UART_LCR_PARITY_EN ((uint8_t)(1<<3)) /*!< UART Parity Enable */
+#define UART_LCR_PARITY_ODD ((uint8_t)(0)) /*!< UART Odd Parity Select */
+#define UART_LCR_PARITY_EVEN ((uint8_t)(1<<4)) /*!< UART Even Parity Select */
+#define UART_LCR_PARITY_F_1 ((uint8_t)(2<<4)) /*!< UART force 1 stick parity */
+#define UART_LCR_PARITY_F_0 ((uint8_t)(3<<4)) /*!< UART force 0 stick parity */
+#define UART_LCR_BREAK_EN ((uint8_t)(1<<6)) /*!< UART Transmission Break enable */
+#define UART_LCR_DLAB_EN ((uint8_t)(1<<7)) /*!< UART Divisor Latches Access bit enable */
+#define UART_LCR_BITMASK ((uint8_t)(0xFF)) /*!< UART line control bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART1 Modem Control Register
+ **********************************************************************/
+#define UART1_MCR_DTR_CTRL ((uint8_t)(1<<0)) /*!< Source for modem output pin DTR */
+#define UART1_MCR_RTS_CTRL ((uint8_t)(1<<1)) /*!< Source for modem output pin RTS */
+#define UART1_MCR_LOOPB_EN ((uint8_t)(1<<4)) /*!< Loop back mode select */
+#define UART1_MCR_AUTO_RTS_EN ((uint8_t)(1<<6)) /*!< Enable Auto RTS flow-control */
+#define UART1_MCR_AUTO_CTS_EN ((uint8_t)(1<<7)) /*!< Enable Auto CTS flow-control */
+#define UART1_MCR_BITMASK ((uint8_t)(0x0F3)) /*!< UART1 bit mask value */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART line status register
+ **********************************************************************/
+#define UART_LSR_RDR ((uint8_t)(1<<0)) /*!<Line status register: Receive data ready*/
+#define UART_LSR_OE ((uint8_t)(1<<1)) /*!<Line status register: Overrun error*/
+#define UART_LSR_PE ((uint8_t)(1<<2)) /*!<Line status register: Parity error*/
+#define UART_LSR_FE ((uint8_t)(1<<3)) /*!<Line status register: Framing error*/
+#define UART_LSR_BI ((uint8_t)(1<<4)) /*!<Line status register: Break interrupt*/
+#define UART_LSR_THRE ((uint8_t)(1<<5)) /*!<Line status register: Transmit holding register empty*/
+#define UART_LSR_TEMT ((uint8_t)(1<<6)) /*!<Line status register: Transmitter empty*/
+#define UART_LSR_RXFE ((uint8_t)(1<<7)) /*!<Error in RX FIFO*/
+#define UART_LSR_BITMASK ((uint8_t)(0xFF)) /*!<UART Line status bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART Modem (UART1 only) status register
+ **********************************************************************/
+#define UART1_MSR_DELTA_CTS ((uint8_t)(1<<0)) /*!< Set upon state change of input CTS */
+#define UART1_MSR_DELTA_DSR ((uint8_t)(1<<1)) /*!< Set upon state change of input DSR */
+#define UART1_MSR_LO2HI_RI ((uint8_t)(1<<2)) /*!< Set upon low to high transition of input RI */
+#define UART1_MSR_DELTA_DCD ((uint8_t)(1<<3)) /*!< Set upon state change of input DCD */
+#define UART1_MSR_CTS ((uint8_t)(1<<4)) /*!< Clear To Send State */
+#define UART1_MSR_DSR ((uint8_t)(1<<5)) /*!< Data Set Ready State */
+#define UART1_MSR_RI ((uint8_t)(1<<6)) /*!< Ring Indicator State */
+#define UART1_MSR_DCD ((uint8_t)(1<<7)) /*!< Data Carrier Detect State */
+#define UART1_MSR_BITMASK ((uint8_t)(0xFF)) /*!< MSR register bit-mask value */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART Scratch Pad Register
+ **********************************************************************/
+#define UART_SCR_BIMASK ((uint8_t)(0xFF)) /*!< UART Scratch Pad bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART Auto baudrate control register
+ **********************************************************************/
+#define UART_ACR_START ((uint32_t)(1<<0)) /**< UART Auto-baud start */
+#define UART_ACR_MODE ((uint32_t)(1<<1)) /**< UART Auto baudrate Mode 1 */
+#define UART_ACR_AUTO_RESTART ((uint32_t)(1<<2)) /**< UART Auto baudrate restart */
+#define UART_ACR_ABEOINT_CLR ((uint32_t)(1<<8)) /**< UART End of auto-baud interrupt clear */
+#define UART_ACR_ABTOINT_CLR ((uint32_t)(1<<9)) /**< UART Auto-baud time-out interrupt clear */
+#define UART_ACR_BITMASK ((uint32_t)(0x307)) /**< UART Auto Baudrate register bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART IrDA control register
+ **********************************************************************/
+#define UART_ICR_IRDAEN ((uint32_t)(1<<0)) /**< IrDA mode enable */
+#define UART_ICR_IRDAINV ((uint32_t)(1<<1)) /**< IrDA serial input inverted */
+#define UART_ICR_FIXPULSE_EN ((uint32_t)(1<<2)) /**< IrDA fixed pulse width mode */
+#define UART_ICR_PULSEDIV(n) ((uint32_t)((n&0x07)<<3)) /**< PulseDiv - Configures the pulse when FixPulseEn = 1 */
+#define UART_ICR_BITMASK ((uint32_t)(0x3F)) /*!< UART IRDA bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART Fractional divider register
+ **********************************************************************/
+#define UART_FDR_DIVADDVAL(n) ((uint32_t)(n&0x0F)) /**< Baud-rate generation pre-scaler divisor */
+#define UART_FDR_MULVAL(n) ((uint32_t)((n<<4)&0xF0)) /**< Baud-rate pre-scaler multiplier value */
+#define UART_FDR_BITMASK ((uint32_t)(0xFF)) /**< UART Fractional Divider register bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART Tx Enable register
+ **********************************************************************/
+#define UART_TER_TXEN ((uint8_t)(1<<7)) /*!< Transmit enable bit */
+#define UART_TER_BITMASK ((uint8_t)(0x80)) /**< UART Transmit Enable Register bit mask */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART1 RS485 Control register
+ **********************************************************************/
+#define UART1_RS485CTRL_NMM_EN ((uint32_t)(1<<0)) /*!< RS-485/EIA-485 Normal Multi-drop Mode (NMM)
+ is disabled */
+#define UART1_RS485CTRL_RX_DIS ((uint32_t)(1<<1)) /*!< The receiver is disabled */
+#define UART1_RS485CTRL_AADEN ((uint32_t)(1<<2)) /*!< Auto Address Detect (AAD) is enabled */
+#define UART1_RS485CTRL_SEL_DTR ((uint32_t)(1<<3)) /*!< If direction control is enabled
+ (bit DCTRL = 1), pin DTR is used for direction control */
+#define UART1_RS485CTRL_DCTRL_EN ((uint32_t)(1<<4)) /*!< Enable Auto Direction Control */
+#define UART1_RS485CTRL_OINV_1 ((uint32_t)(1<<5)) /*!< This bit reverses the polarity of the direction
+ control signal on the RTS (or DTR) pin. The direction control pin
+ will be driven to logic "1" when the transmitter has data to be sent */
+#define UART1_RS485CTRL_BITMASK ((uint32_t)(0x3F)) /**< RS485 control bit-mask value */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART1 RS-485 Address Match register
+ **********************************************************************/
+#define UART1_RS485ADRMATCH_BITMASK ((uint8_t)(0xFF)) /**< Bit mask value */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART1 RS-485 Delay value register
+ **********************************************************************/
+/* Macro defines for UART1 RS-485 Delay value register */
+#define UART1_RS485DLY_BITMASK ((uint8_t)(0xFF)) /** Bit mask value */
+
+/*********************************************************************//**
+ * Macro defines for Macro defines for UART FIFO Level register
+ **********************************************************************/
+#define UART_FIFOLVL_RXFIFOLVL(n) ((uint32_t)(n&0x0F)) /**< Reflects the current level of the UART receiver FIFO */
+#define UART_FIFOLVL_TXFIFOLVL(n) ((uint32_t)((n>>8)&0x0F)) /**< Reflects the current level of the UART transmitter FIFO */
+#define UART_FIFOLVL_BITMASK ((uint32_t)(0x0F0F)) /**< UART FIFO Level Register bit mask */
+
+
+/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
+
+/** Macro to check the input UART_DATABIT parameters */
+#define PARAM_UART_DATABIT(databit) ((databit==UART_DATABIT_5) || (databit==UART_DATABIT_6)\
+|| (databit==UART_DATABIT_7) || (databit==UART_DATABIT_8))
+
+/** Macro to check the input UART_STOPBIT parameters */
+#define PARAM_UART_STOPBIT(stopbit) ((stopbit==UART_STOPBIT_1) || (stopbit==UART_STOPBIT_2))
+
+/** Macro to check the input UART_PARITY parameters */
+#define PARAM_UART_PARITY(parity) ((parity==UART_PARITY_NONE) || (parity==UART_PARITY_ODD) \
+|| (parity==UART_PARITY_EVEN) || (parity==UART_PARITY_SP_1) \
+|| (parity==UART_PARITY_SP_0))
+
+/** Macro to check the input UART_FIFO parameters */
+#define PARAM_UART_FIFO_LEVEL(fifo) ((fifo==UART_FIFO_TRGLEV0) \
+|| (fifo==UART_FIFO_TRGLEV1) || (fifo==UART_FIFO_TRGLEV2) \
+|| (fifo==UART_FIFO_TRGLEV3))
+
+/** Macro to check the input UART_INTCFG parameters */
+#define PARAM_UART_INTCFG(IntCfg) ((IntCfg==UART_INTCFG_RBR) || (IntCfg==UART_INTCFG_THRE) \
+|| (IntCfg==UART_INTCFG_RLS) || (IntCfg==UART_INTCFG_ABEO) \
+|| (IntCfg==UART_INTCFG_ABTO))
+
+/** Macro to check the input UART1_INTCFG parameters - expansion input parameter for UART1 */
+#define PARAM_UART1_INTCFG(IntCfg) ((IntCfg==UART1_INTCFG_MS) || (IntCfg==UART1_INTCFG_CTS))
+
+/** Macro to check the input UART_AUTOBAUD_MODE parameters */
+#define PARAM_UART_AUTOBAUD_MODE(ABmode) ((ABmode==UART_AUTOBAUD_MODE0) || (ABmode==UART_AUTOBAUD_MODE1))
+
+/** Macro to check the input UART_AUTOBAUD_INTSTAT parameters */
+#define PARAM_UART_AUTOBAUD_INTSTAT(ABIntStat) ((ABIntStat==UART_AUTOBAUD_INTSTAT_ABEO) || \
+ (ABIntStat==UART_AUTOBAUD_INTSTAT_ABTO))
+
+/** Macro to check the input UART_IrDA_PULSEDIV parameters */
+#define PARAM_UART_IrDA_PULSEDIV(PulseDiv) ((PulseDiv==UART_IrDA_PULSEDIV2) || (PulseDiv==UART_IrDA_PULSEDIV4) \
+|| (PulseDiv==UART_IrDA_PULSEDIV8) || (PulseDiv==UART_IrDA_PULSEDIV16) \
+|| (PulseDiv==UART_IrDA_PULSEDIV32) || (PulseDiv==UART_IrDA_PULSEDIV64) \
+|| (PulseDiv==UART_IrDA_PULSEDIV128) || (PulseDiv==UART_IrDA_PULSEDIV256))
+
+/* Macro to check the input UART1_SignalState parameters */
+#define PARAM_UART1_SIGNALSTATE(x) ((x==INACTIVE) || (x==ACTIVE))
+
+/** Macro to check the input PARAM_UART1_MODEM_PIN parameters */
+#define PARAM_UART1_MODEM_PIN(x) ((x==UART1_MODEM_PIN_DTR) || (x==UART1_MODEM_PIN_RTS))
+
+/** Macro to check the input PARAM_UART1_MODEM_MODE parameters */
+#define PARAM_UART1_MODEM_MODE(x) ((x==UART1_MODEM_MODE_LOOPBACK) || (x==UART1_MODEM_MODE_AUTO_RTS) \
+|| (x==UART1_MODEM_MODE_AUTO_CTS))
+
+/** Macro to check the direction control pin type */
+#define PARAM_UART_RS485_DIRCTRL_PIN(x) ((x==UART1_RS485_DIRCTRL_RTS) || (x==UART1_RS485_DIRCTRL_DTR))
+
+/* Macro to determine if it is valid UART port number */
+#define PARAM_UARTx(x) ((((uint32_t *)x)==((uint32_t *)LPC_UART0)) \
+|| (((uint32_t *)x)==((uint32_t *)LPC_UART1)) \
+|| (((uint32_t *)x)==((uint32_t *)LPC_UART2)) \
+|| (((uint32_t *)x)==((uint32_t *)LPC_UART3)))
+#define PARAM_UART_IrDA(x) (((uint32_t *)x)==((uint32_t *)LPC_UART3))
+#define PARAM_UART1_MODEM(x) (((uint32_t *)x)==((uint32_t *)LPC_UART1))
+
+/** Macro to check the input value for UART1_RS485_CFG_MATCHADDRVALUE parameter */
+#define PARAM_UART1_RS485_CFG_MATCHADDRVALUE(x) ((x<0xFF))
+
+/** Macro to check the input value for UART1_RS485_CFG_DELAYVALUE parameter */
+#define PARAM_UART1_RS485_CFG_DELAYVALUE(x) ((x<0xFF))
+
+/**
+ * @}
+ */
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup UART_Public_Types UART Public Types
+ * @{
+ */
+
+/**
+ * @brief UART Databit type definitions
+ */
+typedef enum {
+ UART_DATABIT_5 = 0, /*!< UART 5 bit data mode */
+ UART_DATABIT_6, /*!< UART 6 bit data mode */
+ UART_DATABIT_7, /*!< UART 7 bit data mode */
+ UART_DATABIT_8 /*!< UART 8 bit data mode */
+} UART_DATABIT_Type;
+
+/**
+ * @brief UART Stop bit type definitions
+ */
+typedef enum {
+ UART_STOPBIT_1 = (0), /*!< UART 1 Stop Bits Select */
+ UART_STOPBIT_2 /*!< UART Two Stop Bits Select */
+} UART_STOPBIT_Type;
+
+/**
+ * @brief UART Parity type definitions
+ */
+typedef enum {
+ UART_PARITY_NONE = 0, /*!< No parity */
+ UART_PARITY_ODD, /*!< Odd parity */
+ UART_PARITY_EVEN, /*!< Even parity */
+ UART_PARITY_SP_1, /*!< Forced "1" stick parity */
+ UART_PARITY_SP_0 /*!< Forced "0" stick parity */
+} UART_PARITY_Type;
+
+/**
+ * @brief FIFO Level type definitions
+ */
+typedef enum {
+ UART_FIFO_TRGLEV0 = 0, /*!< UART FIFO trigger level 0: 1 character */
+ UART_FIFO_TRGLEV1, /*!< UART FIFO trigger level 1: 4 character */
+ UART_FIFO_TRGLEV2, /*!< UART FIFO trigger level 2: 8 character */
+ UART_FIFO_TRGLEV3 /*!< UART FIFO trigger level 3: 14 character */
+} UART_FITO_LEVEL_Type;
+
+/********************************************************************//**
+* @brief UART Interrupt Type definitions
+**********************************************************************/
+typedef enum {
+ UART_INTCFG_RBR = 0, /*!< RBR Interrupt enable*/
+ UART_INTCFG_THRE, /*!< THR Interrupt enable*/
+ UART_INTCFG_RLS, /*!< RX line status interrupt enable*/
+ UART1_INTCFG_MS, /*!< Modem status interrupt enable (UART1 only) */
+ UART1_INTCFG_CTS, /*!< CTS1 signal transition interrupt enable (UART1 only) */
+ UART_INTCFG_ABEO, /*!< Enables the end of auto-baud interrupt */
+ UART_INTCFG_ABTO /*!< Enables the auto-baud time-out interrupt */
+} UART_INT_Type;
+
+/**
+ * @brief UART Line Status Type definition
+ */
+typedef enum {
+ UART_LINESTAT_RDR = UART_LSR_RDR, /*!<Line status register: Receive data ready*/
+ UART_LINESTAT_OE = UART_LSR_OE, /*!<Line status register: Overrun error*/
+ UART_LINESTAT_PE = UART_LSR_PE, /*!<Line status register: Parity error*/
+ UART_LINESTAT_FE = UART_LSR_FE, /*!<Line status register: Framing error*/
+ UART_LINESTAT_BI = UART_LSR_BI, /*!<Line status register: Break interrupt*/
+ UART_LINESTAT_THRE = UART_LSR_THRE, /*!<Line status register: Transmit holding register empty*/
+ UART_LINESTAT_TEMT = UART_LSR_TEMT, /*!<Line status register: Transmitter empty*/
+ UART_LINESTAT_RXFE = UART_LSR_RXFE /*!<Error in RX FIFO*/
+} UART_LS_Type;
+
+/**
+ * @brief UART Auto-baudrate mode type definition
+ */
+typedef enum {
+ UART_AUTOBAUD_MODE0 = 0, /**< UART Auto baudrate Mode 0 */
+ UART_AUTOBAUD_MODE1 /**< UART Auto baudrate Mode 1 */
+} UART_AB_MODE_Type;
+
+/**
+ * @brief Auto Baudrate mode configuration type definition
+ */
+typedef struct {
+ UART_AB_MODE_Type ABMode; /**< Autobaudrate mode */
+ FunctionalState AutoRestart; /**< Auto Restart state */
+} UART_AB_CFG_Type;
+
+/**
+ * @brief UART End of Auto-baudrate type definition
+ */
+typedef enum {
+ UART_AUTOBAUD_INTSTAT_ABEO = UART_IIR_ABEO_INT, /**< UART End of auto-baud interrupt */
+ UART_AUTOBAUD_INTSTAT_ABTO = UART_IIR_ABTO_INT /**< UART Auto-baud time-out interrupt */
+}UART_ABEO_Type;
+
+/**
+ * UART IrDA Control type Definition
+ */
+typedef enum {
+ UART_IrDA_PULSEDIV2 = 0, /**< Pulse width = 2 * Tpclk
+ - Configures the pulse when FixPulseEn = 1 */
+ UART_IrDA_PULSEDIV4, /**< Pulse width = 4 * Tpclk
+ - Configures the pulse when FixPulseEn = 1 */
+ UART_IrDA_PULSEDIV8, /**< Pulse width = 8 * Tpclk
+ - Configures the pulse when FixPulseEn = 1 */
+ UART_IrDA_PULSEDIV16, /**< Pulse width = 16 * Tpclk
+ - Configures the pulse when FixPulseEn = 1 */
+ UART_IrDA_PULSEDIV32, /**< Pulse width = 32 * Tpclk
+ - Configures the pulse when FixPulseEn = 1 */
+ UART_IrDA_PULSEDIV64, /**< Pulse width = 64 * Tpclk
+ - Configures the pulse when FixPulseEn = 1 */
+ UART_IrDA_PULSEDIV128, /**< Pulse width = 128 * Tpclk
+ - Configures the pulse when FixPulseEn = 1 */
+ UART_IrDA_PULSEDIV256 /**< Pulse width = 256 * Tpclk
+ - Configures the pulse when FixPulseEn = 1 */
+} UART_IrDA_PULSE_Type;
+
+/********************************************************************//**
+* @brief UART1 Full modem - Signal states definition
+**********************************************************************/
+typedef enum {
+ INACTIVE = 0, /* In-active state */
+ ACTIVE = !INACTIVE /* Active state */
+}UART1_SignalState;
+
+/**
+ * @brief UART modem status type definition
+ */
+typedef enum {
+ UART1_MODEM_STAT_DELTA_CTS = UART1_MSR_DELTA_CTS, /*!< Set upon state change of input CTS */
+ UART1_MODEM_STAT_DELTA_DSR = UART1_MSR_DELTA_DSR, /*!< Set upon state change of input DSR */
+ UART1_MODEM_STAT_LO2HI_RI = UART1_MSR_LO2HI_RI, /*!< Set upon low to high transition of input RI */
+ UART1_MODEM_STAT_DELTA_DCD = UART1_MSR_DELTA_DCD, /*!< Set upon state change of input DCD */
+ UART1_MODEM_STAT_CTS = UART1_MSR_CTS, /*!< Clear To Send State */
+ UART1_MODEM_STAT_DSR = UART1_MSR_DSR, /*!< Data Set Ready State */
+ UART1_MODEM_STAT_RI = UART1_MSR_RI, /*!< Ring Indicator State */
+ UART1_MODEM_STAT_DCD = UART1_MSR_DCD /*!< Data Carrier Detect State */
+} UART_MODEM_STAT_type;
+
+/**
+ * @brief Modem output pin type definition
+ */
+typedef enum {
+ UART1_MODEM_PIN_DTR = 0, /*!< Source for modem output pin DTR */
+ UART1_MODEM_PIN_RTS /*!< Source for modem output pin RTS */
+} UART_MODEM_PIN_Type;
+
+/**
+ * @brief UART Modem mode type definition
+ */
+typedef enum {
+ UART1_MODEM_MODE_LOOPBACK = 0, /*!< Loop back mode select */
+ UART1_MODEM_MODE_AUTO_RTS, /*!< Enable Auto RTS flow-control */
+ UART1_MODEM_MODE_AUTO_CTS /*!< Enable Auto CTS flow-control */
+} UART_MODEM_MODE_Type;
+
+/**
+ * @brief UART Direction Control Pin type definition
+ */
+typedef enum {
+ UART1_RS485_DIRCTRL_RTS = 0, /**< Pin RTS is used for direction control */
+ UART1_RS485_DIRCTRL_DTR /**< Pin DTR is used for direction control */
+} UART_RS485_DIRCTRL_PIN_Type;
+
+/********************************************************************//**
+* @brief UART Configuration Structure definition
+**********************************************************************/
+typedef struct {
+ uint32_t Baud_rate; /**< UART baud rate */
+ UART_PARITY_Type Parity; /**< Parity selection, should be:
+ - UART_PARITY_NONE: No parity
+ - UART_PARITY_ODD: Odd parity
+ - UART_PARITY_EVEN: Even parity
+ - UART_PARITY_SP_1: Forced "1" stick parity
+ - UART_PARITY_SP_0: Forced "0" stick parity
+ */
+ UART_DATABIT_Type Databits; /**< Number of data bits, should be:
+ - UART_DATABIT_5: UART 5 bit data mode
+ - UART_DATABIT_6: UART 6 bit data mode
+ - UART_DATABIT_7: UART 7 bit data mode
+ - UART_DATABIT_8: UART 8 bit data mode
+ */
+ UART_STOPBIT_Type Stopbits; /**< Number of stop bits, should be:
+ - UART_STOPBIT_1: UART 1 Stop Bits Select
+ - UART_STOPBIT_2: UART 2 Stop Bits Select
+ */
+} UART_CFG_Type;
+
+/********************************************************************//**
+* @brief UART FIFO Configuration Structure definition
+**********************************************************************/
+
+typedef struct {
+ FunctionalState FIFO_ResetRxBuf; /**< Reset Rx FIFO command state , should be:
+ - ENABLE: Reset Rx FIFO in UART
+ - DISABLE: Do not reset Rx FIFO in UART
+ */
+ FunctionalState FIFO_ResetTxBuf; /**< Reset Tx FIFO command state , should be:
+ - ENABLE: Reset Tx FIFO in UART
+ - DISABLE: Do not reset Tx FIFO in UART
+ */
+ FunctionalState FIFO_DMAMode; /**< DMA mode, should be:
+ - ENABLE: Enable DMA mode in UART
+ - DISABLE: Disable DMA mode in UART
+ */
+ UART_FITO_LEVEL_Type FIFO_Level; /**< Rx FIFO trigger level, should be:
+ - UART_FIFO_TRGLEV0: UART FIFO trigger level 0: 1 character
+ - UART_FIFO_TRGLEV1: UART FIFO trigger level 1: 4 character
+ - UART_FIFO_TRGLEV2: UART FIFO trigger level 2: 8 character
+ - UART_FIFO_TRGLEV3: UART FIFO trigger level 3: 14 character
+ */
+} UART_FIFO_CFG_Type;
+
+/********************************************************************//**
+* @brief UART1 Full modem - RS485 Control configuration type
+**********************************************************************/
+typedef struct {
+ FunctionalState NormalMultiDropMode_State; /*!< Normal MultiDrop mode State:
+ - ENABLE: Enable this function.
+ - DISABLE: Disable this function. */
+ FunctionalState Rx_State; /*!< Receiver State:
+ - ENABLE: Enable Receiver.
+ - DISABLE: Disable Receiver. */
+ FunctionalState AutoAddrDetect_State; /*!< Auto Address Detect mode state:
+ - ENABLE: ENABLE this function.
+ - DISABLE: Disable this function. */
+ FunctionalState AutoDirCtrl_State; /*!< Auto Direction Control State:
+ - ENABLE: Enable this function.
+ - DISABLE: Disable this function. */
+ UART_RS485_DIRCTRL_PIN_Type DirCtrlPin; /*!< If direction control is enabled, state:
+ - UART1_RS485_DIRCTRL_RTS:
+ pin RTS is used for direction control.
+ - UART1_RS485_DIRCTRL_DTR:
+ pin DTR is used for direction control. */
+ SetState DirCtrlPol_Level; /*!< Polarity of the direction control signal on
+ the RTS (or DTR) pin:
+ - RESET: The direction control pin will be driven
+ to logic "0" when the transmitter has data to be sent.
+ - SET: The direction control pin will be driven
+ to logic "1" when the transmitter has data to be sent. */
+ uint8_t MatchAddrValue; /*!< address match value for RS-485/EIA-485 mode, 8-bit long */
+ uint8_t DelayValue; /*!< delay time is in periods of the baud clock, 8-bit long */
+} UART1_RS485_CTRLCFG_Type;
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup UART_Public_Functions UART Public Functions
+ * @{
+ */
+/* UART Init/DeInit functions --------------------------------------------------*/
+void UART_Init(LPC_UART_TypeDef *UARTx, UART_CFG_Type *UART_ConfigStruct);
+void UART_DeInit(LPC_UART_TypeDef* UARTx);
+void UART_ConfigStructInit(UART_CFG_Type *UART_InitStruct);
+
+/* UART Send/Receive functions -------------------------------------------------*/
+void UART_SendByte(LPC_UART_TypeDef* UARTx, uint8_t Data);
+uint8_t UART_ReceiveByte(LPC_UART_TypeDef* UARTx);
+uint32_t UART_Send(LPC_UART_TypeDef *UARTx, uint8_t *txbuf,
+ uint32_t buflen, TRANSFER_BLOCK_Type flag);
+uint32_t UART_Receive(LPC_UART_TypeDef *UARTx, uint8_t *rxbuf, \
+ uint32_t buflen, TRANSFER_BLOCK_Type flag);
+
+/* UART FIFO functions ----------------------------------------------------------*/
+void UART_FIFOConfig(LPC_UART_TypeDef *UARTx, UART_FIFO_CFG_Type *FIFOCfg);
+void UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct);
+
+/* UART get information functions -----------------------------------------------*/
+uint32_t UART_GetIntId(LPC_UART_TypeDef* UARTx);
+uint8_t UART_GetLineStatus(LPC_UART_TypeDef* UARTx);
+
+/* UART operate functions -------------------------------------------------------*/
+void UART_IntConfig(LPC_UART_TypeDef *UARTx, UART_INT_Type UARTIntCfg, \
+ FunctionalState NewState);
+void UART_TxCmd(LPC_UART_TypeDef *UARTx, FunctionalState NewState);
+FlagStatus UART_CheckBusy(LPC_UART_TypeDef *UARTx);
+void UART_ForceBreak(LPC_UART_TypeDef* UARTx);
+
+/* UART Auto-baud functions -----------------------------------------------------*/
+void UART_ABClearIntPending(LPC_UART_TypeDef *UARTx, UART_ABEO_Type ABIntType);
+void UART_ABCmd(LPC_UART_TypeDef *UARTx, UART_AB_CFG_Type *ABConfigStruct, \
+ FunctionalState NewState);
+
+/* UART1 FullModem functions ----------------------------------------------------*/
+void UART_FullModemForcePinState(LPC_UART1_TypeDef *UARTx, UART_MODEM_PIN_Type Pin, \
+ UART1_SignalState NewState);
+void UART_FullModemConfigMode(LPC_UART1_TypeDef *UARTx, UART_MODEM_MODE_Type Mode, \
+ FunctionalState NewState);
+uint8_t UART_FullModemGetStatus(LPC_UART1_TypeDef *UARTx);
+
+/* UART RS485 functions ----------------------------------------------------------*/
+void UART_RS485Config(LPC_UART1_TypeDef *UARTx, \
+ UART1_RS485_CTRLCFG_Type *RS485ConfigStruct);
+void UART_RS485ReceiverCmd(LPC_UART1_TypeDef *UARTx, FunctionalState NewState);
+void UART_RS485SendSlvAddr(LPC_UART1_TypeDef *UARTx, uint8_t SlvAddr);
+uint32_t UART_RS485SendData(LPC_UART1_TypeDef *UARTx, uint8_t *pData, uint32_t size);
+
+/* UART IrDA functions-------------------------------------------------------------*/
+void UART_IrDAInvtInputCmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState);
+void UART_IrDACmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState);
+void UART_IrDAPulseDivConfig(LPC_UART_TypeDef *UARTx, UART_IrDA_PULSE_Type PulseDiv);
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __LPC17XX_UART_H */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/src/shared/cmsis/Drivers/include/lpc17xx_wdt.h b/src/shared/cmsis/Drivers/include/lpc17xx_wdt.h
@@ -0,0 +1,154 @@
+/**********************************************************************
+* $Id$ lpc17xx_wdt.h 2010-05-21
+*//**
+* @file lpc17xx_wdt.h
+* @brief Contains all macro definitions and function prototypes
+* support for WDT firmware library on LPC17xx
+* @version 2.0
+* @date 21. May. 2010
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2010, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @defgroup WDT WDT (Watch-Dog Timer)
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC17XX_WDT_H_
+#define LPC17XX_WDT_H_
+
+/* Includes ------------------------------------------------------------------- */
+#include "LPC17xx.h"
+#include "lpc_types.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/* Private Macros ------------------------------------------------------------- */
+/** @defgroup WDT_Private_Macros WDT Private Macros
+ * @{
+ */
+
+/* --------------------- BIT DEFINITIONS -------------------------------------- */
+/** WDT interrupt enable bit */
+#define WDT_WDMOD_WDEN ((uint32_t)(1<<0))
+/** WDT interrupt enable bit */
+#define WDT_WDMOD_WDRESET ((uint32_t)(1<<1))
+/** WDT time out flag bit */
+#define WDT_WDMOD_WDTOF ((uint32_t)(1<<2))
+/** WDT Time Out flag bit */
+#define WDT_WDMOD_WDINT ((uint32_t)(1<<3))
+/** WDT Mode */
+#define WDT_WDMOD(n) ((uint32_t)(1<<1))
+
+/** Define divider index for microsecond ( us ) */
+#define WDT_US_INDEX ((uint32_t)(1000000))
+/** WDT Time out minimum value */
+#define WDT_TIMEOUT_MIN ((uint32_t)(0xFF))
+/** WDT Time out maximum value */
+#define WDT_TIMEOUT_MAX ((uint32_t)(0xFFFFFFFF))
+
+/** Watchdog mode register mask */
+#define WDT_WDMOD_MASK (uint8_t)(0x02)
+/** Watchdog timer constant register mask */
+#define WDT_WDTC_MASK (uint8_t)(0xFFFFFFFF)
+/** Watchdog feed sequence register mask */
+#define WDT_WDFEED_MASK (uint8_t)(0x000000FF)
+/** Watchdog timer value register mask */
+#define WDT_WDCLKSEL_MASK (uint8_t)(0x03)
+/** Clock selected from internal RC */
+#define WDT_WDCLKSEL_RC (uint8_t)(0x00)
+/** Clock selected from PCLK */
+#define WDT_WDCLKSEL_PCLK (uint8_t)(0x01)
+/** Clock selected from external RTC */
+#define WDT_WDCLKSEL_RTC (uint8_t)(0x02)
+
+/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
+/* Macro check clock source selection */
+#define PARAM_WDT_CLK_OPT(OPTION) ((OPTION ==WDT_CLKSRC_IRC)||(OPTION ==WDT_CLKSRC_PCLK)\
+||(OPTION ==WDT_CLKSRC_RTC))
+
+/* Macro check WDT mode */
+#define PARAM_WDT_MODE_OPT(OPTION) ((OPTION ==WDT_MODE_INT_ONLY)||(OPTION ==WDT_MODE_RESET))
+/**
+ * @}
+ */
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup WDT_Public_Types WDT Public Types
+ * @{
+ */
+
+/** @brief Clock source option for WDT */
+typedef enum {
+ WDT_CLKSRC_IRC = 0, /*!< Clock source from Internal RC oscillator */
+ WDT_CLKSRC_PCLK = 1, /*!< Selects the APB peripheral clock (PCLK) */
+ WDT_CLKSRC_RTC = 2 /*!< Selects the RTC oscillator */
+} WDT_CLK_OPT;
+
+/** @brief WDT operation mode */
+typedef enum {
+ WDT_MODE_INT_ONLY = 0, /*!< Use WDT to generate interrupt only */
+ WDT_MODE_RESET = 1 /*!< Use WDT to generate interrupt and reset MCU */
+} WDT_MODE_OPT;
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @defgroup WDT_Public_Functions WDT Public Functions
+ * @{
+ */
+
+void WDT_Init (WDT_CLK_OPT ClkSrc, WDT_MODE_OPT WDTMode);
+void WDT_Start(uint32_t TimeOut);
+void WDT_Feed (void);
+void WDT_UpdateTimeOut ( uint32_t TimeOut);
+FlagStatus WDT_ReadTimeOutFlag (void);
+void WDT_ClrTimeOutFlag (void);
+uint32_t WDT_GetCurrentCount(void);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPC17XX_WDT_H_ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/src/shared/cmsis/Drivers/include/lpc_types.h b/src/shared/cmsis/Drivers/include/lpc_types.h
@@ -0,0 +1,212 @@
+/**********************************************************************
+* $Id$ lpc_types.h 2008-07-27
+*//**
+* @file lpc_types.h
+* @brief Contains the NXP ABL typedefs for C standard types.
+* It is intended to be used in ISO C conforming development
+* environments and checks for this insofar as it is possible
+* to do so.
+* @version 2.0
+* @date 27 July. 2008
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2008, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Type group ----------------------------------------------------------- */
+/** @defgroup LPC_Types LPC_Types
+ * @ingroup LPC1700CMSIS_FwLib_Drivers
+ * @{
+ */
+
+#ifndef LPC_TYPES_H
+#define LPC_TYPES_H
+
+/* Includes ------------------------------------------------------------------- */
+#include <stdint.h>
+
+
+/* Public Types --------------------------------------------------------------- */
+/** @defgroup LPC_Types_Public_Types LPC_Types Public Types
+ * @{
+ */
+
+/**
+ * @brief Boolean Type definition
+ */
+typedef enum {FALSE = 0, TRUE = !FALSE} Bool;
+
+/**
+ * @brief Flag Status and Interrupt Flag Status type definition
+ */
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState;
+#define PARAM_SETSTATE(State) ((State==RESET) || (State==SET))
+
+/**
+ * @brief Functional State Definition
+ */
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define PARAM_FUNCTIONALSTATE(State) ((State==DISABLE) || (State==ENABLE))
+
+/**
+ * @ Status type definition
+ */
+typedef enum {ERROR = 0, SUCCESS = !ERROR} Status;
+
+
+/**
+ * Read/Write transfer type mode (Block or non-block)
+ */
+typedef enum
+{
+ NONE_BLOCKING = 0, /**< None Blocking type */
+ BLOCKING /**< Blocking type */
+} TRANSFER_BLOCK_Type;
+
+
+/** Pointer to Function returning Void (any number of parameters) */
+// typedef void (*PFV)();
+
+/** Pointer to Function returning int32_t (any number of parameters) */
+// typedef int32_t(*PFI)();
+
+/**
+ * @}
+ */
+
+
+/* Public Macros -------------------------------------------------------------- */
+/** @defgroup LPC_Types_Public_Macros LPC_Types Public Macros
+ * @{
+ */
+
+/* _BIT(n) sets the bit at position "n"
+ * _BIT(n) is intended to be used in "OR" and "AND" expressions:
+ * e.g., "(_BIT(3) | _BIT(7))".
+ */
+#undef _BIT
+/* Set bit macro */
+#define _BIT(n) (1<<n)
+
+/* _SBF(f,v) sets the bit field starting at position "f" to value "v".
+ * _SBF(f,v) is intended to be used in "OR" and "AND" expressions:
+ * e.g., "((_SBF(5,7) | _SBF(12,0xF)) & 0xFFFF)"
+ */
+#undef _SBF
+/* Set bit field macro */
+#define _SBF(f,v) (v<<f)
+
+/* _BITMASK constructs a symbol with 'field_width' least significant
+ * bits set.
+ * e.g., _BITMASK(5) constructs '0x1F', _BITMASK(16) == 0xFFFF
+ * The symbol is intended to be used to limit the bit field width
+ * thusly:
+ * <a_register> = (any_expression) & _BITMASK(x), where 0 < x <= 32.
+ * If "any_expression" results in a value that is larger than can be
+ * contained in 'x' bits, the bits above 'x - 1' are masked off. When
+ * used with the _SBF example above, the example would be written:
+ * a_reg = ((_SBF(5,7) | _SBF(12,0xF)) & _BITMASK(16))
+ * This ensures that the value written to a_reg is no wider than
+ * 16 bits, and makes the code easier to read and understand.
+ */
+#undef _BITMASK
+/* Bitmask creation macro */
+#define _BITMASK(field_width) ( _BIT(field_width) - 1)
+
+/* NULL pointer */
+#ifndef NULL
+#define NULL ((void*) 0)
+#endif
+
+/* Number of elements in an array */
+#define NELEMENTS(array) (sizeof (array) / sizeof (array[0]))
+
+/* Static data/function define */
+#define STATIC static
+/* External data/function define */
+#define EXTERN extern
+
+#if !defined(MAX)
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#endif
+#if !defined(MIN)
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+/**
+ * @}
+ */
+
+
+/* Old Type Definition compatibility ------------------------------------------ */
+/** @addtogroup LPC_Types_Public_Types LPC_Types Public Types
+ * @{
+ */
+
+/** SMA type for character type */
+typedef char CHAR;
+
+/** SMA type for 8 bit unsigned value */
+typedef uint8_t UNS_8;
+
+/** SMA type for 8 bit signed value */
+typedef int8_t INT_8;
+
+/** SMA type for 16 bit unsigned value */
+typedef uint16_t UNS_16;
+
+/** SMA type for 16 bit signed value */
+typedef int16_t INT_16;
+
+/** SMA type for 32 bit unsigned value */
+typedef uint32_t UNS_32;
+
+/** SMA type for 32 bit signed value */
+typedef int32_t INT_32;
+
+/** SMA type for 64 bit signed value */
+typedef int64_t INT_64;
+
+/** SMA type for 64 bit unsigned value */
+typedef uint64_t UNS_64;
+
+/** 32 bit boolean type */
+typedef Bool BOOL_32;
+
+/** 16 bit boolean type */
+typedef Bool BOOL_16;
+
+/** 8 bit boolean type */
+typedef Bool BOOL_8;
+
+/**
+ * @}
+ */
+
+
+#endif /* LPC_TYPES_H */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/src/shared/cmsis/Drivers/include/vector.h b/src/shared/cmsis/Drivers/include/vector.h
@@ -0,0 +1,63 @@
+/*
+ * Source: libopencm3 library: https://github.com/libopencm3/libopencm3
+ */
+
+#define NVIC_WDT_IRQ 0
+#define NVIC_TIMER0_IRQ 1
+#define NVIC_TIMER1_IRQ 2
+#define NVIC_TIMER2_IRQ 3
+#define NVIC_TIMER3_IRQ 4
+#define NVIC_UART0_IRQ 5
+#define NVIC_UART1_IRQ 6
+#define NVIC_UART2_IRQ 7
+#define NVIC_UART3_IRQ 8
+#define NVIC_PWM_IRQ 9
+#define NVIC_I2C0_IRQ 10
+#define NVIC_I2C1_IRQ 11
+#define NVIC_I2C2_IRQ 12
+#define NVIC_SPI_IRQ 13
+#define NVIC_SSP0_IRQ 14
+#define NVIC_SSP1_IRQ 15
+#define NVIC_PLL0_IRQ 16
+#define NVIC_RTC_IRQ 17
+#define NVIC_EINT0_IRQ 18
+#define NVIC_EINT1_IRQ 19
+#define NVIC_EINT2_IRQ 20
+#define NVIC_EINT3_IRQ 21
+#define NVIC_ADC_IRQ 22
+#define NVIC_BOD_IRQ 23
+#define NVIC_USB_IRQ 24
+#define NVIC_CAN_IRQ 25
+#define NVIC_GPDMA_IRQ 26
+#define NVIC_I2S_IRQ 27
+#define NVIC_ETHERNET_IRQ 28
+#define NVIC_RIT_IRQ 29
+#define NVIC_MOTOR_PWM_IRQ 30
+#define NVIC_QEI_IRQ 31
+#define NVIC_PLL1_IRQ 32
+#define NVIC_USB_ACT_IRQ 33
+#define NVIC_CAN_ACT_IRQ 34
+
+#define NVIC_IRQ_COUNT 35
+
+typedef void (*vector_table_entry_t)(void);
+
+typedef struct {
+ unsigned int *initial_sp_value; /**< Initial stack pointer value. */
+ vector_table_entry_t reset;
+ vector_table_entry_t nmi;
+ vector_table_entry_t hard_fault;
+ vector_table_entry_t memory_manage_fault; /* not in CM0 */
+ vector_table_entry_t bus_fault; /* not in CM0 */
+ vector_table_entry_t usage_fault; /* not in CM0 */
+ vector_table_entry_t reserved_x001c[4];
+ vector_table_entry_t sv_call;
+ vector_table_entry_t debug_monitor; /* not in CM0 */
+ vector_table_entry_t reserved_x0034;
+ vector_table_entry_t pend_sv;
+ vector_table_entry_t systick;
+ vector_table_entry_t irq[NVIC_IRQ_COUNT];
+} vector_table_t;
+
+extern unsigned _data_lma, _data, _edata, _ebss, _stack;
+extern vector_table_t vector_table;
diff --git a/src/shared/cmsis/Drivers/makefile b/src/shared/cmsis/Drivers/makefile
@@ -0,0 +1,84 @@
+########################################################################
+# $Id:: makefile 814 2008-06-19 19:57:32Z pdurgesh $
+#
+# Project: Standard compile makefile
+#
+# Description:
+# Makefile
+#
+########################################################################
+# Software that is described herein is for illustrative purposes only
+# which provides customers with programming information regarding the
+# products. This software is supplied "AS IS" without any warranties.
+# NXP Semiconductors assumes no responsibility or liability for the
+# use of the software, conveys no license or title under any patent,
+# copyright, or mask work right to the product. NXP Semiconductors
+# reserves the right to make changes in the software without
+# notification. NXP Semiconductors also make no representation or
+# warranty that such application will be suitable for the specified
+# use without further testing or modification.
+########################################################################
+
+########################################################################
+#
+# Pick up the configuration file in make section
+#
+########################################################################
+include ../../makesection/makeconfig
+
+########################################################################
+#
+# Pick up the default build rules
+#
+########################################################################
+
+include $(PROJ_ROOT)/makesection/makerule/$(DEVICE)/make.$(DEVICE).$(TOOL)
+
+########################################################################
+#
+# Pick up the assembler and C source files in the directory
+#
+########################################################################
+include $(PROJ_ROOT)/makesection/makerule/common/make.rules.ftypes
+AFLAGS +=-I../include
+CFLAGS +=-I../include
+
+
+########################################################################
+#
+# Build the library
+#
+########################################################################
+
+$(TARGET_FWLIB_LIB) : .vias $(OBJS) $(FWLIB_LIB_DIR)
+ $(ECHO) "creating" $(FWLIB) "Firmware support package library"
+ $(AR) $@ $(OBJS)
+
+$(FWLIB_LIB_DIR):
+ $(MKDIR) $(FWLIB_LIB_DIR)
+
+# delete all targets this Makefile can make
+lib_clean:
+ -@$(RM) $(TARGET_FWLIB_LIB)
+
+# delete all targets this Makefile can make and all built libraries
+# linked in
+lib_realclean:
+ -@$(RM) $(FWLIB_LIB_DIR)/*.a
+ -@$(RMDIR) $(FWLIB_LIB_DIR)
+
+clean: lib_clean
+realclean: lib_realclean
+
+########################################################################
+#
+# Compile the code base
+#
+########################################################################
+
+include $(PROJ_ROOT)/makesection/makerule/common/make.rules.build
+
+.PHONY: all lib_clean lib_realclean
+
+
+
diff --git a/src/shared/cmsis/Drivers/source/debug_frmwrk.c b/src/shared/cmsis/Drivers/source/debug_frmwrk.c
@@ -0,0 +1,322 @@
+/**********************************************************************
+* $Id$ debug_frmwrk.c 2010-05-21
+*//**
+* @file debug_frmwrk.c
+* @brief Contains some utilities that used for debugging through UART
+* @version 2.0
+* @date 21. May. 2010
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2010, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+#include "debug_frmwrk.h"
+#include "lpc17xx_pinsel.h"
+
+/* If this source file built with example, the LPC17xx FW library configuration
+ * file in each example directory ("lpc17xx_libcfg.h") must be included,
+ * otherwise the default FW library configuration file must be included instead
+ */
+#ifdef __BUILD_WITH_EXAMPLE__
+#include "lpc17xx_libcfg.h"
+#else
+#include "lpc17xx_libcfg_default.h"
+#endif /* __BUILD_WITH_EXAMPLE__ */
+
+#ifdef _DBGFWK
+/* Debug framework */
+
+void (*_db_msg)(LPC_UART_TypeDef *UARTx, const void *s);
+void (*_db_msg_)(LPC_UART_TypeDef *UARTx, const void *s);
+void (*_db_char)(LPC_UART_TypeDef *UARTx, uint8_t ch);
+void (*_db_dec)(LPC_UART_TypeDef *UARTx, uint8_t decn);
+void (*_db_dec_16)(LPC_UART_TypeDef *UARTx, uint16_t decn);
+void (*_db_dec_32)(LPC_UART_TypeDef *UARTx, uint32_t decn);
+void (*_db_hex)(LPC_UART_TypeDef *UARTx, uint8_t hexn);
+void (*_db_hex_16)(LPC_UART_TypeDef *UARTx, uint16_t hexn);
+void (*_db_hex_32)(LPC_UART_TypeDef *UARTx, uint32_t hexn);
+uint8_t (*_db_get_char)(LPC_UART_TypeDef *UARTx);
+
+
+/*********************************************************************//**
+ * @brief Puts a character to UART port
+ * @param[in] UARTx Pointer to UART peripheral
+ * @param[in] ch Character to put
+ * @return None
+ **********************************************************************/
+void UARTPutChar (LPC_UART_TypeDef *UARTx, uint8_t ch)
+{
+ UART_Send(UARTx, &ch, 1, BLOCKING);
+}
+
+
+/*********************************************************************//**
+ * @brief Get a character to UART port
+ * @param[in] UARTx Pointer to UART peripheral
+ * @return character value that returned
+ **********************************************************************/
+uint8_t UARTGetChar (LPC_UART_TypeDef *UARTx)
+{
+ uint8_t tmp = 0;
+ UART_Receive(UARTx, &tmp, 1, BLOCKING);
+ return(tmp);
+}
+
+
+/*********************************************************************//**
+ * @brief Puts a string to UART port
+ * @param[in] UARTx Pointer to UART peripheral
+ * @param[in] str string to put
+ * @return None
+ **********************************************************************/
+void UARTPuts(LPC_UART_TypeDef *UARTx, const void *str)
+{
+ uint8_t *s = (uint8_t *) str;
+
+ while (*s)
+ {
+ UARTPutChar(UARTx, *s++);
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Puts a string to UART port and print new line
+ * @param[in] UARTx Pointer to UART peripheral
+ * @param[in] str String to put
+ * @return None
+ **********************************************************************/
+void UARTPuts_(LPC_UART_TypeDef *UARTx, const void *str)
+{
+ UARTPuts (UARTx, str);
+ UARTPuts (UARTx, "\n\r");
+}
+
+
+/*********************************************************************//**
+ * @brief Puts a decimal number to UART port
+ * @param[in] UARTx Pointer to UART peripheral
+ * @param[in] decnum Decimal number (8-bit long)
+ * @return None
+ **********************************************************************/
+void UARTPutDec(LPC_UART_TypeDef *UARTx, uint8_t decnum)
+{
+ uint8_t c1=decnum%10;
+ uint8_t c2=(decnum/10)%10;
+ uint8_t c3=(decnum/100)%10;
+ UARTPutChar(UARTx, '0'+c3);
+ UARTPutChar(UARTx, '0'+c2);
+ UARTPutChar(UARTx, '0'+c1);
+}
+
+/*********************************************************************//**
+ * @brief Puts a decimal number to UART port
+ * @param[in] UARTx Pointer to UART peripheral
+ * @param[in] decnum Decimal number (8-bit long)
+ * @return None
+ **********************************************************************/
+void UARTPutDec16(LPC_UART_TypeDef *UARTx, uint16_t decnum)
+{
+ uint8_t c1=decnum%10;
+ uint8_t c2=(decnum/10)%10;
+ uint8_t c3=(decnum/100)%10;
+ uint8_t c4=(decnum/1000)%10;
+ uint8_t c5=(decnum/10000)%10;
+ UARTPutChar(UARTx, '0'+c5);
+ UARTPutChar(UARTx, '0'+c4);
+ UARTPutChar(UARTx, '0'+c3);
+ UARTPutChar(UARTx, '0'+c2);
+ UARTPutChar(UARTx, '0'+c1);
+}
+
+/*********************************************************************//**
+ * @brief Puts a decimal number to UART port
+ * @param[in] UARTx Pointer to UART peripheral
+ * @param[in] decnum Decimal number (8-bit long)
+ * @return None
+ **********************************************************************/
+void UARTPutDec32(LPC_UART_TypeDef *UARTx, uint32_t decnum)
+{
+ uint8_t c1=decnum%10;
+ uint8_t c2=(decnum/10)%10;
+ uint8_t c3=(decnum/100)%10;
+ uint8_t c4=(decnum/1000)%10;
+ uint8_t c5=(decnum/10000)%10;
+ uint8_t c6=(decnum/100000)%10;
+ uint8_t c7=(decnum/1000000)%10;
+ uint8_t c8=(decnum/10000000)%10;
+ uint8_t c9=(decnum/100000000)%10;
+ uint8_t c10=(decnum/1000000000)%10;
+ UARTPutChar(UARTx, '0'+c10);
+ UARTPutChar(UARTx, '0'+c9);
+ UARTPutChar(UARTx, '0'+c8);
+ UARTPutChar(UARTx, '0'+c7);
+ UARTPutChar(UARTx, '0'+c6);
+ UARTPutChar(UARTx, '0'+c5);
+ UARTPutChar(UARTx, '0'+c4);
+ UARTPutChar(UARTx, '0'+c3);
+ UARTPutChar(UARTx, '0'+c2);
+ UARTPutChar(UARTx, '0'+c1);
+}
+
+/*********************************************************************//**
+ * @brief Puts a hex number to UART port
+ * @param[in] UARTx Pointer to UART peripheral
+ * @param[in] hexnum Hex number (8-bit long)
+ * @return None
+ **********************************************************************/
+void UARTPutHex (LPC_UART_TypeDef *UARTx, uint8_t hexnum)
+{
+ uint8_t nibble, i;
+
+ UARTPuts(UARTx, "0x");
+ i = 1;
+ do {
+ nibble = (hexnum >> (4*i)) & 0x0F;
+ UARTPutChar(UARTx, (nibble > 9) ? ('A' + nibble - 10) : ('0' + nibble));
+ } while (i--);
+}
+
+
+/*********************************************************************//**
+ * @brief Puts a hex number to UART port
+ * @param[in] UARTx Pointer to UART peripheral
+ * @param[in] hexnum Hex number (16-bit long)
+ * @return None
+ **********************************************************************/
+void UARTPutHex16 (LPC_UART_TypeDef *UARTx, uint16_t hexnum)
+{
+ uint8_t nibble, i;
+
+ UARTPuts(UARTx, "0x");
+ i = 3;
+ do {
+ nibble = (hexnum >> (4*i)) & 0x0F;
+ UARTPutChar(UARTx, (nibble > 9) ? ('A' + nibble - 10) : ('0' + nibble));
+ } while (i--);
+}
+
+/*********************************************************************//**
+ * @brief Puts a hex number to UART port
+ * @param[in] UARTx Pointer to UART peripheral
+ * @param[in] hexnum Hex number (32-bit long)
+ * @return None
+ **********************************************************************/
+void UARTPutHex32 (LPC_UART_TypeDef *UARTx, uint32_t hexnum)
+{
+ uint8_t nibble, i;
+
+ UARTPuts(UARTx, "0x");
+ i = 7;
+ do {
+ nibble = (hexnum >> (4*i)) & 0x0F;
+ UARTPutChar(UARTx, (nibble > 9) ? ('A' + nibble - 10) : ('0' + nibble));
+ } while (i--);
+}
+
+///*********************************************************************//**
+// * @brief print function that supports format as same as printf()
+// * function of <stdio.h> library
+// * @param[in] None
+// * @return None
+// **********************************************************************/
+//void _printf (const char *format, ...)
+//{
+// static char buffer[512 + 1];
+// va_list vArgs;
+// char *tmp;
+// va_start(vArgs, format);
+// vsprintf((char *)buffer, (char const *)format, vArgs);
+// va_end(vArgs);
+//
+// _DBG(buffer);
+//}
+
+/*********************************************************************//**
+ * @brief Initialize Debug frame work through initializing UART port
+ * @param[in] None
+ * @return None
+ **********************************************************************/
+void debug_frmwrk_init(void)
+{
+ UART_CFG_Type UARTConfigStruct;
+ PINSEL_CFG_Type PinCfg;
+
+#if (USED_UART_DEBUG_PORT==0)
+ /*
+ * Initialize UART0 pin connect
+ */
+ PinCfg.Funcnum = 1;
+ PinCfg.OpenDrain = 0;
+ PinCfg.Pinmode = 0;
+ PinCfg.Pinnum = 2;
+ PinCfg.Portnum = 0;
+ PINSEL_ConfigPin(&PinCfg);
+ PinCfg.Pinnum = 3;
+ PINSEL_ConfigPin(&PinCfg);
+
+#elif (USED_UART_DEBUG_PORT==1)
+ /*
+ * Initialize UART1 pin connect
+ */
+ PinCfg.Funcnum = 1;
+ PinCfg.OpenDrain = 0;
+ PinCfg.Pinmode = 0;
+ PinCfg.Pinnum = 15;
+ PinCfg.Portnum = 0;
+ PINSEL_ConfigPin(&PinCfg);
+ PinCfg.Pinnum = 16;
+ PINSEL_ConfigPin(&PinCfg);
+#endif
+
+ /* Initialize UART Configuration parameter structure to default state:
+ * Baudrate = 9600bps
+ * 8 data bit
+ * 1 Stop bit
+ * None parity
+ */
+ UART_ConfigStructInit(&UARTConfigStruct);
+
+ // Re-configure baudrate to 115200bps
+ UARTConfigStruct.Baud_rate = 115200;
+
+ // Initialize DEBUG_UART_PORT peripheral with given to corresponding parameter
+ UART_Init((LPC_UART_TypeDef *)DEBUG_UART_PORT, &UARTConfigStruct);
+
+ // Enable UART Transmit
+ UART_TxCmd((LPC_UART_TypeDef *)DEBUG_UART_PORT, ENABLE);
+
+ _db_msg = UARTPuts;
+ _db_msg_ = UARTPuts_;
+ _db_char = UARTPutChar;
+ _db_hex = UARTPutHex;
+ _db_hex_16 = UARTPutHex16;
+ _db_hex_32 = UARTPutHex32;
+ _db_dec = UARTPutDec;
+ _db_dec_16 = UARTPutDec16;
+ _db_dec_32 = UARTPutDec32;
+ _db_get_char = UARTGetChar;
+}
+#endif /*_DBGFWK */
+
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/src/shared/cmsis/Drivers/source/lpc17xx_adc.c b/src/shared/cmsis/Drivers/source/lpc17xx_adc.c
@@ -0,0 +1,358 @@
+/**********************************************************************
+* $Id$ lpc17xx_adc.c 2010-06-18
+*//**
+* @file lpc17xx_adc.c
+* @brief Contains all functions support for ADC firmware library on LPC17xx
+* @version 3.1
+* @date 26. July. 2011
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @addtogroup ADC
+ * @{
+ */
+
+/* Includes ------------------------------------------------------------------- */
+#include "lpc17xx_adc.h"
+#include "lpc17xx_clkpwr.h"
+
+/* If this source file built with example, the LPC17xx FW library configuration
+ * file in each example directory ("lpc17xx_libcfg.h") must be included,
+ * otherwise the default FW library configuration file must be included instead
+ */
+#ifdef __BUILD_WITH_EXAMPLE__
+#include "lpc17xx_libcfg.h"
+#else
+#include "lpc17xx_libcfg_default.h"
+#endif /* __BUILD_WITH_EXAMPLE__ */
+
+
+#ifdef _ADC
+
+/* Public Functions ----------------------------------------------------------- */
+/** @addtogroup ADC_Public_Functions
+ * @{
+ */
+
+/*********************************************************************//**
+ * @brief Initial for ADC
+ * + Set bit PCADC
+ * + Set clock for ADC
+ * + Set Clock Frequency
+ * @param[in] ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC
+ * @param[in] rate ADC conversion rate, should be <=200KHz
+ * @return None
+ **********************************************************************/
+void ADC_Init(LPC_ADC_TypeDef *ADCx, uint32_t rate)
+{
+ uint32_t ADCPClk, temp, tmp;
+
+ CHECK_PARAM(PARAM_ADCx(ADCx));
+ CHECK_PARAM(PARAM_ADC_RATE(rate));
+
+ // Turn on power and clock
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCAD, ENABLE);
+
+ ADCx->ADCR = 0;
+
+ //Enable PDN bit
+ tmp = ADC_CR_PDN;
+ // Set clock frequency
+ ADCPClk = CLKPWR_GetPCLK(CLKPWR_PCLKSEL_ADC);
+ /* The APB clock (PCLK_ADC0) is divided by (CLKDIV+1) to produce the clock for
+ * A/D converter, which should be less than or equal to 13MHz.
+ * A fully conversion requires 65 of these clocks.
+ * ADC clock = PCLK_ADC0 / (CLKDIV + 1);
+ * ADC rate = ADC clock / 65;
+ */
+ temp = rate * 65;
+ temp = (ADCPClk * 2 + temp)/(2 * temp) - 1; //get the round value by fomular: (2*A + B)/(2*B)
+ tmp |= ADC_CR_CLKDIV(temp);
+
+ ADCx->ADCR = tmp;
+}
+
+
+/*********************************************************************//**
+* @brief Close ADC
+* @param[in] ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC
+* @return None
+**********************************************************************/
+void ADC_DeInit(LPC_ADC_TypeDef *ADCx)
+{
+ CHECK_PARAM(PARAM_ADCx(ADCx));
+ if (ADCx->ADCR & ADC_CR_START_MASK) //need to stop START bits before DeInit
+ ADCx->ADCR &= ~ADC_CR_START_MASK;
+ // Clear SEL bits
+ ADCx->ADCR &= ~0xFF;
+ // Clear PDN bit
+ ADCx->ADCR &= ~ADC_CR_PDN;
+ // Turn on power and clock
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCAD, DISABLE);
+}
+
+
+/*********************************************************************//**
+* @brief Get Result conversion from A/D data register
+* @param[in] channel number which want to read back the result
+* @return Result of conversion
+*********************************************************************/
+uint32_t ADC_GetData(uint32_t channel)
+{
+ uint32_t adc_value;
+
+ CHECK_PARAM(PARAM_ADC_CHANNEL_SELECTION(channel));
+
+ adc_value = *(uint32_t *)((&LPC_ADC->ADDR0) + channel);
+ return ADC_GDR_RESULT(adc_value);
+}
+
+/*********************************************************************//**
+* @brief Set start mode for ADC
+* @param[in] ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC
+* @param[in] start_mode Start mode choose one of modes in
+* 'ADC_START_OPT' enumeration type definition, should be:
+* - ADC_START_CONTINUOUS
+* - ADC_START_NOW
+* - ADC_START_ON_EINT0
+* - ADC_START_ON_CAP01
+* - ADC_START_ON_MAT01
+* - ADC_START_ON_MAT03
+* - ADC_START_ON_MAT10
+* - ADC_START_ON_MAT11
+* @return None
+*********************************************************************/
+void ADC_StartCmd(LPC_ADC_TypeDef *ADCx, uint8_t start_mode)
+{
+ CHECK_PARAM(PARAM_ADCx(ADCx));
+ CHECK_PARAM(PARAM_ADC_START_OPT(start_mode));
+
+ ADCx->ADCR &= ~ADC_CR_START_MASK;
+ ADCx->ADCR |=ADC_CR_START_MODE_SEL((uint32_t)start_mode);
+}
+
+
+/*********************************************************************//**
+* @brief ADC Burst mode setting
+* @param[in] ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC
+* @param[in] NewState
+* - 1: Set Burst mode
+* - 0: reset Burst mode
+* @return None
+**********************************************************************/
+void ADC_BurstCmd(LPC_ADC_TypeDef *ADCx, FunctionalState NewState)
+{
+ CHECK_PARAM(PARAM_ADCx(ADCx));
+
+ ADCx->ADCR &= ~ADC_CR_BURST;
+ if (NewState){
+ ADCx->ADCR |= ADC_CR_BURST;
+ }
+}
+
+/*********************************************************************//**
+* @brief Set AD conversion in power mode
+* @param[in] ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC
+* @param[in] NewState
+* - 1: AD converter is optional
+* - 0: AD Converter is in power down mode
+* @return None
+**********************************************************************/
+void ADC_PowerdownCmd(LPC_ADC_TypeDef *ADCx, FunctionalState NewState)
+{
+ CHECK_PARAM(PARAM_ADCx(ADCx));
+
+ ADCx->ADCR &= ~ADC_CR_PDN;
+ if (NewState){
+ ADCx->ADCR |= ADC_CR_PDN;
+ }
+}
+
+/*********************************************************************//**
+* @brief Set Edge start configuration
+* @param[in] ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC
+* @param[in] EdgeOption is ADC_START_ON_RISING and ADC_START_ON_FALLING
+* 0:ADC_START_ON_RISING
+* 1:ADC_START_ON_FALLING
+* @return None
+**********************************************************************/
+void ADC_EdgeStartConfig(LPC_ADC_TypeDef *ADCx, uint8_t EdgeOption)
+{
+ CHECK_PARAM(PARAM_ADCx(ADCx));
+ CHECK_PARAM(PARAM_ADC_START_ON_EDGE_OPT(EdgeOption));
+
+ ADCx->ADCR &= ~ADC_CR_EDGE;
+ if (EdgeOption){
+ ADCx->ADCR |= ADC_CR_EDGE;
+ }
+}
+
+/*********************************************************************//**
+* @brief ADC interrupt configuration
+* @param[in] ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC
+* @param[in] IntType: type of interrupt, should be:
+* - ADC_ADINTEN0: Interrupt channel 0
+* - ADC_ADINTEN1: Interrupt channel 1
+* ...
+* - ADC_ADINTEN7: Interrupt channel 7
+* - ADC_ADGINTEN: Individual channel/global flag done generate an interrupt
+* @param[in] NewState:
+* - SET : enable ADC interrupt
+* - RESET: disable ADC interrupt
+* @return None
+**********************************************************************/
+void ADC_IntConfig (LPC_ADC_TypeDef *ADCx, ADC_TYPE_INT_OPT IntType, FunctionalState NewState)
+{
+ CHECK_PARAM(PARAM_ADCx(ADCx));
+ CHECK_PARAM(PARAM_ADC_TYPE_INT_OPT(IntType));
+
+ ADCx->ADINTEN &= ~ADC_INTEN_CH(IntType);
+ if (NewState){
+ ADCx->ADINTEN |= ADC_INTEN_CH(IntType);
+ }
+}
+
+/*********************************************************************//**
+* @brief Enable/Disable ADC channel number
+* @param[in] ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC
+* @param[in] Channel channel number
+* @param[in] NewState Enable or Disable
+*
+* @return None
+**********************************************************************/
+void ADC_ChannelCmd (LPC_ADC_TypeDef *ADCx, uint8_t Channel, FunctionalState NewState)
+{
+ CHECK_PARAM(PARAM_ADCx(ADCx));
+ CHECK_PARAM(PARAM_ADC_CHANNEL_SELECTION(Channel));
+
+ if (NewState == ENABLE) {
+ ADCx->ADCR |= ADC_CR_CH_SEL(Channel);
+ } else {
+ if (ADCx->ADCR & ADC_CR_START_MASK) //need to stop START bits before disable channel
+ ADCx->ADCR &= ~ADC_CR_START_MASK;
+ ADCx->ADCR &= ~ADC_CR_CH_SEL(Channel);
+ }
+}
+
+/*********************************************************************//**
+* @brief Get ADC result
+* @param[in] ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC
+* @param[in] channel: channel number, should be 0...7
+* @return Data conversion
+**********************************************************************/
+uint16_t ADC_ChannelGetData(LPC_ADC_TypeDef *ADCx, uint8_t channel)
+{
+ uint32_t adc_value;
+
+ CHECK_PARAM(PARAM_ADCx(ADCx));
+ CHECK_PARAM(PARAM_ADC_CHANNEL_SELECTION(channel));
+
+ adc_value = *(uint32_t *) ((&ADCx->ADDR0) + channel);
+ return ADC_DR_RESULT(adc_value);
+}
+
+/*********************************************************************//**
+* @brief Get ADC Chanel status from ADC data register
+* @param[in] ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC
+* @param[in] channel: channel number, should be 0..7
+* @param[in] StatusType
+* 0:Burst status
+* 1:Done status
+* @return SET / RESET
+**********************************************************************/
+FlagStatus ADC_ChannelGetStatus(LPC_ADC_TypeDef *ADCx, uint8_t channel, uint32_t StatusType)
+{
+ uint32_t temp;
+
+ CHECK_PARAM(PARAM_ADCx(ADCx));
+ CHECK_PARAM(PARAM_ADC_CHANNEL_SELECTION(channel));
+ CHECK_PARAM(PARAM_ADC_DATA_STATUS(StatusType));
+
+ temp = *(uint32_t *) ((&ADCx->ADDR0) + channel);
+ if (StatusType) {
+ temp &= ADC_DR_DONE_FLAG;
+ }else{
+ temp &= ADC_DR_OVERRUN_FLAG;
+ }
+ if (temp) {
+ return SET;
+ } else {
+ return RESET;
+ }
+
+}
+
+/*********************************************************************//**
+* @brief Get ADC Data from AD Global register
+* @param[in] ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC
+* @return Result of conversion
+**********************************************************************/
+uint32_t ADC_GlobalGetData(LPC_ADC_TypeDef *ADCx)
+{
+ CHECK_PARAM(PARAM_ADCx(ADCx));
+
+ return ((uint32_t)(ADCx->ADGDR));
+}
+
+/*********************************************************************//**
+* @brief Get ADC Chanel status from AD global data register
+* @param[in] ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC
+* @param[in] StatusType
+* 0:Burst status
+* 1:Done status
+* @return SET / RESET
+**********************************************************************/
+FlagStatus ADC_GlobalGetStatus(LPC_ADC_TypeDef *ADCx, uint32_t StatusType)
+{
+ uint32_t temp;
+
+ CHECK_PARAM(PARAM_ADCx(ADCx));
+ CHECK_PARAM(PARAM_ADC_DATA_STATUS(StatusType));
+
+ temp = ADCx->ADGDR;
+ if (StatusType){
+ temp &= ADC_DR_DONE_FLAG;
+ }else{
+ temp &= ADC_DR_OVERRUN_FLAG;
+ }
+ if (temp){
+ return SET;
+ }else{
+ return RESET;
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* _ADC */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
+
diff --git a/src/shared/cmsis/Drivers/source/lpc17xx_can.c b/src/shared/cmsis/Drivers/source/lpc17xx_can.c
@@ -0,0 +1,1936 @@
+/**********************************************************************
+* $Id$ lpc17xx_can.c 2011-03-09
+*//**
+* @file lpc17xx_can.c
+* @brief Contains all functions support for CAN firmware library on LPC17xx
+* @version 3.3
+* @date 09. March. 2011
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @addtogroup CAN
+ * @{
+ */
+
+/* Includes ------------------------------------------------------------------- */
+#include "lpc17xx_can.h"
+#include "lpc17xx_clkpwr.h"
+
+/* If this source file built with example, the LPC17xx FW library configuration
+ * file in each example directory ("lpc17xx_libcfg.h") must be included,
+ * otherwise the default FW library configuration file must be included instead
+ */
+#ifdef __BUILD_WITH_EXAMPLE__
+#include "lpc17xx_libcfg.h"
+#else
+#include "lpc17xx_libcfg_default.h"
+#endif /* __BUILD_WITH_EXAMPLE__ */
+
+
+#ifdef _CAN
+
+/* Private Variables ---------------------------------------------------------- */
+/** @defgroup CAN_Private_Variables CAN Private Variables
+ * @{
+ */
+
+FunctionalState FULLCAN_ENABLE;
+
+
+/* Counts number of filters (CAN message objects) used */
+uint16_t CANAF_FullCAN_cnt = 0;
+uint16_t CANAF_std_cnt = 0;
+uint16_t CANAF_gstd_cnt = 0;
+uint16_t CANAF_ext_cnt = 0;
+uint16_t CANAF_gext_cnt = 0;
+
+/* End of Private Variables ----------------------------------------------------*/
+/**
+ * @}
+ */
+
+/* Private Variables ---------------------------------------------------------- */
+static void can_SetBaudrate (LPC_CAN_TypeDef *CANx, uint32_t baudrate);
+
+/*********************************************************************//**
+ * @brief Setting CAN baud rate (bps)
+ * @param[in] CANx point to LPC_CAN_TypeDef object, should be:
+ * - LPC_CAN1: CAN1 peripheral
+ * - LPC_CAN2: CAN2 peripheral
+ * @param[in] baudrate: is the baud rate value will be set
+ * @return None
+ ***********************************************************************/
+static void can_SetBaudrate (LPC_CAN_TypeDef *CANx, uint32_t baudrate)
+{
+ uint32_t result = 0;
+ uint8_t NT, TSEG1, TSEG2, BRFail;
+ uint32_t CANPclk = 0;
+ uint32_t BRP;
+ CHECK_PARAM(PARAM_CANx(CANx));
+
+ if (CANx == LPC_CAN1)
+ {
+ CANPclk = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_CAN1);
+ }
+ else
+ {
+ CANPclk = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_CAN2);
+ }
+ result = CANPclk / baudrate;
+ /* Calculate suitable nominal time value
+ * NT (nominal time) = (TSEG1 + TSEG2 + 3)
+ * NT <= 24
+ * TSEG1 >= 2*TSEG2
+ */
+ BRFail = 1;
+ for(NT=24;NT>0;NT=NT-2)
+ {
+ if ((result%NT)==0)
+ {
+ BRP = result / NT - 1;
+ NT--;
+ TSEG2 = (NT/3) - 1;
+ TSEG1 = NT -(NT/3) - 1;
+ BRFail = 0;
+ break;
+ }
+ }
+ if(BRFail)
+ while(1); // Failed to calculate exact CAN baud rate
+ /* Enter reset mode */
+ CANx->MOD = 0x01;
+ /* Set bit timing
+ * Default: SAM = 0x00;
+ * SJW = 0x03;
+ */
+ CANx->BTR = (TSEG2<<20)|(TSEG1<<16)|(3<<14)|BRP;
+ /* Return to normal operating */
+ CANx->MOD = 0;
+}
+/* End of Private Functions ----------------------------------------------------*/
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @addtogroup CAN_Public_Functions
+ * @{
+ */
+
+/********************************************************************//**
+ * @brief Initialize CAN peripheral with given baudrate
+ * @param[in] CANx pointer to LPC_CAN_TypeDef, should be:
+ * - LPC_CAN1: CAN1 peripheral
+ * - LPC_CAN2: CAN2 peripheral
+ * @param[in] baudrate: the value of CAN baudrate will be set (bps)
+ * @return None
+ *********************************************************************/
+void CAN_Init(LPC_CAN_TypeDef *CANx, uint32_t baudrate)
+{
+ uint16_t i;
+ CHECK_PARAM(PARAM_CANx(CANx));
+
+ if(CANx == LPC_CAN1)
+ {
+ /* Turn on power and clock for CAN1 */
+ CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCAN1, ENABLE);
+ /* Set clock divide for CAN1 */
+ }
+ else
+ {
+ /* Turn on power and clock for CAN1 */
+ CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCAN2, ENABLE);
+ /* Set clock divide for CAN2 */
+ }
+ CLKPWR_SetPCLKDiv (CLKPWR_PCLKSEL_CAN1, CLKPWR_PCLKSEL_CCLK_DIV_2);
+ CLKPWR_SetPCLKDiv (CLKPWR_PCLKSEL_CAN2, CLKPWR_PCLKSEL_CCLK_DIV_2);
+ CLKPWR_SetPCLKDiv (CLKPWR_PCLKSEL_ACF, CLKPWR_PCLKSEL_CCLK_DIV_2);
+
+ CANx->MOD = 1; // Enter Reset Mode
+ CANx->IER = 0; // Disable All CAN Interrupts
+ CANx->GSR = 0;
+ /* Request command to release Rx, Tx buffer and clear data overrun */
+ //CANx->CMR = CAN_CMR_AT | CAN_CMR_RRB | CAN_CMR_CDO;
+ CANx->CMR = (1<<1)|(1<<2)|(1<<3);
+ /* Read to clear interrupt pending in interrupt capture register */
+ i = CANx->ICR;
+ CANx->MOD = 0;// Return Normal operating
+
+ //Reset CANAF value
+ LPC_CANAF->AFMR = 0x01;
+
+ //clear ALUT RAM
+ for (i = 0; i < 512; i++) {
+ LPC_CANAF_RAM->mask[i] = 0x00;
+ }
+
+ LPC_CANAF->SFF_sa = 0x00;
+ LPC_CANAF->SFF_GRP_sa = 0x00;
+ LPC_CANAF->EFF_sa = 0x00;
+ LPC_CANAF->EFF_GRP_sa = 0x00;
+ LPC_CANAF->ENDofTable = 0x00;
+
+ LPC_CANAF->AFMR = 0x00;
+ /* Set baudrate */
+ can_SetBaudrate (CANx, baudrate);
+}
+
+/********************************************************************//**
+ * @brief CAN deInit
+ * @param[in] CANx pointer to LPC_CAN_TypeDef, should be:
+ * - LPC_CAN1: CAN1 peripheral
+ * - LPC_CAN2: CAN2 peripheral
+ * @return None
+ *********************************************************************/
+void CAN_DeInit(LPC_CAN_TypeDef *CANx)
+{
+ CHECK_PARAM(PARAM_CANx(CANx));
+
+ if(CANx == LPC_CAN1)
+ {
+ /* Turn on power and clock for CAN1 */
+ CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCAN1, DISABLE);
+ }
+ else
+ {
+ /* Turn on power and clock for CAN1 */
+ CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCAN2, DISABLE);
+ }
+}
+
+/********************************************************************//**
+ * @brief Setup Acceptance Filter Look-Up Table
+ * @param[in] CANAFx pointer to LPC_CANAF_TypeDef
+ * Should be: LPC_CANAF
+ * @param[in] AFSection the pointer to AF_SectionDef structure
+ * It contain information about 5 sections will be install in AFLUT
+ * @return CAN Error could be:
+ * - CAN_OBJECTS_FULL_ERROR: No more rx or tx objects available
+ * - CAN_AF_ENTRY_ERROR: table error-violation of ascending numerical order
+ * - CAN_OK: ID is added into table successfully
+ *********************************************************************/
+CAN_ERROR CAN_SetupAFLUT(LPC_CANAF_TypeDef* CANAFx, AF_SectionDef* AFSection)
+{
+ uint8_t ctrl1,ctrl2;
+ uint8_t dis1, dis2;
+ uint16_t SID, ID_temp,i, count = 0;
+ uint32_t EID, entry, buf;
+ uint16_t lowerSID, upperSID;
+ uint32_t lowerEID, upperEID;
+
+ CHECK_PARAM(PARAM_CANAFx(CANAFx));
+ CANAFx->AFMR = 0x01;
+
+/***** setup FullCAN Table *****/
+ if(AFSection->FullCAN_Sec == NULL)
+ {
+ FULLCAN_ENABLE = DISABLE;
+ }
+ else
+ {
+ FULLCAN_ENABLE = ENABLE;
+ for(i=0;i<(AFSection->FC_NumEntry);i++)
+ {
+ if(count + 1 > 64)
+ {
+ return CAN_OBJECTS_FULL_ERROR;
+ }
+ ctrl1 = AFSection->FullCAN_Sec->controller;
+ SID = AFSection->FullCAN_Sec->id_11;
+ dis1 = AFSection->FullCAN_Sec->disable;
+
+ CHECK_PARAM(PARAM_CTRL(ctrl1));
+ CHECK_PARAM(PARAM_ID_11(SID));
+ CHECK_PARAM(PARAM_MSG_DISABLE(dis1));
+ entry = 0x00; //reset entry value
+ if((CANAF_FullCAN_cnt & 0x00000001)==0)
+ {
+ if(count!=0x00)
+ {
+ buf = LPC_CANAF_RAM->mask[count-1];
+ ID_temp = (buf & 0xE7FF); //mask controller & identifier bits
+ if(ID_temp > ((ctrl1<<13)|SID))
+ {
+ return CAN_AF_ENTRY_ERROR;
+ }
+ }
+ entry = (ctrl1<<29)|(dis1<<28)|(SID<<16)|(1<<27);
+ LPC_CANAF_RAM->mask[count] &= 0x0000FFFF;
+ LPC_CANAF_RAM->mask[count] |= entry;
+ CANAF_FullCAN_cnt++;
+ if(CANAF_FullCAN_cnt == AFSection->FC_NumEntry) //this is the lastest FullCAN entry
+ count++;
+ }
+ else
+ {
+ buf = LPC_CANAF_RAM->mask[count];
+ ID_temp = (buf >>16) & 0xE7FF;
+ if(ID_temp > ((ctrl1<<13)|SID))
+ {
+ return CAN_AF_ENTRY_ERROR;
+ }
+ entry = (ctrl1<<13)|(dis1<<12)|(SID<<0)|(1<<11);
+ LPC_CANAF_RAM->mask[count] &= 0xFFFF0000;
+ LPC_CANAF_RAM->mask[count]|= entry;
+ count++;
+ CANAF_FullCAN_cnt++;
+ }
+ AFSection->FullCAN_Sec = (FullCAN_Entry *)((uint32_t)(AFSection->FullCAN_Sec)+ sizeof(FullCAN_Entry));
+ }
+ }
+
+/***** Setup Explicit Standard Frame Format Section *****/
+ if(AFSection->SFF_Sec != NULL)
+ {
+ for(i=0;i<(AFSection->SFF_NumEntry);i++)
+ {
+ if(count + 1 > 512)
+ {
+ return CAN_OBJECTS_FULL_ERROR;
+ }
+ ctrl1 = AFSection->SFF_Sec->controller;
+ SID = AFSection->SFF_Sec->id_11;
+ dis1 = AFSection->SFF_Sec->disable;
+
+ //check parameter
+ CHECK_PARAM(PARAM_CTRL(ctrl1));
+ CHECK_PARAM(PARAM_ID_11(SID));
+ CHECK_PARAM(PARAM_MSG_DISABLE(dis1));
+
+ entry = 0x00; //reset entry value
+ if((CANAF_std_cnt & 0x00000001)==0)
+ {
+ if(CANAF_std_cnt !=0 )
+ {
+ buf = LPC_CANAF_RAM->mask[count-1];
+ ID_temp = (buf & 0xE7FF); //mask controller & identifier bits
+ if(ID_temp > ((ctrl1<<13)|SID))
+ {
+ return CAN_AF_ENTRY_ERROR;
+ }
+ }
+ entry = (ctrl1<<29)|(dis1<<28)|(SID<<16);
+ LPC_CANAF_RAM->mask[count] &= 0x0000FFFF;
+ LPC_CANAF_RAM->mask[count] |= entry;
+ CANAF_std_cnt++;
+ if(CANAF_std_cnt == AFSection->SFF_NumEntry)//if this is the last SFF entry
+ count++;
+ }
+ else
+ {
+ buf = LPC_CANAF_RAM->mask[count];
+ ID_temp = (buf >>16) & 0xE7FF;
+ if(ID_temp > ((ctrl1<<13)|SID))
+ {
+ return CAN_AF_ENTRY_ERROR;
+ }
+ entry = (ctrl1<<13)|(dis1<<12)|(SID<<0);
+ LPC_CANAF_RAM->mask[count] &= 0xFFFF0000;
+ LPC_CANAF_RAM->mask[count] |= entry;
+ count++;
+ CANAF_std_cnt++;
+ }
+ AFSection->SFF_Sec = (SFF_Entry *)((uint32_t)(AFSection->SFF_Sec)+ sizeof(SFF_Entry));
+ }
+ }
+
+/***** Setup Group of Standard Frame Format Identifier Section *****/
+ if(AFSection->SFF_GPR_Sec != NULL)
+ {
+ for(i=0;i<(AFSection->SFF_GPR_NumEntry);i++)
+ {
+ if(count + 1 > 512)
+ {
+ return CAN_OBJECTS_FULL_ERROR;
+ }
+ ctrl1 = AFSection->SFF_GPR_Sec->controller1;
+ ctrl2 = AFSection->SFF_GPR_Sec->controller2;
+ dis1 = AFSection->SFF_GPR_Sec->disable1;
+ dis2 = AFSection->SFF_GPR_Sec->disable2;
+ lowerSID = AFSection->SFF_GPR_Sec->lowerID;
+ upperSID = AFSection->SFF_GPR_Sec->upperID;
+
+ /* check parameter */
+ CHECK_PARAM(PARAM_CTRL(ctrl1));
+ CHECK_PARAM(PARAM_CTRL(ctrl2));
+ CHECK_PARAM(PARAM_MSG_DISABLE(dis1));
+ CHECK_PARAM(PARAM_MSG_DISABLE(dis2));
+ CHECK_PARAM(PARAM_ID_11(lowerSID));
+ CHECK_PARAM(PARAM_ID_11(upperSID));
+
+ entry = 0x00;
+ if(CANAF_gstd_cnt!=0)
+ {
+ buf = LPC_CANAF_RAM->mask[count-1];
+ ID_temp = buf & 0xE7FF;
+ if((ctrl1 != ctrl2)||(lowerSID > upperSID)||(ID_temp > ((ctrl1<<13)|lowerSID)))
+ {
+ return CAN_AF_ENTRY_ERROR;
+ }
+ }
+ entry = (ctrl1 << 29)|(dis1 << 28)|(lowerSID << 16)| \
+ (ctrl2 << 13)|(dis2 << 12)|(upperSID << 0);
+ LPC_CANAF_RAM->mask[count] = entry;
+ CANAF_gstd_cnt++;
+ count++;
+ AFSection->SFF_GPR_Sec = (SFF_GPR_Entry *)((uint32_t)(AFSection->SFF_GPR_Sec)+ sizeof(SFF_GPR_Entry));
+ }
+ }
+
+/***** Setup Explicit Extend Frame Format Identifier Section *****/
+ if(AFSection->EFF_Sec != NULL)
+ {
+ for(i=0;i<(AFSection->EFF_NumEntry);i++)
+ {
+ if(count + 1 > 512)
+ {
+ return CAN_OBJECTS_FULL_ERROR;
+ }
+ EID = AFSection->EFF_Sec->ID_29;
+ ctrl1 = AFSection->EFF_Sec->controller;
+
+ // check parameter
+ CHECK_PARAM(PARAM_ID_29(EID));
+ CHECK_PARAM(PARAM_CTRL(ctrl1));
+
+ entry = (ctrl1 << 29)|(EID << 0);
+ if(CANAF_ext_cnt != 0)
+ {
+ buf = LPC_CANAF_RAM->mask[count-1];
+// EID_temp = buf & 0x0FFFFFFF;
+ if(buf > entry)
+ {
+ return CAN_AF_ENTRY_ERROR;
+ }
+ }
+ LPC_CANAF_RAM->mask[count] = entry;
+ CANAF_ext_cnt ++;
+ count++;
+ AFSection->EFF_Sec = (EFF_Entry *)((uint32_t)(AFSection->EFF_Sec)+ sizeof(EFF_Entry));
+ }
+ }
+
+/***** Setup Group of Extended Frame Format Identifier Section *****/
+ if(AFSection->EFF_GPR_Sec != NULL)
+ {
+ for(i=0;i<(AFSection->EFF_GPR_NumEntry);i++)
+ {
+ if(count + 2 > 512)
+ {
+ return CAN_OBJECTS_FULL_ERROR;
+ }
+ ctrl1 = AFSection->EFF_GPR_Sec->controller1;
+ ctrl2 = AFSection->EFF_GPR_Sec->controller2;
+ lowerEID = AFSection->EFF_GPR_Sec->lowerEID;
+ upperEID = AFSection->EFF_GPR_Sec->upperEID;
+
+ //check parameter
+ CHECK_PARAM(PARAM_CTRL(ctrl1));
+ CHECK_PARAM(PARAM_CTRL(ctrl2));
+ CHECK_PARAM(PARAM_ID_29(lowerEID));
+ CHECK_PARAM(PARAM_ID_29(upperEID));
+
+ entry = 0x00;
+ if(CANAF_gext_cnt != 0)
+ {
+ buf = LPC_CANAF_RAM->mask[count-1];
+// EID_temp = buf & 0x0FFFFFFF;
+ if((ctrl1 != ctrl2) || (lowerEID > upperEID) || (buf > ((ctrl1 << 29)|(lowerEID << 0))))
+ {
+ return CAN_AF_ENTRY_ERROR;
+ }
+ }
+ entry = (ctrl1 << 29)|(lowerEID << 0);
+ LPC_CANAF_RAM->mask[count++] = entry;
+ entry = (ctrl2 << 29)|(upperEID << 0);
+ LPC_CANAF_RAM->mask[count++] = entry;
+ CANAF_gext_cnt++;
+ AFSection->EFF_GPR_Sec = (EFF_GPR_Entry *)((uint32_t)(AFSection->EFF_GPR_Sec)+ sizeof(EFF_GPR_Entry));
+ }
+ }
+ //update address values
+ LPC_CANAF->SFF_sa = ((CANAF_FullCAN_cnt + 1)>>1)<<2;
+ LPC_CANAF->SFF_GRP_sa = LPC_CANAF->SFF_sa + (((CANAF_std_cnt+1)>>1)<< 2);
+ LPC_CANAF->EFF_sa = LPC_CANAF->SFF_GRP_sa + (CANAF_gstd_cnt << 2);
+ LPC_CANAF->EFF_GRP_sa = LPC_CANAF->EFF_sa + (CANAF_ext_cnt << 2);
+ LPC_CANAF->ENDofTable = LPC_CANAF->EFF_GRP_sa + (CANAF_gext_cnt << 3);
+
+ if(FULLCAN_ENABLE == DISABLE)
+ {
+ LPC_CANAF->AFMR = 0x00; // Normal mode
+ }
+ else
+ {
+ LPC_CANAF->AFMR = 0x04;
+ }
+ return CAN_OK;
+}
+/********************************************************************//**
+ * @brief Add Explicit ID into AF Look-Up Table dynamically.
+ * @param[in] CANx pointer to LPC_CAN_TypeDef, should be:
+ * - LPC_CAN1: CAN1 peripheral
+ * - LPC_CAN2: CAN2 peripheral
+ * @param[in] id: The ID of entry will be added
+ * @param[in] format: is the type of ID Frame Format, should be:
+ * - STD_ID_FORMAT: 11-bit ID value
+ * - EXT_ID_FORMAT: 29-bit ID value
+ * @return CAN Error, could be:
+ * - CAN_OBJECTS_FULL_ERROR: No more rx or tx objects available
+ * - CAN_ID_EXIT_ERROR: ID exited in table
+ * - CAN_OK: ID is added into table successfully
+ *********************************************************************/
+CAN_ERROR CAN_LoadExplicitEntry(LPC_CAN_TypeDef* CANx, uint32_t id, CAN_ID_FORMAT_Type format)
+{
+ uint32_t tmp0 = 0;
+ uint32_t buf0=0, buf1=0;
+ int16_t cnt1=0, cnt2=0, bound1=0, total=0;
+
+
+ CHECK_PARAM(PARAM_CANx(CANx));
+ CHECK_PARAM(PARAM_ID_FORMAT(format));
+
+ if (CANx == LPC_CAN1)
+ {
+ tmp0 = 0;
+ }
+ else if (CANx == LPC_CAN2)
+ {
+ tmp0 = 1;
+ }
+
+ /* Acceptance Filter Memory full - return */
+ total =((CANAF_FullCAN_cnt+1)>>1)+ CANAF_FullCAN_cnt*3 +((CANAF_std_cnt + 1) >> 1)+ \
+ CANAF_gstd_cnt + CANAF_ext_cnt + (CANAF_gext_cnt<<1);
+ if (total >= 512){ //don't have enough space
+ return CAN_OBJECTS_FULL_ERROR;
+ }
+
+ /* Setup Acceptance Filter Configuration
+ Acceptance Filter Mode Register = Off */
+ LPC_CANAF->AFMR = 0x00000001;
+
+/*********** Add Explicit Standard Identifier Frame Format entry *********/
+ if(format == STD_ID_FORMAT)
+ {
+ id &= 0x07FF;
+ id |= (tmp0 << 13); /* Add controller number */
+ /* Move all remaining sections one place up
+ if new entry will increase FullCAN list */
+ if ((CANAF_std_cnt & 0x0001) == 0)
+ {
+ cnt1 = ((CANAF_FullCAN_cnt+1)>>1)+((CANAF_std_cnt+1)>>1);
+ bound1 = total - cnt1;
+ buf0 = LPC_CANAF_RAM->mask[cnt1];
+ while(bound1--)
+ {
+ cnt1++;
+ buf1 = LPC_CANAF_RAM->mask[cnt1];
+ LPC_CANAF_RAM->mask[cnt1] = buf0;
+ buf0 = buf1;
+ }
+ }
+ if (CANAF_std_cnt == 0)
+ {
+ cnt2 = (CANAF_FullCAN_cnt + 1)>>1;
+ /* For entering first ID */
+ LPC_CANAF_RAM->mask[cnt2] = 0x0000FFFF | (id << 16);
+ }
+ else if (CANAF_std_cnt == 1)
+ {
+ cnt2 = (CANAF_FullCAN_cnt + 1)>>1;
+ /* For entering second ID */
+ if (((LPC_CANAF_RAM->mask[cnt2] >> 16)& 0xE7FF) > id)
+ {
+ LPC_CANAF_RAM->mask[cnt2] = (LPC_CANAF_RAM->mask[cnt2] >> 16) | (id << 16);
+ }
+ else
+ {
+ LPC_CANAF_RAM->mask[cnt2] = (LPC_CANAF_RAM->mask[cnt2] & 0xFFFF0000) | id;
+ }
+ }
+ else
+ {
+ /* Find where to insert new ID */
+ cnt1 = (CANAF_FullCAN_cnt+1)>>1;
+ cnt2 = CANAF_std_cnt;
+ bound1 = ((CANAF_FullCAN_cnt+1)>>1)+((CANAF_std_cnt+1)>>1);
+ while (cnt1 < bound1)
+ {
+ /* Loop through standard existing IDs */
+ if (((LPC_CANAF_RAM->mask[cnt1] >> 16) & 0xE7FF) > id)
+ {
+ cnt2 = cnt1 * 2;
+ break;
+ }
+
+ if ((LPC_CANAF_RAM->mask[cnt1] & 0x0000E7FF) > id)
+ {
+ cnt2 = cnt1 * 2 + 1;
+ break;
+ }
+
+ cnt1++;
+ }
+ /* cnt1 = U32 where to insert new ID */
+ /* cnt2 = U16 where to insert new ID */
+
+ if (cnt1 == bound1)
+ {
+ /* Adding ID as last entry */
+ /* Even number of IDs exists */
+ if ((CANAF_std_cnt & 0x0001) == 0)
+ {
+ LPC_CANAF_RAM->mask[cnt1] = 0x0000FFFF | (id << 16);
+ }
+ /* Odd number of IDs exists */
+ else
+ {
+ LPC_CANAF_RAM->mask[cnt1] = (LPC_CANAF_RAM->mask[cnt1] & 0xFFFF0000) | id;
+ }
+ }
+ else
+ {
+ buf0 = LPC_CANAF_RAM->mask[cnt1]; /* Remember current entry */
+ if ((cnt2 & 0x0001) == 0)
+ {
+ /* Insert new mask to even address*/
+ buf1 = (id << 16) | (buf0 >> 16);
+ }
+ else
+ {
+ /* Insert new mask to odd address */
+ buf1 = (buf0 & 0xFFFF0000) | id;
+ }
+ LPC_CANAF_RAM->mask[cnt1] = buf1;/* Insert mask */
+ bound1 = ((CANAF_FullCAN_cnt+1)>>1)+((CANAF_std_cnt+1)>>1)-1;
+ /* Move all remaining standard mask entries one place up */
+ while (cnt1 < bound1)
+ {
+ cnt1++;
+ buf1 = LPC_CANAF_RAM->mask[cnt1];
+ LPC_CANAF_RAM->mask[cnt1] = (buf1 >> 16) | (buf0 << 16);
+ buf0 = buf1;
+ }
+
+ if ((CANAF_std_cnt & 0x0001) == 0)
+ {
+ /* Even number of IDs exists */
+ LPC_CANAF_RAM->mask[cnt1+1] = (buf0 <<16) |(0x0000FFFF);
+ }
+ }
+ }
+ CANAF_std_cnt++;
+ //update address values
+ LPC_CANAF->SFF_GRP_sa +=0x04 ;
+ LPC_CANAF->EFF_sa +=0x04 ;
+ LPC_CANAF->EFF_GRP_sa +=0x04;
+ LPC_CANAF->ENDofTable +=0x04;
+ }
+
+/*********** Add Explicit Extended Identifier Frame Format entry *********/
+ else
+ {
+ /* Add controller number */
+ id |= (tmp0) << 29;
+
+ cnt1 = ((CANAF_FullCAN_cnt+1)>>1)+(((CANAF_std_cnt + 1) >> 1) + CANAF_gstd_cnt);
+ cnt2 = 0;
+ while (cnt2 < CANAF_ext_cnt)
+ {
+ /* Loop through extended existing masks*/
+ if (LPC_CANAF_RAM->mask[cnt1] > id)
+ {
+ break;
+ }
+ cnt1++;/* cnt1 = U32 where to insert new mask */
+ cnt2++;
+ }
+
+ buf0 = LPC_CANAF_RAM->mask[cnt1]; /* Remember current entry */
+ LPC_CANAF_RAM->mask[cnt1] = id; /* Insert mask */
+
+ CANAF_ext_cnt++;
+
+ bound1 = total;
+ /* Move all remaining extended mask entries one place up*/
+ while (cnt2 < bound1)
+ {
+ cnt1++;
+ cnt2++;
+ buf1 = LPC_CANAF_RAM->mask[cnt1];
+ LPC_CANAF_RAM->mask[cnt1] = buf0;
+ buf0 = buf1;
+ }
+ /* update address values */
+ LPC_CANAF->EFF_GRP_sa += 4;
+ LPC_CANAF->ENDofTable += 4;
+ }
+ if(CANAF_FullCAN_cnt == 0) //not use FullCAN mode
+ {
+ LPC_CANAF->AFMR = 0x00;//not use FullCAN mode
+ }
+ else
+ {
+ LPC_CANAF->AFMR = 0x04;
+ }
+
+ return CAN_OK;
+}
+
+/********************************************************************//**
+ * @brief Load FullCAN entry into AFLUT
+ * @param[in] CANx: CAN peripheral selected, should be:
+ * - LPC_CAN1: CAN1 peripheral
+ * - LPC_CAN2: CAN2 peripheral
+ * @param[in] id: identifier of entry that will be added
+ * @return CAN_ERROR, could be:
+ * - CAN_OK: loading is successful
+ * - CAN_ID_EXIT_ERROR: ID exited in FullCAN Section
+ * - CAN_OBJECTS_FULL_ERROR: no more space available
+ *********************************************************************/
+CAN_ERROR CAN_LoadFullCANEntry (LPC_CAN_TypeDef* CANx, uint16_t id)
+{
+ uint32_t ctrl0 = 0;
+ uint32_t buf0=0, buf1=0, buf2=0;
+ uint32_t tmp0=0, tmp1=0, tmp2=0;
+ int16_t cnt1=0, cnt2=0, bound1=0, total=0;
+
+ CHECK_PARAM(PARAM_CANx(CANx));
+
+ if (CANx == LPC_CAN1)
+ {
+ ctrl0 = 0;
+ }
+ else if (CANx == LPC_CAN2)
+ {
+ ctrl0 = 1;
+ }
+
+ /* Acceptance Filter Memory full - return */
+ total =((CANAF_FullCAN_cnt+1)>>1)+ CANAF_FullCAN_cnt*3 +((CANAF_std_cnt + 1) >> 1)+ \
+ CANAF_gstd_cnt + CANAF_ext_cnt + (CANAF_gext_cnt<<1);
+ //don't have enough space for this fullCAN Entry and its Object(3*32 bytes)
+ if ((total >=508)||(CANAF_FullCAN_cnt>=64)){
+ return CAN_OBJECTS_FULL_ERROR;
+ }
+ /* Setup Acceptance Filter Configuration
+ Acceptance Filter Mode Register = Off */
+ LPC_CANAF->AFMR = 0x00000001;
+
+ /* Add mask for standard identifiers */
+ id &= 0x07FF;
+ id |= (ctrl0 << 13) | (1 << 11); /* Add controller number */
+// total = ((CANAF_std_cnt + 1) >> 1)+ CANAF_gstd_cnt + CANAF_ext_cnt + (CANAF_gext_cnt<<1);
+ /* Move all remaining sections one place up
+ if new entry will increase FullCAN list */
+ if (((CANAF_FullCAN_cnt & 0x0001) == 0)&&(total!=0))
+ {
+ //then remove remaining section
+ cnt1 = (CANAF_FullCAN_cnt >> 1);
+ bound1 = total;
+ buf0 = LPC_CANAF_RAM->mask[cnt1];
+
+ while (bound1--)
+ {
+ cnt1++;
+ buf1 = LPC_CANAF_RAM->mask[cnt1];
+ LPC_CANAF_RAM->mask[cnt1] = buf0;
+ buf0 = buf1;
+ }
+ }
+ if (CANAF_FullCAN_cnt == 0)
+ {
+ /* For entering first ID */
+ LPC_CANAF_RAM->mask[0] = 0x0000FFFF | (id << 16);
+ }
+ else if (CANAF_FullCAN_cnt == 1)
+ {
+ /* For entering second ID */
+ if (((LPC_CANAF_RAM->mask[0] >> 16)& 0xE7FF) > id)
+ {
+ LPC_CANAF_RAM->mask[0] = (LPC_CANAF_RAM->mask[0] >> 16) | (id << 16);
+ }
+ else
+ {
+ LPC_CANAF_RAM->mask[0] = (LPC_CANAF_RAM->mask[0] & 0xFFFF0000) | id;
+ }
+ }
+ else
+ {
+ /* Find where to insert new ID */
+ cnt1 = 0;
+ cnt2 = CANAF_FullCAN_cnt;
+ bound1 = (CANAF_FullCAN_cnt - 1) >> 1;
+ while (cnt1 <= bound1)
+ {
+ /* Loop through standard existing IDs */
+ if (((LPC_CANAF_RAM->mask[cnt1] >> 16) & 0xE7FF) > (id & 0xE7FF))
+ {
+ cnt2 = cnt1 * 2;
+ break;
+ }
+
+ if ((LPC_CANAF_RAM->mask[cnt1] & 0x0000E7FF) > (id & 0xE7FF))
+ {
+ cnt2 = cnt1 * 2 + 1;
+ break;
+ }
+
+ cnt1++;
+ }
+ /* cnt1 = U32 where to insert new ID */
+ /* cnt2 = U16 where to insert new ID */
+
+ if (cnt1 > bound1)
+ {
+ /* Adding ID as last entry */
+ /* Even number of IDs exists */
+ if ((CANAF_FullCAN_cnt & 0x0001) == 0)
+ {
+ LPC_CANAF_RAM->mask[cnt1] = 0x0000FFFF | (id << 16);
+ }
+ /* Odd number of IDs exists */
+ else
+ {
+ LPC_CANAF_RAM->mask[cnt1] = (LPC_CANAF_RAM->mask[cnt1] & 0xFFFF0000) | id;
+ }
+ }
+ else
+ {
+ buf0 = LPC_CANAF_RAM->mask[cnt1]; /* Remember current entry */
+ if ((cnt2 & 0x0001) == 0)
+ {
+ /* Insert new mask to even address*/
+ buf1 = (id << 16) | (buf0 >> 16);
+ }
+ else
+ {
+ /* Insert new mask to odd address */
+ buf1 = (buf0 & 0xFFFF0000) | id;
+ }
+ LPC_CANAF_RAM->mask[cnt1] = buf1;/* Insert mask */
+ bound1 = CANAF_FullCAN_cnt >> 1;
+ /* Move all remaining standard mask entries one place up */
+ while (cnt1 < bound1)
+ {
+ cnt1++;
+ buf1 = LPC_CANAF_RAM->mask[cnt1];
+ LPC_CANAF_RAM->mask[cnt1] = (buf1 >> 16) | (buf0 << 16);
+ buf0 = buf1;
+ }
+
+ if ((CANAF_FullCAN_cnt & 0x0001) == 0)
+ {
+ /* Even number of IDs exists */
+ LPC_CANAF_RAM->mask[cnt1] = (LPC_CANAF_RAM->mask[cnt1] & 0xFFFF0000)
+ | (0x0000FFFF);
+ }
+ }
+ }
+ //restruct FulCAN Object Section
+ bound1 = CANAF_FullCAN_cnt - cnt2;
+ cnt1 = total - (CANAF_FullCAN_cnt)*3 + cnt2*3 + 1;
+ buf0 = LPC_CANAF_RAM->mask[cnt1];
+ buf1 = LPC_CANAF_RAM->mask[cnt1+1];
+ buf2 = LPC_CANAF_RAM->mask[cnt1+2];
+ LPC_CANAF_RAM->mask[cnt1]=LPC_CANAF_RAM->mask[cnt1+1]= LPC_CANAF_RAM->mask[cnt1+2]=0x00;
+ cnt1+=3;
+ while(bound1--)
+ {
+ tmp0 = LPC_CANAF_RAM->mask[cnt1];
+ tmp1 = LPC_CANAF_RAM->mask[cnt1+1];
+ tmp2 = LPC_CANAF_RAM->mask[cnt1+2];
+ LPC_CANAF_RAM->mask[cnt1]= buf0;
+ LPC_CANAF_RAM->mask[cnt1+1]= buf1;
+ LPC_CANAF_RAM->mask[cnt1+2]= buf2;
+ buf0 = tmp0;
+ buf1 = tmp1;
+ buf2 = tmp2;
+ cnt1+=3;
+ }
+ CANAF_FullCAN_cnt++;
+ //update address values
+ LPC_CANAF->SFF_sa +=0x04;
+ LPC_CANAF->SFF_GRP_sa +=0x04 ;
+ LPC_CANAF->EFF_sa +=0x04 ;
+ LPC_CANAF->EFF_GRP_sa +=0x04;
+ LPC_CANAF->ENDofTable +=0x04;
+
+ LPC_CANAF->AFMR = 0x04;
+ return CAN_OK;
+}
+
+/********************************************************************//**
+ * @brief Load Group entry into AFLUT
+ * @param[in] CANx: CAN peripheral selected, should be:
+ * - LPC_CAN1: CAN1 peripheral
+ * - LPC_CAN2: CAN2 peripheral
+ * @param[in] lowerID, upperID: lower and upper identifier of entry
+ * @param[in] format: type of ID format, should be:
+ * - STD_ID_FORMAT: Standard ID format (11-bit value)
+ * - EXT_ID_FORMAT: Extended ID format (29-bit value)
+ * @return CAN_ERROR, could be:
+ * - CAN_OK: loading is successful
+ * - CAN_CONFLICT_ID_ERROR: Conflict ID occurs
+ * - CAN_OBJECTS_FULL_ERROR: no more space available
+ *********************************************************************/
+CAN_ERROR CAN_LoadGroupEntry(LPC_CAN_TypeDef* CANx, uint32_t lowerID, \
+ uint32_t upperID, CAN_ID_FORMAT_Type format)
+{
+ uint16_t tmp = 0;
+ uint32_t buf0, buf1, entry1, entry2, LID,UID;
+ int16_t cnt1, bound1, total;
+ //LPC_CANAF_RAM_TypeDef *AFLUTTest = LPC_CANAF_RAM;
+
+ CHECK_PARAM(PARAM_CANx(CANx));
+ CHECK_PARAM(PARAM_ID_FORMAT(format));
+
+ if(lowerID > upperID) return CAN_CONFLICT_ID_ERROR;
+ if(CANx == LPC_CAN1)
+ {
+ tmp = 0;
+ }
+ else
+ {
+ tmp = 1;
+ }
+
+ total =((CANAF_FullCAN_cnt+1)>>1)+ CANAF_FullCAN_cnt*3 +((CANAF_std_cnt + 1) >> 1)+ \
+ CANAF_gstd_cnt + CANAF_ext_cnt + (CANAF_gext_cnt<<1);
+
+ /* Setup Acceptance Filter Configuration
+ Acceptance Filter Mode Register = Off */
+ LPC_CANAF->AFMR = 0x00000001;
+
+/*********Add Group of Standard Identifier Frame Format************/
+ if(format == STD_ID_FORMAT)
+ {
+ if ((total >= 512)){//don't have enough space
+ return CAN_OBJECTS_FULL_ERROR;
+ }
+ lowerID &=0x7FF; //mask ID
+ upperID &=0x7FF;
+ entry1 = (tmp << 29)|(lowerID << 16)|(tmp << 13)|(upperID << 0);
+ cnt1 = ((CANAF_FullCAN_cnt+1)>>1) + ((CANAF_std_cnt + 1) >> 1);
+
+ //if this is the first Group standard ID entry
+ if(CANAF_gstd_cnt == 0)
+ {
+ LPC_CANAF_RAM->mask[cnt1] = entry1;
+ }
+ else
+ {
+ //find the position to add new Group entry
+ bound1 = ((CANAF_FullCAN_cnt+1)>>1) + ((CANAF_std_cnt + 1) >> 1) + CANAF_gstd_cnt;
+ while(cnt1 < bound1)
+ {
+ //compare controller first
+ while((LPC_CANAF_RAM->mask[cnt1] >> 29)< (entry1 >> 29))//increase until meet greater or equal controller
+ cnt1++;
+ buf0 = LPC_CANAF_RAM->mask[cnt1];
+ if((LPC_CANAF_RAM->mask[cnt1] >> 29)> (entry1 >> 29)) //meet greater controller
+ {
+ //add at this position
+ LPC_CANAF_RAM->mask[cnt1] = entry1;
+ break;
+ }
+ else //meet equal controller
+ {
+ LID = (buf0 >> 16)&0x7FF;
+ UID = buf0 & 0x7FF;
+ if (upperID <= LID)
+ {
+ //add new entry before this entry
+ LPC_CANAF_RAM->mask[cnt1] = entry1;
+ break;
+ }
+ else if (lowerID >= UID)
+ {
+ //load next entry to compare
+ cnt1 ++;
+ }
+ else
+ return CAN_CONFLICT_ID_ERROR;
+ }
+ }
+ if(cnt1 >= bound1)
+ {
+ //add new entry at the last position in this list
+ buf0 = LPC_CANAF_RAM->mask[cnt1];
+ LPC_CANAF_RAM->mask[cnt1] = entry1;
+ }
+
+ //remove all remaining entry of this section one place up
+ bound1 = total - cnt1;
+ while(bound1--)
+ {
+ cnt1++;
+ buf1 = LPC_CANAF_RAM->mask[cnt1];
+ LPC_CANAF_RAM->mask[cnt1] = buf0;
+ buf0 = buf1;
+ }
+ }
+ CANAF_gstd_cnt++;
+ //update address values
+ LPC_CANAF->EFF_sa +=0x04 ;
+ LPC_CANAF->EFF_GRP_sa +=0x04;
+ LPC_CANAF->ENDofTable +=0x04;
+ }
+
+
+/*********Add Group of Extended Identifier Frame Format************/
+ else
+ {
+ if ((total >= 511)){//don't have enough space
+ return CAN_OBJECTS_FULL_ERROR;
+ }
+ lowerID &= 0x1FFFFFFF; //mask ID
+ upperID &= 0x1FFFFFFF;
+ entry1 = (tmp << 29)|(lowerID << 0);
+ entry2 = (tmp << 29)|(upperID << 0);
+
+ cnt1 = ((CANAF_FullCAN_cnt+1)>>1) + ((CANAF_std_cnt + 1) >> 1) + CANAF_gstd_cnt + CANAF_ext_cnt;
+ //if this is the first Group standard ID entry
+ if(CANAF_gext_cnt == 0)
+ {
+ LPC_CANAF_RAM->mask[cnt1] = entry1;
+ LPC_CANAF_RAM->mask[cnt1+1] = entry2;
+ }
+ else
+ {
+ //find the position to add new Group entry
+ bound1 = ((CANAF_FullCAN_cnt+1)>>1) + ((CANAF_std_cnt + 1) >> 1) + CANAF_gstd_cnt \
+ + CANAF_ext_cnt + (CANAF_gext_cnt<<1);
+ while(cnt1 < bound1)
+ {
+ while((LPC_CANAF_RAM->mask[cnt1] >>29)< tmp) //increase until meet greater or equal controller
+ cnt1++;
+ buf0 = LPC_CANAF_RAM->mask[cnt1];
+ buf1 = LPC_CANAF_RAM->mask[cnt1+1];
+ if((LPC_CANAF_RAM->mask[cnt1] >> 29)> (entry1 >> 29)) //meet greater controller
+ {
+ //add at this position
+ LPC_CANAF_RAM->mask[cnt1] = entry1;
+ LPC_CANAF_RAM->mask[++cnt1] = entry2;
+ break;
+ }
+ else //meet equal controller
+ {
+ LID = buf0 & 0x1FFFFFFF; //mask ID
+ UID = buf1 & 0x1FFFFFFF;
+ if (upperID <= LID)
+ {
+ //add new entry before this entry
+ LPC_CANAF_RAM->mask[cnt1] = entry1;
+ LPC_CANAF_RAM->mask[++cnt1] = entry2;
+ break;
+ }
+ else if (lowerID >= UID)
+ {
+ //load next entry to compare
+ cnt1 +=2;
+ }
+ else
+ return CAN_CONFLICT_ID_ERROR;
+ }
+ }
+ if(cnt1 >= bound1)
+ {
+ //add new entry at the last position in this list
+ buf0 = LPC_CANAF_RAM->mask[cnt1];
+ buf1 = LPC_CANAF_RAM->mask[cnt1+1];
+ LPC_CANAF_RAM->mask[cnt1] = entry1;
+ LPC_CANAF_RAM->mask[++cnt1] = entry2;
+ }
+ //remove all remaining entry of this section two place up
+ bound1 = total - cnt1 + 1;
+ cnt1++;
+ while(bound1>0)
+ {
+ entry1 = LPC_CANAF_RAM->mask[cnt1];
+ entry2 = LPC_CANAF_RAM->mask[cnt1+1];
+ LPC_CANAF_RAM->mask[cnt1] = buf0;
+ LPC_CANAF_RAM->mask[cnt1+1] = buf1;
+ buf0 = entry1;
+ buf1 = entry2;
+ cnt1 +=2;
+ bound1 -=2;
+ }
+ }
+ CANAF_gext_cnt++;
+ //update address values
+ LPC_CANAF->ENDofTable +=0x08;
+ }
+ LPC_CANAF->AFMR = 0x04;
+ return CAN_OK;
+}
+
+/********************************************************************//**
+ * @brief Remove AFLUT entry (FullCAN entry and Explicit Standard entry)
+ * @param[in] EntryType: the type of entry that want to remove, should be:
+ * - FULLCAN_ENTRY
+ * - EXPLICIT_STANDARD_ENTRY
+ * - GROUP_STANDARD_ENTRY
+ * - EXPLICIT_EXTEND_ENTRY
+ * - GROUP_EXTEND_ENTRY
+ * @param[in] position: the position of this entry in its section
+ * Note: the first position is 0
+ * @return CAN_ERROR, could be:
+ * - CAN_OK: removing is successful
+ * - CAN_ENTRY_NOT_EXIT_ERROR: entry want to remove is not exit
+ *********************************************************************/
+CAN_ERROR CAN_RemoveEntry(AFLUT_ENTRY_Type EntryType, uint16_t position)
+{
+ uint16_t cnt, bound, total;
+ uint32_t buf0, buf1;
+ CHECK_PARAM(PARAM_AFLUT_ENTRY_TYPE(EntryType));
+ CHECK_PARAM(PARAM_POSITION(position));
+
+ /* Setup Acceptance Filter Configuration
+ Acceptance Filter Mode Register = Off */
+ LPC_CANAF->AFMR = 0x00000001;
+ total = ((CANAF_FullCAN_cnt+1)>>1)+((CANAF_std_cnt + 1) >> 1) + \
+ CANAF_gstd_cnt + CANAF_ext_cnt + (CANAF_gext_cnt<<1);
+
+
+/************** Remove FullCAN Entry *************/
+ if(EntryType == FULLCAN_ENTRY)
+ {
+ if((CANAF_FullCAN_cnt==0)||(position >= CANAF_FullCAN_cnt))
+ {
+ return CAN_ENTRY_NOT_EXIT_ERROR;
+ }
+ else
+ {
+ cnt = position >> 1;
+ buf0 = LPC_CANAF_RAM->mask[cnt];
+ bound = (CANAF_FullCAN_cnt - position -1)>>1;
+ if((position & 0x0001) == 0) //event position
+ {
+ while(bound--)
+ {
+ //remove all remaining FullCAN entry one place down
+ buf1 = LPC_CANAF_RAM->mask[cnt+1];
+ LPC_CANAF_RAM->mask[cnt] = (buf1 >> 16) | (buf0 << 16);
+ buf0 = buf1;
+ cnt++;
+ }
+ }
+ else //odd position
+ {
+ while(bound--)
+ {
+ //remove all remaining FullCAN entry one place down
+ buf1 = LPC_CANAF_RAM->mask[cnt+1];
+ LPC_CANAF_RAM->mask[cnt] = (buf0 & 0xFFFF0000)|(buf1 >> 16);
+ LPC_CANAF_RAM->mask[cnt+1] = LPC_CANAF_RAM->mask[cnt+1] << 16;
+ buf0 = buf1<<16;
+ cnt++;
+ }
+ }
+ if((CANAF_FullCAN_cnt & 0x0001) == 0)
+ {
+ if((position & 0x0001)==0)
+ LPC_CANAF_RAM->mask[cnt] = (buf0 << 16) | (0x0000FFFF);
+ else
+ LPC_CANAF_RAM->mask[cnt] = buf0 | 0x0000FFFF;
+ }
+ else
+ {
+ //remove all remaining section one place down
+ cnt = (CANAF_FullCAN_cnt + 1)>>1;
+ bound = total + CANAF_FullCAN_cnt * 3;
+ while(bound>cnt)
+ {
+ LPC_CANAF_RAM->mask[cnt-1] = LPC_CANAF_RAM->mask[cnt];
+ cnt++;
+ }
+ LPC_CANAF_RAM->mask[cnt-1]=0x00;
+ //update address values
+ LPC_CANAF->SFF_sa -=0x04;
+ LPC_CANAF->SFF_GRP_sa -=0x04 ;
+ LPC_CANAF->EFF_sa -=0x04 ;
+ LPC_CANAF->EFF_GRP_sa -=0x04;
+ LPC_CANAF->ENDofTable -=0x04;
+ }
+ CANAF_FullCAN_cnt--;
+
+ //delete its FullCAN Object in the FullCAN Object section
+ //remove all remaining FullCAN Object three place down
+ cnt = total + position * 3;
+ bound = (CANAF_FullCAN_cnt - position + 1) * 3;
+
+ while(bound)
+ {
+ LPC_CANAF_RAM->mask[cnt]=LPC_CANAF_RAM->mask[cnt+3];;
+ LPC_CANAF_RAM->mask[cnt+1]=LPC_CANAF_RAM->mask[cnt+4];
+ LPC_CANAF_RAM->mask[cnt+2]=LPC_CANAF_RAM->mask[cnt+5];
+ bound -=3;
+ cnt +=3;
+ }
+ }
+ }
+
+/************** Remove Explicit Standard ID Entry *************/
+ else if(EntryType == EXPLICIT_STANDARD_ENTRY)
+ {
+ if((CANAF_std_cnt==0)||(position >= CANAF_std_cnt))
+ {
+ return CAN_ENTRY_NOT_EXIT_ERROR;
+ }
+ else
+ {
+ cnt = ((CANAF_FullCAN_cnt+1)>>1)+ (position >> 1);
+ buf0 = LPC_CANAF_RAM->mask[cnt];
+ bound = (CANAF_std_cnt - position - 1)>>1;
+ if((position & 0x0001) == 0) //event position
+ {
+ while(bound--)
+ {
+ //remove all remaining FullCAN entry one place down
+ buf1 = LPC_CANAF_RAM->mask[cnt+1];
+ LPC_CANAF_RAM->mask[cnt] = (buf1 >> 16) | (buf0 << 16);
+ buf0 = buf1;
+ cnt++;
+ }
+ }
+ else //odd position
+ {
+ while(bound--)
+ {
+ //remove all remaining FullCAN entry one place down
+ buf1 = LPC_CANAF_RAM->mask[cnt+1];
+ LPC_CANAF_RAM->mask[cnt] = (buf0 & 0xFFFF0000)|(buf1 >> 16);
+ LPC_CANAF_RAM->mask[cnt+1] = LPC_CANAF_RAM->mask[cnt+1] << 16;
+ buf0 = buf1<<16;
+ cnt++;
+ }
+ }
+ if((CANAF_std_cnt & 0x0001) == 0)
+ {
+ if((position & 0x0001)==0)
+ LPC_CANAF_RAM->mask[cnt] = (buf0 << 16) | (0x0000FFFF);
+ else
+ LPC_CANAF_RAM->mask[cnt] = buf0 | 0x0000FFFF;
+ }
+ else
+ {
+ //remove all remaining section one place down
+ cnt = ((CANAF_FullCAN_cnt + 1)>>1) + ((CANAF_std_cnt + 1) >> 1);
+ bound = total + CANAF_FullCAN_cnt * 3;
+ while(bound>cnt)
+ {
+ LPC_CANAF_RAM->mask[cnt-1] = LPC_CANAF_RAM->mask[cnt];
+ cnt++;
+ }
+ LPC_CANAF_RAM->mask[cnt-1]=0x00;
+ //update address value
+ LPC_CANAF->SFF_GRP_sa -=0x04 ;
+ LPC_CANAF->EFF_sa -=0x04 ;
+ LPC_CANAF->EFF_GRP_sa -=0x04;
+ LPC_CANAF->ENDofTable -=0x04;
+ }
+ CANAF_std_cnt--;
+ }
+ }
+
+/************** Remove Group of Standard ID Entry *************/
+ else if(EntryType == GROUP_STANDARD_ENTRY)
+ {
+ if((CANAF_gstd_cnt==0)||(position >= CANAF_gstd_cnt))
+ {
+ return CAN_ENTRY_NOT_EXIT_ERROR;
+ }
+ else
+ {
+ cnt = ((CANAF_FullCAN_cnt + 1)>>1) + ((CANAF_std_cnt + 1) >> 1)+ position + 1;
+ bound = total + CANAF_FullCAN_cnt * 3;
+ while (cnt<bound)
+ {
+ LPC_CANAF_RAM->mask[cnt-1] = LPC_CANAF_RAM->mask[cnt];
+ cnt++;
+ }
+ LPC_CANAF_RAM->mask[cnt-1]=0x00;
+ }
+ CANAF_gstd_cnt--;
+ //update address value
+ LPC_CANAF->EFF_sa -=0x04;
+ LPC_CANAF->EFF_GRP_sa -=0x04;
+ LPC_CANAF->ENDofTable -=0x04;
+ }
+
+/************** Remove Explicit Extended ID Entry *************/
+ else if(EntryType == EXPLICIT_EXTEND_ENTRY)
+ {
+ if((CANAF_ext_cnt==0)||(position >= CANAF_ext_cnt))
+ {
+ return CAN_ENTRY_NOT_EXIT_ERROR;
+ }
+ else
+ {
+ cnt = ((CANAF_FullCAN_cnt + 1)>>1) + ((CANAF_std_cnt + 1) >> 1)+ CANAF_gstd_cnt + position + 1;
+ bound = total + CANAF_FullCAN_cnt * 3;
+ while (cnt<bound)
+ {
+ LPC_CANAF_RAM->mask[cnt-1] = LPC_CANAF_RAM->mask[cnt];
+ cnt++;
+ }
+ LPC_CANAF_RAM->mask[cnt-1]=0x00;
+ }
+ CANAF_ext_cnt--;
+ LPC_CANAF->EFF_GRP_sa -=0x04;
+ LPC_CANAF->ENDofTable -=0x04;
+ }
+
+/************** Remove Group of Extended ID Entry *************/
+ else
+ {
+ if((CANAF_gext_cnt==0)||(position >= CANAF_gext_cnt))
+ {
+ return CAN_ENTRY_NOT_EXIT_ERROR;
+ }
+ else
+ {
+ cnt = total - (CANAF_gext_cnt<<1) + (position<<1);
+ bound = total + CANAF_FullCAN_cnt * 3;
+ while (cnt<bound)
+ {
+ //remove all remaining entry two place up
+ LPC_CANAF_RAM->mask[cnt] = LPC_CANAF_RAM->mask[cnt+2];
+ LPC_CANAF_RAM->mask[cnt+1] = LPC_CANAF_RAM->mask[cnt+3];
+ cnt+=2;
+ }
+ }
+ CANAF_gext_cnt--;
+ LPC_CANAF->ENDofTable -=0x08;
+ }
+ LPC_CANAF->AFMR = 0x04;
+ return CAN_OK;
+}
+
+/********************************************************************//**
+ * @brief Send message data
+ * @param[in] CANx pointer to LPC_CAN_TypeDef, should be:
+ * - LPC_CAN1: CAN1 peripheral
+ * - LPC_CAN2: CAN2 peripheral
+ * @param[in] CAN_Msg point to the CAN_MSG_Type Structure, it contains message
+ * information such as: ID, DLC, RTR, ID Format
+ * @return Status:
+ * - SUCCESS: send message successfully
+ * - ERROR: send message unsuccessfully
+ *********************************************************************/
+Status CAN_SendMsg (LPC_CAN_TypeDef *CANx, CAN_MSG_Type *CAN_Msg)
+{
+ uint32_t data;
+ CHECK_PARAM(PARAM_CANx(CANx));
+ CHECK_PARAM(PARAM_ID_FORMAT(CAN_Msg->format));
+ if(CAN_Msg->format==STD_ID_FORMAT)
+ {
+ CHECK_PARAM(PARAM_ID_11(CAN_Msg->id));
+ }
+ else
+ {
+ CHECK_PARAM(PARAM_ID_29(CAN_Msg->id));
+ }
+ CHECK_PARAM(PARAM_DLC(CAN_Msg->len));
+ CHECK_PARAM(PARAM_FRAME_TYPE(CAN_Msg->type));
+
+ //Check status of Transmit Buffer 1
+ if (CANx->SR & (1<<2))
+ {
+ /* Transmit Channel 1 is available */
+ /* Write frame informations and frame data into its CANxTFI1,
+ * CANxTID1, CANxTDA1, CANxTDB1 register */
+ CANx->TFI1 &= ~0x000F0000;
+ CANx->TFI1 |= (CAN_Msg->len)<<16;
+ if(CAN_Msg->type == REMOTE_FRAME)
+ {
+ CANx->TFI1 |= (1<<30); //set bit RTR
+ }
+ else
+ {
+ CANx->TFI1 &= ~(1<<30);
+ }
+ if(CAN_Msg->format == EXT_ID_FORMAT)
+ {
+ CANx->TFI1 |= (0x80000000); //set bit FF
+ }
+ else
+ {
+ CANx->TFI1 &= ~(0x80000000);
+ }
+
+ /* Write CAN ID*/
+ CANx->TID1 = CAN_Msg->id;
+
+ /*Write first 4 data bytes*/
+ data = (CAN_Msg->dataA[0])|(((CAN_Msg->dataA[1]))<<8)|((CAN_Msg->dataA[2])<<16)|((CAN_Msg->dataA[3])<<24);
+ CANx->TDA1 = data;
+
+ /*Write second 4 data bytes*/
+ data = (CAN_Msg->dataB[0])|(((CAN_Msg->dataB[1]))<<8)|((CAN_Msg->dataB[2])<<16)|((CAN_Msg->dataB[3])<<24);
+ CANx->TDB1 = data;
+
+ /*Write transmission request*/
+ CANx->CMR = 0x21;
+ return SUCCESS;
+ }
+ //check status of Transmit Buffer 2
+ else if(CANx->SR & (1<<10))
+ {
+ /* Transmit Channel 2 is available */
+ /* Write frame informations and frame data into its CANxTFI2,
+ * CANxTID2, CANxTDA2, CANxTDB2 register */
+ CANx->TFI2 &= ~0x000F0000;
+ CANx->TFI2 |= (CAN_Msg->len)<<16;
+ if(CAN_Msg->type == REMOTE_FRAME)
+ {
+ CANx->TFI2 |= (1<<30); //set bit RTR
+ }
+ else
+ {
+ CANx->TFI2 &= ~(1<<30);
+ }
+ if(CAN_Msg->format == EXT_ID_FORMAT)
+ {
+ CANx->TFI2 |= (0x80000000); //set bit FF
+ }
+ else
+ {
+ CANx->TFI2 &= ~(0x80000000);
+ }
+
+ /* Write CAN ID*/
+ CANx->TID2 = CAN_Msg->id;
+
+ /*Write first 4 data bytes*/
+ data = (CAN_Msg->dataA[0])|(((CAN_Msg->dataA[1]))<<8)|((CAN_Msg->dataA[2])<<16)|((CAN_Msg->dataA[3])<<24);
+ CANx->TDA2 = data;
+
+ /*Write second 4 data bytes*/
+ data = (CAN_Msg->dataB[0])|(((CAN_Msg->dataB[1]))<<8)|((CAN_Msg->dataB[2])<<16)|((CAN_Msg->dataB[3])<<24);
+ CANx->TDB2 = data;
+
+ /*Write transmission request*/
+ CANx->CMR = 0x41;
+ return SUCCESS;
+ }
+ //check status of Transmit Buffer 3
+ else if (CANx->SR & (1<<18))
+ {
+ /* Transmit Channel 3 is available */
+ /* Write frame informations and frame data into its CANxTFI3,
+ * CANxTID3, CANxTDA3, CANxTDB3 register */
+ CANx->TFI3 &= ~0x000F0000;
+ CANx->TFI3 |= (CAN_Msg->len)<<16;
+ if(CAN_Msg->type == REMOTE_FRAME)
+ {
+ CANx->TFI3 |= (1<<30); //set bit RTR
+ }
+ else
+ {
+ CANx->TFI3 &= ~(1<<30);
+ }
+ if(CAN_Msg->format == EXT_ID_FORMAT)
+ {
+ CANx->TFI3 |= (0x80000000); //set bit FF
+ }
+ else
+ {
+ CANx->TFI3 &= ~(0x80000000);
+ }
+
+ /* Write CAN ID*/
+ CANx->TID3 = CAN_Msg->id;
+
+ /*Write first 4 data bytes*/
+ data = (CAN_Msg->dataA[0])|(((CAN_Msg->dataA[1]))<<8)|((CAN_Msg->dataA[2])<<16)|((CAN_Msg->dataA[3])<<24);
+ CANx->TDA3 = data;
+
+ /*Write second 4 data bytes*/
+ data = (CAN_Msg->dataB[0])|(((CAN_Msg->dataB[1]))<<8)|((CAN_Msg->dataB[2])<<16)|((CAN_Msg->dataB[3])<<24);
+ CANx->TDB3 = data;
+
+ /*Write transmission request*/
+ CANx->CMR = 0x81;
+ return SUCCESS;
+ }
+ else
+ {
+ return ERROR;
+ }
+}
+
+/********************************************************************//**
+ * @brief Receive message data
+ * @param[in] CANx pointer to LPC_CAN_TypeDef, should be:
+ * - LPC_CAN1: CAN1 peripheral
+ * - LPC_CAN2: CAN2 peripheral
+ * @param[in] CAN_Msg point to the CAN_MSG_Type Struct, it will contain received
+ * message information such as: ID, DLC, RTR, ID Format
+ * @return Status:
+ * - SUCCESS: receive message successfully
+ * - ERROR: receive message unsuccessfully
+ *********************************************************************/
+Status CAN_ReceiveMsg (LPC_CAN_TypeDef *CANx, CAN_MSG_Type *CAN_Msg)
+{
+ uint32_t data;
+
+ CHECK_PARAM(PARAM_CANx(CANx));
+
+ //check status of Receive Buffer
+ if((CANx->SR &0x00000001))
+ {
+ /* Receive message is available */
+ /* Read frame informations */
+ CAN_Msg->format = (uint8_t)(((CANx->RFS) & 0x80000000)>>31);
+ CAN_Msg->type = (uint8_t)(((CANx->RFS) & 0x40000000)>>30);
+ CAN_Msg->len = (uint8_t)(((CANx->RFS) & 0x000F0000)>>16);
+
+
+ /* Read CAN message identifier */
+ CAN_Msg->id = CANx->RID;
+
+ /* Read the data if received message was DATA FRAME */
+ if (CAN_Msg->type == DATA_FRAME)
+ {
+ /* Read first 4 data bytes */
+ data = CANx->RDA;
+ *((uint8_t *) &CAN_Msg->dataA[0])= data & 0x000000FF;
+ *((uint8_t *) &CAN_Msg->dataA[1])= (data & 0x0000FF00)>>8;;
+ *((uint8_t *) &CAN_Msg->dataA[2])= (data & 0x00FF0000)>>16;
+ *((uint8_t *) &CAN_Msg->dataA[3])= (data & 0xFF000000)>>24;
+
+ /* Read second 4 data bytes */
+ data = CANx->RDB;
+ *((uint8_t *) &CAN_Msg->dataB[0])= data & 0x000000FF;
+ *((uint8_t *) &CAN_Msg->dataB[1])= (data & 0x0000FF00)>>8;
+ *((uint8_t *) &CAN_Msg->dataB[2])= (data & 0x00FF0000)>>16;
+ *((uint8_t *) &CAN_Msg->dataB[3])= (data & 0xFF000000)>>24;
+
+ /*release receive buffer*/
+ CANx->CMR = 0x04;
+ }
+ else
+ {
+ /* Received Frame is a Remote Frame, not have data, we just receive
+ * message information only */
+ CANx->CMR = 0x04; /*release receive buffer*/
+ return SUCCESS;
+ }
+ }
+ else
+ {
+ // no receive message available
+ return ERROR;
+ }
+ return SUCCESS;
+}
+
+/********************************************************************//**
+ * @brief Receive FullCAN Object
+ * @param[in] CANAFx: CAN Acceptance Filter register, should be: LPC_CANAF
+ * @param[in] CAN_Msg point to the CAN_MSG_Type Struct, it will contain received
+ * message information such as: ID, DLC, RTR, ID Format
+ * @return CAN_ERROR, could be:
+ * - CAN_FULL_OBJ_NOT_RCV: FullCAN Object is not be received
+ * - CAN_OK: Received FullCAN Object successful
+ *
+ *********************************************************************/
+CAN_ERROR FCAN_ReadObj (LPC_CANAF_TypeDef* CANAFx, CAN_MSG_Type *CAN_Msg)
+{
+ uint32_t *pSrc, data;
+ uint32_t interrut_word, msg_idx, test_bit, head_idx, tail_idx;
+
+ CHECK_PARAM(PARAM_CANAFx(CANAFx));
+
+ interrut_word = 0;
+
+ if (LPC_CANAF->FCANIC0 != 0)
+ {
+ interrut_word = LPC_CANAF->FCANIC0;
+ head_idx = 0;
+ tail_idx = 31;
+ }
+ else if (LPC_CANAF->FCANIC1 != 0)
+ {
+ interrut_word = LPC_CANAF->FCANIC1;
+ head_idx = 32;
+ tail_idx = 63;
+ }
+
+ if (interrut_word != 0)
+ {
+ /* Detect for interrupt pending */
+ msg_idx = 0;
+ for (msg_idx = head_idx; msg_idx <= tail_idx; msg_idx++)
+ {
+ test_bit = interrut_word & 0x1;
+ interrut_word = interrut_word >> 1;
+
+ if (test_bit)
+ {
+ pSrc = (uint32_t *) (LPC_CANAF->ENDofTable + LPC_CANAF_RAM_BASE + msg_idx * 12);
+
+ /* Has been finished updating the content */
+ if ((*pSrc & 0x03000000L) == 0x03000000L)
+ {
+ /*clear semaphore*/
+ *pSrc &= 0xFCFFFFFF;
+
+ /*Set to DatA*/
+ pSrc++;
+ /* Copy to dest buf */
+ data = *pSrc;
+ *((uint8_t *) &CAN_Msg->dataA[0])= data & 0x000000FF;
+ *((uint8_t *) &CAN_Msg->dataA[1])= (data & 0x0000FF00)>>8;
+ *((uint8_t *) &CAN_Msg->dataA[2])= (data & 0x00FF0000)>>16;
+ *((uint8_t *) &CAN_Msg->dataA[3])= (data & 0xFF000000)>>24;
+
+ /*Set to DatB*/
+ pSrc++;
+ /* Copy to dest buf */
+ data = *pSrc;
+ *((uint8_t *) &CAN_Msg->dataB[0])= data & 0x000000FF;
+ *((uint8_t *) &CAN_Msg->dataB[1])= (data & 0x0000FF00)>>8;
+ *((uint8_t *) &CAN_Msg->dataB[2])= (data & 0x00FF0000)>>16;
+ *((uint8_t *) &CAN_Msg->dataB[3])= (data & 0xFF000000)>>24;
+ /*Back to Dat1*/
+ pSrc -= 2;
+
+ CAN_Msg->id = *pSrc & 0x7FF;
+ CAN_Msg->len = (uint8_t) (*pSrc >> 16) & 0x0F;
+ CAN_Msg->format = 0; //FullCAN Object ID always is 11-bit value
+ CAN_Msg->type = (uint8_t)(*pSrc >> 30) &0x01;
+ /*Re-read semaphore*/
+ if ((*pSrc & 0x03000000L) == 0)
+ {
+ return CAN_OK;
+ }
+ }
+ }
+ }
+ }
+ return CAN_FULL_OBJ_NOT_RCV;
+}
+/********************************************************************//**
+ * @brief Get CAN Control Status
+ * @param[in] CANx pointer to LPC_CAN_TypeDef, should be:
+ * - LPC_CAN1: CAN1 peripheral
+ * - LPC_CAN2: CAN2 peripheral
+ * @param[in] arg: type of CAN status to get from CAN status register
+ * Should be:
+ * - CANCTRL_GLOBAL_STS: CAN Global Status
+ * - CANCTRL_INT_CAP: CAN Interrupt and Capture
+ * - CANCTRL_ERR_WRN: CAN Error Warning Limit
+ * - CANCTRL_STS: CAN Control Status
+ * @return Current Control Status that you want to get value
+ *********************************************************************/
+uint32_t CAN_GetCTRLStatus (LPC_CAN_TypeDef* CANx, CAN_CTRL_STS_Type arg)
+{
+ CHECK_PARAM(PARAM_CANx(CANx));
+ CHECK_PARAM(PARAM_CTRL_STS_TYPE(arg));
+
+ switch (arg)
+ {
+ case CANCTRL_GLOBAL_STS:
+ return CANx->GSR;
+
+ case CANCTRL_INT_CAP:
+ return CANx->ICR;
+
+ case CANCTRL_ERR_WRN:
+ return CANx->EWL;
+
+ default: // CANCTRL_STS
+ return CANx->SR;
+ }
+}
+/********************************************************************//**
+ * @brief Get CAN Central Status
+ * @param[in] CANCRx point to LPC_CANCR_TypeDef, should be: LPC_CANCR
+ * @param[in] arg: type of CAN status to get from CAN Central status register
+ * Should be:
+ * - CANCR_TX_STS: Central CAN Tx Status
+ * - CANCR_RX_STS: Central CAN Rx Status
+ * - CANCR_MS: Central CAN Miscellaneous Status
+ * @return Current Central Status that you want to get value
+ *********************************************************************/
+uint32_t CAN_GetCRStatus (LPC_CANCR_TypeDef* CANCRx, CAN_CR_STS_Type arg)
+{
+ CHECK_PARAM(PARAM_CANCRx(CANCRx));
+ CHECK_PARAM(PARAM_CR_STS_TYPE(arg));
+
+ switch (arg)
+ {
+ case CANCR_TX_STS:
+ return CANCRx->CANTxSR;
+
+ case CANCR_RX_STS:
+ return CANCRx->CANRxSR;
+
+ default: // CANCR_MS
+ return CANCRx->CANMSR;
+ }
+}
+/********************************************************************//**
+ * @brief Enable/Disable CAN Interrupt
+ * @param[in] CANx pointer to LPC_CAN_TypeDef, should be:
+ * - LPC_CAN1: CAN1 peripheral
+ * - LPC_CAN2: CAN2 peripheral
+ * @param[in] arg: type of CAN interrupt that you want to enable/disable
+ * Should be:
+ * - CANINT_RIE: CAN Receiver Interrupt Enable
+ * - CANINT_TIE1: CAN Transmit Interrupt Enable
+ * - CANINT_EIE: CAN Error Warning Interrupt Enable
+ * - CANINT_DOIE: CAN Data Overrun Interrupt Enable
+ * - CANINT_WUIE: CAN Wake-Up Interrupt Enable
+ * - CANINT_EPIE: CAN Error Passive Interrupt Enable
+ * - CANINT_ALIE: CAN Arbitration Lost Interrupt Enable
+ * - CANINT_BEIE: CAN Bus Error Interrupt Enable
+ * - CANINT_IDIE: CAN ID Ready Interrupt Enable
+ * - CANINT_TIE2: CAN Transmit Interrupt Enable for Buffer2
+ * - CANINT_TIE3: CAN Transmit Interrupt Enable for Buffer3
+ * - CANINT_FCE: FullCAN Interrupt Enable
+ * @param[in] NewState: New state of this function, should be:
+ * - ENABLE
+ * - DISABLE
+ * @return none
+ *********************************************************************/
+void CAN_IRQCmd (LPC_CAN_TypeDef* CANx, CAN_INT_EN_Type arg, FunctionalState NewState)
+{
+ CHECK_PARAM(PARAM_CANx(CANx));
+ CHECK_PARAM(PARAM_INT_EN_TYPE(arg));
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
+
+ if(NewState == ENABLE)
+ {
+ if(arg==CANINT_FCE)
+ {
+ LPC_CANAF->AFMR = 0x01;
+ LPC_CANAF->FCANIE = 0x01;
+ LPC_CANAF->AFMR = 0x04;
+ }
+ else
+ CANx->IER |= (1 << arg);
+ }
+ else
+ {
+ if(arg==CANINT_FCE){
+ LPC_CANAF->AFMR = 0x01;
+ LPC_CANAF->FCANIE = 0x01;
+ LPC_CANAF->AFMR = 0x00;
+ }
+ else
+ CANx->IER &= ~(1 << arg);
+ }
+}
+
+/********************************************************************//**
+ * @brief Setting Acceptance Filter mode
+ * @param[in] CANAFx point to LPC_CANAF_TypeDef object, should be: LPC_CANAF
+ * @param[in] AFMode: type of AF mode that you want to set, should be:
+ * - CAN_Normal: Normal mode
+ * - CAN_AccOff: Acceptance Filter Off Mode
+ * - CAN_AccBP: Acceptance Fileter Bypass Mode
+ * - CAN_eFCAN: FullCAN Mode Enhancement
+ * @return none
+ *********************************************************************/
+void CAN_SetAFMode (LPC_CANAF_TypeDef* CANAFx, CAN_AFMODE_Type AFMode)
+{
+ CHECK_PARAM(PARAM_CANAFx(CANAFx));
+ CHECK_PARAM(PARAM_AFMODE_TYPE(AFMode));
+
+ switch(AFMode)
+ {
+ case CAN_Normal:
+ CANAFx->AFMR = 0x00;
+ break;
+ case CAN_AccOff:
+ CANAFx->AFMR = 0x01;
+ break;
+ case CAN_AccBP:
+ CANAFx->AFMR = 0x02;
+ break;
+ case CAN_eFCAN:
+ CANAFx->AFMR = 0x04;
+ break;
+ }
+}
+
+/********************************************************************//**
+ * @brief Enable/Disable CAN Mode
+ * @param[in] CANx pointer to LPC_CAN_TypeDef, should be:
+ * - LPC_CAN1: CAN1 peripheral
+ * - LPC_CAN2: CAN2 peripheral
+ * @param[in] mode: type of CAN mode that you want to enable/disable, should be:
+ * - CAN_OPERATING_MODE: Normal Operating Mode
+ * - CAN_RESET_MODE: Reset Mode
+ * - CAN_LISTENONLY_MODE: Listen Only Mode
+ * - CAN_SELFTEST_MODE: Self Test Mode
+ * - CAN_TXPRIORITY_MODE: Transmit Priority Mode
+ * - CAN_SLEEP_MODE: Sleep Mode
+ * - CAN_RXPOLARITY_MODE: Receive Polarity Mode
+ * - CAN_TEST_MODE: Test Mode
+ * @param[in] NewState: New State of this function, should be:
+ * - ENABLE
+ * - DISABLE
+ * @return none
+ *********************************************************************/
+void CAN_ModeConfig(LPC_CAN_TypeDef* CANx, CAN_MODE_Type mode, FunctionalState NewState)
+{
+ CHECK_PARAM(PARAM_CANx(CANx));
+ CHECK_PARAM(PARAM_MODE_TYPE(mode));
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
+
+ switch(mode)
+ {
+ case CAN_OPERATING_MODE:
+ CANx->MOD = 0x00;
+ break;
+ case CAN_RESET_MODE:
+ if(NewState == ENABLE)
+ CANx->MOD |=CAN_MOD_RM;
+ else
+ CANx->MOD &= ~CAN_MOD_RM;
+ break;
+ case CAN_LISTENONLY_MODE:
+ CANx->MOD |=CAN_MOD_RM;//Enter Reset mode
+ if(NewState == ENABLE)
+ CANx->MOD |=CAN_MOD_LOM;
+ else
+ CANx->MOD &=~CAN_MOD_LOM;
+ CANx->MOD &=~CAN_MOD_RM;//Release Reset mode
+ break;
+ case CAN_SELFTEST_MODE:
+ CANx->MOD |=CAN_MOD_RM;//Enter Reset mode
+ if(NewState == ENABLE)
+ CANx->MOD |=CAN_MOD_STM;
+ else
+ CANx->MOD &=~CAN_MOD_STM;
+ CANx->MOD &=~CAN_MOD_RM;//Release Reset mode
+ break;
+ case CAN_TXPRIORITY_MODE:
+ if(NewState == ENABLE)
+ CANx->MOD |=CAN_MOD_TPM;
+ else
+ CANx->MOD &=~CAN_MOD_TPM;
+ break;
+ case CAN_SLEEP_MODE:
+ if(NewState == ENABLE)
+ CANx->MOD |=CAN_MOD_SM;
+ else
+ CANx->MOD &=~CAN_MOD_SM;
+ break;
+ case CAN_RXPOLARITY_MODE:
+ if(NewState == ENABLE)
+ CANx->MOD |=CAN_MOD_RPM;
+ else
+ CANx->MOD &=~CAN_MOD_RPM;
+ break;
+ case CAN_TEST_MODE:
+ if(NewState == ENABLE)
+ CANx->MOD |=CAN_MOD_TM;
+ else
+ CANx->MOD &=~CAN_MOD_TM;
+ break;
+ }
+}
+/*********************************************************************//**
+ * @brief Set CAN command request
+ * @param[in] CANx point to CAN peripheral selected, should be:
+ * - LPC_CAN1: CAN1 peripheral
+ * - LPC_CAN2: CAN2 peripheral
+ * @param[in] CMRType command request type, should be:
+ * - CAN_CMR_TR: Transmission request
+ * - CAN_CMR_AT: Abort Transmission request
+ * - CAN_CMR_RRB: Release Receive Buffer request
+ * - CAN_CMR_CDO: Clear Data Overrun request
+ * - CAN_CMR_SRR: Self Reception request
+ * - CAN_CMR_STB1: Select Tx Buffer 1 request
+ * - CAN_CMR_STB2: Select Tx Buffer 2 request
+ * - CAN_CMR_STB3: Select Tx Buffer 3 request
+ * @return CANICR (CAN interrupt and Capture register) value
+ **********************************************************************/
+void CAN_SetCommand(LPC_CAN_TypeDef* CANx, uint32_t CMRType)
+{
+ CHECK_PARAM(PARAM_CANx(CANx));
+ CANx->CMR |= CMRType;
+}
+
+/*********************************************************************//**
+ * @brief Get CAN interrupt status
+ * @param[in] CANx point to CAN peripheral selected, should be:
+ * - LPC_CAN1: CAN1 peripheral
+ * - LPC_CAN2: CAN2 peripheral
+ * @return CANICR (CAN interrupt and Capture register) value
+ **********************************************************************/
+uint32_t CAN_IntGetStatus(LPC_CAN_TypeDef* CANx)
+{
+ CHECK_PARAM(PARAM_CANx(CANx));
+ return CANx->ICR;
+}
+
+/*********************************************************************//**
+ * @brief Check if FullCAN interrupt enable or not
+ * @param[in] CANAFx point to LPC_CANAF_TypeDef object, should be: LPC_CANAF
+ * @return IntStatus, could be:
+ * - SET: if FullCAN interrupt is enable
+ * - RESET: if FullCAN interrupt is disable
+ **********************************************************************/
+IntStatus CAN_FullCANIntGetStatus (LPC_CANAF_TypeDef* CANAFx)
+{
+ CHECK_PARAM( PARAM_CANAFx(CANAFx));
+ if (CANAFx->FCANIE)
+ return SET;
+ return RESET;
+}
+
+/*********************************************************************//**
+ * @brief Get value of FullCAN interrupt and capture register
+ * @param[in] CANAFx point to LPC_CANAF_TypeDef object, should be: LPC_CANAF
+ * @param[in] type: FullCAN IC type, should be:
+ * - FULLCAN_IC0: FullCAN Interrupt Capture 0
+ * - FULLCAN_IC1: FullCAN Interrupt Capture 1
+ * @return FCANIC0 or FCANIC1 (FullCAN interrupt and Capture register) value
+ **********************************************************************/
+uint32_t CAN_FullCANPendGetStatus(LPC_CANAF_TypeDef* CANAFx, FullCAN_IC_Type type)
+{
+ CHECK_PARAM(PARAM_CANAFx(CANAFx));
+ CHECK_PARAM( PARAM_FULLCAN_IC(type));
+ if (type == FULLCAN_IC0)
+ return CANAFx->FCANIC0;
+ return CANAFx->FCANIC1;
+}
+/* End of Public Variables ---------------------------------------------------------- */
+/**
+ * @}
+ */
+
+#endif /* _CAN */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/src/shared/cmsis/Drivers/source/lpc17xx_clkpwr.c b/src/shared/cmsis/Drivers/source/lpc17xx_clkpwr.c
@@ -0,0 +1,350 @@
+/**********************************************************************
+* $Id$ lpc17xx_clkpwr.c 2010-06-18
+*//**
+* @file lpc17xx_clkpwr.c
+* @brief Contains all functions support for Clock and Power Control
+* firmware library on LPC17xx
+* @version 3.0
+* @date 18. June. 2010
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2010, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @addtogroup CLKPWR
+ * @{
+ */
+
+/* Includes ------------------------------------------------------------------- */
+#include "lpc17xx_clkpwr.h"
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @addtogroup CLKPWR_Public_Functions
+ * @{
+ */
+
+/*********************************************************************//**
+ * @brief Set value of each Peripheral Clock Selection
+ * @param[in] ClkType Peripheral Clock Selection of each type,
+ * should be one of the following:
+ * - CLKPWR_PCLKSEL_WDT : WDT
+ - CLKPWR_PCLKSEL_TIMER0 : Timer 0
+ - CLKPWR_PCLKSEL_TIMER1 : Timer 1
+ - CLKPWR_PCLKSEL_UART0 : UART 0
+ - CLKPWR_PCLKSEL_UART1 : UART 1
+ - CLKPWR_PCLKSEL_PWM1 : PWM 1
+ - CLKPWR_PCLKSEL_I2C0 : I2C 0
+ - CLKPWR_PCLKSEL_SPI : SPI
+ - CLKPWR_PCLKSEL_SSP1 : SSP 1
+ - CLKPWR_PCLKSEL_DAC : DAC
+ - CLKPWR_PCLKSEL_ADC : ADC
+ - CLKPWR_PCLKSEL_CAN1 : CAN 1
+ - CLKPWR_PCLKSEL_CAN2 : CAN 2
+ - CLKPWR_PCLKSEL_ACF : ACF
+ - CLKPWR_PCLKSEL_QEI : QEI
+ - CLKPWR_PCLKSEL_PCB : PCB
+ - CLKPWR_PCLKSEL_I2C1 : I2C 1
+ - CLKPWR_PCLKSEL_SSP0 : SSP 0
+ - CLKPWR_PCLKSEL_TIMER2 : Timer 2
+ - CLKPWR_PCLKSEL_TIMER3 : Timer 3
+ - CLKPWR_PCLKSEL_UART2 : UART 2
+ - CLKPWR_PCLKSEL_UART3 : UART 3
+ - CLKPWR_PCLKSEL_I2C2 : I2C 2
+ - CLKPWR_PCLKSEL_I2S : I2S
+ - CLKPWR_PCLKSEL_RIT : RIT
+ - CLKPWR_PCLKSEL_SYSCON : SYSCON
+ - CLKPWR_PCLKSEL_MC : MC
+
+ * @param[in] DivVal Value of divider, should be:
+ * - CLKPWR_PCLKSEL_CCLK_DIV_4 : PCLK_peripheral = CCLK/4
+ * - CLKPWR_PCLKSEL_CCLK_DIV_1 : PCLK_peripheral = CCLK/1
+ * - CLKPWR_PCLKSEL_CCLK_DIV_2 : PCLK_peripheral = CCLK/2
+ *
+ * @return none
+ **********************************************************************/
+void CLKPWR_SetPCLKDiv (uint32_t ClkType, uint32_t DivVal)
+{
+ uint32_t bitpos;
+
+ bitpos = (ClkType < 32) ? (ClkType) : (ClkType - 32);
+
+ /* PCLKSEL0 selected */
+ if (ClkType < 32)
+ {
+ /* Clear two bit at bit position */
+ LPC_SC->PCLKSEL0 &= (~(CLKPWR_PCLKSEL_BITMASK(bitpos)));
+
+ /* Set two selected bit */
+ LPC_SC->PCLKSEL0 |= (CLKPWR_PCLKSEL_SET(bitpos, DivVal));
+ }
+ /* PCLKSEL1 selected */
+ else
+ {
+ /* Clear two bit at bit position */
+ LPC_SC->PCLKSEL1 &= ~(CLKPWR_PCLKSEL_BITMASK(bitpos));
+
+ /* Set two selected bit */
+ LPC_SC->PCLKSEL1 |= (CLKPWR_PCLKSEL_SET(bitpos, DivVal));
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Get current value of each Peripheral Clock Selection
+ * @param[in] ClkType Peripheral Clock Selection of each type,
+ * should be one of the following:
+ * - CLKPWR_PCLKSEL_WDT : WDT
+ - CLKPWR_PCLKSEL_TIMER0 : Timer 0
+ - CLKPWR_PCLKSEL_TIMER1 : Timer 1
+ - CLKPWR_PCLKSEL_UART0 : UART 0
+ - CLKPWR_PCLKSEL_UART1 : UART 1
+ - CLKPWR_PCLKSEL_PWM1 : PWM 1
+ - CLKPWR_PCLKSEL_I2C0 : I2C 0
+ - CLKPWR_PCLKSEL_SPI : SPI
+ - CLKPWR_PCLKSEL_SSP1 : SSP 1
+ - CLKPWR_PCLKSEL_DAC : DAC
+ - CLKPWR_PCLKSEL_ADC : ADC
+ - CLKPWR_PCLKSEL_CAN1 : CAN 1
+ - CLKPWR_PCLKSEL_CAN2 : CAN 2
+ - CLKPWR_PCLKSEL_ACF : ACF
+ - CLKPWR_PCLKSEL_QEI : QEI
+ - CLKPWR_PCLKSEL_PCB : PCB
+ - CLKPWR_PCLKSEL_I2C1 : I2C 1
+ - CLKPWR_PCLKSEL_SSP0 : SSP 0
+ - CLKPWR_PCLKSEL_TIMER2 : Timer 2
+ - CLKPWR_PCLKSEL_TIMER3 : Timer 3
+ - CLKPWR_PCLKSEL_UART2 : UART 2
+ - CLKPWR_PCLKSEL_UART3 : UART 3
+ - CLKPWR_PCLKSEL_I2C2 : I2C 2
+ - CLKPWR_PCLKSEL_I2S : I2S
+ - CLKPWR_PCLKSEL_RIT : RIT
+ - CLKPWR_PCLKSEL_SYSCON : SYSCON
+ - CLKPWR_PCLKSEL_MC : MC
+
+ * @return Value of Selected Peripheral Clock Selection
+ **********************************************************************/
+uint32_t CLKPWR_GetPCLKSEL (uint32_t ClkType)
+{
+ uint32_t bitpos, retval;
+
+ if (ClkType < 32)
+ {
+ bitpos = ClkType;
+ retval = LPC_SC->PCLKSEL0;
+ }
+ else
+ {
+ bitpos = ClkType - 32;
+ retval = LPC_SC->PCLKSEL1;
+ }
+
+ retval = CLKPWR_PCLKSEL_GET(bitpos, retval);
+ return retval;
+}
+
+
+
+/*********************************************************************//**
+ * @brief Get current value of each Peripheral Clock
+ * @param[in] ClkType Peripheral Clock Selection of each type,
+ * should be one of the following:
+ * - CLKPWR_PCLKSEL_WDT : WDT
+ - CLKPWR_PCLKSEL_TIMER0 : Timer 0
+ - CLKPWR_PCLKSEL_TIMER1 : Timer 1
+ - CLKPWR_PCLKSEL_UART0 : UART 0
+ - CLKPWR_PCLKSEL_UART1 : UART 1
+ - CLKPWR_PCLKSEL_PWM1 : PWM 1
+ - CLKPWR_PCLKSEL_I2C0 : I2C 0
+ - CLKPWR_PCLKSEL_SPI : SPI
+ - CLKPWR_PCLKSEL_SSP1 : SSP 1
+ - CLKPWR_PCLKSEL_DAC : DAC
+ - CLKPWR_PCLKSEL_ADC : ADC
+ - CLKPWR_PCLKSEL_CAN1 : CAN 1
+ - CLKPWR_PCLKSEL_CAN2 : CAN 2
+ - CLKPWR_PCLKSEL_ACF : ACF
+ - CLKPWR_PCLKSEL_QEI : QEI
+ - CLKPWR_PCLKSEL_PCB : PCB
+ - CLKPWR_PCLKSEL_I2C1 : I2C 1
+ - CLKPWR_PCLKSEL_SSP0 : SSP 0
+ - CLKPWR_PCLKSEL_TIMER2 : Timer 2
+ - CLKPWR_PCLKSEL_TIMER3 : Timer 3
+ - CLKPWR_PCLKSEL_UART2 : UART 2
+ - CLKPWR_PCLKSEL_UART3 : UART 3
+ - CLKPWR_PCLKSEL_I2C2 : I2C 2
+ - CLKPWR_PCLKSEL_I2S : I2S
+ - CLKPWR_PCLKSEL_RIT : RIT
+ - CLKPWR_PCLKSEL_SYSCON : SYSCON
+ - CLKPWR_PCLKSEL_MC : MC
+
+ * @return Value of Selected Peripheral Clock
+ **********************************************************************/
+uint32_t CLKPWR_GetPCLK (uint32_t ClkType)
+{
+ uint32_t retval, div;
+
+ retval = SystemCoreClock;
+ div = CLKPWR_GetPCLKSEL(ClkType);
+
+ switch (div)
+ {
+ case 0:
+ div = 4;
+ break;
+
+ case 1:
+ div = 1;
+ break;
+
+ case 2:
+ div = 2;
+ break;
+
+ case 3:
+ div = 8;
+ break;
+ }
+ retval /= div;
+
+ return retval;
+}
+
+
+
+/*********************************************************************//**
+ * @brief Configure power supply for each peripheral according to NewState
+ * @param[in] PPType Type of peripheral used to enable power,
+ * should be one of the following:
+ * - CLKPWR_PCONP_PCTIM0 : Timer 0
+ - CLKPWR_PCONP_PCTIM1 : Timer 1
+ - CLKPWR_PCONP_PCUART0 : UART 0
+ - CLKPWR_PCONP_PCUART1 : UART 1
+ - CLKPWR_PCONP_PCPWM1 : PWM 1
+ - CLKPWR_PCONP_PCI2C0 : I2C 0
+ - CLKPWR_PCONP_PCSPI : SPI
+ - CLKPWR_PCONP_PCRTC : RTC
+ - CLKPWR_PCONP_PCSSP1 : SSP 1
+ - CLKPWR_PCONP_PCAD : ADC
+ - CLKPWR_PCONP_PCAN1 : CAN 1
+ - CLKPWR_PCONP_PCAN2 : CAN 2
+ - CLKPWR_PCONP_PCGPIO : GPIO
+ - CLKPWR_PCONP_PCRIT : RIT
+ - CLKPWR_PCONP_PCMC : MC
+ - CLKPWR_PCONP_PCQEI : QEI
+ - CLKPWR_PCONP_PCI2C1 : I2C 1
+ - CLKPWR_PCONP_PCSSP0 : SSP 0
+ - CLKPWR_PCONP_PCTIM2 : Timer 2
+ - CLKPWR_PCONP_PCTIM3 : Timer 3
+ - CLKPWR_PCONP_PCUART2 : UART 2
+ - CLKPWR_PCONP_PCUART3 : UART 3
+ - CLKPWR_PCONP_PCI2C2 : I2C 2
+ - CLKPWR_PCONP_PCI2S : I2S
+ - CLKPWR_PCONP_PCGPDMA : GPDMA
+ - CLKPWR_PCONP_PCENET : Ethernet
+ - CLKPWR_PCONP_PCUSB : USB
+ *
+ * @param[in] NewState New state of Peripheral Power, should be:
+ * - ENABLE : Enable power for this peripheral
+ * - DISABLE : Disable power for this peripheral
+ *
+ * @return none
+ **********************************************************************/
+void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState)
+{
+ if (NewState == ENABLE)
+ {
+ LPC_SC->PCONP |= PPType & CLKPWR_PCONP_BITMASK;
+ }
+ else if (NewState == DISABLE)
+ {
+ LPC_SC->PCONP &= (~PPType) & CLKPWR_PCONP_BITMASK;
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Enter Sleep mode with co-operated instruction by the Cortex-M3.
+ * @param[in] None
+ * @return None
+ **********************************************************************/
+void CLKPWR_Sleep(void)
+{
+ LPC_SC->PCON = 0x00;
+ /* Sleep Mode*/
+ __WFI();
+}
+
+
+/*********************************************************************//**
+ * @brief Enter Deep Sleep mode with co-operated instruction by the Cortex-M3.
+ * @param[in] None
+ * @return None
+ **********************************************************************/
+void CLKPWR_DeepSleep(void)
+{
+ /* Deep-Sleep Mode, set SLEEPDEEP bit */
+ SCB->SCR = 0x4;
+ LPC_SC->PCON = 0x00;
+ /* Deep Sleep Mode*/
+ __WFI();
+}
+
+
+/*********************************************************************//**
+ * @brief Enter Power Down mode with co-operated instruction by the Cortex-M3.
+ * @param[in] None
+ * @return None
+ **********************************************************************/
+void CLKPWR_PowerDown(void)
+{
+ /* Deep-Sleep Mode, set SLEEPDEEP bit */
+ SCB->SCR = 0x4;
+ LPC_SC->PCON = 0x01;
+ /* Power Down Mode*/
+ __WFI();
+}
+
+
+/*********************************************************************//**
+ * @brief Enter Deep Power Down mode with co-operated instruction by the Cortex-M3.
+ * @param[in] None
+ * @return None
+ **********************************************************************/
+void CLKPWR_DeepPowerDown(void)
+{
+ /* Deep-Sleep Mode, set SLEEPDEEP bit */
+ SCB->SCR = 0x4;
+ LPC_SC->PCON = 0x03;
+ /* Deep Power Down Mode*/
+ __WFI();
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/src/shared/cmsis/Drivers/source/lpc17xx_dac.c b/src/shared/cmsis/Drivers/source/lpc17xx_dac.c
@@ -0,0 +1,151 @@
+/**********************************************************************
+* $Id$ lpc17xx_dac.c 2010-05-21
+*//**
+* @file lpc17xx_dac.c
+* @brief Contains all functions support for DAC firmware library on LPC17xx
+* @version 2.0
+* @date 21. May. 2010
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2010, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @addtogroup DAC
+ * @{
+ */
+
+/* Includes ------------------------------------------------------------------- */
+#include "lpc17xx_dac.h"
+#include "lpc17xx_clkpwr.h"
+
+/* If this source file built with example, the LPC17xx FW library configuration
+ * file in each example directory ("lpc17xx_libcfg.h") must be included,
+ * otherwise the default FW library configuration file must be included instead
+ */
+#ifdef __BUILD_WITH_EXAMPLE__
+#include "lpc17xx_libcfg.h"
+#else
+#include "lpc17xx_libcfg_default.h"
+#endif /* __BUILD_WITH_EXAMPLE__ */
+
+
+#ifdef _DAC
+
+/* Public Functions ----------------------------------------------------------- */
+/** @addtogroup DAC_Public_Functions
+ * @{
+ */
+
+/*********************************************************************//**
+ * @brief Initial ADC configuration
+ * - Maximum current is 700 uA
+ * - Value to AOUT is 0
+ * @param[in] DACx pointer to LPC_DAC_TypeDef, should be: LPC_DAC
+ * @return None
+ ***********************************************************************/
+void DAC_Init(LPC_DAC_TypeDef *DACx)
+{
+ CHECK_PARAM(PARAM_DACx(DACx));
+ /* Set default clock divider for DAC */
+ // CLKPWR_SetPCLKDiv (CLKPWR_PCLKSEL_DAC, CLKPWR_PCLKSEL_CCLK_DIV_4);
+ //Set maximum current output
+ DAC_SetBias(LPC_DAC,DAC_MAX_CURRENT_700uA);
+}
+
+/*********************************************************************//**
+ * @brief Update value to DAC
+ * @param[in] DACx pointer to LPC_DAC_TypeDef, should be: LPC_DAC
+ * @param[in] dac_value : value 10 bit to be converted to output
+ * @return None
+ ***********************************************************************/
+void DAC_UpdateValue (LPC_DAC_TypeDef *DACx,uint32_t dac_value)
+{
+ uint32_t tmp;
+ CHECK_PARAM(PARAM_DACx(DACx));
+ tmp = DACx->DACR & DAC_BIAS_EN;
+ tmp |= DAC_VALUE(dac_value);
+ // Update value
+ DACx->DACR = tmp;
+}
+
+/*********************************************************************//**
+ * @brief Set Maximum current for DAC
+ * @param[in] DACx pointer to LPC_DAC_TypeDef, should be: LPC_DAC
+ * @param[in] bias : 0 is 700 uA
+ * 1 350 uA
+ * @return None
+ ***********************************************************************/
+void DAC_SetBias (LPC_DAC_TypeDef *DACx,uint32_t bias)
+{
+ CHECK_PARAM(PARAM_DAC_CURRENT_OPT(bias));
+ DACx->DACR &=~DAC_BIAS_EN;
+ if (bias == DAC_MAX_CURRENT_350uA)
+ {
+ DACx->DACR |= DAC_BIAS_EN;
+ }
+}
+
+/*********************************************************************//**
+ * @brief To enable the DMA operation and control DMA timer
+ * @param[in] DACx pointer to LPC_DAC_TypeDef, should be: LPC_DAC
+ * @param[in] DAC_ConverterConfigStruct pointer to DAC_CONVERTER_CFG_Type
+ * - DBLBUF_ENA : enable/disable DACR double buffering feature
+ * - CNT_ENA : enable/disable timer out counter
+ * - DMA_ENA : enable/disable DMA access
+ * @return None
+ ***********************************************************************/
+void DAC_ConfigDAConverterControl (LPC_DAC_TypeDef *DACx,DAC_CONVERTER_CFG_Type *DAC_ConverterConfigStruct)
+{
+ CHECK_PARAM(PARAM_DACx(DACx));
+ DACx->DACCTRL &= ~DAC_DACCTRL_MASK;
+ if (DAC_ConverterConfigStruct->DBLBUF_ENA)
+ DACx->DACCTRL |= DAC_DBLBUF_ENA;
+ if (DAC_ConverterConfigStruct->CNT_ENA)
+ DACx->DACCTRL |= DAC_CNT_ENA;
+ if (DAC_ConverterConfigStruct->DMA_ENA)
+ DACx->DACCTRL |= DAC_DMA_ENA;
+}
+
+/*********************************************************************//**
+ * @brief Set reload value for interrupt/DMA counter
+ * @param[in] DACx pointer to LPC_DAC_TypeDef, should be: LPC_DAC
+ * @param[in] time_out time out to reload for interrupt/DMA counter
+ * @return None
+ ***********************************************************************/
+void DAC_SetDMATimeOut(LPC_DAC_TypeDef *DACx, uint32_t time_out)
+{
+ CHECK_PARAM(PARAM_DACx(DACx));
+ DACx->DACCNTVAL = DAC_CCNT_VALUE(time_out);
+}
+
+/**
+ * @}
+ */
+
+#endif /* _DAC */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/src/shared/cmsis/Drivers/source/lpc17xx_emac.c b/src/shared/cmsis/Drivers/source/lpc17xx_emac.c
@@ -0,0 +1,963 @@
+/**********************************************************************
+* $Id$ lpc17xx_emac.c 2010-05-21
+*//**
+* @file lpc17xx_emac.c
+* @brief Contains all functions support for Ethernet MAC firmware
+* library on LPC17xx
+* @version 2.0
+* @date 21. May. 2010
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2010, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @addtogroup EMAC
+ * @{
+ */
+
+/* Includes ------------------------------------------------------------------- */
+#include "lpc17xx_emac.h"
+#include "lpc17xx_clkpwr.h"
+
+/* If this source file built with example, the LPC17xx FW library configuration
+ * file in each example directory ("lpc17xx_libcfg.h") must be included,
+ * otherwise the default FW library configuration file must be included instead
+ */
+#ifdef __BUILD_WITH_EXAMPLE__
+#include "lpc17xx_libcfg.h"
+#else
+#include "lpc17xx_libcfg_default.h"
+#endif /* __BUILD_WITH_EXAMPLE__ */
+
+
+#ifdef _EMAC
+
+/* Private Variables ---------------------------------------------------------- */
+/** @defgroup EMAC_Private_Variables EMAC Private Variables
+ * @{
+ */
+
+/* MII Mgmt Configuration register - Clock divider setting */
+const uint8_t EMAC_clkdiv[] = { 4, 6, 8, 10, 14, 20, 28, 36, 40, 44, 48, 52, 56, 60, 64};
+
+/* EMAC local DMA Descriptors */
+
+/** Rx Descriptor data array */
+static RX_Desc Rx_Desc[EMAC_NUM_RX_FRAG];
+
+/** Rx Status data array - Must be 8-Byte aligned */
+#if defined ( __CC_ARM )
+static __align(8) RX_Stat Rx_Stat[EMAC_NUM_RX_FRAG];
+#elif defined ( __ICCARM__ )
+#pragma data_alignment=8
+static RX_Stat Rx_Stat[EMAC_NUM_RX_FRAG];
+#elif defined ( __GNUC__ )
+static __attribute__ ((aligned (8))) RX_Stat Rx_Stat[EMAC_NUM_RX_FRAG];
+#endif
+
+/** Tx Descriptor data array */
+static TX_Desc Tx_Desc[EMAC_NUM_TX_FRAG];
+/** Tx Status data array */
+static TX_Stat Tx_Stat[EMAC_NUM_TX_FRAG];
+
+/* EMAC local DMA buffers */
+/** Rx buffer data */
+static uint32_t rx_buf[EMAC_NUM_RX_FRAG][EMAC_ETH_MAX_FLEN>>2];
+/** Tx buffer data */
+static uint32_t tx_buf[EMAC_NUM_TX_FRAG][EMAC_ETH_MAX_FLEN>>2];
+
+/**
+ * @}
+ */
+
+/* Private Functions ---------------------------------------------------------- */
+static void rx_descr_init (void);
+static void tx_descr_init (void);
+static int32_t write_PHY (uint32_t PhyReg, uint16_t Value);
+static int32_t read_PHY (uint32_t PhyReg);
+
+static void setEmacAddr(uint8_t abStationAddr[]);
+static int32_t emac_CRCCalc(uint8_t frame_no_fcs[], int32_t frame_len);
+
+
+/*--------------------------- rx_descr_init ---------------------------------*/
+/*********************************************************************//**
+ * @brief Initializes RX Descriptor
+ * @param[in] None
+ * @return None
+ ***********************************************************************/
+static void rx_descr_init (void)
+{
+ /* Initialize Receive Descriptor and Status array. */
+ uint32_t i;
+
+ for (i = 0; i < EMAC_NUM_RX_FRAG; i++) {
+ Rx_Desc[i].Packet = (uint32_t)&rx_buf[i];
+ Rx_Desc[i].Ctrl = EMAC_RCTRL_INT | (EMAC_ETH_MAX_FLEN - 1);
+ Rx_Stat[i].Info = 0;
+ Rx_Stat[i].HashCRC = 0;
+ }
+
+ /* Set EMAC Receive Descriptor Registers. */
+ LPC_EMAC->RxDescriptor = (uint32_t)&Rx_Desc[0];
+ LPC_EMAC->RxStatus = (uint32_t)&Rx_Stat[0];
+ LPC_EMAC->RxDescriptorNumber = EMAC_NUM_RX_FRAG - 1;
+
+ /* Rx Descriptors Point to 0 */
+ LPC_EMAC->RxConsumeIndex = 0;
+}
+
+
+/*--------------------------- tx_descr_init ---- ----------------------------*/
+/*********************************************************************//**
+ * @brief Initializes TX Descriptor
+ * @param[in] None
+ * @return None
+ ***********************************************************************/
+static void tx_descr_init (void) {
+ /* Initialize Transmit Descriptor and Status array. */
+ uint32_t i;
+
+ for (i = 0; i < EMAC_NUM_TX_FRAG; i++) {
+ Tx_Desc[i].Packet = (uint32_t)&tx_buf[i];
+ Tx_Desc[i].Ctrl = 0;
+ Tx_Stat[i].Info = 0;
+ }
+
+ /* Set EMAC Transmit Descriptor Registers. */
+ LPC_EMAC->TxDescriptor = (uint32_t)&Tx_Desc[0];
+ LPC_EMAC->TxStatus = (uint32_t)&Tx_Stat[0];
+ LPC_EMAC->TxDescriptorNumber = EMAC_NUM_TX_FRAG - 1;
+
+ /* Tx Descriptors Point to 0 */
+ LPC_EMAC->TxProduceIndex = 0;
+}
+
+
+/*--------------------------- write_PHY -------------------------------------*/
+/*********************************************************************//**
+ * @brief Write value to PHY device
+ * @param[in] PhyReg: PHY Register address
+ * @param[in] Value: Value to write
+ * @return 0 - if success
+ * 1 - if fail
+ ***********************************************************************/
+static int32_t write_PHY (uint32_t PhyReg, uint16_t Value)
+{
+ /* Write a data 'Value' to PHY register 'PhyReg'. */
+ uint32_t tout;
+
+ LPC_EMAC->MADR = EMAC_DEF_ADR | PhyReg;
+ LPC_EMAC->MWTD = Value;
+
+ /* Wait until operation completed */
+ tout = 0;
+ for (tout = 0; tout < EMAC_MII_WR_TOUT; tout++) {
+ if ((LPC_EMAC->MIND & EMAC_MIND_BUSY) == 0) {
+ return (0);
+ }
+ }
+ // Time out!
+ return (-1);
+}
+
+
+/*--------------------------- read_PHY --------------------------------------*/
+/*********************************************************************//**
+ * @brief Read value from PHY device
+ * @param[in] PhyReg: PHY Register address
+ * @return 0 - if success
+ * 1 - if fail
+ ***********************************************************************/
+static int32_t read_PHY (uint32_t PhyReg)
+{
+ /* Read a PHY register 'PhyReg'. */
+ uint32_t tout;
+
+ LPC_EMAC->MADR = EMAC_DEF_ADR | PhyReg;
+ LPC_EMAC->MCMD = EMAC_MCMD_READ;
+
+ /* Wait until operation completed */
+ tout = 0;
+ for (tout = 0; tout < EMAC_MII_RD_TOUT; tout++) {
+ if ((LPC_EMAC->MIND & EMAC_MIND_BUSY) == 0) {
+ LPC_EMAC->MCMD = 0;
+ return (LPC_EMAC->MRDD);
+ }
+ }
+ // Time out!
+ return (-1);
+}
+
+/*********************************************************************//**
+ * @brief Set Station MAC address for EMAC module
+ * @param[in] abStationAddr Pointer to Station address that contains 6-bytes
+ * of MAC address (should be in order from MAC Address 1 to MAC Address 6)
+ * @return None
+ **********************************************************************/
+static void setEmacAddr(uint8_t abStationAddr[])
+{
+ /* Set the Ethernet MAC Address registers */
+ LPC_EMAC->SA0 = ((uint32_t)abStationAddr[5] << 8) | (uint32_t)abStationAddr[4];
+ LPC_EMAC->SA1 = ((uint32_t)abStationAddr[3] << 8) | (uint32_t)abStationAddr[2];
+ LPC_EMAC->SA2 = ((uint32_t)abStationAddr[1] << 8) | (uint32_t)abStationAddr[0];
+}
+
+
+/*********************************************************************//**
+ * @brief Calculates CRC code for number of bytes in the frame
+ * @param[in] frame_no_fcs Pointer to the first byte of the frame
+ * @param[in] frame_len length of the frame without the FCS
+ * @return the CRC as a 32 bit integer
+ **********************************************************************/
+static int32_t emac_CRCCalc(uint8_t frame_no_fcs[], int32_t frame_len)
+{
+ int i; // iterator
+ int j; // another iterator
+ char byte; // current byte
+ int crc; // CRC result
+ int q0, q1, q2, q3; // temporary variables
+ crc = 0xFFFFFFFF;
+ for (i = 0; i < frame_len; i++) {
+ byte = *frame_no_fcs++;
+ for (j = 0; j < 2; j++) {
+ if (((crc >> 28) ^ (byte >> 3)) & 0x00000001) {
+ q3 = 0x04C11DB7;
+ } else {
+ q3 = 0x00000000;
+ }
+ if (((crc >> 29) ^ (byte >> 2)) & 0x00000001) {
+ q2 = 0x09823B6E;
+ } else {
+ q2 = 0x00000000;
+ }
+ if (((crc >> 30) ^ (byte >> 1)) & 0x00000001) {
+ q1 = 0x130476DC;
+ } else {
+ q1 = 0x00000000;
+ }
+ if (((crc >> 31) ^ (byte >> 0)) & 0x00000001) {
+ q0 = 0x2608EDB8;
+ } else {
+ q0 = 0x00000000;
+ }
+ crc = (crc << 4) ^ q3 ^ q2 ^ q1 ^ q0;
+ byte >>= 4;
+ }
+ }
+ return crc;
+}
+/* End of Private Functions --------------------------------------------------- */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @addtogroup EMAC_Public_Functions
+ * @{
+ */
+
+
+/*********************************************************************//**
+ * @brief Initializes the EMAC peripheral according to the specified
+* parameters in the EMAC_ConfigStruct.
+ * @param[in] EMAC_ConfigStruct Pointer to a EMAC_CFG_Type structure
+* that contains the configuration information for the
+* specified EMAC peripheral.
+ * @return None
+ *
+ * Note: This function will initialize EMAC module according to procedure below:
+ * - Remove the soft reset condition from the MAC
+ * - Configure the PHY via the MIIM interface of the MAC
+ * - Select RMII mode
+ * - Configure the transmit and receive DMA engines, including the descriptor arrays
+ * - Configure the host registers (MAC1,MAC2 etc.) in the MAC
+ * - Enable the receive and transmit data paths
+ * In default state after initializing, only Rx Done and Tx Done interrupt are enabled,
+ * all remain interrupts are disabled
+ * (Ref. from LPC17xx UM)
+ **********************************************************************/
+Status EMAC_Init(EMAC_CFG_Type *EMAC_ConfigStruct)
+{
+ /* Initialize the EMAC Ethernet controller. */
+ int32_t regv,tout, tmp;
+
+ /* Set up clock and power for Ethernet module */
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCENET, ENABLE);
+
+ /* Reset all EMAC internal modules */
+ LPC_EMAC->MAC1 = EMAC_MAC1_RES_TX | EMAC_MAC1_RES_MCS_TX | EMAC_MAC1_RES_RX |
+ EMAC_MAC1_RES_MCS_RX | EMAC_MAC1_SIM_RES | EMAC_MAC1_SOFT_RES;
+
+ LPC_EMAC->Command = EMAC_CR_REG_RES | EMAC_CR_TX_RES | EMAC_CR_RX_RES | EMAC_CR_PASS_RUNT_FRM;
+
+ /* A short delay after reset. */
+ for (tout = 100; tout; tout--);
+
+ /* Initialize MAC control registers. */
+ LPC_EMAC->MAC1 = EMAC_MAC1_PASS_ALL;
+ LPC_EMAC->MAC2 = EMAC_MAC2_CRC_EN | EMAC_MAC2_PAD_EN;
+ LPC_EMAC->MAXF = EMAC_ETH_MAX_FLEN;
+ /*
+ * Find the clock that close to desired target clock
+ */
+ tmp = SystemCoreClock / EMAC_MCFG_MII_MAXCLK;
+ for (tout = 0; tout < (int32_t)sizeof (EMAC_clkdiv); tout++){
+ if (EMAC_clkdiv[tout] >= tmp) break;
+ }
+ tout++;
+ // Write to MAC configuration register and reset
+ LPC_EMAC->MCFG = EMAC_MCFG_CLK_SEL(tout) | EMAC_MCFG_RES_MII;
+ // release reset
+ LPC_EMAC->MCFG &= ~(EMAC_MCFG_RES_MII);
+ LPC_EMAC->CLRT = EMAC_CLRT_DEF;
+ LPC_EMAC->IPGR = EMAC_IPGR_P2_DEF;
+
+ /* Enable Reduced MII interface. */
+ LPC_EMAC->Command = EMAC_CR_RMII | EMAC_CR_PASS_RUNT_FRM;
+
+ /* Reset Reduced MII Logic. */
+// LPC_EMAC->SUPP = EMAC_SUPP_RES_RMII;
+
+ for (tout = 100; tout; tout--);
+ LPC_EMAC->SUPP = 0;
+
+ /* Put the DP83848C in reset mode */
+ write_PHY (EMAC_PHY_REG_BMCR, EMAC_PHY_BMCR_RESET);
+
+ /* Wait for hardware reset to end. */
+ for (tout = EMAC_PHY_RESP_TOUT; tout>=0; tout--) {
+ regv = read_PHY (EMAC_PHY_REG_BMCR);
+ if (!(regv & (EMAC_PHY_BMCR_RESET | EMAC_PHY_BMCR_POWERDOWN))) {
+ /* Reset complete, device not Power Down. */
+ break;
+ }
+ if (tout == 0){
+ // Time out, return ERROR
+ return (ERROR);
+ }
+ }
+
+ // Set PHY mode
+ if (EMAC_SetPHYMode(EMAC_ConfigStruct->Mode) < 0){
+ return (ERROR);
+ }
+
+ // Set EMAC address
+ setEmacAddr(EMAC_ConfigStruct->pbEMAC_Addr);
+
+ /* Initialize Tx and Rx DMA Descriptors */
+ rx_descr_init ();
+ tx_descr_init ();
+
+ // Set Receive Filter register: enable broadcast and multicast
+ LPC_EMAC->RxFilterCtrl = EMAC_RFC_MCAST_EN | EMAC_RFC_BCAST_EN | EMAC_RFC_PERFECT_EN;
+
+ /* Enable Rx Done and Tx Done interrupt for EMAC */
+ LPC_EMAC->IntEnable = EMAC_INT_RX_DONE | EMAC_INT_TX_DONE;
+
+ /* Reset all interrupts */
+ LPC_EMAC->IntClear = 0xFFFF;
+
+ /* Enable receive and transmit mode of MAC Ethernet core */
+ LPC_EMAC->Command |= (EMAC_CR_RX_EN | EMAC_CR_TX_EN);
+ LPC_EMAC->MAC1 |= EMAC_MAC1_REC_EN;
+
+ return SUCCESS;
+}
+
+
+/*********************************************************************//**
+ * @brief De-initializes the EMAC peripheral registers to their
+* default reset values.
+ * @param[in] None
+ * @return None
+ **********************************************************************/
+void EMAC_DeInit(void)
+{
+ // Disable all interrupt
+ LPC_EMAC->IntEnable = 0x00;
+ // Clear all pending interrupt
+ LPC_EMAC->IntClear = (0xFF) | (EMAC_INT_SOFT_INT | EMAC_INT_WAKEUP);
+
+ /* TurnOff clock and power for Ethernet module */
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCENET, DISABLE);
+}
+
+
+/*********************************************************************//**
+ * @brief Check specified PHY status in EMAC peripheral
+ * @param[in] ulPHYState Specified PHY Status Type, should be:
+ * - EMAC_PHY_STAT_LINK: Link Status
+ * - EMAC_PHY_STAT_SPEED: Speed Status
+ * - EMAC_PHY_STAT_DUP: Duplex Status
+ * @return Status of specified PHY status (0 or 1).
+ * (-1) if error.
+ *
+ * Note:
+ * For EMAC_PHY_STAT_LINK, return value:
+ * - 0: Link Down
+ * - 1: Link Up
+ * For EMAC_PHY_STAT_SPEED, return value:
+ * - 0: 10Mbps
+ * - 1: 100Mbps
+ * For EMAC_PHY_STAT_DUP, return value:
+ * - 0: Half-Duplex
+ * - 1: Full-Duplex
+ **********************************************************************/
+int32_t EMAC_CheckPHYStatus(uint32_t ulPHYState)
+{
+ int32_t regv, tmp;
+#ifdef MCB_LPC_1768
+ regv = read_PHY (EMAC_PHY_REG_STS);
+ switch(ulPHYState){
+ case EMAC_PHY_STAT_LINK:
+ tmp = (regv & EMAC_PHY_SR_LINK) ? 1 : 0;
+ break;
+ case EMAC_PHY_STAT_SPEED:
+ tmp = (regv & EMAC_PHY_SR_SPEED) ? 0 : 1;
+ break;
+ case EMAC_PHY_STAT_DUP:
+ tmp = (regv & EMAC_PHY_SR_FULL_DUP) ? 1 : 0;
+ break;
+#elif defined(IAR_LPC_1768)
+ /* Use IAR_LPC_1768 board:
+ * FSZ8721BL doesn't have Status Register
+ * so we read Basic Mode Status Register (0x01h) instead
+ */
+ regv = read_PHY (EMAC_PHY_REG_BMSR);
+ switch(ulPHYState){
+ case EMAC_PHY_STAT_LINK:
+ tmp = (regv & EMAC_PHY_BMSR_LINK_STATUS) ? 1 : 0;
+ break;
+ case EMAC_PHY_STAT_SPEED:
+ tmp = (regv & EMAC_PHY_SR_100_SPEED) ? 1 : 0;
+ break;
+ case EMAC_PHY_STAT_DUP:
+ tmp = (regv & EMAC_PHY_SR_FULL_DUP) ? 1 : 0;
+ break;
+#endif
+ default:
+ tmp = -1;
+ break;
+ }
+ return (tmp);
+}
+
+
+/*********************************************************************//**
+ * @brief Set specified PHY mode in EMAC peripheral
+ * @param[in] ulPHYMode Specified PHY mode, should be:
+ * - EMAC_MODE_AUTO
+ * - EMAC_MODE_10M_FULL
+ * - EMAC_MODE_10M_HALF
+ * - EMAC_MODE_100M_FULL
+ * - EMAC_MODE_100M_HALF
+ * @return Return (0) if no error, otherwise return (-1)
+ **********************************************************************/
+int32_t EMAC_SetPHYMode(uint32_t ulPHYMode)
+{
+ int32_t id1, id2, tout;
+
+ /* Check if this is a DP83848C PHY. */
+ id1 = read_PHY (EMAC_PHY_REG_IDR1);
+ id2 = read_PHY (EMAC_PHY_REG_IDR2);
+
+#ifdef MCB_LPC_1768
+ if (((id1 << 16) | (id2 & 0xFFF0)) == EMAC_DP83848C_ID) {
+ switch(ulPHYMode){
+ case EMAC_MODE_AUTO:
+ write_PHY (EMAC_PHY_REG_BMCR, EMAC_PHY_AUTO_NEG);
+#elif defined(IAR_LPC_1768) /* Use IAR LPC1768 KickStart board */
+ if (((id1 << 16) | id2) == EMAC_KSZ8721BL_ID) {
+ /* Configure the PHY device */
+ switch(ulPHYMode){
+ case EMAC_MODE_AUTO:
+ /* Use auto-negotiation about the link speed. */
+ write_PHY (EMAC_PHY_REG_BMCR, EMAC_PHY_AUTO_NEG);
+// write_PHY (EMAC_PHY_REG_BMCR, EMAC_PHY_BMCR_AN);
+#endif
+ /* Wait to complete Auto_Negotiation */
+ for (tout = EMAC_PHY_RESP_TOUT; tout>=0; tout--) {
+
+ }
+ break;
+ case EMAC_MODE_10M_FULL:
+ /* Connect at 10MBit full-duplex */
+ write_PHY (EMAC_PHY_REG_BMCR, EMAC_PHY_FULLD_10M);
+ break;
+ case EMAC_MODE_10M_HALF:
+ /* Connect at 10MBit half-duplex */
+ write_PHY (EMAC_PHY_REG_BMCR, EMAC_PHY_HALFD_10M);
+ break;
+ case EMAC_MODE_100M_FULL:
+ /* Connect at 100MBit full-duplex */
+ write_PHY (EMAC_PHY_REG_BMCR, EMAC_PHY_FULLD_100M);
+ break;
+ case EMAC_MODE_100M_HALF:
+ /* Connect at 100MBit half-duplex */
+ write_PHY (EMAC_PHY_REG_BMCR, EMAC_PHY_HALFD_100M);
+ break;
+ default:
+ // un-supported
+ return (-1);
+ }
+ }
+ // It's not correct module ID
+ else {
+ return (-1);
+ }
+
+ // Update EMAC configuration with current PHY status
+ if (EMAC_UpdatePHYStatus() < 0){
+ return (-1);
+ }
+
+ // Complete
+ return (0);
+}
+
+
+/*********************************************************************//**
+ * @brief Auto-Configures value for the EMAC configuration register to
+ * match with current PHY mode
+ * @param[in] None
+ * @return Return (0) if no error, otherwise return (-1)
+ *
+ * Note: The EMAC configuration will be auto-configured:
+ * - Speed mode.
+ * - Half/Full duplex mode
+ **********************************************************************/
+int32_t EMAC_UpdatePHYStatus(void)
+{
+ int32_t regv, tout;
+
+ /* Check the link status. */
+#ifdef MCB_LPC_1768
+ for (tout = EMAC_PHY_RESP_TOUT; tout>=0; tout--) {
+ regv = read_PHY (EMAC_PHY_REG_STS);
+ if (regv & EMAC_PHY_SR_LINK) {
+ /* Link is on. */
+ break;
+ }
+ if (tout == 0){
+ // time out
+ return (-1);
+ }
+ }
+ /* Configure Full/Half Duplex mode. */
+ if (regv & EMAC_PHY_SR_DUP) {
+ /* Full duplex is enabled. */
+ LPC_EMAC->MAC2 |= EMAC_MAC2_FULL_DUP;
+ LPC_EMAC->Command |= EMAC_CR_FULL_DUP;
+ LPC_EMAC->IPGT = EMAC_IPGT_FULL_DUP;
+ } else {
+ /* Half duplex mode. */
+ LPC_EMAC->IPGT = EMAC_IPGT_HALF_DUP;
+ }
+ if (regv & EMAC_PHY_SR_SPEED) {
+ /* 10MBit mode. */
+ LPC_EMAC->SUPP = 0;
+ } else {
+ /* 100MBit mode. */
+ LPC_EMAC->SUPP = EMAC_SUPP_SPEED;
+ }
+#elif defined(IAR_LPC_1768)
+ for (tout = EMAC_PHY_RESP_TOUT; tout>=0; tout--) {
+ regv = read_PHY (EMAC_PHY_REG_BMSR);
+ if (regv & EMAC_PHY_BMSR_LINK_STATUS) {
+ /* Link is on. */
+ break;
+ }
+ if (tout == 0){
+ // time out
+ return (-1);
+ }
+ }
+
+ /* Configure Full/Half Duplex mode. */
+ if (regv & EMAC_PHY_SR_FULL_DUP) {
+ /* Full duplex is enabled. */
+ LPC_EMAC->MAC2 |= EMAC_MAC2_FULL_DUP;
+ LPC_EMAC->Command |= EMAC_CR_FULL_DUP;
+ LPC_EMAC->IPGT = EMAC_IPGT_FULL_DUP;
+ } else {
+ /* Half duplex mode. */
+ LPC_EMAC->IPGT = EMAC_IPGT_HALF_DUP;
+ }
+
+ /* Configure 100MBit/10MBit mode. */
+ if (!(regv & EMAC_PHY_SR_100_SPEED)) {
+ /* 10MBit mode. */
+ LPC_EMAC->SUPP = 0;
+ } else {
+ /* 100MBit mode. */
+ LPC_EMAC->SUPP = EMAC_SUPP_SPEED;
+ }
+#endif
+ // Complete
+ return (0);
+}
+
+
+/*********************************************************************//**
+ * @brief Enable/Disable hash filter functionality for specified destination
+ * MAC address in EMAC module
+ * @param[in] dstMAC_addr Pointer to the first MAC destination address, should
+ * be 6-bytes length, in order LSB to the MSB
+ * @param[in] NewState New State of this command, should be:
+ * - ENABLE.
+ * - DISABLE.
+ * @return None
+ *
+ * Note:
+ * The standard Ethernet cyclic redundancy check (CRC) function is calculated from
+ * the 6 byte destination address in the Ethernet frame (this CRC is calculated
+ * anyway as part of calculating the CRC of the whole frame), then bits [28:23] out of
+ * the 32 bits CRC result are taken to form the hash. The 6 bit hash is used to access
+ * the hash table: it is used as an index in the 64 bit HashFilter register that has been
+ * programmed with accept values. If the selected accept value is 1, the frame is
+ * accepted.
+ **********************************************************************/
+void EMAC_SetHashFilter(uint8_t dstMAC_addr[], FunctionalState NewState)
+{
+ uint32_t *pReg;
+ uint32_t tmp;
+ int32_t crc;
+
+ // Calculate the CRC from the destination MAC address
+ crc = emac_CRCCalc(dstMAC_addr, 6);
+ // Extract the value from CRC to get index value for hash filter table
+ crc = (crc >> 23) & 0x3F;
+
+ pReg = (crc > 31) ? ((uint32_t *)&LPC_EMAC->HashFilterH) \
+ : ((uint32_t *)&LPC_EMAC->HashFilterL);
+ tmp = (crc > 31) ? (crc - 32) : crc;
+ if (NewState == ENABLE) {
+ (*pReg) |= (1UL << tmp);
+ } else {
+ (*pReg) &= ~(1UL << tmp);
+ }
+ // Enable Rx Filter
+ LPC_EMAC->Command &= ~EMAC_CR_PASS_RX_FILT;
+}
+
+/*********************************************************************//**
+ * @brief Enable/Disable Filter mode for each specified type EMAC peripheral
+ * @param[in] ulFilterMode Filter mode, should be:
+ * - EMAC_RFC_UCAST_EN: all frames of unicast types
+ * will be accepted
+ * - EMAC_RFC_BCAST_EN: broadcast frame will be
+ * accepted
+ * - EMAC_RFC_MCAST_EN: all frames of multicast
+ * types will be accepted
+ * - EMAC_RFC_UCAST_HASH_EN: The imperfect hash
+ * filter will be applied to unicast addresses
+ * - EMAC_RFC_MCAST_HASH_EN: The imperfect hash
+ * filter will be applied to multicast addresses
+ * - EMAC_RFC_PERFECT_EN: the destination address
+ * will be compared with the 6 byte station address
+ * programmed in the station address by the filter
+ * - EMAC_RFC_MAGP_WOL_EN: the result of the magic
+ * packet filter will generate a WoL interrupt when
+ * there is a match
+ * - EMAC_RFC_PFILT_WOL_EN: the result of the perfect address
+ * matching filter and the imperfect hash filter will
+ * generate a WoL interrupt when there is a match
+ * @param[in] NewState New State of this command, should be:
+ * - ENABLE
+ * - DISABLE
+ * @return None
+ **********************************************************************/
+void EMAC_SetFilterMode(uint32_t ulFilterMode, FunctionalState NewState)
+{
+ if (NewState == ENABLE){
+ LPC_EMAC->RxFilterCtrl |= ulFilterMode;
+ } else {
+ LPC_EMAC->RxFilterCtrl &= ~ulFilterMode;
+ }
+}
+
+/*********************************************************************//**
+ * @brief Get status of Wake On LAN Filter for each specified
+ * type in EMAC peripheral, clear this status if it is set
+ * @param[in] ulWoLMode WoL Filter mode, should be:
+ * - EMAC_WOL_UCAST: unicast frames caused WoL
+ * - EMAC_WOL_UCAST: broadcast frame caused WoL
+ * - EMAC_WOL_MCAST: multicast frame caused WoL
+ * - EMAC_WOL_UCAST_HASH: unicast frame that passes the
+ * imperfect hash filter caused WoL
+ * - EMAC_WOL_MCAST_HASH: multicast frame that passes the
+ * imperfect hash filter caused WoL
+ * - EMAC_WOL_PERFECT:perfect address matching filter
+ * caused WoL
+ * - EMAC_WOL_RX_FILTER: the receive filter caused WoL
+ * - EMAC_WOL_MAG_PACKET: the magic packet filter caused WoL
+ * @return SET/RESET
+ **********************************************************************/
+FlagStatus EMAC_GetWoLStatus(uint32_t ulWoLMode)
+{
+ if (LPC_EMAC->RxFilterWoLStatus & ulWoLMode) {
+ LPC_EMAC->RxFilterWoLClear = ulWoLMode;
+ return SET;
+ } else {
+ return RESET;
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Write data to Tx packet data buffer at current index due to
+ * TxProduceIndex
+ * @param[in] pDataStruct Pointer to a EMAC_PACKETBUF_Type structure
+ * data that contain specified information about
+ * Packet data buffer.
+ * @return None
+ **********************************************************************/
+void EMAC_WritePacketBuffer(EMAC_PACKETBUF_Type *pDataStruct)
+{
+ uint32_t idx,len;
+ uint32_t *sp,*dp;
+
+ idx = LPC_EMAC->TxProduceIndex;
+ sp = (uint32_t *)pDataStruct->pbDataBuf;
+ dp = (uint32_t *)Tx_Desc[idx].Packet;
+ /* Copy frame data to EMAC packet buffers. */
+ for (len = (pDataStruct->ulDataLen + 3) >> 2; len; len--) {
+ *dp++ = *sp++;
+ }
+ Tx_Desc[idx].Ctrl = (pDataStruct->ulDataLen - 1) | (EMAC_TCTRL_INT | EMAC_TCTRL_LAST);
+}
+
+/*********************************************************************//**
+ * @brief Read data from Rx packet data buffer at current index due
+ * to RxConsumeIndex
+ * @param[in] pDataStruct Pointer to a EMAC_PACKETBUF_Type structure
+ * data that contain specified information about
+ * Packet data buffer.
+ * @return None
+ **********************************************************************/
+void EMAC_ReadPacketBuffer(EMAC_PACKETBUF_Type *pDataStruct)
+{
+ uint32_t idx, len;
+ uint32_t *dp, *sp;
+
+ idx = LPC_EMAC->RxConsumeIndex;
+ dp = (uint32_t *)pDataStruct->pbDataBuf;
+ sp = (uint32_t *)Rx_Desc[idx].Packet;
+
+ if (pDataStruct->pbDataBuf != NULL) {
+ for (len = (pDataStruct->ulDataLen + 3) >> 2; len; len--) {
+ *dp++ = *sp++;
+ }
+ }
+}
+
+/*********************************************************************//**
+ * @brief Enable/Disable interrupt for each type in EMAC
+ * @param[in] ulIntType Interrupt Type, should be:
+ * - EMAC_INT_RX_OVERRUN: Receive Overrun
+ * - EMAC_INT_RX_ERR: Receive Error
+ * - EMAC_INT_RX_FIN: Receive Descriptor Finish
+ * - EMAC_INT_RX_DONE: Receive Done
+ * - EMAC_INT_TX_UNDERRUN: Transmit Under-run
+ * - EMAC_INT_TX_ERR: Transmit Error
+ * - EMAC_INT_TX_FIN: Transmit descriptor finish
+ * - EMAC_INT_TX_DONE: Transmit Done
+ * - EMAC_INT_SOFT_INT: Software interrupt
+ * - EMAC_INT_WAKEUP: Wakeup interrupt
+ * @param[in] NewState New State of this function, should be:
+ * - ENABLE.
+ * - DISABLE.
+ * @return None
+ **********************************************************************/
+void EMAC_IntCmd(uint32_t ulIntType, FunctionalState NewState)
+{
+ if (NewState == ENABLE) {
+ LPC_EMAC->IntEnable |= ulIntType;
+ } else {
+ LPC_EMAC->IntEnable &= ~(ulIntType);
+ }
+}
+
+/*********************************************************************//**
+ * @brief Check whether if specified interrupt flag is set or not
+ * for each interrupt type in EMAC and clear interrupt pending
+ * if it is set.
+ * @param[in] ulIntType Interrupt Type, should be:
+ * - EMAC_INT_RX_OVERRUN: Receive Overrun
+ * - EMAC_INT_RX_ERR: Receive Error
+ * - EMAC_INT_RX_FIN: Receive Descriptor Finish
+ * - EMAC_INT_RX_DONE: Receive Done
+ * - EMAC_INT_TX_UNDERRUN: Transmit Under-run
+ * - EMAC_INT_TX_ERR: Transmit Error
+ * - EMAC_INT_TX_FIN: Transmit descriptor finish
+ * - EMAC_INT_TX_DONE: Transmit Done
+ * - EMAC_INT_SOFT_INT: Software interrupt
+ * - EMAC_INT_WAKEUP: Wakeup interrupt
+ * @return New state of specified interrupt (SET or RESET)
+ **********************************************************************/
+IntStatus EMAC_IntGetStatus(uint32_t ulIntType)
+{
+ if (LPC_EMAC->IntStatus & ulIntType) {
+ LPC_EMAC->IntClear = ulIntType;
+ return SET;
+ } else {
+ return RESET;
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Check whether if the current RxConsumeIndex is not equal to the
+ * current RxProduceIndex.
+ * @param[in] None
+ * @return TRUE if they're not equal, otherwise return FALSE
+ *
+ * Note: In case the RxConsumeIndex is not equal to the RxProduceIndex,
+ * it means there're available data has been received. They should be read
+ * out and released the Receive Data Buffer by updating the RxConsumeIndex value.
+ **********************************************************************/
+Bool EMAC_CheckReceiveIndex(void)
+{
+ if (LPC_EMAC->RxConsumeIndex != LPC_EMAC->RxProduceIndex) {
+ return TRUE;
+ } else {
+ return FALSE;
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Check whether if the current TxProduceIndex is not equal to the
+ * current RxProduceIndex - 1.
+ * @param[in] None
+ * @return TRUE if they're not equal, otherwise return FALSE
+ *
+ * Note: In case the RxConsumeIndex is equal to the RxProduceIndex - 1,
+ * it means the transmit buffer is available and data can be written to transmit
+ * buffer to be sent.
+ **********************************************************************/
+Bool EMAC_CheckTransmitIndex(void)
+{
+ uint32_t tmp = LPC_EMAC->TxConsumeIndex;
+ if (LPC_EMAC->TxProduceIndex == ( tmp - 1 ))
+ {
+ return FALSE;
+ }
+ else if( ( tmp == 0 ) && ( LPC_EMAC->TxProduceIndex == ( EMAC_NUM_TX_FRAG - 1 ) ) )
+ {
+ return FALSE;
+ }
+ else
+ {
+ return TRUE;
+ }
+}
+
+
+
+/*********************************************************************//**
+ * @brief Get current status value of receive data (due to RxConsumeIndex)
+ * @param[in] ulRxStatType Received Status type, should be one of following:
+ * - EMAC_RINFO_CTRL_FRAME: Control Frame
+ * - EMAC_RINFO_VLAN: VLAN Frame
+ * - EMAC_RINFO_FAIL_FILT: RX Filter Failed
+ * - EMAC_RINFO_MCAST: Multicast Frame
+ * - EMAC_RINFO_BCAST: Broadcast Frame
+ * - EMAC_RINFO_CRC_ERR: CRC Error in Frame
+ * - EMAC_RINFO_SYM_ERR: Symbol Error from PHY
+ * - EMAC_RINFO_LEN_ERR: Length Error
+ * - EMAC_RINFO_RANGE_ERR: Range error(exceeded max size)
+ * - EMAC_RINFO_ALIGN_ERR: Alignment error
+ * - EMAC_RINFO_OVERRUN: Receive overrun
+ * - EMAC_RINFO_NO_DESCR: No new Descriptor available
+ * - EMAC_RINFO_LAST_FLAG: last Fragment in Frame
+ * - EMAC_RINFO_ERR: Error Occurred (OR of all error)
+ * @return Current value of receive data (due to RxConsumeIndex)
+ **********************************************************************/
+FlagStatus EMAC_CheckReceiveDataStatus(uint32_t ulRxStatType)
+{
+ uint32_t idx;
+ idx = LPC_EMAC->RxConsumeIndex;
+ return (((Rx_Stat[idx].Info) & ulRxStatType) ? SET : RESET);
+}
+
+
+/*********************************************************************//**
+ * @brief Get size of current Received data in received buffer (due to
+ * RxConsumeIndex)
+ * @param[in] None
+ * @return Size of received data
+ **********************************************************************/
+uint32_t EMAC_GetReceiveDataSize(void)
+{
+ uint32_t idx;
+ idx =LPC_EMAC->RxConsumeIndex;
+ return ((Rx_Stat[idx].Info) & EMAC_RINFO_SIZE);
+}
+
+/*********************************************************************//**
+ * @brief Increase the RxConsumeIndex (after reading the Receive buffer
+ * to release the Receive buffer) and wrap-around the index if
+ * it reaches the maximum Receive Number
+ * @param[in] None
+ * @return None
+ **********************************************************************/
+void EMAC_UpdateRxConsumeIndex(void)
+{
+ // Get current Rx consume index
+ uint32_t idx = LPC_EMAC->RxConsumeIndex;
+
+ /* Release frame from EMAC buffer */
+ if (++idx == EMAC_NUM_RX_FRAG) idx = 0;
+ LPC_EMAC->RxConsumeIndex = idx;
+}
+
+/*********************************************************************//**
+ * @brief Increase the TxProduceIndex (after writting to the Transmit buffer
+ * to enable the Transmit buffer) and wrap-around the index if
+ * it reaches the maximum Transmit Number
+ * @param[in] None
+ * @return None
+ **********************************************************************/
+void EMAC_UpdateTxProduceIndex(void)
+{
+ // Get current Tx produce index
+ uint32_t idx = LPC_EMAC->TxProduceIndex;
+
+ /* Start frame transmission */
+ if (++idx == EMAC_NUM_TX_FRAG) idx = 0;
+ LPC_EMAC->TxProduceIndex = idx;
+}
+
+
+/**
+ * @}
+ */
+
+#endif /* _EMAC */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/src/shared/cmsis/Drivers/source/lpc17xx_exti.c b/src/shared/cmsis/Drivers/source/lpc17xx_exti.c
@@ -0,0 +1,171 @@
+/**********************************************************************
+* $Id$ lpc17xx_exti.c 2010-06-18
+*//**
+* @file lpc17xx_exti.c
+* @brief Contains all functions support for External interrupt firmware
+* library on LPC17xx
+* @version 3.0
+* @date 18. June. 2010
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2010, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @addtogroup EXTI
+ * @{
+ */
+
+/* Includes ------------------------------------------------------------------- */
+#include "lpc17xx_exti.h"
+
+/* If this source file built with example, the LPC17xx FW library configuration
+ * file in each example directory ("lpc17xx_libcfg.h") must be included,
+ * otherwise the default FW library configuration file must be included instead
+ */
+#ifdef __BUILD_WITH_EXAMPLE__
+#include "lpc17xx_libcfg.h"
+#else
+#include "lpc17xx_libcfg_default.h"
+#endif /* __BUILD_WITH_EXAMPLE__ */
+
+
+#ifdef _EXTI
+
+/* Public Functions ----------------------------------------------------------- */
+/** @addtogroup EXTI_Public_Functions
+ * @{
+ */
+
+/*********************************************************************//**
+ * @brief Initial for EXT
+ * - Set EXTINT, EXTMODE, EXTPOLAR registers to default value
+ * @param[in] None
+ * @return None
+ **********************************************************************/
+void EXTI_Init(void)
+{
+ LPC_SC->EXTINT = 0xF;
+ LPC_SC->EXTMODE = 0x0;
+ LPC_SC->EXTPOLAR = 0x0;
+}
+
+
+/*********************************************************************//**
+* @brief Close EXT
+* @param[in] None
+* @return None
+**********************************************************************/
+void EXTI_DeInit(void)
+{
+ ;
+}
+
+/*********************************************************************//**
+ * @brief Configuration for EXT
+ * - Set EXTINT, EXTMODE, EXTPOLAR register
+ * @param[in] EXTICfg Pointer to a EXTI_InitTypeDef structure
+ * that contains the configuration information for the
+ * specified external interrupt
+ * @return None
+ **********************************************************************/
+void EXTI_Config(EXTI_InitTypeDef *EXTICfg)
+{
+ LPC_SC->EXTINT = 0x0;
+ EXTI_SetMode(EXTICfg->EXTI_Line, EXTICfg->EXTI_Mode);
+ EXTI_SetPolarity(EXTICfg->EXTI_Line, EXTICfg->EXTI_polarity);
+}
+
+/*********************************************************************//**
+* @brief Set mode for EXTI pin
+* @param[in] EXTILine external interrupt line, should be:
+* - EXTI_EINT0: external interrupt line 0
+* - EXTI_EINT1: external interrupt line 1
+* - EXTI_EINT2: external interrupt line 2
+* - EXTI_EINT3: external interrupt line 3
+* @param[in] mode external mode, should be:
+* - EXTI_MODE_LEVEL_SENSITIVE
+* - EXTI_MODE_EDGE_SENSITIVE
+* @return None
+*********************************************************************/
+void EXTI_SetMode(EXTI_LINE_ENUM EXTILine, EXTI_MODE_ENUM mode)
+{
+ if(mode == EXTI_MODE_EDGE_SENSITIVE)
+ {
+ LPC_SC->EXTMODE |= (1 << EXTILine);
+ }
+ else if(mode == EXTI_MODE_LEVEL_SENSITIVE)
+ {
+ LPC_SC->EXTMODE &= ~(1 << EXTILine);
+ }
+}
+
+/*********************************************************************//**
+* @brief Set polarity for EXTI pin
+* @param[in] EXTILine external interrupt line, should be:
+* - EXTI_EINT0: external interrupt line 0
+* - EXTI_EINT1: external interrupt line 1
+* - EXTI_EINT2: external interrupt line 2
+* - EXTI_EINT3: external interrupt line 3
+* @param[in] polarity external polarity value, should be:
+* - EXTI_POLARITY_LOW_ACTIVE_OR_FALLING_EDGE
+* - EXTI_POLARITY_LOW_ACTIVE_OR_FALLING_EDGE
+* @return None
+*********************************************************************/
+void EXTI_SetPolarity(EXTI_LINE_ENUM EXTILine, EXTI_POLARITY_ENUM polarity)
+{
+ if(polarity == EXTI_POLARITY_HIGH_ACTIVE_OR_RISING_EDGE)
+ {
+ LPC_SC->EXTPOLAR |= (1 << EXTILine);
+ }
+ else if(polarity == EXTI_POLARITY_LOW_ACTIVE_OR_FALLING_EDGE)
+ {
+ LPC_SC->EXTPOLAR &= ~(1 << EXTILine);
+ }
+}
+
+/*********************************************************************//**
+* @brief Clear External interrupt flag
+* @param[in] EXTILine external interrupt line, should be:
+* - EXTI_EINT0: external interrupt line 0
+* - EXTI_EINT1: external interrupt line 1
+* - EXTI_EINT2: external interrupt line 2
+* - EXTI_EINT3: external interrupt line 3
+* @return None
+*********************************************************************/
+void EXTI_ClearEXTIFlag(EXTI_LINE_ENUM EXTILine)
+{
+ LPC_SC->EXTINT = (1 << EXTILine);
+}
+
+/**
+ * @}
+ */
+
+#endif /* _EXTI */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
+
diff --git a/src/shared/cmsis/Drivers/source/lpc17xx_gpdma.c b/src/shared/cmsis/Drivers/source/lpc17xx_gpdma.c
@@ -0,0 +1,463 @@
+/**********************************************************************
+* $Id$ lpc17xx_gpdma.c 2010-03-21
+*//**
+* @file lpc17xx_gpdma.c
+* @brief Contains all functions support for GPDMA firmware
+* library on LPC17xx
+* @version 2.1
+* @date 25. July. 2011
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2010, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @addtogroup GPDMA
+ * @{
+ */
+
+/* Includes ------------------------------------------------------------------- */
+#include "lpc17xx_gpdma.h"
+#include "lpc17xx_clkpwr.h"
+
+/* If this source file built with example, the LPC17xx FW library configuration
+ * file in each example directory ("lpc17xx_libcfg.h") must be included,
+ * otherwise the default FW library configuration file must be included instead
+ */
+#ifdef __BUILD_WITH_EXAMPLE__
+#include "lpc17xx_libcfg.h"
+#else
+#include "lpc17xx_libcfg_default.h"
+#endif /* __BUILD_WITH_EXAMPLE__ */
+
+#ifdef _GPDMA
+
+
+/* Private Variables ---------------------------------------------------------- */
+/** @defgroup GPDMA_Private_Variables GPDMA Private Variables
+ * @{
+ */
+
+/**
+ * @brief Lookup Table of Connection Type matched with
+ * Peripheral Data (FIFO) register base address
+ */
+//#ifdef __IAR_SYSTEMS_ICC__
+volatile const void *GPDMA_LUTPerAddr[] = {
+ (&LPC_SSP0->DR), // SSP0 Tx
+ (&LPC_SSP0->DR), // SSP0 Rx
+ (&LPC_SSP1->DR), // SSP1 Tx
+ (&LPC_SSP1->DR), // SSP1 Rx
+ (&LPC_ADC->ADGDR), // ADC
+ (&LPC_I2S->I2STXFIFO), // I2S Tx
+ (&LPC_I2S->I2SRXFIFO), // I2S Rx
+ (&LPC_DAC->DACR), // DAC
+ (&LPC_UART0->/*RBTHDLR.*/THR), // UART0 Tx
+ (&LPC_UART0->/*RBTHDLR.*/RBR), // UART0 Rx
+ (&LPC_UART1->/*RBTHDLR.*/THR), // UART1 Tx
+ (&LPC_UART1->/*RBTHDLR.*/RBR), // UART1 Rx
+ (&LPC_UART2->/*RBTHDLR.*/THR), // UART2 Tx
+ (&LPC_UART2->/*RBTHDLR.*/RBR), // UART2 Rx
+ (&LPC_UART3->/*RBTHDLR.*/THR), // UART3 Tx
+ (&LPC_UART3->/*RBTHDLR.*/RBR), // UART3 Rx
+ (&LPC_TIM0->MR0), // MAT0.0
+ (&LPC_TIM0->MR1), // MAT0.1
+ (&LPC_TIM1->MR0), // MAT1.0
+ (&LPC_TIM1->MR1), // MAT1.1
+ (&LPC_TIM2->MR0), // MAT2.0
+ (&LPC_TIM2->MR1), // MAT2.1
+ (&LPC_TIM3->MR0), // MAT3.0
+ (&LPC_TIM3->MR1) // MAT3.1
+};
+//#else
+//const uint32_t GPDMA_LUTPerAddr[] = {
+// ((uint32_t)&LPC_SSP0->DR), // SSP0 Tx
+// ((uint32_t)&LPC_SSP0->DR), // SSP0 Rx
+// ((uint32_t)&LPC_SSP1->DR), // SSP1 Tx
+// ((uint32_t)&LPC_SSP1->DR), // SSP1 Rx
+// ((uint32_t)&LPC_ADC->ADGDR), // ADC
+// ((uint32_t)&LPC_I2S->I2STXFIFO), // I2S Tx
+// ((uint32_t)&LPC_I2S->I2SRXFIFO), // I2S Rx
+// ((uint32_t)&LPC_DAC->DACR), // DAC
+// ((uint32_t)&LPC_UART0->/*RBTHDLR.*/THR), // UART0 Tx
+// ((uint32_t)&LPC_UART0->/*RBTHDLR.*/RBR), // UART0 Rx
+// ((uint32_t)&LPC_UART1->/*RBTHDLR.*/THR), // UART1 Tx
+// ((uint32_t)&LPC_UART1->/*RBTHDLR.*/RBR), // UART1 Rx
+// ((uint32_t)&LPC_UART2->/*RBTHDLR.*/THR), // UART2 Tx
+// ((uint32_t)&LPC_UART2->/*RBTHDLR.*/RBR), // UART2 Rx
+// ((uint32_t)&LPC_UART3->/*RBTHDLR.*/THR), // UART3 Tx
+// ((uint32_t)&LPC_UART3->/*RBTHDLR.*/RBR), // UART3 Rx
+// ((uint32_t)&LPC_TIM0->MR0), // MAT0.0
+// ((uint32_t)&LPC_TIM0->MR1), // MAT0.1
+// ((uint32_t)&LPC_TIM1->MR0), // MAT1.0
+// ((uint32_t)&LPC_TIM1->MR1), // MAT1.1
+// ((uint32_t)&LPC_TIM2->MR0), // MAT2.0
+// ((uint32_t)&LPC_TIM2->MR1), // MAT2.1
+// ((uint32_t)&LPC_TIM3->MR0), // MAT3.0
+// ((uint32_t)&LPC_TIM3->MR1) // MAT3.1
+//};
+//#endif
+/**
+ * @brief Lookup Table of GPDMA Channel Number matched with
+ * GPDMA channel pointer
+ */
+const LPC_GPDMACH_TypeDef *pGPDMACh[8] = {
+ LPC_GPDMACH0, // GPDMA Channel 0
+ LPC_GPDMACH1, // GPDMA Channel 1
+ LPC_GPDMACH2, // GPDMA Channel 2
+ LPC_GPDMACH3, // GPDMA Channel 3
+ LPC_GPDMACH4, // GPDMA Channel 4
+ LPC_GPDMACH5, // GPDMA Channel 5
+ LPC_GPDMACH6, // GPDMA Channel 6
+ LPC_GPDMACH7 // GPDMA Channel 7
+};
+/**
+ * @brief Optimized Peripheral Source and Destination burst size
+ */
+const uint8_t GPDMA_LUTPerBurst[] = {
+ GPDMA_BSIZE_4, // SSP0 Tx
+ GPDMA_BSIZE_4, // SSP0 Rx
+ GPDMA_BSIZE_4, // SSP1 Tx
+ GPDMA_BSIZE_4, // SSP1 Rx
+ GPDMA_BSIZE_1, // ADC
+ GPDMA_BSIZE_32, // I2S channel 0
+ GPDMA_BSIZE_32, // I2S channel 1
+ GPDMA_BSIZE_1, // DAC
+ GPDMA_BSIZE_1, // UART0 Tx
+ GPDMA_BSIZE_1, // UART0 Rx
+ GPDMA_BSIZE_1, // UART1 Tx
+ GPDMA_BSIZE_1, // UART1 Rx
+ GPDMA_BSIZE_1, // UART2 Tx
+ GPDMA_BSIZE_1, // UART2 Rx
+ GPDMA_BSIZE_1, // UART3 Tx
+ GPDMA_BSIZE_1, // UART3 Rx
+ GPDMA_BSIZE_1, // MAT0.0
+ GPDMA_BSIZE_1, // MAT0.1
+ GPDMA_BSIZE_1, // MAT1.0
+ GPDMA_BSIZE_1, // MAT1.1
+ GPDMA_BSIZE_1, // MAT2.0
+ GPDMA_BSIZE_1, // MAT2.1
+ GPDMA_BSIZE_1, // MAT3.0
+ GPDMA_BSIZE_1 // MAT3.1
+};
+/**
+ * @brief Optimized Peripheral Source and Destination transfer width
+ */
+const uint8_t GPDMA_LUTPerWid[] = {
+ GPDMA_WIDTH_BYTE, // SSP0 Tx
+ GPDMA_WIDTH_BYTE, // SSP0 Rx
+ GPDMA_WIDTH_BYTE, // SSP1 Tx
+ GPDMA_WIDTH_BYTE, // SSP1 Rx
+ GPDMA_WIDTH_WORD, // ADC
+ GPDMA_WIDTH_WORD, // I2S channel 0
+ GPDMA_WIDTH_WORD, // I2S channel 1
+ GPDMA_WIDTH_BYTE, // DAC
+ GPDMA_WIDTH_BYTE, // UART0 Tx
+ GPDMA_WIDTH_BYTE, // UART0 Rx
+ GPDMA_WIDTH_BYTE, // UART1 Tx
+ GPDMA_WIDTH_BYTE, // UART1 Rx
+ GPDMA_WIDTH_BYTE, // UART2 Tx
+ GPDMA_WIDTH_BYTE, // UART2 Rx
+ GPDMA_WIDTH_BYTE, // UART3 Tx
+ GPDMA_WIDTH_BYTE, // UART3 Rx
+ GPDMA_WIDTH_WORD, // MAT0.0
+ GPDMA_WIDTH_WORD, // MAT0.1
+ GPDMA_WIDTH_WORD, // MAT1.0
+ GPDMA_WIDTH_WORD, // MAT1.1
+ GPDMA_WIDTH_WORD, // MAT2.0
+ GPDMA_WIDTH_WORD, // MAT2.1
+ GPDMA_WIDTH_WORD, // MAT3.0
+ GPDMA_WIDTH_WORD // MAT3.1
+};
+
+/**
+ * @}
+ */
+
+/* Public Functions ----------------------------------------------------------- */
+/** @addtogroup GPDMA_Public_Functions
+ * @{
+ */
+
+/********************************************************************//**
+ * @brief Initialize GPDMA controller
+ * @param None
+ * @return None
+ *********************************************************************/
+void GPDMA_Init(void)
+{
+ /* Enable GPDMA clock */
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCGPDMA, ENABLE);
+
+ // Reset all channel configuration register
+ LPC_GPDMACH0->DMACCConfig = 0;
+ LPC_GPDMACH1->DMACCConfig = 0;
+ LPC_GPDMACH2->DMACCConfig = 0;
+ LPC_GPDMACH3->DMACCConfig = 0;
+ LPC_GPDMACH4->DMACCConfig = 0;
+ LPC_GPDMACH5->DMACCConfig = 0;
+ LPC_GPDMACH6->DMACCConfig = 0;
+ LPC_GPDMACH7->DMACCConfig = 0;
+
+ /* Clear all DMA interrupt and error flag */
+ LPC_GPDMA->DMACIntTCClear = 0xFF;
+ LPC_GPDMA->DMACIntErrClr = 0xFF;
+}
+
+/********************************************************************//**
+ * @brief Setup GPDMA channel peripheral according to the specified
+ * parameters in the GPDMAChannelConfig.
+ * @param[in] GPDMAChannelConfig Pointer to a GPDMA_CH_CFG_Type
+ * structure that contains the configuration
+ * information for the specified GPDMA channel peripheral.
+ * @return ERROR if selected channel is enabled before
+ * or SUCCESS if channel is configured successfully
+ *********************************************************************/
+Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig)
+{
+ LPC_GPDMACH_TypeDef *pDMAch;
+ uint32_t tmp1, tmp2;
+
+ if (LPC_GPDMA->DMACEnbldChns & (GPDMA_DMACEnbldChns_Ch(GPDMAChannelConfig->ChannelNum))) {
+ // This channel is enabled, return ERROR, need to release this channel first
+ return ERROR;
+ }
+
+ // Get Channel pointer
+ pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[GPDMAChannelConfig->ChannelNum];
+
+ // Reset the Interrupt status
+ LPC_GPDMA->DMACIntTCClear = GPDMA_DMACIntTCClear_Ch(GPDMAChannelConfig->ChannelNum);
+ LPC_GPDMA->DMACIntErrClr = GPDMA_DMACIntErrClr_Ch(GPDMAChannelConfig->ChannelNum);
+
+ // Clear DMA configure
+ pDMAch->DMACCControl = 0x00;
+ pDMAch->DMACCConfig = 0x00;
+
+ /* Assign Linker List Item value */
+ pDMAch->DMACCLLI = GPDMAChannelConfig->DMALLI;
+
+ /* Set value to Channel Control Registers */
+ switch (GPDMAChannelConfig->TransferType)
+ {
+ // Memory to memory
+ case GPDMA_TRANSFERTYPE_M2M:
+ // Assign physical source and destination address
+ pDMAch->DMACCSrcAddr = GPDMAChannelConfig->SrcMemAddr;
+ pDMAch->DMACCDestAddr = GPDMAChannelConfig->DstMemAddr;
+ pDMAch->DMACCControl
+ = GPDMA_DMACCxControl_TransferSize(GPDMAChannelConfig->TransferSize) \
+ | GPDMA_DMACCxControl_SBSize(GPDMA_BSIZE_32) \
+ | GPDMA_DMACCxControl_DBSize(GPDMA_BSIZE_32) \
+ | GPDMA_DMACCxControl_SWidth(GPDMAChannelConfig->TransferWidth) \
+ | GPDMA_DMACCxControl_DWidth(GPDMAChannelConfig->TransferWidth) \
+ | GPDMA_DMACCxControl_SI \
+ | GPDMA_DMACCxControl_DI \
+ | GPDMA_DMACCxControl_I;
+ break;
+ // Memory to peripheral
+ case GPDMA_TRANSFERTYPE_M2P:
+ // Assign physical source
+ pDMAch->DMACCSrcAddr = GPDMAChannelConfig->SrcMemAddr;
+ // Assign peripheral destination address
+ pDMAch->DMACCDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn];
+ pDMAch->DMACCControl
+ = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
+ | GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
+ | GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
+ | GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
+ | GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
+ | GPDMA_DMACCxControl_SI \
+ | GPDMA_DMACCxControl_I;
+ break;
+ // Peripheral to memory
+ case GPDMA_TRANSFERTYPE_P2M:
+ // Assign peripheral source address
+ pDMAch->DMACCSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn];
+ // Assign memory destination address
+ pDMAch->DMACCDestAddr = GPDMAChannelConfig->DstMemAddr;
+ pDMAch->DMACCControl
+ = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
+ | GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
+ | GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
+ | GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
+ | GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
+ | GPDMA_DMACCxControl_DI \
+ | GPDMA_DMACCxControl_I;
+ break;
+ // Peripheral to peripheral
+ case GPDMA_TRANSFERTYPE_P2P:
+ // Assign peripheral source address
+ pDMAch->DMACCSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn];
+ // Assign peripheral destination address
+ pDMAch->DMACCDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn];
+ pDMAch->DMACCControl
+ = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
+ | GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
+ | GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
+ | GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
+ | GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
+ | GPDMA_DMACCxControl_I;
+ break;
+ // Do not support any more transfer type, return ERROR
+ default:
+ return ERROR;
+ }
+
+ /* Re-Configure DMA Request Select for source peripheral */
+ if (GPDMAChannelConfig->SrcConn > 15)
+ {
+ LPC_SC->DMAREQSEL |= (1<<(GPDMAChannelConfig->SrcConn - 16));
+ } else {
+ LPC_SC->DMAREQSEL &= ~(1<<(GPDMAChannelConfig->SrcConn - 8));
+ }
+
+ /* Re-Configure DMA Request Select for Destination peripheral */
+ if (GPDMAChannelConfig->DstConn > 15)
+ {
+ LPC_SC->DMAREQSEL |= (1<<(GPDMAChannelConfig->DstConn - 16));
+ } else {
+ LPC_SC->DMAREQSEL &= ~(1<<(GPDMAChannelConfig->DstConn - 8));
+ }
+
+ /* Enable DMA channels, little endian */
+ LPC_GPDMA->DMACConfig = GPDMA_DMACConfig_E;
+ while (!(LPC_GPDMA->DMACConfig & GPDMA_DMACConfig_E));
+
+ // Calculate absolute value for Connection number
+ tmp1 = GPDMAChannelConfig->SrcConn;
+ tmp1 = ((tmp1 > 15) ? (tmp1 - 8) : tmp1);
+ tmp2 = GPDMAChannelConfig->DstConn;
+ tmp2 = ((tmp2 > 15) ? (tmp2 - 8) : tmp2);
+
+ // Configure DMA Channel, enable Error Counter and Terminate counter
+ pDMAch->DMACCConfig = GPDMA_DMACCxConfig_IE | GPDMA_DMACCxConfig_ITC /*| GPDMA_DMACCxConfig_E*/ \
+ | GPDMA_DMACCxConfig_TransferType((uint32_t)GPDMAChannelConfig->TransferType) \
+ | GPDMA_DMACCxConfig_SrcPeripheral(tmp1) \
+ | GPDMA_DMACCxConfig_DestPeripheral(tmp2);
+
+ return SUCCESS;
+}
+
+
+/*********************************************************************//**
+ * @brief Enable/Disable DMA channel
+ * @param[in] channelNum GPDMA channel, should be in range from 0 to 7
+ * @param[in] NewState New State of this command, should be:
+ * - ENABLE.
+ * - DISABLE.
+ * @return None
+ **********************************************************************/
+void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState)
+{
+ LPC_GPDMACH_TypeDef *pDMAch;
+
+ // Get Channel pointer
+ pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[channelNum];
+
+ if (NewState == ENABLE) {
+ pDMAch->DMACCConfig |= GPDMA_DMACCxConfig_E;
+ } else {
+ pDMAch->DMACCConfig &= ~GPDMA_DMACCxConfig_E;
+ }
+}
+/*********************************************************************//**
+ * @brief Check if corresponding channel does have an active interrupt
+ * request or not
+ * @param[in] type type of status, should be:
+ * - GPDMA_STAT_INT: GPDMA Interrupt Status
+ * - GPDMA_STAT_INTTC: GPDMA Interrupt Terminal Count Request Status
+ * - GPDMA_STAT_INTERR: GPDMA Interrupt Error Status
+ * - GPDMA_STAT_RAWINTTC: GPDMA Raw Interrupt Terminal Count Status
+ * - GPDMA_STAT_RAWINTERR: GPDMA Raw Error Interrupt Status
+ * - GPDMA_STAT_ENABLED_CH:GPDMA Enabled Channel Status
+ * @param[in] channel GPDMA channel, should be in range from 0 to 7
+ * @return IntStatus status of DMA channel interrupt after masking
+ * Should be:
+ * - SET: the corresponding channel has no active interrupt request
+ * - RESET: the corresponding channel does have an active interrupt request
+ **********************************************************************/
+IntStatus GPDMA_IntGetStatus(GPDMA_Status_Type type, uint8_t channel)
+{
+ CHECK_PARAM(PARAM_GPDMA_STAT(type));
+ CHECK_PARAM(PARAM_GPDMA_CHANNEL(channel));
+
+ switch (type)
+ {
+ case GPDMA_STAT_INT: //check status of DMA channel interrupts
+ if (LPC_GPDMA->DMACIntStat & (GPDMA_DMACIntStat_Ch(channel)))
+ return SET;
+ return RESET;
+ case GPDMA_STAT_INTTC: // check terminal count interrupt request status for DMA
+ if (LPC_GPDMA->DMACIntTCStat & GPDMA_DMACIntTCStat_Ch(channel))
+ return SET;
+ return RESET;
+ case GPDMA_STAT_INTERR: //check interrupt status for DMA channels
+ if (LPC_GPDMA->DMACIntErrStat & GPDMA_DMACIntTCClear_Ch(channel))
+ return SET;
+ return RESET;
+ case GPDMA_STAT_RAWINTTC: //check status of the terminal count interrupt for DMA channels
+ if (LPC_GPDMA->DMACRawIntErrStat & GPDMA_DMACRawIntTCStat_Ch(channel))
+ return SET;
+ return RESET;
+ case GPDMA_STAT_RAWINTERR: //check status of the error interrupt for DMA channels
+ if (LPC_GPDMA->DMACRawIntTCStat & GPDMA_DMACRawIntErrStat_Ch(channel))
+ return SET;
+ return RESET;
+ default: //check enable status for DMA channels
+ if (LPC_GPDMA->DMACEnbldChns & GPDMA_DMACEnbldChns_Ch(channel))
+ return SET;
+ return RESET;
+ }
+}
+
+/*********************************************************************//**
+ * @brief Clear one or more interrupt requests on DMA channels
+ * @param[in] type type of interrupt request, should be:
+ * - GPDMA_STATCLR_INTTC: GPDMA Interrupt Terminal Count Request Clear
+ * - GPDMA_STATCLR_INTERR: GPDMA Interrupt Error Clear
+ * @param[in] channel GPDMA channel, should be in range from 0 to 7
+ * @return None
+ **********************************************************************/
+void GPDMA_ClearIntPending(GPDMA_StateClear_Type type, uint8_t channel)
+{
+ CHECK_PARAM(PARAM_GPDMA_STATCLR(type));
+ CHECK_PARAM(PARAM_GPDMA_CHANNEL(channel));
+
+ if (type == GPDMA_STATCLR_INTTC) // clears the terminal count interrupt request on DMA channel
+ LPC_GPDMA->DMACIntTCClear = GPDMA_DMACIntTCClear_Ch(channel);
+ else // clear the error interrupt request
+ LPC_GPDMA->DMACIntErrClr = GPDMA_DMACIntErrClr_Ch(channel);
+}
+
+/**
+ * @}
+ */
+
+#endif /* _GPDMA */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
+
diff --git a/src/shared/cmsis/Drivers/source/lpc17xx_gpio.c b/src/shared/cmsis/Drivers/source/lpc17xx_gpio.c
@@ -0,0 +1,762 @@
+/**********************************************************************
+* $Id$ lpc17xx_gpio.c 2010-05-21
+*//**
+* @file lpc17xx_gpio.c
+* @brief Contains all functions support for GPIO firmware
+* library on LPC17xx
+* @version 2.0
+* @date 21. May. 2010
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2010, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @addtogroup GPIO
+ * @{
+ */
+
+/* Includes ------------------------------------------------------------------- */
+#include "lpc17xx_gpio.h"
+
+/* If this source file built with example, the LPC17xx FW library configuration
+ * file in each example directory ("lpc17xx_libcfg.h") must be included,
+ * otherwise the default FW library configuration file must be included instead
+ */
+#ifdef __BUILD_WITH_EXAMPLE__
+#include "lpc17xx_libcfg.h"
+#else
+#include "lpc17xx_libcfg_default.h"
+#endif /* __BUILD_WITH_EXAMPLE__ */
+
+
+#ifdef _GPIO
+
+/* Private Functions ---------------------------------------------------------- */
+
+static LPC_GPIO_TypeDef *GPIO_GetPointer(uint8_t portNum);
+static GPIO_HalfWord_TypeDef *FIO_HalfWordGetPointer(uint8_t portNum);
+static GPIO_Byte_TypeDef *FIO_ByteGetPointer(uint8_t portNum);
+
+/*********************************************************************//**
+ * @brief Get pointer to GPIO peripheral due to GPIO port
+ * @param[in] portNum Port Number value, should be in range from 0 to 4.
+ * @return Pointer to GPIO peripheral
+ **********************************************************************/
+static LPC_GPIO_TypeDef *GPIO_GetPointer(uint8_t portNum)
+{
+ LPC_GPIO_TypeDef *pGPIO = NULL;
+
+ switch (portNum) {
+ case 0:
+ pGPIO = LPC_GPIO0;
+ break;
+ case 1:
+ pGPIO = LPC_GPIO1;
+ break;
+ case 2:
+ pGPIO = LPC_GPIO2;
+ break;
+ case 3:
+ pGPIO = LPC_GPIO3;
+ break;
+ case 4:
+ pGPIO = LPC_GPIO4;
+ break;
+ default:
+ break;
+ }
+
+ return pGPIO;
+}
+
+/*********************************************************************//**
+ * @brief Get pointer to FIO peripheral in halfword accessible style
+ * due to FIO port
+ * @param[in] portNum Port Number value, should be in range from 0 to 4.
+ * @return Pointer to FIO peripheral
+ **********************************************************************/
+static GPIO_HalfWord_TypeDef *FIO_HalfWordGetPointer(uint8_t portNum)
+{
+ GPIO_HalfWord_TypeDef *pFIO = NULL;
+
+ switch (portNum) {
+ case 0:
+ pFIO = GPIO0_HalfWord;
+ break;
+ case 1:
+ pFIO = GPIO1_HalfWord;
+ break;
+ case 2:
+ pFIO = GPIO2_HalfWord;
+ break;
+ case 3:
+ pFIO = GPIO3_HalfWord;
+ break;
+ case 4:
+ pFIO = GPIO4_HalfWord;
+ break;
+ default:
+ break;
+ }
+
+ return pFIO;
+}
+
+/*********************************************************************//**
+ * @brief Get pointer to FIO peripheral in byte accessible style
+ * due to FIO port
+ * @param[in] portNum Port Number value, should be in range from 0 to 4.
+ * @return Pointer to FIO peripheral
+ **********************************************************************/
+static GPIO_Byte_TypeDef *FIO_ByteGetPointer(uint8_t portNum)
+{
+ GPIO_Byte_TypeDef *pFIO = NULL;
+
+ switch (portNum) {
+ case 0:
+ pFIO = GPIO0_Byte;
+ break;
+ case 1:
+ pFIO = GPIO1_Byte;
+ break;
+ case 2:
+ pFIO = GPIO2_Byte;
+ break;
+ case 3:
+ pFIO = GPIO3_Byte;
+ break;
+ case 4:
+ pFIO = GPIO4_Byte;
+ break;
+ default:
+ break;
+ }
+
+ return pFIO;
+}
+
+/* End of Private Functions --------------------------------------------------- */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @addtogroup GPIO_Public_Functions
+ * @{
+ */
+
+
+/* GPIO ------------------------------------------------------------------------------ */
+
+/*********************************************************************//**
+ * @brief Set Direction for GPIO port.
+ * @param[in] portNum Port Number value, should be in range from 0 to 4
+ * @param[in] bitValue Value that contains all bits to set direction,
+ * in range from 0 to 0xFFFFFFFF.
+ * example: value 0x5 to set direction for bit 0 and bit 1.
+ * @param[in] dir Direction value, should be:
+ * - 0: Input.
+ * - 1: Output.
+ * @return None
+ *
+ * Note: All remaining bits that are not activated in bitValue (value '0')
+ * will not be effected by this function.
+ **********************************************************************/
+void GPIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t dir)
+{
+ LPC_GPIO_TypeDef *pGPIO = GPIO_GetPointer(portNum);
+
+ if (pGPIO != NULL) {
+ // Enable Output
+ if (dir) {
+ pGPIO->FIODIR |= bitValue;
+ }
+ // Enable Input
+ else {
+ pGPIO->FIODIR &= ~bitValue;
+ }
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Set Value for bits that have output direction on GPIO port.
+ * @param[in] portNum Port number value, should be in range from 0 to 4
+ * @param[in] bitValue Value that contains all bits on GPIO to set,
+ * in range from 0 to 0xFFFFFFFF.
+ * example: value 0x5 to set bit 0 and bit 1.
+ * @return None
+ *
+ * Note:
+ * - For all bits that has been set as input direction, this function will
+ * not effect.
+ * - For all remaining bits that are not activated in bitValue (value '0')
+ * will not be effected by this function.
+ **********************************************************************/
+void GPIO_SetValue(uint8_t portNum, uint32_t bitValue)
+{
+ LPC_GPIO_TypeDef *pGPIO = GPIO_GetPointer(portNum);
+
+ if (pGPIO != NULL) {
+ pGPIO->FIOSET = bitValue;
+ }
+}
+
+/*********************************************************************//**
+ * @brief Clear Value for bits that have output direction on GPIO port.
+ * @param[in] portNum Port number value, should be in range from 0 to 4
+ * @param[in] bitValue Value that contains all bits on GPIO to clear,
+ * in range from 0 to 0xFFFFFFFF.
+ * example: value 0x5 to clear bit 0 and bit 1.
+ * @return None
+ *
+ * Note:
+ * - For all bits that has been set as input direction, this function will
+ * not effect.
+ * - For all remaining bits that are not activated in bitValue (value '0')
+ * will not be effected by this function.
+ **********************************************************************/
+void GPIO_ClearValue(uint8_t portNum, uint32_t bitValue)
+{
+ LPC_GPIO_TypeDef *pGPIO = GPIO_GetPointer(portNum);
+
+ if (pGPIO != NULL) {
+ pGPIO->FIOCLR = bitValue;
+ }
+}
+
+/*********************************************************************//**
+ * @brief Read Current state on port pin that have input direction of GPIO
+ * @param[in] portNum Port number to read value, in range from 0 to 4
+ * @return Current value of GPIO port.
+ *
+ * Note: Return value contain state of each port pin (bit) on that GPIO regardless
+ * its direction is input or output.
+ **********************************************************************/
+uint32_t GPIO_ReadValue(uint8_t portNum)
+{
+ LPC_GPIO_TypeDef *pGPIO = GPIO_GetPointer(portNum);
+
+ if (pGPIO != NULL) {
+ return pGPIO->FIOPIN;
+ }
+
+ return (0);
+}
+
+/*********************************************************************//**
+ * @brief Enable GPIO interrupt (just used for P0.0-P0.30, P2.0-P2.13)
+ * @param[in] portNum Port number to read value, should be: 0 or 2
+ * @param[in] bitValue Value that contains all bits on GPIO to enable,
+ * in range from 0 to 0xFFFFFFFF.
+ * @param[in] edgeState state of edge, should be:
+ * - 0: Rising edge
+ * - 1: Falling edge
+ * @return None
+ **********************************************************************/
+void GPIO_IntCmd(uint8_t portNum, uint32_t bitValue, uint8_t edgeState)
+{
+ if((portNum == 0)&&(edgeState == 0))
+ LPC_GPIOINT->IO0IntEnR = bitValue;
+ else if ((portNum == 2)&&(edgeState == 0))
+ LPC_GPIOINT->IO2IntEnR = bitValue;
+ else if ((portNum == 0)&&(edgeState == 1))
+ LPC_GPIOINT->IO0IntEnF = bitValue;
+ else if ((portNum == 2)&&(edgeState == 1))
+ LPC_GPIOINT->IO2IntEnF = bitValue;
+ else
+ //Error
+ while(1);
+}
+
+/*********************************************************************//**
+ * @brief Get GPIO Interrupt Status (just used for P0.0-P0.30, P2.0-P2.13)
+ * @param[in] portNum Port number to read value, should be: 0 or 2
+ * @param[in] pinNum Pin number, should be: 0..30(with port 0) and 0..13
+ * (with port 2)
+ * @param[in] edgeState state of edge, should be:
+ * - 0: Rising edge
+ * - 1: Falling edge
+ * @return Bool could be:
+ * - ENABLE: Interrupt has been generated due to a rising
+ * edge on P0.0
+ * - DISABLE: A rising edge has not been detected on P0.0
+ **********************************************************************/
+FunctionalState GPIO_GetIntStatus(uint8_t portNum, uint32_t pinNum, uint8_t edgeState)
+{
+ if((portNum == 0) && (edgeState == 0))//Rising Edge
+ return ((FunctionalState)(((LPC_GPIOINT->IO0IntStatR)>>pinNum)& 0x1));
+ else if ((portNum == 2) && (edgeState == 0))
+ return ((FunctionalState)(((LPC_GPIOINT->IO2IntStatR)>>pinNum)& 0x1));
+ else if ((portNum == 0) && (edgeState == 1))//Falling Edge
+ return ((FunctionalState)(((LPC_GPIOINT->IO0IntStatF)>>pinNum)& 0x1));
+ else if ((portNum == 2) && (edgeState == 1))
+ return ((FunctionalState)(((LPC_GPIOINT->IO2IntStatF)>>pinNum)& 0x1));
+ else
+ //Error
+ while(1);
+}
+/*********************************************************************//**
+ * @brief Clear GPIO interrupt (just used for P0.0-P0.30, P2.0-P2.13)
+ * @param[in] portNum Port number to read value, should be: 0 or 2
+ * @param[in] bitValue Value that contains all bits on GPIO to enable,
+ * in range from 0 to 0xFFFFFFFF.
+ * @return None
+ **********************************************************************/
+void GPIO_ClearInt(uint8_t portNum, uint32_t bitValue)
+{
+ if(portNum == 0)
+ LPC_GPIOINT->IO0IntClr = bitValue;
+ else if (portNum == 2)
+ LPC_GPIOINT->IO2IntClr = bitValue;
+ else
+ //Invalid portNum
+ while(1);
+}
+
+/* FIO word accessible ----------------------------------------------------------------- */
+/* Stub function for FIO (word-accessible) style */
+
+/**
+ * @brief The same with GPIO_SetDir()
+ */
+void FIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t dir)
+{
+ GPIO_SetDir(portNum, bitValue, dir);
+}
+
+/**
+ * @brief The same with GPIO_SetValue()
+ */
+void FIO_SetValue(uint8_t portNum, uint32_t bitValue)
+{
+ GPIO_SetValue(portNum, bitValue);
+}
+
+/**
+ * @brief The same with GPIO_ClearValue()
+ */
+void FIO_ClearValue(uint8_t portNum, uint32_t bitValue)
+{
+ GPIO_ClearValue(portNum, bitValue);
+}
+
+/**
+ * @brief The same with GPIO_ReadValue()
+ */
+uint32_t FIO_ReadValue(uint8_t portNum)
+{
+ return (GPIO_ReadValue(portNum));
+}
+
+/**
+ * @brief The same with GPIO_IntCmd()
+ */
+void FIO_IntCmd(uint8_t portNum, uint32_t bitValue, uint8_t edgeState)
+{
+ GPIO_IntCmd(portNum, bitValue, edgeState);
+}
+
+/**
+ * @brief The same with GPIO_GetIntStatus()
+ */
+FunctionalState FIO_GetIntStatus(uint8_t portNum, uint32_t pinNum, uint8_t edgeState)
+{
+ return (GPIO_GetIntStatus(portNum, pinNum, edgeState));
+}
+
+/**
+ * @brief The same with GPIO_ClearInt()
+ */
+void FIO_ClearInt(uint8_t portNum, uint32_t bitValue)
+{
+ GPIO_ClearInt(portNum, bitValue);
+}
+/*********************************************************************//**
+ * @brief Set mask value for bits in FIO port
+ * @param[in] portNum Port number, in range from 0 to 4
+ * @param[in] bitValue Value that contains all bits in to set,
+ * in range from 0 to 0xFFFFFFFF.
+ * @param[in] maskValue Mask value contains state value for each bit:
+ * - 0: not mask.
+ * - 1: mask.
+ * @return None
+ *
+ * Note:
+ * - All remaining bits that are not activated in bitValue (value '0')
+ * will not be effected by this function.
+ * - After executing this function, in mask register, value '0' on each bit
+ * enables an access to the corresponding physical pin via a read or write access,
+ * while value '1' on bit (masked) that corresponding pin will not be changed
+ * with write access and if read, will not be reflected in the updated pin.
+ **********************************************************************/
+void FIO_SetMask(uint8_t portNum, uint32_t bitValue, uint8_t maskValue)
+{
+ LPC_GPIO_TypeDef *pFIO = GPIO_GetPointer(portNum);
+ if(pFIO != NULL) {
+ // Mask
+ if (maskValue){
+ pFIO->FIOMASK |= bitValue;
+ }
+ // Un-mask
+ else {
+ pFIO->FIOMASK &= ~bitValue;
+ }
+ }
+}
+
+
+/* FIO halfword accessible ------------------------------------------------------------- */
+
+/*********************************************************************//**
+ * @brief Set direction for FIO port in halfword accessible style
+ * @param[in] portNum Port number, in range from 0 to 4
+ * @param[in] halfwordNum HalfWord part number, should be 0 (lower) or 1(upper)
+ * @param[in] bitValue Value that contains all bits in to set direction,
+ * in range from 0 to 0xFFFF.
+ * @param[in] dir Direction value, should be:
+ * - 0: Input.
+ * - 1: Output.
+ * @return None
+ *
+ * Note: All remaining bits that are not activated in bitValue (value '0')
+ * will not be effected by this function.
+ **********************************************************************/
+void FIO_HalfWordSetDir(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue, uint8_t dir)
+{
+ GPIO_HalfWord_TypeDef *pFIO = FIO_HalfWordGetPointer(portNum);
+ if(pFIO != NULL) {
+ // Output direction
+ if (dir) {
+ // Upper
+ if(halfwordNum) {
+ pFIO->FIODIRU |= bitValue;
+ }
+ // lower
+ else {
+ pFIO->FIODIRL |= bitValue;
+ }
+ }
+ // Input direction
+ else {
+ // Upper
+ if(halfwordNum) {
+ pFIO->FIODIRU &= ~bitValue;
+ }
+ // lower
+ else {
+ pFIO->FIODIRL &= ~bitValue;
+ }
+ }
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Set mask value for bits in FIO port in halfword accessible style
+ * @param[in] portNum Port number, in range from 0 to 4
+ * @param[in] halfwordNum HalfWord part number, should be 0 (lower) or 1(upper)
+ * @param[in] bitValue Value that contains all bits in to set,
+ * in range from 0 to 0xFFFF.
+ * @param[in] maskValue Mask value contains state value for each bit:
+ * - 0: not mask.
+ * - 1: mask.
+ * @return None
+ *
+ * Note:
+ * - All remaining bits that are not activated in bitValue (value '0')
+ * will not be effected by this function.
+ * - After executing this function, in mask register, value '0' on each bit
+ * enables an access to the corresponding physical pin via a read or write access,
+ * while value '1' on bit (masked) that corresponding pin will not be changed
+ * with write access and if read, will not be reflected in the updated pin.
+ **********************************************************************/
+void FIO_HalfWordSetMask(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue, uint8_t maskValue)
+{
+ GPIO_HalfWord_TypeDef *pFIO = FIO_HalfWordGetPointer(portNum);
+ if(pFIO != NULL) {
+ // Mask
+ if (maskValue){
+ // Upper
+ if(halfwordNum) {
+ pFIO->FIOMASKU |= bitValue;
+ }
+ // lower
+ else {
+ pFIO->FIOMASKL |= bitValue;
+ }
+ }
+ // Un-mask
+ else {
+ // Upper
+ if(halfwordNum) {
+ pFIO->FIOMASKU &= ~bitValue;
+ }
+ // lower
+ else {
+ pFIO->FIOMASKL &= ~bitValue;
+ }
+ }
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Set bits for FIO port in halfword accessible style
+ * @param[in] portNum Port number, in range from 0 to 4
+ * @param[in] halfwordNum HalfWord part number, should be 0 (lower) or 1(upper)
+ * @param[in] bitValue Value that contains all bits in to set,
+ * in range from 0 to 0xFFFF.
+ * @return None
+ *
+ * Note:
+ * - For all bits that has been set as input direction, this function will
+ * not effect.
+ * - For all remaining bits that are not activated in bitValue (value '0')
+ * will not be effected by this function.
+ **********************************************************************/
+void FIO_HalfWordSetValue(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue)
+{
+ GPIO_HalfWord_TypeDef *pFIO = FIO_HalfWordGetPointer(portNum);
+ if(pFIO != NULL) {
+ // Upper
+ if(halfwordNum) {
+ pFIO->FIOSETU = bitValue;
+ }
+ // lower
+ else {
+ pFIO->FIOSETL = bitValue;
+ }
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Clear bits for FIO port in halfword accessible style
+ * @param[in] portNum Port number, in range from 0 to 4
+ * @param[in] halfwordNum HalfWord part number, should be 0 (lower) or 1(upper)
+ * @param[in] bitValue Value that contains all bits in to clear,
+ * in range from 0 to 0xFFFF.
+ * @return None
+ *
+ * Note:
+ * - For all bits that has been set as input direction, this function will
+ * not effect.
+ * - For all remaining bits that are not activated in bitValue (value '0')
+ * will not be effected by this function.
+ **********************************************************************/
+void FIO_HalfWordClearValue(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue)
+{
+ GPIO_HalfWord_TypeDef *pFIO = FIO_HalfWordGetPointer(portNum);
+ if(pFIO != NULL) {
+ // Upper
+ if(halfwordNum) {
+ pFIO->FIOCLRU = bitValue;
+ }
+ // lower
+ else {
+ pFIO->FIOCLRL = bitValue;
+ }
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Read Current state on port pin that have input direction of GPIO
+ * in halfword accessible style.
+ * @param[in] portNum Port number, in range from 0 to 4
+ * @param[in] halfwordNum HalfWord part number, should be 0 (lower) or 1(upper)
+ * @return Current value of FIO port pin of specified halfword.
+ * Note: Return value contain state of each port pin (bit) on that FIO regardless
+ * its direction is input or output.
+ **********************************************************************/
+uint16_t FIO_HalfWordReadValue(uint8_t portNum, uint8_t halfwordNum)
+{
+ GPIO_HalfWord_TypeDef *pFIO = FIO_HalfWordGetPointer(portNum);
+ if(pFIO != NULL) {
+ // Upper
+ if(halfwordNum) {
+ return (pFIO->FIOPINU);
+ }
+ // lower
+ else {
+ return (pFIO->FIOPINL);
+ }
+ }
+ return (0);
+}
+
+
+/* FIO Byte accessible ------------------------------------------------------------ */
+
+/*********************************************************************//**
+ * @brief Set direction for FIO port in byte accessible style
+ * @param[in] portNum Port number, in range from 0 to 4
+ * @param[in] byteNum Byte part number, should be in range from 0 to 3
+ * @param[in] bitValue Value that contains all bits in to set direction,
+ * in range from 0 to 0xFF.
+ * @param[in] dir Direction value, should be:
+ * - 0: Input.
+ * - 1: Output.
+ * @return None
+ *
+ * Note: All remaining bits that are not activated in bitValue (value '0')
+ * will not be effected by this function.
+ **********************************************************************/
+void FIO_ByteSetDir(uint8_t portNum, uint8_t byteNum, uint8_t bitValue, uint8_t dir)
+{
+ GPIO_Byte_TypeDef *pFIO = FIO_ByteGetPointer(portNum);
+ if(pFIO != NULL) {
+ // Output direction
+ if (dir) {
+ if (byteNum <= 3) {
+ pFIO->FIODIR[byteNum] |= bitValue;
+ }
+ }
+ // Input direction
+ else {
+ if (byteNum <= 3) {
+ pFIO->FIODIR[byteNum] &= ~bitValue;
+ }
+ }
+ }
+}
+
+/*********************************************************************//**
+ * @brief Set mask value for bits in FIO port in byte accessible style
+ * @param[in] portNum Port number, in range from 0 to 4
+ * @param[in] byteNum Byte part number, should be in range from 0 to 3
+ * @param[in] bitValue Value that contains all bits in to set mask,
+ * in range from 0 to 0xFF.
+ * @param[in] maskValue Mask value contains state value for each bit:
+ * - 0: not mask.
+ * - 1: mask.
+ * @return None
+ *
+ * Note:
+ * - All remaining bits that are not activated in bitValue (value '0')
+ * will not be effected by this function.
+ * - After executing this function, in mask register, value '0' on each bit
+ * enables an access to the corresponding physical pin via a read or write access,
+ * while value '1' on bit (masked) that corresponding pin will not be changed
+ * with write access and if read, will not be reflected in the updated pin.
+ **********************************************************************/
+void FIO_ByteSetMask(uint8_t portNum, uint8_t byteNum, uint8_t bitValue, uint8_t maskValue)
+{
+ GPIO_Byte_TypeDef *pFIO = FIO_ByteGetPointer(portNum);
+ if(pFIO != NULL) {
+ // Mask
+ if (maskValue) {
+ if (byteNum <= 3) {
+ pFIO->FIOMASK[byteNum] |= bitValue;
+ }
+ }
+ // Un-mask
+ else {
+ if (byteNum <= 3) {
+ pFIO->FIOMASK[byteNum] &= ~bitValue;
+ }
+ }
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Set bits for FIO port in byte accessible style
+ * @param[in] portNum Port number, in range from 0 to 4
+ * @param[in] byteNum Byte part number, should be in range from 0 to 3
+ * @param[in] bitValue Value that contains all bits in to set,
+ * in range from 0 to 0xFF.
+ * @return None
+ *
+ * Note:
+ * - For all bits that has been set as input direction, this function will
+ * not effect.
+ * - For all remaining bits that are not activated in bitValue (value '0')
+ * will not be effected by this function.
+ **********************************************************************/
+void FIO_ByteSetValue(uint8_t portNum, uint8_t byteNum, uint8_t bitValue)
+{
+ GPIO_Byte_TypeDef *pFIO = FIO_ByteGetPointer(portNum);
+ if (pFIO != NULL) {
+ if (byteNum <= 3){
+ pFIO->FIOSET[byteNum] = bitValue;
+ }
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Clear bits for FIO port in byte accessible style
+ * @param[in] portNum Port number, in range from 0 to 4
+ * @param[in] byteNum Byte part number, should be in range from 0 to 3
+ * @param[in] bitValue Value that contains all bits in to clear,
+ * in range from 0 to 0xFF.
+ * @return None
+ *
+ * Note:
+ * - For all bits that has been set as input direction, this function will
+ * not effect.
+ * - For all remaining bits that are not activated in bitValue (value '0')
+ * will not be effected by this function.
+ **********************************************************************/
+void FIO_ByteClearValue(uint8_t portNum, uint8_t byteNum, uint8_t bitValue)
+{
+ GPIO_Byte_TypeDef *pFIO = FIO_ByteGetPointer(portNum);
+ if (pFIO != NULL) {
+ if (byteNum <= 3){
+ pFIO->FIOCLR[byteNum] = bitValue;
+ }
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Read Current state on port pin that have input direction of GPIO
+ * in byte accessible style.
+ * @param[in] portNum Port number, in range from 0 to 4
+ * @param[in] byteNum Byte part number, should be in range from 0 to 3
+ * @return Current value of FIO port pin of specified byte part.
+ * Note: Return value contain state of each port pin (bit) on that FIO regardless
+ * its direction is input or output.
+ **********************************************************************/
+uint8_t FIO_ByteReadValue(uint8_t portNum, uint8_t byteNum)
+{
+ GPIO_Byte_TypeDef *pFIO = FIO_ByteGetPointer(portNum);
+ if (pFIO != NULL) {
+ if (byteNum <= 3){
+ return (pFIO->FIOPIN[byteNum]);
+ }
+ }
+ return (0);
+}
+
+/**
+ * @}
+ */
+
+#endif /* _GPIO */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/src/shared/cmsis/Drivers/source/lpc17xx_i2c.c b/src/shared/cmsis/Drivers/source/lpc17xx_i2c.c
@@ -0,0 +1,1344 @@
+/**********************************************************************
+* $Id$ lpc17xx_i2c.c 2011-03-31
+*//**
+* @file lpc17xx_i2c.c
+* @brief Contains all functions support for I2C firmware
+* library on LPC17xx
+* @version 2.1
+* @date 31. Mar. 2011
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2010, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @addtogroup I2C
+ * @{
+ */
+
+/* Includes ------------------------------------------------------------------- */
+#include "lpc17xx_i2c.h"
+#include "lpc17xx_clkpwr.h"
+#include "lpc17xx_pinsel.h"
+
+
+/* If this source file built with example, the LPC17xx FW library configuration
+ * file in each example directory ("lpc17xx_libcfg.h") must be included,
+ * otherwise the default FW library configuration file must be included instead
+ */
+#ifdef __BUILD_WITH_EXAMPLE__
+#include "lpc17xx_libcfg.h"
+#else
+#include "lpc17xx_libcfg_default.h"
+#endif /* __BUILD_WITH_EXAMPLE__ */
+
+
+#ifdef _I2C
+
+
+/* Private Types -------------------------------------------------------------- */
+/** @defgroup I2C_Private_Types I2C Private Types
+ * @{
+ */
+
+/**
+ * @brief I2C device configuration structure type
+ */
+typedef struct
+{
+ uint32_t txrx_setup; /* Transmission setup */
+ int32_t dir; /* Current direction phase, 0 - write, 1 - read */
+} I2C_CFG_T;
+
+/**
+ * @}
+ */
+
+/* Private Variables ---------------------------------------------------------- */
+/**
+ * @brief II2C driver data for I2C0, I2C1 and I2C2
+ */
+static I2C_CFG_T i2cdat[3];
+
+static uint32_t I2C_MasterComplete[3];
+static uint32_t I2C_SlaveComplete[3];
+
+static uint32_t I2C_MonitorBufferIndex;
+
+/* Private Functions ---------------------------------------------------------- */
+
+/* Get I2C number */
+static int32_t I2C_getNum(LPC_I2C_TypeDef *I2Cx);
+
+/* Generate a start condition on I2C bus (in master mode only) */
+static uint32_t I2C_Start (LPC_I2C_TypeDef *I2Cx);
+
+/* Generate a stop condition on I2C bus (in master mode only) */
+static void I2C_Stop (LPC_I2C_TypeDef *I2Cx);
+
+/* I2C send byte subroutine */
+static uint32_t I2C_SendByte (LPC_I2C_TypeDef *I2Cx, uint8_t databyte);
+
+/* I2C get byte subroutine */
+static uint32_t I2C_GetByte (LPC_I2C_TypeDef *I2Cx, uint8_t *retdat, Bool ack);
+
+/* I2C set clock (hz) */
+static void I2C_SetClock (LPC_I2C_TypeDef *I2Cx, uint32_t target_clock);
+
+/*--------------------------------------------------------------------------------*/
+/********************************************************************//**
+ * @brief Convert from I2C peripheral to number
+ * @param[in] I2Cx: I2C peripheral selected, should be:
+ * - LPC_I2C0
+ * - LPC_I2C1
+ * - LPC_I2C2
+ * @return I2C number, could be: 0..2
+ *********************************************************************/
+static int32_t I2C_getNum(LPC_I2C_TypeDef *I2Cx){
+ if (I2Cx == LPC_I2C0) {
+ return (0);
+ } else if (I2Cx == LPC_I2C1) {
+ return (1);
+ } else if (I2Cx == LPC_I2C2) {
+ return (2);
+ }
+ return (-1);
+}
+
+/********************************************************************//**
+ * @brief Generate a start condition on I2C bus (in master mode only)
+ * @param[in] I2Cx: I2C peripheral selected, should be:
+ * - LPC_I2C0
+ * - LPC_I2C1
+ * - LPC_I2C2
+ * @return value of I2C status register after generate a start condition
+ *********************************************************************/
+static uint32_t I2C_Start (LPC_I2C_TypeDef *I2Cx)
+{
+ // Reset STA, STO, SI
+ I2Cx->I2CONCLR = I2C_I2CONCLR_SIC|I2C_I2CONCLR_STOC|I2C_I2CONCLR_STAC;
+
+ // Enter to Master Transmitter mode
+ I2Cx->I2CONSET = I2C_I2CONSET_STA;
+
+ // Wait for complete
+ while (!(I2Cx->I2CONSET & I2C_I2CONSET_SI));
+ I2Cx->I2CONCLR = I2C_I2CONCLR_STAC;
+ return (I2Cx->I2STAT & I2C_STAT_CODE_BITMASK);
+}
+
+/********************************************************************//**
+ * @brief Generate a stop condition on I2C bus (in master mode only)
+ * @param[in] I2Cx: I2C peripheral selected, should be:
+ * - LPC_I2C0
+ * - LPC_I2C1
+ * - LPC_I2C2
+ * @return None
+ *********************************************************************/
+static void I2C_Stop (LPC_I2C_TypeDef *I2Cx)
+{
+
+ /* Make sure start bit is not active */
+ if (I2Cx->I2CONSET & I2C_I2CONSET_STA)
+ {
+ I2Cx->I2CONCLR = I2C_I2CONCLR_STAC;
+ }
+
+ I2Cx->I2CONSET = I2C_I2CONSET_STO|I2C_I2CONSET_AA;
+
+ I2Cx->I2CONCLR = I2C_I2CONCLR_SIC;
+}
+
+/********************************************************************//**
+ * @brief Send a byte
+ * @param[in] I2Cx: I2C peripheral selected, should be:
+ * - LPC_I2C0
+ * - LPC_I2C1
+ * - LPC_I2C2
+ * @param[in] databyte: number of byte
+ * @return value of I2C status register after sending
+ *********************************************************************/
+static uint32_t I2C_SendByte (LPC_I2C_TypeDef *I2Cx, uint8_t databyte)
+{
+ uint32_t CodeStatus = I2Cx->I2STAT & I2C_STAT_CODE_BITMASK;
+
+ if((CodeStatus != I2C_I2STAT_M_TX_START) &&
+ (CodeStatus != I2C_I2STAT_M_TX_RESTART) &&
+ (CodeStatus != I2C_I2STAT_M_TX_SLAW_ACK) &&
+ (CodeStatus != I2C_I2STAT_M_TX_DAT_ACK) )
+ {
+ return CodeStatus;
+ }
+
+ /* Make sure start bit is not active */
+ if (I2Cx->I2CONSET & I2C_I2CONSET_STA)
+ {
+ I2Cx->I2CONCLR = I2C_I2CONCLR_STAC;
+ }
+ I2Cx->I2DAT = databyte & I2C_I2DAT_BITMASK;
+
+ I2Cx->I2CONSET = I2C_I2CONSET_AA;
+
+ I2Cx->I2CONCLR = I2C_I2CONCLR_SIC;
+
+ return (I2Cx->I2STAT & I2C_STAT_CODE_BITMASK);
+}
+
+/********************************************************************//**
+ * @brief Get a byte
+ * @param[in] I2Cx: I2C peripheral selected, should be:
+ * - LPC_I2C0
+ * - LPC_I2C1
+ * - LPC_I2C2
+ * @param[out] retdat pointer to return data
+ * @param[in] ack assert acknowledge or not, should be: TRUE/FALSE
+ * @return value of I2C status register after sending
+ *********************************************************************/
+static uint32_t I2C_GetByte (LPC_I2C_TypeDef *I2Cx, uint8_t *retdat, Bool ack)
+{
+ *retdat = (uint8_t) (I2Cx->I2DAT & I2C_I2DAT_BITMASK);
+
+ if (ack == TRUE)
+ {
+ I2Cx->I2CONSET = I2C_I2CONSET_AA;
+ }
+ else
+ {
+ I2Cx->I2CONCLR = I2C_I2CONCLR_AAC;
+ }
+
+ I2Cx->I2CONCLR = I2C_I2CONCLR_SIC;
+
+ return (I2Cx->I2STAT & I2C_STAT_CODE_BITMASK);
+}
+
+/*********************************************************************//**
+ * @brief Setup clock rate for I2C peripheral
+ * @param[in] I2Cx I2C peripheral selected, should be:
+ * - LPC_I2C0
+ * - LPC_I2C1
+ * - LPC_I2C2
+ * @param[in] target_clock : clock of SSP (Hz)
+ * @return None
+ ***********************************************************************/
+static void I2C_SetClock (LPC_I2C_TypeDef *I2Cx, uint32_t target_clock)
+{
+ uint32_t temp;
+
+ CHECK_PARAM(PARAM_I2Cx(I2Cx));
+
+ // Get PCLK of I2C controller
+ if (I2Cx == LPC_I2C0)
+ {
+ temp = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_I2C0) / target_clock;
+ }
+ else if (I2Cx == LPC_I2C1)
+ {
+ temp = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_I2C1) / target_clock;
+ }
+ else if (I2Cx == LPC_I2C2)
+ {
+ temp = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_I2C2) / target_clock;
+ }
+
+ /* Set the I2C clock value to register */
+ I2Cx->I2SCLH = (uint32_t)(temp / 2);
+ I2Cx->I2SCLL = (uint32_t)(temp - I2Cx->I2SCLH);
+}
+/* End of Private Functions --------------------------------------------------- */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @addtogroup I2C_Public_Functions
+ * @{
+ */
+
+/********************************************************************//**
+ * @brief Initializes the I2Cx peripheral with specified parameter.
+ * @param[in] I2Cx I2C peripheral selected, should be
+ * - LPC_I2C0
+ * - LPC_I2C1
+ * - LPC_I2C2
+ * @param[in] clockrate Target clock rate value to initialized I2C
+ * peripheral (Hz)
+ * @return None
+ *********************************************************************/
+void I2C_Init(LPC_I2C_TypeDef *I2Cx, uint32_t clockrate)
+{
+ CHECK_PARAM(PARAM_I2Cx(I2Cx));
+
+ if (I2Cx==LPC_I2C0)
+ {
+ /* Set up clock and power for I2C0 module */
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCI2C0, ENABLE);
+ /* As default, peripheral clock for I2C0 module
+ * is set to FCCLK / 2 */
+ CLKPWR_SetPCLKDiv(CLKPWR_PCLKSEL_I2C0, CLKPWR_PCLKSEL_CCLK_DIV_2);
+ }
+ else if (I2Cx==LPC_I2C1)
+ {
+ /* Set up clock and power for I2C1 module */
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCI2C1, ENABLE);
+ /* As default, peripheral clock for I2C1 module
+ * is set to FCCLK / 2 */
+ CLKPWR_SetPCLKDiv(CLKPWR_PCLKSEL_I2C1, CLKPWR_PCLKSEL_CCLK_DIV_2);
+ }
+ else if (I2Cx==LPC_I2C2)
+ {
+ /* Set up clock and power for I2C2 module */
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCI2C2, ENABLE);
+ /* As default, peripheral clock for I2C2 module
+ * is set to FCCLK / 2 */
+ CLKPWR_SetPCLKDiv(CLKPWR_PCLKSEL_I2C2, CLKPWR_PCLKSEL_CCLK_DIV_2);
+ }
+ else {
+ // Up-Support this device
+ return;
+ }
+
+ /* Set clock rate */
+ I2C_SetClock(I2Cx, clockrate);
+ /* Set I2C operation to default */
+ I2Cx->I2CONCLR = (I2C_I2CONCLR_AAC | I2C_I2CONCLR_STAC | I2C_I2CONCLR_I2ENC);
+}
+
+/*********************************************************************//**
+ * @brief De-initializes the I2C peripheral registers to their
+ * default reset values.
+ * @param[in] I2Cx I2C peripheral selected, should be
+ * - LPC_I2C0
+ * - LPC_I2C1
+ * - LPC_I2C2
+ * @return None
+ **********************************************************************/
+void I2C_DeInit(LPC_I2C_TypeDef* I2Cx)
+{
+ CHECK_PARAM(PARAM_I2Cx(I2Cx));
+
+ /* Disable I2C control */
+ I2Cx->I2CONCLR = I2C_I2CONCLR_I2ENC;
+
+ if (I2Cx==LPC_I2C0)
+ {
+ /* Disable power for I2C0 module */
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCI2C0, DISABLE);
+ }
+ else if (I2Cx==LPC_I2C1)
+ {
+ /* Disable power for I2C1 module */
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCI2C1, DISABLE);
+ }
+ else if (I2Cx==LPC_I2C2)
+ {
+ /* Disable power for I2C2 module */
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCI2C2, DISABLE);
+ }
+}
+
+/*********************************************************************//**
+ * @brief Enable or disable I2C peripheral's operation
+ * @param[in] I2Cx I2C peripheral selected, should be
+ * - LPC_I2C0
+ * - LPC_I2C1
+ * - LPC_I2C2
+ * @param[in] NewState New State of I2Cx peripheral's operation
+ * @return none
+ **********************************************************************/
+void I2C_Cmd(LPC_I2C_TypeDef* I2Cx, en_I2C_Mode Mode, FunctionalState NewState)
+{
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
+ CHECK_PARAM(PARAM_I2Cx(I2Cx));
+
+ if (NewState == ENABLE)
+ {
+ if(Mode != I2C_SLAVE_MODE)
+ I2Cx->I2CONSET = I2C_I2CONSET_I2EN;
+ else
+ I2Cx->I2CONSET = I2C_I2CONSET_I2EN | I2C_I2CONSET_AA;
+ }
+ else
+ {
+ I2Cx->I2CONCLR = I2C_I2CONCLR_I2ENC;
+ }
+}
+
+/*********************************************************************//**
+ * @brief Enable/Disable interrupt for I2C peripheral
+ * @param[in] I2Cx I2C peripheral selected, should be:
+ * - LPC_I2C0
+ * - LPC_I2C1
+ * - LPC_I2C2
+ * @param[in] NewState New State of I2C peripheral interrupt in NVIC core
+ * should be:
+ * - ENABLE: enable interrupt for this I2C peripheral
+ * - DISABLE: disable interrupt for this I2C peripheral
+ * @return None
+ **********************************************************************/
+void I2C_IntCmd (LPC_I2C_TypeDef *I2Cx, Bool NewState)
+{
+ if (NewState)
+ {
+ if(I2Cx == LPC_I2C0)
+ {
+ NVIC_EnableIRQ(I2C0_IRQn);
+ }
+ else if (I2Cx == LPC_I2C1)
+ {
+ NVIC_EnableIRQ(I2C1_IRQn);
+ }
+ else if (I2Cx == LPC_I2C2)
+ {
+ NVIC_EnableIRQ(I2C2_IRQn);
+ }
+ }
+ else
+ {
+ if(I2Cx == LPC_I2C0)
+ {
+ NVIC_DisableIRQ(I2C0_IRQn);
+ }
+ else if (I2Cx == LPC_I2C1)
+ {
+ NVIC_DisableIRQ(I2C1_IRQn);
+ }
+ else if (I2Cx == LPC_I2C2)
+ {
+ NVIC_DisableIRQ(I2C2_IRQn);
+ }
+ }
+ return;
+}
+
+
+/*********************************************************************//**
+ * @brief Handle I2C Master states.
+ * @param[in] I2Cx I2C peripheral selected, should be:
+ * - LPC_I2C
+ * - LPC_I2C1
+ * - LPC_I2C2
+ * @param[in] CodeStatus I2C state
+ * @param[in] TransferCfg Pointer to a I2C_S_SETUP_Type structure that
+ * contains specified information about the
+ * configuration for master transfer.
+ * @return It can be
+ * - I2C_OK
+ * -I2C_BYTE_RECV
+ * -I2C_BYTE_SENT
+ * -I2C_SEND_END
+ * -I2C_RECV_END
+ * - I2C_ERR
+ * - I2C_NAK_RECV
+ **********************************************************************/
+int32_t I2C_MasterHanleStates(LPC_I2C_TypeDef *I2Cx, uint32_t CodeStatus, I2C_M_SETUP_Type *TransferCfg)
+{
+ uint8_t *txdat;
+ uint8_t *rxdat;
+ uint8_t tmp;
+ int32_t Ret = I2C_OK;
+
+ //get buffer to send/receive
+ txdat = (uint8_t *) &TransferCfg->tx_data[TransferCfg->tx_count];
+ rxdat = (uint8_t *) &TransferCfg->rx_data[TransferCfg->rx_count];
+
+ switch(CodeStatus)
+ {
+ case I2C_I2STAT_M_TX_START:
+ case I2C_I2STAT_M_TX_RESTART:
+ //case I2C_I2STAT_M_RX_START:
+ //case I2C_I2STAT_M_RX_RESTART
+ // Send data first
+ if(TransferCfg->tx_count < TransferCfg->tx_length)
+ {
+ /* Send slave address + WR direction bit = 0 ----------------------------------- */
+ I2C_SendByte(I2Cx, (TransferCfg->sl_addr7bit << 1));
+ Ret = I2C_BYTE_SENT;
+ }
+ else if (TransferCfg->rx_count < TransferCfg->rx_length)
+ {
+ /* Send slave address + RD direction bit = 1 ----------------------------------- */
+ I2C_SendByte(I2Cx, ((TransferCfg->sl_addr7bit << 1) | 0x01));
+ Ret = I2C_BYTE_SENT;
+ }
+ break;
+ case I2C_I2STAT_M_TX_SLAW_ACK:
+ case I2C_I2STAT_M_TX_DAT_ACK:
+
+ if(TransferCfg->tx_count < TransferCfg->tx_length)
+ {
+ I2C_SendByte(I2Cx, *txdat);
+
+ txdat++;
+
+ TransferCfg->tx_count++;
+
+ Ret = I2C_BYTE_SENT;
+ }
+ else
+ {
+ I2C_Stop(I2Cx);
+
+ Ret = I2C_SEND_END;
+
+ }
+ break;
+ case I2C_I2STAT_M_TX_DAT_NACK:
+ I2C_Stop(I2Cx);
+ Ret = I2C_SEND_END;
+ break;
+ case I2C_I2STAT_M_RX_ARB_LOST:
+ //case I2C_I2STAT_M_TX_ARB_LOST:
+ I2Cx->I2CONSET = I2C_I2CONSET_STA|I2C_I2CONSET_AA;
+ I2Cx->I2CONCLR = I2C_I2CONCLR_SIC;
+ break;
+ case I2C_I2STAT_M_RX_SLAR_ACK:
+ I2Cx->I2CONSET = I2C_I2CONSET_AA;
+ I2Cx->I2CONCLR = I2C_I2CONCLR_SIC;
+
+ Ret = I2C_BYTE_RECV;
+ break;
+ case I2C_I2STAT_M_RX_DAT_ACK:
+ if (TransferCfg->rx_count <TransferCfg->rx_length)
+ {
+ if (TransferCfg->rx_count < (TransferCfg->rx_length - 2))
+ {
+ I2C_GetByte(I2Cx, &tmp, TRUE);
+
+ Ret = I2C_BYTE_RECV;
+ }
+ else // the next byte is the last byte, send NACK instead.
+ {
+ I2C_GetByte(I2Cx, &tmp, FALSE);
+ Ret = I2C_BYTE_RECV;
+ }
+ *rxdat++ = tmp;
+
+ TransferCfg->rx_count++;
+ }
+ else
+ {
+ Ret = I2C_RECV_END;
+ }
+
+ break;
+ case I2C_I2STAT_M_RX_DAT_NACK:
+ I2C_GetByte(I2Cx, &tmp, FALSE);
+ *rxdat++ = tmp;
+ TransferCfg->rx_count++;
+ I2C_Stop(I2Cx);
+ Ret = I2C_RECV_END;
+ break;
+ case I2C_I2STAT_M_RX_SLAR_NACK:
+ case I2C_I2STAT_M_TX_SLAW_NACK:
+ case I2C_I2STAT_BUS_ERROR:
+ // Send STOP condition
+ I2C_Stop(I2Cx);
+ Ret = I2C_ERR;
+ break;
+ /* No status information */
+ case I2C_I2STAT_NO_INF:
+ default:
+ I2Cx->I2CONCLR = I2C_I2CONCLR_SIC;
+ break;
+ }
+
+ return Ret;
+}
+
+/*********************************************************************//**
+ * @brief Handle I2C Slave states.
+ * @param[in] I2Cx I2C peripheral selected, should be:
+ * - LPC_I2C
+ * - LPC_I2C1
+ * - LPC_I2C2
+ * @param[in] CodeStatus I2C state
+ * @param[in] TransferCfg Pointer to a I2C_S_SETUP_Type structure that
+ * contains specified information about the
+ * configuration for master transfer.
+ * @return It can be
+ * - I2C_OK
+ * -I2C_BYTE_RECV
+ * -I2C_BYTE_SENT
+ * -I2C_SEND_END
+ * -I2C_RECV_END
+ * - I2C_ERR
+ * - I2C_NAK_RECV
+ **********************************************************************/
+int32_t I2C_SlaveHanleStates(LPC_I2C_TypeDef *I2Cx, uint32_t CodeStatus, I2C_S_SETUP_Type *TransferCfg)
+{
+
+ int32_t Ret = I2C_OK;
+ uint8_t *txdat;
+ uint8_t *rxdat;
+
+ //get buffer to send/receive
+ txdat = (uint8_t *) &TransferCfg->tx_data[TransferCfg->tx_count];
+ rxdat = (uint8_t *) &TransferCfg->rx_data[TransferCfg->rx_count];
+
+ switch (CodeStatus)
+ {
+ /* Reading phase -------------------------------------------------------- */
+ /* Own SLA+R has been received, ACK has been returned */
+ case I2C_I2STAT_S_RX_SLAW_ACK:
+
+ /* General call address has been received, ACK has been returned */
+ case I2C_I2STAT_S_RX_GENCALL_ACK:
+ I2Cx->I2CONSET = I2C_I2CONSET_AA;
+ I2Cx->I2CONCLR = I2C_I2CONCLR_SIC;
+ break;
+ /* Arbitration has been lost in Slave Address + R/W bit as bus Master. General Call has
+ been received and ACK has been returned.*/
+ case I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL:
+ I2Cx->I2CONSET = I2C_I2CONSET_AA|I2C_I2CONSET_STA;
+ I2Cx->I2CONCLR = I2C_I2CONCLR_SIC;
+ break;
+ /* Previously addressed with own SLA;
+ * DATA byte has been received;
+ * ACK has been returned */
+ case I2C_I2STAT_S_RX_ARB_LOST_M_SLA:
+ case I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK:
+
+ /*
+ * All data bytes that over-flow the specified receive
+ * data length, just ignore them.
+ */
+ if ((TransferCfg->rx_count < TransferCfg->rx_length) && (TransferCfg->rx_data != NULL))
+ {
+ *rxdat++ = (uint8_t)I2Cx->I2DAT;
+
+ TransferCfg->rx_count++;
+
+ Ret = I2C_BYTE_RECV;
+ }
+ if(TransferCfg->rx_count == (TransferCfg->rx_length) ) {
+ I2Cx->I2CONCLR = I2C_I2CONCLR_AAC|I2C_I2CONCLR_SIC;
+ Ret = I2C_BYTE_RECV;
+ }
+ else {
+ I2Cx->I2CONSET = I2C_I2CONSET_AA;
+ I2Cx->I2CONCLR = I2C_I2CONCLR_SIC;
+ }
+
+ break;
+ /* DATA has been received, Only the first data byte will be received with ACK. Additional
+ data will be received with NOT ACK. */
+ case I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK:
+ if ((TransferCfg->rx_count < TransferCfg->rx_length) && (TransferCfg->rx_data != NULL))
+ {
+ *rxdat++ = (uint8_t)I2Cx->I2DAT;
+
+ TransferCfg->rx_count++;
+
+ Ret = I2C_BYTE_RECV;
+ }
+ I2Cx->I2CONCLR = I2C_I2CONCLR_AAC|I2C_I2CONCLR_SIC;
+ break;
+
+ /* Writing phase -------------------------------------------------------- */
+ /* Own SLA+R has been received, ACK has been returned */
+ case I2C_I2STAT_S_TX_SLAR_ACK:
+
+ /* Data has been transmitted, ACK has been received */
+ case I2C_I2STAT_S_TX_DAT_ACK:
+ /*
+ * All data bytes that over-flow the specified receive
+ * data length, just ignore them.
+ */
+ if ((TransferCfg->tx_count < TransferCfg->tx_length) && (TransferCfg->tx_data != NULL))
+ {
+ I2Cx->I2DAT = *txdat++;
+
+ TransferCfg->tx_count++;
+
+ Ret = I2C_BYTE_SENT;
+ }
+
+ I2Cx->I2CONSET = I2C_I2CONSET_AA;
+ I2Cx->I2CONCLR = I2C_I2CONCLR_SIC;
+ break;
+ /* Arbitration lost in Slave Address and R/W bit as bus Master. Own Slave Address + Read
+ has been received, ACK has been returned. */
+ case I2C_I2STAT_S_TX_ARB_LOST_M_SLA:
+ if ((TransferCfg->tx_count < TransferCfg->tx_length) && (TransferCfg->tx_data != NULL))
+ {
+ I2Cx->I2DAT = *txdat++;
+
+ TransferCfg->tx_count++;
+
+ Ret = I2C_BYTE_SENT;
+ }
+ I2Cx->I2CONSET = I2C_I2CONSET_AA|I2C_I2CONSET_STA;
+ I2Cx->I2CONCLR = I2C_I2CONCLR_SIC;
+ break;
+
+ case I2C_I2STAT_S_TX_LAST_DAT_ACK:
+ /* Data has been transmitted, NACK has been received,
+ * that means there's no more data to send, exit now */
+ /*
+ * Note: Don't wait for stop event since in slave transmit mode,
+ * since there no proof lets us know when a stop signal has been received
+ * on slave side.
+ */
+ case I2C_I2STAT_S_TX_DAT_NACK:
+ I2Cx->I2CONSET = I2C_I2CONSET_AA;
+ I2Cx->I2CONCLR = I2C_I2CONCLR_SIC;
+ Ret = I2C_SEND_END;
+ break;
+
+ /* Previously addressed with own SLA;
+ * DATA byte has been received;
+ * NOT ACK has been returned */
+ case I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK:
+
+ /* DATA has been received, NOT ACK has been returned */
+ case I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK:
+ I2Cx->I2CONSET = I2C_I2CONSET_AA;
+ I2Cx->I2CONCLR = I2C_I2CONCLR_SIC;
+ Ret = I2C_RECV_END;
+ break;
+
+ /*
+ * Note that: Return code only let us know a stop condition mixed
+ * with a repeat start condition in the same code value.
+ * So we should provide a time-out. In case this is really a stop
+ * condition, this will return back after time out condition. Otherwise,
+ * next session that is slave receive data will be completed.
+ */
+
+ /* A Stop or a repeat start condition */
+ case I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX:
+ I2Cx->I2CONSET = I2C_I2CONSET_AA;
+ I2Cx->I2CONCLR = I2C_I2CONCLR_SIC;
+ Ret = I2C_STA_STO_RECV;
+ break;
+
+ /* No status information */
+ case I2C_I2STAT_NO_INF:
+ /* Other status must be captured */
+ default:
+ I2Cx->I2CONSET = I2C_I2CONSET_AA;
+ I2Cx->I2CONCLR = I2C_I2CONCLR_SIC;
+ break;
+
+ }
+
+ return Ret;
+}
+/*********************************************************************//**
+ * @brief General Master Interrupt handler for I2C peripheral
+ * @param[in] I2Cx I2C peripheral selected, should be:
+ * - LPC_I2C
+ * - LPC_I2C1
+ * - LPC_I2C2
+ * @return None
+ **********************************************************************/
+void I2C_MasterHandler(LPC_I2C_TypeDef *I2Cx)
+{
+ uint32_t i2cId = I2C_getNum(I2Cx);
+ uint8_t returnCode;
+ I2C_M_SETUP_Type *txrx_setup;
+ int32_t Ret = I2C_OK;
+
+ txrx_setup = (I2C_M_SETUP_Type *) i2cdat[i2cId].txrx_setup;
+
+ returnCode = (I2Cx->I2STAT & I2C_STAT_CODE_BITMASK);
+
+ // Save current status
+ txrx_setup->status = returnCode;
+
+ Ret = I2C_MasterHanleStates(I2Cx, returnCode, txrx_setup);
+
+ if(I2C_CheckError(Ret))
+ {
+ if(txrx_setup->retransmissions_count < txrx_setup->retransmissions_max)
+ {
+ // Retry
+ txrx_setup->retransmissions_count ++;
+ txrx_setup->tx_count = 0;
+ txrx_setup->rx_count = 0;
+ // Reset STA, STO, SI
+ I2Cx->I2CONCLR = I2C_I2CONCLR_SIC|I2C_I2CONCLR_STOC|I2C_I2CONCLR_STAC;
+ I2Cx->I2CONSET = I2C_I2CONSET_STA;
+ return;
+ }
+ else
+ {
+ goto s_int_end;
+ }
+ }
+ else if (Ret & I2C_SEND_END)
+ {
+ // If no need to wait for data from Slave
+ if(txrx_setup->rx_count >= (txrx_setup->rx_length))
+ {
+ goto s_int_end;
+ }
+ else // Start to wait for data from Slave
+ {
+ // Reset STA, STO, SI
+ I2Cx->I2CONCLR = I2C_I2CONCLR_SIC|I2C_I2CONCLR_STOC|I2C_I2CONCLR_STAC;
+ I2Cx->I2CONSET = I2C_I2CONSET_STA;
+ return;
+ }
+ }
+ else if (Ret & I2C_RECV_END)
+ {
+ goto s_int_end;
+ }
+ else
+ {
+ return;
+ }
+
+s_int_end:
+ // Disable interrupt
+ I2C_IntCmd(I2Cx, FALSE);
+
+ I2Cx->I2CONCLR = I2C_I2CONCLR_AAC | I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC;
+
+ I2C_MasterComplete[i2cId] = TRUE;
+
+}
+
+
+/*********************************************************************//**
+ * @brief General Slave Interrupt handler for I2C peripheral
+ * @param[in] I2Cx I2C peripheral selected, should be:
+ * - LPC_I2C0
+ * - LPC_I2C1
+ * - LPC_I2C2
+ * @return None
+ **********************************************************************/
+void I2C_SlaveHandler (LPC_I2C_TypeDef *I2Cx)
+{
+ uint32_t i2cId = I2C_getNum(I2Cx);
+ uint8_t returnCode;
+ I2C_S_SETUP_Type *txrx_setup;
+ uint32_t timeout;
+ int32_t Ret = I2C_OK;
+
+ txrx_setup = (I2C_S_SETUP_Type *) i2cdat[i2cId].txrx_setup;
+
+handle_state:
+
+ returnCode = (I2Cx->I2STAT & I2C_STAT_CODE_BITMASK);
+ // Save current status
+ txrx_setup->status = returnCode;
+
+
+ Ret = I2C_SlaveHanleStates(I2Cx, returnCode, txrx_setup);
+
+ if(I2C_CheckError(Ret))
+ {
+ goto s_int_end;
+ }
+ else if (Ret & I2C_STA_STO_RECV)
+ {
+ // Temporally lock the interrupt for timeout condition
+ I2C_IntCmd(I2Cx, FALSE);
+ // enable time out
+ timeout = I2C_SLAVE_TIME_OUT;
+ while(1)
+ {
+ if (I2Cx->I2CONSET & I2C_I2CONSET_SI)
+ {
+ // re-Enable interrupt
+ I2C_IntCmd(I2Cx, TRUE);
+ goto handle_state;
+ }
+ else
+ {
+ timeout--;
+ if (timeout == 0)
+ {
+ // timeout occur, it's really a stop condition
+ txrx_setup->status |= I2C_SETUP_STATUS_DONE;
+ goto s_int_end;
+ }
+ }
+ }
+ }
+ else if(Ret &I2C_SEND_END)
+ {
+ goto s_int_end;
+ }
+ else
+ {
+ return;
+ }
+
+s_int_end:
+ // Disable interrupt
+ I2C_IntCmd(I2Cx, FALSE);
+ I2Cx->I2CONCLR = I2C_I2CONCLR_AAC | I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC;
+
+ I2C_SlaveComplete[i2cId] = TRUE;
+}
+
+/*********************************************************************//**
+ * @brief Transmit and Receive data in master mode
+ * @param[in] I2Cx I2C peripheral selected, should be:
+ * - LPC_I2C0
+ * - LPC_I2C1
+ * - LPC_I2C2
+ * @param[in] TransferCfg Pointer to a I2C_M_SETUP_Type structure that
+ * contains specified information about the
+ * configuration for master transfer.
+ * @param[in] Opt a I2C_TRANSFER_OPT_Type type that selected for
+ * interrupt or polling mode.
+ * @return SUCCESS or ERROR
+ *
+ * Note:
+ * - In case of using I2C to transmit data only, either transmit length set to 0
+ * or transmit data pointer set to NULL.
+ * - In case of using I2C to receive data only, either receive length set to 0
+ * or receive data pointer set to NULL.
+ * - In case of using I2C to transmit followed by receive data, transmit length,
+ * transmit data pointer, receive length and receive data pointer should be set
+ * corresponding.
+ **********************************************************************/
+Status I2C_MasterTransferData(LPC_I2C_TypeDef *I2Cx, I2C_M_SETUP_Type *TransferCfg, \
+ I2C_TRANSFER_OPT_Type Opt)
+{
+ uint32_t i2cId = I2C_getNum(I2Cx); uint32_t CodeStatus;
+ int32_t Ret = I2C_OK;
+
+ // Reset I2C setup value to default state
+ TransferCfg->tx_count = 0;
+ TransferCfg->rx_count = 0;
+ TransferCfg->status = 0;
+
+ if (Opt == I2C_TRANSFER_POLLING)
+ {
+ /* First Start condition -------------------------------------------------------------- */
+ TransferCfg->retransmissions_count = 0;
+retry:
+ // Reset I2C setup value to default state
+ TransferCfg->tx_count = 0;
+ TransferCfg->rx_count = 0;
+
+ // Start command
+ CodeStatus = I2C_Start(I2Cx);
+
+ while(1) // send data first and then receive data from Slave.
+ {
+ Ret = I2C_MasterHanleStates(I2Cx, CodeStatus, TransferCfg);
+ if(I2C_CheckError(Ret))
+ {
+ TransferCfg->retransmissions_count++;
+ if (TransferCfg->retransmissions_count > TransferCfg->retransmissions_max){
+ // save status
+ TransferCfg->status = CodeStatus | I2C_SETUP_STATUS_NOACKF;
+ goto error;
+ } else {
+ goto retry;
+ }
+ }
+ else if( (Ret & I2C_BYTE_SENT) ||
+ (Ret & I2C_BYTE_RECV))
+ {
+ // Wait for sending ends
+ while (!(I2Cx->I2CONSET & I2C_I2CONSET_SI));
+ }
+ else if (Ret & I2C_SEND_END) // already send all data
+ {
+ // If no need to wait for data from Slave
+ if(TransferCfg->rx_count >= (TransferCfg->rx_length))
+ {
+ break;
+ }
+ else
+ {
+ I2C_Start(I2Cx);
+ }
+ }
+ else if (Ret & I2C_RECV_END) // already receive all data
+ {
+ break;
+ }
+ CodeStatus = I2Cx->I2STAT & I2C_STAT_CODE_BITMASK;
+ }
+ return SUCCESS;
+error:
+ return ERROR;
+ }
+
+ else if (Opt == I2C_TRANSFER_INTERRUPT)
+ {
+ // Setup tx_rx data, callback and interrupt handler
+ i2cdat[i2cId].txrx_setup = (uint32_t) TransferCfg;
+
+ // Set direction phase, write first
+ i2cdat[i2cId].dir = 0;
+
+ /* First Start condition -------------------------------------------------------------- */
+ // Reset STA, STO, SI
+ I2Cx->I2CONCLR = I2C_I2CONCLR_SIC|I2C_I2CONCLR_STOC|I2C_I2CONCLR_STAC;
+ I2Cx->I2CONSET = I2C_I2CONSET_STA;
+
+ I2C_IntCmd(I2Cx, TRUE);
+
+ return (SUCCESS);
+ }
+
+ return ERROR;
+}
+
+/*********************************************************************//**
+ * @brief Receive and Transmit data in slave mode
+ * @param[in] I2Cx I2C peripheral selected, should be
+ * - LPC_I2C0
+ * - LPC_I2C1
+ * - LPC_I2C2
+ * @param[in] TransferCfg Pointer to a I2C_S_SETUP_Type structure that
+ * contains specified information about the
+ * configuration for master transfer.
+ * @param[in] Opt I2C_TRANSFER_OPT_Type type that selected for
+ * interrupt or polling mode.
+ * @return SUCCESS or ERROR
+ *
+ * Note:
+ * The mode of slave's operation depends on the command sent from master on
+ * the I2C bus. If the master send a SLA+W command, this sub-routine will
+ * use receive data length and receive data pointer. If the master send a SLA+R
+ * command, this sub-routine will use transmit data length and transmit data
+ * pointer.
+ * If the master issue an repeat start command or a stop command, the slave will
+ * enable an time out condition, during time out condition, if there's no activity
+ * on I2C bus, the slave will exit, otherwise (i.e. the master send a SLA+R/W),
+ * the slave then switch to relevant operation mode. The time out should be used
+ * because the return status code can not show difference from stop and repeat
+ * start command in slave operation.
+ * In case of the expected data length from master is greater than data length
+ * that slave can support:
+ * - In case of reading operation (from master): slave will return I2C_I2DAT_IDLE_CHAR
+ * value.
+ * - In case of writing operation (from master): slave will ignore remain data from master.
+ **********************************************************************/
+Status I2C_SlaveTransferData(LPC_I2C_TypeDef *I2Cx, I2C_S_SETUP_Type *TransferCfg, \
+ I2C_TRANSFER_OPT_Type Opt)
+{
+ int32_t Ret = I2C_OK;
+
+ uint32_t CodeStatus;
+ uint32_t timeout;
+ int32_t time_en;
+ uint32_t i2cId = I2C_getNum(I2Cx);
+ // Reset I2C setup value to default state
+ TransferCfg->tx_count = 0;
+ TransferCfg->rx_count = 0;
+ TransferCfg->status = 0;
+
+ // Polling option
+ if (Opt == I2C_TRANSFER_POLLING)
+ {
+ /* Set AA bit to ACK command on I2C bus */
+ I2Cx->I2CONSET = I2C_I2CONSET_AA;
+
+ /* Clear SI bit to be ready ... */
+ I2Cx->I2CONCLR = (I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC|I2C_I2CONCLR_STOC);
+
+ time_en = 0;
+ timeout = 0;
+
+ while (1)
+ {
+ /* Check SI flag ready */
+ if (I2Cx->I2CONSET & I2C_I2CONSET_SI)
+ {
+ time_en = 0;
+
+ CodeStatus = (I2Cx->I2STAT & I2C_STAT_CODE_BITMASK);
+
+ Ret = I2C_SlaveHanleStates(I2Cx, CodeStatus, TransferCfg);
+ if(I2C_CheckError(Ret))
+ {
+ goto s_error;
+ }
+ else if(Ret & I2C_STA_STO_RECV)
+ {
+ time_en = 1;
+ timeout = 0;
+ }
+ else if (Ret & I2C_SEND_END)
+ {
+ goto s_end_stage;
+ }
+ }
+ else if (time_en)
+ {
+ if (timeout++ > I2C_SLAVE_TIME_OUT)
+ {
+ // it's really a stop condition, goto end stage
+ goto s_end_stage;
+ }
+ }
+ }
+
+s_end_stage:
+ /* Clear AA bit to disable ACK on I2C bus */
+ I2Cx->I2CONCLR = I2C_I2CONCLR_AAC;
+
+ // Check if there's no error during operation
+ // Update status
+ TransferCfg->status = CodeStatus | I2C_SETUP_STATUS_DONE;
+ return SUCCESS;
+
+s_error:
+ /* Clear AA bit to disable ACK on I2C bus */
+ I2Cx->I2CONCLR = I2C_I2CONCLR_AAC;
+
+ // Update status
+ TransferCfg->status = CodeStatus;
+ return ERROR;
+ }
+
+ else if (Opt == I2C_TRANSFER_INTERRUPT)
+ {
+ // Setup tx_rx data, callback and interrupt handler
+ i2cdat[i2cId].txrx_setup = (uint32_t) TransferCfg;
+
+ // Set direction phase, read first
+ i2cdat[i2cId].dir = 1;
+
+ // Enable AA
+ I2Cx->I2CONSET = I2C_I2CONSET_AA;
+ I2Cx->I2CONCLR = I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC;
+ I2C_IntCmd(I2Cx, TRUE);
+
+ return (SUCCESS);
+ }
+
+ return ERROR;
+}
+
+/*********************************************************************//**
+ * @brief Set Own slave address in I2C peripheral corresponding to
+ * parameter specified in OwnSlaveAddrConfigStruct.
+ * @param[in] I2Cx I2C peripheral selected, should be
+ * - LPC_I2C0
+ * - LPC_I2C1
+ * - LPC_I2C2
+ * @param[in] OwnSlaveAddrConfigStruct Pointer to a I2C_OWNSLAVEADDR_CFG_Type
+ * structure that contains the configuration information for the
+* specified I2C slave address.
+ * @return None
+ **********************************************************************/
+void I2C_SetOwnSlaveAddr(LPC_I2C_TypeDef *I2Cx, I2C_OWNSLAVEADDR_CFG_Type *OwnSlaveAddrConfigStruct)
+{
+ uint32_t tmp;
+ CHECK_PARAM(PARAM_I2Cx(I2Cx));
+ CHECK_PARAM(PARAM_I2C_SLAVEADDR_CH(OwnSlaveAddrConfigStruct->SlaveAddrChannel));
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(OwnSlaveAddrConfigStruct->GeneralCallState));
+
+ tmp = (((uint32_t)(OwnSlaveAddrConfigStruct->SlaveAddr_7bit << 1)) \
+ | ((OwnSlaveAddrConfigStruct->GeneralCallState == ENABLE) ? 0x01 : 0x00))& I2C_I2ADR_BITMASK;
+ switch (OwnSlaveAddrConfigStruct->SlaveAddrChannel)
+ {
+ case 0:
+ I2Cx->I2ADR0 = tmp;
+ I2Cx->I2MASK0 = I2C_I2MASK_MASK((uint32_t) \
+ (OwnSlaveAddrConfigStruct->SlaveAddrMaskValue));
+ break;
+ case 1:
+ I2Cx->I2ADR1 = tmp;
+ I2Cx->I2MASK1 = I2C_I2MASK_MASK((uint32_t) \
+ (OwnSlaveAddrConfigStruct->SlaveAddrMaskValue));
+ break;
+ case 2:
+ I2Cx->I2ADR2 = tmp;
+ I2Cx->I2MASK2 = I2C_I2MASK_MASK((uint32_t) \
+ (OwnSlaveAddrConfigStruct->SlaveAddrMaskValue));
+ break;
+ case 3:
+ I2Cx->I2ADR3 = tmp;
+ I2Cx->I2MASK3 = I2C_I2MASK_MASK((uint32_t) \
+ (OwnSlaveAddrConfigStruct->SlaveAddrMaskValue));
+ break;
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Configures functionality in I2C monitor mode
+ * @param[in] I2Cx I2C peripheral selected, should be
+ * - LPC_I2C0
+ * - LPC_I2C1
+ * - LPC_I2C2
+ * @param[in] MonitorCfgType Monitor Configuration type, should be:
+ * - I2C_MONITOR_CFG_SCL_OUTPUT: I2C module can 'stretch'
+ * the clock line (hold it low) until it has had time to
+ * respond to an I2C interrupt.
+ * - I2C_MONITOR_CFG_MATCHALL: When this bit is set to '1'
+ * and the I2C is in monitor mode, an interrupt will be
+ * generated on ANY address received.
+ * @param[in] NewState New State of this function, should be:
+ * - ENABLE: Enable this function.
+ * - DISABLE: Disable this function.
+ * @return None
+ **********************************************************************/
+void I2C_MonitorModeConfig(LPC_I2C_TypeDef *I2Cx, uint32_t MonitorCfgType, FunctionalState NewState)
+{
+ CHECK_PARAM(PARAM_I2Cx(I2Cx));
+ CHECK_PARAM(PARAM_I2C_MONITOR_CFG(MonitorCfgType));
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
+
+ if (NewState == ENABLE)
+ {
+ I2Cx->MMCTRL |= MonitorCfgType;
+ }
+ else
+ {
+ I2Cx->MMCTRL &= (~MonitorCfgType) & I2C_I2MMCTRL_BITMASK;
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Enable/Disable I2C monitor mode
+ * @param[in] I2Cx I2C peripheral selected, should be
+ * - LPC_I2C0
+ * - LPC_I2C1
+ * - LPC_I2C2
+ * @param[in] NewState New State of this function, should be:
+ * - ENABLE: Enable monitor mode.
+ * - DISABLE: Disable monitor mode.
+ * @return None
+ **********************************************************************/
+void I2C_MonitorModeCmd(LPC_I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+ CHECK_PARAM(PARAM_I2Cx(I2Cx));
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
+
+ if (NewState == ENABLE)
+ {
+ I2Cx->MMCTRL |= I2C_I2MMCTRL_MM_ENA;
+ I2Cx->I2CONSET = I2C_I2CONSET_AA;
+ I2Cx->I2CONCLR = I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC;
+ }
+ else
+ {
+ I2Cx->MMCTRL &= (~I2C_I2MMCTRL_MM_ENA) & I2C_I2MMCTRL_BITMASK;
+ I2Cx->I2CONCLR = I2C_I2CONCLR_SIC | I2C_I2CONCLR_STAC | I2C_I2CONCLR_AAC;
+ }
+ I2C_MonitorBufferIndex = 0;
+}
+
+
+/*********************************************************************//**
+ * @brief Get data from I2C data buffer in monitor mode.
+ * @param[in] I2Cx I2C peripheral selected, should be
+ * - LPC_I2C0
+ * - LPC_I2C1
+ * - LPC_I2C2
+ * @return None
+ * Note: In monitor mode, the I2C module may lose the ability to stretch
+ * the clock (stall the bus) if the ENA_SCL bit is not set. This means that
+ * the processor will have a limited amount of time to read the contents of
+ * the data received on the bus. If the processor reads the I2DAT shift
+ * register, as it ordinarily would, it could have only one bit-time to
+ * respond to the interrupt before the received data is overwritten by
+ * new data.
+ **********************************************************************/
+uint8_t I2C_MonitorGetDatabuffer(LPC_I2C_TypeDef *I2Cx)
+{
+ CHECK_PARAM(PARAM_I2Cx(I2Cx));
+ return ((uint8_t)(I2Cx->I2DATA_BUFFER));
+}
+
+/*********************************************************************//**
+ * @brief Get data from I2C data buffer in monitor mode.
+ * @param[in] I2Cx I2C peripheral selected, should be
+ * - LPC_I2C0
+ * - LPC_I2C1
+ * - LPC_I2C2
+ * @return None
+ * Note: In monitor mode, the I2C module may lose the ability to stretch
+ * the clock (stall the bus) if the ENA_SCL bit is not set. This means that
+ * the processor will have a limited amount of time to read the contents of
+ * the data received on the bus. If the processor reads the I2DAT shift
+ * register, as it ordinarily would, it could have only one bit-time to
+ * respond to the interrupt before the received data is overwritten by
+ * new data.
+ **********************************************************************/
+BOOL_8 I2C_MonitorHandler(LPC_I2C_TypeDef *I2Cx, uint8_t *buffer, uint32_t size)
+{
+ BOOL_8 ret=FALSE;
+
+ I2Cx->I2CONCLR = I2C_I2CONCLR_SIC;
+
+ buffer[I2C_MonitorBufferIndex] = (uint8_t)(I2Cx->I2DATA_BUFFER);
+ I2C_MonitorBufferIndex++;
+ if(I2C_MonitorBufferIndex >= size)
+ {
+ ret = TRUE;
+ }
+ return ret;
+}
+/*********************************************************************//**
+ * @brief Get status of Master Transfer
+ * @param[in] I2Cx I2C peripheral selected, should be:
+ * - LPC_I2C0
+ * - LPC_I2C1
+ * - LPC_I2C2
+ * @return Master transfer status, could be:
+ * - TRUE master transfer completed
+ * - FALSE master transfer have not completed yet
+ **********************************************************************/
+uint32_t I2C_MasterTransferComplete(LPC_I2C_TypeDef *I2Cx)
+{
+ uint32_t retval, tmp;
+ tmp = I2C_getNum(I2Cx);
+ retval = I2C_MasterComplete[tmp];
+ I2C_MasterComplete[tmp] = FALSE;
+ return retval;
+}
+
+/*********************************************************************//**
+ * @brief Get status of Slave Transfer
+ * @param[in] I2Cx I2C peripheral selected, should be:
+ * - LPC_I2C0
+ * - LPC_I2C1
+ * - LPC_I2C2
+ * @return Complete status, could be: TRUE/FALSE
+ **********************************************************************/
+uint32_t I2C_SlaveTransferComplete(LPC_I2C_TypeDef *I2Cx)
+{
+ uint32_t retval, tmp;
+ tmp = I2C_getNum(I2Cx);
+ retval = I2C_SlaveComplete[tmp];
+ I2C_SlaveComplete[tmp] = FALSE;
+ return retval;
+}
+
+
+
+/**
+ * @}
+ */
+
+#endif /* _I2C */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/src/shared/cmsis/Drivers/source/lpc17xx_i2s.c b/src/shared/cmsis/Drivers/source/lpc17xx_i2s.c
@@ -0,0 +1,664 @@
+/**********************************************************************
+* $Id$ lpc17xx_i2s.c 2010-09-23
+*//**
+* @file lpc17xx_i2s.c
+* @brief Contains all functions support for I2S firmware
+* library on LPC17xx
+* @version 3.1
+* @date 23. Sep. 2010
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2010, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @addtogroup I2S
+ * @{
+ */
+
+/* Includes ------------------------------------------------------------------- */
+#include "lpc17xx_i2s.h"
+#include "lpc17xx_clkpwr.h"
+
+
+/* If this source file built with example, the LPC17xx FW library configuration
+ * file in each example directory ("lpc17xx_libcfg.h") must be included,
+ * otherwise the default FW library configuration file must be included instead
+ */
+#ifdef __BUILD_WITH_EXAMPLE__
+#include "lpc17xx_libcfg.h"
+#else
+#include "lpc17xx_libcfg_default.h"
+#endif /* __BUILD_WITH_EXAMPLE__ */
+
+
+#ifdef _I2S
+
+/* Private Functions ---------------------------------------------------------- */
+
+static uint8_t i2s_GetWordWidth(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
+static uint8_t i2s_GetChannel(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
+
+/********************************************************************//**
+ * @brief Get I2S wordwidth value
+ * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
+ * @param[in] TRMode is the I2S mode, should be:
+ * - I2S_TX_MODE = 0: transmit mode
+ * - I2S_RX_MODE = 1: receive mode
+ * @return The wordwidth value, should be: 8,16 or 32
+ *********************************************************************/
+static uint8_t i2s_GetWordWidth(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode) {
+ uint8_t value;
+
+ CHECK_PARAM(PARAM_I2Sx(I2Sx));
+ CHECK_PARAM(PARAM_I2S_TRX(TRMode));
+
+ if (TRMode == I2S_TX_MODE) {
+ value = (I2Sx->I2SDAO) & 0x03; /* get wordwidth bit */
+ } else {
+ value = (I2Sx->I2SDAI) & 0x03; /* get wordwidth bit */
+ }
+ switch (value) {
+ case I2S_WORDWIDTH_8:
+ return 8;
+ case I2S_WORDWIDTH_16:
+ return 16;
+ default:
+ return 32;
+ }
+}
+
+/********************************************************************//**
+ * @brief Get I2S channel value
+ * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
+ * @param[in] TRMode is the I2S mode, should be:
+ * - I2S_TX_MODE = 0: transmit mode
+ * - I2S_RX_MODE = 1: receive mode
+ * @return The channel value, should be: 1(mono) or 2(stereo)
+ *********************************************************************/
+static uint8_t i2s_GetChannel(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode) {
+ uint8_t value;
+
+ CHECK_PARAM(PARAM_I2Sx(I2Sx));
+ CHECK_PARAM(PARAM_I2S_TRX(TRMode));
+
+ if (TRMode == I2S_TX_MODE) {
+ value = ((I2Sx->I2SDAO) & 0x04)>>2; /* get bit[2] */
+ } else {
+ value = ((I2Sx->I2SDAI) & 0x04)>>2; /* get bit[2] */
+ }
+ if(value == I2S_MONO) return 1;
+ return 2;
+}
+
+/* End of Private Functions --------------------------------------------------- */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @addtogroup I2S_Public_Functions
+ * @{
+ */
+
+/********************************************************************//**
+ * @brief Initialize I2S
+ * - Turn on power and clock
+ * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
+ * @return none
+ *********************************************************************/
+void I2S_Init(LPC_I2S_TypeDef *I2Sx) {
+ CHECK_PARAM(PARAM_I2Sx(I2Sx));
+
+ // Turn on power and clock
+ CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCI2S, ENABLE);
+ LPC_I2S->I2SDAI = LPC_I2S->I2SDAO = 0x00;
+}
+
+/********************************************************************//**
+ * @brief Configuration I2S, setting:
+ * - master/slave mode
+ * - wordwidth value
+ * - channel mode
+ * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
+ * @param[in] TRMode transmit/receive mode, should be:
+ * - I2S_TX_MODE = 0: transmit mode
+ * - I2S_RX_MODE = 1: receive mode
+ * @param[in] ConfigStruct pointer to I2S_CFG_Type structure
+ * which will be initialized.
+ * @return none
+ *********************************************************************/
+void I2S_Config(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, I2S_CFG_Type* ConfigStruct)
+{
+ uint32_t bps, config;
+
+ CHECK_PARAM(PARAM_I2Sx(I2Sx));
+
+ CHECK_PARAM(PARAM_I2S_WORDWIDTH(ConfigStruct->wordwidth));
+ CHECK_PARAM(PARAM_I2S_CHANNEL(ConfigStruct->mono));
+ CHECK_PARAM(PARAM_I2S_STOP(ConfigStruct->stop));
+ CHECK_PARAM(PARAM_I2S_RESET(ConfigStruct->reset));
+ CHECK_PARAM(PARAM_I2S_WS_SEL(ConfigStruct->ws_sel));
+ CHECK_PARAM(PARAM_I2S_MUTE(ConfigStruct->mute));
+
+ /* Setup clock */
+ bps = (ConfigStruct->wordwidth +1)*8;
+
+ /* Calculate audio config */
+ config = (bps - 1)<<6 | (ConfigStruct->ws_sel)<<5 | (ConfigStruct->reset)<<4 |
+ (ConfigStruct->stop)<<3 | (ConfigStruct->mono)<<2 | (ConfigStruct->wordwidth);
+
+ if(TRMode == I2S_RX_MODE){
+ LPC_I2S->I2SDAI = config;
+ }else{
+ LPC_I2S->I2SDAO = config;
+ }
+}
+
+/********************************************************************//**
+ * @brief DeInitial both I2S transmit or receive
+ * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
+ * @return none
+ *********************************************************************/
+void I2S_DeInit(LPC_I2S_TypeDef *I2Sx) {
+ CHECK_PARAM(PARAM_I2Sx(I2Sx));
+
+ // Turn off power and clock
+ CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCI2S, DISABLE);
+}
+
+/********************************************************************//**
+ * @brief Get I2S Buffer Level
+ * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
+ * @param[in] TRMode Transmit/receive mode, should be:
+ * - I2S_TX_MODE = 0: transmit mode
+ * - I2S_RX_MODE = 1: receive mode
+ * @return current level of Transmit/Receive Buffer
+ *********************************************************************/
+uint8_t I2S_GetLevel(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode)
+{
+ CHECK_PARAM(PARAM_I2Sx(I2Sx));
+ CHECK_PARAM(PARAM_I2S_TRX(TRMode));
+
+ if(TRMode == I2S_TX_MODE)
+ {
+ return ((I2Sx->I2SSTATE >> 16) & 0xFF);
+ }
+ else
+ {
+ return ((I2Sx->I2SSTATE >> 8) & 0xFF);
+ }
+}
+
+/********************************************************************//**
+ * @brief I2S Start: clear all STOP,RESET and MUTE bit, ready to operate
+ * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
+ * @return none
+ *********************************************************************/
+void I2S_Start(LPC_I2S_TypeDef *I2Sx)
+{
+ //Clear STOP,RESET and MUTE bit
+ I2Sx->I2SDAO &= ~I2S_DAI_RESET;
+ I2Sx->I2SDAI &= ~I2S_DAI_RESET;
+ I2Sx->I2SDAO &= ~I2S_DAI_STOP;
+ I2Sx->I2SDAI &= ~I2S_DAI_STOP;
+ I2Sx->I2SDAO &= ~I2S_DAI_MUTE;
+}
+
+/********************************************************************//**
+ * @brief I2S Send data
+ * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
+ * @param[in] BufferData pointer to uint32_t is the data will be send
+ * @return none
+ *********************************************************************/
+void I2S_Send(LPC_I2S_TypeDef *I2Sx, uint32_t BufferData) {
+ CHECK_PARAM(PARAM_I2Sx(I2Sx));
+
+ I2Sx->I2STXFIFO = BufferData;
+}
+
+/********************************************************************//**
+ * @brief I2S Receive Data
+ * @param[in] I2Sx pointer to LPC_I2S_TypeDef
+ * @return received value
+ *********************************************************************/
+uint32_t I2S_Receive(LPC_I2S_TypeDef* I2Sx) {
+ CHECK_PARAM(PARAM_I2Sx(I2Sx));
+
+ return (I2Sx->I2SRXFIFO);
+
+}
+
+/********************************************************************//**
+ * @brief I2S Pause
+ * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
+ * @param[in] TRMode is transmit/receive mode, should be:
+ * - I2S_TX_MODE = 0: transmit mode
+ * - I2S_RX_MODE = 1: receive mode
+ * @return none
+ *********************************************************************/
+void I2S_Pause(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode) {
+ CHECK_PARAM(PARAM_I2Sx(I2Sx));
+ CHECK_PARAM(PARAM_I2S_TRX(TRMode));
+
+ if (TRMode == I2S_TX_MODE) //Transmit mode
+ {
+ I2Sx->I2SDAO |= I2S_DAO_STOP;
+ } else //Receive mode
+ {
+ I2Sx->I2SDAI |= I2S_DAI_STOP;
+ }
+}
+
+/********************************************************************//**
+ * @brief I2S Mute
+ * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
+ * @param[in] TRMode is transmit/receive mode, should be:
+ * - I2S_TX_MODE = 0: transmit mode
+ * - I2S_RX_MODE = 1: receive mode
+ * @return none
+ *********************************************************************/
+void I2S_Mute(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode) {
+ CHECK_PARAM(PARAM_I2Sx(I2Sx));
+ CHECK_PARAM(PARAM_I2S_TRX(TRMode));
+
+ if (TRMode == I2S_TX_MODE) //Transmit mode
+ {
+ I2Sx->I2SDAO |= I2S_DAO_MUTE;
+ } else //Receive mode
+ {
+ I2Sx->I2SDAI |= I2S_DAI_MUTE;
+ }
+}
+
+/********************************************************************//**
+ * @brief I2S Stop
+ * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
+ * @param[in] TRMode is transmit/receive mode, should be:
+ * - I2S_TX_MODE = 0: transmit mode
+ * - I2S_RX_MODE = 1: receive mode
+ * @return none
+ *********************************************************************/
+void I2S_Stop(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode) {
+ CHECK_PARAM(PARAM_I2Sx(I2Sx));
+ CHECK_PARAM(PARAM_I2S_TRX(TRMode));
+
+ if (TRMode == I2S_TX_MODE) //Transmit mode
+ {
+ I2Sx->I2SDAO &= ~I2S_DAO_MUTE;
+ I2Sx->I2SDAO |= I2S_DAO_STOP;
+ I2Sx->I2SDAO |= I2S_DAO_RESET;
+ } else //Receive mode
+ {
+ I2Sx->I2SDAI |= I2S_DAI_STOP;
+ I2Sx->I2SDAI |= I2S_DAI_RESET;
+ }
+}
+
+/********************************************************************//**
+ * @brief Set frequency for I2S
+ * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
+ * @param[in] Freq is the frequency for I2S will be set. It can range
+ * from 16-96 kHz(16, 22.05, 32, 44.1, 48, 96kHz)
+ * @param[in] TRMode is transmit/receive mode, should be:
+ * - I2S_TX_MODE = 0: transmit mode
+ * - I2S_RX_MODE = 1: receive mode
+ * @return Status: ERROR or SUCCESS
+ *********************************************************************/
+Status I2S_FreqConfig(LPC_I2S_TypeDef *I2Sx, uint32_t Freq, uint8_t TRMode) {
+
+ uint32_t i2s_clk;
+ uint8_t channel, wordwidth;
+ uint32_t x, y;
+ uint64_t divider;
+ uint16_t dif;
+ uint16_t x_divide;
+ uint16_t y_divide = 0;
+ uint16_t err, ErrorOptimal = 0xFFFF;
+
+ uint32_t N;
+
+ CHECK_PARAM(PARAM_I2Sx(I2Sx));
+ CHECK_PARAM(PRAM_I2S_FREQ(Freq));
+ CHECK_PARAM(PARAM_I2S_TRX(TRMode));
+
+ //Get the frequency of PCLK_I2S
+ i2s_clk = CLKPWR_GetPCLK(CLKPWR_PCLKSEL_I2S);
+
+ if(TRMode == I2S_TX_MODE)
+ {
+ channel = i2s_GetChannel(I2Sx,I2S_TX_MODE);
+ wordwidth = i2s_GetWordWidth(I2Sx,I2S_TX_MODE);
+ }
+ else
+ {
+ channel = i2s_GetChannel(I2Sx,I2S_RX_MODE);
+ wordwidth = i2s_GetWordWidth(I2Sx,I2S_RX_MODE);
+ }
+
+ /* Calculate X and Y divider
+ * The MCLK rate for the I2S transmitter is determined by the value
+ * in the I2STXRATE/I2SRXRATE register. The required I2STXRATE/I2SRXRATE
+ * setting depends on the desired audio sample rate desired, the format
+ * (stereo/mono) used, and the data size.
+ * The formula is:
+ * I2S_MCLK = PCLK_I2S * (X/Y) / 2
+ * In that, Y must be greater than or equal to X. X should divides evenly
+ * into Y.
+ * We have:
+ * I2S_MCLK = Freq * channel*wordwidth * (I2STXBITRATE+1);
+ * So: (X/Y) = (Freq * channel*wordwidth * (I2STXBITRATE+1))*2/PCLK_I2S
+ * We use a loop function to chose the most suitable X,Y value
+ */
+
+ /* divider is a fixed point number with 16 fractional bits */
+ divider = (((uint64_t)Freq *channel*wordwidth * 2)<<16) / i2s_clk;
+
+ /* find N that make x/y <= 1 -> divider <= 2^16 */
+ for(N=64;N>0;N--){
+ if((divider*N) < (1<<16)) break;
+ }
+
+ if(N == 0) return ERROR;
+
+ divider *= N;
+
+ for (y = 255; y > 0; y--) {
+ x = y * divider;
+ if(x & (0xFF000000)) continue;
+ dif = x & 0xFFFF;
+ if(dif>0x8000) err = 0x10000-dif;
+ else err = dif;
+ if (err == 0)
+ {
+ y_divide = y;
+ break;
+ }
+ else if (err < ErrorOptimal)
+ {
+ ErrorOptimal = err;
+ y_divide = y;
+ }
+ }
+ x_divide = ((uint64_t)y_divide * Freq *(channel*wordwidth)* N * 2)/i2s_clk;
+ if(x_divide >= 256) x_divide = 0xFF;
+ if(x_divide == 0) x_divide = 1;
+
+ if (TRMode == I2S_TX_MODE)// Transmitter
+ {
+ I2Sx->I2STXBITRATE = N-1;
+ I2Sx->I2STXRATE = y_divide | (x_divide << 8);
+ } else //Receiver
+ {
+ I2Sx->I2SRXBITRATE = N-1;
+ I2Sx->I2STXRATE = y_divide | (x_divide << 8);
+ }
+ return SUCCESS;
+}
+
+/********************************************************************//**
+ * @brief I2S set bitrate
+ * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
+ * @param[in] bitrate value will be set
+ * bitrate value should be in range: 0 .. 63
+ * @param[in] TRMode is transmit/receive mode, should be:
+ * - I2S_TX_MODE = 0: transmit mode
+ * - I2S_RX_MODE = 1: receive mode
+ * @return none
+ *********************************************************************/
+void I2S_SetBitRate(LPC_I2S_TypeDef *I2Sx, uint8_t bitrate, uint8_t TRMode)
+{
+ CHECK_PARAM(PARAM_I2Sx(I2Sx));
+ CHECK_PARAM(PARAM_I2S_BITRATE(bitrate));
+ CHECK_PARAM(PARAM_I2S_TRX(TRMode));
+
+ if(TRMode == I2S_TX_MODE)
+ {
+ I2Sx->I2STXBITRATE = bitrate;
+ }
+ else
+ {
+ I2Sx->I2SRXBITRATE = bitrate;
+ }
+}
+
+/********************************************************************//**
+ * @brief Configuration operating mode for I2S
+ * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
+ * @param[in] ModeConfig pointer to I2S_MODEConf_Type will be used to
+ * configure
+ * @param[in] TRMode is transmit/receive mode, should be:
+ * - I2S_TX_MODE = 0: transmit mode
+ * - I2S_RX_MODE = 1: receive mode
+ * @return none
+ *********************************************************************/
+void I2S_ModeConfig(LPC_I2S_TypeDef *I2Sx, I2S_MODEConf_Type* ModeConfig,
+ uint8_t TRMode)
+{
+ CHECK_PARAM(PARAM_I2Sx(I2Sx));
+ CHECK_PARAM(PARAM_I2S_CLKSEL(ModeConfig->clksel));
+ CHECK_PARAM(PARAM_I2S_4PIN(ModeConfig->fpin));
+ CHECK_PARAM(PARAM_I2S_MCLK(ModeConfig->mcena));
+ CHECK_PARAM(PARAM_I2S_TRX(TRMode));
+
+ if (TRMode == I2S_TX_MODE) {
+ I2Sx->I2STXMODE &= ~0x0F; //clear bit 3:0 in I2STXMODE register
+ if (ModeConfig->clksel == I2S_CLKSEL_MCLK) {
+ I2Sx->I2STXMODE |= 0x02;
+ }
+ if (ModeConfig->fpin == I2S_4PIN_ENABLE) {
+ I2Sx->I2STXMODE |= (1 << 2);
+ }
+ if (ModeConfig->mcena == I2S_MCLK_ENABLE) {
+ I2Sx->I2STXMODE |= (1 << 3);
+ }
+ } else {
+ I2Sx->I2SRXMODE &= ~0x0F; //clear bit 3:0 in I2STXMODE register
+ if (ModeConfig->clksel == I2S_CLKSEL_MCLK) {
+ I2Sx->I2SRXMODE |= 0x02;
+ }
+ if (ModeConfig->fpin == I2S_4PIN_ENABLE) {
+ I2Sx->I2SRXMODE |= (1 << 2);
+ }
+ if (ModeConfig->mcena == I2S_MCLK_ENABLE) {
+ I2Sx->I2SRXMODE |= (1 << 3);
+ }
+ }
+}
+
+/********************************************************************//**
+ * @brief Configure DMA operation for I2S
+ * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
+ * @param[in] DMAConfig pointer to I2S_DMAConf_Type will be used to configure
+ * @param[in] TRMode is transmit/receive mode, should be:
+ * - I2S_TX_MODE = 0: transmit mode
+ * - I2S_RX_MODE = 1: receive mode
+ * @return none
+ *********************************************************************/
+void I2S_DMAConfig(LPC_I2S_TypeDef *I2Sx, I2S_DMAConf_Type* DMAConfig,
+ uint8_t TRMode)
+{
+ CHECK_PARAM(PARAM_I2Sx(I2Sx));
+ CHECK_PARAM(PARAM_I2S_DMA(DMAConfig->DMAIndex));
+ CHECK_PARAM(PARAM_I2S_DMA_DEPTH(DMAConfig->depth));
+ CHECK_PARAM(PARAM_I2S_TRX(TRMode));
+
+ if (TRMode == I2S_RX_MODE) {
+ if (DMAConfig->DMAIndex == I2S_DMA_1) {
+ LPC_I2S->I2SDMA1 = (DMAConfig->depth) << 8;
+ } else {
+ LPC_I2S->I2SDMA2 = (DMAConfig->depth) << 8;
+ }
+ } else {
+ if (DMAConfig->DMAIndex == I2S_DMA_1) {
+ LPC_I2S->I2SDMA1 = (DMAConfig->depth) << 16;
+ } else {
+ LPC_I2S->I2SDMA2 = (DMAConfig->depth) << 16;
+ }
+ }
+}
+
+/********************************************************************//**
+ * @brief Enable/Disable DMA operation for I2S
+ * @param[in] I2Sx: I2S peripheral selected, should be: LPC_I2S
+ * @param[in] DMAIndex chose what DMA is used, should be:
+ * - I2S_DMA_1 = 0: DMA1
+ * - I2S_DMA_2 = 1: DMA2
+ * @param[in] TRMode is transmit/receive mode, should be:
+ * - I2S_TX_MODE = 0: transmit mode
+ * - I2S_RX_MODE = 1: receive mode
+ * @param[in] NewState is new state of DMA operation, should be:
+ * - ENABLE
+ * - DISABLE
+ * @return none
+ *********************************************************************/
+void I2S_DMACmd(LPC_I2S_TypeDef *I2Sx, uint8_t DMAIndex, uint8_t TRMode,
+ FunctionalState NewState)
+{
+ CHECK_PARAM(PARAM_I2Sx(I2Sx));
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
+ CHECK_PARAM(PARAM_I2S_DMA(DMAIndex));
+ CHECK_PARAM(PARAM_I2S_TRX(TRMode));
+
+ if (TRMode == I2S_RX_MODE) {
+ if (DMAIndex == I2S_DMA_1) {
+ if (NewState == ENABLE)
+ I2Sx->I2SDMA1 |= 0x01;
+ else
+ I2Sx->I2SDMA1 &= ~0x01;
+ } else {
+ if (NewState == ENABLE)
+ I2Sx->I2SDMA2 |= 0x01;
+ else
+ I2Sx->I2SDMA2 &= ~0x01;
+ }
+ } else {
+ if (DMAIndex == I2S_DMA_1) {
+ if (NewState == ENABLE)
+ I2Sx->I2SDMA1 |= 0x02;
+ else
+ I2Sx->I2SDMA1 &= ~0x02;
+ } else {
+ if (NewState == ENABLE)
+ I2Sx->I2SDMA2 |= 0x02;
+ else
+ I2Sx->I2SDMA2 &= ~0x02;
+ }
+ }
+}
+
+/********************************************************************//**
+ * @brief Configure IRQ for I2S
+ * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
+ * @param[in] TRMode is transmit/receive mode, should be:
+ * - I2S_TX_MODE = 0: transmit mode
+ * - I2S_RX_MODE = 1: receive mode
+ * @param[in] level is the FIFO level that triggers IRQ request
+ * @return none
+ *********************************************************************/
+void I2S_IRQConfig(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, uint8_t level) {
+ CHECK_PARAM(PARAM_I2Sx(I2Sx));
+ CHECK_PARAM(PARAM_I2S_TRX(TRMode));
+ CHECK_PARAM(PARAM_I2S_IRQ_LEVEL(level));
+
+ if (TRMode == I2S_RX_MODE) {
+ I2Sx->I2SIRQ |= (level << 8);
+ } else {
+ I2Sx->I2SIRQ |= (level << 16);
+ }
+}
+
+/********************************************************************//**
+ * @brief Enable/Disable IRQ for I2S
+ * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
+ * @param[in] TRMode is transmit/receive mode, should be:
+ * - I2S_TX_MODE = 0: transmit mode
+ * - I2S_RX_MODE = 1: receive mode
+ * @param[in] NewState is new state of DMA operation, should be:
+ * - ENABLE
+ * - DISABLE
+ * @return none
+ *********************************************************************/
+void I2S_IRQCmd(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, FunctionalState NewState) {
+ CHECK_PARAM(PARAM_I2Sx(I2Sx));
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
+
+ if (TRMode == I2S_RX_MODE) {
+ if (NewState == ENABLE)
+ I2Sx->I2SIRQ |= 0x01;
+ else
+ I2Sx->I2SIRQ &= ~0x01;
+ //Enable DMA
+
+ } else {
+ if (NewState == ENABLE)
+ I2Sx->I2SIRQ |= 0x02;
+ else
+ I2Sx->I2SIRQ &= ~0x02;
+ }
+}
+
+/********************************************************************//**
+ * @brief Get I2S interrupt status
+ * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
+ * @param[in] TRMode is transmit/receive mode, should be:
+ * - I2S_TX_MODE = 0: transmit mode
+ * - I2S_RX_MODE = 1: receive mode
+ * @return FunctionState should be:
+ * - ENABLE: interrupt is enable
+ * - DISABLE: interrupt is disable
+ *********************************************************************/
+FunctionalState I2S_GetIRQStatus(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode)
+{
+ CHECK_PARAM(PARAM_I2Sx(I2Sx));
+ if(TRMode == I2S_TX_MODE)
+ return ((FunctionalState)((I2Sx->I2SIRQ >> 1)&0x01));
+ else
+ return ((FunctionalState)((I2Sx->I2SIRQ)&0x01));
+}
+
+/********************************************************************//**
+ * @brief Get I2S interrupt depth
+ * @param[in] I2Sx I2S peripheral selected, should be: LPC_I2S
+ * @param[in] TRMode is transmit/receive mode, should be:
+ * - I2S_TX_MODE = 0: transmit mode
+ * - I2S_RX_MODE = 1: receive mode
+ * @return depth of FIFO level on which to create an irq request
+ *********************************************************************/
+uint8_t I2S_GetIRQDepth(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode)
+{
+ CHECK_PARAM(PARAM_I2Sx(I2Sx));
+ if(TRMode == I2S_TX_MODE)
+ return (((I2Sx->I2SIRQ)>>16)&0xFF);
+ else
+ return (((I2Sx->I2SIRQ)>>8)&0xFF);
+}
+/**
+ * @}
+ */
+
+#endif /* _I2S */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
+
diff --git a/src/shared/cmsis/Drivers/source/lpc17xx_iap.c b/src/shared/cmsis/Drivers/source/lpc17xx_iap.c
@@ -0,0 +1,310 @@
+/**********************************************************************
+* $Id$ lpc17xx_iap.c 2012-04-18
+*//**
+* @file lpc17xx_iap.c
+ * @brief Contains all functions support for IAP on lpc17xx
+* @version 1.0
+* @date 18. April. 2012
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+#include "lpc17xx_iap.h"
+#include "system_LPC17xx.h"
+
+// IAP Command
+typedef void (*IAP)(uint32_t *cmd,uint32_t *result);
+IAP iap_entry = (IAP) IAP_LOCATION;
+#define IAP_Call iap_entry
+
+/** @addtogroup IAP_Public_Functions IAP Public Function
+ * @ingroup IAP
+ * @{
+ */
+
+
+/*********************************************************************//**
+ * @brief Get Sector Number
+ *
+ * @param[in] adr Sector Address
+ *
+ * @return Sector Number.
+ *
+ **********************************************************************/
+ uint32_t GetSecNum (uint32_t adr)
+{
+ uint32_t n;
+
+ n = adr >> 12; // 4kB Sector
+ if (n >= 0x10) {
+ n = 0x0E + (n >> 3); // 32kB Sector
+ }
+
+ return (n); // Sector Number
+}
+
+/*********************************************************************//**
+ * @brief Prepare sector(s) for write operation
+ *
+ * @param[in] start_sec The number of start sector
+ * @param[in] end_sec The number of end sector
+ *
+ * @return CMD_SUCCESS/BUSY/INVALID_SECTOR.
+ *
+ **********************************************************************/
+IAP_STATUS_CODE PrepareSector(uint32_t start_sec, uint32_t end_sec)
+{
+ IAP_COMMAND_Type command;
+ command.cmd = IAP_PREPARE; // Prepare Sector for Write
+ command.param[0] = start_sec; // Start Sector
+ command.param[1] = end_sec; // End Sector
+ IAP_Call (&command.cmd, &command.status); // Call IAP Command
+ return (IAP_STATUS_CODE)command.status;
+}
+
+/*********************************************************************//**
+ * @brief Copy RAM to Flash
+ *
+ * @param[in] dest destination buffer (in Flash memory).
+ * @param[in] source source buffer (in RAM).
+ * @param[in] size the write size.
+ *
+ * @return CMD_SUCCESS.
+ * SRC_ADDR_ERROR/DST_ADDR_ERROR
+ * SRC_ADDR_NOT_MAPPED/DST_ADDR_NOT_MAPPED
+ * COUNT_ERROR/SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION
+ * BUSY
+ *
+ **********************************************************************/
+IAP_STATUS_CODE CopyRAM2Flash(uint8_t * dest, uint8_t* source, IAP_WRITE_SIZE size)
+{
+ uint32_t sec;
+ IAP_STATUS_CODE status;
+ IAP_COMMAND_Type command;
+
+ // Prepare sectors
+ sec = GetSecNum((uint32_t)dest);
+ status = PrepareSector(sec, sec);
+ if(status != CMD_SUCCESS)
+ return status;
+
+ // write
+ command.cmd = IAP_COPY_RAM2FLASH; // Copy RAM to Flash
+ command.param[0] = (uint32_t)dest; // Destination Flash Address
+ command.param[1] = (uint32_t)source; // Source RAM Address
+ command.param[2] = size; // Number of bytes
+ command.param[3] = SystemCoreClock / 1000; // CCLK in kHz
+ IAP_Call (&command.cmd, &command.status); // Call IAP Command
+
+ return (IAP_STATUS_CODE)command.status; // Finished without Errors
+}
+
+/*********************************************************************//**
+ * @brief Erase sector(s)
+ *
+ * @param[in] start_sec The number of start sector
+ * @param[in] end_sec The number of end sector
+ *
+ * @return CMD_SUCCESS.
+ * INVALID_SECTOR
+ * SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION
+ * BUSY
+ *
+ **********************************************************************/
+IAP_STATUS_CODE EraseSector(uint32_t start_sec, uint32_t end_sec)
+{
+ IAP_COMMAND_Type command;
+ IAP_STATUS_CODE status;
+
+ // Prepare sectors
+ status = PrepareSector(start_sec, end_sec);
+ if(status != CMD_SUCCESS)
+ return status;
+
+ // Erase sectors
+ command.cmd = IAP_ERASE; // Prepare Sector for Write
+ command.param[0] = start_sec; // Start Sector
+ command.param[1] = end_sec; // End Sector
+ command.param[2] = SystemCoreClock / 1000; // CCLK in kHz
+ IAP_Call (&command.cmd, &command.status); // Call IAP Command
+ return (IAP_STATUS_CODE)command.status;
+}
+
+/*********************************************************************//**
+ * @brief Blank check sector(s)
+ *
+ * @param[in] start_sec The number of start sector
+ * @param[in] end_sec The number of end sector
+ * @param[out] first_nblank_loc The offset of the first non-blank word
+ * @param[out] first_nblank_val The value of the first non-blank word
+ *
+ * @return CMD_SUCCESS.
+ * INVALID_SECTOR
+ * SECTOR_NOT_BLANK
+ * BUSY
+ *
+ **********************************************************************/
+IAP_STATUS_CODE BlankCheckSector(uint32_t start_sec, uint32_t end_sec,
+ uint32_t *first_nblank_loc,
+ uint32_t *first_nblank_val)
+{
+ IAP_COMMAND_Type command;
+
+ command.cmd = IAP_BLANK_CHECK; // Prepare Sector for Write
+ command.param[0] = start_sec; // Start Sector
+ command.param[1] = end_sec; // End Sector
+ IAP_Call (&command.cmd, &command.status); // Call IAP Command
+
+ if(command.status == SECTOR_NOT_BLANK)
+ {
+ // Update out value
+ if(first_nblank_loc != NULL)
+ *first_nblank_loc = command.result[0];
+ if(first_nblank_val != NULL)
+ *first_nblank_val = command.result[1];
+ }
+
+ return (IAP_STATUS_CODE)command.status;
+}
+
+/*********************************************************************//**
+ * @brief Read part identification number
+ *
+ * @param[out] partID Part ID
+ *
+ * @return CMD_SUCCESS
+ *
+ **********************************************************************/
+IAP_STATUS_CODE ReadPartID(uint32_t *partID)
+{
+ IAP_COMMAND_Type command;
+ command.cmd = IAP_READ_PART_ID;
+ IAP_Call (&command.cmd, &command.status); // Call IAP Command
+
+ if(command.status == CMD_SUCCESS)
+ {
+ if(partID != NULL)
+ *partID = command.result[0];
+ }
+
+ return (IAP_STATUS_CODE)command.status;
+}
+
+/*********************************************************************//**
+ * @brief Read boot code version. The version is interpreted as <major>.<minor>.
+ *
+ * @param[out] major The major
+ * @param[out] minor The minor
+ *
+ * @return CMD_SUCCESS
+ *
+ **********************************************************************/
+IAP_STATUS_CODE ReadBootCodeVer(uint8_t *major, uint8_t* minor)
+{
+ IAP_COMMAND_Type command;
+ command.cmd = IAP_READ_BOOT_VER;
+ IAP_Call (&command.cmd, &command.status); // Call IAP Command
+
+ if(command.status == CMD_SUCCESS)
+ {
+ if(major != NULL)
+ *major = (command.result[0] >> 8) & 0xFF;
+ if(minor != NULL)
+ *minor = (command.result[0]) & 0xFF;
+ }
+
+ return (IAP_STATUS_CODE)command.status;
+}
+
+/*********************************************************************//**
+ * @brief Read Device serial number.
+ *
+ * @param[out] uid Serial number.
+ *
+ * @return CMD_SUCCESS
+ *
+ **********************************************************************/
+IAP_STATUS_CODE ReadDeviceSerialNum(uint32_t *uid)
+{
+ IAP_COMMAND_Type command;
+ command.cmd = IAP_READ_SERIAL_NUMBER;
+ IAP_Call (&command.cmd, &command.status); // Call IAP Command
+
+ if(command.status == CMD_SUCCESS)
+ {
+ if(uid != NULL)
+ {
+ uint32_t i = 0;
+ for(i = 0; i < 4; i++)
+ uid[i] = command.result[i];
+ }
+ }
+
+ return (IAP_STATUS_CODE)command.status;
+}
+
+/*********************************************************************//**
+ * @brief compare the memory contents at two locations.
+ *
+ * @param[in] addr1 The address of the 1st buffer (in RAM/Flash).
+ * @param[in] addr2 The address of the 2nd buffer (in RAM/Flash).
+ * @param[in] size Number of bytes to be compared; should be a multiple of 4.
+ *
+ * @return CMD_SUCCESS
+ * COMPARE_ERROR
+ * COUNT_ERROR (Byte count is not a multiple of 4)
+ * ADDR_ERROR
+ * ADDR_NOT_MAPPED
+ *
+ **********************************************************************/
+IAP_STATUS_CODE Compare(uint8_t *addr1, uint8_t *addr2, uint32_t size)
+{
+ IAP_COMMAND_Type command;
+ command.cmd = IAP_COMPARE;
+ command.param[0] = (uint32_t)addr1;
+ command.param[1] = (uint32_t)addr2;
+ command.param[2] = size;
+ IAP_Call (&command.cmd, &command.status); // Call IAP Command
+
+ return (IAP_STATUS_CODE)command.status;
+}
+
+/*********************************************************************//**
+ * @brief Re-invoke ISP.
+ *
+ * @param[in] None.
+ *
+ * @return None.
+ *
+ **********************************************************************/
+void InvokeISP(void)
+{
+ IAP_COMMAND_Type command;
+ command.cmd = IAP_REINVOKE_ISP;
+ IAP_Call (&command.cmd, &command.status); // Call IAP Command
+}
+
+/**
+ * @}
+ */
+
+
diff --git a/src/shared/cmsis/Drivers/source/lpc17xx_libcfg_default.c b/src/shared/cmsis/Drivers/source/lpc17xx_libcfg_default.c
@@ -0,0 +1,78 @@
+/**********************************************************************
+* $Id$ lpc17xx_libcfg_default.c 2010-05-21
+*//**
+* @file lpc17xx_libcfg_default.c
+* @brief Library configuration source file (default), used to build
+* library without examples
+* @version 2.0
+* @date 21. May. 2010
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2010, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Library group ----------------------------------------------------------- */
+/** @addtogroup LIBCFG_DEFAULT
+ * @{
+ */
+
+/* Includes ------------------------------------------------------------------- */
+#include "lpc17xx_libcfg_default.h"
+
+/* Public Functions ----------------------------------------------------------- */
+/** @addtogroup LIBCFG_DEFAULT_Public_Functions
+ * @{
+ */
+
+#ifndef __BUILD_WITH_EXAMPLE__
+
+#ifdef DEBUG
+/*******************************************************************************
+* @brief Reports the name of the source file and the source line number
+* where the CHECK_PARAM error has occurred.
+* @param[in] file Pointer to the source file name
+* @param[in] line assert_param error line source number
+* @return None
+*******************************************************************************/
+void check_failed(uint8_t *file, uint32_t line)
+{
+ (void)file;
+ (void)line;
+ /* User can add his own implementation to report the file name and line number,
+ ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+
+ /* Infinite loop */
+ while(1);
+}
+#endif /* DEBUG */
+
+#endif /* __BUILD_WITH_EXAMPLE__ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/src/shared/cmsis/Drivers/source/lpc17xx_mcpwm.c b/src/shared/cmsis/Drivers/source/lpc17xx_mcpwm.c
@@ -0,0 +1,509 @@
+/**********************************************************************
+* $Id$ lpc17xx_mcpwm.c 2010-05-21
+*//**
+* @file lpc17xx_mcpwm.c
+* @brief Contains all functions support for Motor Control PWM firmware
+* library on LPC17xx
+* @version 2.0
+* @date 21. May. 2010
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2010, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @addtogroup MCPWM
+ * @{
+ */
+
+/* Includes ------------------------------------------------------------------- */
+#include "lpc17xx_mcpwm.h"
+#include "lpc17xx_clkpwr.h"
+
+/* If this source file built with example, the LPC17xx FW library configuration
+ * file in each example directory ("lpc17xx_libcfg.h") must be included,
+ * otherwise the default FW library configuration file must be included instead
+ */
+#ifdef __BUILD_WITH_EXAMPLE__
+#include "lpc17xx_libcfg.h"
+#else
+#include "lpc17xx_libcfg_default.h"
+#endif /* __BUILD_WITH_EXAMPLE__ */
+
+
+#ifdef _MCPWM
+
+/* Public Functions ----------------------------------------------------------- */
+/** @addtogroup MCPWM_Public_Functions
+ * @{
+ */
+
+/*********************************************************************//**
+ * @brief Initializes the MCPWM peripheral
+ * @param[in] MCPWMx Motor Control PWM peripheral selected,
+ * Should be: LPC_MCPWM
+ * @return None
+ **********************************************************************/
+void MCPWM_Init(LPC_MCPWM_TypeDef *MCPWMx)
+{
+
+ /* Turn On MCPWM PCLK */
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCMC, ENABLE);
+ /* As default, peripheral clock for MCPWM module
+ * is set to FCCLK / 2 */
+ // CLKPWR_SetPCLKDiv(CLKPWR_PCLKSEL_MC, CLKPWR_PCLKSEL_CCLK_DIV_2);
+
+ MCPWMx->MCCAP_CLR = MCPWM_CAPCLR_CAP(0) | MCPWM_CAPCLR_CAP(1) | MCPWM_CAPCLR_CAP(2);
+ MCPWMx->MCINTFLAG_CLR = MCPWM_INT_ILIM(0) | MCPWM_INT_ILIM(1) | MCPWM_INT_ILIM(2) \
+ | MCPWM_INT_IMAT(0) | MCPWM_INT_IMAT(1) | MCPWM_INT_IMAT(2) \
+ | MCPWM_INT_ICAP(0) | MCPWM_INT_ICAP(1) | MCPWM_INT_ICAP(2);
+ MCPWMx->MCINTEN_CLR = MCPWM_INT_ILIM(0) | MCPWM_INT_ILIM(1) | MCPWM_INT_ILIM(2) \
+ | MCPWM_INT_IMAT(0) | MCPWM_INT_IMAT(1) | MCPWM_INT_IMAT(2) \
+ | MCPWM_INT_ICAP(0) | MCPWM_INT_ICAP(1) | MCPWM_INT_ICAP(2);
+}
+
+
+/*********************************************************************//**
+ * @brief Configures each channel in MCPWM peripheral according to the
+ * specified parameters in the MCPWM_CHANNEL_CFG_Type.
+ * @param[in] MCPWMx Motor Control PWM peripheral selected
+ * should be: LPC_MCPWM
+ * @param[in] channelNum Channel number, should be: 0..2.
+ * @param[in] channelSetup Pointer to a MCPWM_CHANNEL_CFG_Type structure
+* that contains the configuration information for the
+* specified MCPWM channel.
+ * @return None
+ **********************************************************************/
+void MCPWM_ConfigChannel(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
+ MCPWM_CHANNEL_CFG_Type * channelSetup)
+{
+ if (channelNum <= 2) {
+ if (channelNum == 0) {
+ MCPWMx->MCTIM0 = channelSetup->channelTimercounterValue;
+ MCPWMx->MCPER0 = channelSetup->channelPeriodValue;
+ MCPWMx->MCPW0 = channelSetup->channelPulsewidthValue;
+ } else if (channelNum == 1) {
+ MCPWMx->MCTIM1 = channelSetup->channelTimercounterValue;
+ MCPWMx->MCPER1 = channelSetup->channelPeriodValue;
+ MCPWMx->MCPW1 = channelSetup->channelPulsewidthValue;
+ } else if (channelNum == 2) {
+ MCPWMx->MCTIM2 = channelSetup->channelTimercounterValue;
+ MCPWMx->MCPER2 = channelSetup->channelPeriodValue;
+ MCPWMx->MCPW2 = channelSetup->channelPulsewidthValue;
+ } else {
+ return;
+ }
+
+ if (channelSetup->channelType /* == MCPWM_CHANNEL_CENTER_MODE */){
+ MCPWMx->MCCON_SET = MCPWM_CON_CENTER(channelNum);
+ } else {
+ MCPWMx->MCCON_CLR = MCPWM_CON_CENTER(channelNum);
+ }
+
+ if (channelSetup->channelPolarity /* == MCPWM_CHANNEL_PASSIVE_HI */){
+ MCPWMx->MCCON_SET = MCPWM_CON_POLAR(channelNum);
+ } else {
+ MCPWMx->MCCON_CLR = MCPWM_CON_POLAR(channelNum);
+ }
+
+ if (channelSetup->channelDeadtimeEnable /* == ENABLE */){
+ MCPWMx->MCCON_SET = MCPWM_CON_DTE(channelNum);
+ MCPWMx->MCDEADTIME &= ~(MCPWM_DT(channelNum, 0x3FF));
+ MCPWMx->MCDEADTIME |= MCPWM_DT(channelNum, channelSetup->channelDeadtimeValue);
+ } else {
+ MCPWMx->MCCON_CLR = MCPWM_CON_DTE(channelNum);
+ }
+
+ if (channelSetup->channelUpdateEnable /* == ENABLE */){
+ MCPWMx->MCCON_CLR = MCPWM_CON_DISUP(channelNum);
+ } else {
+ MCPWMx->MCCON_SET = MCPWM_CON_DISUP(channelNum);
+ }
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Write to MCPWM shadow registers - Update the value for period
+ * and pulse width in MCPWM peripheral.
+ * @param[in] MCPWMx Motor Control PWM peripheral selected
+ * Should be: LPC_MCPWM
+ * @param[in] channelNum Channel Number, should be: 0..2.
+ * @param[in] channelSetup Pointer to a MCPWM_CHANNEL_CFG_Type structure
+* that contains the configuration information for the
+* specified MCPWM channel.
+ * @return None
+ **********************************************************************/
+void MCPWM_WriteToShadow(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
+ MCPWM_CHANNEL_CFG_Type *channelSetup)
+{
+ if (channelNum == 0){
+ MCPWMx->MCPER0 = channelSetup->channelPeriodValue;
+ MCPWMx->MCPW0 = channelSetup->channelPulsewidthValue;
+ } else if (channelNum == 1) {
+ MCPWMx->MCPER1 = channelSetup->channelPeriodValue;
+ MCPWMx->MCPW1 = channelSetup->channelPulsewidthValue;
+ } else if (channelNum == 2) {
+ MCPWMx->MCPER2 = channelSetup->channelPeriodValue;
+ MCPWMx->MCPW2 = channelSetup->channelPulsewidthValue;
+ }
+}
+
+
+
+/*********************************************************************//**
+ * @brief Configures capture function in MCPWM peripheral
+ * @param[in] MCPWMx Motor Control PWM peripheral selected
+ * Should be: LPC_MCPWM
+ * @param[in] channelNum MCI (Motor Control Input pin) number
+ * Should be: 0..2
+ * @param[in] captureConfig Pointer to a MCPWM_CAPTURE_CFG_Type structure
+* that contains the configuration information for the
+* specified MCPWM capture.
+ * @return
+ **********************************************************************/
+void MCPWM_ConfigCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
+ MCPWM_CAPTURE_CFG_Type *captureConfig)
+{
+ if (channelNum <= 2) {
+
+ if (captureConfig->captureFalling /* == ENABLE */) {
+ MCPWMx->MCCAPCON_SET = MCPWM_CAPCON_CAPMCI_FE(captureConfig->captureChannel, channelNum);
+ } else {
+ MCPWMx->MCCAPCON_CLR = MCPWM_CAPCON_CAPMCI_FE(captureConfig->captureChannel, channelNum);
+ }
+
+ if (captureConfig->captureRising /* == ENABLE */) {
+ MCPWMx->MCCAPCON_SET = MCPWM_CAPCON_CAPMCI_RE(captureConfig->captureChannel, channelNum);
+ } else {
+ MCPWMx->MCCAPCON_CLR = MCPWM_CAPCON_CAPMCI_RE(captureConfig->captureChannel, channelNum);
+ }
+
+ if (captureConfig->timerReset /* == ENABLE */){
+ MCPWMx->MCCAPCON_SET = MCPWM_CAPCON_RT(captureConfig->captureChannel);
+ } else {
+ MCPWMx->MCCAPCON_CLR = MCPWM_CAPCON_RT(captureConfig->captureChannel);
+ }
+
+ if (captureConfig->hnfEnable /* == ENABLE */){
+ MCPWMx->MCCAPCON_SET = MCPWM_CAPCON_HNFCAP(channelNum);
+ } else {
+ MCPWMx->MCCAPCON_CLR = MCPWM_CAPCON_HNFCAP(channelNum);
+ }
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Clears current captured value in specified capture channel
+ * @param[in] MCPWMx Motor Control PWM peripheral selected
+ * Should be: LPC_MCPWM
+ * @param[in] captureChannel Capture channel number, should be: 0..2
+ * @return None
+ **********************************************************************/
+void MCPWM_ClearCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t captureChannel)
+{
+ MCPWMx->MCCAP_CLR = MCPWM_CAPCLR_CAP(captureChannel);
+}
+
+/*********************************************************************//**
+ * @brief Get current captured value in specified capture channel
+ * @param[in] MCPWMx Motor Control PWM peripheral selected,
+ * Should be: LPC_MCPWM
+ * @param[in] captureChannel Capture channel number, should be: 0..2
+ * @return None
+ **********************************************************************/
+uint32_t MCPWM_GetCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t captureChannel)
+{
+ if (captureChannel == 0){
+ return (MCPWMx->MCCR0);
+ } else if (captureChannel == 1) {
+ return (MCPWMx->MCCR1);
+ } else if (captureChannel == 2) {
+ return (MCPWMx->MCCR2);
+ }
+ return (0);
+}
+
+
+/*********************************************************************//**
+ * @brief Configures Count control in MCPWM peripheral
+ * @param[in] MCPWMx Motor Control PWM peripheral selected
+ * Should be: LPC_MCPWM
+ * @param[in] channelNum Channel number, should be: 0..2
+ * @param[in] countMode Count mode, should be:
+ * - ENABLE: Enables count mode.
+ * - DISABLE: Disable count mode, the channel is in timer mode.
+ * @param[in] countConfig Pointer to a MCPWM_COUNT_CFG_Type structure
+* that contains the configuration information for the
+* specified MCPWM count control.
+ * @return None
+ **********************************************************************/
+void MCPWM_CountConfig(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
+ uint32_t countMode, MCPWM_COUNT_CFG_Type *countConfig)
+{
+ if (channelNum <= 2) {
+ if (countMode /* == ENABLE */){
+ MCPWMx->MCCNTCON_SET = MCPWM_CNTCON_CNTR(channelNum);
+ if (countConfig->countFalling /* == ENABLE */) {
+ MCPWMx->MCCNTCON_SET = MCPWM_CNTCON_TCMCI_FE(countConfig->counterChannel,channelNum);
+ } else {
+ MCPWMx->MCCNTCON_CLR = MCPWM_CNTCON_TCMCI_FE(countConfig->counterChannel,channelNum);
+ }
+ if (countConfig->countRising /* == ENABLE */) {
+ MCPWMx->MCCNTCON_SET = MCPWM_CNTCON_TCMCI_RE(countConfig->counterChannel,channelNum);
+ } else {
+ MCPWMx->MCCNTCON_CLR = MCPWM_CNTCON_TCMCI_RE(countConfig->counterChannel,channelNum);
+ }
+ } else {
+ MCPWMx->MCCNTCON_CLR = MCPWM_CNTCON_CNTR(channelNum);
+ }
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Start MCPWM activity for each MCPWM channel
+ * @param[in] MCPWMx Motor Control PWM peripheral selected
+ * Should be: LPC_MCPWM
+ * @param[in] channel0 State of this command on channel 0:
+ * - ENABLE: 'Start' command will effect on channel 0
+ * - DISABLE: 'Start' command will not effect on channel 0
+ * @param[in] channel1 State of this command on channel 1:
+ * - ENABLE: 'Start' command will effect on channel 1
+ * - DISABLE: 'Start' command will not effect on channel 1
+ * @param[in] channel2 State of this command on channel 2:
+ * - ENABLE: 'Start' command will effect on channel 2
+ * - DISABLE: 'Start' command will not effect on channel 2
+ * @return None
+ **********************************************************************/
+void MCPWM_Start(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channel0,
+ uint32_t channel1, uint32_t channel2)
+{
+ uint32_t regVal = 0;
+ regVal = (channel0 ? MCPWM_CON_RUN(0) : 0) | (channel1 ? MCPWM_CON_RUN(1) : 0) \
+ | (channel2 ? MCPWM_CON_RUN(2) : 0);
+ MCPWMx->MCCON_SET = regVal;
+}
+
+
+/*********************************************************************//**
+ * @brief Stop MCPWM activity for each MCPWM channel
+ * @param[in] MCPWMx Motor Control PWM peripheral selected
+ * Should be: LPC_MCPWM
+ * @param[in] channel0 State of this command on channel 0:
+ * - ENABLE: 'Stop' command will effect on channel 0
+ * - DISABLE: 'Stop' command will not effect on channel 0
+ * @param[in] channel1 State of this command on channel 1:
+ * - ENABLE: 'Stop' command will effect on channel 1
+ * - DISABLE: 'Stop' command will not effect on channel 1
+ * @param[in] channel2 State of this command on channel 2:
+ * - ENABLE: 'Stop' command will effect on channel 2
+ * - DISABLE: 'Stop' command will not effect on channel 2
+ * @return None
+ **********************************************************************/
+void MCPWM_Stop(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channel0,
+ uint32_t channel1, uint32_t channel2)
+{
+ uint32_t regVal = 0;
+ regVal = (channel0 ? MCPWM_CON_RUN(0) : 0) | (channel1 ? MCPWM_CON_RUN(1) : 0) \
+ | (channel2 ? MCPWM_CON_RUN(2) : 0);
+ MCPWMx->MCCON_CLR = regVal;
+}
+
+
+/*********************************************************************//**
+ * @brief Enables/Disables 3-phase AC motor mode on MCPWM peripheral
+ * @param[in] MCPWMx Motor Control PWM peripheral selected
+ * Should be: LPC_MCPWM
+ * @param[in] acMode State of this command, should be:
+ * - ENABLE.
+ * - DISABLE.
+ * @return None
+ **********************************************************************/
+void MCPWM_ACMode(LPC_MCPWM_TypeDef *MCPWMx, uint32_t acMode)
+{
+ if (acMode){
+ MCPWMx->MCCON_SET = MCPWM_CON_ACMODE;
+ } else {
+ MCPWMx->MCCON_CLR = MCPWM_CON_ACMODE;
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Enables/Disables 3-phase DC motor mode on MCPWM peripheral
+ * @param[in] MCPWMx Motor Control PWM peripheral selected
+ * Should be: LPC_MCPWM
+ * @param[in] dcMode State of this command, should be:
+ * - ENABLE.
+ * - DISABLE.
+ * @param[in] outputInvered Polarity of the MCOB outputs for all 3 channels,
+ * should be:
+ * - ENABLE: The MCOB outputs have opposite polarity
+ * from the MCOA outputs.
+ * - DISABLE: The MCOB outputs have the same basic
+ * polarity as the MCOA outputs.
+ * @param[in] outputPattern A value contains bits that enables/disables the specified
+ * output pins route to the internal MCOA0 signal, should be:
+ - MCPWM_PATENT_A0: MCOA0 tracks internal MCOA0
+ - MCPWM_PATENT_B0: MCOB0 tracks internal MCOA0
+ - MCPWM_PATENT_A1: MCOA1 tracks internal MCOA0
+ - MCPWM_PATENT_B1: MCOB1 tracks internal MCOA0
+ - MCPWM_PATENT_A2: MCOA2 tracks internal MCOA0
+ - MCPWM_PATENT_B2: MCOB2 tracks internal MCOA0
+ * @return None
+ *
+ * Note: all these outputPatent values above can be ORed together for using as input parameter.
+ **********************************************************************/
+void MCPWM_DCMode(LPC_MCPWM_TypeDef *MCPWMx, uint32_t dcMode,
+ uint32_t outputInvered, uint32_t outputPattern)
+{
+ if (dcMode){
+ MCPWMx->MCCON_SET = MCPWM_CON_DCMODE;
+ } else {
+ MCPWMx->MCCON_CLR = MCPWM_CON_DCMODE;
+ }
+
+ if (outputInvered) {
+ MCPWMx->MCCON_SET = MCPWM_CON_INVBDC;
+ } else {
+ MCPWMx->MCCON_CLR = MCPWM_CON_INVBDC;
+ }
+
+ MCPWMx->MCCCP = outputPattern;
+}
+
+
+/*********************************************************************//**
+ * @brief Configures the specified interrupt in MCPWM peripheral
+ * @param[in] MCPWMx Motor Control PWM peripheral selected
+ * Should be: LPC_MCPWM
+ * @param[in] ulIntType Interrupt type, should be:
+ * - MCPWM_INTFLAG_LIM0: Limit interrupt for channel (0)
+ * - MCPWM_INTFLAG_MAT0: Match interrupt for channel (0)
+ * - MCPWM_INTFLAG_CAP0: Capture interrupt for channel (0)
+ * - MCPWM_INTFLAG_LIM1: Limit interrupt for channel (1)
+ * - MCPWM_INTFLAG_MAT1: Match interrupt for channel (1)
+ * - MCPWM_INTFLAG_CAP1: Capture interrupt for channel (1)
+ * - MCPWM_INTFLAG_LIM2: Limit interrupt for channel (2)
+ * - MCPWM_INTFLAG_MAT2: Match interrupt for channel (2)
+ * - MCPWM_INTFLAG_CAP2: Capture interrupt for channel (2)
+ * - MCPWM_INTFLAG_ABORT: Fast abort interrupt
+ * @param[in] NewState New State of this command, should be:
+ * - ENABLE.
+ * - DISABLE.
+ * @return None
+ *
+ * Note: all these ulIntType values above can be ORed together for using as input parameter.
+ **********************************************************************/
+void MCPWM_IntConfig(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType, FunctionalState NewState)
+{
+ if (NewState) {
+ MCPWMx->MCINTEN_SET = ulIntType;
+ } else {
+ MCPWMx->MCINTEN_CLR = ulIntType;
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Sets/Forces the specified interrupt for MCPWM peripheral
+ * @param[in] MCPWMx Motor Control PWM peripheral selected
+ * Should be LPC_MCPWM
+ * @param[in] ulIntType Interrupt type, should be:
+ * - MCPWM_INTFLAG_LIM0: Limit interrupt for channel (0)
+ * - MCPWM_INTFLAG_MAT0: Match interrupt for channel (0)
+ * - MCPWM_INTFLAG_CAP0: Capture interrupt for channel (0)
+ * - MCPWM_INTFLAG_LIM1: Limit interrupt for channel (1)
+ * - MCPWM_INTFLAG_MAT1: Match interrupt for channel (1)
+ * - MCPWM_INTFLAG_CAP1: Capture interrupt for channel (1)
+ * - MCPWM_INTFLAG_LIM2: Limit interrupt for channel (2)
+ * - MCPWM_INTFLAG_MAT2: Match interrupt for channel (2)
+ * - MCPWM_INTFLAG_CAP2: Capture interrupt for channel (2)
+ * - MCPWM_INTFLAG_ABORT: Fast abort interrupt
+ * @return None
+ * Note: all these ulIntType values above can be ORed together for using as input parameter.
+ **********************************************************************/
+void MCPWM_IntSet(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType)
+{
+ MCPWMx->MCINTFLAG_SET = ulIntType;
+}
+
+
+/*********************************************************************//**
+ * @brief Clear the specified interrupt pending for MCPWM peripheral
+ * @param[in] MCPWMx Motor Control PWM peripheral selected,
+ * should be: LPC_MCPWM
+ * @param[in] ulIntType Interrupt type, should be:
+ * - MCPWM_INTFLAG_LIM0: Limit interrupt for channel (0)
+ * - MCPWM_INTFLAG_MAT0: Match interrupt for channel (0)
+ * - MCPWM_INTFLAG_CAP0: Capture interrupt for channel (0)
+ * - MCPWM_INTFLAG_LIM1: Limit interrupt for channel (1)
+ * - MCPWM_INTFLAG_MAT1: Match interrupt for channel (1)
+ * - MCPWM_INTFLAG_CAP1: Capture interrupt for channel (1)
+ * - MCPWM_INTFLAG_LIM2: Limit interrupt for channel (2)
+ * - MCPWM_INTFLAG_MAT2: Match interrupt for channel (2)
+ * - MCPWM_INTFLAG_CAP2: Capture interrupt for channel (2)
+ * - MCPWM_INTFLAG_ABORT: Fast abort interrupt
+ * @return None
+ * Note: all these ulIntType values above can be ORed together for using as input parameter.
+ **********************************************************************/
+void MCPWM_IntClear(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType)
+{
+ MCPWMx->MCINTFLAG_CLR = ulIntType;
+}
+
+
+/*********************************************************************//**
+ * @brief Check whether if the specified interrupt in MCPWM is set or not
+ * @param[in] MCPWMx Motor Control PWM peripheral selected,
+ * should be: LPC_MCPWM
+ * @param[in] ulIntType Interrupt type, should be:
+ * - MCPWM_INTFLAG_LIM0: Limit interrupt for channel (0)
+ * - MCPWM_INTFLAG_MAT0: Match interrupt for channel (0)
+ * - MCPWM_INTFLAG_CAP0: Capture interrupt for channel (0)
+ * - MCPWM_INTFLAG_LIM1: Limit interrupt for channel (1)
+ * - MCPWM_INTFLAG_MAT1: Match interrupt for channel (1)
+ * - MCPWM_INTFLAG_CAP1: Capture interrupt for channel (1)
+ * - MCPWM_INTFLAG_LIM2: Limit interrupt for channel (2)
+ * - MCPWM_INTFLAG_MAT2: Match interrupt for channel (2)
+ * - MCPWM_INTFLAG_CAP2: Capture interrupt for channel (2)
+ * - MCPWM_INTFLAG_ABORT: Fast abort interrupt
+ * @return None
+ **********************************************************************/
+FlagStatus MCPWM_GetIntStatus(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType)
+{
+ return ((MCPWMx->MCINTFLAG & ulIntType) ? SET : RESET);
+}
+
+/**
+ * @}
+ */
+
+#endif /* _MCPWM */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/src/shared/cmsis/Drivers/source/lpc17xx_nvic.c b/src/shared/cmsis/Drivers/source/lpc17xx_nvic.c
@@ -0,0 +1,148 @@
+/**********************************************************************
+* $Id$ lpc17xx_nvic.c 2010-05-21
+*//**
+* @file lpc17xx_nvic.c
+* @brief Contains all expansion functions support for
+* NVIC firmware library on LPC17xx. The main
+* NVIC functions are defined in core_cm3.h
+* @version 2.0
+* @date 21. May. 2010
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2010, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @addtogroup NVIC
+ * @{
+ */
+
+/* Includes ------------------------------------------------------------------- */
+#include "lpc17xx_nvic.h"
+
+
+/* Private Macros ------------------------------------------------------------- */
+/** @addtogroup NVIC_Private_Macros
+ * @{
+ */
+
+/* Vector table offset bit mask */
+#define NVIC_VTOR_MASK 0x3FFFFF80
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @addtogroup NVIC_Public_Functions
+ * @{
+ */
+
+
+/*****************************************************************************//**
+ * @brief De-initializes the NVIC peripheral registers to their default
+ * reset values.
+ * @param None
+ * @return None
+ *
+ * These following NVIC peripheral registers will be de-initialized:
+ * - Disable Interrupt (32 IRQ interrupt sources that matched with LPC17xx)
+ * - Clear all Pending Interrupts (32 IRQ interrupt source that matched with LPC17xx)
+ * - Clear all Interrupt Priorities (32 IRQ interrupt source that matched with LPC17xx)
+ *******************************************************************************/
+void NVIC_DeInit(void)
+{
+ uint8_t tmp;
+
+ /* Disable all interrupts */
+ NVIC->ICER[0] = 0xFFFFFFFF;
+ NVIC->ICER[1] = 0x00000001;
+ /* Clear all pending interrupts */
+ NVIC->ICPR[0] = 0xFFFFFFFF;
+ NVIC->ICPR[1] = 0x00000001;
+
+ /* Clear all interrupt priority */
+ for (tmp = 0; tmp < 32; tmp++) {
+ NVIC->IP[tmp] = 0x00;
+ }
+}
+
+/*****************************************************************************//**
+ * @brief De-initializes the SCB peripheral registers to their default
+ * reset values.
+ * @param none
+ * @return none
+ *
+ * These following SCB NVIC peripheral registers will be de-initialized:
+ * - Interrupt Control State register
+ * - Interrupt Vector Table Offset register
+ * - Application Interrupt/Reset Control register
+ * - System Control register
+ * - Configuration Control register
+ * - System Handlers Priority Registers
+ * - System Handler Control and State Register
+ * - Configurable Fault Status Register
+ * - Hard Fault Status Register
+ * - Debug Fault Status Register
+ *******************************************************************************/
+void NVIC_SCBDeInit(void)
+{
+ uint8_t tmp;
+
+ SCB->ICSR = 0x0A000000;
+ SCB->VTOR = 0x00000000;
+ SCB->AIRCR = 0x05FA0000;
+ SCB->SCR = 0x00000000;
+ SCB->CCR = 0x00000000;
+
+ for (tmp = 0; tmp < 12; tmp++) {
+ SCB->SHP[tmp] = 0x00;
+ }
+
+ SCB->SHCSR = 0x00000000;
+ SCB->CFSR = 0xFFFFFFFF;
+ SCB->HFSR = 0xFFFFFFFF;
+ SCB->DFSR = 0xFFFFFFFF;
+}
+
+
+/*****************************************************************************//**
+ * @brief Set Vector Table Offset value
+ * @param offset Offset value
+ * @return None
+ *******************************************************************************/
+void NVIC_SetVTOR(uint32_t offset)
+{
+// SCB->VTOR = (offset & NVIC_VTOR_MASK);
+ SCB->VTOR = offset;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/src/shared/cmsis/Drivers/source/lpc17xx_pinsel.c b/src/shared/cmsis/Drivers/source/lpc17xx_pinsel.c
@@ -0,0 +1,318 @@
+/**********************************************************************
+* $Id$ lpc17xx_pinsel.c 2010-05-21
+*//**
+* @file lpc17xx_pinsel.c
+* @brief Contains all functions support for Pin connect block firmware
+* library on LPC17xx
+* @version 2.0
+* @date 21. May. 2010
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2010, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @addtogroup PINSEL
+ * @{
+ */
+
+/* Includes ------------------------------------------------------------------- */
+#include "lpc17xx_pinsel.h"
+
+/* Public Functions ----------------------------------------------------------- */
+
+static void set_PinFunc ( uint8_t portnum, uint8_t pinnum, uint8_t funcnum);
+static void set_ResistorMode ( uint8_t portnum, uint8_t pinnum, uint8_t modenum);
+static void set_OpenDrainMode( uint8_t portnum, uint8_t pinnum, uint8_t modenum);
+
+/*********************************************************************//**
+ * @brief Setup the pin selection function
+ * @param[in] portnum PORT number,
+ * should be one of the following:
+ * - PINSEL_PORT_0 : Port 0
+ * - PINSEL_PORT_1 : Port 1
+ * - PINSEL_PORT_2 : Port 2
+ * - PINSEL_PORT_3 : Port 3
+ *
+ * @param[in] pinnum Pin number,
+ * should be one of the following:
+ - PINSEL_PIN_0 : Pin 0
+ - PINSEL_PIN_1 : Pin 1
+ - PINSEL_PIN_2 : Pin 2
+ - PINSEL_PIN_3 : Pin 3
+ - PINSEL_PIN_4 : Pin 4
+ - PINSEL_PIN_5 : Pin 5
+ - PINSEL_PIN_6 : Pin 6
+ - PINSEL_PIN_7 : Pin 7
+ - PINSEL_PIN_8 : Pin 8
+ - PINSEL_PIN_9 : Pin 9
+ - PINSEL_PIN_10 : Pin 10
+ - PINSEL_PIN_11 : Pin 11
+ - PINSEL_PIN_12 : Pin 12
+ - PINSEL_PIN_13 : Pin 13
+ - PINSEL_PIN_14 : Pin 14
+ - PINSEL_PIN_15 : Pin 15
+ - PINSEL_PIN_16 : Pin 16
+ - PINSEL_PIN_17 : Pin 17
+ - PINSEL_PIN_18 : Pin 18
+ - PINSEL_PIN_19 : Pin 19
+ - PINSEL_PIN_20 : Pin 20
+ - PINSEL_PIN_21 : Pin 21
+ - PINSEL_PIN_22 : Pin 22
+ - PINSEL_PIN_23 : Pin 23
+ - PINSEL_PIN_24 : Pin 24
+ - PINSEL_PIN_25 : Pin 25
+ - PINSEL_PIN_26 : Pin 26
+ - PINSEL_PIN_27 : Pin 27
+ - PINSEL_PIN_28 : Pin 28
+ - PINSEL_PIN_29 : Pin 29
+ - PINSEL_PIN_30 : Pin 30
+ - PINSEL_PIN_31 : Pin 31
+
+ * @param[in] funcnum Function number,
+ * should be one of the following:
+ * - PINSEL_FUNC_0 : default function
+ * - PINSEL_FUNC_1 : first alternate function
+ * - PINSEL_FUNC_2 : second alternate function
+ * - PINSEL_FUNC_3 : third alternate function
+ *
+ * @return None
+ **********************************************************************/
+static void set_PinFunc ( uint8_t portnum, uint8_t pinnum, uint8_t funcnum)
+{
+ uint32_t pinnum_t = pinnum;
+ uint32_t pinselreg_idx = 2 * portnum;
+ uint32_t *pPinCon = (uint32_t *)&LPC_PINCON->PINSEL0;
+
+ if (pinnum_t >= 16) {
+ pinnum_t -= 16;
+ pinselreg_idx++;
+ }
+ *(uint32_t *)(pPinCon + pinselreg_idx) &= ~(0x03UL << (pinnum_t * 2));
+ *(uint32_t *)(pPinCon + pinselreg_idx) |= ((uint32_t)funcnum) << (pinnum_t * 2);
+}
+
+/*********************************************************************//**
+ * @brief Setup resistor mode for each pin
+ * @param[in] portnum PORT number,
+ * should be one of the following:
+ * - PINSEL_PORT_0 : Port 0
+ * - PINSEL_PORT_1 : Port 1
+ * - PINSEL_PORT_2 : Port 2
+ * - PINSEL_PORT_3 : Port 3
+ * @param[in] pinnum Pin number,
+ * should be one of the following:
+ - PINSEL_PIN_0 : Pin 0
+ - PINSEL_PIN_1 : Pin 1
+ - PINSEL_PIN_2 : Pin 2
+ - PINSEL_PIN_3 : Pin 3
+ - PINSEL_PIN_4 : Pin 4
+ - PINSEL_PIN_5 : Pin 5
+ - PINSEL_PIN_6 : Pin 6
+ - PINSEL_PIN_7 : Pin 7
+ - PINSEL_PIN_8 : Pin 8
+ - PINSEL_PIN_9 : Pin 9
+ - PINSEL_PIN_10 : Pin 10
+ - PINSEL_PIN_11 : Pin 11
+ - PINSEL_PIN_12 : Pin 12
+ - PINSEL_PIN_13 : Pin 13
+ - PINSEL_PIN_14 : Pin 14
+ - PINSEL_PIN_15 : Pin 15
+ - PINSEL_PIN_16 : Pin 16
+ - PINSEL_PIN_17 : Pin 17
+ - PINSEL_PIN_18 : Pin 18
+ - PINSEL_PIN_19 : Pin 19
+ - PINSEL_PIN_20 : Pin 20
+ - PINSEL_PIN_21 : Pin 21
+ - PINSEL_PIN_22 : Pin 22
+ - PINSEL_PIN_23 : Pin 23
+ - PINSEL_PIN_24 : Pin 24
+ - PINSEL_PIN_25 : Pin 25
+ - PINSEL_PIN_26 : Pin 26
+ - PINSEL_PIN_27 : Pin 27
+ - PINSEL_PIN_28 : Pin 28
+ - PINSEL_PIN_29 : Pin 29
+ - PINSEL_PIN_30 : Pin 30
+ - PINSEL_PIN_31 : Pin 31
+
+ * @param[in] modenum: Mode number,
+ * should be one of the following:
+ - PINSEL_PINMODE_PULLUP : Internal pull-up resistor
+ - PINSEL_PINMODE_TRISTATE : Tri-state
+ - PINSEL_PINMODE_PULLDOWN : Internal pull-down resistor
+
+ * @return None
+ **********************************************************************/
+void set_ResistorMode ( uint8_t portnum, uint8_t pinnum, uint8_t modenum)
+{
+ uint32_t pinnum_t = pinnum;
+ uint32_t pinmodereg_idx = 2 * portnum;
+ uint32_t *pPinCon = (uint32_t *)&LPC_PINCON->PINMODE0;
+
+ if (pinnum_t >= 16) {
+ pinnum_t -= 16;
+ pinmodereg_idx++ ;
+ }
+
+ *(uint32_t *)(pPinCon + pinmodereg_idx) &= ~(0x03UL << (pinnum_t * 2));
+ *(uint32_t *)(pPinCon + pinmodereg_idx) |= ((uint32_t)modenum) << (pinnum_t * 2);
+}
+
+/*********************************************************************//**
+ * @brief Setup Open drain mode for each pin
+ * @param[in] portnum PORT number,
+ * should be one of the following:
+ * - PINSEL_PORT_0 : Port 0
+ * - PINSEL_PORT_1 : Port 1
+ * - PINSEL_PORT_2 : Port 2
+ * - PINSEL_PORT_3 : Port 3
+ *
+ * @param[in] pinnum Pin number,
+ * should be one of the following:
+ - PINSEL_PIN_0 : Pin 0
+ - PINSEL_PIN_1 : Pin 1
+ - PINSEL_PIN_2 : Pin 2
+ - PINSEL_PIN_3 : Pin 3
+ - PINSEL_PIN_4 : Pin 4
+ - PINSEL_PIN_5 : Pin 5
+ - PINSEL_PIN_6 : Pin 6
+ - PINSEL_PIN_7 : Pin 7
+ - PINSEL_PIN_8 : Pin 8
+ - PINSEL_PIN_9 : Pin 9
+ - PINSEL_PIN_10 : Pin 10
+ - PINSEL_PIN_11 : Pin 11
+ - PINSEL_PIN_12 : Pin 12
+ - PINSEL_PIN_13 : Pin 13
+ - PINSEL_PIN_14 : Pin 14
+ - PINSEL_PIN_15 : Pin 15
+ - PINSEL_PIN_16 : Pin 16
+ - PINSEL_PIN_17 : Pin 17
+ - PINSEL_PIN_18 : Pin 18
+ - PINSEL_PIN_19 : Pin 19
+ - PINSEL_PIN_20 : Pin 20
+ - PINSEL_PIN_21 : Pin 21
+ - PINSEL_PIN_22 : Pin 22
+ - PINSEL_PIN_23 : Pin 23
+ - PINSEL_PIN_24 : Pin 24
+ - PINSEL_PIN_25 : Pin 25
+ - PINSEL_PIN_26 : Pin 26
+ - PINSEL_PIN_27 : Pin 27
+ - PINSEL_PIN_28 : Pin 28
+ - PINSEL_PIN_29 : Pin 29
+ - PINSEL_PIN_30 : Pin 30
+ - PINSEL_PIN_31 : Pin 31
+
+ * @param[in] modenum Open drain mode number,
+ * should be one of the following:
+ * - PINSEL_PINMODE_NORMAL : Pin is in the normal (not open drain) mode
+ * - PINSEL_PINMODE_OPENDRAIN : Pin is in the open drain mode
+ *
+ * @return None
+ **********************************************************************/
+void set_OpenDrainMode( uint8_t portnum, uint8_t pinnum, uint8_t modenum)
+{
+ uint32_t *pPinCon = (uint32_t *)&LPC_PINCON->PINMODE_OD0;
+
+ if (modenum == PINSEL_PINMODE_OPENDRAIN){
+ *(uint32_t *)(pPinCon + portnum) |= (0x01UL << pinnum);
+ } else {
+ *(uint32_t *)(pPinCon + portnum) &= ~(0x01UL << pinnum);
+ }
+}
+
+/* End of Public Functions ---------------------------------------------------- */
+
+/* Public Functions ----------------------------------------------------------- */
+/** @addtogroup PINSEL_Public_Functions
+ * @{
+ */
+/*********************************************************************//**
+ * @brief Configure trace function
+ * @param[in] NewState State of the Trace function configuration,
+ * should be one of the following:
+ * - ENABLE : Enable Trace Function
+ * - DISABLE : Disable Trace Function
+ *
+ * @return None
+ **********************************************************************/
+void PINSEL_ConfigTraceFunc(FunctionalState NewState)
+{
+ if (NewState == ENABLE) {
+ LPC_PINCON->PINSEL10 |= (0x01UL << 3);
+ } else if (NewState == DISABLE) {
+ LPC_PINCON->PINSEL10 &= ~(0x01UL << 3);
+ }
+}
+
+/*********************************************************************//**
+ * @brief Setup I2C0 pins
+ * @param[in] i2cPinMode I2C pin mode,
+ * should be one of the following:
+ * - PINSEL_I2C_Normal_Mode : The standard drive mode
+ * - PINSEL_I2C_Fast_Mode : Fast Mode Plus drive mode
+ *
+ * @param[in] filterSlewRateEnable should be:
+ * - ENABLE: Enable filter and slew rate.
+ * - DISABLE: Disable filter and slew rate.
+ *
+ * @return None
+ **********************************************************************/
+void PINSEL_SetI2C0Pins(uint8_t i2cPinMode, FunctionalState filterSlewRateEnable)
+{
+ uint32_t regVal;
+
+ if (i2cPinMode == PINSEL_I2C_Fast_Mode){
+ regVal = PINSEL_I2CPADCFG_SCLDRV0 | PINSEL_I2CPADCFG_SDADRV0;
+ }
+
+ if (filterSlewRateEnable == DISABLE){
+ regVal = PINSEL_I2CPADCFG_SCLI2C0 | PINSEL_I2CPADCFG_SDAI2C0;
+ }
+ LPC_PINCON->I2CPADCFG = regVal;
+}
+
+
+/*********************************************************************//**
+ * @brief Configure Pin corresponding to specified parameters passed
+ * in the PinCfg
+ * @param[in] PinCfg Pointer to a PINSEL_CFG_Type structure
+ * that contains the configuration information for the
+ * specified pin.
+ * @return None
+ **********************************************************************/
+void PINSEL_ConfigPin(PINSEL_CFG_Type *PinCfg)
+{
+ set_PinFunc(PinCfg->Portnum, PinCfg->Pinnum, PinCfg->Funcnum);
+ set_ResistorMode(PinCfg->Portnum, PinCfg->Pinnum, PinCfg->Pinmode);
+ set_OpenDrainMode(PinCfg->Portnum, PinCfg->Pinnum, PinCfg->OpenDrain);
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/src/shared/cmsis/Drivers/source/lpc17xx_pwm.c b/src/shared/cmsis/Drivers/source/lpc17xx_pwm.c
@@ -0,0 +1,588 @@
+/**********************************************************************
+* $Id$ lpc17xx_pwm.c 2011-03-31
+*//**
+* @file lpc17xx_pwm.c
+* @brief Contains all functions support for PWM firmware library on LPC17xx
+* @version 2.1
+* @date 31. Mar. 2011
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @addtogroup PWM
+ * @{
+ */
+
+/* Includes ------------------------------------------------------------------- */
+#include "lpc17xx_pwm.h"
+#include "lpc17xx_clkpwr.h"
+
+/* If this source file built with example, the LPC17xx FW library configuration
+ * file in each example directory ("lpc17xx_libcfg.h") must be included,
+ * otherwise the default FW library configuration file must be included instead
+ */
+#ifdef __BUILD_WITH_EXAMPLE__
+#include "lpc17xx_libcfg.h"
+#else
+#include "lpc17xx_libcfg_default.h"
+#endif /* __BUILD_WITH_EXAMPLE__ */
+
+
+#ifdef _PWM
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @addtogroup PWM_Public_Functions
+ * @{
+ */
+
+
+/*********************************************************************//**
+ * @brief Check whether specified interrupt flag in PWM is set or not
+ * @param[in] PWMx: PWM peripheral, should be LPC_PWM1
+ * @param[in] IntFlag: PWM interrupt flag, should be:
+ * - PWM_INTSTAT_MR0: Interrupt flag for PWM match channel 0
+ * - PWM_INTSTAT_MR1: Interrupt flag for PWM match channel 1
+ * - PWM_INTSTAT_MR2: Interrupt flag for PWM match channel 2
+ * - PWM_INTSTAT_MR3: Interrupt flag for PWM match channel 3
+ * - PWM_INTSTAT_MR4: Interrupt flag for PWM match channel 4
+ * - PWM_INTSTAT_MR5: Interrupt flag for PWM match channel 5
+ * - PWM_INTSTAT_MR6: Interrupt flag for PWM match channel 6
+ * - PWM_INTSTAT_CAP0: Interrupt flag for capture input 0
+ * - PWM_INTSTAT_CAP1: Interrupt flag for capture input 1
+ * @return New State of PWM interrupt flag (SET or RESET)
+ **********************************************************************/
+IntStatus PWM_GetIntStatus(LPC_PWM_TypeDef *PWMx, uint32_t IntFlag)
+{
+ CHECK_PARAM(PARAM_PWMx(PWMx));
+ CHECK_PARAM(PARAM_PWM_INTSTAT(IntFlag));
+
+ return ((PWMx->IR & IntFlag) ? SET : RESET);
+}
+
+
+
+/*********************************************************************//**
+ * @brief Clear specified PWM Interrupt pending
+ * @param[in] PWMx: PWM peripheral, should be LPC_PWM1
+ * @param[in] IntFlag: PWM interrupt flag, should be:
+ * - PWM_INTSTAT_MR0: Interrupt flag for PWM match channel 0
+ * - PWM_INTSTAT_MR1: Interrupt flag for PWM match channel 1
+ * - PWM_INTSTAT_MR2: Interrupt flag for PWM match channel 2
+ * - PWM_INTSTAT_MR3: Interrupt flag for PWM match channel 3
+ * - PWM_INTSTAT_MR4: Interrupt flag for PWM match channel 4
+ * - PWM_INTSTAT_MR5: Interrupt flag for PWM match channel 5
+ * - PWM_INTSTAT_MR6: Interrupt flag for PWM match channel 6
+ * - PWM_INTSTAT_CAP0: Interrupt flag for capture input 0
+ * - PWM_INTSTAT_CAP1: Interrupt flag for capture input 1
+ * @return None
+ **********************************************************************/
+void PWM_ClearIntPending(LPC_PWM_TypeDef *PWMx, uint32_t IntFlag)
+{
+ CHECK_PARAM(PARAM_PWMx(PWMx));
+ CHECK_PARAM(PARAM_PWM_INTSTAT(IntFlag));
+ PWMx->IR = IntFlag;
+}
+
+
+
+/*****************************************************************************//**
+* @brief Fills each PWM_InitStruct member with its default value:
+* - If PWMCounterMode = PWM_MODE_TIMER:
+* + PrescaleOption = PWM_TIMER_PRESCALE_USVAL
+* + PrescaleValue = 1
+* - If PWMCounterMode = PWM_MODE_COUNTER:
+* + CountInputSelect = PWM_COUNTER_PCAP1_0
+* + CounterOption = PWM_COUNTER_RISING
+* @param[in] PWMTimerCounterMode Timer or Counter mode, should be:
+* - PWM_MODE_TIMER: Counter of PWM peripheral is in Timer mode
+* - PWM_MODE_COUNTER: Counter of PWM peripheral is in Counter mode
+* @param[in] PWM_InitStruct Pointer to structure (PWM_TIMERCFG_Type or
+* PWM_COUNTERCFG_Type) which will be initialized.
+* @return None
+* Note: PWM_InitStruct pointer will be assigned to corresponding structure
+* (PWM_TIMERCFG_Type or PWM_COUNTERCFG_Type) due to PWMTimerCounterMode.
+*******************************************************************************/
+void PWM_ConfigStructInit(uint8_t PWMTimerCounterMode, void *PWM_InitStruct)
+{
+ PWM_TIMERCFG_Type *pTimeCfg;
+ PWM_COUNTERCFG_Type *pCounterCfg;
+ CHECK_PARAM(PARAM_PWM_TC_MODE(PWMTimerCounterMode));
+
+ pTimeCfg = (PWM_TIMERCFG_Type *) PWM_InitStruct;
+ pCounterCfg = (PWM_COUNTERCFG_Type *) PWM_InitStruct;
+
+ if (PWMTimerCounterMode == PWM_MODE_TIMER )
+ {
+ pTimeCfg->PrescaleOption = PWM_TIMER_PRESCALE_USVAL;
+ pTimeCfg->PrescaleValue = 1;
+ }
+ else if (PWMTimerCounterMode == PWM_MODE_COUNTER)
+ {
+ pCounterCfg->CountInputSelect = PWM_COUNTER_PCAP1_0;
+ pCounterCfg->CounterOption = PWM_COUNTER_RISING;
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Initializes the PWMx peripheral corresponding to the specified
+ * parameters in the PWM_ConfigStruct.
+ * @param[in] PWMx PWM peripheral, should be LPC_PWM1
+ * @param[in] PWMTimerCounterMode Timer or Counter mode, should be:
+ * - PWM_MODE_TIMER: Counter of PWM peripheral is in Timer mode
+ * - PWM_MODE_COUNTER: Counter of PWM peripheral is in Counter mode
+ * @param[in] PWM_ConfigStruct Pointer to structure (PWM_TIMERCFG_Type or
+ * PWM_COUNTERCFG_Type) which will be initialized.
+ * @return None
+ * Note: PWM_ConfigStruct pointer will be assigned to corresponding structure
+ * (PWM_TIMERCFG_Type or PWM_COUNTERCFG_Type) due to PWMTimerCounterMode.
+ **********************************************************************/
+void PWM_Init(LPC_PWM_TypeDef *PWMx, uint32_t PWMTimerCounterMode, void *PWM_ConfigStruct)
+{
+ PWM_TIMERCFG_Type *pTimeCfg;
+ PWM_COUNTERCFG_Type *pCounterCfg;
+ uint64_t clkdlycnt;
+
+ CHECK_PARAM(PARAM_PWMx(PWMx));
+ CHECK_PARAM(PARAM_PWM_TC_MODE(PWMTimerCounterMode));
+
+ pTimeCfg = (PWM_TIMERCFG_Type *)PWM_ConfigStruct;
+ pCounterCfg = (PWM_COUNTERCFG_Type *)PWM_ConfigStruct;
+
+
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCPWM1, ENABLE);
+ CLKPWR_SetPCLKDiv (CLKPWR_PCLKSEL_PWM1, CLKPWR_PCLKSEL_CCLK_DIV_4);
+ // Get peripheral clock of PWM1
+ clkdlycnt = (uint64_t) CLKPWR_GetPCLK (CLKPWR_PCLKSEL_PWM1);
+
+
+ // Clear all interrupts pending
+ PWMx->IR = 0xFF & PWM_IR_BITMASK;
+ PWMx->TCR = 0x00;
+ PWMx->CTCR = 0x00;
+ PWMx->MCR = 0x00;
+ PWMx->CCR = 0x00;
+ PWMx->PCR = 0x00;
+ PWMx->LER = 0x00;
+
+ if (PWMTimerCounterMode == PWM_MODE_TIMER)
+ {
+ CHECK_PARAM(PARAM_PWM_TIMER_PRESCALE(pTimeCfg->PrescaleOption));
+
+ /* Absolute prescale value */
+ if (pTimeCfg->PrescaleOption == PWM_TIMER_PRESCALE_TICKVAL)
+ {
+ PWMx->PR = pTimeCfg->PrescaleValue - 1;
+ }
+ /* uSecond prescale value */
+ else
+ {
+ clkdlycnt = (clkdlycnt * pTimeCfg->PrescaleValue) / 1000000;
+ PWMx->PR = ((uint32_t) clkdlycnt) - 1;
+ }
+
+ }
+ else if (PWMTimerCounterMode == PWM_MODE_COUNTER)
+ {
+ CHECK_PARAM(PARAM_PWM_COUNTER_INPUTSEL(pCounterCfg->CountInputSelect));
+ CHECK_PARAM(PARAM_PWM_COUNTER_EDGE(pCounterCfg->CounterOption));
+
+ PWMx->CTCR |= (PWM_CTCR_MODE((uint32_t)pCounterCfg->CounterOption)) \
+ | (PWM_CTCR_SELECT_INPUT((uint32_t)pCounterCfg->CountInputSelect));
+ }
+}
+
+/*********************************************************************//**
+ * @brief De-initializes the PWM peripheral registers to their
+* default reset values.
+ * @param[in] PWMx PWM peripheral selected, should be LPC_PWM1
+ * @return None
+ **********************************************************************/
+void PWM_DeInit (LPC_PWM_TypeDef *PWMx)
+{
+ CHECK_PARAM(PARAM_PWMx(PWMx));
+
+ // Disable PWM control (timer, counter and PWM)
+ PWMx->TCR = 0x00;
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCPWM1, DISABLE);
+
+}
+
+
+/*********************************************************************//**
+ * @brief Enable/Disable PWM peripheral
+ * @param[in] PWMx PWM peripheral selected, should be LPC_PWM1
+ * @param[in] NewState New State of this function, should be:
+ * - ENABLE: Enable PWM peripheral
+ * - DISABLE: Disable PWM peripheral
+ * @return None
+ **********************************************************************/
+void PWM_Cmd(LPC_PWM_TypeDef *PWMx, FunctionalState NewState)
+{
+ CHECK_PARAM(PARAM_PWMx(PWMx));
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
+
+ if (NewState == ENABLE)
+ {
+ PWMx->TCR |= PWM_TCR_PWM_ENABLE;
+ }
+ else
+ {
+ PWMx->TCR &= (~PWM_TCR_PWM_ENABLE) & PWM_TCR_BITMASK;
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Enable/Disable Counter in PWM peripheral
+ * @param[in] PWMx PWM peripheral selected, should be LPC_PWM1
+ * @param[in] NewState New State of this function, should be:
+ * - ENABLE: Enable Counter in PWM peripheral
+ * - DISABLE: Disable Counter in PWM peripheral
+ * @return None
+ **********************************************************************/
+void PWM_CounterCmd(LPC_PWM_TypeDef *PWMx, FunctionalState NewState)
+{
+ CHECK_PARAM(PARAM_PWMx(PWMx));
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
+ if (NewState == ENABLE)
+ {
+ PWMx->TCR |= PWM_TCR_COUNTER_ENABLE;
+ }
+ else
+ {
+ PWMx->TCR &= (~PWM_TCR_COUNTER_ENABLE) & PWM_TCR_BITMASK;
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Reset Counter in PWM peripheral
+ * @param[in] PWMx PWM peripheral selected, should be LPC_PWM1
+ * @return None
+ **********************************************************************/
+void PWM_ResetCounter(LPC_PWM_TypeDef *PWMx)
+{
+ CHECK_PARAM(PARAM_PWMx(PWMx));
+ PWMx->TCR |= PWM_TCR_COUNTER_RESET;
+ PWMx->TCR &= (~PWM_TCR_COUNTER_RESET) & PWM_TCR_BITMASK;
+}
+
+
+/*********************************************************************//**
+ * @brief Configures match for PWM peripheral
+ * @param[in] PWMx PWM peripheral selected, should be LPC_PWM1
+ * @param[in] PWM_MatchConfigStruct Pointer to a PWM_MATCHCFG_Type structure
+* that contains the configuration information for the
+* specified PWM match function.
+ * @return None
+ **********************************************************************/
+void PWM_ConfigMatch(LPC_PWM_TypeDef *PWMx, PWM_MATCHCFG_Type *PWM_MatchConfigStruct)
+{
+ CHECK_PARAM(PARAM_PWMx(PWMx));
+ CHECK_PARAM(PARAM_PWM1_MATCH_CHANNEL(PWM_MatchConfigStruct->MatchChannel));
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(PWM_MatchConfigStruct->IntOnMatch));
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(PWM_MatchConfigStruct->ResetOnMatch));
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(PWM_MatchConfigStruct->StopOnMatch));
+
+ //interrupt on MRn
+ if (PWM_MatchConfigStruct->IntOnMatch == ENABLE)
+ {
+ PWMx->MCR |= PWM_MCR_INT_ON_MATCH(PWM_MatchConfigStruct->MatchChannel);
+ }
+ else
+ {
+ PWMx->MCR &= (~PWM_MCR_INT_ON_MATCH(PWM_MatchConfigStruct->MatchChannel)) \
+ & PWM_MCR_BITMASK;
+ }
+
+ //reset on MRn
+ if (PWM_MatchConfigStruct->ResetOnMatch == ENABLE)
+ {
+ PWMx->MCR |= PWM_MCR_RESET_ON_MATCH(PWM_MatchConfigStruct->MatchChannel);
+ }
+ else
+ {
+ PWMx->MCR &= (~PWM_MCR_RESET_ON_MATCH(PWM_MatchConfigStruct->MatchChannel)) \
+ & PWM_MCR_BITMASK;
+ }
+
+ //stop on MRn
+ if (PWM_MatchConfigStruct->StopOnMatch == ENABLE)
+ {
+ PWMx->MCR |= PWM_MCR_STOP_ON_MATCH(PWM_MatchConfigStruct->MatchChannel);
+ }
+ else
+ {
+ PWMx->MCR &= (~PWM_MCR_STOP_ON_MATCH(PWM_MatchConfigStruct->MatchChannel)) \
+ & PWM_MCR_BITMASK;
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Configures capture input for PWM peripheral
+ * @param[in] PWMx PWM peripheral selected, should be LPC_PWM1
+ * @param[in] PWM_CaptureConfigStruct Pointer to a PWM_CAPTURECFG_Type structure
+* that contains the configuration information for the
+* specified PWM capture input function.
+ * @return None
+ **********************************************************************/
+void PWM_ConfigCapture(LPC_PWM_TypeDef *PWMx, PWM_CAPTURECFG_Type *PWM_CaptureConfigStruct)
+{
+ CHECK_PARAM(PARAM_PWMx(PWMx));
+ CHECK_PARAM(PARAM_PWM1_CAPTURE_CHANNEL(PWM_CaptureConfigStruct->CaptureChannel));
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(PWM_CaptureConfigStruct->FallingEdge));
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(PWM_CaptureConfigStruct->IntOnCaption));
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(PWM_CaptureConfigStruct->RisingEdge));
+
+ if (PWM_CaptureConfigStruct->RisingEdge == ENABLE)
+ {
+ PWMx->CCR |= PWM_CCR_CAP_RISING(PWM_CaptureConfigStruct->CaptureChannel);
+ }
+ else
+ {
+ PWMx->CCR &= (~PWM_CCR_CAP_RISING(PWM_CaptureConfigStruct->CaptureChannel)) \
+ & PWM_CCR_BITMASK;
+ }
+
+ if (PWM_CaptureConfigStruct->FallingEdge == ENABLE)
+ {
+ PWMx->CCR |= PWM_CCR_CAP_FALLING(PWM_CaptureConfigStruct->CaptureChannel);
+ }
+ else
+ {
+ PWMx->CCR &= (~PWM_CCR_CAP_FALLING(PWM_CaptureConfigStruct->CaptureChannel)) \
+ & PWM_CCR_BITMASK;
+ }
+
+ if (PWM_CaptureConfigStruct->IntOnCaption == ENABLE)
+ {
+ PWMx->CCR |= PWM_CCR_INT_ON_CAP(PWM_CaptureConfigStruct->CaptureChannel);
+ }
+ else
+ {
+ PWMx->CCR &= (~PWM_CCR_INT_ON_CAP(PWM_CaptureConfigStruct->CaptureChannel)) \
+ & PWM_CCR_BITMASK;
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Read value of capture register PWM peripheral
+ * @param[in] PWMx PWM peripheral selected, should be LPC_PWM1
+ * @param[in] CaptureChannel: capture channel number, should be in
+ * range 0 to 1
+ * @return Value of capture register
+ **********************************************************************/
+uint32_t PWM_GetCaptureValue(LPC_PWM_TypeDef *PWMx, uint8_t CaptureChannel)
+{
+ CHECK_PARAM(PARAM_PWMx(PWMx));
+ CHECK_PARAM(PARAM_PWM1_CAPTURE_CHANNEL(CaptureChannel));
+
+ switch (CaptureChannel)
+ {
+ case 0:
+ return PWMx->CR0;
+
+ case 1:
+ return PWMx->CR1;
+
+ default:
+ return (0);
+ }
+}
+
+
+/********************************************************************//**
+ * @brief Update value for each PWM channel with update type option
+ * @param[in] PWMx PWM peripheral selected, should be LPC_PWM1
+ * @param[in] MatchChannel Match channel
+ * @param[in] MatchValue Match value
+ * @param[in] UpdateType Type of Update, should be:
+ * - PWM_MATCH_UPDATE_NOW: The update value will be updated for
+ * this channel immediately
+ * - PWM_MATCH_UPDATE_NEXT_RST: The update value will be updated for
+ * this channel on next reset by a PWM Match event.
+ * @return None
+ *********************************************************************/
+void PWM_MatchUpdate(LPC_PWM_TypeDef *PWMx, uint8_t MatchChannel, \
+ uint32_t MatchValue, uint8_t UpdateType)
+{
+ CHECK_PARAM(PARAM_PWMx(PWMx));
+ CHECK_PARAM(PARAM_PWM1_MATCH_CHANNEL(MatchChannel));
+ CHECK_PARAM(PARAM_PWM_MATCH_UPDATE(UpdateType));
+
+ switch (MatchChannel)
+ {
+ case 0:
+ PWMx->MR0 = MatchValue;
+ break;
+
+ case 1:
+ PWMx->MR1 = MatchValue;
+ break;
+
+ case 2:
+ PWMx->MR2 = MatchValue;
+ break;
+
+ case 3:
+ PWMx->MR3 = MatchValue;
+ break;
+
+ case 4:
+ PWMx->MR4 = MatchValue;
+ break;
+
+ case 5:
+ PWMx->MR5 = MatchValue;
+ break;
+
+ case 6:
+ PWMx->MR6 = MatchValue;
+ break;
+ }
+
+ // Write Latch register
+ PWMx->LER |= PWM_LER_EN_MATCHn_LATCH(MatchChannel);
+
+ // In case of update now
+ if (UpdateType == PWM_MATCH_UPDATE_NOW)
+ {
+ PWMx->TCR |= PWM_TCR_COUNTER_RESET;
+ PWMx->TCR &= (~PWM_TCR_COUNTER_RESET) & PWM_TCR_BITMASK;
+ }
+}
+
+/********************************************************************//**
+ * @brief Update value for multi PWM channel with update type option
+ * at the same time
+ * @param[in] PWMx PWM peripheral selected, should be LPC_PWM1
+ * @param[in] MatchStruct Structure that contents match value of 7 pwm channels
+ * @param[in] UpdateType Type of Update, should be:
+ * - PWM_MATCH_UPDATE_NOW: The update value will be updated for
+ * this channel immediately
+ * - PWM_MATCH_UPDATE_NEXT_RST: The update value will be updated for
+ * this channel on next reset by a PWM Match event.
+ * @return None
+ *********************************************************************/
+void PWM_MultiMatchUpdate(LPC_PWM_TypeDef *PWMx, PWM_Match_T *MatchStruct , uint8_t UpdateType)
+{
+ uint8_t LatchValue = 0;
+ uint8_t i;
+
+ CHECK_PARAM(PARAM_PWMx(PWMx));
+ CHECK_PARAM(PARAM_PWM_MATCH_UPDATE(UpdateType));
+
+ //Update match value
+ for(i=0;i<7;i++)
+ {
+ if(MatchStruct[i].Status == SET)
+ {
+ if(i<4)
+ *((volatile unsigned int *)(&(PWMx->MR0) + i)) = MatchStruct[i].Matchvalue;
+ else
+ {
+ *((volatile unsigned int *)(&(PWMx->MR4) + (i-4))) = MatchStruct[i].Matchvalue;
+ }
+ LatchValue |=(1<<i);
+ }
+ }
+ //set update for multi-channel at the same time
+ PWMx->LER = LatchValue;
+
+ // In case of update now
+ if (UpdateType == PWM_MATCH_UPDATE_NOW)
+ {
+ PWMx->TCR |= PWM_TCR_COUNTER_RESET;
+ PWMx->TCR &= (~PWM_TCR_COUNTER_RESET) & PWM_TCR_BITMASK;
+ }
+}
+/********************************************************************//**
+ * @brief Configure Edge mode for each PWM channel
+ * @param[in] PWMx PWM peripheral selected, should be LPC_PWM1
+ * @param[in] PWMChannel PWM channel, should be in range from 2 to 6
+ * @param[in] ModeOption PWM mode option, should be:
+ * - PWM_CHANNEL_SINGLE_EDGE: Single Edge mode
+ * - PWM_CHANNEL_DUAL_EDGE: Dual Edge mode
+ * @return None
+ * Note: PWM Channel 1 can not be selected for mode option
+ *********************************************************************/
+void PWM_ChannelConfig(LPC_PWM_TypeDef *PWMx, uint8_t PWMChannel, uint8_t ModeOption)
+{
+ CHECK_PARAM(PARAM_PWMx(PWMx));
+ CHECK_PARAM(PARAM_PWM1_EDGE_MODE_CHANNEL(PWMChannel));
+ CHECK_PARAM(PARAM_PWM_CHANNEL_EDGE(ModeOption));
+
+ // Single edge mode
+ if (ModeOption == PWM_CHANNEL_SINGLE_EDGE)
+ {
+ PWMx->PCR &= (~PWM_PCR_PWMSELn(PWMChannel)) & PWM_PCR_BITMASK;
+ }
+ // Double edge mode
+ else if (PWM_CHANNEL_DUAL_EDGE)
+ {
+ PWMx->PCR |= PWM_PCR_PWMSELn(PWMChannel);
+ }
+}
+
+
+
+/********************************************************************//**
+ * @brief Enable/Disable PWM channel output
+ * @param[in] PWMx PWM peripheral selected, should be LPC_PWM1
+ * @param[in] PWMChannel PWM channel, should be in range from 1 to 6
+ * @param[in] NewState New State of this function, should be:
+ * - ENABLE: Enable this PWM channel output
+ * - DISABLE: Disable this PWM channel output
+ * @return None
+ *********************************************************************/
+void PWM_ChannelCmd(LPC_PWM_TypeDef *PWMx, uint8_t PWMChannel, FunctionalState NewState)
+{
+ CHECK_PARAM(PARAM_PWMx(PWMx));
+ CHECK_PARAM(PARAM_PWM1_CHANNEL(PWMChannel));
+
+ if (NewState == ENABLE)
+ {
+ PWMx->PCR |= PWM_PCR_PWMENAn(PWMChannel);
+ }
+ else
+ {
+ PWMx->PCR &= (~PWM_PCR_PWMENAn(PWMChannel)) & PWM_PCR_BITMASK;
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* _PWM */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/src/shared/cmsis/Drivers/source/lpc17xx_qei.c b/src/shared/cmsis/Drivers/source/lpc17xx_qei.c
@@ -0,0 +1,514 @@
+/**********************************************************************
+* $Id$ lpc17xx_qei.c 2010-05-21
+*//**
+* @file lpc17xx_qei.c
+* @brief Contains all functions support for QEI firmware library on LPC17xx
+* @version 2.0
+* @date 21. May. 2010
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2010, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @addtogroup QEI
+ * @{
+ */
+
+/* Includes ------------------------------------------------------------------- */
+#include "lpc17xx_qei.h"
+#include "lpc17xx_clkpwr.h"
+
+
+/* If this source file built with example, the LPC17xx FW library configuration
+ * file in each example directory ("lpc17xx_libcfg.h") must be included,
+ * otherwise the default FW library configuration file must be included instead
+ */
+#ifdef __BUILD_WITH_EXAMPLE__
+#include "lpc17xx_libcfg.h"
+#else
+#include "lpc17xx_libcfg_default.h"
+#endif /* __BUILD_WITH_EXAMPLE__ */
+
+
+#ifdef _QEI
+
+/* Private Types -------------------------------------------------------------- */
+/** @defgroup QEI_Private_Types QEI Private Types
+ * @{
+ */
+
+/**
+ * @brief QEI configuration union type definition
+ */
+typedef union {
+ QEI_CFG_Type bmQEIConfig;
+ uint32_t ulQEIConfig;
+} QEI_CFGOPT_Type;
+
+/**
+ * @}
+ */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @addtogroup QEI_Public_Functions
+ * @{
+ */
+
+/*********************************************************************//**
+ * @brief Resets value for each type of QEI value, such as velocity,
+ * counter, position, etc..
+ * @param[in] QEIx QEI peripheral, should be LPC_QEI
+ * @param[in] ulResetType QEI Reset Type, should be one of the following:
+ * - QEI_RESET_POS: Reset Position Counter
+ * - QEI_RESET_POSOnIDX: Reset Position Counter on Index signal
+ * - QEI_RESET_VEL: Reset Velocity
+ * - QEI_RESET_IDX: Reset Index Counter
+ * @return None
+ **********************************************************************/
+void QEI_Reset(LPC_QEI_TypeDef *QEIx, uint32_t ulResetType)
+{
+ CHECK_PARAM(PARAM_QEIx(QEIx));
+ CHECK_PARAM(PARAM_QEI_RESET(ulResetType));
+
+ QEIx->QEICON = ulResetType;
+}
+
+/*********************************************************************//**
+ * @brief Initializes the QEI peripheral according to the specified
+* parameters in the QEI_ConfigStruct.
+ * @param[in] QEIx QEI peripheral, should be LPC_QEI
+ * @param[in] QEI_ConfigStruct Pointer to a QEI_CFG_Type structure
+* that contains the configuration information for the
+* specified QEI peripheral
+ * @return None
+ **********************************************************************/
+void QEI_Init(LPC_QEI_TypeDef *QEIx, QEI_CFG_Type *QEI_ConfigStruct)
+{
+
+ CHECK_PARAM(PARAM_QEIx(QEIx));
+ CHECK_PARAM(PARAM_QEI_DIRINV(QEI_ConfigStruct->DirectionInvert));
+ CHECK_PARAM(PARAM_QEI_SIGNALMODE(QEI_ConfigStruct->SignalMode));
+ CHECK_PARAM(PARAM_QEI_CAPMODE(QEI_ConfigStruct->CaptureMode));
+ CHECK_PARAM(PARAM_QEI_INVINX(QEI_ConfigStruct->InvertIndex));
+
+ /* Set up clock and power for QEI module */
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCQEI, ENABLE);
+
+ /* As default, peripheral clock for QEI module
+ * is set to FCCLK / 2 */
+ CLKPWR_SetPCLKDiv(CLKPWR_PCLKSEL_QEI, CLKPWR_PCLKSEL_CCLK_DIV_1);
+
+ // Reset all remaining value in QEI peripheral
+ QEIx->QEICON = QEI_CON_RESP | QEI_CON_RESV | QEI_CON_RESI;
+ QEIx->QEIMAXPOS = 0x00;
+ QEIx->CMPOS0 = 0x00;
+ QEIx->CMPOS1 = 0x00;
+ QEIx->CMPOS2 = 0x00;
+ QEIx->INXCMP = 0x00;
+ QEIx->QEILOAD = 0x00;
+ QEIx->VELCOMP = 0x00;
+ QEIx->FILTER = 0x00;
+ // Disable all Interrupt
+ QEIx->QEIIEC = QEI_IECLR_BITMASK;
+ // Clear all Interrupt pending
+ QEIx->QEICLR = QEI_INTCLR_BITMASK;
+ // Set QEI configuration value corresponding to its setting up value
+ QEIx->QEICONF = ((QEI_CFGOPT_Type *)QEI_ConfigStruct)->ulQEIConfig;
+}
+
+
+/*********************************************************************//**
+ * @brief De-initializes the QEI peripheral registers to their
+* default reset values.
+ * @param[in] QEIx QEI peripheral, should be LPC_QEI
+ * @return None
+ **********************************************************************/
+void QEI_DeInit(LPC_QEI_TypeDef *QEIx)
+{
+ CHECK_PARAM(PARAM_QEIx(QEIx));
+
+ /* Turn off clock and power for QEI module */
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCQEI, DISABLE);
+}
+
+
+/*****************************************************************************//**
+* @brief Fills each QIE_InitStruct member with its default value:
+* - DirectionInvert = QEI_DIRINV_NONE
+* - SignalMode = QEI_SIGNALMODE_QUAD
+* - CaptureMode = QEI_CAPMODE_4X
+* - InvertIndex = QEI_INVINX_NONE
+* @param[in] QIE_InitStruct Pointer to a QEI_CFG_Type structure
+* which will be initialized.
+* @return None
+*******************************************************************************/
+void QEI_ConfigStructInit(QEI_CFG_Type *QIE_InitStruct)
+{
+ QIE_InitStruct->CaptureMode = QEI_CAPMODE_4X;
+ QIE_InitStruct->DirectionInvert = QEI_DIRINV_NONE;
+ QIE_InitStruct->InvertIndex = QEI_INVINX_NONE;
+ QIE_InitStruct->SignalMode = QEI_SIGNALMODE_QUAD;
+}
+
+
+/*********************************************************************//**
+ * @brief Check whether if specified flag status is set or not
+ * @param[in] QEIx QEI peripheral, should be LPC_QEI
+ * @param[in] ulFlagType Status Flag Type, should be one of the following:
+ * - QEI_STATUS_DIR: Direction Status
+ * @return New Status of this status flag (SET or RESET)
+ **********************************************************************/
+FlagStatus QEI_GetStatus(LPC_QEI_TypeDef *QEIx, uint32_t ulFlagType)
+{
+ CHECK_PARAM(PARAM_QEIx(QEIx));
+ CHECK_PARAM(PARAM_QEI_STATUS(ulFlagType));
+ return ((QEIx->QEISTAT & ulFlagType) ? SET : RESET);
+}
+
+/*********************************************************************//**
+ * @brief Get current position value in QEI peripheral
+ * @param[in] QEIx QEI peripheral, should be LPC_QEI
+ * @return Current position value of QEI peripheral
+ **********************************************************************/
+uint32_t QEI_GetPosition(LPC_QEI_TypeDef *QEIx)
+{
+ CHECK_PARAM(PARAM_QEIx(QEIx));
+ return (QEIx->QEIPOS);
+}
+
+/*********************************************************************//**
+ * @brief Set max position value for QEI peripheral
+ * @param[in] QEIx QEI peripheral, should be LPC_QEI
+ * @param[in] ulMaxPos Max position value to set
+ * @return None
+ **********************************************************************/
+void QEI_SetMaxPosition(LPC_QEI_TypeDef *QEIx, uint32_t ulMaxPos)
+{
+ CHECK_PARAM(PARAM_QEIx(QEIx));
+ QEIx->QEIMAXPOS = ulMaxPos;
+}
+
+/*********************************************************************//**
+ * @brief Set position compare value for QEI peripheral
+ * @param[in] QEIx QEI peripheral, should be LPC_QEI
+ * @param[in] bPosCompCh Compare Position channel, should be:
+ * - QEI_COMPPOS_CH_0: QEI compare position channel 0
+ * - QEI_COMPPOS_CH_1: QEI compare position channel 1
+ * - QEI_COMPPOS_CH_2: QEI compare position channel 2
+ * @param[in] ulPosComp Compare Position value to set
+ * @return None
+ **********************************************************************/
+void QEI_SetPositionComp(LPC_QEI_TypeDef *QEIx, uint8_t bPosCompCh, uint32_t ulPosComp)
+{
+ uint32_t *tmp;
+
+ CHECK_PARAM(PARAM_QEIx(QEIx));
+ CHECK_PARAM(PARAM_QEI_COMPPOS_CH(bPosCompCh));
+ tmp = (uint32_t *) (&(QEIx->CMPOS0) + bPosCompCh * 4);
+ *tmp = ulPosComp;
+
+}
+
+/*********************************************************************//**
+ * @brief Get current index counter of QEI peripheral
+ * @param[in] QEIx QEI peripheral, should be LPC_QEI
+ * @return Current value of QEI index counter
+ **********************************************************************/
+uint32_t QEI_GetIndex(LPC_QEI_TypeDef *QEIx)
+{
+ CHECK_PARAM(PARAM_QEIx(QEIx));
+ return (QEIx->INXCNT);
+}
+
+/*********************************************************************//**
+ * @brief Set value for index compare in QEI peripheral
+ * @param[in] QEIx QEI peripheral, should be LPC_QEI
+ * @param[in] ulIndexComp Compare Index Value to set
+ * @return None
+ **********************************************************************/
+void QEI_SetIndexComp(LPC_QEI_TypeDef *QEIx, uint32_t ulIndexComp)
+{
+ CHECK_PARAM(PARAM_QEIx(QEIx));
+ QEIx->INXCMP = ulIndexComp;
+}
+
+/*********************************************************************//**
+ * @brief Set timer reload value for QEI peripheral. When the velocity timer is
+ * over-flow, the value that set for Timer Reload register will be loaded
+ * into the velocity timer for next period. The calculated velocity in RPM
+ * therefore will be affect by this value.
+ * @param[in] QEIx QEI peripheral, should be LPC_QEI
+ * @param[in] QEIReloadStruct QEI reload structure
+ * @return None
+ **********************************************************************/
+void QEI_SetTimerReload(LPC_QEI_TypeDef *QEIx, QEI_RELOADCFG_Type *QEIReloadStruct)
+{
+ uint64_t pclk;
+
+ CHECK_PARAM(PARAM_QEIx(QEIx));
+ CHECK_PARAM(PARAM_QEI_TIMERRELOAD(QEIReloadStruct->ReloadOption));
+
+ if (QEIReloadStruct->ReloadOption == QEI_TIMERRELOAD_TICKVAL) {
+ QEIx->QEILOAD = QEIReloadStruct->ReloadValue - 1;
+ } else {
+ pclk = (uint64_t)CLKPWR_GetPCLK(CLKPWR_PCLKSEL_QEI);
+ pclk = (pclk /(1000000/QEIReloadStruct->ReloadValue)) - 1;
+ QEIx->QEILOAD = (uint32_t)pclk;
+ }
+}
+
+/*********************************************************************//**
+ * @brief Get current timer counter in QEI peripheral
+ * @param[in] QEIx QEI peripheral, should be LPC_QEI
+ * @return Current timer counter in QEI peripheral
+ **********************************************************************/
+uint32_t QEI_GetTimer(LPC_QEI_TypeDef *QEIx)
+{
+ CHECK_PARAM(PARAM_QEIx(QEIx));
+ return (QEIx->QEITIME);
+}
+
+/*********************************************************************//**
+ * @brief Get current velocity pulse counter in current time period
+ * @param[in] QEIx QEI peripheral, should be LPC_QEI
+ * @return Current velocity pulse counter value
+ **********************************************************************/
+uint32_t QEI_GetVelocity(LPC_QEI_TypeDef *QEIx)
+{
+ CHECK_PARAM(PARAM_QEIx(QEIx));
+ return (QEIx->QEIVEL);
+}
+
+/*********************************************************************//**
+ * @brief Get the most recently measured velocity of the QEI. When
+ * the Velocity timer in QEI is over-flow, the current velocity
+ * value will be loaded into Velocity Capture register.
+ * @param[in] QEIx QEI peripheral, should be LPC_QEI
+ * @return The most recently measured velocity value
+ **********************************************************************/
+uint32_t QEI_GetVelocityCap(LPC_QEI_TypeDef *QEIx)
+{
+ CHECK_PARAM(PARAM_QEIx(QEIx));
+ return (QEIx->QEICAP);
+}
+
+/*********************************************************************//**
+ * @brief Set Velocity Compare value for QEI peripheral
+ * @param[in] QEIx QEI peripheral, should be LPC_QEI
+ * @param[in] ulVelComp Compare Velocity value to set
+ * @return None
+ **********************************************************************/
+void QEI_SetVelocityComp(LPC_QEI_TypeDef *QEIx, uint32_t ulVelComp)
+{
+ CHECK_PARAM(PARAM_QEIx(QEIx));
+ QEIx->VELCOMP = ulVelComp;
+}
+
+/*********************************************************************//**
+ * @brief Set value of sampling count for the digital filter in
+ * QEI peripheral
+ * @param[in] QEIx QEI peripheral, should be LPC_QEI
+ * @param[in] ulSamplingPulse Value of sampling count to set
+ * @return None
+ **********************************************************************/
+void QEI_SetDigiFilter(LPC_QEI_TypeDef *QEIx, uint32_t ulSamplingPulse)
+{
+ CHECK_PARAM(PARAM_QEIx(QEIx));
+ QEIx->FILTER = ulSamplingPulse;
+}
+
+/*********************************************************************//**
+ * @brief Check whether if specified interrupt flag status in QEI
+ * peripheral is set or not
+ * @param[in] QEIx QEI peripheral, should be LPC_QEI
+ * @param[in] ulIntType Interrupt Flag Status type, should be:
+ - QEI_INTFLAG_INX_Int: index pulse was detected interrupt
+ - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt
+ - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt
+ - QEI_INTFLAG_DIR_Int: Change of direction interrupt
+ - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt
+ - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt
+ - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the
+ current position interrupt
+ - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the
+ current position interrupt
+ - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the
+ current position interrupt
+ - QEI_INTFLAG_REV_Int: Index compare value is equal to the current
+ index count interrupt
+ - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt
+ - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt
+ - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt
+ * @return New State of specified interrupt flag status (SET or RESET)
+ **********************************************************************/
+FlagStatus QEI_GetIntStatus(LPC_QEI_TypeDef *QEIx, uint32_t ulIntType)
+{
+ CHECK_PARAM(PARAM_QEIx(QEIx));
+ CHECK_PARAM(PARAM_QEI_INTFLAG(ulIntType));
+
+ return((QEIx->QEIINTSTAT & ulIntType) ? SET : RESET);
+}
+
+/*********************************************************************//**
+ * @brief Enable/Disable specified interrupt in QEI peripheral
+ * @param[in] QEIx QEI peripheral, should be LPC_QEI
+ * @param[in] ulIntType Interrupt Flag Status type, should be:
+ * - QEI_INTFLAG_INX_Int: index pulse was detected interrupt
+ * - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt
+ * - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt
+ * - QEI_INTFLAG_DIR_Int: Change of direction interrupt
+ * - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt
+ * - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt
+ * - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the
+ * current position interrupt
+ * - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the
+ * current position interrupt
+ * - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the
+ * current position interrupt
+ * - QEI_INTFLAG_REV_Int: Index compare value is equal to the current
+ * index count interrupt
+ * - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt
+ * - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt
+ * - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt
+ * @param[in] NewState New function state, should be:
+ * - DISABLE
+ * - ENABLE
+ * @return None
+ **********************************************************************/
+void QEI_IntCmd(LPC_QEI_TypeDef *QEIx, uint32_t ulIntType, FunctionalState NewState)
+{
+ CHECK_PARAM(PARAM_QEIx(QEIx));
+ CHECK_PARAM(PARAM_QEI_INTFLAG(ulIntType));
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
+
+ if (NewState == ENABLE) {
+ QEIx->QEIIES = ulIntType;
+ } else {
+ QEIx->QEIIEC = ulIntType;
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Sets (forces) specified interrupt in QEI peripheral
+ * @param[in] QEIx QEI peripheral, should be LPC_QEI
+ * @param[in] ulIntType Interrupt Flag Status type, should be:
+ - QEI_INTFLAG_INX_Int: index pulse was detected interrupt
+ - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt
+ - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt
+ - QEI_INTFLAG_DIR_Int: Change of direction interrupt
+ - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt
+ - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt
+ - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the
+ current position interrupt
+ - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the
+ current position interrupt
+ - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the
+ current position interrupt
+ - QEI_INTFLAG_REV_Int: Index compare value is equal to the current
+ index count interrupt
+ - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt
+ - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt
+ - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt
+ * @return None
+ **********************************************************************/
+void QEI_IntSet(LPC_QEI_TypeDef *QEIx, uint32_t ulIntType)
+{
+ CHECK_PARAM(PARAM_QEIx(QEIx));
+ CHECK_PARAM(PARAM_QEI_INTFLAG(ulIntType));
+
+ QEIx->QEISET = ulIntType;
+}
+
+/*********************************************************************//**
+ * @brief Clear (force) specified interrupt (pending) in QEI peripheral
+ * @param[in] QEIx QEI peripheral, should be LPC_QEI
+ * @param[in] ulIntType Interrupt Flag Status type, should be:
+ - QEI_INTFLAG_INX_Int: index pulse was detected interrupt
+ - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt
+ - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt
+ - QEI_INTFLAG_DIR_Int: Change of direction interrupt
+ - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt
+ - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt
+ - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the
+ current position interrupt
+ - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the
+ current position interrupt
+ - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the
+ current position interrupt
+ - QEI_INTFLAG_REV_Int: Index compare value is equal to the current
+ index count interrupt
+ - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt
+ - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt
+ - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt
+ * @return None
+ **********************************************************************/
+void QEI_IntClear(LPC_QEI_TypeDef *QEIx, uint32_t ulIntType)
+{
+ CHECK_PARAM(PARAM_QEIx(QEIx));
+ CHECK_PARAM(PARAM_QEI_INTFLAG(ulIntType));
+
+ QEIx->QEICLR = ulIntType;
+}
+
+
+/*********************************************************************//**
+ * @brief Calculates the actual velocity in RPM passed via velocity
+ * capture value and Pulse Per Round (of the encoder) value
+ * parameter input.
+ * @param[in] QEIx QEI peripheral, should be LPC_QEI
+ * @param[in] ulVelCapValue Velocity capture input value that can
+ * be got from QEI_GetVelocityCap() function
+ * @param[in] ulPPR Pulse per round of encoder
+ * @return The actual value of velocity in RPM (Round per minute)
+ **********************************************************************/
+uint32_t QEI_CalculateRPM(LPC_QEI_TypeDef *QEIx, uint32_t ulVelCapValue, uint32_t ulPPR)
+{
+ uint64_t rpm, clock, Load, edges;
+
+ // Get current Clock rate for timer input
+ clock = (uint64_t)CLKPWR_GetPCLK(CLKPWR_PCLKSEL_QEI);
+ // Get Timer load value (velocity capture period)
+ Load = (uint64_t)(QEIx->QEILOAD + 1);
+ // Get Edge
+ edges = (uint64_t)((QEIx->QEICONF & QEI_CONF_CAPMODE) ? 4 : 2);
+ // Calculate RPM
+ rpm = ((clock * ulVelCapValue * 60) / (Load * ulPPR * edges));
+
+ return (uint32_t)(rpm);
+}
+
+
+/**
+ * @}
+ */
+
+#endif /* _QEI */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
+
diff --git a/src/shared/cmsis/Drivers/source/lpc17xx_rit.c b/src/shared/cmsis/Drivers/source/lpc17xx_rit.c
@@ -0,0 +1,199 @@
+/**********************************************************************
+* $Id$ lpc17xx_rit.c 2010-05-21
+*//**
+* @file lpc17xx_rit.c
+* @brief Contains all functions support for RIT firmware library on LPC17xx
+* @version 2.0
+* @date 21. May. 2010
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2010, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @addtogroup RIT
+ * @{
+ */
+
+/* Includes ------------------------------------------------------------------- */
+#include "lpc17xx_rit.h"
+#include "lpc17xx_clkpwr.h"
+
+/* If this source file built with example, the LPC17xx FW library configuration
+ * file in each example directory ("lpc17xx_libcfg.h") must be included,
+ * otherwise the default FW library configuration file must be included instead
+ */
+#ifdef __BUILD_WITH_EXAMPLE__
+#include "lpc17xx_libcfg.h"
+#else
+#include "lpc17xx_libcfg_default.h"
+#endif /* __BUILD_WITH_EXAMPLE__ */
+
+#ifdef _RIT
+
+/* Public Functions ----------------------------------------------------------- */
+/** @addtogroup RIT_Public_Functions
+ * @{
+ */
+
+/******************************************************************************//*
+ * @brief Initial for RIT
+ * - Turn on power and clock
+ * - Setup default register values
+ * @param[in] RITx is RIT peripheral selected, should be: LPC_RIT
+ * @return None
+ *******************************************************************************/
+void RIT_Init(LPC_RIT_TypeDef *RITx)
+{
+ CHECK_PARAM(PARAM_RITx(RITx));
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCRIT, ENABLE);
+ //Set up default register values
+ RITx->RICOMPVAL = 0xFFFFFFFF;
+ RITx->RIMASK = 0x00000000;
+ RITx->RICTRL = 0x0C;
+ RITx->RICOUNTER = 0x00000000;
+ // Turn on power and clock
+
+}
+/******************************************************************************//*
+ * @brief DeInitial for RIT
+ * - Turn off power and clock
+ * - ReSetup default register values
+ * @param[in] RITx is RIT peripheral selected, should be: LPC_RIT
+ * @return None
+ *******************************************************************************/
+void RIT_DeInit(LPC_RIT_TypeDef *RITx)
+{
+ CHECK_PARAM(PARAM_RITx(RITx));
+
+ // Turn off power and clock
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCRIT, DISABLE);
+ //ReSetup default register values
+ RITx->RICOMPVAL = 0xFFFFFFFF;
+ RITx->RIMASK = 0x00000000;
+ RITx->RICTRL = 0x0C;
+ RITx->RICOUNTER = 0x00000000;
+}
+
+/******************************************************************************//*
+ * @brief Set compare value, mask value and time counter value
+ * @param[in] RITx is RIT peripheral selected, should be: LPC_RIT
+ * @param[in] time_interval: timer interval value (ms)
+ * @return None
+ *******************************************************************************/
+void RIT_TimerConfig(LPC_RIT_TypeDef *RITx, uint32_t time_interval)
+{
+ uint32_t clock_rate, cmp_value;
+ CHECK_PARAM(PARAM_RITx(RITx));
+
+ // Get PCLK value of RIT
+ clock_rate = CLKPWR_GetPCLK(CLKPWR_PCLKSEL_RIT);
+
+ /* calculate compare value for RIT to generate interrupt at
+ * specified time interval
+ * COMPVAL = (RIT_PCLK * time_interval)/1000
+ * (with time_interval unit is millisecond)
+ */
+ cmp_value = (clock_rate /1000) * time_interval;
+ RITx->RICOMPVAL = cmp_value;
+
+ /* Set timer enable clear bit to clear timer to 0 whenever
+ * counter value equals the contents of RICOMPVAL
+ */
+ RITx->RICTRL |= (1<<1);
+}
+
+
+/******************************************************************************//*
+ * @brief Enable/Disable Timer
+ * @param[in] RITx is RIT peripheral selected, should be: LPC_RIT
+ * @param[in] NewState New State of this function
+ * -ENABLE: Enable Timer
+ * -DISABLE: Disable Timer
+ * @return None
+ *******************************************************************************/
+void RIT_Cmd(LPC_RIT_TypeDef *RITx, FunctionalState NewState)
+{
+ CHECK_PARAM(PARAM_RITx(RITx));
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
+
+ //Enable or Disable Timer
+ if(NewState==ENABLE)
+ {
+ RITx->RICTRL |= RIT_CTRL_TEN;
+ }
+ else
+ {
+ RITx->RICTRL &= ~RIT_CTRL_TEN;
+ }
+}
+
+/******************************************************************************//*
+ * @brief Timer Enable/Disable on debug
+ * @param[in] RITx is RIT peripheral selected, should be: LPC_RIT
+ * @param[in] NewState New State of this function
+ * -ENABLE: The timer is halted whenever a hardware break condition occurs
+ * -DISABLE: Hardware break has no effect on the timer operation
+ * @return None
+ *******************************************************************************/
+void RIT_TimerDebugCmd(LPC_RIT_TypeDef *RITx, FunctionalState NewState)
+{
+ CHECK_PARAM(PARAM_RITx(RITx));
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
+
+ //Timer Enable/Disable on break
+ if(NewState==ENABLE)
+ {
+ RITx->RICTRL |= RIT_CTRL_ENBR;
+ }
+ else
+ {
+ RITx->RICTRL &= ~RIT_CTRL_ENBR;
+ }
+}
+/******************************************************************************//*
+ * @brief Check whether interrupt flag is set or not
+ * @param[in] RITx is RIT peripheral selected, should be: LPC_RIT
+ * @return Current interrupt status, could be: SET/RESET
+ *******************************************************************************/
+IntStatus RIT_GetIntStatus(LPC_RIT_TypeDef *RITx)
+{
+ IntStatus result;
+ CHECK_PARAM(PARAM_RITx(RITx));
+ if((RITx->RICTRL&RIT_CTRL_INTEN)==1) result= SET;
+ else return RESET;
+ //clear interrupt flag
+ RITx->RICTRL |= RIT_CTRL_INTEN;
+ return result;
+}
+
+/**
+ * @}
+ */
+
+#endif /* _RIT */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/src/shared/cmsis/Drivers/source/lpc17xx_rtc.c b/src/shared/cmsis/Drivers/source/lpc17xx_rtc.c
@@ -0,0 +1,783 @@
+/**********************************************************************
+* $Id$ lpc17xx_rtc.c 2011-06-06
+*//**
+* @file lpc17xx_rtc.c
+* @brief Contains all functions support for RTC firmware library on LPC17xx
+* @version 3.1
+* @date 6. June. 2011
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @addtogroup RTC
+ * @{
+ */
+
+/* Includes ------------------------------------------------------------------- */
+#include "lpc17xx_rtc.h"
+#include "lpc17xx_clkpwr.h"
+
+
+/* If this source file built with example, the LPC17xx FW library configuration
+ * file in each example directory ("lpc17xx_libcfg.h") must be included,
+ * otherwise the default FW library configuration file must be included instead
+ */
+#ifdef __BUILD_WITH_EXAMPLE__
+#include "lpc17xx_libcfg.h"
+#else
+#include "lpc17xx_libcfg_default.h"
+#endif /* __BUILD_WITH_EXAMPLE__ */
+
+
+#ifdef _RTC
+
+/* Public Functions ----------------------------------------------------------- */
+/** @addtogroup RTC_Public_Functions
+ * @{
+ */
+
+/********************************************************************//**
+ * @brief Initializes the RTC peripheral.
+ * @param[in] RTCx RTC peripheral selected, should be LPC_RTC
+ * @return None
+ *********************************************************************/
+void RTC_Init (LPC_RTC_TypeDef *RTCx)
+{
+ CHECK_PARAM(PARAM_RTCx(RTCx));
+
+ /* Set up clock and power for RTC module */
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCRTC, ENABLE);
+
+ // Clear all register to be default
+ RTCx->ILR = 0x00;
+ RTCx->CCR = 0x00;
+ RTCx->CIIR = 0x00;
+ RTCx->AMR = 0xFF;
+ RTCx->CALIBRATION = 0x00;
+}
+
+
+/*********************************************************************//**
+ * @brief De-initializes the RTC peripheral registers to their
+* default reset values.
+ * @param[in] RTCx RTC peripheral selected, should be LPC_RTC
+ * @return None
+ **********************************************************************/
+void RTC_DeInit(LPC_RTC_TypeDef *RTCx)
+{
+ CHECK_PARAM(PARAM_RTCx(RTCx));
+
+ RTCx->CCR = 0x00;
+ // Disable power and clock for RTC module
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCRTC, DISABLE);
+}
+
+/*********************************************************************//**
+ * @brief Reset clock tick counter in RTC peripheral
+ * @param[in] RTCx RTC peripheral selected, should be LPC_RTC
+ * @return None
+ **********************************************************************/
+void RTC_ResetClockTickCounter(LPC_RTC_TypeDef *RTCx)
+{
+ CHECK_PARAM(PARAM_RTCx(RTCx));
+
+ RTCx->CCR |= RTC_CCR_CTCRST;
+ RTCx->CCR &= (~RTC_CCR_CTCRST) & RTC_CCR_BITMASK;
+}
+
+/*********************************************************************//**
+ * @brief Start/Stop RTC peripheral
+ * @param[in] RTCx RTC peripheral selected, should be LPC_RTC
+ * @param[in] NewState New State of this function, should be:
+ * - ENABLE: The time counters are enabled
+ * - DISABLE: The time counters are disabled
+ * @return None
+ **********************************************************************/
+void RTC_Cmd (LPC_RTC_TypeDef *RTCx, FunctionalState NewState)
+{
+ CHECK_PARAM(PARAM_RTCx(RTCx));
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
+
+ if (NewState == ENABLE)
+ {
+ RTCx->CCR |= RTC_CCR_CLKEN;
+ }
+ else
+ {
+ RTCx->CCR &= (~RTC_CCR_CLKEN) & RTC_CCR_BITMASK;
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Enable/Disable Counter increment interrupt for each time type
+ * in RTC peripheral
+ * @param[in] RTCx RTC peripheral selected, should be LPC_RTC
+ * @param[in] CntIncrIntType: Counter Increment Interrupt type,
+ * an increment of this type value below will generates
+ * an interrupt, should be:
+ * - RTC_TIMETYPE_SECOND
+ * - RTC_TIMETYPE_MINUTE
+ * - RTC_TIMETYPE_HOUR
+ * - RTC_TIMETYPE_DAYOFWEEK
+ * - RTC_TIMETYPE_DAYOFMONTH
+ * - RTC_TIMETYPE_DAYOFYEAR
+ * - RTC_TIMETYPE_MONTH
+ * - RTC_TIMETYPE_YEAR
+ * @param[in] NewState New State of this function, should be:
+ * - ENABLE: Counter Increment interrupt for this
+ * time type are enabled
+ * - DISABLE: Counter Increment interrupt for this
+ * time type are disabled
+ * @return None
+ **********************************************************************/
+void RTC_CntIncrIntConfig (LPC_RTC_TypeDef *RTCx, uint32_t CntIncrIntType, \
+ FunctionalState NewState)
+{
+ CHECK_PARAM(PARAM_RTCx(RTCx));
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
+ CHECK_PARAM(PARAM_RTC_TIMETYPE(CntIncrIntType));
+
+ if (NewState == ENABLE)
+ {
+ switch (CntIncrIntType)
+ {
+ case RTC_TIMETYPE_SECOND:
+ RTCx->CIIR |= RTC_CIIR_IMSEC;
+ break;
+ case RTC_TIMETYPE_MINUTE:
+ RTCx->CIIR |= RTC_CIIR_IMMIN;
+ break;
+ case RTC_TIMETYPE_HOUR:
+ RTCx->CIIR |= RTC_CIIR_IMHOUR;
+ break;
+ case RTC_TIMETYPE_DAYOFWEEK:
+ RTCx->CIIR |= RTC_CIIR_IMDOW;
+ break;
+ case RTC_TIMETYPE_DAYOFMONTH:
+ RTCx->CIIR |= RTC_CIIR_IMDOM;
+ break;
+ case RTC_TIMETYPE_DAYOFYEAR:
+ RTCx->CIIR |= RTC_CIIR_IMDOY;
+ break;
+ case RTC_TIMETYPE_MONTH:
+ RTCx->CIIR |= RTC_CIIR_IMMON;
+ break;
+ case RTC_TIMETYPE_YEAR:
+ RTCx->CIIR |= RTC_CIIR_IMYEAR;
+ break;
+ }
+ }
+ else
+ {
+ switch (CntIncrIntType)
+ {
+ case RTC_TIMETYPE_SECOND:
+ RTCx->CIIR &= (~RTC_CIIR_IMSEC) & RTC_CIIR_BITMASK;
+ break;
+ case RTC_TIMETYPE_MINUTE:
+ RTCx->CIIR &= (~RTC_CIIR_IMMIN) & RTC_CIIR_BITMASK;
+ break;
+ case RTC_TIMETYPE_HOUR:
+ RTCx->CIIR &= (~RTC_CIIR_IMHOUR) & RTC_CIIR_BITMASK;
+ break;
+ case RTC_TIMETYPE_DAYOFWEEK:
+ RTCx->CIIR &= (~RTC_CIIR_IMDOW) & RTC_CIIR_BITMASK;
+ break;
+ case RTC_TIMETYPE_DAYOFMONTH:
+ RTCx->CIIR &= (~RTC_CIIR_IMDOM) & RTC_CIIR_BITMASK;
+ break;
+ case RTC_TIMETYPE_DAYOFYEAR:
+ RTCx->CIIR &= (~RTC_CIIR_IMDOY) & RTC_CIIR_BITMASK;
+ break;
+ case RTC_TIMETYPE_MONTH:
+ RTCx->CIIR &= (~RTC_CIIR_IMMON) & RTC_CIIR_BITMASK;
+ break;
+ case RTC_TIMETYPE_YEAR:
+ RTCx->CIIR &= (~RTC_CIIR_IMYEAR) & RTC_CIIR_BITMASK;
+ break;
+ }
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Enable/Disable Alarm interrupt for each time type
+ * in RTC peripheral
+ * @param[in] RTCx RTC peripheral selected, should be LPC_RTC
+ * @param[in] AlarmTimeType: Alarm Time Interrupt type,
+ * an matching of this type value below with current time
+ * in RTC will generates an interrupt, should be:
+ * - RTC_TIMETYPE_SECOND
+ * - RTC_TIMETYPE_MINUTE
+ * - RTC_TIMETYPE_HOUR
+ * - RTC_TIMETYPE_DAYOFWEEK
+ * - RTC_TIMETYPE_DAYOFMONTH
+ * - RTC_TIMETYPE_DAYOFYEAR
+ * - RTC_TIMETYPE_MONTH
+ * - RTC_TIMETYPE_YEAR
+ * @param[in] NewState New State of this function, should be:
+ * - ENABLE: Alarm interrupt for this
+ * time type are enabled
+ * - DISABLE: Alarm interrupt for this
+ * time type are disabled
+ * @return None
+ **********************************************************************/
+void RTC_AlarmIntConfig (LPC_RTC_TypeDef *RTCx, uint32_t AlarmTimeType, \
+ FunctionalState NewState)
+{
+ CHECK_PARAM(PARAM_RTCx(RTCx));
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
+ CHECK_PARAM(PARAM_RTC_TIMETYPE(AlarmTimeType));
+
+ if (NewState == ENABLE)
+ {
+ switch (AlarmTimeType)
+ {
+ case RTC_TIMETYPE_SECOND:
+ RTCx->AMR &= (~RTC_AMR_AMRSEC) & RTC_AMR_BITMASK;
+ break;
+ case RTC_TIMETYPE_MINUTE:
+ RTCx->AMR &= (~RTC_AMR_AMRMIN) & RTC_AMR_BITMASK;
+ break;
+ case RTC_TIMETYPE_HOUR:
+ RTCx->AMR &= (~RTC_AMR_AMRHOUR) & RTC_AMR_BITMASK;
+ break;
+ case RTC_TIMETYPE_DAYOFWEEK:
+ RTCx->AMR &= (~RTC_AMR_AMRDOW) & RTC_AMR_BITMASK;
+ break;
+ case RTC_TIMETYPE_DAYOFMONTH:
+ RTCx->AMR &= (~RTC_AMR_AMRDOM) & RTC_AMR_BITMASK;
+ break;
+ case RTC_TIMETYPE_DAYOFYEAR:
+ RTCx->AMR &= (~RTC_AMR_AMRDOY) & RTC_AMR_BITMASK;
+ break;
+ case RTC_TIMETYPE_MONTH:
+ RTCx->AMR &= (~RTC_AMR_AMRMON) & RTC_AMR_BITMASK;
+ break;
+ case RTC_TIMETYPE_YEAR:
+ RTCx->AMR &= (~RTC_AMR_AMRYEAR) & RTC_AMR_BITMASK;
+ break;
+ }
+ }
+ else
+ {
+ switch (AlarmTimeType)
+ {
+ case RTC_TIMETYPE_SECOND:
+ RTCx->AMR |= (RTC_AMR_AMRSEC);
+ break;
+ case RTC_TIMETYPE_MINUTE:
+ RTCx->AMR |= (RTC_AMR_AMRMIN);
+ break;
+ case RTC_TIMETYPE_HOUR:
+ RTCx->AMR |= (RTC_AMR_AMRHOUR);
+ break;
+ case RTC_TIMETYPE_DAYOFWEEK:
+ RTCx->AMR |= (RTC_AMR_AMRDOW);
+ break;
+ case RTC_TIMETYPE_DAYOFMONTH:
+ RTCx->AMR |= (RTC_AMR_AMRDOM);
+ break;
+ case RTC_TIMETYPE_DAYOFYEAR:
+ RTCx->AMR |= (RTC_AMR_AMRDOY);
+ break;
+ case RTC_TIMETYPE_MONTH:
+ RTCx->AMR |= (RTC_AMR_AMRMON);
+ break;
+ case RTC_TIMETYPE_YEAR:
+ RTCx->AMR |= (RTC_AMR_AMRYEAR);
+ break;
+ }
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Set current time value for each time type in RTC peripheral
+ * @param[in] RTCx RTC peripheral selected, should be LPC_RTC
+ * @param[in] Timetype: Time Type, should be:
+ * - RTC_TIMETYPE_SECOND
+ * - RTC_TIMETYPE_MINUTE
+ * - RTC_TIMETYPE_HOUR
+ * - RTC_TIMETYPE_DAYOFWEEK
+ * - RTC_TIMETYPE_DAYOFMONTH
+ * - RTC_TIMETYPE_DAYOFYEAR
+ * - RTC_TIMETYPE_MONTH
+ * - RTC_TIMETYPE_YEAR
+ * @param[in] TimeValue Time value to set
+ * @return None
+ **********************************************************************/
+void RTC_SetTime (LPC_RTC_TypeDef *RTCx, uint32_t Timetype, uint32_t TimeValue)
+{
+ CHECK_PARAM(PARAM_RTCx(RTCx));
+ CHECK_PARAM(PARAM_RTC_TIMETYPE(Timetype));
+
+ switch ( Timetype)
+ {
+ case RTC_TIMETYPE_SECOND:
+ CHECK_PARAM(TimeValue <= RTC_SECOND_MAX);
+
+ RTCx->SEC = TimeValue & RTC_SEC_MASK;
+ break;
+
+ case RTC_TIMETYPE_MINUTE:
+ CHECK_PARAM(TimeValue <= RTC_MINUTE_MAX);
+
+ RTCx->MIN = TimeValue & RTC_MIN_MASK;
+ break;
+
+ case RTC_TIMETYPE_HOUR:
+ CHECK_PARAM(TimeValue <= RTC_HOUR_MAX);
+
+ RTCx->HOUR = TimeValue & RTC_HOUR_MASK;
+ break;
+
+ case RTC_TIMETYPE_DAYOFWEEK:
+ CHECK_PARAM(TimeValue <= RTC_DAYOFWEEK_MAX);
+
+ RTCx->DOW = TimeValue & RTC_DOW_MASK;
+ break;
+
+ case RTC_TIMETYPE_DAYOFMONTH:
+ CHECK_PARAM((TimeValue <= RTC_DAYOFMONTH_MAX) \
+ && (TimeValue >= RTC_DAYOFMONTH_MIN));
+
+ RTCx->DOM = TimeValue & RTC_DOM_MASK;
+ break;
+
+ case RTC_TIMETYPE_DAYOFYEAR:
+ CHECK_PARAM((TimeValue >= RTC_DAYOFYEAR_MIN) \
+ && (TimeValue <= RTC_DAYOFYEAR_MAX));
+
+ RTCx->DOY = TimeValue & RTC_DOY_MASK;
+ break;
+
+ case RTC_TIMETYPE_MONTH:
+ CHECK_PARAM((TimeValue >= RTC_MONTH_MIN) \
+ && (TimeValue <= RTC_MONTH_MAX));
+
+ RTCx->MONTH = TimeValue & RTC_MONTH_MASK;
+ break;
+
+ case RTC_TIMETYPE_YEAR:
+ CHECK_PARAM(TimeValue <= RTC_YEAR_MAX);
+
+ RTCx->YEAR = TimeValue & RTC_YEAR_MASK;
+ break;
+ }
+}
+
+/*********************************************************************//**
+ * @brief Get current time value for each type time type
+ * @param[in] RTCx RTC peripheral selected, should be LPC_RTC
+ * @param[in] Timetype: Time Type, should be:
+ * - RTC_TIMETYPE_SECOND
+ * - RTC_TIMETYPE_MINUTE
+ * - RTC_TIMETYPE_HOUR
+ * - RTC_TIMETYPE_DAYOFWEEK
+ * - RTC_TIMETYPE_DAYOFMONTH
+ * - RTC_TIMETYPE_DAYOFYEAR
+ * - RTC_TIMETYPE_MONTH
+ * - RTC_TIMETYPE_YEAR
+ * @return Value of time according to specified time type
+ **********************************************************************/
+uint32_t RTC_GetTime(LPC_RTC_TypeDef *RTCx, uint32_t Timetype)
+{
+ CHECK_PARAM(PARAM_RTCx(RTCx));
+ CHECK_PARAM(PARAM_RTC_TIMETYPE(Timetype));
+
+ switch (Timetype)
+ {
+ case RTC_TIMETYPE_SECOND:
+ return (RTCx->SEC & RTC_SEC_MASK);
+ case RTC_TIMETYPE_MINUTE:
+ return (RTCx->MIN & RTC_MIN_MASK);
+ case RTC_TIMETYPE_HOUR:
+ return (RTCx->HOUR & RTC_HOUR_MASK);
+ case RTC_TIMETYPE_DAYOFWEEK:
+ return (RTCx->DOW & RTC_DOW_MASK);
+ case RTC_TIMETYPE_DAYOFMONTH:
+ return (RTCx->DOM & RTC_DOM_MASK);
+ case RTC_TIMETYPE_DAYOFYEAR:
+ return (RTCx->DOY & RTC_DOY_MASK);
+ case RTC_TIMETYPE_MONTH:
+ return (RTCx->MONTH & RTC_MONTH_MASK);
+ case RTC_TIMETYPE_YEAR:
+ return (RTCx->YEAR & RTC_YEAR_MASK);
+ default:
+ return (0);
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Set full of time in RTC peripheral
+ * @param[in] RTCx RTC peripheral selected, should be LPC_RTC
+ * @param[in] pFullTime Pointer to a RTC_TIME_Type structure that
+ * contains time value in full.
+ * @return None
+ **********************************************************************/
+void RTC_SetFullTime (LPC_RTC_TypeDef *RTCx, RTC_TIME_Type *pFullTime)
+{
+ CHECK_PARAM(PARAM_RTCx(RTCx));
+
+ RTCx->DOM = pFullTime->DOM & RTC_DOM_MASK;
+ RTCx->DOW = pFullTime->DOW & RTC_DOW_MASK;
+ RTCx->DOY = pFullTime->DOY & RTC_DOY_MASK;
+ RTCx->HOUR = pFullTime->HOUR & RTC_HOUR_MASK;
+ RTCx->MIN = pFullTime->MIN & RTC_MIN_MASK;
+ RTCx->SEC = pFullTime->SEC & RTC_SEC_MASK;
+ RTCx->MONTH = pFullTime->MONTH & RTC_MONTH_MASK;
+ RTCx->YEAR = pFullTime->YEAR & RTC_YEAR_MASK;
+}
+
+
+/*********************************************************************//**
+ * @brief Get full of time in RTC peripheral
+ * @param[in] RTCx RTC peripheral selected, should be LPC_RTC
+ * @param[in] pFullTime Pointer to a RTC_TIME_Type structure that
+ * will be stored time in full.
+ * @return None
+ **********************************************************************/
+void RTC_GetFullTime (LPC_RTC_TypeDef *RTCx, RTC_TIME_Type *pFullTime)
+{
+ CHECK_PARAM(PARAM_RTCx(RTCx));
+
+ pFullTime->DOM = RTCx->DOM & RTC_DOM_MASK;
+ pFullTime->DOW = RTCx->DOW & RTC_DOW_MASK;
+ pFullTime->DOY = RTCx->DOY & RTC_DOY_MASK;
+ pFullTime->HOUR = RTCx->HOUR & RTC_HOUR_MASK;
+ pFullTime->MIN = RTCx->MIN & RTC_MIN_MASK;
+ pFullTime->SEC = RTCx->SEC & RTC_SEC_MASK;
+ pFullTime->MONTH = RTCx->MONTH & RTC_MONTH_MASK;
+ pFullTime->YEAR = RTCx->YEAR & RTC_YEAR_MASK;
+}
+
+
+/*********************************************************************//**
+ * @brief Set alarm time value for each time type
+ * @param[in] RTCx RTC peripheral selected, should be LPC_RTC
+ * @param[in] Timetype: Time Type, should be:
+ * - RTC_TIMETYPE_SECOND
+ * - RTC_TIMETYPE_MINUTE
+ * - RTC_TIMETYPE_HOUR
+ * - RTC_TIMETYPE_DAYOFWEEK
+ * - RTC_TIMETYPE_DAYOFMONTH
+ * - RTC_TIMETYPE_DAYOFYEAR
+ * - RTC_TIMETYPE_MONTH
+ * - RTC_TIMETYPE_YEAR
+ * @param[in] ALValue Alarm time value to set
+ * @return None
+ **********************************************************************/
+void RTC_SetAlarmTime (LPC_RTC_TypeDef *RTCx, uint32_t Timetype, uint32_t ALValue)
+{
+ CHECK_PARAM(PARAM_RTCx(RTCx));
+
+ switch (Timetype)
+ {
+ case RTC_TIMETYPE_SECOND:
+ CHECK_PARAM(ALValue <= RTC_SECOND_MAX);
+
+ RTCx->ALSEC = ALValue & RTC_SEC_MASK;
+ break;
+
+ case RTC_TIMETYPE_MINUTE:
+ CHECK_PARAM(ALValue <= RTC_MINUTE_MAX);
+
+ RTCx->ALMIN = ALValue & RTC_MIN_MASK;
+ break;
+
+ case RTC_TIMETYPE_HOUR:
+ CHECK_PARAM(ALValue <= RTC_HOUR_MAX);
+
+ RTCx->ALHOUR = ALValue & RTC_HOUR_MASK;
+ break;
+
+ case RTC_TIMETYPE_DAYOFWEEK:
+ CHECK_PARAM(ALValue <= RTC_DAYOFWEEK_MAX);
+
+ RTCx->ALDOW = ALValue & RTC_DOW_MASK;
+ break;
+
+ case RTC_TIMETYPE_DAYOFMONTH:
+ CHECK_PARAM((ALValue <= RTC_DAYOFMONTH_MAX) \
+ && (ALValue >= RTC_DAYOFMONTH_MIN));
+
+ RTCx->ALDOM = ALValue & RTC_DOM_MASK;
+ break;
+
+ case RTC_TIMETYPE_DAYOFYEAR:
+ CHECK_PARAM((ALValue >= RTC_DAYOFYEAR_MIN) \
+ && (ALValue <= RTC_DAYOFYEAR_MAX));
+
+ RTCx->ALDOY = ALValue & RTC_DOY_MASK;
+ break;
+
+ case RTC_TIMETYPE_MONTH:
+ CHECK_PARAM((ALValue >= RTC_MONTH_MIN) \
+ && (ALValue <= RTC_MONTH_MAX));
+
+ RTCx->ALMON = ALValue & RTC_MONTH_MASK;
+ break;
+
+ case RTC_TIMETYPE_YEAR:
+ CHECK_PARAM(ALValue <= RTC_YEAR_MAX);
+
+ RTCx->ALYEAR = ALValue & RTC_YEAR_MASK;
+ break;
+ }
+}
+
+
+
+/*********************************************************************//**
+ * @brief Get alarm time value for each time type
+ * @param[in] RTCx RTC peripheral selected, should be LPC_RTC
+ * @param[in] Timetype: Time Type, should be:
+ * - RTC_TIMETYPE_SECOND
+ * - RTC_TIMETYPE_MINUTE
+ * - RTC_TIMETYPE_HOUR
+ * - RTC_TIMETYPE_DAYOFWEEK
+ * - RTC_TIMETYPE_DAYOFMONTH
+ * - RTC_TIMETYPE_DAYOFYEAR
+ * - RTC_TIMETYPE_MONTH
+ * - RTC_TIMETYPE_YEAR
+ * @return Value of Alarm time according to specified time type
+ **********************************************************************/
+uint32_t RTC_GetAlarmTime (LPC_RTC_TypeDef *RTCx, uint32_t Timetype)
+{
+ switch (Timetype)
+ {
+ case RTC_TIMETYPE_SECOND:
+ return (RTCx->ALSEC & RTC_SEC_MASK);
+ case RTC_TIMETYPE_MINUTE:
+ return (RTCx->ALMIN & RTC_MIN_MASK);
+ case RTC_TIMETYPE_HOUR:
+ return (RTCx->ALHOUR & RTC_HOUR_MASK);
+ case RTC_TIMETYPE_DAYOFWEEK:
+ return (RTCx->ALDOW & RTC_DOW_MASK);
+ case RTC_TIMETYPE_DAYOFMONTH:
+ return (RTCx->ALDOM & RTC_DOM_MASK);
+ case RTC_TIMETYPE_DAYOFYEAR:
+ return (RTCx->ALDOY & RTC_DOY_MASK);
+ case RTC_TIMETYPE_MONTH:
+ return (RTCx->ALMON & RTC_MONTH_MASK);
+ case RTC_TIMETYPE_YEAR:
+ return (RTCx->ALYEAR & RTC_YEAR_MASK);
+ default:
+ return (0);
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Set full of alarm time in RTC peripheral
+ * @param[in] RTCx RTC peripheral selected, should be LPC_RTC
+ * @param[in] pFullTime Pointer to a RTC_TIME_Type structure that
+ * contains alarm time value in full.
+ * @return None
+ **********************************************************************/
+void RTC_SetFullAlarmTime (LPC_RTC_TypeDef *RTCx, RTC_TIME_Type *pFullTime)
+{
+ CHECK_PARAM(PARAM_RTCx(RTCx));
+
+ RTCx->ALDOM = pFullTime->DOM & RTC_DOM_MASK;
+ RTCx->ALDOW = pFullTime->DOW & RTC_DOW_MASK;
+ RTCx->ALDOY = pFullTime->DOY & RTC_DOY_MASK;
+ RTCx->ALHOUR = pFullTime->HOUR & RTC_HOUR_MASK;
+ RTCx->ALMIN = pFullTime->MIN & RTC_MIN_MASK;
+ RTCx->ALSEC = pFullTime->SEC & RTC_SEC_MASK;
+ RTCx->ALMON = pFullTime->MONTH & RTC_MONTH_MASK;
+ RTCx->ALYEAR = pFullTime->YEAR & RTC_YEAR_MASK;
+}
+
+
+/*********************************************************************//**
+ * @brief Get full of alarm time in RTC peripheral
+ * @param[in] RTCx RTC peripheral selected, should be LPC_RTC
+ * @param[in] pFullTime Pointer to a RTC_TIME_Type structure that
+ * will be stored alarm time in full.
+ * @return None
+ **********************************************************************/
+void RTC_GetFullAlarmTime (LPC_RTC_TypeDef *RTCx, RTC_TIME_Type *pFullTime)
+{
+ CHECK_PARAM(PARAM_RTCx(RTCx));
+
+ pFullTime->DOM = RTCx->ALDOM & RTC_DOM_MASK;
+ pFullTime->DOW = RTCx->ALDOW & RTC_DOW_MASK;
+ pFullTime->DOY = RTCx->ALDOY & RTC_DOY_MASK;
+ pFullTime->HOUR = RTCx->ALHOUR & RTC_HOUR_MASK;
+ pFullTime->MIN = RTCx->ALMIN & RTC_MIN_MASK;
+ pFullTime->SEC = RTCx->ALSEC & RTC_SEC_MASK;
+ pFullTime->MONTH = RTCx->ALMON & RTC_MONTH_MASK;
+ pFullTime->YEAR = RTCx->ALYEAR & RTC_YEAR_MASK;
+}
+
+
+/*********************************************************************//**
+ * @brief Check whether if specified Location interrupt in
+ * RTC peripheral is set or not
+ * @param[in] RTCx RTC peripheral selected, should be LPC_RTC
+ * @param[in] IntType Interrupt location type, should be:
+ * - RTC_INT_COUNTER_INCREASE: Counter Increment Interrupt
+ * block generated an interrupt.
+ * - RTC_INT_ALARM: Alarm generated an
+ * interrupt.
+ * @return New state of specified Location interrupt in RTC peripheral
+ * (SET or RESET)
+ **********************************************************************/
+IntStatus RTC_GetIntPending (LPC_RTC_TypeDef *RTCx, uint32_t IntType)
+{
+ CHECK_PARAM(PARAM_RTCx(RTCx));
+ CHECK_PARAM(PARAM_RTC_INT(IntType));
+
+ return ((RTCx->ILR & IntType) ? SET : RESET);
+}
+
+
+/*********************************************************************//**
+ * @brief Clear specified Location interrupt pending in
+ * RTC peripheral
+ * @param[in] RTCx RTC peripheral selected, should be LPC_RTC
+ * @param[in] IntType Interrupt location type, should be:
+ * - RTC_INT_COUNTER_INCREASE: Clear Counter Increment
+ * Interrupt pending.
+ * - RTC_INT_ALARM: Clear alarm interrupt pending
+ * @return None
+ **********************************************************************/
+void RTC_ClearIntPending (LPC_RTC_TypeDef *RTCx, uint32_t IntType)
+{
+ CHECK_PARAM(PARAM_RTCx(RTCx));
+ CHECK_PARAM(PARAM_RTC_INT(IntType));
+
+ RTCx->ILR |= IntType;
+}
+
+/*********************************************************************//**
+ * @brief Enable/Disable calibration counter in RTC peripheral
+ * @param[in] RTCx RTC peripheral selected, should be LPC_RTC
+ * @param[in] NewState New State of this function, should be:
+ * - ENABLE: The calibration counter is enabled and counting
+ * - DISABLE: The calibration counter is disabled and reset to zero
+ * @return None
+ **********************************************************************/
+void RTC_CalibCounterCmd(LPC_RTC_TypeDef *RTCx, FunctionalState NewState)
+{
+ CHECK_PARAM(PARAM_RTCx(RTCx));
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
+
+ if (NewState == ENABLE)
+ {
+ RTCx->CCR &= (~RTC_CCR_CCALEN) & RTC_CCR_BITMASK;
+ }
+ else
+ {
+ RTCx->CCR |= RTC_CCR_CCALEN;
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Configures Calibration in RTC peripheral
+ * @param[in] RTCx RTC peripheral selected, should be LPC_RTC
+ * @param[in] CalibValue Calibration value, should be in range from
+ * 0 to 131,072
+ * @param[in] CalibDir Calibration Direction, should be:
+ * - RTC_CALIB_DIR_FORWARD: Forward calibration
+ * - RTC_CALIB_DIR_BACKWARD: Backward calibration
+ * @return None
+ **********************************************************************/
+void RTC_CalibConfig(LPC_RTC_TypeDef *RTCx, uint32_t CalibValue, uint8_t CalibDir)
+{
+ CHECK_PARAM(PARAM_RTCx(RTCx));
+ CHECK_PARAM(PARAM_RTC_CALIB_DIR(CalibDir));
+ CHECK_PARAM(CalibValue < RTC_CALIBRATION_MAX);
+
+ RTCx->CALIBRATION = ((CalibValue) & RTC_CALIBRATION_CALVAL_MASK) \
+ | ((CalibDir == RTC_CALIB_DIR_BACKWARD) ? RTC_CALIBRATION_LIBDIR : 0);
+}
+
+
+/*********************************************************************//**
+ * @brief Write value to General purpose registers
+ * @param[in] RTCx RTC peripheral selected, should be LPC_RTC
+ * @param[in] Channel General purpose registers Channel number,
+ * should be in range from 0 to 4.
+ * @param[in] Value Value to write
+ * @return None
+ * Note: These General purpose registers can be used to store important
+ * information when the main power supply is off. The value in these
+ * registers is not affected by chip reset.
+ **********************************************************************/
+void RTC_WriteGPREG (LPC_RTC_TypeDef *RTCx, uint8_t Channel, uint32_t Value)
+{
+ uint32_t *preg;
+
+ CHECK_PARAM(PARAM_RTCx(RTCx));
+ CHECK_PARAM(PARAM_RTC_GPREG_CH(Channel));
+
+ preg = (uint32_t *)&RTCx->GPREG0;
+ preg += Channel;
+ *preg = Value;
+}
+
+
+/*********************************************************************//**
+ * @brief Read value from General purpose registers
+ * @param[in] RTCx RTC peripheral selected, should be LPC_RTC
+ * @param[in] Channel General purpose registers Channel number,
+ * should be in range from 0 to 4.
+ * @return Read Value
+ * Note: These General purpose registers can be used to store important
+ * information when the main power supply is off. The value in these
+ * registers is not affected by chip reset.
+ **********************************************************************/
+uint32_t RTC_ReadGPREG (LPC_RTC_TypeDef *RTCx, uint8_t Channel)
+{
+ uint32_t *preg;
+ uint32_t value;
+
+ CHECK_PARAM(PARAM_RTCx(RTCx));
+ CHECK_PARAM(PARAM_RTC_GPREG_CH(Channel));
+
+ preg = (uint32_t *)&RTCx->GPREG0;
+ preg += Channel;
+ value = *preg;
+ return (value);
+}
+
+/**
+ * @}
+ */
+
+#endif /* _RTC */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
+
diff --git a/src/shared/cmsis/Drivers/source/lpc17xx_spi.c b/src/shared/cmsis/Drivers/source/lpc17xx_spi.c
@@ -0,0 +1,443 @@
+/**********************************************************************
+* $Id$ lpc17xx_spi.c 2010-05-21
+*//**
+* @file lpc17xx_spi.c
+* @brief Contains all functions support for SPI firmware library on LPC17xx
+* @version 2.0
+* @date 21. May. 2010
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2010, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @addtogroup SPI
+ * @{
+ */
+
+/* Includes ------------------------------------------------------------------- */
+#include "lpc17xx_spi.h"
+#include "lpc17xx_clkpwr.h"
+
+/* If this source file built with example, the LPC17xx FW library configuration
+ * file in each example directory ("lpc17xx_libcfg.h") must be included,
+ * otherwise the default FW library configuration file must be included instead
+ */
+#ifdef __BUILD_WITH_EXAMPLE__
+#include "lpc17xx_libcfg.h"
+#else
+#include "lpc17xx_libcfg_default.h"
+#endif /* __BUILD_WITH_EXAMPLE__ */
+
+#ifdef _SPI
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @addtogroup SPI_Public_Functions
+ * @{
+ */
+
+/*********************************************************************//**
+ * @brief Setup clock rate for SPI device
+ * @param[in] SPIx SPI peripheral definition, should be LPC_SPI
+ * @param[in] target_clock : clock of SPI (Hz)
+ * @return None
+ ***********************************************************************/
+void SPI_SetClock (LPC_SPI_TypeDef *SPIx, uint32_t target_clock)
+{
+ uint32_t spi_pclk;
+ uint32_t prescale, temp;
+
+ CHECK_PARAM(PARAM_SPIx(SPIx));
+
+ if (SPIx == LPC_SPI){
+ spi_pclk = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_SPI);
+ } else {
+ return;
+ }
+
+ prescale = 8;
+ // Find closest clock to target clock
+ while (1){
+ temp = target_clock * prescale;
+ if (temp >= spi_pclk){
+ break;
+ }
+ prescale += 2;
+ if(prescale >= 254){
+ break;
+ }
+ }
+
+ // Write to register
+ SPIx->SPCCR = SPI_SPCCR_COUNTER(prescale);
+}
+
+
+/*********************************************************************//**
+ * @brief De-initializes the SPIx peripheral registers to their
+* default reset values.
+ * @param[in] SPIx SPI peripheral selected, should be LPC_SPI
+ * @return None
+ **********************************************************************/
+void SPI_DeInit(LPC_SPI_TypeDef *SPIx)
+{
+ CHECK_PARAM(PARAM_SPIx(SPIx));
+
+ if (SPIx == LPC_SPI){
+ /* Set up clock and power for SPI module */
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCSPI, DISABLE);
+ }
+}
+
+/*********************************************************************//**
+ * @brief Get data bit size per transfer
+ * @param[in] SPIx SPI peripheral selected, should be LPC_SPI
+ * @return number of bit per transfer, could be 8-16
+ **********************************************************************/
+uint8_t SPI_GetDataSize (LPC_SPI_TypeDef *SPIx)
+{
+ CHECK_PARAM(PARAM_SPIx(SPIx));
+ return ((SPIx->SPCR)>>8 & 0xF);
+}
+
+/********************************************************************//**
+ * @brief Initializes the SPIx peripheral according to the specified
+* parameters in the UART_ConfigStruct.
+ * @param[in] SPIx SPI peripheral selected, should be LPC_SPI
+ * @param[in] SPI_ConfigStruct Pointer to a SPI_CFG_Type structure
+* that contains the configuration information for the
+* specified SPI peripheral.
+ * @return None
+ *********************************************************************/
+void SPI_Init(LPC_SPI_TypeDef *SPIx, SPI_CFG_Type *SPI_ConfigStruct)
+{
+ uint32_t tmp;
+
+ CHECK_PARAM(PARAM_SPIx(SPIx));
+
+ if(SPIx == LPC_SPI){
+ /* Set up clock and power for UART module */
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCSPI, ENABLE);
+ } else {
+ return;
+ }
+
+ // Configure SPI, interrupt is disable as default
+ tmp = ((SPI_ConfigStruct->CPHA) | (SPI_ConfigStruct->CPOL) \
+ | (SPI_ConfigStruct->DataOrder) | (SPI_ConfigStruct->Databit) \
+ | (SPI_ConfigStruct->Mode) | SPI_SPCR_BIT_EN) & SPI_SPCR_BITMASK;
+ // write back to SPI control register
+ SPIx->SPCR = tmp;
+
+ // Set clock rate for SPI peripheral
+ SPI_SetClock(SPIx, SPI_ConfigStruct->ClockRate);
+
+ // If interrupt flag is set, Write '1' to Clear interrupt flag
+ if (SPIx->SPINT & SPI_SPINT_INTFLAG){
+ SPIx->SPINT = SPI_SPINT_INTFLAG;
+ }
+}
+
+
+
+/*****************************************************************************//**
+* @brief Fills each SPI_InitStruct member with its default value:
+* - CPHA = SPI_CPHA_FIRST
+* - CPOL = SPI_CPOL_HI
+* - ClockRate = 1000000
+* - DataOrder = SPI_DATA_MSB_FIRST
+* - Databit = SPI_DATABIT_8
+* - Mode = SPI_MASTER_MODE
+* @param[in] SPI_InitStruct Pointer to a SPI_CFG_Type structure
+* which will be initialized.
+* @return None
+*******************************************************************************/
+void SPI_ConfigStructInit(SPI_CFG_Type *SPI_InitStruct)
+{
+ SPI_InitStruct->CPHA = SPI_CPHA_FIRST;
+ SPI_InitStruct->CPOL = SPI_CPOL_HI;
+ SPI_InitStruct->ClockRate = 1000000;
+ SPI_InitStruct->DataOrder = SPI_DATA_MSB_FIRST;
+ SPI_InitStruct->Databit = SPI_DATABIT_8;
+ SPI_InitStruct->Mode = SPI_MASTER_MODE;
+}
+
+/*********************************************************************//**
+ * @brief Transmit a single data through SPIx peripheral
+ * @param[in] SPIx SPI peripheral selected, should be LPC_SPI
+ * @param[in] Data Data to transmit (must be 16 or 8-bit long,
+ * this depend on SPI data bit number configured)
+ * @return none
+ **********************************************************************/
+void SPI_SendData(LPC_SPI_TypeDef* SPIx, uint16_t Data)
+{
+ CHECK_PARAM(PARAM_SPIx(SPIx));
+
+ SPIx->SPDR = Data & SPI_SPDR_BITMASK;
+}
+
+
+
+/*********************************************************************//**
+ * @brief Receive a single data from SPIx peripheral
+ * @param[in] SPIx SPI peripheral selected, should be LPC_SPI
+ * @return Data received (16-bit long)
+ **********************************************************************/
+uint16_t SPI_ReceiveData(LPC_SPI_TypeDef* SPIx)
+{
+ CHECK_PARAM(PARAM_SPIx(SPIx));
+
+ return ((uint16_t) (SPIx->SPDR & SPI_SPDR_BITMASK));
+}
+
+/*********************************************************************//**
+ * @brief SPI Read write data function
+ * @param[in] SPIx Pointer to SPI peripheral, should be LPC_SPI
+ * @param[in] dataCfg Pointer to a SPI_DATA_SETUP_Type structure that
+ * contains specified information about transmit
+ * data configuration.
+ * @param[in] xfType Transfer type, should be:
+ * - SPI_TRANSFER_POLLING: Polling mode
+ * - SPI_TRANSFER_INTERRUPT: Interrupt mode
+ * @return Actual Data length has been transferred in polling mode.
+ * In interrupt mode, always return (0)
+ * Return (-1) if error.
+ * Note: This function can be used in both master and slave mode.
+ ***********************************************************************/
+int32_t SPI_ReadWrite (LPC_SPI_TypeDef *SPIx, SPI_DATA_SETUP_Type *dataCfg, \
+ SPI_TRANSFER_Type xfType)
+{
+ uint8_t *rdata8 = NULL;
+ uint8_t *wdata8 = NULL;
+ uint16_t *rdata16 = NULL;
+ uint16_t *wdata16 = NULL;
+ uint32_t stat = 0;
+ uint32_t temp;
+ uint8_t dataword;
+
+ //read for empty buffer
+ temp = SPIx->SPDR;
+ //dummy to clear status
+ temp = SPIx->SPSR;
+ dataCfg->counter = 0;
+ dataCfg->status = 0;
+
+ if(SPI_GetDataSize (SPIx) == 8)
+ dataword = 0;
+ else dataword = 1;
+ if (xfType == SPI_TRANSFER_POLLING){
+
+ if (dataword == 0){
+ rdata8 = (uint8_t *)dataCfg->rx_data;
+ wdata8 = (uint8_t *)dataCfg->tx_data;
+ } else {
+ rdata16 = (uint16_t *)dataCfg->rx_data;
+ wdata16 = (uint16_t *)dataCfg->tx_data;
+ }
+
+ while(dataCfg->counter < dataCfg->length)
+ {
+ // Write data to buffer
+ if(dataCfg->tx_data == NULL){
+ if (dataword == 0){
+ SPI_SendData(SPIx, 0xFF);
+ } else {
+ SPI_SendData(SPIx, 0xFFFF);
+ }
+ } else {
+ if (dataword == 0){
+ SPI_SendData(SPIx, *wdata8);
+ wdata8++;
+ } else {
+ SPI_SendData(SPIx, *wdata16);
+ wdata16++;
+ }
+ }
+ // Wait for transfer complete
+ while (!((stat = SPIx->SPSR) & SPI_SPSR_SPIF));
+ // Check for error
+ if (stat & (SPI_SPSR_ABRT | SPI_SPSR_MODF | SPI_SPSR_ROVR | SPI_SPSR_WCOL)){
+ // save status
+ dataCfg->status = stat | SPI_STAT_ERROR;
+ return (dataCfg->counter);
+ }
+ // Read data from SPI dat
+ temp = (uint32_t) SPI_ReceiveData(SPIx);
+
+ // Store data to destination
+ if (dataCfg->rx_data != NULL)
+ {
+ if (dataword == 0){
+ *(rdata8) = (uint8_t) temp;
+ rdata8++;
+ } else {
+ *(rdata16) = (uint16_t) temp;
+ rdata16++;
+ }
+ }
+ // Increase counter
+ if (dataword == 0){
+ dataCfg->counter++;
+ } else {
+ dataCfg->counter += 2;
+ }
+ }
+
+ // Return length of actual data transferred
+ // save status
+ dataCfg->status = stat | SPI_STAT_DONE;
+ return (dataCfg->counter);
+ }
+ // Interrupt mode
+ else {
+
+ // Check if interrupt flag is already set
+ if(SPIx->SPINT & SPI_SPINT_INTFLAG){
+ SPIx->SPINT = SPI_SPINT_INTFLAG;
+ }
+ if (dataCfg->counter < dataCfg->length){
+ // Write data to buffer
+ if(dataCfg->tx_data == NULL){
+ if (dataword == 0){
+ SPI_SendData(SPIx, 0xFF);
+ } else {
+ SPI_SendData(SPIx, 0xFFFF);
+ }
+ } else {
+ if (dataword == 0){
+ SPI_SendData(SPIx, (*(uint8_t *)dataCfg->tx_data));
+ } else {
+ SPI_SendData(SPIx, (*(uint16_t *)dataCfg->tx_data));
+ }
+ }
+ SPI_IntCmd(SPIx, ENABLE);
+ } else {
+ // Save status
+ dataCfg->status = SPI_STAT_DONE;
+ }
+ return (0);
+ }
+}
+
+
+/********************************************************************//**
+ * @brief Enable or disable SPIx interrupt.
+ * @param[in] SPIx SPI peripheral selected, should be LPC_SPI
+ * @param[in] NewState New state of specified UART interrupt type,
+ * should be:
+ * - ENALBE: Enable this SPI interrupt.
+* - DISALBE: Disable this SPI interrupt.
+ * @return None
+ *********************************************************************/
+void SPI_IntCmd(LPC_SPI_TypeDef *SPIx, FunctionalState NewState)
+{
+ CHECK_PARAM(PARAM_SPIx(SPIx));
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
+
+ if (NewState == ENABLE)
+ {
+ SPIx->SPCR |= SPI_SPCR_SPIE;
+ }
+ else
+ {
+ SPIx->SPCR &= (~SPI_SPCR_SPIE) & SPI_SPCR_BITMASK;
+ }
+}
+
+
+/********************************************************************//**
+ * @brief Checks whether the SPI interrupt flag is set or not.
+ * @param[in] SPIx SPI peripheral selected, should be LPC_SPI
+ * @return The new state of SPI Interrupt Flag (SET or RESET)
+ *********************************************************************/
+IntStatus SPI_GetIntStatus (LPC_SPI_TypeDef *SPIx)
+{
+ CHECK_PARAM(PARAM_SPIx(SPIx));
+
+ return ((SPIx->SPINT & SPI_SPINT_INTFLAG) ? SET : RESET);
+}
+
+/********************************************************************//**
+ * @brief Clear SPI interrupt flag.
+ * @param[in] SPIx SPI peripheral selected, should be LPC_SPI
+ * @return None
+ *********************************************************************/
+void SPI_ClearIntPending(LPC_SPI_TypeDef *SPIx)
+{
+ CHECK_PARAM(PARAM_SPIx(SPIx));
+
+ SPIx->SPINT = SPI_SPINT_INTFLAG;
+}
+
+/********************************************************************//**
+ * @brief Get current value of SPI Status register in SPIx peripheral.
+ * @param[in] SPIx SPI peripheral selected, should be LPC_SPI
+ * @return Current value of SPI Status register in SPI peripheral.
+ * Note: The return value of this function must be used with
+ * SPI_CheckStatus() to determine current flag status
+ * corresponding to each SPI status type. Because some flags in
+ * SPI Status register will be cleared after reading, the next reading
+ * SPI Status register could not be correct. So this function used to
+ * read SPI status register in one time only, then the return value
+ * used to check all flags.
+ *********************************************************************/
+uint32_t SPI_GetStatus(LPC_SPI_TypeDef* SPIx)
+{
+ CHECK_PARAM(PARAM_SPIx(SPIx));
+
+ return (SPIx->SPSR & SPI_SPSR_BITMASK);
+}
+
+/********************************************************************//**
+ * @brief Checks whether the specified SPI Status flag is set or not
+ * via inputSPIStatus parameter.
+ * @param[in] inputSPIStatus Value to check status of each flag type.
+ * This value is the return value from SPI_GetStatus().
+ * @param[in] SPIStatus Specifies the SPI status flag to check,
+ * should be one of the following:
+ - SPI_STAT_ABRT: Slave abort.
+ - SPI_STAT_MODF: Mode fault.
+ - SPI_STAT_ROVR: Read overrun.
+ - SPI_STAT_WCOL: Write collision.
+ - SPI_STAT_SPIF: SPI transfer complete.
+ * @return The new state of SPIStatus (SET or RESET)
+ *********************************************************************/
+FlagStatus SPI_CheckStatus (uint32_t inputSPIStatus, uint8_t SPIStatus)
+{
+ CHECK_PARAM(PARAM_SPI_STAT(SPIStatus));
+
+ return ((inputSPIStatus & SPIStatus) ? SET : RESET);
+}
+
+
+/**
+ * @}
+ */
+
+#endif /* _SPI */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/src/shared/cmsis/Drivers/source/lpc17xx_ssp.c b/src/shared/cmsis/Drivers/source/lpc17xx_ssp.c
@@ -0,0 +1,694 @@
+/**********************************************************************
+* $Id$ lpc17xx_ssp.c 2010-06-18
+*//**
+* @file lpc17xx_ssp.c
+* @brief Contains all functions support for SSP firmware library on LPC17xx
+* @version 3.0
+* @date 18. June. 2010
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2010, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @addtogroup SSP
+ * @{
+ */
+
+/* Includes ------------------------------------------------------------------- */
+#include "lpc17xx_ssp.h"
+#include "lpc17xx_clkpwr.h"
+
+
+/* If this source file built with example, the LPC17xx FW library configuration
+ * file in each example directory ("lpc17xx_libcfg.h") must be included,
+ * otherwise the default FW library configuration file must be included instead
+ */
+#ifdef __BUILD_WITH_EXAMPLE__
+#include "lpc17xx_libcfg.h"
+#else
+#include "lpc17xx_libcfg_default.h"
+#endif /* __BUILD_WITH_EXAMPLE__ */
+
+
+#ifdef _SSP
+
+/* Public Functions ----------------------------------------------------------- */
+/** @addtogroup SSP_Public_Functions
+ * @{
+ */
+static void setSSPclock (LPC_SSP_TypeDef *SSPx, uint32_t target_clock);
+
+/*********************************************************************//**
+ * @brief Setup clock rate for SSP device
+ * @param[in] SSPx SSP peripheral definition, should be:
+ * - LPC_SSP0: SSP0 peripheral
+ * - LPC_SSP1: SSP1 peripheral
+ * @param[in] target_clock : clock of SSP (Hz)
+ * @return None
+ ***********************************************************************/
+static void setSSPclock (LPC_SSP_TypeDef *SSPx, uint32_t target_clock)
+{
+ uint32_t prescale, cr0_div, cmp_clk, ssp_clk;
+
+ CHECK_PARAM(PARAM_SSPx(SSPx));
+
+ /* The SSP clock is derived from the (main system oscillator / 2),
+ so compute the best divider from that clock */
+ if (SSPx == LPC_SSP0){
+ ssp_clk = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_SSP0);
+ } else if (SSPx == LPC_SSP1) {
+ ssp_clk = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_SSP1);
+ } else {
+ return;
+ }
+
+ /* Find closest divider to get at or under the target frequency.
+ Use smallest prescale possible and rely on the divider to get
+ the closest target frequency */
+ cr0_div = 0;
+ cmp_clk = 0xFFFFFFFF;
+ prescale = 2;
+ while (cmp_clk > target_clock)
+ {
+ cmp_clk = ssp_clk / ((cr0_div + 1) * prescale);
+ if (cmp_clk > target_clock)
+ {
+ cr0_div++;
+ if (cr0_div > 0xFF)
+ {
+ cr0_div = 0;
+ prescale += 2;
+ }
+ }
+ }
+
+ /* Write computed prescaler and divider back to register */
+ SSPx->CR0 &= (~SSP_CR0_SCR(0xFF)) & SSP_CR0_BITMASK;
+ SSPx->CR0 |= (SSP_CR0_SCR(cr0_div)) & SSP_CR0_BITMASK;
+ SSPx->CPSR = prescale & SSP_CPSR_BITMASK;
+}
+
+/**
+ * @}
+ */
+
+/* Public Functions ----------------------------------------------------------- */
+/** @addtogroup SSP_Public_Functions
+ * @{
+ */
+
+/********************************************************************//**
+ * @brief Initializes the SSPx peripheral according to the specified
+* parameters in the SSP_ConfigStruct.
+ * @param[in] SSPx SSP peripheral selected, should be:
+ * - LPC_SSP0: SSP0 peripheral
+ * - LPC_SSP1: SSP1 peripheral
+ * @param[in] SSP_ConfigStruct Pointer to a SSP_CFG_Type structure
+* that contains the configuration information for the
+* specified SSP peripheral.
+ * @return None
+ *********************************************************************/
+void SSP_Init(LPC_SSP_TypeDef *SSPx, SSP_CFG_Type *SSP_ConfigStruct)
+{
+ uint32_t tmp;
+
+ CHECK_PARAM(PARAM_SSPx(SSPx));
+
+ if(SSPx == LPC_SSP0) {
+ /* Set up clock and power for SSP0 module */
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCSSP0, ENABLE);
+ } else if(SSPx == LPC_SSP1) {
+ /* Set up clock and power for SSP1 module */
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCSSP1, ENABLE);
+ } else {
+ return;
+ }
+
+ /* Configure SSP, interrupt is disable, LoopBack mode is disable,
+ * SSP is disable, Slave output is disable as default
+ */
+ tmp = ((SSP_ConfigStruct->CPHA) | (SSP_ConfigStruct->CPOL) \
+ | (SSP_ConfigStruct->FrameFormat) | (SSP_ConfigStruct->Databit))
+ & SSP_CR0_BITMASK;
+ // write back to SSP control register
+ SSPx->CR0 = tmp;
+
+ tmp = SSP_ConfigStruct->Mode & SSP_CR1_BITMASK;
+ // Write back to CR1
+ SSPx->CR1 = tmp;
+
+ // Set clock rate for SSP peripheral
+ setSSPclock(SSPx, SSP_ConfigStruct->ClockRate);
+}
+
+/*********************************************************************//**
+ * @brief De-initializes the SSPx peripheral registers to their
+* default reset values.
+ * @param[in] SSPx SSP peripheral selected, should be:
+ * - LPC_SSP0: SSP0 peripheral
+ * - LPC_SSP1: SSP1 peripheral
+ * @return None
+ **********************************************************************/
+void SSP_DeInit(LPC_SSP_TypeDef* SSPx)
+{
+ CHECK_PARAM(PARAM_SSPx(SSPx));
+
+ if (SSPx == LPC_SSP0){
+ /* Set up clock and power for SSP0 module */
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCSSP0, DISABLE);
+ } else if (SSPx == LPC_SSP1) {
+ /* Set up clock and power for SSP1 module */
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCSSP1, DISABLE);
+ }
+}
+
+/*****************************************************************************//**
+* @brief Get data size bit selected
+* @param[in] SSPx pointer to LPC_SSP_TypeDef structure, should be:
+* - LPC_SSP0: SSP0 peripheral
+* - LPC_SSP1: SSP1 peripheral
+* @return Data size, could be:
+* - SSP_DATABIT_4: 4 bit transfer
+* - SSP_DATABIT_5: 5 bit transfer
+* ...
+* - SSP_DATABIT_16: 16 bit transfer
+*******************************************************************************/
+uint8_t SSP_GetDataSize(LPC_SSP_TypeDef* SSPx)
+{
+ CHECK_PARAM(PARAM_SSPx(SSPx));
+ return (SSPx->CR0 & (0xF));
+}
+
+/*****************************************************************************//**
+* @brief Fills each SSP_InitStruct member with its default value:
+* - CPHA = SSP_CPHA_FIRST
+* - CPOL = SSP_CPOL_HI
+* - ClockRate = 1000000
+* - Databit = SSP_DATABIT_8
+* - Mode = SSP_MASTER_MODE
+* - FrameFormat = SSP_FRAME_SSP
+* @param[in] SSP_InitStruct Pointer to a SSP_CFG_Type structure
+* which will be initialized.
+* @return None
+*******************************************************************************/
+void SSP_ConfigStructInit(SSP_CFG_Type *SSP_InitStruct)
+{
+ SSP_InitStruct->CPHA = SSP_CPHA_FIRST;
+ SSP_InitStruct->CPOL = SSP_CPOL_HI;
+ SSP_InitStruct->ClockRate = 1000000;
+ SSP_InitStruct->Databit = SSP_DATABIT_8;
+ SSP_InitStruct->Mode = SSP_MASTER_MODE;
+ SSP_InitStruct->FrameFormat = SSP_FRAME_SPI;
+}
+
+
+/*********************************************************************//**
+ * @brief Enable or disable SSP peripheral's operation
+ * @param[in] SSPx SSP peripheral, should be:
+ * - LPC_SSP0: SSP0 peripheral
+ * - LPC_SSP1: SSP1 peripheral
+ * @param[in] NewState New State of SSPx peripheral's operation
+ * @return none
+ **********************************************************************/
+void SSP_Cmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState)
+{
+ CHECK_PARAM(PARAM_SSPx(SSPx));
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
+
+ if (NewState == ENABLE)
+ {
+ SSPx->CR1 |= SSP_CR1_SSP_EN;
+ }
+ else
+ {
+ SSPx->CR1 &= (~SSP_CR1_SSP_EN) & SSP_CR1_BITMASK;
+ }
+}
+
+/*********************************************************************//**
+ * @brief Enable or disable Loop Back mode function in SSP peripheral
+ * @param[in] SSPx SSP peripheral selected, should be:
+ * - LPC_SSP0: SSP0 peripheral
+ * - LPC_SSP1: SSP1 peripheral
+ * @param[in] NewState New State of Loop Back mode, should be:
+ * - ENABLE: Enable this function
+ * - DISABLE: Disable this function
+ * @return None
+ **********************************************************************/
+void SSP_LoopBackCmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState)
+{
+ CHECK_PARAM(PARAM_SSPx(SSPx));
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
+
+ if (NewState == ENABLE)
+ {
+ SSPx->CR1 |= SSP_CR1_LBM_EN;
+ }
+ else
+ {
+ SSPx->CR1 &= (~SSP_CR1_LBM_EN) & SSP_CR1_BITMASK;
+ }
+}
+
+/*********************************************************************//**
+ * @brief Enable or disable Slave Output function in SSP peripheral
+ * @param[in] SSPx SSP peripheral selected, should be:
+ * - LPC_SSP0: SSP0 peripheral
+ * - LPC_SSP1: SSP1 peripheral
+ * @param[in] NewState New State of Slave Output function, should be:
+ * - ENABLE: Slave Output in normal operation
+ * - DISABLE: Slave Output is disabled. This blocks
+ * SSP controller from driving the transmit data
+ * line (MISO)
+ * Note: This function is available when SSP peripheral in Slave mode
+ * @return None
+ **********************************************************************/
+void SSP_SlaveOutputCmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState)
+{
+ CHECK_PARAM(PARAM_SSPx(SSPx));
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
+
+ if (NewState == ENABLE)
+ {
+ SSPx->CR1 &= (~SSP_CR1_SO_DISABLE) & SSP_CR1_BITMASK;
+ }
+ else
+ {
+ SSPx->CR1 |= SSP_CR1_SO_DISABLE;
+ }
+}
+
+
+
+/*********************************************************************//**
+ * @brief Transmit a single data through SSPx peripheral
+ * @param[in] SSPx SSP peripheral selected, should be:
+ * - LPC_SSP0: SSP0 peripheral
+ * - LPC_SSP1: SSP1 peripheral
+ * @param[in] Data Data to transmit (must be 16 or 8-bit long,
+ * this depend on SSP data bit number configured)
+ * @return none
+ **********************************************************************/
+void SSP_SendData(LPC_SSP_TypeDef* SSPx, uint16_t Data)
+{
+ CHECK_PARAM(PARAM_SSPx(SSPx));
+
+ SSPx->DR = SSP_DR_BITMASK(Data);
+}
+
+
+
+/*********************************************************************//**
+ * @brief Receive a single data from SSPx peripheral
+ * @param[in] SSPx SSP peripheral selected, should be
+ * - LPC_SSP0: SSP0 peripheral
+ * - LPC_SSP1: SSP1 peripheral
+ * @return Data received (16-bit long)
+ **********************************************************************/
+uint16_t SSP_ReceiveData(LPC_SSP_TypeDef* SSPx)
+{
+ CHECK_PARAM(PARAM_SSPx(SSPx));
+
+ return ((uint16_t) (SSP_DR_BITMASK(SSPx->DR)));
+}
+
+/*********************************************************************//**
+ * @brief SSP Read write data function
+ * @param[in] SSPx Pointer to SSP peripheral, should be
+ * - LPC_SSP0: SSP0 peripheral
+ * - LPC_SSP1: SSP1 peripheral
+ * @param[in] dataCfg Pointer to a SSP_DATA_SETUP_Type structure that
+ * contains specified information about transmit
+ * data configuration.
+ * @param[in] xfType Transfer type, should be:
+ * - SSP_TRANSFER_POLLING: Polling mode
+ * - SSP_TRANSFER_INTERRUPT: Interrupt mode
+ * @return Actual Data length has been transferred in polling mode.
+ * In interrupt mode, always return (0)
+ * Return (-1) if error.
+ * Note: This function can be used in both master and slave mode.
+ ***********************************************************************/
+int32_t SSP_ReadWrite (LPC_SSP_TypeDef *SSPx, SSP_DATA_SETUP_Type *dataCfg, \
+ SSP_TRANSFER_Type xfType)
+{
+ uint8_t *rdata8 = NULL;
+ uint8_t *wdata8 = NULL;
+ uint16_t *rdata16 = NULL;
+ uint16_t *wdata16 = NULL;
+ uint32_t stat;
+ uint32_t tmp;
+ int32_t dataword;
+
+ dataCfg->rx_cnt = 0;
+ dataCfg->tx_cnt = 0;
+ dataCfg->status = 0;
+
+
+ /* Clear all remaining data in RX FIFO */
+ while (SSPx->SR & SSP_SR_RNE){
+ tmp = (uint32_t) SSP_ReceiveData(SSPx);
+ }
+
+ // Clear status
+ SSPx->ICR = SSP_ICR_BITMASK;
+ if(SSP_GetDataSize(SSPx)>SSP_DATABIT_8)
+ dataword = 1;
+ else dataword = 0;
+
+ // Polling mode ----------------------------------------------------------------------
+ if (xfType == SSP_TRANSFER_POLLING){
+ if (dataword == 0){
+ rdata8 = (uint8_t *)dataCfg->rx_data;
+ wdata8 = (uint8_t *)dataCfg->tx_data;
+ } else {
+ rdata16 = (uint16_t *)dataCfg->rx_data;
+ wdata16 = (uint16_t *)dataCfg->tx_data;
+ }
+ while ((dataCfg->tx_cnt < dataCfg->length) || (dataCfg->rx_cnt < dataCfg->length)){
+ if ((SSPx->SR & SSP_SR_TNF) && (dataCfg->tx_cnt < dataCfg->length)){
+ // Write data to buffer
+ if(dataCfg->tx_data == NULL){
+ if (dataword == 0){
+ SSP_SendData(SSPx, 0xFF);
+ dataCfg->tx_cnt++;
+ } else {
+ SSP_SendData(SSPx, 0xFFFF);
+ dataCfg->tx_cnt += 2;
+ }
+ } else {
+ if (dataword == 0){
+ SSP_SendData(SSPx, *wdata8);
+ wdata8++;
+ dataCfg->tx_cnt++;
+ } else {
+ SSP_SendData(SSPx, *wdata16);
+ wdata16++;
+ dataCfg->tx_cnt += 2;
+ }
+ }
+ }
+
+ // Check overrun error
+ if ((stat = SSPx->RIS) & SSP_RIS_ROR){
+ // save status and return
+ dataCfg->status = stat | SSP_STAT_ERROR;
+ return (-1);
+ }
+
+ // Check for any data available in RX FIFO
+ while ((SSPx->SR & SSP_SR_RNE) && (dataCfg->rx_cnt < dataCfg->length)){
+ // Read data from SSP data
+ tmp = SSP_ReceiveData(SSPx);
+
+ // Store data to destination
+ if (dataCfg->rx_data != NULL)
+ {
+ if (dataword == 0){
+ *(rdata8) = (uint8_t) tmp;
+ rdata8++;
+ } else {
+ *(rdata16) = (uint16_t) tmp;
+ rdata16++;
+ }
+ }
+ // Increase counter
+ if (dataword == 0){
+ dataCfg->rx_cnt++;
+ } else {
+ dataCfg->rx_cnt += 2;
+ }
+ }
+ }
+
+ // save status
+ dataCfg->status = SSP_STAT_DONE;
+
+ if (dataCfg->tx_data != NULL){
+ return dataCfg->tx_cnt;
+ } else if (dataCfg->rx_data != NULL){
+ return dataCfg->rx_cnt;
+ } else {
+ return (0);
+ }
+ }
+
+ // Interrupt mode ----------------------------------------------------------------------
+ else if (xfType == SSP_TRANSFER_INTERRUPT){
+
+ while ((SSPx->SR & SSP_SR_TNF) && (dataCfg->tx_cnt < dataCfg->length)){
+ // Write data to buffer
+ if(dataCfg->tx_data == NULL){
+ if (dataword == 0){
+ SSP_SendData(SSPx, 0xFF);
+ dataCfg->tx_cnt++;
+ } else {
+ SSP_SendData(SSPx, 0xFFFF);
+ dataCfg->tx_cnt += 2;
+ }
+ } else {
+ if (dataword == 0){
+ SSP_SendData(SSPx, (*(uint8_t *)((uint32_t)dataCfg->tx_data + dataCfg->tx_cnt)));
+ dataCfg->tx_cnt++;
+ } else {
+ SSP_SendData(SSPx, (*(uint16_t *)((uint32_t)dataCfg->tx_data + dataCfg->tx_cnt)));
+ dataCfg->tx_cnt += 2;
+ }
+ }
+
+ // Check error
+ if ((stat = SSPx->RIS) & SSP_RIS_ROR){
+ // save status and return
+ dataCfg->status = stat | SSP_STAT_ERROR;
+ return (-1);
+ }
+
+ // Check for any data available in RX FIFO
+ while ((SSPx->SR & SSP_SR_RNE) && (dataCfg->rx_cnt < dataCfg->length)){
+ // Read data from SSP data
+ tmp = SSP_ReceiveData(SSPx);
+
+ // Store data to destination
+ if (dataCfg->rx_data != NULL)
+ {
+ if (dataword == 0){
+ *(uint8_t *)((uint32_t)dataCfg->rx_data + dataCfg->rx_cnt) = (uint8_t) tmp;
+ } else {
+ *(uint16_t *)((uint32_t)dataCfg->rx_data + dataCfg->rx_cnt) = (uint16_t) tmp;
+ }
+ }
+ // Increase counter
+ if (dataword == 0){
+ dataCfg->rx_cnt++;
+ } else {
+ dataCfg->rx_cnt += 2;
+ }
+ }
+ }
+
+ // If there more data to sent or receive
+ if ((dataCfg->rx_cnt < dataCfg->length) || (dataCfg->tx_cnt < dataCfg->length)){
+ // Enable all interrupt
+ SSPx->IMSC = SSP_IMSC_BITMASK;
+ } else {
+ // Save status
+ dataCfg->status = SSP_STAT_DONE;
+ }
+ return (0);
+ }
+
+ return (-1);
+}
+
+/*********************************************************************//**
+ * @brief Checks whether the specified SSP status flag is set or not
+ * @param[in] SSPx SSP peripheral selected, should be:
+ * - LPC_SSP0: SSP0 peripheral
+ * - LPC_SSP1: SSP1 peripheral
+ * @param[in] FlagType Type of flag to check status, should be one
+ * of following:
+ * - SSP_STAT_TXFIFO_EMPTY: TX FIFO is empty
+ * - SSP_STAT_TXFIFO_NOTFULL: TX FIFO is not full
+ * - SSP_STAT_RXFIFO_NOTEMPTY: RX FIFO is not empty
+ * - SSP_STAT_RXFIFO_FULL: RX FIFO is full
+ * - SSP_STAT_BUSY: SSP peripheral is busy
+ * @return New State of specified SSP status flag
+ **********************************************************************/
+FlagStatus SSP_GetStatus(LPC_SSP_TypeDef* SSPx, uint32_t FlagType)
+{
+ CHECK_PARAM(PARAM_SSPx(SSPx));
+ CHECK_PARAM(PARAM_SSP_STAT(FlagType));
+
+ return ((SSPx->SR & FlagType) ? SET : RESET);
+}
+
+/*********************************************************************//**
+ * @brief Enable or disable specified interrupt type in SSP peripheral
+ * @param[in] SSPx SSP peripheral selected, should be:
+ * - LPC_SSP0: SSP0 peripheral
+ * - LPC_SSP1: SSP1 peripheral
+ * @param[in] IntType Interrupt type in SSP peripheral, should be:
+ * - SSP_INTCFG_ROR: Receive Overrun interrupt
+ * - SSP_INTCFG_RT: Receive Time out interrupt
+ * - SSP_INTCFG_RX: RX FIFO is at least half full interrupt
+ * - SSP_INTCFG_TX: TX FIFO is at least half empty interrupt
+ * @param[in] NewState New State of specified interrupt type, should be:
+ * - ENABLE: Enable this interrupt type
+ * - DISABLE: Disable this interrupt type
+ * @return None
+ * Note: We can enable/disable multi-interrupt type by OR multi value
+ **********************************************************************/
+void SSP_IntConfig(LPC_SSP_TypeDef *SSPx, uint32_t IntType, FunctionalState NewState)
+{
+ CHECK_PARAM(PARAM_SSPx(SSPx));
+
+ if (NewState == ENABLE)
+ {
+ SSPx->IMSC |= IntType;
+ }
+ else
+ {
+ SSPx->IMSC &= (~IntType) & SSP_IMSC_BITMASK;
+ }
+}
+
+/*********************************************************************//**
+ * @brief Check whether the specified Raw interrupt status flag is
+ * set or not
+ * @param[in] SSPx SSP peripheral selected, should be:
+ * - LPC_SSP0: SSP0 peripheral
+ * - LPC_SSP1: SSP1 peripheral
+ * @param[in] RawIntType Raw Interrupt Type, should be:
+ * - SSP_INTSTAT_RAW_ROR: Receive Overrun interrupt
+ * - SSP_INTSTAT_RAW_RT: Receive Time out interrupt
+ * - SSP_INTSTAT_RAW_RX: RX FIFO is at least half full interrupt
+ * - SSP_INTSTAT_RAW_TX: TX FIFO is at least half empty interrupt
+ * @return New State of specified Raw interrupt status flag in SSP peripheral
+ * Note: Enabling/Disabling specified interrupt in SSP peripheral does not
+ * effect to Raw Interrupt Status flag.
+ **********************************************************************/
+IntStatus SSP_GetRawIntStatus(LPC_SSP_TypeDef *SSPx, uint32_t RawIntType)
+{
+ CHECK_PARAM(PARAM_SSPx(SSPx));
+ CHECK_PARAM(PARAM_SSP_INTSTAT_RAW(RawIntType));
+
+ return ((SSPx->RIS & RawIntType) ? SET : RESET);
+}
+
+/*********************************************************************//**
+ * @brief Get Raw Interrupt Status register
+ * @param[in] SSPx SSP peripheral selected, should be:
+ * - LPC_SSP0: SSP0 peripheral
+ * - LPC_SSP1: SSP1 peripheral
+ * @return Raw Interrupt Status (RIS) register value
+ **********************************************************************/
+uint32_t SSP_GetRawIntStatusReg(LPC_SSP_TypeDef *SSPx)
+{
+ CHECK_PARAM(PARAM_SSPx(SSPx));
+ return (SSPx->RIS);
+}
+
+/*********************************************************************//**
+ * @brief Check whether the specified interrupt status flag is
+ * set or not
+ * @param[in] SSPx SSP peripheral selected, should be:
+ * - LPC_SSP0: SSP0 peripheral
+ * - LPC_SSP1: SSP1 peripheral
+ * @param[in] IntType Raw Interrupt Type, should be:
+ * - SSP_INTSTAT_ROR: Receive Overrun interrupt
+ * - SSP_INTSTAT_RT: Receive Time out interrupt
+ * - SSP_INTSTAT_RX: RX FIFO is at least half full interrupt
+ * - SSP_INTSTAT_TX: TX FIFO is at least half empty interrupt
+ * @return New State of specified interrupt status flag in SSP peripheral
+ * Note: Enabling/Disabling specified interrupt in SSP peripheral effects
+ * to Interrupt Status flag.
+ **********************************************************************/
+IntStatus SSP_GetIntStatus (LPC_SSP_TypeDef *SSPx, uint32_t IntType)
+{
+ CHECK_PARAM(PARAM_SSPx(SSPx));
+ CHECK_PARAM(PARAM_SSP_INTSTAT(IntType));
+
+ return ((SSPx->MIS & IntType) ? SET :RESET);
+}
+
+/*********************************************************************//**
+ * @brief Clear specified interrupt pending in SSP peripheral
+ * @param[in] SSPx SSP peripheral selected, should be:
+ * - LPC_SSP0: SSP0 peripheral
+ * - LPC_SSP1: SSP1 peripheral
+ * @param[in] IntType Interrupt pending to clear, should be:
+ * - SSP_INTCLR_ROR: clears the "frame was received when
+ * RxFIFO was full" interrupt.
+ * - SSP_INTCLR_RT: clears the "Rx FIFO was not empty and
+ * has not been read for a timeout period" interrupt.
+ * @return None
+ **********************************************************************/
+void SSP_ClearIntPending(LPC_SSP_TypeDef *SSPx, uint32_t IntType)
+{
+ CHECK_PARAM(PARAM_SSPx(SSPx));
+ CHECK_PARAM(PARAM_SSP_INTCLR(IntType));
+
+ SSPx->ICR = IntType;
+}
+
+/*********************************************************************//**
+ * @brief Enable/Disable DMA function for SSP peripheral
+ * @param[in] SSPx SSP peripheral selected, should be:
+ * - LPC_SSP0: SSP0 peripheral
+ * - LPC_SSP1: SSP1 peripheral
+ * @param[in] DMAMode Type of DMA, should be:
+ * - SSP_DMA_TX: DMA for the transmit FIFO
+ * - SSP_DMA_RX: DMA for the Receive FIFO
+ * @param[in] NewState New State of DMA function on SSP peripheral,
+ * should be:
+ * - ENALBE: Enable this function
+ * - DISABLE: Disable this function
+ * @return None
+ **********************************************************************/
+void SSP_DMACmd(LPC_SSP_TypeDef *SSPx, uint32_t DMAMode, FunctionalState NewState)
+{
+ CHECK_PARAM(PARAM_SSPx(SSPx));
+ CHECK_PARAM(PARAM_SSP_DMA(DMAMode));
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
+
+ if (NewState == ENABLE)
+ {
+ SSPx->DMACR |= DMAMode;
+ }
+ else
+ {
+ SSPx->DMACR &= (~DMAMode) & SSP_DMA_BITMASK;
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif /* _SSP */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
+
diff --git a/src/shared/cmsis/Drivers/source/lpc17xx_systick.c b/src/shared/cmsis/Drivers/source/lpc17xx_systick.c
@@ -0,0 +1,193 @@
+/**********************************************************************
+* $Id$ lpc17xx_systick.c 2010-05-21
+*//**
+* @file lpc17xx_systick.c
+* @brief Contains all functions support for SYSTICK firmware library
+* on LPC17xx
+* @version 2.0
+* @date 21. May. 2010
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2010, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @addtogroup SYSTICK
+ * @{
+ */
+
+/* Includes ------------------------------------------------------------------- */
+#include "lpc17xx_systick.h"
+#include "lpc17xx_clkpwr.h"
+
+/* If this source file built with example, the LPC17xx FW library configuration
+ * file in each example directory ("lpc17xx_libcfg.h") must be included,
+ * otherwise the default FW library configuration file must be included instead
+ */
+#ifdef __BUILD_WITH_EXAMPLE__
+#include "lpc17xx_libcfg.h"
+#else
+#include "lpc17xx_libcfg_default.h"
+#endif /* __BUILD_WITH_EXAMPLE__ */
+
+
+#ifdef _SYSTICK
+
+/* Public Functions ----------------------------------------------------------- */
+/** @addtogroup SYSTICK_Public_Functions
+ * @{
+ */
+/*********************************************************************//**
+ * @brief Initial System Tick with using internal CPU clock source
+ * @param[in] time time interval(ms)
+ * @return None
+ **********************************************************************/
+void SYSTICK_InternalInit(uint32_t time)
+{
+ uint32_t cclk;
+ float maxtime;
+
+ cclk = SystemCoreClock;
+ /* With internal CPU clock frequency for LPC17xx is 'SystemCoreClock'
+ * And limit 24 bit for RELOAD value
+ * So the maximum time can be set:
+ * 1/SystemCoreClock * (2^24) * 1000 (ms)
+ */
+ //check time value is available or not
+ maxtime = (1<<24)/(SystemCoreClock / 1000) ;
+ if(time > maxtime)
+ //Error loop
+ while(1);
+ else
+ {
+ //Select CPU clock is System Tick clock source
+ SysTick->CTRL |= ST_CTRL_CLKSOURCE;
+ /* Set RELOAD value
+ * RELOAD = (SystemCoreClock/1000) * time - 1
+ * with time base is millisecond
+ */
+ SysTick->LOAD = (cclk/1000)*time - 1;
+ }
+}
+
+/*********************************************************************//**
+ * @brief Initial System Tick with using external clock source
+ * @param[in] freq external clock frequency(Hz)
+ * @param[in] time time interval(ms)
+ * @return None
+ **********************************************************************/
+void SYSTICK_ExternalInit(uint32_t freq, uint32_t time)
+{
+ float maxtime;
+
+ /* With external clock frequency for LPC17xx is 'freq'
+ * And limit 24 bit for RELOAD value
+ * So the maximum time can be set:
+ * 1/freq * (2^24) * 1000 (ms)
+ */
+ //check time value is available or not
+ maxtime = (1<<24)/(freq / 1000) ;
+ if (time>maxtime)
+ //Error Loop
+ while(1);
+ else
+ {
+ //Select external clock is System Tick clock source
+ SysTick->CTRL &= ~ ST_CTRL_CLKSOURCE;
+ /* Set RELOAD value
+ * RELOAD = (freq/1000) * time - 1
+ * with time base is millisecond
+ */
+ maxtime = (freq/1000)*time - 1;
+ SysTick->LOAD = (freq/1000)*time - 1;
+ }
+}
+
+/*********************************************************************//**
+ * @brief Enable/disable System Tick counter
+ * @param[in] NewState System Tick counter status, should be:
+ * - ENABLE
+ * - DISABLE
+ * @return None
+ **********************************************************************/
+void SYSTICK_Cmd(FunctionalState NewState)
+{
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
+
+ if(NewState == ENABLE)
+ //Enable System Tick counter
+ SysTick->CTRL |= ST_CTRL_ENABLE;
+ else
+ //Disable System Tick counter
+ SysTick->CTRL &= ~ST_CTRL_ENABLE;
+}
+
+/*********************************************************************//**
+ * @brief Enable/disable System Tick interrupt
+ * @param[in] NewState System Tick interrupt status, should be:
+ * - ENABLE
+ * - DISABLE
+ * @return None
+ **********************************************************************/
+void SYSTICK_IntCmd(FunctionalState NewState)
+{
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
+
+ if(NewState == ENABLE)
+ //Enable System Tick counter
+ SysTick->CTRL |= ST_CTRL_TICKINT;
+ else
+ //Disable System Tick counter
+ SysTick->CTRL &= ~ST_CTRL_TICKINT;
+}
+
+/*********************************************************************//**
+ * @brief Get current value of System Tick counter
+ * @param[in] None
+ * @return current value of System Tick counter
+ **********************************************************************/
+uint32_t SYSTICK_GetCurrentValue(void)
+{
+ return (SysTick->VAL);
+}
+
+/*********************************************************************//**
+ * @brief Clear Counter flag
+ * @param[in] None
+ * @return None
+ **********************************************************************/
+void SYSTICK_ClearCounterFlag(void)
+{
+ SysTick->CTRL &= ~ST_CTRL_COUNTFLAG;
+}
+/**
+ * @}
+ */
+
+#endif /* _SYSTICK */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
+
diff --git a/src/shared/cmsis/Drivers/source/lpc17xx_timer.c b/src/shared/cmsis/Drivers/source/lpc17xx_timer.c
@@ -0,0 +1,609 @@
+/**********************************************************************
+* $Id$ lpc17xx_timer.c 2011-03-10
+*//**
+* @file lpc17xx_timer.c
+* @brief Contains all functions support for Timer firmware library
+* on LPC17xx
+* @version 3.1
+* @date 10. March. 2011
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @addtogroup TIM
+ * @{
+ */
+
+/* Includes ------------------------------------------------------------------- */
+#include "lpc17xx_timer.h"
+#include "lpc17xx_clkpwr.h"
+#include "lpc17xx_pinsel.h"
+
+/* If this source file built with example, the LPC17xx FW library configuration
+ * file in each example directory ("lpc17xx_libcfg.h") must be included,
+ * otherwise the default FW library configuration file must be included instead
+ */
+#ifdef __BUILD_WITH_EXAMPLE__
+#include "lpc17xx_libcfg.h"
+#else
+#include "lpc17xx_libcfg_default.h"
+#endif /* __BUILD_WITH_EXAMPLE__ */
+
+#ifdef _TIM
+
+/* Private Functions ---------------------------------------------------------- */
+
+static uint32_t getPClock (uint32_t timernum);
+static uint32_t converUSecToVal (uint32_t timernum, uint32_t usec);
+static uint32_t converPtrToTimeNum (LPC_TIM_TypeDef *TIMx);
+
+
+/*********************************************************************//**
+ * @brief Get peripheral clock of each timer controller
+ * @param[in] timernum Timer number
+ * @return Peripheral clock of timer
+ **********************************************************************/
+static uint32_t getPClock (uint32_t timernum)
+{
+ uint32_t clkdlycnt = 0;
+ switch (timernum)
+ {
+ case 0:
+ clkdlycnt = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_TIMER0);
+ break;
+
+ case 1:
+ clkdlycnt = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_TIMER1);
+ break;
+
+ case 2:
+ clkdlycnt = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_TIMER2);
+ break;
+
+ case 3:
+ clkdlycnt = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_TIMER3);
+ break;
+ }
+ return clkdlycnt;
+}
+
+
+/*********************************************************************//**
+ * @brief Convert a time to a timer count value
+ * @param[in] timernum Timer number
+ * @param[in] usec Time in microseconds
+ * @return The number of required clock ticks to give the time delay
+ **********************************************************************/
+uint32_t converUSecToVal (uint32_t timernum, uint32_t usec)
+{
+ uint64_t clkdlycnt = 0;
+
+ // Get Pclock of timer
+ clkdlycnt = (uint64_t) getPClock(timernum);
+
+ clkdlycnt = (clkdlycnt * usec) / 1000000;
+ return (uint32_t) clkdlycnt;
+}
+
+
+/*********************************************************************//**
+ * @brief Convert a timer register pointer to a timer number
+ * @param[in] TIMx Pointer to LPC_TIM_TypeDef, should be:
+ * - LPC_TIM0: TIMER0 peripheral
+ * - LPC_TIM1: TIMER1 peripheral
+ * - LPC_TIM2: TIMER2 peripheral
+ * - LPC_TIM3: TIMER3 peripheral
+ * @return The timer number (0 to 3) or 0xFFFF FFFF if register pointer is bad
+ **********************************************************************/
+uint32_t converPtrToTimeNum (LPC_TIM_TypeDef *TIMx)
+{
+ uint32_t tnum = 0xFFFFFFFF;
+
+ if (TIMx == LPC_TIM0)
+ {
+ tnum = 0;
+ }
+ else if (TIMx == LPC_TIM1)
+ {
+ tnum = 1;
+ }
+ else if (TIMx == LPC_TIM2)
+ {
+ tnum = 2;
+ }
+ else if (TIMx == LPC_TIM3)
+ {
+ tnum = 3;
+ }
+
+ return tnum;
+}
+
+/* End of Private Functions ---------------------------------------------------- */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @addtogroup TIM_Public_Functions
+ * @{
+ */
+
+/*********************************************************************//**
+ * @brief Get Interrupt Status
+ * @param[in] TIMx Timer selection, should be:
+ * - LPC_TIM0: TIMER0 peripheral
+ * - LPC_TIM1: TIMER1 peripheral
+ * - LPC_TIM2: TIMER2 peripheral
+ * - LPC_TIM3: TIMER3 peripheral
+ * @param[in] IntFlag: interrupt type, should be:
+ * - TIM_MR0_INT: Interrupt for Match channel 0
+ * - TIM_MR1_INT: Interrupt for Match channel 1
+ * - TIM_MR2_INT: Interrupt for Match channel 2
+ * - TIM_MR3_INT: Interrupt for Match channel 3
+ * - TIM_CR0_INT: Interrupt for Capture channel 0
+ * - TIM_CR1_INT: Interrupt for Capture channel 1
+ * @return FlagStatus
+ * - SET : interrupt
+ * - RESET : no interrupt
+ **********************************************************************/
+FlagStatus TIM_GetIntStatus(LPC_TIM_TypeDef *TIMx, TIM_INT_TYPE IntFlag)
+{
+ uint8_t temp;
+ CHECK_PARAM(PARAM_TIMx(TIMx));
+ CHECK_PARAM(PARAM_TIM_INT_TYPE(IntFlag));
+ temp = (TIMx->IR)& TIM_IR_CLR(IntFlag);
+ if (temp)
+ return SET;
+
+ return RESET;
+
+}
+/*********************************************************************//**
+ * @brief Get Capture Interrupt Status
+ * @param[in] TIMx Timer selection, should be:
+ * - LPC_TIM0: TIMER0 peripheral
+ * - LPC_TIM1: TIMER1 peripheral
+ * - LPC_TIM2: TIMER2 peripheral
+ * - LPC_TIM3: TIMER3 peripheral
+ * @param[in] IntFlag: interrupt type, should be:
+ * - TIM_MR0_INT: Interrupt for Match channel 0
+ * - TIM_MR1_INT: Interrupt for Match channel 1
+ * - TIM_MR2_INT: Interrupt for Match channel 2
+ * - TIM_MR3_INT: Interrupt for Match channel 3
+ * - TIM_CR0_INT: Interrupt for Capture channel 0
+ * - TIM_CR1_INT: Interrupt for Capture channel 1
+ * @return FlagStatus
+ * - SET : interrupt
+ * - RESET : no interrupt
+ **********************************************************************/
+FlagStatus TIM_GetIntCaptureStatus(LPC_TIM_TypeDef *TIMx, TIM_INT_TYPE IntFlag)
+{
+ uint8_t temp;
+ CHECK_PARAM(PARAM_TIMx(TIMx));
+ CHECK_PARAM(PARAM_TIM_INT_TYPE(IntFlag));
+ temp = (TIMx->IR) & (1<<(4+IntFlag));
+ if(temp)
+ return SET;
+ return RESET;
+}
+/*********************************************************************//**
+ * @brief Clear Interrupt pending
+ * @param[in] TIMx Timer selection, should be:
+ * - LPC_TIM0: TIMER0 peripheral
+ * - LPC_TIM1: TIMER1 peripheral
+ * - LPC_TIM2: TIMER2 peripheral
+ * - LPC_TIM3: TIMER3 peripheral
+ * @param[in] IntFlag: interrupt type, should be:
+ * - TIM_MR0_INT: Interrupt for Match channel 0
+ * - TIM_MR1_INT: Interrupt for Match channel 1
+ * - TIM_MR2_INT: Interrupt for Match channel 2
+ * - TIM_MR3_INT: Interrupt for Match channel 3
+ * - TIM_CR0_INT: Interrupt for Capture channel 0
+ * - TIM_CR1_INT: Interrupt for Capture channel 1
+ * @return None
+ **********************************************************************/
+void TIM_ClearIntPending(LPC_TIM_TypeDef *TIMx, TIM_INT_TYPE IntFlag)
+{
+ CHECK_PARAM(PARAM_TIMx(TIMx));
+ CHECK_PARAM(PARAM_TIM_INT_TYPE(IntFlag));
+ TIMx->IR = TIM_IR_CLR(IntFlag);
+}
+
+/*********************************************************************//**
+ * @brief Clear Capture Interrupt pending
+ * @param[in] TIMx Timer selection, should be
+ * - LPC_TIM0: TIMER0 peripheral
+ * - LPC_TIM1: TIMER1 peripheral
+ * - LPC_TIM2: TIMER2 peripheral
+ * - LPC_TIM3: TIMER3 peripheral
+ * @param[in] IntFlag interrupt type, should be:
+ * - TIM_MR0_INT: Interrupt for Match channel 0
+ * - TIM_MR1_INT: Interrupt for Match channel 1
+ * - TIM_MR2_INT: Interrupt for Match channel 2
+ * - TIM_MR3_INT: Interrupt for Match channel 3
+ * - TIM_CR0_INT: Interrupt for Capture channel 0
+ * - TIM_CR1_INT: Interrupt for Capture channel 1
+ * @return None
+ **********************************************************************/
+void TIM_ClearIntCapturePending(LPC_TIM_TypeDef *TIMx, TIM_INT_TYPE IntFlag)
+{
+ CHECK_PARAM(PARAM_TIMx(TIMx));
+ CHECK_PARAM(PARAM_TIM_INT_TYPE(IntFlag));
+ TIMx->IR = (1<<(4+IntFlag));
+}
+
+/*********************************************************************//**
+ * @brief Configuration for Timer at initial time
+ * @param[in] TimerCounterMode timer counter mode, should be:
+ * - TIM_TIMER_MODE: Timer mode
+ * - TIM_COUNTER_RISING_MODE: Counter rising mode
+ * - TIM_COUNTER_FALLING_MODE: Counter falling mode
+ * - TIM_COUNTER_ANY_MODE:Counter on both edges
+ * @param[in] TIM_ConfigStruct pointer to TIM_TIMERCFG_Type or
+ * TIM_COUNTERCFG_Type
+ * @return None
+ **********************************************************************/
+void TIM_ConfigStructInit(TIM_MODE_OPT TimerCounterMode, void *TIM_ConfigStruct)
+{
+ if (TimerCounterMode == TIM_TIMER_MODE )
+ {
+ TIM_TIMERCFG_Type * pTimeCfg = (TIM_TIMERCFG_Type *)TIM_ConfigStruct;
+ pTimeCfg->PrescaleOption = TIM_PRESCALE_USVAL;
+ pTimeCfg->PrescaleValue = 1;
+ }
+ else
+ {
+ TIM_COUNTERCFG_Type * pCounterCfg = (TIM_COUNTERCFG_Type *)TIM_ConfigStruct;
+ pCounterCfg->CountInputSelect = TIM_COUNTER_INCAP0;
+ }
+}
+
+/*********************************************************************//**
+ * @brief Initial Timer/Counter device
+ * Set Clock frequency for Timer
+ * Set initial configuration for Timer
+ * @param[in] TIMx Timer selection, should be:
+ * - LPC_TIM0: TIMER0 peripheral
+ * - LPC_TIM1: TIMER1 peripheral
+ * - LPC_TIM2: TIMER2 peripheral
+ * - LPC_TIM3: TIMER3 peripheral
+ * @param[in] TimerCounterMode Timer counter mode, should be:
+ * - TIM_TIMER_MODE: Timer mode
+ * - TIM_COUNTER_RISING_MODE: Counter rising mode
+ * - TIM_COUNTER_FALLING_MODE: Counter falling mode
+ * - TIM_COUNTER_ANY_MODE:Counter on both edges
+ * @param[in] TIM_ConfigStruct pointer to TIM_TIMERCFG_Type
+ * that contains the configuration information for the
+ * specified Timer peripheral.
+ * @return None
+ **********************************************************************/
+void TIM_Init(LPC_TIM_TypeDef *TIMx, TIM_MODE_OPT TimerCounterMode, void *TIM_ConfigStruct)
+{
+ TIM_TIMERCFG_Type *pTimeCfg;
+ TIM_COUNTERCFG_Type *pCounterCfg;
+
+ CHECK_PARAM(PARAM_TIMx(TIMx));
+ CHECK_PARAM(PARAM_TIM_MODE_OPT(TimerCounterMode));
+
+ //set power
+
+ if (TIMx== LPC_TIM0)
+ {
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCTIM0, ENABLE);
+ //PCLK_Timer0 = CCLK/4
+ CLKPWR_SetPCLKDiv (CLKPWR_PCLKSEL_TIMER0, CLKPWR_PCLKSEL_CCLK_DIV_4);
+ }
+ else if (TIMx== LPC_TIM1)
+ {
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCTIM1, ENABLE);
+ //PCLK_Timer1 = CCLK/4
+ CLKPWR_SetPCLKDiv (CLKPWR_PCLKSEL_TIMER1, CLKPWR_PCLKSEL_CCLK_DIV_4);
+
+ }
+
+ else if (TIMx== LPC_TIM2)
+ {
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCTIM2, ENABLE);
+ //PCLK_Timer2= CCLK/4
+ CLKPWR_SetPCLKDiv (CLKPWR_PCLKSEL_TIMER2, CLKPWR_PCLKSEL_CCLK_DIV_4);
+ }
+ else if (TIMx== LPC_TIM3)
+ {
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCTIM3, ENABLE);
+ //PCLK_Timer3= CCLK/4
+ CLKPWR_SetPCLKDiv (CLKPWR_PCLKSEL_TIMER3, CLKPWR_PCLKSEL_CCLK_DIV_4);
+
+ }
+
+ TIMx->CCR &= ~TIM_CTCR_MODE_MASK;
+ TIMx->CCR |= TIM_TIMER_MODE;
+
+ TIMx->TC =0;
+ TIMx->PC =0;
+ TIMx->PR =0;
+ TIMx->TCR |= (1<<1); //Reset Counter
+ TIMx->TCR &= ~(1<<1); //release reset
+ if (TimerCounterMode == TIM_TIMER_MODE )
+ {
+ pTimeCfg = (TIM_TIMERCFG_Type *)TIM_ConfigStruct;
+ if (pTimeCfg->PrescaleOption == TIM_PRESCALE_TICKVAL)
+ {
+ TIMx->PR = pTimeCfg->PrescaleValue -1 ;
+ }
+ else
+ {
+ TIMx->PR = converUSecToVal (converPtrToTimeNum(TIMx),pTimeCfg->PrescaleValue)-1;
+ }
+ }
+ else
+ {
+
+ pCounterCfg = (TIM_COUNTERCFG_Type *)TIM_ConfigStruct;
+ TIMx->CCR &= ~TIM_CTCR_INPUT_MASK;
+ if (pCounterCfg->CountInputSelect == TIM_COUNTER_INCAP1)
+ TIMx->CCR |= _BIT(2);
+ }
+
+ // Clear interrupt pending
+ TIMx->IR = 0xFFFFFFFF;
+
+}
+
+/*********************************************************************//**
+ * @brief Close Timer/Counter device
+ * @param[in] TIMx Pointer to timer device, should be:
+ * - LPC_TIM0: TIMER0 peripheral
+ * - LPC_TIM1: TIMER1 peripheral
+ * - LPC_TIM2: TIMER2 peripheral
+ * - LPC_TIM3: TIMER3 peripheral
+ * @return None
+ **********************************************************************/
+void TIM_DeInit (LPC_TIM_TypeDef *TIMx)
+{
+ CHECK_PARAM(PARAM_TIMx(TIMx));
+ // Disable timer/counter
+ TIMx->TCR = 0x00;
+
+ // Disable power
+ if (TIMx== LPC_TIM0)
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCTIM0, DISABLE);
+
+ else if (TIMx== LPC_TIM1)
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCTIM1, DISABLE);
+
+ else if (TIMx== LPC_TIM2)
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCTIM2, DISABLE);
+
+ else if (TIMx== LPC_TIM3)
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCTIM2, DISABLE);
+
+}
+
+/*********************************************************************//**
+ * @brief Start/Stop Timer/Counter device
+ * @param[in] TIMx Pointer to timer device, should be:
+ * - LPC_TIM0: TIMER0 peripheral
+ * - LPC_TIM1: TIMER1 peripheral
+ * - LPC_TIM2: TIMER2 peripheral
+ * - LPC_TIM3: TIMER3 peripheral
+ * @param[in] NewState
+ * - ENABLE : set timer enable
+ * - DISABLE : disable timer
+ * @return None
+ **********************************************************************/
+void TIM_Cmd(LPC_TIM_TypeDef *TIMx, FunctionalState NewState)
+{
+ CHECK_PARAM(PARAM_TIMx(TIMx));
+ if (NewState == ENABLE)
+ {
+ TIMx->TCR |= TIM_ENABLE;
+ }
+ else
+ {
+ TIMx->TCR &= ~TIM_ENABLE;
+ }
+}
+
+/*********************************************************************//**
+ * @brief Reset Timer/Counter device,
+ * Make TC and PC are synchronously reset on the next
+ * positive edge of PCLK
+ * @param[in] TIMx Pointer to timer device, should be:
+ * - LPC_TIM0: TIMER0 peripheral
+ * - LPC_TIM1: TIMER1 peripheral
+ * - LPC_TIM2: TIMER2 peripheral
+ * - LPC_TIM3: TIMER3 peripheral
+ * @return None
+ **********************************************************************/
+void TIM_ResetCounter(LPC_TIM_TypeDef *TIMx)
+{
+ CHECK_PARAM(PARAM_TIMx(TIMx));
+ TIMx->TCR |= TIM_RESET;
+ TIMx->TCR &= ~TIM_RESET;
+}
+
+/*********************************************************************//**
+ * @brief Configuration for Match register
+ * @param[in] TIMx Pointer to timer device, should be:
+ * - LPC_TIM0: TIMER0 peripheral
+ * - LPC_TIM1: TIMER1 peripheral
+ * - LPC_TIM2: TIMER2 peripheral
+ * - LPC_TIM3: TIMER3 peripheral
+ * @param[in] TIM_MatchConfigStruct Pointer to TIM_MATCHCFG_Type
+ * - MatchChannel : choose channel 0 or 1
+ * - IntOnMatch : if SET, interrupt will be generated when MRxx match
+ * the value in TC
+ * - StopOnMatch : if SET, TC and PC will be stopped whenM Rxx match
+ * the value in TC
+ * - ResetOnMatch : if SET, Reset on MR0 when MRxx match
+ * the value in TC
+ * -ExtMatchOutputType: Select output for external match
+ * + 0: Do nothing for external output pin if match
+ * + 1: Force external output pin to low if match
+ * + 2: Force external output pin to high if match
+ * + 3: Toggle external output pin if match
+ * MatchValue: Set the value to be compared with TC value
+ * @return None
+ **********************************************************************/
+void TIM_ConfigMatch(LPC_TIM_TypeDef *TIMx, TIM_MATCHCFG_Type *TIM_MatchConfigStruct)
+{
+
+ CHECK_PARAM(PARAM_TIMx(TIMx));
+ CHECK_PARAM(PARAM_TIM_EXTMATCH_OPT(TIM_MatchConfigStruct->ExtMatchOutputType));
+
+ switch(TIM_MatchConfigStruct->MatchChannel)
+ {
+ case 0:
+ TIMx->MR0 = TIM_MatchConfigStruct->MatchValue;
+ break;
+ case 1:
+ TIMx->MR1 = TIM_MatchConfigStruct->MatchValue;
+ break;
+ case 2:
+ TIMx->MR2 = TIM_MatchConfigStruct->MatchValue;
+ break;
+ case 3:
+ TIMx->MR3 = TIM_MatchConfigStruct->MatchValue;
+ break;
+ default:
+ //Error match value
+ //Error loop
+ while(1);
+ }
+ //interrupt on MRn
+ TIMx->MCR &=~TIM_MCR_CHANNEL_MASKBIT(TIM_MatchConfigStruct->MatchChannel);
+
+ if (TIM_MatchConfigStruct->IntOnMatch)
+ TIMx->MCR |= TIM_INT_ON_MATCH(TIM_MatchConfigStruct->MatchChannel);
+
+ //reset on MRn
+ if (TIM_MatchConfigStruct->ResetOnMatch)
+ TIMx->MCR |= TIM_RESET_ON_MATCH(TIM_MatchConfigStruct->MatchChannel);
+
+ //stop on MRn
+ if (TIM_MatchConfigStruct->StopOnMatch)
+ TIMx->MCR |= TIM_STOP_ON_MATCH(TIM_MatchConfigStruct->MatchChannel);
+
+ // match output type
+
+ TIMx->EMR &= ~TIM_EM_MASK(TIM_MatchConfigStruct->MatchChannel);
+ TIMx->EMR |= TIM_EM_SET(TIM_MatchConfigStruct->MatchChannel,TIM_MatchConfigStruct->ExtMatchOutputType);
+}
+/*********************************************************************//**
+ * @brief Update Match value
+ * @param[in] TIMx Pointer to timer device, should be:
+ * - LPC_TIM0: TIMER0 peripheral
+ * - LPC_TIM1: TIMER1 peripheral
+ * - LPC_TIM2: TIMER2 peripheral
+ * - LPC_TIM3: TIMER3 peripheral
+ * @param[in] MatchChannel Match channel, should be: 0..3
+ * @param[in] MatchValue updated match value
+ * @return None
+ **********************************************************************/
+void TIM_UpdateMatchValue(LPC_TIM_TypeDef *TIMx,uint8_t MatchChannel, uint32_t MatchValue)
+{
+ CHECK_PARAM(PARAM_TIMx(TIMx));
+ switch(MatchChannel)
+ {
+ case 0:
+ TIMx->MR0 = MatchValue;
+ break;
+ case 1:
+ TIMx->MR1 = MatchValue;
+ break;
+ case 2:
+ TIMx->MR2 = MatchValue;
+ break;
+ case 3:
+ TIMx->MR3 = MatchValue;
+ break;
+ default:
+ //Error Loop
+ while(1);
+ }
+
+}
+/*********************************************************************//**
+ * @brief Configuration for Capture register
+ * @param[in] TIMx Pointer to timer device, should be:
+ * - LPC_TIM0: TIMER0 peripheral
+ * - LPC_TIM1: TIMER1 peripheral
+ * - LPC_TIM2: TIMER2 peripheral
+ * - LPC_TIM3: TIMER3 peripheral
+ * - CaptureChannel: set the channel to capture data
+ * - RisingEdge : if SET, Capture at rising edge
+ * - FallingEdge : if SET, Capture at falling edge
+ * - IntOnCaption : if SET, Capture generate interrupt
+ * @param[in] TIM_CaptureConfigStruct Pointer to TIM_CAPTURECFG_Type
+ * @return None
+ **********************************************************************/
+void TIM_ConfigCapture(LPC_TIM_TypeDef *TIMx, TIM_CAPTURECFG_Type *TIM_CaptureConfigStruct)
+{
+
+ CHECK_PARAM(PARAM_TIMx(TIMx));
+ TIMx->CCR &= ~TIM_CCR_CHANNEL_MASKBIT(TIM_CaptureConfigStruct->CaptureChannel);
+
+ if (TIM_CaptureConfigStruct->RisingEdge)
+ TIMx->CCR |= TIM_CAP_RISING(TIM_CaptureConfigStruct->CaptureChannel);
+
+ if (TIM_CaptureConfigStruct->FallingEdge)
+ TIMx->CCR |= TIM_CAP_FALLING(TIM_CaptureConfigStruct->CaptureChannel);
+
+ if (TIM_CaptureConfigStruct->IntOnCaption)
+ TIMx->CCR |= TIM_INT_ON_CAP(TIM_CaptureConfigStruct->CaptureChannel);
+}
+
+/*********************************************************************//**
+ * @brief Read value of capture register in timer/counter device
+ * @param[in] TIMx Pointer to timer/counter device, should be:
+ * - LPC_TIM0: TIMER0 peripheral
+ * - LPC_TIM1: TIMER1 peripheral
+ * - LPC_TIM2: TIMER2 peripheral
+ * - LPC_TIM3: TIMER3 peripheral
+ * @param[in] CaptureChannel: capture channel number, should be:
+ * - TIM_COUNTER_INCAP0: CAPn.0 input pin for TIMERn
+ * - TIM_COUNTER_INCAP1: CAPn.1 input pin for TIMERn
+ * @return Value of capture register
+ **********************************************************************/
+uint32_t TIM_GetCaptureValue(LPC_TIM_TypeDef *TIMx, TIM_COUNTER_INPUT_OPT CaptureChannel)
+{
+ CHECK_PARAM(PARAM_TIMx(TIMx));
+ CHECK_PARAM(PARAM_TIM_COUNTER_INPUT_OPT(CaptureChannel));
+
+ if(CaptureChannel==0)
+ return TIMx->CR0;
+ else
+ return TIMx->CR1;
+}
+
+/**
+ * @}
+ */
+
+#endif /* _TIMER */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/src/shared/cmsis/Drivers/source/lpc17xx_uart.c b/src/shared/cmsis/Drivers/source/lpc17xx_uart.c
@@ -0,0 +1,1382 @@
+/**********************************************************************
+* $Id$ lpc17xx_uart.c 2011-06-06
+*//**
+* @file lpc17xx_uart.c
+* @brief Contains all functions support for UART firmware library
+* on LPC17xx
+* @version 3.2
+* @date 25. July. 2011
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2011, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @addtogroup UART
+ * @{
+ */
+
+/* Includes ------------------------------------------------------------------- */
+#include "lpc17xx_uart.h"
+#include "lpc17xx_clkpwr.h"
+
+/* If this source file built with example, the LPC17xx FW library configuration
+ * file in each example directory ("lpc17xx_libcfg.h") must be included,
+ * otherwise the default FW library configuration file must be included instead
+ */
+#ifdef __BUILD_WITH_EXAMPLE__
+#include "lpc17xx_libcfg.h"
+#else
+#include "lpc17xx_libcfg_default.h"
+#endif /* __BUILD_WITH_EXAMPLE__ */
+
+
+#ifdef _UART
+
+/* Private Functions ---------------------------------------------------------- */
+
+static Status uart_set_divisors(LPC_UART_TypeDef *UARTx, uint32_t baudrate);
+
+
+/*********************************************************************//**
+ * @brief Determines best dividers to get a target clock rate
+ * @param[in] UARTx Pointer to selected UART peripheral, should be:
+ * - LPC_UART0: UART0 peripheral
+ * - LPC_UART1: UART1 peripheral
+ * - LPC_UART2: UART2 peripheral
+ * - LPC_UART3: UART3 peripheral
+ * @param[in] baudrate Desired UART baud rate.
+ * @return Error status, could be:
+ * - SUCCESS
+ * - ERROR
+ **********************************************************************/
+static Status uart_set_divisors(LPC_UART_TypeDef *UARTx, uint32_t baudrate)
+{
+ Status errorStatus = ERROR;
+
+ uint32_t uClk = 0;
+ uint32_t d, m, bestd, bestm, tmp;
+ uint64_t best_divisor, divisor;
+ uint32_t current_error, best_error;
+ uint32_t recalcbaud;
+
+ /* get UART block clock */
+ if (UARTx == (LPC_UART_TypeDef *)LPC_UART0)
+ {
+ uClk = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_UART0);
+ }
+ else if (UARTx == (LPC_UART_TypeDef *)LPC_UART1)
+ {
+ uClk = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_UART1);
+ }
+ else if (UARTx == LPC_UART2)
+ {
+ uClk = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_UART2);
+ }
+ else if (UARTx == LPC_UART3)
+ {
+ uClk = CLKPWR_GetPCLK (CLKPWR_PCLKSEL_UART3);
+ }
+
+
+ /* In the Uart IP block, baud rate is calculated using FDR and DLL-DLM registers
+ * The formula is :
+ * BaudRate= uClk * (mulFracDiv/(mulFracDiv+dividerAddFracDiv) / (16 * (DLL)
+ * It involves floating point calculations. That's the reason the formulae are adjusted with
+ * Multiply and divide method.*/
+ /* The value of mulFracDiv and dividerAddFracDiv should comply to the following expressions:
+ * 0 < mulFracDiv <= 15, 0 <= dividerAddFracDiv <= 15 */
+ best_error = 0xFFFFFFFF; /* Worst case */
+ bestd = 0;
+ bestm = 0;
+ best_divisor = 0;
+ for (m = 1 ; m <= 15 ;m++)
+ {
+ for (d = 0 ; d < m ; d++)
+ {
+ divisor = ((uint64_t)uClk<<28)*m/(baudrate*(m+d));
+ current_error = divisor & 0xFFFFFFFF;
+
+ tmp = divisor>>32;
+
+ /* Adjust error */
+ if(current_error > ((uint32_t)1<<31)){
+ current_error = -current_error;
+ tmp++;
+ }
+
+ if(tmp<1 || tmp>65536) /* Out of range */
+ continue;
+
+ if( current_error < best_error){
+ best_error = current_error;
+ best_divisor = tmp;
+ bestd = d;
+ bestm = m;
+ if(best_error == 0) break;
+ }
+ } /* end of inner for loop */
+
+ if (best_error == 0)
+ break;
+ } /* end of outer for loop */
+
+ if(best_divisor == 0) return ERROR; /* can not find best match */
+
+ recalcbaud = (uClk>>4) * bestm/(best_divisor * (bestm + bestd));
+
+ /* reuse best_error to evaluate baud error*/
+ if(baudrate>recalcbaud) best_error = baudrate - recalcbaud;
+ else best_error = recalcbaud -baudrate;
+
+ best_error = best_error * 100 / baudrate;
+
+ if (best_error < UART_ACCEPTED_BAUDRATE_ERROR)
+ {
+ if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+ {
+ ((LPC_UART1_TypeDef *)UARTx)->LCR |= UART_LCR_DLAB_EN;
+ ((LPC_UART1_TypeDef *)UARTx)->/*DLIER.*/DLM = UART_LOAD_DLM(best_divisor);
+ ((LPC_UART1_TypeDef *)UARTx)->/*RBTHDLR.*/DLL = UART_LOAD_DLL(best_divisor);
+ /* Then reset DLAB bit */
+ ((LPC_UART1_TypeDef *)UARTx)->LCR &= (~UART_LCR_DLAB_EN) & UART_LCR_BITMASK;
+ ((LPC_UART1_TypeDef *)UARTx)->FDR = (UART_FDR_MULVAL(bestm) \
+ | UART_FDR_DIVADDVAL(bestd)) & UART_FDR_BITMASK;
+ }
+ else
+ {
+ UARTx->LCR |= UART_LCR_DLAB_EN;
+ UARTx->/*DLIER.*/DLM = UART_LOAD_DLM(best_divisor);
+ UARTx->/*RBTHDLR.*/DLL = UART_LOAD_DLL(best_divisor);
+ /* Then reset DLAB bit */
+ UARTx->LCR &= (~UART_LCR_DLAB_EN) & UART_LCR_BITMASK;
+ UARTx->FDR = (UART_FDR_MULVAL(bestm) \
+ | UART_FDR_DIVADDVAL(bestd)) & UART_FDR_BITMASK;
+ }
+ errorStatus = SUCCESS;
+ }
+
+ return errorStatus;
+}
+
+/* End of Private Functions ---------------------------------------------------- */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @addtogroup UART_Public_Functions
+ * @{
+ */
+/* UART Init/DeInit functions -------------------------------------------------*/
+/********************************************************************//**
+ * @brief Initializes the UARTx peripheral according to the specified
+ * parameters in the UART_ConfigStruct.
+ * @param[in] UARTx UART peripheral selected, should be:
+ * - LPC_UART0: UART0 peripheral
+ * - LPC_UART1: UART1 peripheral
+ * - LPC_UART2: UART2 peripheral
+ * - LPC_UART3: UART3 peripheral
+ * @param[in] UART_ConfigStruct Pointer to a UART_CFG_Type structure
+* that contains the configuration information for the
+* specified UART peripheral.
+ * @return None
+ *********************************************************************/
+void UART_Init(LPC_UART_TypeDef *UARTx, UART_CFG_Type *UART_ConfigStruct)
+{
+ uint32_t tmp;
+
+ // For debug mode
+ CHECK_PARAM(PARAM_UARTx(UARTx));
+ CHECK_PARAM(PARAM_UART_DATABIT(UART_ConfigStruct->Databits));
+ CHECK_PARAM(PARAM_UART_STOPBIT(UART_ConfigStruct->Stopbits));
+ CHECK_PARAM(PARAM_UART_PARITY(UART_ConfigStruct->Parity));
+
+#ifdef _UART0
+ if(UARTx == (LPC_UART_TypeDef *)LPC_UART0)
+ {
+ /* Set up clock and power for UART module */
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART0, ENABLE);
+ }
+#endif
+
+#ifdef _UART1
+ if(((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+ {
+ /* Set up clock and power for UART module */
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART1, ENABLE);
+ }
+#endif
+
+#ifdef _UART2
+ if(UARTx == LPC_UART2)
+ {
+ /* Set up clock and power for UART module */
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART2, ENABLE);
+ }
+#endif
+
+#ifdef _UART3
+ if(UARTx == LPC_UART3)
+ {
+ /* Set up clock and power for UART module */
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART3, ENABLE);
+ }
+#endif
+
+ if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+ {
+ /* FIFOs are empty */
+ ((LPC_UART1_TypeDef *)UARTx)->/*IIFCR.*/FCR = ( UART_FCR_FIFO_EN \
+ | UART_FCR_RX_RS | UART_FCR_TX_RS);
+ // Disable FIFO
+ ((LPC_UART1_TypeDef *)UARTx)->/*IIFCR.*/FCR = 0;
+
+ // Dummy reading
+ while (((LPC_UART1_TypeDef *)UARTx)->LSR & UART_LSR_RDR)
+ {
+ tmp = ((LPC_UART1_TypeDef *)UARTx)->/*RBTHDLR.*/RBR;
+ }
+
+ ((LPC_UART1_TypeDef *)UARTx)->TER = UART_TER_TXEN;
+ // Wait for current transmit complete
+ while (!(((LPC_UART1_TypeDef *)UARTx)->LSR & UART_LSR_THRE));
+ // Disable Tx
+ ((LPC_UART1_TypeDef *)UARTx)->TER = 0;
+
+ // Disable interrupt
+ ((LPC_UART1_TypeDef *)UARTx)->/*DLIER.*/IER = 0;
+ // Set LCR to default state
+ ((LPC_UART1_TypeDef *)UARTx)->LCR = 0;
+ // Set ACR to default state
+ ((LPC_UART1_TypeDef *)UARTx)->ACR = 0;
+ // Set Modem Control to default state
+ ((LPC_UART1_TypeDef *)UARTx)->MCR = 0;
+ // Set RS485 control to default state
+ ((LPC_UART1_TypeDef *)UARTx)->RS485CTRL = 0;
+ // Set RS485 delay timer to default state
+ ((LPC_UART1_TypeDef *)UARTx)->RS485DLY = 0;
+ // Set RS485 addr match to default state
+ ((LPC_UART1_TypeDef *)UARTx)->ADRMATCH = 0;
+ //Dummy Reading to Clear Status
+ tmp = ((LPC_UART1_TypeDef *)UARTx)->MSR;
+ tmp = ((LPC_UART1_TypeDef *)UARTx)->LSR;
+ }
+ else
+ {
+ /* FIFOs are empty */
+ UARTx->/*IIFCR.*/FCR = ( UART_FCR_FIFO_EN | UART_FCR_RX_RS | UART_FCR_TX_RS);
+ // Disable FIFO
+ UARTx->/*IIFCR.*/FCR = 0;
+
+ // Dummy reading
+ while (UARTx->LSR & UART_LSR_RDR)
+ {
+ tmp = UARTx->/*RBTHDLR.*/RBR;
+ }
+
+ UARTx->TER = UART_TER_TXEN;
+ // Wait for current transmit complete
+ while (!(UARTx->LSR & UART_LSR_THRE));
+ // Disable Tx
+ UARTx->TER = 0;
+
+ // Disable interrupt
+ UARTx->/*DLIER.*/IER = 0;
+ // Set LCR to default state
+ UARTx->LCR = 0;
+ // Set ACR to default state
+ UARTx->ACR = 0;
+ // Dummy reading
+ tmp = UARTx->LSR;
+ }
+
+ if (UARTx == LPC_UART3)
+ {
+ // Set IrDA to default state
+ UARTx->ICR = 0;
+ }
+
+ // Set Line Control register ----------------------------
+
+ uart_set_divisors(UARTx, (UART_ConfigStruct->Baud_rate));
+
+ if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+ {
+ tmp = (((LPC_UART1_TypeDef *)UARTx)->LCR & (UART_LCR_DLAB_EN | UART_LCR_BREAK_EN)) \
+ & UART_LCR_BITMASK;
+ }
+ else
+ {
+ tmp = (UARTx->LCR & (UART_LCR_DLAB_EN | UART_LCR_BREAK_EN)) & UART_LCR_BITMASK;
+ }
+
+ switch (UART_ConfigStruct->Databits){
+ case UART_DATABIT_5:
+ tmp |= UART_LCR_WLEN5;
+ break;
+ case UART_DATABIT_6:
+ tmp |= UART_LCR_WLEN6;
+ break;
+ case UART_DATABIT_7:
+ tmp |= UART_LCR_WLEN7;
+ break;
+ case UART_DATABIT_8:
+ default:
+ tmp |= UART_LCR_WLEN8;
+ break;
+ }
+
+ if (UART_ConfigStruct->Parity == UART_PARITY_NONE)
+ {
+ // Do nothing...
+ }
+ else
+ {
+ tmp |= UART_LCR_PARITY_EN;
+ switch (UART_ConfigStruct->Parity)
+ {
+ case UART_PARITY_ODD:
+ tmp |= UART_LCR_PARITY_ODD;
+ break;
+
+ case UART_PARITY_EVEN:
+ tmp |= UART_LCR_PARITY_EVEN;
+ break;
+
+ case UART_PARITY_SP_1:
+ tmp |= UART_LCR_PARITY_F_1;
+ break;
+
+ case UART_PARITY_SP_0:
+ tmp |= UART_LCR_PARITY_F_0;
+ break;
+ default:
+ break;
+ }
+ }
+
+ switch (UART_ConfigStruct->Stopbits){
+ case UART_STOPBIT_2:
+ tmp |= UART_LCR_STOPBIT_SEL;
+ break;
+ case UART_STOPBIT_1:
+ default:
+ // Do no thing
+ break;
+ }
+
+
+ // Write back to LCR, configure FIFO and Disable Tx
+ if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+ {
+ ((LPC_UART1_TypeDef *)UARTx)->LCR = (uint8_t)(tmp & UART_LCR_BITMASK);
+ }
+ else
+ {
+ UARTx->LCR = (uint8_t)(tmp & UART_LCR_BITMASK);
+ }
+}
+
+/*********************************************************************//**
+ * @brief De-initializes the UARTx peripheral registers to their
+ * default reset values.
+ * @param[in] UARTx UART peripheral selected, should be:
+ * - LPC_UART0: UART0 peripheral
+ * - LPC_UART1: UART1 peripheral
+ * - LPC_UART2: UART2 peripheral
+ * - LPC_UART3: UART3 peripheral
+ * @return None
+ **********************************************************************/
+void UART_DeInit(LPC_UART_TypeDef* UARTx)
+{
+ // For debug mode
+ CHECK_PARAM(PARAM_UARTx(UARTx));
+
+ UART_TxCmd(UARTx, DISABLE);
+
+#ifdef _UART0
+ if (UARTx == (LPC_UART_TypeDef *)LPC_UART0)
+ {
+ /* Set up clock and power for UART module */
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART0, DISABLE);
+ }
+#endif
+
+#ifdef _UART1
+ if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+ {
+ /* Set up clock and power for UART module */
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART1, DISABLE);
+ }
+#endif
+
+#ifdef _UART2
+ if (UARTx == LPC_UART2)
+ {
+ /* Set up clock and power for UART module */
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART2, DISABLE);
+ }
+#endif
+
+#ifdef _UART3
+ if (UARTx == LPC_UART3)
+ {
+ /* Set up clock and power for UART module */
+ CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCUART3, DISABLE);
+ }
+#endif
+}
+
+/*****************************************************************************//**
+* @brief Fills each UART_InitStruct member with its default value:
+* - 9600 bps
+* - 8-bit data
+* - 1 Stopbit
+* - None Parity
+* @param[in] UART_InitStruct Pointer to a UART_CFG_Type structure
+* which will be initialized.
+* @return None
+*******************************************************************************/
+void UART_ConfigStructInit(UART_CFG_Type *UART_InitStruct)
+{
+ UART_InitStruct->Baud_rate = 9600;
+ UART_InitStruct->Databits = UART_DATABIT_8;
+ UART_InitStruct->Parity = UART_PARITY_NONE;
+ UART_InitStruct->Stopbits = UART_STOPBIT_1;
+}
+
+/* UART Send/Recieve functions -------------------------------------------------*/
+/*********************************************************************//**
+ * @brief Transmit a single data through UART peripheral
+ * @param[in] UARTx UART peripheral selected, should be:
+ * - LPC_UART0: UART0 peripheral
+ * - LPC_UART1: UART1 peripheral
+ * - LPC_UART2: UART2 peripheral
+ * - LPC_UART3: UART3 peripheral
+ * @param[in] Data Data to transmit (must be 8-bit long)
+ * @return None
+ **********************************************************************/
+void UART_SendByte(LPC_UART_TypeDef* UARTx, uint8_t Data)
+{
+ CHECK_PARAM(PARAM_UARTx(UARTx));
+
+ if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+ {
+ ((LPC_UART1_TypeDef *)UARTx)->/*RBTHDLR.*/THR = Data & UART_THR_MASKBIT;
+ }
+ else
+ {
+ UARTx->/*RBTHDLR.*/THR = Data & UART_THR_MASKBIT;
+ }
+
+}
+
+
+/*********************************************************************//**
+ * @brief Receive a single data from UART peripheral
+ * @param[in] UARTx UART peripheral selected, should be:
+ * - LPC_UART0: UART0 peripheral
+ * - LPC_UART1: UART1 peripheral
+ * - LPC_UART2: UART2 peripheral
+ * - LPC_UART3: UART3 peripheral
+ * @return Data received
+ **********************************************************************/
+uint8_t UART_ReceiveByte(LPC_UART_TypeDef* UARTx)
+{
+ CHECK_PARAM(PARAM_UARTx(UARTx));
+
+ if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+ {
+ return (((LPC_UART1_TypeDef *)UARTx)->/*RBTHDLR.*/RBR & UART_RBR_MASKBIT);
+ }
+ else
+ {
+ return (UARTx->/*RBTHDLR.*/RBR & UART_RBR_MASKBIT);
+ }
+}
+
+/*********************************************************************//**
+ * @brief Send a block of data via UART peripheral
+ * @param[in] UARTx Selected UART peripheral used to send data, should be:
+ * - LPC_UART0: UART0 peripheral
+ * - LPC_UART1: UART1 peripheral
+ * - LPC_UART2: UART2 peripheral
+ * - LPC_UART3: UART3 peripheral
+ * @param[in] txbuf Pointer to Transmit buffer
+ * @param[in] buflen Length of Transmit buffer
+ * @param[in] flag Flag used in UART transfer, should be
+ * NONE_BLOCKING or BLOCKING
+ * @return Number of bytes sent.
+ *
+ * Note: when using UART in BLOCKING mode, a time-out condition is used
+ * via defined symbol UART_BLOCKING_TIMEOUT.
+ **********************************************************************/
+uint32_t UART_Send(LPC_UART_TypeDef *UARTx, uint8_t *txbuf,
+ uint32_t buflen, TRANSFER_BLOCK_Type flag)
+{
+ uint32_t bToSend, bSent, timeOut, fifo_cnt;
+ uint8_t *pChar = txbuf;
+
+ bToSend = buflen;
+
+ // blocking mode
+ if (flag == BLOCKING) {
+ bSent = 0;
+ while (bToSend){
+ timeOut = UART_BLOCKING_TIMEOUT;
+ // Wait for THR empty with timeout
+ while (!(UARTx->LSR & UART_LSR_THRE)) {
+ if (timeOut == 0) break;
+ timeOut--;
+ }
+ // Time out!
+ if(timeOut == 0) break;
+ fifo_cnt = UART_TX_FIFO_SIZE;
+ while (fifo_cnt && bToSend){
+ UART_SendByte(UARTx, (*pChar++));
+ fifo_cnt--;
+ bToSend--;
+ bSent++;
+ }
+ }
+ }
+ // None blocking mode
+ else {
+ bSent = 0;
+ while (bToSend) {
+ if (!(UARTx->LSR & UART_LSR_THRE)){
+ break;
+ }
+ fifo_cnt = UART_TX_FIFO_SIZE;
+ while (fifo_cnt && bToSend) {
+ UART_SendByte(UARTx, (*pChar++));
+ bToSend--;
+ fifo_cnt--;
+ bSent++;
+ }
+ }
+ }
+ return bSent;
+}
+
+/*********************************************************************//**
+ * @brief Receive a block of data via UART peripheral
+ * @param[in] UARTx Selected UART peripheral used to send data,
+ * should be:
+ * - LPC_UART0: UART0 peripheral
+ * - LPC_UART1: UART1 peripheral
+ * - LPC_UART2: UART2 peripheral
+ * - LPC_UART3: UART3 peripheral
+ * @param[out] rxbuf Pointer to Received buffer
+ * @param[in] buflen Length of Received buffer
+ * @param[in] flag Flag mode, should be NONE_BLOCKING or BLOCKING
+
+ * @return Number of bytes received
+ *
+ * Note: when using UART in BLOCKING mode, a time-out condition is used
+ * via defined symbol UART_BLOCKING_TIMEOUT.
+ **********************************************************************/
+uint32_t UART_Receive(LPC_UART_TypeDef *UARTx, uint8_t *rxbuf, \
+ uint32_t buflen, TRANSFER_BLOCK_Type flag)
+{
+ uint32_t bToRecv, bRecv, timeOut;
+ uint8_t *pChar = rxbuf;
+
+ bToRecv = buflen;
+
+ // Blocking mode
+ if (flag == BLOCKING) {
+ bRecv = 0;
+ while (bToRecv){
+ timeOut = UART_BLOCKING_TIMEOUT;
+ while (!(UARTx->LSR & UART_LSR_RDR)){
+ if (timeOut == 0) break;
+ timeOut--;
+ }
+ // Time out!
+ if(timeOut == 0) break;
+ // Get data from the buffer
+ (*pChar++) = UART_ReceiveByte(UARTx);
+ bToRecv--;
+ bRecv++;
+ }
+ }
+ // None blocking mode
+ else {
+ bRecv = 0;
+ while (bToRecv) {
+ if (!(UARTx->LSR & UART_LSR_RDR)) {
+ break;
+ } else {
+ (*pChar++) = UART_ReceiveByte(UARTx);
+ bRecv++;
+ bToRecv--;
+ }
+ }
+ }
+ return bRecv;
+}
+
+/*********************************************************************//**
+ * @brief Force BREAK character on UART line, output pin UARTx TXD is
+ forced to logic 0.
+ * @param[in] UARTx UART peripheral selected, should be:
+ * - LPC_UART0: UART0 peripheral
+ * - LPC_UART1: UART1 peripheral
+ * - LPC_UART2: UART2 peripheral
+ * - LPC_UART3: UART3 peripheral
+ * @return None
+ **********************************************************************/
+void UART_ForceBreak(LPC_UART_TypeDef* UARTx)
+{
+ CHECK_PARAM(PARAM_UARTx(UARTx));
+
+ if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+ {
+ ((LPC_UART1_TypeDef *)UARTx)->LCR |= UART_LCR_BREAK_EN;
+ }
+ else
+ {
+ UARTx->LCR |= UART_LCR_BREAK_EN;
+ }
+}
+
+
+/********************************************************************//**
+ * @brief Enable or disable specified UART interrupt.
+ * @param[in] UARTx UART peripheral selected, should be
+ * - LPC_UART0: UART0 peripheral
+ * - LPC_UART1: UART1 peripheral
+ * - LPC_UART2: UART2 peripheral
+ * - LPC_UART3: UART3 peripheral
+ * @param[in] UARTIntCfg Specifies the interrupt flag,
+ * should be one of the following:
+ - UART_INTCFG_RBR : RBR Interrupt enable
+ - UART_INTCFG_THRE : THR Interrupt enable
+ - UART_INTCFG_RLS : RX line status interrupt enable
+ - UART1_INTCFG_MS : Modem status interrupt enable (UART1 only)
+ - UART1_INTCFG_CTS : CTS1 signal transition interrupt enable (UART1 only)
+ - UART_INTCFG_ABEO : Enables the end of auto-baud interrupt
+ - UART_INTCFG_ABTO : Enables the auto-baud time-out interrupt
+ * @param[in] NewState New state of specified UART interrupt type,
+ * should be:
+ * - ENALBE: Enable this UART interrupt type.
+* - DISALBE: Disable this UART interrupt type.
+ * @return None
+ *********************************************************************/
+void UART_IntConfig(LPC_UART_TypeDef *UARTx, UART_INT_Type UARTIntCfg, FunctionalState NewState)
+{
+ uint32_t tmp = 0;
+
+ CHECK_PARAM(PARAM_UARTx(UARTx));
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
+
+ switch(UARTIntCfg){
+ case UART_INTCFG_RBR:
+ tmp = UART_IER_RBRINT_EN;
+ break;
+ case UART_INTCFG_THRE:
+ tmp = UART_IER_THREINT_EN;
+ break;
+ case UART_INTCFG_RLS:
+ tmp = UART_IER_RLSINT_EN;
+ break;
+ case UART1_INTCFG_MS:
+ tmp = UART1_IER_MSINT_EN;
+ break;
+ case UART1_INTCFG_CTS:
+ tmp = UART1_IER_CTSINT_EN;
+ break;
+ case UART_INTCFG_ABEO:
+ tmp = UART_IER_ABEOINT_EN;
+ break;
+ case UART_INTCFG_ABTO:
+ tmp = UART_IER_ABTOINT_EN;
+ break;
+ }
+
+ if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1)
+ {
+ CHECK_PARAM((PARAM_UART_INTCFG(UARTIntCfg)) || (PARAM_UART1_INTCFG(UARTIntCfg)));
+ }
+ else
+ {
+ CHECK_PARAM(PARAM_UART_INTCFG(UARTIntCfg));
+ }
+
+ if (NewState == ENABLE)
+ {
+ if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1)
+ {
+ ((LPC_UART1_TypeDef *)UARTx)->/*DLIER.*/IER |= tmp;
+ }
+ else
+ {
+ UARTx->/*DLIER.*/IER |= tmp;
+ }
+ }
+ else
+ {
+ if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1)
+ {
+ ((LPC_UART1_TypeDef *)UARTx)->/*DLIER.*/IER &= (~tmp) & UART1_IER_BITMASK;
+ }
+ else
+ {
+ UARTx->/*DLIER.*/IER &= (~tmp) & UART_IER_BITMASK;
+ }
+ }
+}
+
+
+/********************************************************************//**
+ * @brief Get current value of Line Status register in UART peripheral.
+ * @param[in] UARTx UART peripheral selected, should be:
+ * - LPC_UART0: UART0 peripheral
+ * - LPC_UART1: UART1 peripheral
+ * - LPC_UART2: UART2 peripheral
+ * - LPC_UART3: UART3 peripheral
+ * @return Current value of Line Status register in UART peripheral.
+ * Note: The return value of this function must be ANDed with each member in
+ * UART_LS_Type enumeration to determine current flag status
+ * corresponding to each Line status type. Because some flags in
+ * Line Status register will be cleared after reading, the next reading
+ * Line Status register could not be correct. So this function used to
+ * read Line status register in one time only, then the return value
+ * used to check all flags.
+ *********************************************************************/
+uint8_t UART_GetLineStatus(LPC_UART_TypeDef* UARTx)
+{
+ CHECK_PARAM(PARAM_UARTx(UARTx));
+
+ if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+ {
+ return ((((LPC_UART1_TypeDef *)LPC_UART1)->LSR) & UART_LSR_BITMASK);
+ }
+ else
+ {
+ return ((UARTx->LSR) & UART_LSR_BITMASK);
+ }
+}
+
+/********************************************************************//**
+ * @brief Get Interrupt Identification value
+ * @param[in] UARTx UART peripheral selected, should be:
+ * - LPC_UART0: UART0 peripheral
+ * - LPC_UART1: UART1 peripheral
+ * - LPC_UART2: UART2 peripheral
+ * - LPC_UART3: UART3 peripheral
+ * @return Current value of UART UIIR register in UART peripheral.
+ *********************************************************************/
+uint32_t UART_GetIntId(LPC_UART_TypeDef* UARTx)
+{
+ CHECK_PARAM(PARAM_UARTx(UARTx));
+ return (UARTx->IIR & 0x03CF);
+}
+
+/*********************************************************************//**
+ * @brief Check whether if UART is busy or not
+ * @param[in] UARTx UART peripheral selected, should be:
+ * - LPC_UART0: UART0 peripheral
+ * - LPC_UART1: UART1 peripheral
+ * - LPC_UART2: UART2 peripheral
+ * - LPC_UART3: UART3 peripheral
+ * @return RESET if UART is not busy, otherwise return SET.
+ **********************************************************************/
+FlagStatus UART_CheckBusy(LPC_UART_TypeDef *UARTx)
+{
+ if (UARTx->LSR & UART_LSR_TEMT){
+ return RESET;
+ } else {
+ return SET;
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Configure FIFO function on selected UART peripheral
+ * @param[in] UARTx UART peripheral selected, should be:
+ * - LPC_UART0: UART0 peripheral
+ * - LPC_UART1: UART1 peripheral
+ * - LPC_UART2: UART2 peripheral
+ * - LPC_UART3: UART3 peripheral
+ * @param[in] FIFOCfg Pointer to a UART_FIFO_CFG_Type Structure that
+ * contains specified information about FIFO configuration
+ * @return none
+ **********************************************************************/
+void UART_FIFOConfig(LPC_UART_TypeDef *UARTx, UART_FIFO_CFG_Type *FIFOCfg)
+{
+ uint8_t tmp = 0;
+
+ CHECK_PARAM(PARAM_UARTx(UARTx));
+ CHECK_PARAM(PARAM_UART_FIFO_LEVEL(FIFOCfg->FIFO_Level));
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(FIFOCfg->FIFO_DMAMode));
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(FIFOCfg->FIFO_ResetRxBuf));
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(FIFOCfg->FIFO_ResetTxBuf));
+
+ tmp |= UART_FCR_FIFO_EN;
+ switch (FIFOCfg->FIFO_Level){
+ case UART_FIFO_TRGLEV0:
+ tmp |= UART_FCR_TRG_LEV0;
+ break;
+ case UART_FIFO_TRGLEV1:
+ tmp |= UART_FCR_TRG_LEV1;
+ break;
+ case UART_FIFO_TRGLEV2:
+ tmp |= UART_FCR_TRG_LEV2;
+ break;
+ case UART_FIFO_TRGLEV3:
+ default:
+ tmp |= UART_FCR_TRG_LEV3;
+ break;
+ }
+
+ if (FIFOCfg->FIFO_ResetTxBuf == ENABLE)
+ {
+ tmp |= UART_FCR_TX_RS;
+ }
+ if (FIFOCfg->FIFO_ResetRxBuf == ENABLE)
+ {
+ tmp |= UART_FCR_RX_RS;
+ }
+ if (FIFOCfg->FIFO_DMAMode == ENABLE)
+ {
+ tmp |= UART_FCR_DMAMODE_SEL;
+ }
+
+
+ //write to FIFO control register
+ if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+ {
+ ((LPC_UART1_TypeDef *)UARTx)->/*IIFCR.*/FCR = tmp & UART_FCR_BITMASK;
+ }
+ else
+ {
+ UARTx->/*IIFCR.*/FCR = tmp & UART_FCR_BITMASK;
+ }
+}
+
+/*****************************************************************************//**
+* @brief Fills each UART_FIFOInitStruct member with its default value:
+* - FIFO_DMAMode = DISABLE
+* - FIFO_Level = UART_FIFO_TRGLEV0
+* - FIFO_ResetRxBuf = ENABLE
+* - FIFO_ResetTxBuf = ENABLE
+* - FIFO_State = ENABLE
+
+* @param[in] UART_FIFOInitStruct Pointer to a UART_FIFO_CFG_Type structure
+* which will be initialized.
+* @return None
+*******************************************************************************/
+void UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct)
+{
+ UART_FIFOInitStruct->FIFO_DMAMode = DISABLE;
+ UART_FIFOInitStruct->FIFO_Level = UART_FIFO_TRGLEV0;
+ UART_FIFOInitStruct->FIFO_ResetRxBuf = ENABLE;
+ UART_FIFOInitStruct->FIFO_ResetTxBuf = ENABLE;
+}
+
+
+/*********************************************************************//**
+ * @brief Start/Stop Auto Baudrate activity
+ * @param[in] UARTx UART peripheral selected, should be
+ * - LPC_UART0: UART0 peripheral
+ * - LPC_UART1: UART1 peripheral
+ * - LPC_UART2: UART2 peripheral
+ * - LPC_UART3: UART3 peripheral
+ * @param[in] ABConfigStruct A pointer to UART_AB_CFG_Type structure that
+ * contains specified information about UART
+ * auto baudrate configuration
+ * @param[in] NewState New State of Auto baudrate activity, should be:
+ * - ENABLE: Start this activity
+ * - DISABLE: Stop this activity
+ * Note: Auto-baudrate mode enable bit will be cleared once this mode
+ * completed.
+ * @return none
+ **********************************************************************/
+void UART_ABCmd(LPC_UART_TypeDef *UARTx, UART_AB_CFG_Type *ABConfigStruct, \
+ FunctionalState NewState)
+{
+ uint32_t tmp;
+
+ CHECK_PARAM(PARAM_UARTx(UARTx));
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
+
+ tmp = 0;
+ if (NewState == ENABLE) {
+ if (ABConfigStruct->ABMode == UART_AUTOBAUD_MODE1){
+ tmp |= UART_ACR_MODE;
+ }
+ if (ABConfigStruct->AutoRestart == ENABLE){
+ tmp |= UART_ACR_AUTO_RESTART;
+ }
+ }
+
+ if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+ {
+ if (NewState == ENABLE)
+ {
+ // Clear DLL and DLM value
+ ((LPC_UART1_TypeDef *)UARTx)->LCR |= UART_LCR_DLAB_EN;
+ ((LPC_UART1_TypeDef *)UARTx)->DLL = 0;
+ ((LPC_UART1_TypeDef *)UARTx)->DLM = 0;
+ ((LPC_UART1_TypeDef *)UARTx)->LCR &= ~UART_LCR_DLAB_EN;
+ // FDR value must be reset to default value
+ ((LPC_UART1_TypeDef *)UARTx)->FDR = 0x10;
+ ((LPC_UART1_TypeDef *)UARTx)->ACR = UART_ACR_START | tmp;
+ }
+ else
+ {
+ ((LPC_UART1_TypeDef *)UARTx)->ACR = 0;
+ }
+ }
+ else
+ {
+ if (NewState == ENABLE)
+ {
+ // Clear DLL and DLM value
+ UARTx->LCR |= UART_LCR_DLAB_EN;
+ UARTx->DLL = 0;
+ UARTx->DLM = 0;
+ UARTx->LCR &= ~UART_LCR_DLAB_EN;
+ // FDR value must be reset to default value
+ UARTx->FDR = 0x10;
+ UARTx->ACR = UART_ACR_START | tmp;
+ }
+ else
+ {
+ UARTx->ACR = 0;
+ }
+ }
+}
+
+/*********************************************************************//**
+ * @brief Clear Autobaud Interrupt Pending
+ * @param[in] UARTx UART peripheral selected, should be
+ * - LPC_UART0: UART0 peripheral
+ * - LPC_UART1: UART1 peripheral
+ * - LPC_UART2: UART2 peripheral
+ * - LPC_UART3: UART3 peripheral
+ * @param[in] ABIntType type of auto-baud interrupt, should be:
+ * - UART_AUTOBAUD_INTSTAT_ABEO: End of Auto-baud interrupt
+ * - UART_AUTOBAUD_INTSTAT_ABTO: Auto-baud time out interrupt
+ * @return none
+ **********************************************************************/
+void UART_ABClearIntPending(LPC_UART_TypeDef *UARTx, UART_ABEO_Type ABIntType)
+{
+ CHECK_PARAM(PARAM_UARTx(UARTx));
+ if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+ {
+ UARTx->ACR |= ABIntType;
+ }
+ else
+ UARTx->ACR |= ABIntType;
+}
+
+/*********************************************************************//**
+ * @brief Enable/Disable transmission on UART TxD pin
+ * @param[in] UARTx UART peripheral selected, should be:
+ * - LPC_UART0: UART0 peripheral
+ * - LPC_UART1: UART1 peripheral
+ * - LPC_UART2: UART2 peripheral
+ * - LPC_UART3: UART3 peripheral
+ * @param[in] NewState New State of Tx transmission function, should be:
+ * - ENABLE: Enable this function
+ - DISABLE: Disable this function
+ * @return none
+ **********************************************************************/
+void UART_TxCmd(LPC_UART_TypeDef *UARTx, FunctionalState NewState)
+{
+ CHECK_PARAM(PARAM_UARTx(UARTx));
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
+
+ if (NewState == ENABLE)
+ {
+ if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+ {
+ ((LPC_UART1_TypeDef *)UARTx)->TER |= UART_TER_TXEN;
+ }
+ else
+ {
+ UARTx->TER |= UART_TER_TXEN;
+ }
+ }
+ else
+ {
+ if (((LPC_UART1_TypeDef *)UARTx) == LPC_UART1)
+ {
+ ((LPC_UART1_TypeDef *)UARTx)->TER &= (~UART_TER_TXEN) & UART_TER_BITMASK;
+ }
+ else
+ {
+ UARTx->TER &= (~UART_TER_TXEN) & UART_TER_BITMASK;
+ }
+ }
+}
+
+/* UART IrDA functions ---------------------------------------------------*/
+
+#ifdef _UART3
+
+/*********************************************************************//**
+ * @brief Enable or disable inverting serial input function of IrDA
+ * on UART peripheral.
+ * @param[in] UARTx UART peripheral selected, should be LPC_UART3 (only)
+ * @param[in] NewState New state of inverting serial input, should be:
+ * - ENABLE: Enable this function.
+ * - DISABLE: Disable this function.
+ * @return none
+ **********************************************************************/
+void UART_IrDAInvtInputCmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState)
+{
+ CHECK_PARAM(PARAM_UART_IrDA(UARTx));
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
+
+ if (NewState == ENABLE)
+ {
+ UARTx->ICR |= UART_ICR_IRDAINV;
+ }
+ else if (NewState == DISABLE)
+ {
+ UARTx->ICR &= (~UART_ICR_IRDAINV) & UART_ICR_BITMASK;
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Enable or disable IrDA function on UART peripheral.
+ * @param[in] UARTx UART peripheral selected, should be LPC_UART3 (only)
+ * @param[in] NewState New state of IrDA function, should be:
+ * - ENABLE: Enable this function.
+ * - DISABLE: Disable this function.
+ * @return none
+ **********************************************************************/
+void UART_IrDACmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState)
+{
+ CHECK_PARAM(PARAM_UART_IrDA(UARTx));
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
+
+ if (NewState == ENABLE)
+ {
+ UARTx->ICR |= UART_ICR_IRDAEN;
+ }
+ else
+ {
+ UARTx->ICR &= (~UART_ICR_IRDAEN) & UART_ICR_BITMASK;
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Configure Pulse divider for IrDA function on UART peripheral.
+ * @param[in] UARTx UART peripheral selected, should be LPC_UART3 (only)
+ * @param[in] PulseDiv Pulse Divider value from Peripheral clock,
+ * should be one of the following:
+ - UART_IrDA_PULSEDIV2 : Pulse width = 2 * Tpclk
+ - UART_IrDA_PULSEDIV4 : Pulse width = 4 * Tpclk
+ - UART_IrDA_PULSEDIV8 : Pulse width = 8 * Tpclk
+ - UART_IrDA_PULSEDIV16 : Pulse width = 16 * Tpclk
+ - UART_IrDA_PULSEDIV32 : Pulse width = 32 * Tpclk
+ - UART_IrDA_PULSEDIV64 : Pulse width = 64 * Tpclk
+ - UART_IrDA_PULSEDIV128 : Pulse width = 128 * Tpclk
+ - UART_IrDA_PULSEDIV256 : Pulse width = 256 * Tpclk
+
+ * @return none
+ **********************************************************************/
+void UART_IrDAPulseDivConfig(LPC_UART_TypeDef *UARTx, UART_IrDA_PULSE_Type PulseDiv)
+{
+ uint32_t tmp, tmp1;
+ CHECK_PARAM(PARAM_UART_IrDA(UARTx));
+ CHECK_PARAM(PARAM_UART_IrDA_PULSEDIV(PulseDiv));
+
+ tmp1 = UART_ICR_PULSEDIV(PulseDiv);
+ tmp = UARTx->ICR & (~UART_ICR_PULSEDIV(7));
+ tmp |= tmp1 | UART_ICR_FIXPULSE_EN;
+ UARTx->ICR = tmp & UART_ICR_BITMASK;
+}
+
+#endif
+
+
+/* UART1 FullModem function ---------------------------------------------*/
+
+#ifdef _UART1
+
+/*********************************************************************//**
+ * @brief Force pin DTR/RTS corresponding to given state (Full modem mode)
+ * @param[in] UARTx LPC_UART1 (only)
+ * @param[in] Pin Pin that NewState will be applied to, should be:
+ * - UART1_MODEM_PIN_DTR: DTR pin.
+ * - UART1_MODEM_PIN_RTS: RTS pin.
+ * @param[in] NewState New State of DTR/RTS pin, should be:
+ * - INACTIVE: Force the pin to inactive signal.
+ - ACTIVE: Force the pin to active signal.
+ * @return none
+ **********************************************************************/
+void UART_FullModemForcePinState(LPC_UART1_TypeDef *UARTx, UART_MODEM_PIN_Type Pin, \
+ UART1_SignalState NewState)
+{
+ uint8_t tmp = 0;
+
+ CHECK_PARAM(PARAM_UART1_MODEM(UARTx));
+ CHECK_PARAM(PARAM_UART1_MODEM_PIN(Pin));
+ CHECK_PARAM(PARAM_UART1_SIGNALSTATE(NewState));
+
+ switch (Pin){
+ case UART1_MODEM_PIN_DTR:
+ tmp = UART1_MCR_DTR_CTRL;
+ break;
+ case UART1_MODEM_PIN_RTS:
+ tmp = UART1_MCR_RTS_CTRL;
+ break;
+ default:
+ break;
+ }
+
+ if (NewState == ACTIVE){
+ UARTx->MCR |= tmp;
+ } else {
+ UARTx->MCR &= (~tmp) & UART1_MCR_BITMASK;
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Configure Full Modem mode for UART peripheral
+ * @param[in] UARTx LPC_UART1 (only)
+ * @param[in] Mode Full Modem mode, should be:
+ * - UART1_MODEM_MODE_LOOPBACK: Loop back mode.
+ * - UART1_MODEM_MODE_AUTO_RTS: Auto-RTS mode.
+ * - UART1_MODEM_MODE_AUTO_CTS: Auto-CTS mode.
+ * @param[in] NewState New State of this mode, should be:
+ * - ENABLE: Enable this mode.
+ - DISABLE: Disable this mode.
+ * @return none
+ **********************************************************************/
+void UART_FullModemConfigMode(LPC_UART1_TypeDef *UARTx, UART_MODEM_MODE_Type Mode, \
+ FunctionalState NewState)
+{
+ uint8_t tmp = 0;
+
+ CHECK_PARAM(PARAM_UART1_MODEM(UARTx));
+ CHECK_PARAM(PARAM_UART1_MODEM_MODE(Mode));
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState));
+
+ switch(Mode){
+ case UART1_MODEM_MODE_LOOPBACK:
+ tmp = UART1_MCR_LOOPB_EN;
+ break;
+ case UART1_MODEM_MODE_AUTO_RTS:
+ tmp = UART1_MCR_AUTO_RTS_EN;
+ break;
+ case UART1_MODEM_MODE_AUTO_CTS:
+ tmp = UART1_MCR_AUTO_CTS_EN;
+ break;
+ default:
+ break;
+ }
+
+ if (NewState == ENABLE)
+ {
+ UARTx->MCR |= tmp;
+ }
+ else
+ {
+ UARTx->MCR &= (~tmp) & UART1_MCR_BITMASK;
+ }
+}
+
+
+/*********************************************************************//**
+ * @brief Get current status of modem status register
+ * @param[in] UARTx LPC_UART1 (only)
+ * @return Current value of modem status register
+ * Note: The return value of this function must be ANDed with each member
+ * UART_MODEM_STAT_type enumeration to determine current flag status
+ * corresponding to each modem flag status. Because some flags in
+ * modem status register will be cleared after reading, the next reading
+ * modem register could not be correct. So this function used to
+ * read modem status register in one time only, then the return value
+ * used to check all flags.
+ **********************************************************************/
+uint8_t UART_FullModemGetStatus(LPC_UART1_TypeDef *UARTx)
+{
+ CHECK_PARAM(PARAM_UART1_MODEM(UARTx));
+ return ((UARTx->MSR) & UART1_MSR_BITMASK);
+}
+
+
+/* UART RS485 functions --------------------------------------------------------------*/
+
+/*********************************************************************//**
+ * @brief Configure UART peripheral in RS485 mode according to the specified
+* parameters in the RS485ConfigStruct.
+ * @param[in] UARTx LPC_UART1 (only)
+ * @param[in] RS485ConfigStruct Pointer to a UART1_RS485_CTRLCFG_Type structure
+* that contains the configuration information for specified UART
+* in RS485 mode.
+ * @return None
+ **********************************************************************/
+void UART_RS485Config(LPC_UART1_TypeDef *UARTx, UART1_RS485_CTRLCFG_Type *RS485ConfigStruct)
+{
+ uint32_t tmp;
+
+ CHECK_PARAM(PARAM_UART1_MODEM(UARTx));
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(RS485ConfigStruct->AutoAddrDetect_State));
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(RS485ConfigStruct->AutoDirCtrl_State));
+ CHECK_PARAM(PARAM_UART1_RS485_CFG_DELAYVALUE(RS485ConfigStruct->DelayValue));
+ CHECK_PARAM(PARAM_SETSTATE(RS485ConfigStruct->DirCtrlPol_Level));
+ CHECK_PARAM(PARAM_UART_RS485_DIRCTRL_PIN(RS485ConfigStruct->DirCtrlPin));
+ CHECK_PARAM(PARAM_UART1_RS485_CFG_MATCHADDRVALUE(RS485ConfigStruct->MatchAddrValue));
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(RS485ConfigStruct->NormalMultiDropMode_State));
+ CHECK_PARAM(PARAM_FUNCTIONALSTATE(RS485ConfigStruct->Rx_State));
+
+ tmp = 0;
+ // If Auto Direction Control is enabled - This function is used in Master mode
+ if (RS485ConfigStruct->AutoDirCtrl_State == ENABLE)
+ {
+ tmp |= UART1_RS485CTRL_DCTRL_EN;
+
+ // Set polar
+ if (RS485ConfigStruct->DirCtrlPol_Level == SET)
+ {
+ tmp |= UART1_RS485CTRL_OINV_1;
+ }
+
+ // Set pin according to
+ if (RS485ConfigStruct->DirCtrlPin == UART1_RS485_DIRCTRL_DTR)
+ {
+ tmp |= UART1_RS485CTRL_SEL_DTR;
+ }
+
+ // Fill delay time
+ UARTx->RS485DLY = RS485ConfigStruct->DelayValue & UART1_RS485DLY_BITMASK;
+ }
+
+ // MultiDrop mode is enable
+ if (RS485ConfigStruct->NormalMultiDropMode_State == ENABLE)
+ {
+ tmp |= UART1_RS485CTRL_NMM_EN;
+ }
+
+ // Auto Address Detect function
+ if (RS485ConfigStruct->AutoAddrDetect_State == ENABLE)
+ {
+ tmp |= UART1_RS485CTRL_AADEN;
+ // Fill Match Address
+ UARTx->ADRMATCH = RS485ConfigStruct->MatchAddrValue & UART1_RS485ADRMATCH_BITMASK;
+ }
+
+
+ // Receiver is disable
+ if (RS485ConfigStruct->Rx_State == DISABLE)
+ {
+ tmp |= UART1_RS485CTRL_RX_DIS;
+ }
+
+ // write back to RS485 control register
+ UARTx->RS485CTRL = tmp & UART1_RS485CTRL_BITMASK;
+
+ // Enable Parity function and leave parity in stick '0' parity as default
+ UARTx->LCR |= (UART_LCR_PARITY_F_0 | UART_LCR_PARITY_EN);
+}
+
+/*********************************************************************//**
+ * @brief Enable/Disable receiver in RS485 module in UART1
+ * @param[in] UARTx LPC_UART1 (only)
+ * @param[in] NewState New State of command, should be:
+ * - ENABLE: Enable this function.
+ * - DISABLE: Disable this function.
+ * @return None
+ **********************************************************************/
+void UART_RS485ReceiverCmd(LPC_UART1_TypeDef *UARTx, FunctionalState NewState)
+{
+ if (NewState == ENABLE){
+ UARTx->RS485CTRL &= ~UART1_RS485CTRL_RX_DIS;
+ } else {
+ UARTx->RS485CTRL |= UART1_RS485CTRL_RX_DIS;
+ }
+}
+
+/*********************************************************************//**
+ * @brief Send data on RS485 bus with specified parity stick value (9-bit mode).
+ * @param[in] UARTx LPC_UART1 (only)
+ * @param[in] pDatFrm Pointer to data frame.
+ * @param[in] size Size of data.
+ * @param[in] ParityStick Parity Stick value, should be 0 or 1.
+ * @return None
+ **********************************************************************/
+static uint32_t UART_RS485Send(LPC_UART1_TypeDef *UARTx, uint8_t *pDatFrm, \
+ uint32_t size, uint8_t ParityStick)
+{
+ uint8_t tmp, save;
+ uint32_t cnt;
+
+ if (ParityStick){
+ save = tmp = UARTx->LCR & UART_LCR_BITMASK;
+ tmp &= ~(UART_LCR_PARITY_EVEN);
+ UARTx->LCR = tmp;
+ cnt = UART_Send((LPC_UART_TypeDef *)UARTx, pDatFrm, size, BLOCKING);
+ while (!(UARTx->LSR & UART_LSR_TEMT));
+ UARTx->LCR = save;
+ } else {
+ cnt = UART_Send((LPC_UART_TypeDef *)UARTx, pDatFrm, size, BLOCKING);
+ while (!(UARTx->LSR & UART_LSR_TEMT));
+ }
+ return cnt;
+}
+
+/*********************************************************************//**
+ * @brief Send Slave address frames on RS485 bus.
+ * @param[in] UARTx LPC_UART1 (only)
+ * @param[in] SlvAddr Slave Address.
+ * @return None
+ **********************************************************************/
+void UART_RS485SendSlvAddr(LPC_UART1_TypeDef *UARTx, uint8_t SlvAddr)
+{
+ UART_RS485Send(UARTx, &SlvAddr, 1, 1);
+}
+
+/*********************************************************************//**
+ * @brief Send Data frames on RS485 bus.
+ * @param[in] UARTx LPC_UART1 (only)
+ * @param[in] pData Pointer to data to be sent.
+ * @param[in] size Size of data frame to be sent.
+ * @return None
+ **********************************************************************/
+uint32_t UART_RS485SendData(LPC_UART1_TypeDef *UARTx, uint8_t *pData, uint32_t size)
+{
+ return (UART_RS485Send(UARTx, pData, size, 0));
+}
+
+#endif /* _UART1 */
+
+#endif /* _UART */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* --------------------------------- End Of File ------------------------------ */
+
diff --git a/src/shared/cmsis/Drivers/source/lpc17xx_wdt.c b/src/shared/cmsis/Drivers/source/lpc17xx_wdt.c
@@ -0,0 +1,274 @@
+/**********************************************************************
+* $Id$ lpc17xx_wdt.c 2010-05-21
+*//**
+* @file lpc17xx_wdt.c
+* @brief Contains all functions support for WDT firmware library
+* on LPC17xx
+* @version 2.0
+* @date 21. May. 2010
+* @author NXP MCU SW Application Team
+*
+* Copyright(C) 2010, NXP Semiconductor
+* All rights reserved.
+*
+***********************************************************************
+* Software that is described herein is for illustrative purposes only
+* which provides customers with programming information regarding the
+* products. This software is supplied "AS IS" without any warranties.
+* NXP Semiconductors assumes no responsibility or liability for the
+* use of the software, conveys no license or title under any patent,
+* copyright, or mask work right to the product. NXP Semiconductors
+* reserves the right to make changes in the software without
+* notification. NXP Semiconductors also make no representation or
+* warranty that such application will be suitable for the specified
+* use without further testing or modification.
+* Permission to use, copy, modify, and distribute this software and its
+* documentation is hereby granted, under NXP Semiconductors'
+* relevant copyright in the software, without fee, provided that it
+* is used in conjunction with NXP Semiconductors microcontrollers. This
+* copyright, permission, and disclaimer notice must appear in all copies of
+* this code.
+**********************************************************************/
+
+/* Peripheral group ----------------------------------------------------------- */
+/** @addtogroup WDT
+ * @{
+ */
+
+/* Includes ------------------------------------------------------------------- */
+#include "lpc17xx_wdt.h"
+#include "lpc17xx_clkpwr.h"
+#include "lpc17xx_pinsel.h"
+
+
+/* If this source file built with example, the LPC17xx FW library configuration
+ * file in each example directory ("lpc17xx_libcfg.h") must be included,
+ * otherwise the default FW library configuration file must be included instead
+ */
+#ifdef __BUILD_WITH_EXAMPLE__
+#include "lpc17xx_libcfg.h"
+#else
+#include "lpc17xx_libcfg_default.h"
+#endif /* __BUILD_WITH_EXAMPLE__ */
+
+
+#ifdef _WDT
+
+/* Private Functions ---------------------------------------------------------- */
+
+static uint8_t WDT_SetTimeOut (uint8_t clk_source, uint32_t timeout);
+
+/********************************************************************//**
+ * @brief Set WDT time out value and WDT mode
+ * @param[in] clk_source select Clock source for WDT device
+ * @param[in] timeout value of time-out for WDT (us)
+ * @return None
+ *********************************************************************/
+static uint8_t WDT_SetTimeOut (uint8_t clk_source, uint32_t timeout)
+{
+
+ uint32_t pclk_wdt = 0;
+ uint32_t tempval = 0;
+
+ switch ((WDT_CLK_OPT) clk_source)
+ {
+ case WDT_CLKSRC_IRC:
+ pclk_wdt = 4000000;
+ // Calculate TC in WDT
+ tempval = ((((uint64_t)pclk_wdt * (uint64_t)timeout / 4) / (uint64_t)WDT_US_INDEX));
+ // Check if it valid
+ if (tempval >= WDT_TIMEOUT_MIN)
+ {
+ LPC_WDT->WDTC = tempval;
+ return SUCCESS;
+ }
+
+ break;
+
+ case WDT_CLKSRC_PCLK:
+
+ // Get WDT clock with CCLK divider = 4
+ pclk_wdt = SystemCoreClock / 4;
+ // Calculate TC in WDT
+ tempval = ((((uint64_t)pclk_wdt * (uint64_t)timeout / 4) / (uint64_t)WDT_US_INDEX));
+
+ if (tempval >= WDT_TIMEOUT_MIN)
+ {
+ CLKPWR_SetPCLKDiv (CLKPWR_PCLKSEL_WDT, CLKPWR_PCLKSEL_CCLK_DIV_4);
+ LPC_WDT->WDTC = (uint32_t) tempval;
+ return SUCCESS;
+ }
+
+ // Get WDT clock with CCLK divider = 2
+ pclk_wdt = SystemCoreClock / 2;
+ // Calculate TC in WDT
+ tempval = ((((uint64_t)pclk_wdt * (uint64_t)timeout / 4) / (uint64_t)WDT_US_INDEX));
+
+ if (tempval >= WDT_TIMEOUT_MIN)
+ {
+ CLKPWR_SetPCLKDiv (CLKPWR_PCLKSEL_WDT, CLKPWR_PCLKSEL_CCLK_DIV_2);
+ LPC_WDT->WDTC = (uint32_t) tempval;
+ return SUCCESS;
+ }
+
+ // Get WDT clock with CCLK divider = 1
+ pclk_wdt = SystemCoreClock;
+ // Calculate TC in WDT
+ tempval = ((((uint64_t)pclk_wdt * (uint64_t)timeout / 4) / (uint64_t)WDT_US_INDEX));
+
+ if (tempval >= WDT_TIMEOUT_MIN)
+ {
+ CLKPWR_SetPCLKDiv (CLKPWR_PCLKSEL_WDT, CLKPWR_PCLKSEL_CCLK_DIV_1);
+ LPC_WDT->WDTC = (uint32_t) tempval;
+ return SUCCESS;
+ }
+ break ;
+
+
+ case WDT_CLKSRC_RTC:
+ pclk_wdt = 32768;
+ // Calculate TC in WDT
+ tempval = ((((uint64_t)pclk_wdt * (uint64_t)timeout / 4) / (uint64_t)WDT_US_INDEX));
+ // Check if it valid
+ if (tempval >= WDT_TIMEOUT_MIN)
+ {
+ LPC_WDT->WDTC = (uint32_t) tempval;
+ return SUCCESS;
+ }
+
+ break;
+
+// Error parameter
+ default:
+ break;
+}
+
+ return ERROR;
+}
+
+/* End of Private Functions --------------------------------------------------- */
+
+
+/* Public Functions ----------------------------------------------------------- */
+/** @addtogroup WDT_Public_Functions
+ * @{
+ */
+
+
+/*********************************************************************//**
+* @brief Initial for Watchdog function
+* Clock source = RTC ,
+* @param[in] ClkSrc Select clock source, should be:
+* - WDT_CLKSRC_IRC: Clock source from Internal RC oscillator
+* - WDT_CLKSRC_PCLK: Selects the APB peripheral clock (PCLK)
+* - WDT_CLKSRC_RTC: Selects the RTC oscillator
+* @param[in] WDTMode WDT mode, should be:
+* - WDT_MODE_INT_ONLY: Use WDT to generate interrupt only
+* - WDT_MODE_RESET: Use WDT to generate interrupt and reset MCU
+* @return None
+ **********************************************************************/
+void WDT_Init (WDT_CLK_OPT ClkSrc, WDT_MODE_OPT WDTMode)
+{
+ CHECK_PARAM(PARAM_WDT_CLK_OPT(ClkSrc));
+ CHECK_PARAM(PARAM_WDT_MODE_OPT(WDTMode));
+ CLKPWR_SetPCLKDiv (CLKPWR_PCLKSEL_WDT, CLKPWR_PCLKSEL_CCLK_DIV_4);
+
+ //Set clock source
+ LPC_WDT->WDCLKSEL &= ~WDT_WDCLKSEL_MASK;
+ LPC_WDT->WDCLKSEL |= ClkSrc;
+ //Set WDT mode
+ if (WDTMode == WDT_MODE_RESET){
+ LPC_WDT->WDMOD |= WDT_WDMOD(WDTMode);
+ }
+}
+
+/*********************************************************************//**
+* @brief Start WDT activity with given timeout value
+* @param[in] TimeOut WDT reset after timeout if it is not feed
+* @return None
+ **********************************************************************/
+void WDT_Start(uint32_t TimeOut)
+{
+ uint32_t ClkSrc;
+
+ ClkSrc = LPC_WDT->WDCLKSEL;
+ ClkSrc &=WDT_WDCLKSEL_MASK;
+ WDT_SetTimeOut(ClkSrc,TimeOut);
+ //enable watchdog
+ LPC_WDT->WDMOD |= WDT_WDMOD_WDEN;
+ WDT_Feed();
+}
+
+/********************************************************************//**
+ * @brief Read WDT Time out flag
+ * @param[in] None
+ * @return Time out flag status of WDT
+ *********************************************************************/
+FlagStatus WDT_ReadTimeOutFlag (void)
+{
+ return ((FlagStatus)((LPC_WDT->WDMOD & WDT_WDMOD_WDTOF) >>2));
+}
+
+/********************************************************************//**
+ * @brief Clear WDT Time out flag
+ * @param[in] None
+ * @return None
+ *********************************************************************/
+void WDT_ClrTimeOutFlag (void)
+{
+ LPC_WDT->WDMOD &=~WDT_WDMOD_WDTOF;
+}
+
+/********************************************************************//**
+ * @brief Update WDT timeout value and feed
+ * @param[in] TimeOut TimeOut value to be updated
+ * @return None
+ *********************************************************************/
+void WDT_UpdateTimeOut ( uint32_t TimeOut)
+{
+ uint32_t ClkSrc;
+ ClkSrc = LPC_WDT->WDCLKSEL;
+ ClkSrc &=WDT_WDCLKSEL_MASK;
+ WDT_SetTimeOut(ClkSrc,TimeOut);
+ WDT_Feed();
+}
+
+
+/********************************************************************//**
+ * @brief After set WDTEN, call this function to start Watchdog
+ * or reload the Watchdog timer
+ * @param[in] None
+ *
+ * @return None
+ *********************************************************************/
+void WDT_Feed (void)
+{
+ // Disable irq interrupt
+ __disable_irq();
+ LPC_WDT->WDFEED = 0xAA;
+ LPC_WDT->WDFEED = 0x55;
+ // Then enable irq interrupt
+ __enable_irq();
+}
+
+/********************************************************************//**
+ * @brief Get the current value of WDT
+ * @param[in] None
+ * @return current value of WDT
+ *********************************************************************/
+uint32_t WDT_GetCurrentCount(void)
+{
+ return LPC_WDT->WDTV;
+}
+
+/**
+ * @}
+ */
+
+#endif /* _WDT */
+
+/**
+ * @}
+ */
+
+/* --------------------------------- End Of File ------------------------------ */
diff --git a/src/shared/cmsis/Drivers/source/system_LPC17xx.c b/src/shared/cmsis/Drivers/source/system_LPC17xx.c
@@ -0,0 +1,575 @@
+/**************************************************************************//**
+ * @file system_LPC17xx.c
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File
+ * for the NXP LPC17xx Device Series
+ * @version V1.03
+ * @date 07. October 2009
+ *
+ * @note
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#include <stdint.h>
+#include "LPC17xx.h"
+
+/** @addtogroup LPC17xx_System
+ * @{
+ */
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- Clock Configuration ----------------------------------
+//
+// <e> Clock Configuration
+// <h> System Controls and Status Register (SCS)
+// <o1.4> OSCRANGE: Main Oscillator Range Select
+// <0=> 1 MHz to 20 MHz
+// <1=> 15 MHz to 24 MHz
+// <e1.5> OSCEN: Main Oscillator Enable
+// </e>
+// </h>
+//
+// <h> Clock Source Select Register (CLKSRCSEL)
+// <o2.0..1> CLKSRC: PLL Clock Source Selection
+// <0=> Internal RC oscillator
+// <1=> Main oscillator
+// <2=> RTC oscillator
+// </h>
+//
+// <e3> PLL0 Configuration (Main PLL)
+// <h> PLL0 Configuration Register (PLL0CFG)
+// <i> F_cco0 = (2 * M * F_in) / N
+// <i> F_in must be in the range of 32 kHz to 50 MHz
+// <i> F_cco0 must be in the range of 275 MHz to 550 MHz
+// <o4.0..14> MSEL: PLL Multiplier Selection
+// <6-32768><#-1>
+// <i> M Value
+// <o4.16..23> NSEL: PLL Divider Selection
+// <1-256><#-1>
+// <i> N Value
+// </h>
+// </e>
+//
+// <e5> PLL1 Configuration (USB PLL)
+// <h> PLL1 Configuration Register (PLL1CFG)
+// <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P)
+// <i> F_cco1 = F_osc * M * 2 * P
+// <i> F_cco1 must be in the range of 156 MHz to 320 MHz
+// <o6.0..4> MSEL: PLL Multiplier Selection
+// <1-32><#-1>
+// <i> M Value (for USB maximum value is 4)
+// <o6.5..6> PSEL: PLL Divider Selection
+// <0=> 1
+// <1=> 2
+// <2=> 4
+// <3=> 8
+// <i> P Value
+// </h>
+// </e>
+//
+// <h> CPU Clock Configuration Register (CCLKCFG)
+// <o7.0..7> CCLKSEL: Divide Value for CPU Clock from PLL0
+// <3-256><#-1>
+// </h>
+//
+// <h> USB Clock Configuration Register (USBCLKCFG)
+// <o8.0..3> USBSEL: Divide Value for USB Clock from PLL0
+// <0-15>
+// <i> Divide is USBSEL + 1
+// </h>
+//
+// <h> Peripheral Clock Selection Register 0 (PCLKSEL0)
+// <o9.0..1> PCLK_WDT: Peripheral Clock Selection for WDT
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.6..7> PCLK_UART0: Peripheral Clock Selection for UART0
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.8..9> PCLK_UART1: Peripheral Clock Selection for UART1
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.16..17> PCLK_SPI: Peripheral Clock Selection for SPI
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.22..23> PCLK_DAC: Peripheral Clock Selection for DAC
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.24..25> PCLK_ADC: Peripheral Clock Selection for ADC
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o9.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 6
+// <o9.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 6
+// <o9.30..31> PCLK_ACF: Peripheral Clock Selection for ACF
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 6
+// </h>
+//
+// <h> Peripheral Clock Selection Register 1 (PCLKSEL1)
+// <o10.0..1> PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.4..5> PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM
+// <0=> Pclk = Cclk / 4
+// <1=> Pclk = Cclk
+// <2=> Pclk = Cclk / 2
+// <3=> Pclk = Hclk / 8
+// </h>
+//
+// <h> Power Control for Peripherals Register (PCONP)
+// <o11.1> PCTIM0: Timer/Counter 0 power/clock enable
+// <o11.2> PCTIM1: Timer/Counter 1 power/clock enable
+// <o11.3> PCUART0: UART 0 power/clock enable
+// <o11.4> PCUART1: UART 1 power/clock enable
+// <o11.6> PCPWM1: PWM 1 power/clock enable
+// <o11.7> PCI2C0: I2C interface 0 power/clock enable
+// <o11.8> PCSPI: SPI interface power/clock enable
+// <o11.9> PCRTC: RTC power/clock enable
+// <o11.10> PCSSP1: SSP interface 1 power/clock enable
+// <o11.12> PCAD: A/D converter power/clock enable
+// <o11.13> PCCAN1: CAN controller 1 power/clock enable
+// <o11.14> PCCAN2: CAN controller 2 power/clock enable
+// <o11.15> PCGPIO: GPIOs power/clock enable
+// <o11.16> PCRIT: Repetitive interrupt timer power/clock enable
+// <o11.17> PCMC: Motor control PWM power/clock enable
+// <o11.18> PCQEI: Quadrature encoder interface power/clock enable
+// <o11.19> PCI2C1: I2C interface 1 power/clock enable
+// <o11.21> PCSSP0: SSP interface 0 power/clock enable
+// <o11.22> PCTIM2: Timer 2 power/clock enable
+// <o11.23> PCTIM3: Timer 3 power/clock enable
+// <o11.24> PCUART2: UART 2 power/clock enable
+// <o11.25> PCUART3: UART 3 power/clock enable
+// <o11.26> PCI2C2: I2C interface 2 power/clock enable
+// <o11.27> PCI2S: I2S interface power/clock enable
+// <o11.29> PCGPDMA: GP DMA function power/clock enable
+// <o11.30> PCENET: Ethernet block power/clock enable
+// <o11.31> PCUSB: USB interface power/clock enable
+// </h>
+//
+// <h> Clock Output Configuration Register (CLKOUTCFG)
+// <o12.0..3> CLKOUTSEL: Selects clock source for CLKOUT
+// <0=> CPU clock
+// <1=> Main oscillator
+// <2=> Internal RC oscillator
+// <3=> USB clock
+// <4=> RTC oscillator
+// <o12.4..7> CLKOUTDIV: Selects clock divider for CLKOUT
+// <1-16><#-1>
+// <o12.8> CLKOUT_EN: CLKOUT enable control
+// </h>
+//
+// </e>
+*/
+
+
+
+/** @addtogroup LPC17xx_System_Defines LPC17xx System Defines
+ @{
+ */
+
+#define CLOCK_SETUP 1
+#define SCS_Val 0x00000020
+#define CLKSRCSEL_Val 0x00000001
+#define PLL0_SETUP 1
+#define PLL0CFG_Val 0x00050063
+#define PLL1_SETUP 1
+#define PLL1CFG_Val 0x00000023
+#define CCLKCFG_Val 0x00000003
+#define USBCLKCFG_Val 0x00000000
+#define PCLKSEL0_Val 0x00000000
+#define PCLKSEL1_Val 0x00000000
+#define PCONP_Val 0x042887DE
+#define CLKOUTCFG_Val 0x00000000
+
+
+/*--------------------- Flash Accelerator Configuration ----------------------
+//
+// <e> Flash Accelerator Configuration
+// <o1.0..11> Reserved
+// <o1.12..15> FLASHTIM: Flash Access Time
+// <0=> 1 CPU clock (for CPU clock up to 20 MHz)
+// <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
+// <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
+// <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
+// <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
+// <5=> 6 CPU clocks (for any CPU clock)
+// </e>
+*/
+#define FLASH_SETUP 1
+#define FLASHCFG_Val 0x0000303A
+
+/*
+//-------- <<< end of configuration section >>> ------------------------------
+*/
+
+/*----------------------------------------------------------------------------
+ Check the register settings
+ *----------------------------------------------------------------------------*/
+#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
+#define CHECK_RSVD(val, mask) (val & mask)
+
+/* Clock Configuration -------------------------------------------------------*/
+#if (CHECK_RSVD((SCS_Val), ~0x00000030))
+ #error "SCS: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2))
+ #error "CLKSRCSEL: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF))
+ #error "PLL0CFG: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))
+ #error "PLL1CFG: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE(CCLKCFG_Val, 2, 255))
+ #error "CCLKCFG: CCLKSEL field does not contain value in range from 2 to 255!"
+#endif
+
+#if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F))
+ #error "USBCLKCFG: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00))
+ #error "PCLKSEL0: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300))
+ #error "PCLKSEL1: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PCONP_Val), 0x10100821))
+ #error "PCONP: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
+ #error "CLKOUTCFG: Invalid values of reserved bits!"
+#endif
+
+/* Flash Accelerator Configuration -------------------------------------------*/
+#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F))
+ #error "FLASHCFG: Invalid values of reserved bits!"
+#endif
+
+
+/*----------------------------------------------------------------------------
+ DEFINES
+ *----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define XTAL (12000000UL) /* Oscillator frequency */
+#define OSC_CLK ( XTAL) /* Main oscillator frequency */
+#define RTC_CLK ( 32768UL) /* RTC oscillator frequency */
+#define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */
+
+
+/* F_cco0 = (2 * M * F_in) / N */
+#define __M (((PLL0CFG_Val ) & 0x7FFF) + 1)
+#define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1)
+#define __FCCO(__F_IN) ((2 * __M * __F_IN) / __N)
+#define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1)
+
+/* Determine core clock frequency according to settings */
+ #if (PLL0_SETUP)
+ #if ((CLKSRCSEL_Val & 0x03) == 1)
+ #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)
+ #elif ((CLKSRCSEL_Val & 0x03) == 2)
+ #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)
+ #else
+ #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)
+ #endif
+ #else
+ #if ((CLKSRCSEL_Val & 0x03) == 1)
+ #define __CORE_CLK (OSC_CLK / __CCLK_DIV)
+ #elif ((CLKSRCSEL_Val & 0x03) == 2)
+ #define __CORE_CLK (RTC_CLK / __CCLK_DIV)
+ #else
+ #define __CORE_CLK (IRC_OSC / __CCLK_DIV)
+ #endif
+ #endif
+
+ /**
+ * @}
+ */
+
+
+/** @addtogroup LPC17xx_System_Public_Variables LPC17xx System Public Variables
+ @{
+ */
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup LPC17xx_System_Public_Functions LPC17xx System Public Functions
+ @{
+ */
+
+/*----------------------------------------------------------------------------
+ Clock functions
+ *----------------------------------------------------------------------------*/
+
+
+void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
+{
+ /* Determine clock frequency according to clock register values */
+ if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */
+ switch (LPC_SC->CLKSRCSEL & 0x03) {
+ case 0: /* Int. RC oscillator => PLL0 */
+ case 3: /* Reserved, default to Int. RC */
+ SystemCoreClock = (IRC_OSC *
+ ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
+ (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
+ ((LPC_SC->CCLKCFG & 0xFF)+ 1));
+ break;
+ case 1: /* Main oscillator => PLL0 */
+ SystemCoreClock = (OSC_CLK *
+ ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
+ (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
+ ((LPC_SC->CCLKCFG & 0xFF)+ 1));
+ break;
+ case 2: /* RTC oscillator => PLL0 */
+ SystemCoreClock = (RTC_CLK *
+ ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
+ (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
+ ((LPC_SC->CCLKCFG & 0xFF)+ 1));
+ break;
+ }
+ } else {
+ switch (LPC_SC->CLKSRCSEL & 0x03) {
+ case 0: /* Int. RC oscillator => PLL0 */
+ case 3: /* Reserved, default to Int. RC */
+ SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
+ break;
+ case 1: /* Main oscillator => PLL0 */
+ SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
+ break;
+ case 2: /* RTC oscillator => PLL0 */
+ SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
+ break;
+ }
+ }
+
+}
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System.
+ */
+void SystemInit (void)
+{
+ const uint32_t PLL0_CONNECT_FLG = (1<<25) | (1<<24);
+ const uint32_t PLL1_CONNECT_FLG = (1<<8) | (1<<9);
+
+#if (CLOCK_SETUP) /* Clock Setup */
+ LPC_SC->SCS = SCS_Val;
+ if (LPC_SC->SCS & (1 << 5)) { /* If Main Oscillator is enabled */
+ while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */
+ }
+
+ LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */
+ /* Periphral clock must be selected before PLL0 enabling and connecting
+ * - according errata.lpc1768-16.March.2010 -
+ */
+ LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */
+ LPC_SC->PCLKSEL1 = PCLKSEL1_Val;
+
+#if (PLL0_SETUP)
+ LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */
+
+ LPC_SC->PLL0CFG = PLL0CFG_Val; /* configure PLL0 */
+ LPC_SC->PLL0FEED = 0xAA;
+ LPC_SC->PLL0FEED = 0x55;
+
+ LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
+ LPC_SC->PLL0FEED = 0xAA;
+ LPC_SC->PLL0FEED = 0x55;
+ while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0 */
+
+ LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */
+ LPC_SC->PLL0FEED = 0xAA;
+ LPC_SC->PLL0FEED = 0x55;
+ while ((LPC_SC->PLL0STAT & PLL0_CONNECT_FLG) != PLL0_CONNECT_FLG);/* Wait for PLLC0_STAT & PLLE0_STAT */
+#endif
+
+#if (PLL1_SETUP)
+ LPC_SC->PLL1CFG = PLL1CFG_Val;
+ LPC_SC->PLL1FEED = 0xAA;
+ LPC_SC->PLL1FEED = 0x55;
+
+ LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */
+ LPC_SC->PLL1FEED = 0xAA;
+ LPC_SC->PLL1FEED = 0x55;
+ while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */
+
+ LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */
+ LPC_SC->PLL1FEED = 0xAA;
+ LPC_SC->PLL1FEED = 0x55;
+ while ((LPC_SC->PLL1STAT & PLL1_CONNECT_FLG) != PLL1_CONNECT_FLG);/* Wait for PLLC1_STAT & PLLE1_STAT */
+#else
+ LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */
+#endif
+ LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
+
+ LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */
+#endif
+
+#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */
+ LPC_SC->FLASHCFG = FLASHCFG_Val;
+#endif
+
+#define __RAM_MODE__ 0
+// Set Vector table offset value
+#if (__RAM_MODE__==1)
+ SCB->VTOR = 0x10000000 & 0x3FFFFF80;
+#else
+ SCB->VTOR = 0x00000000 & 0x3FFFFF80;
+#endif
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/src/shared/cmsis/Drivers/source/vector.c b/src/shared/cmsis/Drivers/source/vector.c
@@ -0,0 +1,135 @@
+
+/*
+ * Source: libopencm3 library: https://github.com/libopencm3/libopencm3
+ */
+
+#include "vector.h"
+
+void blocking_handler(void);
+void null_handler(void);
+void reset_handler(void);
+int main(void);
+
+void nmi_handler(void) __attribute__((weak, alias("null_handler")));
+void hard_fault_handler(void) __attribute__((weak, alias("blocking_handler")));
+void sv_call_handler(void) __attribute__((weak, alias("null_handler")));
+void pend_sv_handler(void) __attribute__((weak, alias("null_handler")));
+void systick_handler(void) __attribute__((weak, alias("null_handler")));
+void mem_manage_handler(void) __attribute__((weak, alias("blocking_handler")));
+void bus_fault_handler(void) __attribute__((weak, alias("blocking_handler")));
+void usage_fault_handler(void) __attribute__((weak, alias("blocking_handler")));
+void debug_monitor_handler(void) __attribute__((weak, alias("null_handler")));
+
+void wdt_isr(void) __attribute__((weak, alias("blocking_handler")));
+void timer0_isr(void) __attribute__((weak, alias("blocking_handler")));
+void timer1_isr(void) __attribute__((weak, alias("blocking_handler")));
+void timer2_isr(void) __attribute__((weak, alias("blocking_handler")));
+void timer3_isr(void) __attribute__((weak, alias("blocking_handler")));
+void uart0_isr(void) __attribute__((weak, alias("blocking_handler")));
+void uart1_isr(void) __attribute__((weak, alias("blocking_handler")));
+void uart2_isr(void) __attribute__((weak, alias("blocking_handler")));
+void uart3_isr(void) __attribute__((weak, alias("blocking_handler")));
+void pwm_isr(void) __attribute__((weak, alias("blocking_handler")));
+void i2c0_isr(void) __attribute__((weak, alias("blocking_handler")));
+void i2c1_isr(void) __attribute__((weak, alias("blocking_handler")));
+void i2c2_isr(void) __attribute__((weak, alias("blocking_handler")));
+void spi_isr(void) __attribute__((weak, alias("blocking_handler")));
+void ssp0_isr(void) __attribute__((weak, alias("blocking_handler")));
+void ssp1_isr(void) __attribute__((weak, alias("blocking_handler")));
+void pll0_isr(void) __attribute__((weak, alias("blocking_handler")));
+void rtc_isr(void) __attribute__((weak, alias("blocking_handler")));
+void eint0_isr(void) __attribute__((weak, alias("blocking_handler")));
+void eint1_isr(void) __attribute__((weak, alias("blocking_handler")));
+void eint2_isr(void) __attribute__((weak, alias("blocking_handler")));
+void eint3_isr(void) __attribute__((weak, alias("blocking_handler")));
+void adc_isr(void) __attribute__((weak, alias("blocking_handler")));
+void bod_isr(void) __attribute__((weak, alias("blocking_handler")));
+void usb_isr(void) __attribute__((weak, alias("blocking_handler")));
+void can_isr(void) __attribute__((weak, alias("blocking_handler")));
+void gpdma_isr(void) __attribute__((weak, alias("blocking_handler")));
+void i2s_isr(void) __attribute__((weak, alias("blocking_handler")));
+void ethernet_isr(void) __attribute__((weak, alias("blocking_handler")));
+void rit_isr(void) __attribute__((weak, alias("blocking_handler")));
+void motor_pwm_isr(void) __attribute__((weak, alias("blocking_handler")));
+void qei_isr(void) __attribute__((weak, alias("blocking_handler")));
+void pll1_isr(void) __attribute__((weak, alias("blocking_handler")));
+void usb_act_isr(void) __attribute__((weak, alias("blocking_handler")));
+void can_act_isr(void) __attribute__((weak, alias("blocking_handler")));
+
+#define IRQ_HANDLERS \
+ [NVIC_WDT_IRQ] = wdt_isr, \
+ [NVIC_TIMER0_IRQ] = timer0_isr, \
+ [NVIC_TIMER1_IRQ] = timer1_isr, \
+ [NVIC_TIMER2_IRQ] = timer2_isr, \
+ [NVIC_TIMER3_IRQ] = timer3_isr, \
+ [NVIC_UART0_IRQ] = uart0_isr, \
+ [NVIC_UART1_IRQ] = uart1_isr, \
+ [NVIC_UART2_IRQ] = uart2_isr, \
+ [NVIC_UART3_IRQ] = uart3_isr, \
+ [NVIC_PWM_IRQ] = pwm_isr, \
+ [NVIC_I2C0_IRQ] = i2c0_isr, \
+ [NVIC_I2C1_IRQ] = i2c1_isr, \
+ [NVIC_I2C2_IRQ] = i2c2_isr, \
+ [NVIC_SPI_IRQ] = spi_isr, \
+ [NVIC_SSP0_IRQ] = ssp0_isr, \
+ [NVIC_SSP1_IRQ] = ssp1_isr, \
+ [NVIC_PLL0_IRQ] = pll0_isr, \
+ [NVIC_RTC_IRQ] = rtc_isr, \
+ [NVIC_EINT0_IRQ] = eint0_isr, \
+ [NVIC_EINT1_IRQ] = eint1_isr, \
+ [NVIC_EINT2_IRQ] = eint2_isr, \
+ [NVIC_EINT3_IRQ] = eint3_isr, \
+ [NVIC_ADC_IRQ] = adc_isr, \
+ [NVIC_BOD_IRQ] = bod_isr, \
+ [NVIC_USB_IRQ] = usb_isr, \
+ [NVIC_CAN_IRQ] = can_isr, \
+ [NVIC_GPDMA_IRQ] = gpdma_isr, \
+ [NVIC_I2S_IRQ] = i2s_isr, \
+ [NVIC_ETHERNET_IRQ] = ethernet_isr, \
+ [NVIC_RIT_IRQ] = rit_isr, \
+ [NVIC_MOTOR_PWM_IRQ] = motor_pwm_isr, \
+ [NVIC_QEI_IRQ] = qei_isr, \
+ [NVIC_PLL1_IRQ] = pll1_isr, \
+ [NVIC_USB_ACT_IRQ] = usb_act_isr, \
+ [NVIC_CAN_ACT_IRQ] = can_act_isr
+
+__attribute__ ((section(".vectors")))
+vector_table_t vector_table = {
+ .initial_sp_value = &_stack,
+ .reset = reset_handler,
+ .nmi = nmi_handler,
+ .hard_fault = hard_fault_handler,
+ .memory_manage_fault = mem_manage_handler,
+ .bus_fault = bus_fault_handler,
+ .usage_fault = usage_fault_handler,
+ .sv_call = sv_call_handler,
+ .debug_monitor = debug_monitor_handler,
+ .pend_sv = pend_sv_handler,
+ .systick = systick_handler,
+ .irq = { IRQ_HANDLERS },
+};
+
+void reset_handler(void) {
+ unsigned int *src, *dest;
+
+ for (src = &_data_lma, dest = &_data;
+ dest < &_edata;
+ src++, dest++) {
+ *dest = *src;
+ }
+
+ while (dest < &_ebss) {
+ *dest++ = 0;
+ }
+
+ (void)main();
+
+ blocking_handler();
+}
+
+void blocking_handler(void) {
+ while(1) {}
+}
+
+void null_handler(void) { }
+
diff --git a/src/shared/make-shared.mk b/src/shared/make-shared.mk
@@ -0,0 +1,16 @@
+SHARED_DIR = $(SRC_DIR)/shared
+CMSIS_DIR = $(SHARED_DIR)/cmsis
+CMSIS_INC_CORE_DEVICE = $(CMSIS_DIR)/Core/Device/NXP/LPC17xx/Include
+CMSIS_INC_CORE_CMSIS = $(CMSIS_DIR)/Core/CMSIS/Include
+CMSIS_INC_DRIVERS = $(CMSIS_DIR)/Drivers/include
+
+# Modules
+DRIVERS_SRC_C = $(wildcard $(SHARED_DIR)/cmsis/Drivers/source/*.c)
+DRIVERS_SRC_S = $(wildcard $(SHARED_DIR)/cmsis/Drivers/source/*.s)
+
+UTILS_SRC =
+
+SHARED_SRC_C = $(DRIVERS_SRC_C) $(UTILS_SRC)
+SHARED_SRC_S = $(DRIVERS_SRC_S)
+SHARED_INC = -I$(CMSIS_INC_CORE_DEVICE) -I$(CMSIS_INC_DRIVERS) -I$(CMSIS_INC_CORE_CMSIS)
+
